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path: root/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
AgeCommit message (Expand)Author
2025-07-02[AMDGPU] Add a debug option `-amdgpu-snop-padding` for `GCNHazardRecognizer` ...Shilei Tian
2025-06-05[AMDGPU] Support bottom-up postRA scheduing. (#135295)Harrison Hao
2025-05-07[AMDGPU] Classify FLAT instructions as VMEM (#137148)Robert Imschweiler
2025-03-14[AMDGPU][True16][CodeGen] add v_cndmask_t16 to hazardmask (#128912)Brox Chen
2025-02-28[AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. (#129103)sstipano
2025-02-19[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)Fabian Ritter
2025-02-12[TableGen] Emit OpName as an enum class instead of a namespace (#125313)Rahul Joshi
2025-02-12AMDGPU: Handle gfx950 XDL Write-VGPR-VALU-WAW wait state change (#126132)Vigneshwar Jayakumar
2025-02-12AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727)Vigneshwar Jayakumar
2025-02-11AMDGPU: Handle gfx950 XDL-write-VGPR-Overlap-Src-AB wait state (#126732)Vigneshwar Jayakumar
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson
2025-01-21[AMDGPU] Fix crash due to missing check for FLAT instructions that dont use v...Chinmay Deshpande
2025-01-16[AMDGPU][True16][MC][CodeGen] true16 for v_cndmask_b16 (#119736)Brox Chen
2024-12-11[AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (#118589)Pravin Jagtap
2024-12-02AMDGPU: Handle cvt_scale F32/F16->F4/F8 gfx950 hazard (#117844)Matt Arsenault
2024-11-25AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (#117287)Matt Arsenault
2024-11-25AMDGPU: Handle vcmpx+permalane gfx950 hazard (#117286)Matt Arsenault
2024-11-25AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (#117285)Matt Arsenault
2024-11-22AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change...Matt Arsenault
2024-11-22AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx95...Matt Arsenault
2024-11-22AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (#11...Matt Arsenault
2024-11-22AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (#117262)Matt Arsenault
2024-10-02[AMDGPU] Use the SchedModel available in SIInstrInfo (#110859)Juan Manuel Martinez Caamaño
2024-09-04[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)Carl Ritson
2024-08-23[AMDGPU] Refactor code for GETPC bundle updates in hazards (NFCI)Carl Ritson
2024-08-22[AMDGPU] Correctly insert s_nops for dst forwarding hazard (#100276)Jeffrey Byrnes
2024-07-23[AMDGPU] Implement workaround for GFX11.5 export priority (#99273)Carl Ritson
2024-07-16[AMDGPU] Use using instead of typedef. NFC.Jay Foad
2024-05-01[AMDGPU] Remove some pointless fallthrough annotationsJay Foad
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang
2024-03-31[AMDGPU] Extend MFMA padding option to gfx90a+ (#86768)Austin Kerbow
2024-03-07AMDGPU: Refactor mfma hazard handling [NFC] (#84276)Matt Arsenault
2024-03-06AMDGPU: Correct cycle counts for f64 mfma on gfx940 (#83782)Matt Arsenault
2024-02-23[AMDGPU][NFC] Have helpers to deal with encoding fields. (#82772)Ivan Kosarev
2024-01-30AMDGPU: Simplify else if to else in GCNHazardRecognizerMatt Arsenault
2024-01-24[AMDGPU] Add GFX12 WMMA and SWMMAC instructions (#77795)Mirko Brkušanin
2024-01-24AMDGPU: update GFX11 wmma hazards (#76143)Petar Avramovic
2024-01-23[AMDGPU] Handle V_PERMLANE64_B32 in fixVcmpxPermlaneHazards (#79125)Pierre van Houtryve
2024-01-19[AMDGPU] Update hazard recognition for new GFX12 wait counters (#78722)Jay Foad
2024-01-18[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)Jay Foad
2024-01-11[AMDGPU] Support GFX12 VDSDIR instructions WAITVMSRC operand in GCNHazardReco...Jay Foad
2023-12-15[AMDGPU][GFX12] Add new v_permlane16 variants (#75475)Mariusz Sikora
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland
2023-08-24Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"Michael Maitland
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland
2023-07-04[AMDGPU] Fix incorrect hazard mitigationStephen Thomas
2023-07-04[AMDGPU] Add functions for composing and decomposing S_WAIT_DEPCTR operandsStephen Thomas
2023-06-16[MC] Add MCRegisterInfo::regunits for iteration over register unitsSergei Barannikov
2023-05-19[AMDGPU] Fix odd implicit operand handling in clause breakingJay Foad
2023-04-15[Target] Use range-based for loops (NFC)Kazu Hirata
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