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so that subclasses can provide the appropriate MCAsmInfo to print
MCExpr objects.
At present, llvm/utils/TableGen/AsmMatcherEmitter.cpp constucts a
generic MCAsmInfo.
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MCExpr::print has an optional MCAsmInfo argument, which is error-prone
when omitted. MCExpr::print and the convenience helper operator<< are
discouraged to use. Switch to MCAsmInfo::printExpr instead. Use the
target-specific MCAsmInfo if available.
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Note that StringRef::consume_back returns true while consuming the
given prefix if present.
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## Purpose
This patch is one in a series of code-mods that annotate LLVM’s public
interface for export. This patch annotates the `llvm/Target` library.
These annotations currently have no meaningful impact on the LLVM build;
however, they are a prerequisite to support an LLVM Windows DLL (shared
library) build.
## Background
This effort is tracked in #109483. Additional context is provided in
[this
discourse](https://discourse.llvm.org/t/psa-annotating-llvm-public-interface/85307),
and documentation for `LLVM_ABI` and related annotations is found in the
LLVM repo
[here](https://github.com/llvm/llvm-project/blob/main/llvm/docs/InterfaceExportAnnotations.rst).
A sub-set of these changes were generated automatically using the
[Interface Definition Scanner (IDS)](https://github.com/compnerd/ids)
tool, followed formatting with `git clang-format`.
The bulk of this change is manual additions of `LLVM_ABI` to
`LLVMInitializeX` functions defined in .cpp files under llvm/lib/Target.
Adding `LLVM_ABI` to the function implementation is required here
because they do not `#include "llvm/Support/TargetSelect.h"`, which
contains the declarations for this functions and was already updated
with `LLVM_ABI` in a previous patch. I considered patching these files
with `#include "llvm/Support/TargetSelect.h"` instead, but since
TargetSelect.h is a large file with a bunch of preprocessor x-macro
stuff in it I was concerned it would unnecessarily impact compile times.
In addition, a number of unit tests under llvm/unittests/Target required
additional dependencies to make them build correctly against the LLVM
DLL on Windows using MSVC.
## Validation
Local builds and tests to validate cross-platform compatibility. This
included llvm, clang, and lldb on the following configurations:
- Windows with MSVC
- Windows with Clang
- Linux with GCC
- Linux with Clang
- Darwin with Clang
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(#143997)
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Update true16/fake16 profile with v_cvt_pk_bf8/fp8_f32, keeping the
vdst_in profile, and update codegen pattern.
update mc test and codegen test.
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bugfix on parsing FP literals for scale values in the scaled MFMA.
Due to the change in order of operands between MCinst and parsed
operands, the FP literal imms for scale values were not parsed
correctly.
---------
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
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It has been made ineffective by e015626f189dc76f8df9fdc25a47638c6a2f3feb.
This change migrates the users.
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The conditions in parseAssignmentExpression are conservative. We should
also report an error when a non-redefiniable variable (e.g. .equiv
followed by .set; .weakref followed by .set).
Make MCAsmStreamer::emitLabel call setOffset to make the behavior
similar to MCObjectStreamer. `isUndefined()` can now be replaced with
`isUnset()`.
Additionally, fix an AMDGPU API user (tested by a few tests including
MC/AMDGPU/hsa-v4.s)
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MCAsmLexer.h has been made a forwarder header since #134207
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Fix for src scale opsel flags encoding and ASM parsing for gfx950 scaled MFMA.
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All immediates are deferred now.
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Downstream patch by Pravin Jagtap.
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So it matches the documentation
Fixes: SWDEV-526726
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NFC. (#133398)
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This is an extension of #131357. Hopefully this would be the last one.
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Follow-up to 14951a5a3120e50084b3c5fb217e2d47992a24d1
* Unify getVariantKindName and getVariantKindForName
* Allow each target to specify the preferred case (albeit ignored in MCParser)
Note: targets that use variant kinds should call MCExpr::print with a
non-null MAI to print variant kinds. operator<< passes a nullptr to
`MCExpr::print`, which should be avoided (e.g. Hexagon; fixed in
commit cf00ac81ac049cddb80aec1d6d88b8fab4f209e8).
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All VariantKinds except VK_None/VK_Invalid are target-specific (e.g. a
target may not support "@plt" even if it is widely available).
Move the parsers to lib/Target to ensure that VariantKind from unrelated
targets will not be parsed.
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- Change InstrInfoEmitter to emit OpName as an enum class
instead of an anonymous enum in the OpName namespace.
- This will help clearly distinguish between values that are
OpNames vs just operand indices and should help avoid
bugs due to confusion between the two.
- Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES.
- Emit declaration of getOperandIdx() along with the OpName
enum so it doesn't have to be repeated in various headers.
- Also updated AMDGPU, RISCV, and WebAssembly backends
to conform to the new definition of OpName (mostly
mechanical changes).
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The field INST_PREF_SIZE is available since gfx11.
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check if op_sel is consistent with .l/.h syntax if both are presented
reopen this https://github.com/llvm/llvm-project/pull/123250 since
problem is resolved in https://github.com/llvm/llvm-project/pull/125561
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All load transpose instructions follow gfx950 standard of even aligned
VGPR except ds_read_b96_tr_b6, which allows unaligned VGPR.
Co-authored-by: Sirish Pande
[Sirish.Pande@amd.com](mailto:Sirish.Pande@amd.com)
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This reverts commit fabe747bf051697cde72a963f1012d6ba9c3f5f5.
Multiple buildbots are failing. See:
https://github.com/llvm/llvm-project/pull/123250
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check if op_sel is consistent with .l/.h syntax if both are presented
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For GFX10+, currently null cannot be used as dst reg in instructions
that expect the dst reg to be 128b or larger (e.g., s_load_dwordx4).
This patch fixes this problem while ensuring null cannot be used as S#,
T#, or V#.
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Co-authored-by: Jay Foad <jay.foad@amd.com>
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Verify the register widths of the corresponding operands match
the floating point format expected size.
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Co-authored-by: Shilei Tian <shilei.tian@amd.com>
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gfx950 (#117742)
OPSEL[3] determines low/high 16 bits of word to write.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
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These instructions have non-standard use of OPSEL bits to select
dest write byte. The src2_modifiers operand is used without having
its corresponding src2 operand by introducing dummy src2.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
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Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
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Identified with misc-include-cleaner.
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Generated automatically with:
$ clang-tidy -fix -checks=-*,llvm-qualified-auto $(find
lib/Target/AMDGPU/ -type f)
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In addition to the basic mode, the ds_swizzle_b32 is supposed to support
two specific modes: fft and rotate. This patch implements those two
modes.
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Unlike with implicitly preloaded data UserSGPRs firmware is unable to
handle cases where SGPRs for kernel arguments contain preloaded data but
not are not explicitly referenced in the kernel. We need to include
these preloaded SGPRs in the GRANULATED_WAVEFRONT_SGPR_COUNT calculation
to not clobber SGPRs in adjacent waves.
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Don't call raw_string_ostream::flush(), which is essentially a no-op.
As specified in the docs, raw_string_ostream is always unbuffered.
( 65b13610a5226b84889b923bae884ba395ad084d for further reference )
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Update function names to adhere to LLVM coding standard.
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This is a large patch includes the MC level support for V_CVT_F16_F32,
V_CVT_F32_F16 and V_LDEXP_F16 in true16 format.
This patch includes the asm/disasm changes to encode/decode the 16bit
vsrc, vdst and src modifieres for vop and dpp format. This patch is a
dependency for many 16 bit instructions while only three instructions
are updated to make it easier to review.
There will be another patch to support these three instructions in the
codeGen level, this patch just replaces these two instructions with its
fake16 format.
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use MCRegister. (#106015)
Replace unsigned with MCRegister.
Update some ternary operators that started giving errors.
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And declare it to take an MCRegister.
Also rename related entities and remove a comment for the function that
depending on its purpose is either irrelevant or misleading.
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Mention the names of unavailable registers in error messages to not make
the diagnostics for execz/vccz less rich than it was.
Clean up unnecessary name qualifications while there.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
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The work of ParseRegularReg() should remain to be parsing the register
as it was specified, and not to try translate it to anything else.
It's up to operand predicates to decide on what is and is not an
acceptable register for an operand, including considering its expected
register class, and for the rest of the AsmParser infrastructure to
handle it respectively from there on.
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Knowing just their numeric values is not very helpful.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
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When we have a modifier with a value (like dst_sel:DWORD for example) we
only accept symbolic values. SP3 allows to use numberic constants as
well. Adding a helper function to allow both.
Besides the compatibility it is easier to use.
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For GFX10+, the MIMG instrucitons generally require a dim operand.
However, when dim is missing, the assembler produces the error message
"operands are not valid for this GPU or mode" (See issue
https://github.com/llvm/llvm-project/issues/47585). This patch fixes the
issue by producing a more direct error message.
---------
Co-authored-by: Jun Wang <jun.wang7@amd.com>
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