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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
AgeCommit message (Expand)Author
2018-12-07[Targets] Add errors for tiny and kernel codemodel on targets that don't supp...David Green
2018-12-06[AMDGPU] Partial revert of rL348371: Turn on the DPP combiner by defaultValery Pykhtin
2018-12-05[AMDGPU]: Turn on the DPP combiner by defaultValery Pykhtin
2018-11-30[AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)Valery Pykhtin
2018-11-29Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic"David Stuttard
2018-11-29Add support for TFE/LWE in image intrinsicsDavid Stuttard
2018-11-26AMDGPU: Don't optimize exec masks at -O0Matt Arsenault
2018-11-16[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/STRon Lieberman
2018-11-07Allow subclassing ExternalAAMatt Arsenault
2018-10-31AMDGPU: Rewrite SILowerI1Copies to always stay on SALUNicolai Haehnle
2018-10-26[AMDGPU] Add a pass to promote bitcast callsScott Linder
2018-10-08[AMDGPU] Add an AMDGPU specific atomic optimizer.Neil Henning
2018-10-03AMDGPU: Always run AMDGPUAlwaysInlineMatt Arsenault
2018-10-02AMDGPU: Expand atomicrmw nand in IRMatt Arsenault
2018-09-25[AMDGPU] restore r342722 which was reverted with r342743Sameer Sahasrabuddhe
2018-09-21revert changes from r342722Sameer Sahasrabuddhe
2018-09-21[AMDGPU] lower-switch in preISel as a workaround for legacy DASameer Sahasrabuddhe
2018-08-31AMDGPU: Stop forcing internalize at -O0Matt Arsenault
2018-08-31AMDGPU: Remove remnants of old address space mappingMatt Arsenault
2018-07-16run post-RA hazard recognizer pass lateMark Searles
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-07-10Reapply "AMDGPU: Force inlining if LDS global address is used"Matt Arsenault
2018-07-10Revert "AMDGPU: Force inlining if LDS global address is used"Vlad Tsyrklevich
2018-07-09AMDGPU: Force inlining if LDS global address is usedMatt Arsenault
2018-06-29[AMDGPU] Enable LICM in the BE pipelineStanislav Mekhanoshin
2018-06-26AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault
2018-05-31[AMDGPU] Construct memory clauses before RAStanislav Mekhanoshin
2018-05-30AMDGPU: Split AMDGPUTTI into GCNTTI and R600TTITom Stellard
2018-05-29AMDGPU: Fix typo in option descriptionMatt Arsenault
2018-05-25[AMDGPU][Waitcnt] Remove obsolete waitcnt optionMark Searles
2018-05-18AMDGPU: Add pass to optimize reqd_work_group_sizeMatt Arsenault
2018-05-13AMDGPU: Rename OpenCL lowering pass to be R600 specific.Matt Arsenault
2018-05-07[AMDGPU][Waitcnt] Remove the old waitcnt passMark Searles
2018-05-01Remove \brief commands from doxygen comments.Adrian Prantl
2018-04-09AMDGPU: Initialize GlobalISel passesTom Stellard
2018-03-27AMDGPU: Set natural stack alignment in DataLayoutMatt Arsenault
2018-03-23Move TargetLoweringObjectFile from CodeGen to Target to fix layeringDavid Blaikie
2018-02-13[AMDGPU] Change constant addr space to 4Yaxun Liu
2018-02-09Reapply "AMDGPU: Add 32-bit constant address space"Matt Arsenault
2018-02-07Revert "AMDGPU: Add 32-bit constant address space"Rafael Espindola
2018-02-07AMDGPU: Add 32-bit constant address spaceMarek Olsak
2018-02-07[AMDGPU] Suppress redundant waitcnt instrs.Mark Searles
2018-02-02[AMDGPU] Switch to the new addr space mapping by defaultYaxun Liu
2018-01-29[NFC] fix trivial typos in comments and documentsHiroshi Inoue
2018-01-19Split MachineLICM into EarlyMachineLICM and MachineLICM; NFCMatthias Braun
2017-12-22(Re-landing) Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das
2017-12-21Revert "Expose a TargetMachine::getTargetTransformInfo function"Sanjoy Das
2017-12-21Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das
2017-11-20AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experi...Valery Pykhtin
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie
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