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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
AgeCommit message (Expand)Author
2020-02-04AMDGPU: Split denormal mode tracking bitsMatt Arsenault
2020-01-24[AMDGPU] Bundle loads before post-RA schedulerStanislav Mekhanoshin
2020-01-22AMDGPU/GlobalISel: Add pre-legalize combiner passMatt Arsenault
2020-01-22Resubmit: [AMDGPU] Invert the handling of skip insertion.cdevadas
2020-01-21Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle
2020-01-15[AMDGPU] Invert the handling of skip insertion.cdevadas
2020-01-14CMake: Make most target symbols hidden by defaultTom Stellard
2020-01-14[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.Michael Liao
2019-11-13Sink all InitializePasses.h includesReid Kleckner
2019-11-01AMDGPU: Add default denormal mode to MachineFunctionInfoMatt Arsenault
2019-10-10Revert "[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs."Jay Foad
2019-10-10AMDGPU: Use SGPR_128 instead of SReg_128 for vregsMatt Arsenault
2019-08-27AMDGPU: Run AMDGPUCodeGenPrepare after scalar optsMatt Arsenault
2019-08-15[llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere
2019-08-12[AMDGPU] Printf runtime binding passStanislav Mekhanoshin
2019-07-25[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs.Michael Liao
2019-07-16[AMDGPU] Add the adjusted FP as a livein register.Michael Liao
2019-07-10AMDGPU: Serialize mode from MachineFunctionInfoMatt Arsenault
2019-07-05AMDGPU: Make AMDGPUPerfHintAnalysis an SCC passMatt Arsenault
2019-07-03AMDGPU: Add pass to lower SGPR spillsMatt Arsenault
2019-07-03[AMDGPU] Enable serializing of argument info.Michael Liao
2019-07-02[AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent...Alexander Timofeev
2019-06-19Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault
2019-06-17[AMDGPU] Propagate function attributes thru bitcastsStanislav Mekhanoshin
2019-06-17[AMDGPU] gfx1010 wavefrontsize intrinsic foldingStanislav Mekhanoshin
2019-06-17[AMDGPU] Pass to propagate ABI attributes from kernels to the functionsStanislav Mekhanoshin
2019-06-11Revert CMake: Make most target symbols hidden by defaultTom Stellard
2019-06-10CMake: Make most target symbols hidden by defaultTom Stellard
2019-05-14[AMDGPU] Create a TargetInfo header. NFCRichard Trieu
2019-05-01[AMDGPU] gfx1010 GCNRegBankReassign passStanislav Mekhanoshin
2019-05-01[AMDGPU] gfx1010 GCNNSAReassign passStanislav Mekhanoshin
2019-04-15[GlobalISel] Introduce a CSEConfigBase class to allow targets to define their...Amara Emerson
2019-04-07Reapply [ValueTracking] Support min/max selects in computeConstantRange()Nikita Popov
2019-04-05[AMDGPU] Add MachineDCE pass after RenameIndependentSubregsStanislav Mekhanoshin
2019-04-01[AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning
2019-03-27AMDGPU: Add additional MIR tests for exec mask optimizationsMatt Arsenault
2019-03-19CodeGen: Refactor regallocator command line and target selectionMatt Arsenault
2019-03-18[AMDGPU] Add an experimental buffer fat pointer address space.Neil Henning
2019-03-17AMDGPU: Partially fix default device for HSAMatt Arsenault
2019-03-14MIR: Allow targets to serialize MachineFunctionInfoMatt Arsenault
2019-03-07AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV)Aakanksha Patil
2019-02-28AMDGPU: Fix typoMatt Arsenault
2019-02-28AMDGPU: Enable function calls by defaultMatt Arsenault
2019-02-21AMDGPU: Remove debugger related subtarget featuresMatt Arsenault
2019-02-11[AMDGPU] Enable DPP combiner pass by default.Valery Pykhtin
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
2019-01-14[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd tryDavid Stuttard
2018-12-13Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil
2018-12-12[AMDGPU] Support for "uniform-work-group-size" attributeAakanksha Patil
2018-12-10[AMDGPU] Add new Mode Register passTim Corringham
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