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path: root/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
AgeCommit message (Expand)Author
2025-06-18AMDGPU: Directly select minimumnum/maximumnum with ieee_mode=0 (#141903)Matt Arsenault
2025-06-08[llvm] Compare std::optional<T> to values directly (NFC) (#143340)Kazu Hirata
2025-06-06AMDGPU: Custom lower fptrunc vectors for f32 -> f16 (#141883)Changpeng Fang
2025-05-28Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)Justin Bogner
2025-05-23[AMDGPU] Correct bitshift legality transformation for small vectors (#140940)zGoldthorpe
2025-05-21AMDGPU/GlobalISel: Start legalizing minimumnum and maximumnum (#140900)Matt Arsenault
2025-05-08[GlobalISel][AMDGPU] Fix handling of v2i128 type for AND, OR, XOR (#138574)Chinmay Deshpande
2025-05-07[AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (#131308)Pierre van Houtryve
2025-05-05[AMDGPU] Support arbitrary types in amdgcn.dead (#134841)Diana Picus
2025-04-17AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (#135659)Changpeng Fang
2025-04-16Reapply "[AMDGPU][GlobalISel] Properly handle lane op lowering for larger vec...Vikram Hegde
2025-04-14Revert "[AMDGPU][GlobalISel] Properly handle lane op lowering for larger vect...Kazu Hirata
2025-04-15[AMDGPU][GlobalISel] Properly handle lane op lowering for larger vector types...Vikram Hegde
2025-03-29[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)Tim Gymnich
2025-03-19[AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (#130041)Mariusz Sikora
2025-03-19[AMDGPU] Add intrinsic and MI for image_bvh_dual_intersect_ray (#130038)Mariusz Sikora
2025-03-18[NFC][AMDGPU][GlobalISel] Make LLTs constexpr (#131673)Tim Gymnich
2025-03-17[AMDGPU][GlobalISel] Enable vector reductions (#131413)Tim Gymnich
2025-03-06[AMDGPU][NFC] Update name for BVH Intersect Ray (#130036)Mariusz Sikora
2025-03-04[AMDGPU] Don't store an immediate in a Register. NFCCraig Topper
2025-02-25[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)Brox Chen
2025-02-25AMDGPU: Drop legacy r600.read.global.size intrinsics from amdgcn (#128700)Matt Arsenault
2025-02-20Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fm...Matt Arsenault
2025-02-19AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(m...Changpeng Fang
2025-02-17AMDGPU: Stop emitting an error on illegal addrspacecasts (#127487)Matt Arsenault
2025-02-11[AMDGPU][NFC] Remove an unneeded return value. (#126739)Ivan Kosarev
2025-01-18[CodeGen] Use Register/MCRegister::isPhysical. NFCCraig Topper
2024-12-12[GlobalISel][NFC] Fix LLT Propagation (#119587)Tim Gymnich
2024-12-08Revert "[amdgpu][lds] Simplify error diag path - lds variable names are no lo...Jon Chesterfield
2024-12-08[amdgpu][lds] Simplify error diag path - lds variable names are no longer spe...Jon Chesterfield
2024-12-02AMDGPU: Add support for V_CVT_PK_F16_F32 instruction for gfx950 (#118300)Matt Arsenault
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata
2024-11-06[AMDGPU] modify named barrier builtins and intrinsics (#114550)Gang Chen
2024-11-05[AMDGPU] Extend type support for update_dpp intrinsic (#114597)Stanislav Mekhanoshin
2024-11-01Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN ...Krzysztof Drewniak
2024-10-31[AMDGPU] Extend mov_dpp8 intrinsic lowering for generic types (#114296)Stanislav Mekhanoshin
2024-10-10Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buff...Mikhail Goncharov
2024-10-09Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN ...Krzysztof Drewniak
2024-10-08[AMDGPU] Adopt new lowering sequence for `fdiv16` (#109295)Shilei Tian
2024-10-06Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buff...NAKAMURA Takumi
2024-10-04Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN ...Krzysztof Drewniak
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad
2024-10-03Revert "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (...NAKAMURA Takumi
2024-10-02[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)Krzysztof Drewniak
2024-09-25Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLI...sstipano
2024-09-25Revert "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLI...NAKAMURA Takumi
2024-09-24[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF ...sstipano
2024-09-11[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)Jay Foad
2024-09-06[AMDGPU] Add target intrinsic for s_buffer_prefetch_data (#107293)Stanislav Mekhanoshin
2024-08-29AMDGPU: Use pattern to select instruction for intrinsic llvm.fptrunc.round (#...Changpeng Fang
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