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path: root/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
AgeCommit message (Expand)Author
2025-06-26[AMDGPU] Convert 64-bit sra to 32-bit if shift amt >= 32 (#144421)LU-JOHN
2025-06-23AMDGPU: Use reportFatalUsageError for unhandled calling conventions (#145261)Matt Arsenault
2025-06-20AMDGPU: Remove AMDGPUInstrInfo class (#144984)Matt Arsenault
2025-06-13[AMDGPU] Convert more 64-bit lshr to 32-bit if shift amt>=32 (#138204)LU-JOHN
2025-05-30[AMDGPU] Extend SRA i64 simplification for shift amts in range [33:62] (#138913)LU-JOHN
2025-05-28Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)Justin Bogner
2025-05-16[AMDGPU] Handle min/max in isNarrowingProfitable (#140206)Pierre van Houtryve
2025-05-09AMDGPU: Use poison instead of undef in more lowerings (#139208)Matt Arsenault
2025-05-09AMDGPU: Handle minimumnum/maximumnum in fneg combines (#139133)Matt Arsenault
2025-05-08AMDGPU][True16][CodeGen] FP_Round f64 to f16 in true16 (#128911)Brox Chen
2025-05-05AMDGPU: Fix gcc -Wenum-compare warning (#138529)Matt Arsenault
2025-04-23[DAG] shouldReduceLoadWidth - add optional<unsigned> byte offset argument (#1...Simon Pilgrim
2025-04-18[DAG] isKnownNeverNaN - add DemandedElts element mask to isKnownNeverNaN call...Simon Pilgrim
2025-04-02[Clang][AMDGPU] Add __builtin_amdgcn_cvt_off_f32_i4 (#133741)Juan Manuel Martinez Caamaño
2025-03-29[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)Tim Gymnich
2025-03-28AMDGPU: Convert vector 64-bit shl to 32-bit if shift amt >= 32 (#132964)LU-JOHN
2025-03-20[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)Diana Picus
2025-03-18[CodeGen][GlobalISel] Add a getVectorIdxWidth and getVectorIdxLLT. (#131526)David Green
2025-03-03[AMDGPU] Simplify conditional expressions. NFC. (#129228)Jay Foad
2025-02-13AMDGPU: Reduce shl64 to shl32 if shift range is [63-32] (#125574)LU-JOHN
2025-02-04AMDGPU: Generalize truncate of shift of cast build_vector combine (#125617)Matt Arsenault
2024-12-21[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119...Sergei Barannikov
2024-12-18[SelectionDAG] Add SDNode::user_begin() and use it in some places (#120509)Craig Topper
2024-12-18[SelectionDAG] Rename SDNode::uses() to users(). (#120499)Craig Topper
2024-12-10[DAGCombine] Remove oneuse restrictions for RISCV in folding (shl (add_nsw x,...LiqinWeng
2024-12-08Revert "[amdgpu][lds] Simplify error diag path - lds variable names are no lo...Jon Chesterfield
2024-12-08[amdgpu][lds] Simplify error diag path - lds variable names are no longer spe...Jon Chesterfield
2024-11-25[AMDGPU] Use getSignedConstant() where necessary (#117328)Nikita Popov
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata
2024-11-11[AMDGPU] Remove unused AMDGPUISD enum members (NFC) (#115582)Sergei Barannikov
2024-11-06[AMDGPU] modify named barrier builtins and intrinsics (#114550)Gang Chen
2024-10-29DAG: Fix legalization of vector addrspacecasts (#113964)Matt Arsenault
2024-10-09[TTI] NFC: Port TLI.shouldSinkOperands to TTI (#110564)Jeffrey Byrnes
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad
2024-09-26[AMDGPU] Implement isSDNodeAlwaysUniform for INTRINSIC_W_CHAIN (#110114)Jay Foad
2024-09-19[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)Pierre van Houtryve
2024-09-06[AMDGPU] Add target intrinsic for s_buffer_prefetch_data (#107293)Stanislav Mekhanoshin
2024-08-29AMDGPU: Use pattern to select instruction for intrinsic llvm.fptrunc.round (#...Changpeng Fang
2024-08-29DAG: Check if is_fpclass is custom, instead of isLegalOrCustom (#105577)Matt Arsenault
2024-08-27[AMDGPU] Fix sign confusion in performMulLoHiCombine (#105831)Jay Foad
2024-08-17AMDGPU: Add tonearest and towardzero roundings for intrinsic llvm.fptrunc.rou...Changpeng Fang
2024-08-13[SelectionDAG] Replace EVTToAPFloatSemantics with MVT/EVT::getFltSemantics. (...Craig Topper
2024-08-09[llvm] Construct SmallVector<SDValue> with ArrayRef (NFC) (#102578)Kazu Hirata
2024-08-08AMDGPU: Directly handle all atomicrmw cases in SIISelLowering (#102439)Matt Arsenault
2024-08-01AMDGPU: Cleanup extract_subvector actions (NFC) (#101454)Matt Arsenault
2024-07-25AMDGPU: Fix asserting in DAG kernel argument lowering on v6i32 (#100528)Matt Arsenault
2024-07-24[AMDGPU] Implement llvm.lrint intrinsic lowering (#98931)Sumanth Gundapaneni
2024-07-23[AMDGPU] Implement llvm.lround intrinsic lowering. (#98970)Sumanth Gundapaneni
2024-07-17[AMDGPU] Use range-based for loops. NFC. (#99047)Jay Foad
2024-07-16[AMDGPU] Use std::min with initializer list. NFC.Jay Foad
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