summaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AArch64
AgeCommit message (Expand)Author
2025-09-10[AArch64] Use SignExtend64<N> (NFC) (#157788)Kazu Hirata
2025-09-10[GISel] Combine shift + trunc + shift pattern (#155583)jyli0116
2025-09-10[AArch64] Break up `AArch64FrameLowering::emitPrologue` (NFCI) (#157485)Benjamin Maxwell
2025-09-10[TableGen][CodeGen] Remove feature string from HwMode (#157600)Sergei Barannikov
2025-09-10[AArch64] Lower zero cycle FPR zeroing (#156261)Tomer Shafir
2025-09-09[AArch64][SVE] Add PTEST_FIRST pseudo instruction (#157489)Kerry McLaughlin
2025-09-09[AArch64] Enable RT and partial unrolling with reductions for Apple CPUs. (#1...Florian Hahn
2025-09-09[AArch64][SME] Support agnostic ZA functions in the MachineSMEABIPass (#149064)Benjamin Maxwell
2025-09-09[LoopVectorizer][AArch64] Add a -sve-vscale-for-tuning override option. (#156...David Green
2025-09-09[AArch64] Use unsigned variant of `<s|u>addv_64` SVE vector reduction intrins...Rajveer Singh Bharadwaj
2025-09-08[AArch64] Transform add(x, abs(y)) -> saba(x, y, 0) (#156615)Hari Limaye
2025-09-08[AArch64] Removed redundant FMOV instruction for truncstores of f64/f32 via b...Amina Chabane
2025-09-08[AArch64] Improve lowering for scalable masked interleaving stores (#156718)David Sherwood
2025-09-08[AArch64][SME] Support Windows/stack probes in MachineSMEABIPass (#149063)Benjamin Maxwell
2025-09-08MC: Add Triple overloads for more MC constructors (#157321)Matt Arsenault
2025-09-08CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)Matt Arsenault
2025-09-07[AArch64] Use DAG.getNegative instead of getNegatedInteger (NFC) (#157342)AZero13
2025-09-07[AArch64][GlobalISel] Add regbank information to other sha1 intrinsics.David Green
2025-09-07[AArch64][GlobalISel] Move special selection for aarch64_crypto_sha1h.David Green
2025-09-07[AArch64] Fix vectorToScalarBitmask BE (#156314)Giuseppe Cesarano
2025-09-06[AArch64][GlobalISel] Ensure vector types match in shift instructionsDavid Green
2025-09-06[AArch64] Don't run loop-idiom-vectorize pass in the O0 pipeline (#156802)Fangrui Song
2025-09-05[AArch64] NFC: Rename LastPopI in emitEpilogue (#156884)Sander de Smalen
2025-09-05[AArch64] Provide a custom decoder for LDR_ZA/STR_ZA (#156363)Sergei Barannikov
2025-09-05[AArch64] Correctly disassemble TSB instruction (#156362)Sergei Barannikov
2025-09-05[AArch64][SME] Use `mrs %reg, SVCR` rather than ABI routine with `+sme` (#156...Benjamin Maxwell
2025-09-05[AArch64] canCreateUndefOrPoisonForTargetNode - AArch64ISD::VASHR\VLSHR\VSHL ...Simon Pilgrim
2025-09-04[AArch64] Give a higher cost for more expensive SVE FCMP instructions (#153816)David Green
2025-09-04[LV][AArch64] Prefer epilogue with fixed-width over scalable VF. (#155546)Hassnaa Hamdi
2025-09-04[TableGen][Decoder] Decode operands with zero width or all bits known (#156358)Sergei Barannikov
2025-09-04[AArch64][SME] Resume streaming-mode on entry to exception handlers (#156638)Benjamin Maxwell
2025-09-04[AArch64] canCreateUndefOrPoisonForTargetNode - AArch64ISD::MOVI opcodes can'...Simon Pilgrim
2025-09-03[NFC][LLVM] Use `INITILIZE_PASS` instead of `INITIALIZE_PASS_BEGIN/END` (#156...Rahul Joshi
2025-09-03[llvm-exegesis] [AArch64] Reland Resolving "not all operands are initialized ...Lakshay Kumar
2025-09-03[AArch64] Combine SEXT_INREG(CSET) to CSETM. (#156429)Ricardo Jesus
2025-09-03[AArch64] Update cost model for extracting halves from 128+ bit vectors (#155...Gaëtan Bossu
2025-09-03[AArch64] Improve lowering for scalable masked deinterleaving loads (#154338)David Sherwood
2025-09-03[AArch64] Guard fptosi+sitofp patterns with one use checks. (#156407)David Green
2025-09-02Reland "[AArch64] AArch64TargetLowering::computeKnownBitsForTargetNode - add ...Yatao Wang
2025-09-02[Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (#...Sam Tebbs
2025-09-02Revert "[llvm-exegesis] [AArch64] Resolving "not all operands are initialized...Muhammad Omair Javaid
2025-09-01[LV] Bundle sub reductions into VPExpressionRecipe (#147255)Sam Tebbs
2025-09-01[llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snip...Lakshay Kumar
2025-08-31[AArch64] Add patterns for sub from add negative immediates (#156024)David Green
2025-08-31[AArch64][SDAG] Add f16 -> i16 rounding NEON conversion intrinsics (#155851)Kajetan Puchalski
2025-08-30[AArch64] Remove an unnecessary cast (NFC) (#156139)Kazu Hirata
2025-08-30[TableGen] Require complex operands in InstAlias to be specified as DAGs (#13...Sergei Barannikov
2025-08-30[AArch64][BTI] Add BTI at EH entries. (#155308)Shashi Shankar
2025-08-29[AArch64][GlobalISel] Select *v1f16 for f16->s16 to_int_sat_gi (#154562)Kajetan Puchalski
2025-08-28[AArch64] Add a FeatureFuseCmpCSet (#153189)David Green
generated by cgit v1.2.3 (git 2.25.1) at 2026-10-22 01:56:38 +0000