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path: root/llvm/lib/CodeGen/TargetLoweringBase.cpp
AgeCommit message (Expand)Author
2022-11-22[X86] Allow no X87 on 32-bitPhoebe Wang
2022-11-17[AMDGPU] Allow finer grain control of an unaligned access speedStanislav Mekhanoshin
2022-09-16[VP][VE] Default VP_SREM/UREM to Expand and add generic expansion using VP_SD...Craig Topper
2022-09-12Move TargetTransformInfo::maxLegalDivRemBitWidth -> TargetLowering::maxSuppor...Matthias Gehre
2022-09-08[llvm] Use std::size instead of llvm::array_lengthofJoe Loser
2022-09-06[SelectionDAG] Rewrite bfloat16 softening to use the "half promotion" pathBenjamin Kramer
2022-08-18[NFCI] Move cost estimation from TargetLowering to TargetTransformInfo.Daniil Fukalov
2022-08-08[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFCFangrui Song
2022-07-27Use hasNItemsOrLess() in MRI::hasAtMostUserInstrs().Amara Emerson
2022-07-27[AArch64][GlobalISel] Add heuristics for localizing G_CONSTANT.Amara Emerson
2022-07-17[CodeGen] Qualify auto variables in for loops (NFC)Kazu Hirata
2022-06-15[PS5] Support sin+cos->sincos optimizationPaul Robinson
2022-06-15Add a conversion from double to bf16Benjamin Kramer
2022-06-15Promote bf16 to f32 when the target doesn't support itBenjamin Kramer
2022-06-02[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.Hendrik Greving
2022-06-01Revert "[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4."Hendrik Greving
2022-06-01[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.Hendrik Greving
2022-05-10Avoid 8 and 16bit switch conditions on x86Matthias Braun
2022-04-26Intrinsic for checking floating point classSerge Pavlov
2022-04-13[NFC][CodeGen] Use ArrayRef in TargetLowering functionsShao-Ce SUN
2022-03-16Cleanup codegen includesserge-sans-paille
2022-03-10Revert "Cleanup codegen includes"Nico Weber
2022-03-10Cleanup codegen includesserge-sans-paille
2022-03-03[PS4] isPS4 and isPS4CPU are not meaningfully differentPaul Robinson
2022-02-18[SelectionDAG][X86] Support f16 in getReciprocalOpName.Craig Topper
2022-02-18Revert "[SelectionDAG][X86] Support f16 in getReciprocalOpName."Craig Topper
2022-02-18[SelectionDAG][X86] Support f16 in getReciprocalOpName.Craig Topper
2022-02-11[ISel] Port AArch64 HADD and RHADD to ISelDavid Green
2022-01-26Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C...Benjamin Kramer
2022-01-26Rename llvm::array_lengthof into llvm::size to match std::size from C++17serge-sans-paille
2022-01-05[CodeGen] Initialize MaxBytesForAlignment in TargetLoweringBase::TargetLoweri...David Green
2022-01-05[CodeGen] Emit alignment "Max Skip" operandNicholas Guy
2021-12-17[llvm] Use none_of instead of \!any_of (NFC)Kazu Hirata
2021-11-17[Analysis] Ensure getTypeLegalizationCost returns a simple VT for TypeScalari...David Sherwood
2021-11-05[FreeBSD] Do not mark __stack_chk_guard as dso_localAlfredo Dal'Ava Junior
2021-10-25[LegalizeTypes][TargetLowering] Merge getShiftAmountTyForConstant into Target...Craig Topper
2021-10-09Fixed some errors detected by PVS StudioDávid Bolvanský
2021-10-08Make more places that use alignment use uint64_tArthur Eubanks
2021-09-23[NFC] Remove redundant setOperationAction.Freddy Ye
2021-09-02Revert @llvm.isnan intrinsic patchset.Roman Lebedev
2021-08-18[X86] AVX512FP16 instructions enabling 3/6Wang, Pengfei
2021-08-13GlobalISel: Add helper function for getting EVT from LLTMatt Arsenault
2021-08-13[NFC] Clean up users of AttributeList::hasAttribute()Arthur Eubanks
2021-08-06Introduce intrinsic llvm.isnanSerge Pavlov
2021-08-04[CodeGen] Add -align-loopsFangrui Song
2021-08-04Revert "Introduce intrinsic llvm.isnan"Serge Pavlov
2021-08-04Introduce intrinsic llvm.isnanSerge Pavlov
2021-08-02[AArch64][SelectionDAG] Support passing/returning scalable vectors with unusu...Eli Friedman
2021-07-22[WebAssembly] Implementation of global.get/set for reftypes in LLVM IRPaulo Matos
2021-07-02Revert "[WebAssembly] Implementation of global.get/set for reftypes in LLVM IR"Roman Lebedev
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