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path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
AgeCommit message (Expand)Author
2024-08-07[TargetLowering] Fix the problem of emulated-TLS implementation witho… (#10...cceerczw
2024-08-07Revert b1234ddbe2652aa7948242a57107ca7ab12fd2f8. "[DAG] Add legalization hand...Simon Pilgrim
2024-08-06[DAG] Add legalization handling for ABDS/ABDU (#92576)Simon Pilgrim
2024-08-03Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)Sergei Barannikov
2024-08-02Revert "[AMDGPU] Always lower s/udiv64 by constant to MUL (#100723)"Fangrui Song
2024-08-02[AMDGPU] Always lower s/udiv64 by constant to MUL (#100723)Pierre van Houtryve
2024-08-02[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#99752)Sergei Barannikov
2024-07-30Recommit "[DAG] Reducing instructions by better legalization handling of AVGF...Julius Alexandre
2024-07-27Revert "[DAG] Reducing instructions by better legalization handling of AVGFLO...Craig Topper
2024-07-27[DAG] Reducing instructions by better legalization handling of AVGFLOORU for ...Julius Alexandre
2024-07-26DAG: Lower is.fpclass fcSubnormal|fcZero to fabs(x) < smallest_normal (#100390)Matt Arsenault
2024-07-19[CodeGen] Remove checks for vectors in unsigned division prior to computing l...AtariDreams
2024-07-17[CodeGen] Emit more efficient magic numbers for exact udivs (#87161)AtariDreams
2024-07-17[LLVM] Add `llvm.experimental.vector.compress` intrinsic (#92289)Lawrence Benson
2024-07-16[SelectionDAG] Expand [US]CMP using arithmetic on boolean values instead of s...Volodymyr Vasylkun
2024-07-14[SelectionDAG][RISCV] Fix break of vnsrl pattern in issue #94265 (#95563)Froster
2024-07-10[SelectionDAG] Use LAST_INTEGER_VALUETYPE instead of i64 (#98299)Dmitry Borisenkov
2024-07-04[SelectionDAG] Remove LegalTypes argument from getShiftAmountConstant. (#97653)Craig Topper
2024-07-04[SelectionDAG] Remove LegalTypes argument from getShiftAmountTy. NFC (#97757)Craig Topper
2024-06-26[DAG] expandAVG - attempt to extend to a wider integer type for the add/shift...Simon Pilgrim
2024-06-21Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"Nikita Popov
2024-06-21Intrinsic: introduce minimumnum and maximumnum (#93841)YunQiang Su
2024-06-17[SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (#91871)Poseydon42
2024-06-13[DAG] combineShiftToAVG - don't create avgfloor with scalar constant operand...Simon Pilgrim
2024-06-12[DAG] combineShiftToAVG - only create new types before LegalTypesSimon Pilgrim
2024-06-12[DAG] combineShiftToAVG - ensure the reduced demanded value type is smaller t...Simon Pilgrim
2024-06-12[DAG] Add legalization handling for AVGCEIL/AVGFLOOR nodes (#92096)Simon Pilgrim
2024-06-07[KnownBits] Remove `hasConflict()` assertions (#94568)c8ef
2024-06-06DAG: Improve fminimum/fmaximum vector expansion logic (#93579)Matt Arsenault
2024-06-06[DAG] expandABS - add missing FREEZE in abs(x) -> smax(x,sub(0,x)) expansionSimon Pilgrim
2024-06-01[DAG] Replace getValid*ShiftAmountConstant helpers with getValid*ShiftAmount ...Simon Pilgrim
2024-05-29DAG: Preserve flags when expanding fminimum/fmaximum (#93550)Matt Arsenault
2024-05-28[DAG] Use auto* for cast/dyn_cast results (style). NFC.Simon Pilgrim
2024-05-24[SelectionDAG][RISCV][VE] Rename VP_ASHR->VP_SRA VP_LSHR->VP_SRL. (#93221)Craig Topper
2024-05-23[DAG][X86] expandABD - add branchless abds/abdu expansion for 0/-1 comparison...Simon Pilgrim
2024-05-22[SDAG] Improve `SimplifyDemandedBits` for mul (#90034)Yingwei Zheng
2024-05-22[SDAG] Don't treat ISD::SHL as a uniform binary operator in `ShrinkDemandedOp...Yingwei Zheng
2024-05-22[DAG] SimplifyDemandedBits - ensure we have simplified the shift operands bef...Simon Pilgrim
2024-05-16[DAG] SimplifyDemandedBits - use ComputeKnownBits instead of getValidShiftAmo...Simon Pilgrim
2024-05-16[DAG] SimplifyDemandedBits - ISD::AND - only request DemandedElts when lookin...Simon Pilgrim
2024-05-14[llvm] Support fixed point multiplication on AArch64 (#84237)PiJoules
2024-05-09DAG: Skip 0 sign handling in minimum/maximum lowering for _ieee case (#91326)Matt Arsenault
2024-05-07[Analysis] Attribute Range should not prevent tail call optimization (#91122)Jinsong Ji
2024-04-30[VP][RISCV] Add vp.cttz.elts intrinsic and its RISC-V codegen (#90502)Min-Yih Hsu
2024-04-29[Legalizer] Expand fmaximum and fminimum (#67301)Qiu Chaofan
2024-04-15[SelectionDAG] Propagate Disjoint flag. (#88370)fengfeng
2024-04-12[SelectionDAG] Fix and improve TargetLowering::SimplifySetCC (#87646)Björn Pettersson
2024-04-04[APInt] Add a simpler overload of multiplicativeInverse (#87610)Jay Foad
2024-04-04[DAG] Remove extract_vector_elt(freeze(x)), idx -> freeze(extract_vector_elt(...Simon Pilgrim
2024-04-03[DAG] SimplifyDemandedVectorElts - add ISD::AVGCEILS/AVGCEILU/AVGFLOORS/AVGFL...aniplcc
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