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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
AgeCommit message (Expand)Author
2025-06-09[CodeGen] Construct SmallVector with ArrayRef (NFC) (#143391)Kazu Hirata
2025-06-06RuntimeLibcalls: Rename fminimum_num/fmaximum_num enums (#143078)Matt Arsenault
2025-06-04Revert "[SDAG] Fix fmaximum legalization errors (#142170)"Nikita Popov
2025-06-03[SelectionDAG][AArch64] Legalize power of 2 vector.[de]interleaveN (#141513)Luke Lau
2025-06-02[SDAG] Fix fmaximum legalization errors (#142170)Nikita Popov
2025-05-16[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)Craig Topper
2025-04-23[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#101786)Sergei Barannikov
2025-04-16Fix 'unannotated fall-through between switch labels' warning. (#136000)Jonas Paulsson
2025-04-16[SystemZ] Add support for 16-bit floating point. (#109164)Jonas Paulsson
2025-04-10Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the ...zhijian lin
2025-04-09Revert "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the ...Jakub Kuderski
2025-04-07[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison v...zhijian lin
2025-03-27Port `NVPTXTargetLowering::LowerCONCAT_VECTORS` to SelectionDAG (#120030)Ethan Kaji
2025-03-25Calculate KnownBits from Metadata correctly for vector loads (#128908)LU-JOHN
2025-03-12[NVPTX] Legalize ctpop and ctlz in operation legalization (#130668)Alex MacLean
2025-03-07[SelectionDAG] Clean up some redundant setting of node flags (NFC) (#130307)John Brawn
2025-03-07[SelectionDAG] Preserve fast math flags when legalizing/promoting (#130124)John Brawn
2025-02-28[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} (#128800)Jim Lin
2025-02-11[RTLIB] Rename getFSINCOS() to getSINCOS (NFC) (#126705)Benjamin Maxwell
2025-02-11[IR] Add llvm.sincospi intrinsic (#125873)Benjamin Maxwell
2025-02-07[IR] Add `llvm.modf` intrinsic (#121948)Benjamin Maxwell
2025-01-31[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tablesAlexander Richardson
2025-01-10[SDAG] Set IsPostTypeLegalization flag in LegalizeDAG (#122278)Nikita Popov
2024-12-18[SelectionDAG] Rename SDNode::uses() to users(). (#120499)Craig Topper
2024-12-03[TargetLowering] Use Type* instead of EVT in shouldSignExtendTypeInLibCall. (...Craig Topper
2024-12-03[SelectionDAG] Rename CallOptions::IsSExt to IsSigned. NFC (#118574)Craig Topper
2024-11-25[SelectionDAG] Require last operand of (STRICT_)FP_ROUND to be a TargetConsta...Craig Topper
2024-11-25[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix in...Craig Topper
2024-11-25[AMDGPU] Use getSignedConstant() where necessary (#117328)Nikita Popov
2024-11-06[SDAG] Merge multiple-result libcall expansion into DAG.expandMultipleResultF...Benjamin Maxwell
2024-10-31[SDAG] Support expanding `FSINCOS` to vector library calls (#114039)Benjamin Maxwell
2024-10-30[LegalizeDAG] Use getSignedConstant. NFCCraig Topper
2024-10-31[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)Yingwei Zheng
2024-10-29DAG: Fix legalization of vector addrspacecasts (#113964)Matt Arsenault
2024-10-29[IR] Add `llvm.sincos` intrinsic (#109825)Benjamin Maxwell
2024-10-16[X86][CodeGen] Add base atan2 intrinsic lowering (p4) (#110760)Tex Riddell
2024-10-08Fix comment typo in ExpandFCOPYSIGN (#111489)Ralf Jung
2024-10-04[SDAG][RISCV] Don't promote VP_REDUCE_{FADD,FMUL} (#111000)Luke Lau
2024-09-25[SDAG] Honor signed arguments in floating point libcalls (#109134)Timothy Pearson
2024-09-24[SDAG] Avoid creating redundant stack slots when lowering FSINCOS (#108401)Benjamin Maxwell
2024-08-30[AArch64][SelectionDAG] Vector splitting and promotion for histogram intrinsi...Max Beck-Jones
2024-08-17[SelectionDAG] Use getAllOnesConstant.Craig Topper
2024-08-16[SelectionDAG][X86] Add SelectionDAG::getSignedConstant and use it in a few p...Craig Topper
2024-08-15Intrinsic: introduce minimumnum and maximumnum for IR and SelectionDAG (#96649)YunQiang Su
2024-08-13[SelectionDAG] Replace EVTToAPFloatSemantics with MVT/EVT::getFltSemantics. (...Craig Topper
2024-08-09[llvm] Construct SmallVector<SDValue> with ArrayRef (NFC) (#102578)Kazu Hirata
2024-08-09[SelectionDAG] Use unaligned store/load to move AVX registers onto stack for ...Manish Kausik H
2024-08-03Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)Sergei Barannikov
2024-08-02[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#99752)Sergei Barannikov
2024-07-24[AMDGPU] Implement llvm.lrint intrinsic lowering (#98931)Sumanth Gundapaneni
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