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path: root/llvm/lib/CodeGen/MachineScheduler.cpp
AgeCommit message (Expand)Author
2018-11-28[MachineScheduler] Add support for clustering mem ops with FI base operandsFrancis Visoiu Mistrih
2018-11-28[CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih
2018-11-14Bias physical register immediate assignmentsNirav Dave
2018-11-09Type safe version of MachinePassRegistrySerge Guelton
2018-09-27llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)Fangrui Song
2018-09-19MachineScheduler: Add -misched-print-dags flagMatthias Braun
2018-09-19ScheduleDAG: Cleanup dumping code; NFCMatthias Braun
2018-08-21MachineScheduler: Refactor setPolicy() to limit computing remaining latencyTom Stellard
2018-06-20[NFC] fix trivial typos in commentsHiroshi Inoue
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen
2018-05-09[DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen
2018-05-01Remove \brief commands from doxygen comments.Adrian Prantl
2018-04-30IWYU for llvm-config.h in llvm, additions.Nico Weber
2018-04-12[MachineScheduler] NFC refactoringJonas Paulsson
2018-04-06[CodeGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang
2018-03-23Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie
2018-03-05[MachineScheduler] Dump SUnits before calling SchedImpl->initialize()Jonas Paulsson
2018-02-19Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasic...Francis Visoiu Mistrih
2018-02-08[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::p...Francis Visoiu Mistrih
2018-01-23CodeGen: Fix assertion in ScheduleDAGMILive::scheduleMI due to llvm.dbg.valueYaxun Liu
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun
2017-12-15Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-14Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-13CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-13Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-28[CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie
2017-11-08Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie
2017-10-25[MachineScheduler] Minor refactoring.Jonas Paulsson
2017-10-15Reverting r315590; it did not include changes for llvm-tblgen, which is causi...Aaron Ballman
2017-10-12[dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton
2017-10-10CodeGen: Minor cleanups to use MachineInstr::getMF. NFCJustin Bogner
2017-10-03[MiSched] - Simplify ProcResEntry accessJaved Absar
2017-09-27[Misched]: Remove double call getMicroOpFactor.NFC.Javed Absar
2017-09-13Allow target to decide when to cluster loads/stores in mischedStanislav Mekhanoshin
2017-09-13[MachineScheduler] Put SchedRegion in an anonymous namespace.Mikael Holmen
2017-09-11[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko
2017-08-17[SystemZ, MachineScheduler] Improve post-RA scheduling.Jonas Paulsson
2017-06-21Mark dump() methods as const. NFCSam Clegg
2017-06-21Use range-loop in machine-scheduler. NFCI.Javed Absar
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth
2017-05-27ScheduleDAGInstrs: Fix fixupKills()Matthias Braun
2017-05-25CodeGen: Rename DEBUG_TYPE to match passnamesMatthias Braun
2017-05-23[AArch64] Make instruction fusion more aggressive. Florian Hahn
2017-04-12MachineScheduler: Skip acyclic latency heuristic for in-order coresMatthias Braun
2017-03-27Improve machine schedulers for in-order processorsJaved Absar
2017-03-24[MachineScheduler] Add missing machine pass dependency.Davide Italiano
2017-02-24Revert "Correct register pressure calculation in presence of subregs"Stanislav Mekhanoshin
2017-02-23Correct register pressure calculation in presence of subregsStanislav Mekhanoshin
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