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path: root/llvm/lib/CodeGen/MachineScheduler.cpp
AgeCommit message (Expand)Author
2025-07-22[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolic...Harrison Hao
2025-06-29[CodeGen] Use std::tie to implement a comparison functor (NFC) (#146252)Kazu Hirata
2025-06-05MachineScheduler: Improve instruction clustering (#137784)Ruiling, Song
2025-06-03[MISched] Add templates for creating custom schedulers (#141935)Pengcheng Wang
2025-05-28MachineScheduler: Reset next cluster candidate for each node (#139513)Ruiling, Song
2025-05-17[llvm] Use llvm::is_sorted (NFC) (#140399)Kazu Hirata
2025-05-09[MISched] Add statistics for heuristics (#137981)Cullen Rhodes
2025-05-07[MISched] Add statistics to quantify scheduling (#138090)Cullen Rhodes
2025-05-06[MISched] Fix off-by-one error in debug output with -misched-cutoff=<n> flag ...Cullen Rhodes
2025-04-18[Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)Philip Reames
2025-04-08[MachineScheduler] Add more debug prints w.r.t hazards and pending SUnits (#1...Min-Yih Hsu
2025-03-04[CodeGen] Avoid repeated hash lookups (NFC) (#129821)Kazu Hirata
2025-03-04[CodeGen] Use Register in SDep interface. NFC (#129734)Craig Topper
2025-03-04[MachineScheduler] Optional scheduling of single-MI regions (#129704)Lucas Ramirez
2025-03-04[NPM][NFC] Chain PreservedAnalyses methods (#129505)Akshat Oke
2025-03-03[NFC]Make file-local cl::opt global variables static (#126486)chrisPyr
2025-02-27[MachineScheduler][AMDGPU] Allow scheduling of single-MI regions (#128739)Lucas Ramirez
2025-02-24[MachineSched] Add a first valid reason [nfc]Philip Reames
2025-02-20Revert "[CodeGen] Remove static member function Register::isPhysicalRegister....Christopher Di Bella
2025-02-20[CodeGen] Remove static member function Register::isPhysicalRegister. NFCCraig Topper
2025-02-13[MISched][NFC] Remove unused heuristic NextDefUse from enum (#125879)Cullen Rhodes
2025-02-12Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)Akshat Oke
2025-02-08Revert "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126268)Akshat Oke
2025-02-05[MISched] Small debug improvements (#125072)Cullen Rhodes
2025-02-05CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)Christudasan Devadasan
2025-02-05[CodeGen][MachineScheduler] Remove the unimplemented print method. (#125702)Christudasan Devadasan
2025-02-05[CodeGen] Move MISched target hooks into TargetMachine (#125700)Christudasan Devadasan
2025-01-22[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (#123799)Craig Topper
2024-12-12[MISched] Unify the way to specify scheduling direction (#119518)Pengcheng Wang
2024-12-10[MISched] Compare right next cluster node (#116584)Pengcheng Wang
2024-12-05[Sched] Skip MemOp with unknown size when clustering (#118443)Pengcheng Wang
2024-11-27[MISched] Use right boundary when trying latency heuristics (#116592)Pengcheng Wang
2024-11-12[MISched] Add a hook to override PostRA scheduling policy (#115455)Pengcheng Wang
2024-11-08[CodeGen][MISched] Set DumpDirection after initPolicy (#115112)Pengcheng Wang
2024-09-24llvm-reduce: Don't print verifier failed machine functions (#109673)Matt Arsenault
2024-08-29[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)Stephen Tozer
2024-08-04[CodeGen] Construct SmallVector with ArrayRef (NFC) (#101841)Kazu Hirata
2024-07-10[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)paperchalice
2024-07-09[CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941)paperchalice
2024-07-09[CodeGen][NewPM] Port `machine-loops` to new pass manager (#97793)paperchalice
2024-07-01[llvm][CodeGen] Avoid 'raw_string_ostream::str' (NFC) (#97318)Youngsuk Kim
2024-06-11[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result...paperchalice
2024-05-22[MISched][NFC] Add documentation comment in pickNode for ReadyQueue maintenen...Michael Maitland
2024-05-21MachineScheduler: Add parameter name commentsMatt Arsenault
2024-04-15[mi-sched] Suppress register pressure with i64. (#88256)laichunfeng
2024-04-02MachineScheduler: Simplify usage of TargetInstrInfoMatt Arsenault
2024-03-25[CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (#77138)Michael Maitland
2024-03-06[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)David Green
2024-02-27[CodeGen][MISched] Add misched post-regalloc bottom-up schedulingMichael Maitland
2024-02-27[CodeGen][MISched] dumpSched direction depends on field in DAG.Michael Maitland
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