summaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
AgeCommit message (Collapse)Author
2024-11-12[CodeGen] Remove unused includes (NFC) (#115996)Kazu Hirata
Identified with misc-include-cleaner.
2024-08-28Revert "[CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC)" (#106451)Vitaly Buka
Reverts llvm/llvm-project#106404 Breaks: https://lab.llvm.org/buildbot/#/builders/169/builds/2590 https://lab.llvm.org/buildbot/#/builders/164/builds/2454
2024-08-28[CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC) (#106404)Kazu Hirata
2024-07-10[CodeGen] Use range-based for loops (NFC) (#98104)Kazu Hirata
2024-03-06Restore "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe
This restores commit c7fdd8c11e54585dc9d15d63de9742067e0506b9. Previously reverted in f010b1bef4dda2c7082cbb41dbabf1f149cce306. LLVM function calls carry convergence control tokens as operand bundles, where the tokens themselves are produced by convergence control intrinsics. This patch implements convergence control tokens in MIR as follows: 1. Introduce target-independent ISD opcodes and MIR opcodes for convergence control intrinsics. 2. Model token values as untyped virtual registers in MIR. The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a corresponding machine opcode with the same spelling. This glues the convergence control token to SDNodes that represent calls to intrinsics. The glued token is later translated to an implicit argument in the MIR. The lowering of calls to user-defined functions is target-specific. On AMDGPU, the convergence control operand bundle at a non-intrinsic call is translated to an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment converts this explicit argument to an implicit argument on the SI_CALL instruction.
2024-03-04Revert "Restore "Implement convergence control in MIR using SelectionDAG ↵Mitch Phillips
(#71785)"" This reverts commit c7fdd8c11e54585dc9d15d63de9742067e0506b9. Reason: Broke the sanitizer buildbots. See the comments at https://github.com/llvm/llvm-project/pull/71785 for more information.
2024-03-04Restore "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe
Original commit 79889734b940356ab3381423c93ae06f22e772c9. Perviously reverted in commit a2afcd5721869d1d03c8146bae3885b3385ba15e. LLVM function calls carry convergence control tokens as operand bundles, where the tokens themselves are produced by convergence control intrinsics. This patch implements convergence control tokens in MIR as follows: 1. Introduce target-independent ISD opcodes and MIR opcodes for convergence control intrinsics. 2. Model token values as untyped virtual registers in MIR. The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a corresponding machine opcode with the same spelling. This glues the convergence control token to SDNodes that represent calls to intrinsics. The glued token is later translated to an implicit argument in the MIR. The lowering of calls to user-defined functions is target-specific. On AMDGPU, the convergence control operand bundle at a non-intrinsic call is translated to an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment converts this explicit argument to an implicit argument on the SI_CALL instruction.
2024-02-21Revert "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe
This reverts commit 79889734b940356ab3381423c93ae06f22e772c9. Encountered multiple buildbot failures.
2024-02-21Implement convergence control in MIR using SelectionDAG (#71785)Sameer Sahasrabuddhe
LLVM function calls carry convergence control tokens as operand bundles, where the tokens themselves are produced by convergence control intrinsics. This patch implements convergence control tokens in MIR as follows: 1. Introduce target-independent ISD opcodes and MIR opcodes for convergence control intrinsics. 2. Model token values as untyped virtual registers in MIR. The change also introduces an additional ISD opcode CONVERGENCECTRL_GLUE and a corresponding machine opcode with the same spelling. This glues the convergence control token to SDNodes that represent calls to intrinsics. The glued token is later translated to an implicit argument in the MIR. The lowering of calls to user-defined functions is target-specific. On AMDGPU, the convergence control operand bundle at a non-intrinsic call is translated to an explicit argument to the SI_CALL_ISEL instruction. Post-selection adjustment converts this explicit argument to an implicit argument on the SI_CALL instruction.