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path: root/llvm/lib/CodeGen/LiveRegUnits.cpp
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2022-09-13LiveRegUnits: Break register loop when a clobber is encounteredMatt Arsenault
2022-09-13LiveRegUnits: Cleanup isReg checksMatt Arsenault
This is the common case and should be checked first. Provides a very marginal compile time improvement on the example I'm looking at.
2022-09-12LiveRegUnits: Do not use phys_regs_and_masksMatt Arsenault
Somehow DeadMachineInstructionElim is about 3x slower when using it. Hopefully this reverses the compile time regression reported for b5041527c75de2f409aa9e2e6deba12b17834c59.
2021-01-28[ARM][RegisterScavenging] Don't consider LR liveout if it is not reloadedTomas Matheson
https://bugs.llvm.org/show_bug.cgi?id=48232 When PrologEpilogInserter writes callee-saved registers to the stack, LR is not reloaded but is instead loaded directly into PC. This was not taken into account when determining if each callee-saved register was liveout for the block. When frame elimination inserts virtual registers, and the register scavenger tries to scavenge LR, it considers it liveout and tries to spill again. However there is no emergency spill slot to use, and it fails with an error: fatal error: error in backend: Error while trying to spill LR from class GPR: Cannot scavenge register without an emergency spill slot! This patch pervents any callee-saved registers which are not reloaded (including LR) from being marked liveout. They are therefore available to scavenge without requiring an extra spill.
2020-09-08LiveRegUnits.h - reduce MachineRegisterInfo.h include. NFC.Simon Pilgrim
We only need to include MachineInstrBundle.h, but exposes an implicit dependency in MachineOutliner.h. Also, remove duplicate includes from LiveRegUnits.cpp + MachineOutliner.cpp.
2019-12-11[LiveRegUnits] Add phys_regs_and_masks iterator range (NFC).Florian Hahn
This iterator range just includes physical registers and register masks, which are interesting when dealing with register liveness. Reviewers: evandro, t.p.northover, paquette, MatzeB, arsenm Reviewed By: paquette Differential Revision: https://reviews.llvm.org/D70562
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders
Summary: This clang-tidy check is looking for unsigned integer variables whose initializer starts with an implicit cast from llvm::Register and changes the type of the variable to llvm::Register (dropping the llvm:: where possible). Partial reverts in: X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned& MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register PPCFastISel.cpp - No Register::operator-=() PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned& MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor Manual fixups in: ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned& HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register. PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned& Depends on D65919 Reviewers: arsenm, bogner, craig.topper, RKSimon Reviewed By: arsenm Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65962 llvm-svn: 369041
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders
llvm::Register as started by r367614. NFC llvm-svn: 367633
2019-02-01[CodeGen] Don't scavenge non-saved regs in exception throwing functionsOliver Stannard
Previously, LiveRegUnits was assuming that if a block has no successors and does not return, then no registers are live at the end of it (because the end of the block is unreachable). This was causing the register scavenger to use callee-saved registers to materialise stack frame addresses without saving them in the prologue. This would normally be fine, because the end of the block is unreachable, but this is not legal if the block ends by throwing a C++ exception. If this happens, the scratch register will be modified, but its previous value won't be preserved, so it doesn't get restored by the exception unwinder. Differential revision: https://reviews.llvm.org/D57381 llvm-svn: 352844
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2018-06-21[CodeGen] Avoid handling DBG_VALUE in LiveRegUnits::stepBackwardKrzysztof Parzyszek
Patch by Jesper Antonsson. Differential Revision: https://reviews.llvm.org/D48420 llvm-svn: 335233
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
2017-09-08Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnitsKrzysztof Parzyszek
Differential Revision: https://reviews.llvm.org/D37600 llvm-svn: 312797
2017-07-07LiveRegUnits: Rename accumulateBackward()->accumulate()Matthias Braun
Contrary to the stepForward()/stepBackward() method accumulate() doesn't have a direction as defs, uses and clobbers all have the same effect. Also improve the documentation comment. llvm-svn: 307351
2017-06-03LiveRegUnits: Port recent LivePhysRegs bugfixesMatthias Braun
Adjust code to look more like the code in LivePhysRegs and port over the fix for LivePhysRegs from r304001 and adapt to the new CSR management in MachineRegisterInfo. llvm-svn: 304622
2017-02-17[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko
other minor fixes (NFC). llvm-svn: 295499
2017-01-21LiveRegUnits: Add accumulateBackward() functionMatthias Braun
Re-Commit r292543 with a fix for the situation when the chain end is MBB.end(). This function can be used to accumulate the set of all read and modified register in a sequence of instructions. Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove the concept. - The AArch64A57LoadBalancing code is using a backwards analysis now which is irrespective of kill flags. This is the main motivation for this change. Differential Revision: http://reviews.llvm.org/D22082 llvm-svn: 292705
2017-01-20Revert "LiveRegUnits: Add accumulateBackward() function"Matthias Braun
This seems to be breaking some bots. This reverts commit r292543. llvm-svn: 292574
2017-01-20LiveRegUnits: Add accumulateBackward() functionMatthias Braun
This function can be used to accumulate the set of all read and modified register in a sequence of instructions. Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove the concept. - The AArch64A57LoadBalancing code is using a backwards analysis now which is irrespective of kill flags. This is the main motivation for this change. Differential Revision: http://reviews.llvm.org/D22082 llvm-svn: 292543
2017-01-20CodeGen: Add/Factor out LiveRegUnits class; NFCIMatthias Braun
This is a set of register units intended to track register liveness, it is similar in spirit to LivePhysRegs. You can also think of this as the liveness tracking parts of the RegisterScavenger factored out into an own class. This was proposed in http://llvm.org/PR27609 Differential Revision: http://reviews.llvm.org/D21916 llvm-svn: 292542
2016-08-19Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun
The ppc64 multistage bot fails on this. This reverts commit r279124. Also Revert "CodeGen: Add/Factor out LiveRegUnits class; NFCI" because it depends on the previous change This reverts commit r279171. llvm-svn: 279199
2016-08-18CodeGen: Add/Factor out LiveRegUnits class; NFCIMatthias Braun
This is a set of register units intended to track register liveness, it is similar in spirit to LivePhysRegs. You can also think of this as the liveness tracking parts of the RegisterScavenger factored out into an own class. This was proposed in http://llvm.org/PR27609 Differential Revision: http://reviews.llvm.org/D21916 llvm-svn: 279171
2013-12-14Convert register liveness tracking to work on a sub-register level instead ↵Juergen Ributzka
of just register units. Reviewed by Andy llvm-svn: 197315
2013-12-13Revert "Convert liveness tracking to work on a sub-register level instead of ↵Andrew Trick
just register units." This reverts commit r197253. This was a great change, but Juergen should be the commit author. llvm-svn: 197262
2013-12-13Convert liveness tracking to work on a sub-register level instead of just ↵Andrew Trick
register units. llvm-svn: 197253
2013-10-14LiveRegUnits: Use *MBB for consistency and convenience.Andrew Trick
llvm-svn: 192634
2013-10-14LiveRegUnits::removeRegsInMask safety.Andrew Trick
Clobbering is exclusive not inclusive on register units. For liveness, we need to consider all the preserved registers. e.g. A regmask that clobbers YMM0 may preserve XMM0. Units are only clobbered when all super-registers are clobbered. llvm-svn: 192623
2013-10-14Move LiveRegUnits implementation into .cpp. Comment and format.Andrew Trick
llvm-svn: 192621
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