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path: root/llvm/lib/CodeGen/ExpandVectorPredication.cpp
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2025-06-10[NFC][LLVM] Refactor IRBuilder::Create{VScale,ElementCount,TypeSize}. (#142803)Paul Walker
CreateVScale took a scaling parameter that had a single use outside of IRBuilder with all other callers having to create a redundant ConstantInt. To work round this some code perferred to use CreateIntrinsic directly. This patch simplifies CreateVScale to return a call to the llvm.vscale() intrinsic and nothing more. As well as simplifying the existing call sites I've also migrated the uses of CreateIntrinsic. Whilst IRBuilder used CreateVScale's scaling parameter as part of the implementations of CreateElementCount and CreateTypeSize, I have follow-on work to switch them to the NUW varaiety and thus they would stop using CreateVScale's scaling as well. To prepare for this I have moved the multiplication and constant folding into the implementations of CreateElementCount and CreateTypeSize. As a final step I have replaced some callers of CreateVScale with CreateElementCount where it's clear from the code they wanted the latter.
2025-03-20[Intrinsics] Add Intrinsic::getFnAttributes() (NFC) (#132029)Nikita Popov
Most places that call Intrinsic::getAttributes() are only interested in the function attributes, so add a separate function for that. The motivation for this is that I'd like to add the ability to specify range attributes on intrinsics, which requires knowing the function type. This avoids needing to know the type for most attribute queries.
2025-01-16[VP] Remove createStepVector implementation and use ↵LiqinWeng
IRBuilderBase::CreateStepVector instead. NFC (#122868)
2025-01-16[VP] IR expansion to Int Func Call (#122867)LiqinWeng
Add basic handling for VP ops that can expand to Int intrinsics, which includes: ctpop/cttz/ctlz/sadd.sat/uadd.sat/ssub.sat/usub.sat/fshl/fshr
2024-11-25[VP] Refactoring some functions in ExpandVectorPredication.NFC (#115840)LiqinWeng
Building vp intrinsic functions using a unified interface for expandPredicationToIntCall/expandPredicationToFPCall/expandPredicationToCastIntrinsic functions.
2024-11-12[CodeGen] Remove unused includes (NFC) (#115996)Kazu Hirata
Identified with misc-include-cleaner.
2024-10-17[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)Jay Foad
Convert many instances of: Fn = Intrinsic::getOrInsertDeclaration(...); CreateCall(Fn, ...) to the equivalent CreateIntrinsic call.
2024-10-11[NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (#111752)Rahul Joshi
Rename the function to reflect its correct behavior and to be consistent with `Module::getOrInsertFunction`. This is also in preparation of adding a new `Intrinsic::getDeclaration` that will have behavior similar to `Module::getFunction` (i.e, just lookup, no creation).
2024-09-04Consolidate all IR logic for getting the identity value of a reduction [nfc]Philip Reames
This change merges the three different places (at the IR layer) for finding the identity value of a reduction into a single copy. This depends on several prior commits which fix ommissions and bugs in the distinct copies, but this patch itself should be fully non-functional. As the new comments and naming try to make clear, the identity value is a property of the @llvm.vector.reduce.* intrinsic, not of e.g. the recurrence descriptor. (We still provide an interface for clients using recurrence descriptors, but the implementation simply translates to the intrinsic which each corresponds to.) As a note, the getIntrinsicIdentity API does not support fminnum/fmaxnum or fminimum/fmaximum which is why we still need manual logic (but at least only one copy of manual logic) for those cases.
2024-09-03Prefer use of 0.0 over -0.0 for fadd reductions w/nsz (in IR) (#106770)Philip Reames
This is a follow up to 924907bc6, and is mostly motivated by consistency but does include one additional optimization. In general, we prefer 0.0 over -0.0 as the identity value for an fadd. We use that value in several places, but don't in others. So, let's be consistent and use the same identity (when nsz allows) everywhere. This creates a bunch of test churn, but due to 924907bc6, most of that churn doesn't actually indicate a change in codegen. The exception is that this change enables the use of 0.0 for nsz, but *not* reasoc, fadd reductions. Or said differently, it allows the neutral value of an ordered fadd reduction to be 0.0.
2024-08-30[VP] Reduce duplicate code in vp.reduce expansionsPhilip Reames
Primary goal is having one way of doing this, to ensure that we don't end up with accidental divergence.
2024-08-09[ExpandVectorPredication] Be more precise reporting changes (#102313)Roger Ferrer Ibáñez
This is used by PreISelIntrinsicLowering. With this change, PreISelIntrinsicLowering does not have to assume that there were changes just because we encountered a VP intrinsic.
2024-08-06[VP] Merge ExpandVP pass into PreISelIntrinsicLowering (#101652)Alexis Engelke
Similar to #97727; avoid an extra pass over the entire IR by performing the lowering as part of the pre-isel-intrinsic-lowering pass.
2024-06-28[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)Nikita Popov
Similar to https://github.com/llvm/llvm-project/pull/96902, this adds `getDataLayout()` helpers to Function and GlobalValue, replacing the current `getParent()->getDataLayout()` pattern.
2024-06-24Revert "[IR][NFC] Update IRBuilder to use InsertPosition (#96497)"Stephen Tozer
Reverts the above commit, as it updates a common header function and did not update all callsites: https://lab.llvm.org/buildbot/#/builders/29/builds/382 This reverts commit 6481dc57612671ebe77fe9c34214fba94e1b3b27.
2024-06-24[IR][NFC] Update IRBuilder to use InsertPosition (#96497)Stephen Tozer
Uses the new InsertPosition class (added in #94226) to simplify some of the IRBuilder interface, and removes the need to pass a BasicBlock alongside a BasicBlock::iterator, using the fact that we can now get the parent basic block from the iterator even if it points to the sentinel. This patch removes the BasicBlock argument from each constructor or call to setInsertPoint. This has no functional effect, but later on as we look to remove the `Instruction *InsertBefore` argument from instruction-creation (discussed [here](https://discourse.llvm.org/t/psa-instruction-constructors-changing-to-iterator-only-insertion/77845)), this will simplify the process by allowing us to deprecate the InsertPosition constructor directly and catch all the cases where we use instructions rather than iterators.
2024-06-21Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"Nikita Popov
As far as I can tell, this pull request was not approved, and did not go through an RFC on discourse. This reverts commit 89881480030f48f83af668175b70a9798edca2fb. This reverts commit 225d8fc8eb24fb797154c1ef6dcbe5ba033142da.
2024-06-21Intrinsic: introduce minimumnum and maximumnum (#93841)YunQiang Su
Currently, on different platform, the behaivor of llvm.minnum is different if one operand is sNaN: When we compare sNaN vs NUM: ARM/AArch64/PowerPC: follow the IEEE754-2008's minNUM: return qNaN. RISC-V/Hexagon follow the IEEE754-2019's minimumNumber: return NUM. X86: Returns NUM but not same with IEEE754-2019's minimumNumber as +0.0 is not always greater than -0.0. MIPS/LoongArch/Generic: return NUM. LIBCALL: returns qNaN. So, let's introduce llvm.minmumnum/llvm.maximumnum, which always follow IEEE754-2019's minimumNumber/maximumNumber. Half-fix: #93033
2024-05-10[VP][RISCV] Add vp.reduce.fmaximum/fminimum and its RISC-V codegen (#91782)Min-Yih Hsu
`vp.reduce.fmaximum/fminimum` are the VP version of `vector.reduce.fmaximum/fminimum`.
2024-04-17[VP] Correct lowering of predicated fma and faddmul to avoid strictfp. (#85272)Kevin P. Neal
Correct missing cases in a switch that result in @llvm.vp.fma.v4f32 getting lowered to a constrained fma intrinsic. Vector predicated lowering to contrained intrinsics is not supported currently, and there's no consensus on the path forward. We certainly shouldn't be introducing constrained intrinsics into a function that isn't strictfp. Problem found with D146845.
2024-01-22[VP][RISCV] Introduce llvm.vp.minimum/maximum intrinsics (#74840)Simeon K
Although there are predicated versions of minnum/maxnum, the ones for minimum/maximum are currently missing. This patch introduces these intrinsics and implements their lowering to RISC-V.
2023-10-26[VP] Check if VP ops with functional intrinsics are speculatable (#69504)Luke Lau
Noticed whilst working on #69494. VP intrinsics whose functional equivalent is an intrinsic were being marked as their lanes being non-speculatable, even if the underlying intrinsic was speculatable. This meant that ```llvm %1 = call <4 x i32> @llvm.vp.umax(<4 x i32> %x, <4 x i32> %y, <4 x i1> %mask, i32 %evl) ``` would be expanded out to ```llvm %.splatinsert = insertelement <4 x i32> poison, i32 %evl, i64 0 %.splat = shufflevector <4 x i32> %.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer %1 = icmp ult <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %.splat %2 = and <4 x i1> %1, %mask %3 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> %y) ``` instead of ```llvm %1 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %x, <4 x i32> %y) ``` The cause of this was isSafeToSpeculativelyExecuteWithOpcode checking the function attributes for the VP instruction itself, not the functional intrinsic. Since isSafeToSpeculativelyExecuteWithOpcode expects an already materialized instruction, we can't use it directly for the intrinsic case. So this fixes it by manually checking the function attributes on the intrinsic.
2023-10-09[VP] IR expansion for bitreverse/bswap (#68504)LiqinWeng
2023-10-08[VP] Use the interface of 'getFunctionalIntrinsicID' to get the non-p… ↵LiqinWeng
(#68508) …redicated Intrinsic ID
2023-09-12[VP] IR expansion for maxnum/minnumliqin.weng
Add basic handling for VP ops that can expand to non-predicate ops Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D159494
2023-09-11[VP] IR expansion for zext/sext/trunc/fptosi/fptosi/sitofp/uitofp/fptrunc/fpextliqin.weng
Add basic handling for VP ops that can expand to Cast intrinsics Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D159491
2023-09-11[VP] IR expansion for abs/smax/smin/umax/uminliqin.weng
Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D159495
2023-09-09[VP] IR expansion for inttoptr/ptrtointliqin.weng
Add basic handling for VP ops that can expand to cast intrinsics Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D159478
2023-04-24[VP] Add IR expansion for fnegSimon Pilgrim
Followup to D149052, it wasn't worthwhile to add general support for unary opcodes
2023-04-24[VP] IR expansion for fabs/fsqrt/fma/fmaddSimon Pilgrim
Add basic handling for VP ops that can expand to FP intrinsics Fixes #60464 Differential Revision: https://reviews.llvm.org/D149052
2022-12-16[Transforms,CodeGen] std::optional::value => operator*/operator->Fangrui Song
value() has undesired exception checking semantics and calls __throw_bad_optional_access in libc++. Moreover, the API is unavailable without _LIBCPP_NO_EXCEPTIONS on older Mach-O platforms (see _LIBCPP_AVAILABILITY_BAD_OPTIONAL_ACCESS).
2022-12-04Instructions: convert Optional to std::optionalKrzysztof Parzyszek
2022-10-05[VP] Fix unused variable in release configurationsFraser Cormack
2022-10-05[VP][NFC] Remove \brief commands from doxygen commentsFraser Cormack
Following a precedent set in D46861.
2022-10-05[VP] Add IR expansion for vp.icmp and vp.fcmpFraser Cormack
These intrinsics are simply expanded to regular icmp/fcmp instructions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D121594
2022-08-08[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFCFangrui Song
With C++17 there is no Clang pedantic warning or MSVC C5051.
2022-07-19Use value instead of getValue (NFC)Kazu Hirata
2022-07-19Use has_value instead of hasValue (NFC)Kazu Hirata
2022-07-19[CodeGen] Use value_or instead of getValueOr (NFC)Kazu Hirata
2022-07-18[VP] IR expansion pass for VP gather and scatterLorenzo Albano
Add vp_gather and vp_scatter expansion to unpredicated intrinsics. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D120664
2022-07-18[VP] Implementing expansion pass for VP load and store.Lorenzo Albano
Added function to the ExpandVectorPredication pass to handle VP loads and stores. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D109584
2022-07-06[ValueTracking] Accept Instruction in isSafeToSpeculativelyExecute() (NFC)Nikita Popov
As constant expressions can no longer trap, it only makes sense to call isSafeToSpeculativelyExecute on Instructions, so limit the API to accept only them, rather than general Operators or Values.
2022-06-18[llvm] Use value_or instead of getValueOr (NFC)Kazu Hirata
2022-05-30Re-land "[VP] vp intrinsics are not speculatable" with test fixSimon Moll
Update the llvmir-intrinsics.mlir test to account for the modified attribute sets. This reverts commit 2e2a8a2d9082250e4aad312c6008a526f2b007c7.
2022-05-30Revert "[VP] vp intrinsics are not speculatable"Mehdi Amini
This reverts commit 78a18d2b54e7e8e0e2c1d1cb33d015d7f69b8cc7. Break MLIR bot: https://lab.llvm.org/buildbot/#/builders/61/builds/27127
2022-05-30[VP] vp intrinsics are not speculatableSimon Moll
VP intrinsics show UB if the %evl parameter is out of bounds - they must not carry the speculatable attribute. The out-of-bounds UB disappears when the %evl parameter is expanded into the mask or expansion replaces the entire VP intrinsic with non-VP code. This patch - Removes the speculatable attribute on all VP intrinsics. - Generalizes the isSafeToSpeculativelyExecute function to let VP expansion know whether the VP intrinsic replacement will be speculatable. VP expansion may only discard %evl where this is the case. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D125296
2022-05-25[VP][fix] Don't discard masks in reductionsSimon Moll
When expanding VP reductions to non VP-code, the reduction pass was ignoring the mask before. Fix this by keeping the mask and selecting neutral elements where the mask is zero. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D126362
2022-03-16Cleanup codegen includesserge-sans-paille
This is a (fixed) recommit of https://reviews.llvm.org/D121169 after: 1061034926 before: 1063332844 Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
2022-03-10Revert "Cleanup codegen includes"Nico Weber
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169
2022-03-10Cleanup codegen includesserge-sans-paille
after: 1061034926 before: 1063332844 Differential Revision: https://reviews.llvm.org/D121169