diff options
Diffstat (limited to 'llvm/test')
162 files changed, 11181 insertions, 8258 deletions
diff --git a/llvm/test/Analysis/CostModel/ARM/mve-shuffle-loadstore.ll b/llvm/test/Analysis/CostModel/ARM/mve-shuffle-loadstore.ll index 6a327cfed4e4..ef0b28ea2604 100644 --- a/llvm/test/Analysis/CostModel/ARM/mve-shuffle-loadstore.ll +++ b/llvm/test/Analysis/CostModel/ARM/mve-shuffle-loadstore.ll @@ -7,41 +7,41 @@ define void @vld2(ptr %p) { ; CHECK-LABEL: 'vld2' ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = load <4 x i8>, ptr %p, align 4 -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v4i8_0 = shufflevector <4 x i8> %v4i8, <4 x i8> undef, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v4i8_1 = shufflevector <4 x i8> %v4i8, <4 x i8> undef, <2 x i32> <i32 1, i32 3> +; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v4i8_0 = shufflevector <4 x i8> %v4i8, <4 x i8> undef, <2 x i32> <i32 0, i32 2> +; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v4i8_1 = shufflevector <4 x i8> %v4i8, <4 x i8> undef, <2 x i32> <i32 1, i32 3> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8 = load <8 x i8>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v8i8_0 = shufflevector <8 x i8> %v8i8, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v8i8_1 = shufflevector <8 x i8> %v8i8, <8 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> +; CHECK-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v8i8_0 = shufflevector <8 x i8> %v8i8, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> +; CHECK-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v8i8_1 = shufflevector <8 x i8> %v8i8, <8 x i8> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8 = load <16 x i8>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %v16i8_0 = shufflevector <16 x i8> %v16i8, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> -; CHECK-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %v16i8_1 = shufflevector <16 x i8> %v16i8, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> +; CHECK-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v16i8_0 = shufflevector <16 x i8> %v16i8, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> +; CHECK-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v16i8_1 = shufflevector <16 x i8> %v16i8, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32i8 = load <32 x i8>, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %v32i8_0 = shufflevector <32 x i8> %v32i8, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> -; CHECK-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %v32i8_1 = shufflevector <32 x i8> %v32i8, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> +; CHECK-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v32i8_0 = shufflevector <32 x i8> %v32i8, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> +; CHECK-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v32i8_1 = shufflevector <32 x i8> %v32i8, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = load <4 x i16>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v4i16_0 = shufflevector <4 x i16> %v4i16, <4 x i16> undef, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v4i16_1 = shufflevector <4 x i16> %v4i16, <4 x i16> undef, <2 x i32> <i32 1, i32 3> +; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v4i16_0 = shufflevector <4 x i16> %v4i16, <4 x i16> undef, <2 x i32> <i32 0, i32 2> +; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v4i16_1 = shufflevector <4 x i16> %v4i16, <4 x i16> undef, <2 x i32> <i32 1, i32 3> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16 = load <8 x i16>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v8i16_0 = shufflevector <8 x i16> %v8i16, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v8i16_1 = shufflevector <8 x i16> %v8i16, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> +; CHECK-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v8i16_0 = shufflevector <8 x i16> %v8i16, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> +; CHECK-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v8i16_1 = shufflevector <8 x i16> %v8i16, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i16 = load <16 x i16>, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %v16i16_0 = shufflevector <16 x i16> %v16i16, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> -; CHECK-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %v16i16_1 = shufflevector <16 x i16> %v16i16, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> +; CHECK-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v16i16_0 = shufflevector <16 x i16> %v16i16, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> +; CHECK-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v16i16_1 = shufflevector <16 x i16> %v16i16, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v32i16 = load <32 x i16>, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %v32i16_0 = shufflevector <32 x i16> %v32i16, <32 x i16> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> -; CHECK-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %v32i16_1 = shufflevector <32 x i16> %v32i16, <32 x i16> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> +; CHECK-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v32i16_0 = shufflevector <32 x i16> %v32i16, <32 x i16> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> +; CHECK-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v32i16_1 = shufflevector <32 x i16> %v32i16, <32 x i16> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32 = load <4 x i32>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v4i32_0 = shufflevector <4 x i32> %v4i32, <4 x i32> undef, <2 x i32> <i32 0, i32 2> -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v4i32_1 = shufflevector <4 x i32> %v4i32, <4 x i32> undef, <2 x i32> <i32 1, i32 3> +; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v4i32_0 = shufflevector <4 x i32> %v4i32, <4 x i32> undef, <2 x i32> <i32 0, i32 2> +; CHECK-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v4i32_1 = shufflevector <4 x i32> %v4i32, <4 x i32> undef, <2 x i32> <i32 1, i32 3> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i32 = load <8 x i32>, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v8i32_0 = shufflevector <8 x i32> %v8i32, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v8i32_1 = shufflevector <8 x i32> %v8i32, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> +; CHECK-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v8i32_0 = shufflevector <8 x i32> %v8i32, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> +; CHECK-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v8i32_1 = shufflevector <8 x i32> %v8i32, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i32 = load <16 x i32>, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %v16i32_0 = shufflevector <16 x i32> %v16i32, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> -; CHECK-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %v16i32_1 = shufflevector <16 x i32> %v16i32, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> +; CHECK-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v16i32_0 = shufflevector <16 x i32> %v16i32, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> +; CHECK-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v16i32_1 = shufflevector <16 x i32> %v16i32, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i32 = load <32 x i32>, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %v32i32_0 = shufflevector <32 x i32> %v32i32, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> -; CHECK-NEXT: Cost Model: Found an estimated cost of 768 for instruction: %v32i32_1 = shufflevector <32 x i32> %v32i32, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> +; CHECK-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %v32i32_0 = shufflevector <32 x i32> %v32i32, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> +; CHECK-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %v32i32_1 = shufflevector <32 x i32> %v32i32, <32 x i32> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = load <4 x i64>, ptr %p, align 32 ; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v2i64_0 = shufflevector <4 x i64> %v2i64, <4 x i64> undef, <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %v2i64_1 = shufflevector <4 x i64> %v2i64, <4 x i64> undef, <2 x i32> <i32 1, i32 3> @@ -252,88 +252,171 @@ define void @vld3(ptr %p) { } define void @vld4(ptr %p) { -; CHECK-LABEL: 'vld4' -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = load <8 x i8>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_0 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 0, i32 4> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_1 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 1, i32 5> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_2 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 2, i32 6> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_3 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 3, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = load <16 x i8>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_0 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_1 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_2 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_3 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i8 = load <32 x i8>, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_0 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_1 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_2 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_3 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = load <64 x i8>, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_0 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_1 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_2 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_3 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = load <8 x i16>, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_0 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 0, i32 4> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_1 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 1, i32 5> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_2 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 2, i32 6> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_3 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 3, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = load <16 x i16>, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_0 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_1 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_2 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_3 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = load <32 x i16>, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_0 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_1 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_2 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_3 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16i16 = load <64 x i16>, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_0 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_1 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_2 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_3 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i32 = load <8 x i32>, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_0 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 0, i32 4> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_1 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 1, i32 5> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_2 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 2, i32 6> -; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_3 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 3, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i32 = load <16 x i32>, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_0 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_1 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_2 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_3 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8i32 = load <32 x i32>, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_0 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_1 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_2 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_3 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16i32 = load <64 x i32>, ptr %p, align 256 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_0 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_1 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_2 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_3 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = load <8 x i64>, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_0 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 0, i32 4> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_1 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 1, i32 5> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_2 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 2, i32 6> -; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_3 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 3, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = load <16 x i64>, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_0 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_1 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_2 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> -; CHECK-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_3 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8i64 = load <32 x i64>, ptr %p, align 256 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_0 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_1 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_2 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> -; CHECK-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_3 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16i64 = load <64 x i64>, ptr %p, align 512 -; CHECK-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_0 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_1 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_2 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_3 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-UF2-LABEL: 'vld4' +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = load <8 x i8>, ptr %p, align 8 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_0 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_1 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_2 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i8_3 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = load <16 x i8>, ptr %p, align 8 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_0 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_1 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_2 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i8_3 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i8 = load <32 x i8>, ptr %p, align 32 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_0 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_1 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_2 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i8_3 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = load <64 x i8>, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_0 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_1 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_2 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i8_3 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = load <8 x i16>, ptr %p, align 8 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_0 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_1 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_2 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i16_3 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = load <16 x i16>, ptr %p, align 32 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_0 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_1 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_2 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i16_3 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = load <32 x i16>, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_0 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_1 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_2 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i16_3 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16i16 = load <64 x i16>, ptr %p, align 128 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_0 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_1 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_2 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i16_3 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i32 = load <8 x i32>, ptr %p, align 32 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_0 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_1 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_2 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %v2i32_3 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i32 = load <16 x i32>, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_0 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_1 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_2 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v4i32_3 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8i32 = load <32 x i32>, ptr %p, align 128 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_0 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_1 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_2 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v8i32_3 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16i32 = load <64 x i32>, ptr %p, align 256 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_0 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_1 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_2 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v16i32_3 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = load <8 x i64>, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_0 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_1 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_2 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_3 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = load <16 x i64>, ptr %p, align 128 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_0 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_1 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_2 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_3 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8i64 = load <32 x i64>, ptr %p, align 256 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_0 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_1 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_2 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_3 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16i64 = load <64 x i64>, ptr %p, align 512 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_0 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_1 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_2 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_3 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-UF4-LABEL: 'vld4' +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = load <8 x i8>, ptr %p, align 8 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i8_0 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i8_1 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i8_2 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i8_3 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = load <16 x i8>, ptr %p, align 8 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i8_0 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i8_1 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i8_2 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i8_3 = shufflevector <16 x i8> %v4i8, <16 x i8> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i8 = load <32 x i8>, ptr %p, align 32 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i8_0 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i8_1 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i8_2 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i8_3 = shufflevector <32 x i8> %v8i8, <32 x i8> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = load <64 x i8>, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v16i8_0 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v16i8_1 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v16i8_2 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 258 for instruction: %v16i8_3 = shufflevector <64 x i8> %v16i8, <64 x i8> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = load <8 x i16>, ptr %p, align 8 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i16_0 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i16_1 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i16_2 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i16_3 = shufflevector <8 x i16> %v2i16, <8 x i16> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = load <16 x i16>, ptr %p, align 32 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i16_0 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i16_1 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i16_2 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i16_3 = shufflevector <16 x i16> %v4i16, <16 x i16> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = load <32 x i16>, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i16_0 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i16_1 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i16_2 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %v8i16_3 = shufflevector <32 x i16> %v8i16, <32 x i16> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v16i16 = load <64 x i16>, ptr %p, align 128 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %v16i16_0 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %v16i16_1 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %v16i16_2 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %v16i16_3 = shufflevector <64 x i16> %v16i16, <64 x i16> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v2i32 = load <8 x i32>, ptr %p, align 32 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i32_0 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i32_1 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i32_2 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v2i32_3 = shufflevector <8 x i32> %v2i32, <8 x i32> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v4i32 = load <16 x i32>, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i32_0 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i32_1 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i32_2 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v4i32_3 = shufflevector <16 x i32> %v4i32, <16 x i32> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v8i32 = load <32 x i32>, ptr %p, align 128 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 132 for instruction: %v8i32_0 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 132 for instruction: %v8i32_1 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 132 for instruction: %v8i32_2 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 132 for instruction: %v8i32_3 = shufflevector <32 x i32> %v8i32, <32 x i32> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v16i32 = load <64 x i32>, ptr %p, align 256 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 264 for instruction: %v16i32_0 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 264 for instruction: %v16i32_1 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 264 for instruction: %v16i32_2 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 264 for instruction: %v16i32_3 = shufflevector <64 x i32> %v16i32, <64 x i32> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = load <8 x i64>, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_0 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 0, i32 4> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_1 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 1, i32 5> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_2 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 2, i32 6> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %v2i64_3 = shufflevector <8 x i64> %v2i64, <8 x i64> undef, <2 x i32> <i32 3, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = load <16 x i64>, ptr %p, align 128 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_0 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_1 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 1, i32 5, i32 9, i32 13> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_2 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 640 for instruction: %v4i64_3 = shufflevector <16 x i64> %v4i64, <16 x i64> undef, <4 x i32> <i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8i64 = load <32 x i64>, ptr %p, align 256 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_0 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_1 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_2 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 1280 for instruction: %v8i64_3 = shufflevector <32 x i64> %v8i64, <32 x i64> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v16i64 = load <64 x i64>, ptr %p, align 512 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_0 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_1 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 61> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_2 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30, i32 34, i32 38, i32 42, i32 46, i32 50, i32 54, i32 58, i32 62> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2560 for instruction: %v16i64_3 = shufflevector <64 x i64> %v16i64, <64 x i64> undef, <16 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31, i32 35, i32 39, i32 43, i32 47, i32 51, i32 55, i32 59, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %v2i8 = load <8 x i8>, ptr %p %v2i8_0 = shufflevector <8 x i8> %v2i8, <8 x i8> undef, <2 x i32> <i32 0, i32 4> @@ -424,29 +507,29 @@ define void @vld4(ptr %p) { define void @vst2(ptr %p) { ; CHECK-LABEL: 'vst2' -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i8> %v4i8, ptr %p, align 4 -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i8> %v16i8, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i16> %v4i16, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i16> %v8i16, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i32> %v4i32, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 ; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v4i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <4 x i64> %v4i64, ptr %p, align 32 @@ -575,40 +658,75 @@ define void @vst3(ptr %p) { define void @vst4(ptr %p) { -; CHECK-LABEL: 'vst4' -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i8> %v16i8, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <64 x i8> %v64i8, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i16> %v8i16, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <64 x i16> %v64i16, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <64 x i32> %v64i32, ptr %p, align 256 -; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <8 x i64> %v8i64, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <16 x i64> %v16i64, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <32 x i64> %v32i64, ptr %p, align 256 -; CHECK-NEXT: Cost Model: Found an estimated cost of 2048 for instruction: %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: store <64 x i64> %v64i64, ptr %p, align 512 -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-UF2-LABEL: 'vst4' +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i8> %v16i8, ptr %p, align 8 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <64 x i8> %v64i8, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i16> %v8i16, ptr %p, align 8 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <64 x i16> %v64i16, ptr %p, align 128 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <64 x i32> %v64i32, ptr %p, align 256 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <8 x i64> %v8i64, ptr %p, align 64 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <16 x i64> %v16i64, ptr %p, align 128 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <32 x i64> %v32i64, ptr %p, align 256 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 2048 for instruction: %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 64 for instruction: store <64 x i64> %v64i64, ptr %p, align 512 +; CHECK-UF2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; CHECK-UF4-LABEL: 'vst4' +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i8> %v16i8, ptr %p, align 8 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <64 x i8> %v64i8, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i16> %v8i16, ptr %p, align 8 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <64 x i16> %v64i16, ptr %p, align 128 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <64 x i32> %v64i32, ptr %p, align 256 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <8 x i64> %v8i64, ptr %p, align 64 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <16 x i64> %v16i64, ptr %p, align 128 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <32 x i64> %v32i64, ptr %p, align 256 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 2048 for instruction: %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> <i32 0, i32 16, i32 32, i32 48, i32 1, i32 17, i32 33, i32 49, i32 2, i32 18, i32 34, i32 50, i32 3, i32 19, i32 35, i32 51, i32 4, i32 20, i32 36, i32 52, i32 5, i32 21, i32 37, i32 53, i32 6, i32 22, i32 38, i32 54, i32 7, i32 23, i32 39, i32 55, i32 8, i32 24, i32 40, i32 56, i32 9, i32 25, i32 41, i32 57, i32 10, i32 26, i32 42, i32 58, i32 11, i32 27, i32 43, i32 59, i32 12, i32 28, i32 44, i32 60, i32 13, i32 29, i32 45, i32 61, i32 14, i32 30, i32 46, i32 62, i32 15, i32 31, i32 47, i32 63> +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 64 for instruction: store <64 x i64> %v64i64, ptr %p, align 512 +; CHECK-UF4-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7> store <8 x i8> %v8i8, ptr %p @@ -648,6 +766,3 @@ define void @vst4(ptr %p) { ret void } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK-UF2: {{.*}} -; CHECK-UF4: {{.*}} diff --git a/llvm/test/Bindings/llvm-c/add_globaldebuginfo.ll b/llvm/test/Bindings/llvm-c/add_globaldebuginfo.ll new file mode 100644 index 000000000000..da6536a9ce40 --- /dev/null +++ b/llvm/test/Bindings/llvm-c/add_globaldebuginfo.ll @@ -0,0 +1,2 @@ +; RUN: llvm-c-test --add-globaldebuginfo < /dev/null +; This used to trigger an assertion diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll index d2f72ecacc86..20f19fddf790 100644 --- a/llvm/test/CodeGen/AArch64/bitcast.ll +++ b/llvm/test/CodeGen/AArch64/bitcast.ll @@ -617,6 +617,31 @@ define <8 x i64> @bitcast_v16i32_v8i64(<16 x i32> %a, <16 x i32> %b){ ret <8 x i64> %d } +define <8 x i32> @scalar_i128(<2 x i128> %a) { +; CHECK-SD-LABEL: scalar_i128: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: fmov d1, x2 +; CHECK-SD-NEXT: fmov d0, x0 +; CHECK-SD-NEXT: mov v1.d[1], x3 +; CHECK-SD-NEXT: mov v0.d[1], x1 +; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s +; CHECK-SD-NEXT: add v1.4s, v1.4s, v1.4s +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: scalar_i128: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov v0.d[0], x0 +; CHECK-GI-NEXT: mov v1.d[0], x2 +; CHECK-GI-NEXT: mov v0.d[1], x1 +; CHECK-GI-NEXT: mov v1.d[1], x3 +; CHECK-GI-NEXT: add v0.4s, v0.4s, v0.4s +; CHECK-GI-NEXT: add v1.4s, v1.4s, v1.4s +; CHECK-GI-NEXT: ret + %c = bitcast <2 x i128> %a to <8 x i32> + %d = add <8 x i32> %c, %c + ret <8 x i32> %d +} + ; ===== Vectors with Non-Pow 2 Widths ===== define <6 x i16> @bitcast_v3i32_v6i16(<3 x i32> %a, <3 x i32> %b){ diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir index a70708134a12..57b7a822ed7a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir @@ -2,6 +2,103 @@ # RUN: llc -mtriple=amdgcn -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s --- +name: gep_p0_s_k +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + + ; CHECK-LABEL: name: gep_p0_s_k + ; CHECK: liveins: $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p0) = G_PTR_ADD [[COPY]], [[C]](s64) + %0:_(p0) = COPY $sgpr0_sgpr1 + %1:_(s64) = G_CONSTANT i64 1 + %2:_(p0) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p0_s_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + + ; CHECK-LABEL: name: gep_p0_s_s + ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64) + %0:_(p0) = COPY $sgpr0_sgpr1 + %1:_(s64) = COPY $sgpr2_sgpr3 + %2:_(p0) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p0_v_k +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + + ; CHECK-LABEL: name: gep_p0_v_k + ; CHECK: liveins: $vgpr0_vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64) + %0:_(p0) = COPY $vgpr0_vgpr1 + %1:_(s64) = G_CONSTANT i64 1 + %2:_(p0) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p0_v_s +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $sgpr0_sgpr1 + + ; CHECK-LABEL: name: gep_p0_v_s + ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p0) = G_PTR_ADD [[COPY]], [[COPY2]](s64) + %0:_(p0) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $sgpr0_sgpr1 + %2:_(p0) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p0_v_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + ; CHECK-LABEL: name: gep_p0_v_v + ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64) + %0:_(p0) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(p0) = G_PTR_ADD %0, %1 +... + +--- name: gep_p1_s_k legalized: true @@ -97,3 +194,294 @@ body: | %1:_(s64) = COPY $vgpr2_vgpr3 %2:_(p1) = G_PTR_ADD %0, %1 ... + +--- +name: gep_p3_s_k +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + + ; CHECK-LABEL: name: gep_p3_s_k + ; CHECK: liveins: $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p3) = G_PTR_ADD [[COPY]], [[C]](s32) + %0:_(p3) = COPY $sgpr0 + %1:_(s32) = G_CONSTANT i32 1 + %2:_(p3) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p3_s_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + + ; CHECK-LABEL: name: gep_p3_s_s + ; CHECK: liveins: $sgpr0, $sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p3) = G_PTR_ADD [[COPY]], [[COPY1]](s32) + %0:_(p3) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:_(p3) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p3_v_k +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: gep_p3_v_k + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY]], [[COPY1]](s32) + %0:_(p3) = COPY $vgpr0 + %1:_(s32) = G_CONSTANT i32 1 + %2:_(p3) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p3_v_s +legalized: true + +body: | + bb.0: + liveins: $vgpr0, $sgpr0 + + ; CHECK-LABEL: name: gep_p3_v_s + ; CHECK: liveins: $vgpr0, $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY]], [[COPY2]](s32) + %0:_(p3) = COPY $vgpr0 + %1:_(s32) = COPY $sgpr0 + %2:_(p3) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p3_v_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: gep_p3_v_v + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY]], [[COPY1]](s32) + %0:_(p3) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p3) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p4_s_k +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + + ; CHECK-LABEL: name: gep_p4_s_k + ; CHECK: liveins: $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64) + %0:_(p4) = COPY $sgpr0_sgpr1 + %1:_(s64) = G_CONSTANT i64 1 + %2:_(p4) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p4_s_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + + ; CHECK-LABEL: name: gep_p4_s_s + ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[COPY1]](s64) + %0:_(p4) = COPY $sgpr0_sgpr1 + %1:_(s64) = COPY $sgpr2_sgpr3 + %2:_(p4) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p4_v_k +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1 + + ; CHECK-LABEL: name: gep_p4_v_k + ; CHECK: liveins: $vgpr0_vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p4) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[COPY1]](s64) + %0:_(p4) = COPY $vgpr0_vgpr1 + %1:_(s64) = G_CONSTANT i64 1 + %2:_(p4) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p4_v_s +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $sgpr0_sgpr1 + + ; CHECK-LABEL: name: gep_p4_v_s + ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p4) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[COPY2]](s64) + %0:_(p4) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $sgpr0_sgpr1 + %2:_(p4) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p4_v_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + ; CHECK-LABEL: name: gep_p4_v_v + ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p4) = COPY $vgpr0_vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[COPY1]](s64) + %0:_(p4) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(p4) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p5_s_k +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + + ; CHECK-LABEL: name: gep_p5_s_k + ; CHECK: liveins: $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[C]](s32) + %0:_(p5) = COPY $sgpr0 + %1:_(s32) = G_CONSTANT i32 1 + %2:_(p5) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p5_s_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + + ; CHECK-LABEL: name: gep_p5_s_s + ; CHECK: liveins: $sgpr0, $sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[COPY1]](s32) + %0:_(p5) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:_(p5) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p5_v_k +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: gep_p5_v_k + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p5) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p5) = G_PTR_ADD [[COPY]], [[COPY1]](s32) + %0:_(p5) = COPY $vgpr0 + %1:_(s32) = G_CONSTANT i32 1 + %2:_(p5) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p5_v_s +legalized: true + +body: | + bb.0: + liveins: $vgpr0, $sgpr0 + + ; CHECK-LABEL: name: gep_p5_v_s + ; CHECK: liveins: $vgpr0, $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p5) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p5) = G_PTR_ADD [[COPY]], [[COPY2]](s32) + %0:_(p5) = COPY $vgpr0 + %1:_(s32) = COPY $sgpr0 + %2:_(p5) = G_PTR_ADD %0, %1 +... + +--- +name: gep_p5_v_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; CHECK-LABEL: name: gep_p5_v_v + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p5) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p5) = G_PTR_ADD [[COPY]], [[COPY1]](s32) + %0:_(p5) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p5) = G_PTR_ADD %0, %1 +... diff --git a/llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll b/llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll index 9f7f228297d4..535e02cf80c2 100644 --- a/llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll +++ b/llvm/test/CodeGen/AMDGPU/inlineasm-illegal-type.ll @@ -18,6 +18,12 @@ define amdgpu_kernel void @v_input_output_i8() { ret void } +; GCN: error: couldn't allocate input reg for constraint 'v' +define amdgpu_kernel void @v_input_empty_struct() { + call void asm "", "v"({} poison) + ret void +} + ; SICI: error: couldn't allocate output register for constraint 's' ; SICI: error: couldn't allocate input reg for constraint 's' ; VI-NOT: error diff --git a/llvm/test/CodeGen/AMDGPU/unify-metadata.ll b/llvm/test/CodeGen/AMDGPU/unify-metadata.ll deleted file mode 100644 index 455993b16145..000000000000 --- a/llvm/test/CodeGen/AMDGPU/unify-metadata.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: opt -mtriple=amdgcn--amdhsa -passes=amdgpu-unify-metadata -S < %s | FileCheck -check-prefix=ALL %s -; RUN: opt -mtriple=amdgcn--amdhsa -passes=amdgpu-unify-metadata -S < %s | FileCheck -check-prefix=ALL %s - -; This test check that we have a singe metadata value after linking several -; modules for records such as opencl.ocl.version, llvm.ident and similar. - -; ALL-DAG: !opencl.ocl.version = !{![[OCL_VER:[0-9]+]]} -; ALL-DAG: !llvm.ident = !{![[LLVM_IDENT_0:[0-9]+]], ![[LLVM_IDENT_1:[0-9]+]]} -; ALL-DAG: !opencl.used.extensions = !{![[USED_EXT_0:[0-9]+]], ![[USED_EXT_1:[0-9]+]], ![[USED_EXT_2:[0-9]+]]} - -; ALL-DAG: ![[OCL_VER]] = !{i32 1, i32 2} -; ALL-DAG: ![[LLVM_IDENT_0]] = !{!"clang version 4.0"} -; ALL-DAG: ![[LLVM_IDENT_1]] = !{!"clang version 4.0 (rLXXXXXX)"} -; ALL-DAG: ![[USED_EXT_0]] = !{!"cl_images"} -; ALL-DAG: ![[USED_EXT_1]] = !{!"cl_khr_fp16"} -; ALL-DAG: ![[USED_EXT_2]] = !{!"cl_doubles"} - -!opencl.ocl.version = !{!1, !0, !0, !0} -!llvm.ident = !{!2, !2, !2, !2, !6} -!opencl.used.extensions = !{!3, !3, !4, !5} - -!0 = !{i32 2, i32 0} -!1 = !{i32 1, i32 2} -!2 = !{!"clang version 4.0"} -!3 = !{!"cl_images", !"cl_khr_fp16"} -!4 = !{!"cl_images", !"cl_doubles"} -!5 = !{} -!6 = !{!"clang version 4.0 (rLXXXXXX)"} diff --git a/llvm/test/CodeGen/ARM/vtrn.ll b/llvm/test/CodeGen/ARM/vtrn.ll index 136fec3ac316..63774694f8a9 100644 --- a/llvm/test/CodeGen/ARM/vtrn.ll +++ b/llvm/test/CodeGen/ARM/vtrn.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s define <8 x i8> @vtrni8(ptr %A, ptr %B) nounwind { @@ -20,11 +21,11 @@ define <8 x i8> @vtrni8(ptr %A, ptr %B) nounwind { define <16 x i8> @vtrni8_Qres(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: vtrni8_Qres: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] -; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] -; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]] -; CHECK-NEXT: vmov r0, r1, [[LDR0]] -; CHECK-NEXT: vmov r2, r3, [[LDR1]] +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d17, [r0] +; CHECK-NEXT: vtrn.8 d17, d16 +; CHECK-NEXT: vmov r0, r1, d17 +; CHECK-NEXT: vmov r2, r3, d16 ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, ptr %A %tmp2 = load <8 x i8>, ptr %B @@ -52,11 +53,11 @@ define <4 x i16> @vtrni16(ptr %A, ptr %B) nounwind { define <8 x i16> @vtrni16_Qres(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: vtrni16_Qres: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] -; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] -; CHECK-NEXT: vtrn.16 [[LDR0]], [[LDR1]] -; CHECK-NEXT: vmov r0, r1, [[LDR0]] -; CHECK-NEXT: vmov r2, r3, [[LDR1]] +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d17, [r0] +; CHECK-NEXT: vtrn.16 d17, d16 +; CHECK-NEXT: vmov r0, r1, d17 +; CHECK-NEXT: vmov r2, r3, d16 ; CHECK-NEXT: mov pc, lr %tmp1 = load <4 x i16>, ptr %A %tmp2 = load <4 x i16>, ptr %B @@ -84,11 +85,11 @@ define <2 x i32> @vtrni32(ptr %A, ptr %B) nounwind { define <4 x i32> @vtrni32_Qres(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: vtrni32_Qres: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] -; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] -; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]] -; CHECK-NEXT: vmov r0, r1, [[LDR0]] -; CHECK-NEXT: vmov r2, r3, [[LDR1]] +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d17, [r0] +; CHECK-NEXT: vtrn.32 d17, d16 +; CHECK-NEXT: vmov r0, r1, d17 +; CHECK-NEXT: vmov r2, r3, d16 ; CHECK-NEXT: mov pc, lr %tmp1 = load <2 x i32>, ptr %A %tmp2 = load <2 x i32>, ptr %B @@ -116,11 +117,11 @@ define <2 x float> @vtrnf(ptr %A, ptr %B) nounwind { define <4 x float> @vtrnf_Qres(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: vtrnf_Qres: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] -; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] -; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]] -; CHECK-NEXT: vmov r0, r1, [[LDR0]] -; CHECK-NEXT: vmov r2, r3, [[LDR1]] +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d17, [r0] +; CHECK-NEXT: vtrn.32 d17, d16 +; CHECK-NEXT: vmov r0, r1, d17 +; CHECK-NEXT: vmov r2, r3, d16 ; CHECK-NEXT: mov pc, lr %tmp1 = load <2 x float>, ptr %A %tmp2 = load <2 x float>, ptr %B @@ -281,11 +282,11 @@ define <8 x i8> @vtrni8_undef(ptr %A, ptr %B) nounwind { define <16 x i8> @vtrni8_undef_Qres(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: vtrni8_undef_Qres: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] -; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] -; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]] -; CHECK-NEXT: vmov r0, r1, [[LDR0]] -; CHECK-NEXT: vmov r2, r3, [[LDR1]] +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d17, [r0] +; CHECK-NEXT: vtrn.8 d17, d16 +; CHECK-NEXT: vmov r0, r1, d17 +; CHECK-NEXT: vmov r2, r3, d16 ; CHECK-NEXT: mov pc, lr %tmp1 = load <8 x i8>, ptr %A %tmp2 = load <8 x i8>, ptr %B @@ -327,9 +328,15 @@ define <16 x i16> @vtrnQi16_undef_QQres(ptr %A, ptr %B) nounwind { } define <8 x i16> @vtrn_lower_shufflemask_undef(ptr %A, ptr %B) { +; CHECK-LABEL: vtrn_lower_shufflemask_undef: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d17, [r0] +; CHECK-NEXT: vtrn.16 d17, d16 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: vmov r2, r3, d16 +; CHECK-NEXT: mov pc, lr entry: - ; CHECK-LABEL: vtrn_lower_shufflemask_undef - ; CHECK: vtrn %tmp1 = load <4 x i16>, ptr %A %tmp2 = load <4 x i16>, ptr %B %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 5, i32 3, i32 7> @@ -340,12 +347,26 @@ entry: ; values do modify the type. However, we get different input types, as some of ; them get truncated from i32 to i8 (from comparing cmp0 with cmp1) and some of ; them get truncated from i16 to i8 (from comparing cmp2 with cmp3). -define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1, - <4 x i32> %cmp0, <4 x i32> %cmp1, - <4 x i16> %cmp2, <4 x i16> %cmp3) { - ; CHECK-LABEL: vtrn_mismatched_builvector0: - ; CHECK: vmovn.i32 - ; CHECK: vbsl +define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1, <4 x i32> %cmp0, <4 x i32> %cmp1, <4 x i16> %cmp2, <4 x i16> %cmp3) { +; CHECK-LABEL: vtrn_mismatched_builvector0: +; CHECK: @ %bb.0: +; CHECK-NEXT: mov r12, sp +; CHECK-NEXT: vld1.64 {d16, d17}, [r12] +; CHECK-NEXT: add r12, sp, #16 +; CHECK-NEXT: vld1.64 {d18, d19}, [r12] +; CHECK-NEXT: vcgt.u32 q8, q9, q8 +; CHECK-NEXT: vldr d20, [sp, #32] +; CHECK-NEXT: vldr d18, [sp, #40] +; CHECK-NEXT: vcgt.u16 d18, d18, d20 +; CHECK-NEXT: vmovn.i32 d16, q8 +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vtrn.8 d16, d18 +; CHECK-NEXT: vmov d18, r0, r1 +; CHECK-NEXT: vshl.i8 d16, d16, #7 +; CHECK-NEXT: vshr.s8 d16, d16, #7 +; CHECK-NEXT: vbsl d16, d18, d17 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: mov pc, lr %c0 = icmp ult <4 x i32> %cmp0, %cmp1 %c1 = icmp ult <4 x i16> %cmp2, %cmp3 %c = shufflevector <4 x i1> %c0, <4 x i1> %c1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> @@ -356,12 +377,30 @@ define <8 x i8> @vtrn_mismatched_builvector0(<8 x i8> %tr0, <8 x i8> %tr1, ; Here we get a build_vector node, where half the incoming extract_element ; values do not modify the type (the values form cmp2), but half of them do ; (from the icmp operation). -define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1, - <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) { - ; CHECK-LABEL: vtrn_mismatched_builvector1: - ; We need to extend the 4 x i8 to 4 x i16 in order to perform the vtrn - ; CHECK: vmovl - ; CHECK: vbsl +; We need to extend the 4 x i8 to 4 x i16 in order to perform the vtrn +define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1, <4 x i32> %cmp0, <4 x i32> %cmp1, ptr %cmp2_ptr) { +; CHECK-LABEL: vtrn_mismatched_builvector1: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: add r12, sp, #8 +; CHECK-NEXT: add lr, sp, #24 +; CHECK-NEXT: vld1.64 {d16, d17}, [r12] +; CHECK-NEXT: ldr r12, [sp, #40] +; CHECK-NEXT: vld1.64 {d18, d19}, [lr] +; CHECK-NEXT: vcgt.u32 q8, q9, q8 +; CHECK-NEXT: vld1.32 {d18[0]}, [r12:32] +; CHECK-NEXT: vmovl.u8 q9, d18 +; CHECK-NEXT: vmovn.i32 d16, q8 +; CHECK-NEXT: vmov d17, r2, r3 +; CHECK-NEXT: vtrn.8 d16, d18 +; CHECK-NEXT: vmov d18, r0, r1 +; CHECK-NEXT: vshl.i8 d16, d16, #7 +; CHECK-NEXT: vshr.s8 d16, d16, #7 +; CHECK-NEXT: vbsl d16, d18, d17 +; CHECK-NEXT: vmov r0, r1, d16 +; CHECK-NEXT: pop {r11, lr} +; CHECK-NEXT: mov pc, lr %cmp2_load = load <4 x i8>, ptr %cmp2_ptr, align 4 %cmp2 = trunc <4 x i8> %cmp2_load to <4 x i1> %c0 = icmp ult <4 x i32> %cmp0, %cmp1 @@ -373,15 +412,15 @@ define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1, ; The shuffle mask is half a vtrn; we duplicate the half to produce the ; full result. define void @lower_twice_no_vtrn(ptr %A, ptr %B, ptr %C) { +; CHECK-LABEL: lower_twice_no_vtrn: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d18, [r0] +; CHECK-NEXT: vtrn.16 d18, d16 +; CHECK-NEXT: vorr d17, d16, d16 +; CHECK-NEXT: vst1.64 {d16, d17}, [r2] +; CHECK-NEXT: mov pc, lr entry: - ; CHECK-LABEL: lower_twice_no_vtrn: - ; CHECK: @ %bb.0: - ; CHECK-NEXT: vldr d16, [r1] - ; CHECK-NEXT: vldr d18, [r0] - ; CHECK-NEXT: vtrn.16 d18, d16 - ; CHECK-NEXT: vorr d17, d16, d16 - ; CHECK-NEXT: vst1.64 {d16, d17}, [r2] - ; CHECK-NEXT: mov pc, lr %tmp1 = load <4 x i16>, ptr %A %tmp2 = load <4 x i16>, ptr %B %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 5, i32 3, i32 7, i32 1, i32 5, i32 3, i32 7> @@ -392,18 +431,49 @@ entry: ; The shuffle mask is half a vtrn; we duplicate the half to produce the ; full result. define void @upper_twice_no_vtrn(ptr %A, ptr %B, ptr %C) { +; CHECK-LABEL: upper_twice_no_vtrn: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vldr d16, [r1] +; CHECK-NEXT: vldr d18, [r0] +; CHECK-NEXT: vtrn.16 d18, d16 +; CHECK-NEXT: vorr d19, d18, d18 +; CHECK-NEXT: vst1.64 {d18, d19}, [r2] +; CHECK-NEXT: mov pc, lr entry: - ; CHECK-LABEL: upper_twice_no_vtrn: - ; CHECK: @ %bb.0: - ; CHECK-NEXT: vldr d16, [r1] - ; CHECK-NEXT: vldr d18, [r0] - ; CHECK-NEXT: vtrn.16 d18, d16 - ; CHECK-NEXT: vorr d19, d18, d18 - ; CHECK-NEXT: vst1.64 {d18, d19}, [r2] - ; CHECK-NEXT: mov pc, lr %tmp1 = load <4 x i16>, ptr %A %tmp2 = load <4 x i16>, ptr %B %0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 6, i32 0, i32 4, i32 2, i32 6> store <8 x i16> %0, ptr %C ret void } + +define void @test_15xi16(ptr %next.gep, ptr %next.gep13) { +; CHECK-LABEL: test_15xi16: +; CHECK: @ %bb.0: +; CHECK-NEXT: add r2, r0, #2 +; CHECK-NEXT: add r3, r0, #6 +; CHECK-NEXT: vld1.16 {d16, d17}, [r2]! +; CHECK-NEXT: vld1.16 {d18}, [r2]! +; CHECK-NEXT: vld1.16 {d20, d21}, [r3]! +; CHECK-NEXT: ldr r2, [r2] +; CHECK-NEXT: vld1.16 {d22}, [r3]! +; CHECK-NEXT: vmov.16 d19[0], r2 +; CHECK-NEXT: ldr r3, [r3] +; CHECK-NEXT: add r2, r0, #30 +; CHECK-NEXT: add r0, r0, #34 +; CHECK-NEXT: vmov.16 d19[1], r3 +; CHECK-NEXT: vld1.16 {d19[2]}, [r2:16] +; CHECK-NEXT: vtrn.16 q8, q10 +; CHECK-NEXT: vld1.16 {d19[3]}, [r0:16] +; CHECK-NEXT: vtrn.16 d18, d22 +; CHECK-NEXT: vst1.16 {d16, d17}, [r1]! +; CHECK-NEXT: vst1.16 {d18, d19}, [r1] +; CHECK-NEXT: mov pc, lr + %a = getelementptr inbounds nuw i8, ptr %next.gep, i32 2 + %b = load <15 x i16>, ptr %a, align 2 + %c = getelementptr inbounds nuw i8, ptr %next.gep, i32 6 + %d = load <15 x i16>, ptr %c, align 2 + %interleaved.vec = shufflevector <15 x i16> %b, <15 x i16> %d, <16 x i32> <i32 0, i32 15, i32 2, i32 17, i32 4, i32 19, i32 6, i32 21, i32 8, i32 23, i32 10, i32 25, i32 12, i32 27, i32 14, i32 29> + store <16 x i16> %interleaved.vec, ptr %next.gep13, align 2 + ret void +} diff --git a/llvm/test/CodeGen/ARM/vuzp.ll b/llvm/test/CodeGen/ARM/vuzp.ll index 7e1dfba34db2..d24dadc7fc40 100644 --- a/llvm/test/CodeGen/ARM/vuzp.ll +++ b/llvm/test/CodeGen/ARM/vuzp.ll @@ -535,3 +535,59 @@ define %struct.uint8x8x2_t @vuzp_extract_subvector(<16 x i8> %t) #0 { %.fca.0.1.insert = insertvalue %struct.uint8x8x2_t %.fca.0.0.insert, <8 x i8> %vuzp1.i, 0, 1 ret %struct.uint8x8x2_t %.fca.0.1.insert } + +define void @test_15xi16(ptr %next.gep, ptr %next.gep13) { +; CHECK-LABEL: test_15xi16: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r4, r5, r6, lr} +; CHECK-NEXT: push {r4, r5, r6, lr} +; CHECK-NEXT: add r2, r0, #2 +; CHECK-NEXT: add r3, r0, #6 +; CHECK-NEXT: vld1.16 {d20, d21}, [r2]! +; CHECK-NEXT: vld1.16 {d16}, [r2]! +; CHECK-NEXT: vmov.u16 r12, d16[0] +; CHECK-NEXT: ldr r2, [r2] +; CHECK-NEXT: vmov.u16 r4, d20[0] +; CHECK-NEXT: vld1.16 {d22, d23}, [r3]! +; CHECK-NEXT: vld1.16 {d24}, [r3]! +; CHECK-NEXT: vmov.u16 lr, d16[2] +; CHECK-NEXT: vmov.u16 r5, d22[0] +; CHECK-NEXT: vmov.u16 r6, d21[0] +; CHECK-NEXT: vmov.16 d17[0], r12 +; CHECK-NEXT: vmov.16 d16[0], r4 +; CHECK-NEXT: vmov.u16 r4, d24[0] +; CHECK-NEXT: vmov.u16 r12, d24[2] +; CHECK-NEXT: vmov.16 d17[1], lr +; CHECK-NEXT: vmov.16 d18[0], r5 +; CHECK-NEXT: vmov.u16 r5, d20[2] +; CHECK-NEXT: vmov.u16 lr, d23[0] +; CHECK-NEXT: vmov.16 d19[0], r4 +; CHECK-NEXT: vmov.u16 r4, d22[2] +; CHECK-NEXT: vmov.16 d16[1], r5 +; CHECK-NEXT: vmov.u16 r5, d21[2] +; CHECK-NEXT: vmov.16 d17[2], r2 +; CHECK-NEXT: ldr r2, [r3] +; CHECK-NEXT: vmov.16 d16[2], r6 +; CHECK-NEXT: vmov.16 d18[1], r4 +; CHECK-NEXT: vmov.u16 r4, d23[2] +; CHECK-NEXT: vmov.16 d19[1], r12 +; CHECK-NEXT: vmov.16 d18[2], lr +; CHECK-NEXT: vmov.16 d19[2], r2 +; CHECK-NEXT: add r2, r0, #30 +; CHECK-NEXT: add r0, r0, #34 +; CHECK-NEXT: vld1.16 {d17[3]}, [r2:16] +; CHECK-NEXT: vmov.16 d16[3], r5 +; CHECK-NEXT: vmov.16 d18[3], r4 +; CHECK-NEXT: vld1.16 {d19[3]}, [r0:16] +; CHECK-NEXT: vst1.16 {d16, d17}, [r1]! +; CHECK-NEXT: vst1.16 {d18, d19}, [r1] +; CHECK-NEXT: pop {r4, r5, r6, lr} +; CHECK-NEXT: mov pc, lr + %a = getelementptr inbounds nuw i8, ptr %next.gep, i32 2 + %b = load <15 x i16>, ptr %a, align 2 + %c = getelementptr inbounds nuw i8, ptr %next.gep, i32 6 + %d = load <15 x i16>, ptr %c, align 2 + %interleaved.vec = shufflevector <15 x i16> %b, <15 x i16> %d, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29> + store <16 x i16> %interleaved.vec, ptr %next.gep13, align 2 + ret void +} diff --git a/llvm/test/CodeGen/ARM/vzip.ll b/llvm/test/CodeGen/ARM/vzip.ll index dda774abd851..ce40a2e48b6e 100644 --- a/llvm/test/CodeGen/ARM/vzip.ll +++ b/llvm/test/CodeGen/ARM/vzip.ll @@ -381,3 +381,22 @@ entry: %vzip.i = shufflevector <8 x i8> %lane, <8 x i8> %lane3, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> ret <8 x i8> %vzip.i } + +define <16 x i16> @test_15xi16(ptr %next.gep, ptr %next.gep13) { +; CHECK-LABEL: test_15xi16: +; CHECK: @ %bb.0: +; CHECK-NEXT: add r1, r1, #2 +; CHECK-NEXT: mov r2, #4 +; CHECK-NEXT: vld1.16 {d16, d17}, [r1], r2 +; CHECK-NEXT: vld1.16 {d18, d19}, [r1] +; CHECK-NEXT: vzip.16 q8, q9 +; CHECK-NEXT: vst1.16 {d16, d17}, [r0:128]! +; CHECK-NEXT: vst1.64 {d18, d19}, [r0:128] +; CHECK-NEXT: mov pc, lr + %a = getelementptr inbounds nuw i8, ptr %next.gep, i32 2 + %b = load <15 x i16>, ptr %a, align 2 + %c = getelementptr inbounds nuw i8, ptr %next.gep, i32 6 + %d = load <15 x i16>, ptr %c, align 2 + %interleaved.vec = shufflevector <15 x i16> %b, <15 x i16> %d, <16 x i32> <i32 0, i32 15, i32 1, i32 16, i32 2, i32 17, i32 3, i32 18, i32 4, i32 19, i32 5, i32 20, i32 6, i32 21, i32 7, i32 22> + ret <16 x i16> %interleaved.vec +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll index ac5a2143451d..c074bfecf95b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll @@ -30,8 +30,8 @@ entry: define <8 x i32> @insert_extract_v8i32(<8 x i32> %a) nounwind { ; CHECK-LABEL: insert_extract_v8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7 -; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 1 +; CHECK-NEXT: xvpickve.w $xr1, $xr0, 7 +; CHECK-NEXT: xvinsve0.w $xr0, $xr1, 1 ; CHECK-NEXT: ret entry: %b = extractelement <8 x i32> %a, i32 7 @@ -39,6 +39,18 @@ entry: ret <8 x i32> %c } + +define <8 x i32> @insert_extract0_v8i32(<8 x i32> %a) nounwind { +; CHECK-LABEL: insert_extract0_v8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvinsve0.w $xr0, $xr0, 1 +; CHECK-NEXT: ret +entry: + %b = extractelement <8 x i32> %a, i32 0 + %c = insertelement <8 x i32> %a, i32 %b, i32 1 + ret <8 x i32> %c +} + define <8 x float> @insert_extract_v8f32(<8 x float> %a) nounwind { ; CHECK-LABEL: insert_extract_v8f32: ; CHECK: # %bb.0: # %entry @@ -54,8 +66,8 @@ entry: define <4 x i64> @insert_extract_v4i64(<4 x i64> %a) nounwind { ; CHECK-LABEL: insert_extract_v4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 3 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 1 +; CHECK-NEXT: xvpickve.d $xr1, $xr0, 3 +; CHECK-NEXT: xvinsve0.d $xr0, $xr1, 1 ; CHECK-NEXT: ret entry: %b = extractelement <4 x i64> %a, i32 3 @@ -63,6 +75,17 @@ entry: ret <4 x i64> %c } +define <4 x i64> @insert_extract0_v4i64(<4 x i64> %a) nounwind { +; CHECK-LABEL: insert_extract0_v4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvinsve0.d $xr0, $xr0, 1 +; CHECK-NEXT: ret +entry: + %b = extractelement <4 x i64> %a, i32 0 + %c = insertelement <4 x i64> %a, i64 %b, i32 1 + ret <4 x i64> %c +} + define <4 x double> @insert_extract_v4f64(<4 x double> %a) nounwind { ; CHECK-LABEL: insert_extract_v4f64: ; CHECK: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll b/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll index 80627a03354a..e1d4ef1073a7 100644 --- a/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll +++ b/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx71 --enable-unsafe-fp-math | FileCheck --check-prefixes=CHECK %s -; RUN: %if ptxas-11.8 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx71 --enable-unsafe-fp-math | %ptxas-verify -arch=sm_80 %} +; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx71 | FileCheck --check-prefixes=CHECK %s +; RUN: %if ptxas-11.8 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_80 -mattr=+ptx71 | %ptxas-verify -arch=sm_80 %} target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" @@ -22,7 +22,7 @@ define <2 x bfloat> @test_sin(<2 x bfloat> %a) #0 #1 { ; CHECK-NEXT: cvt.rn.bf16x2.f32 %r5, %r4, %r2; ; CHECK-NEXT: st.param.b32 [func_retval0], %r5; ; CHECK-NEXT: ret; - %r = call <2 x bfloat> @llvm.sin.f16(<2 x bfloat> %a) + %r = call afn <2 x bfloat> @llvm.sin.f16(<2 x bfloat> %a) ret <2 x bfloat> %r } @@ -41,7 +41,7 @@ define <2 x bfloat> @test_cos(<2 x bfloat> %a) #0 #1 { ; CHECK-NEXT: cvt.rn.bf16x2.f32 %r5, %r4, %r2; ; CHECK-NEXT: st.param.b32 [func_retval0], %r5; ; CHECK-NEXT: ret; - %r = call <2 x bfloat> @llvm.cos.f16(<2 x bfloat> %a) + %r = call afn <2 x bfloat> @llvm.cos.f16(<2 x bfloat> %a) ret <2 x bfloat> %r } diff --git a/llvm/test/CodeGen/NVPTX/f16-instructions.ll b/llvm/test/CodeGen/NVPTX/f16-instructions.ll index 2b7e4184670c..d4aec4f16f1a 100644 --- a/llvm/test/CodeGen/NVPTX/f16-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/f16-instructions.ll @@ -886,8 +886,8 @@ define half @test_sqrt(half %a) #0 { ; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]]; ; CHECK: st.param.b16 [func_retval0], [[R]]; ; CHECK: ret; -define half @test_sin(half %a) #0 #1 { - %r = call half @llvm.sin.f16(half %a) +define half @test_sin(half %a) #0 { + %r = call afn half @llvm.sin.f16(half %a) ret half %r } @@ -900,8 +900,8 @@ define half @test_sin(half %a) #0 #1 { ; CHECK: cvt.rn.f16.f32 [[R:%rs[0-9]+]], [[RF]]; ; CHECK: st.param.b16 [func_retval0], [[R]]; ; CHECK: ret; -define half @test_cos(half %a) #0 #1 { - %r = call half @llvm.cos.f16(half %a) +define half @test_cos(half %a) #0 { + %r = call afn half @llvm.cos.f16(half %a) ret half %r } @@ -1183,4 +1183,3 @@ define <2 x half> @test_neg_f16x2(<2 x half> noundef %arg) #0 { } attributes #0 = { nounwind } -attributes #1 = { "unsafe-fp-math" = "true" } diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll index d4fcea320f3a..991311f9492b 100644 --- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll @@ -1674,7 +1674,7 @@ define <2 x half> @test_sqrt(<2 x half> %a) #0 { ; ret <2 x half> %r ;} -define <2 x half> @test_sin(<2 x half> %a) #0 #1 { +define <2 x half> @test_sin(<2 x half> %a) #0 { ; CHECK-LABEL: test_sin( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<5>; @@ -1692,11 +1692,11 @@ define <2 x half> @test_sin(<2 x half> %a) #0 #1 { ; CHECK-NEXT: mov.b32 %r6, {%rs4, %rs3}; ; CHECK-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-NEXT: ret; - %r = call <2 x half> @llvm.sin.f16(<2 x half> %a) + %r = call afn <2 x half> @llvm.sin.f16(<2 x half> %a) ret <2 x half> %r } -define <2 x half> @test_cos(<2 x half> %a) #0 #1 { +define <2 x half> @test_cos(<2 x half> %a) #0 { ; CHECK-LABEL: test_cos( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<5>; @@ -1714,7 +1714,7 @@ define <2 x half> @test_cos(<2 x half> %a) #0 #1 { ; CHECK-NEXT: mov.b32 %r6, {%rs4, %rs3}; ; CHECK-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-NEXT: ret; - %r = call <2 x half> @llvm.cos.f16(<2 x half> %a) + %r = call afn <2 x half> @llvm.cos.f16(<2 x half> %a) ret <2 x half> %r } @@ -2330,4 +2330,3 @@ define void @test_store_2xhalf(ptr %p1, ptr %p2, <2 x half> %v) { attributes #0 = { nounwind } -attributes #1 = { "unsafe-fp-math" = "true" } diff --git a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll index 47b7c9a09be4..467459759c42 100644 --- a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll @@ -1638,7 +1638,7 @@ define <2 x float> @test_sqrt(<2 x float> %a) #0 { ; ret <2 x float> %r ;} -define <2 x float> @test_sin(<2 x float> %a) #0 #1 { +define <2 x float> @test_sin(<2 x float> %a) #0 { ; CHECK-LABEL: test_sin( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -1651,11 +1651,11 @@ define <2 x float> @test_sin(<2 x float> %a) #0 #1 { ; CHECK-NEXT: sin.approx.f32 %r4, %r1; ; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3}; ; CHECK-NEXT: ret; - %r = call <2 x float> @llvm.sin(<2 x float> %a) + %r = call afn <2 x float> @llvm.sin(<2 x float> %a) ret <2 x float> %r } -define <2 x float> @test_cos(<2 x float> %a) #0 #1 { +define <2 x float> @test_cos(<2 x float> %a) #0 { ; CHECK-LABEL: test_cos( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -1668,7 +1668,7 @@ define <2 x float> @test_cos(<2 x float> %a) #0 #1 { ; CHECK-NEXT: cos.approx.f32 %r4, %r1; ; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3}; ; CHECK-NEXT: ret; - %r = call <2 x float> @llvm.cos(<2 x float> %a) + %r = call afn <2 x float> @llvm.cos(<2 x float> %a) ret <2 x float> %r } @@ -2157,5 +2157,4 @@ define void @test_trunc_to_v2f16(<2 x float> %a, ptr %p) { attributes #0 = { nounwind } -attributes #1 = { "unsafe-fp-math" = "true" } attributes #2 = { "denormal-fp-math"="preserve-sign" } diff --git a/llvm/test/CodeGen/NVPTX/fast-math.ll b/llvm/test/CodeGen/NVPTX/fast-math.ll index 5eda3a1e2dda..8561c60a4694 100644 --- a/llvm/test/CodeGen/NVPTX/fast-math.ll +++ b/llvm/test/CodeGen/NVPTX/fast-math.ll @@ -22,7 +22,7 @@ define float @sqrt_div(float %a, float %b) { ret float %t2 } -define float @sqrt_div_fast(float %a, float %b) #0 { +define float @sqrt_div_fast(float %a, float %b) { ; CHECK-LABEL: sqrt_div_fast( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -34,29 +34,25 @@ define float @sqrt_div_fast(float %a, float %b) #0 { ; CHECK-NEXT: div.approx.f32 %r4, %r2, %r3; ; CHECK-NEXT: st.param.b32 [func_retval0], %r4; ; CHECK-NEXT: ret; - %t1 = tail call float @llvm.sqrt.f32(float %a) - %t2 = fdiv float %t1, %b + %t1 = tail call afn float @llvm.sqrt.f32(float %a) + %t2 = fdiv afn float %t1, %b ret float %t2 } -define float @sqrt_div_fast_ninf(float %a, float %b) #0 { +define float @sqrt_div_fast_ninf(float %a, float %b) { ; CHECK-LABEL: sqrt_div_fast_ninf( ; CHECK: { -; CHECK-NEXT: .reg .pred %p<2>; -; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-NEXT: .reg .b32 %r<5>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.b32 %r1, [sqrt_div_fast_ninf_param_0]; ; CHECK-NEXT: sqrt.approx.f32 %r2, %r1; -; CHECK-NEXT: abs.f32 %r3, %r1; -; CHECK-NEXT: setp.lt.f32 %p1, %r3, 0f00800000; -; CHECK-NEXT: selp.f32 %r4, 0f00000000, %r2, %p1; -; CHECK-NEXT: ld.param.b32 %r5, [sqrt_div_fast_ninf_param_1]; -; CHECK-NEXT: div.approx.f32 %r6, %r4, %r5; -; CHECK-NEXT: st.param.b32 [func_retval0], %r6; +; CHECK-NEXT: ld.param.b32 %r3, [sqrt_div_fast_ninf_param_1]; +; CHECK-NEXT: div.approx.f32 %r4, %r2, %r3; +; CHECK-NEXT: st.param.b32 [func_retval0], %r4; ; CHECK-NEXT: ret; %t1 = tail call ninf afn float @llvm.sqrt.f32(float %a) - %t2 = fdiv float %t1, %b + %t2 = fdiv afn float %t1, %b ret float %t2 } @@ -77,7 +73,7 @@ define float @sqrt_div_ftz(float %a, float %b) #1 { ret float %t2 } -define float @sqrt_div_fast_ftz(float %a, float %b) #0 #1 { +define float @sqrt_div_fast_ftz(float %a, float %b) #1 { ; CHECK-LABEL: sqrt_div_fast_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -89,35 +85,32 @@ define float @sqrt_div_fast_ftz(float %a, float %b) #0 #1 { ; CHECK-NEXT: div.approx.ftz.f32 %r4, %r2, %r3; ; CHECK-NEXT: st.param.b32 [func_retval0], %r4; ; CHECK-NEXT: ret; - %t1 = tail call float @llvm.sqrt.f32(float %a) - %t2 = fdiv float %t1, %b + %t1 = tail call afn float @llvm.sqrt.f32(float %a) + %t2 = fdiv afn float %t1, %b ret float %t2 } -define float @sqrt_div_fast_ftz_ninf(float %a, float %b) #0 #1 { +define float @sqrt_div_fast_ftz_ninf(float %a, float %b) #1 { ; CHECK-LABEL: sqrt_div_fast_ftz_ninf( ; CHECK: { -; CHECK-NEXT: .reg .pred %p<2>; -; CHECK-NEXT: .reg .b32 %r<6>; +; CHECK-NEXT: .reg .b32 %r<5>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.b32 %r1, [sqrt_div_fast_ftz_ninf_param_0]; -; CHECK-NEXT: setp.eq.ftz.f32 %p1, %r1, 0f00000000; ; CHECK-NEXT: sqrt.approx.ftz.f32 %r2, %r1; -; CHECK-NEXT: selp.f32 %r3, 0f00000000, %r2, %p1; -; CHECK-NEXT: ld.param.b32 %r4, [sqrt_div_fast_ftz_ninf_param_1]; -; CHECK-NEXT: div.approx.ftz.f32 %r5, %r3, %r4; -; CHECK-NEXT: st.param.b32 [func_retval0], %r5; +; CHECK-NEXT: ld.param.b32 %r3, [sqrt_div_fast_ftz_ninf_param_1]; +; CHECK-NEXT: div.approx.ftz.f32 %r4, %r2, %r3; +; CHECK-NEXT: st.param.b32 [func_retval0], %r4; ; CHECK-NEXT: ret; %t1 = tail call ninf afn float @llvm.sqrt.f32(float %a) - %t2 = fdiv float %t1, %b + %t2 = fdiv afn float %t1, %b ret float %t2 } ; There are no fast-math or ftz versions of sqrt and div for f64. We use ; reciprocal(rsqrt(x)) for sqrt(x), and emit a vanilla divide. -define double @sqrt_div_fast_ftz_f64(double %a, double %b) #0 #1 { +define double @sqrt_div_fast_ftz_f64(double %a, double %b) #1 { ; CHECK-LABEL: sqrt_div_fast_ftz_f64( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<5>; @@ -134,22 +127,17 @@ define double @sqrt_div_fast_ftz_f64(double %a, double %b) #0 #1 { ret double %t2 } -define double @sqrt_div_fast_ftz_f64_ninf(double %a, double %b) #0 #1 { +define double @sqrt_div_fast_ftz_f64_ninf(double %a, double %b) #1 { ; CHECK-LABEL: sqrt_div_fast_ftz_f64_ninf( ; CHECK: { -; CHECK-NEXT: .reg .pred %p<2>; -; CHECK-NEXT: .reg .b64 %rd<8>; +; CHECK-NEXT: .reg .b64 %rd<5>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.b64 %rd1, [sqrt_div_fast_ftz_f64_ninf_param_0]; -; CHECK-NEXT: abs.f64 %rd2, %rd1; -; CHECK-NEXT: setp.lt.f64 %p1, %rd2, 0d0010000000000000; -; CHECK-NEXT: rsqrt.approx.f64 %rd3, %rd1; -; CHECK-NEXT: rcp.approx.ftz.f64 %rd4, %rd3; -; CHECK-NEXT: selp.f64 %rd5, 0d0000000000000000, %rd4, %p1; -; CHECK-NEXT: ld.param.b64 %rd6, [sqrt_div_fast_ftz_f64_ninf_param_1]; -; CHECK-NEXT: div.rn.f64 %rd7, %rd5, %rd6; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd7; +; CHECK-NEXT: sqrt.rn.f64 %rd2, %rd1; +; CHECK-NEXT: ld.param.b64 %rd3, [sqrt_div_fast_ftz_f64_ninf_param_1]; +; CHECK-NEXT: div.rn.f64 %rd4, %rd2, %rd3; +; CHECK-NEXT: st.param.b64 [func_retval0], %rd4; ; CHECK-NEXT: ret; %t1 = tail call ninf afn double @llvm.sqrt.f64(double %a) %t2 = fdiv double %t1, %b @@ -172,7 +160,7 @@ define float @rsqrt(float %a) { ret float %ret } -define float @rsqrt_fast(float %a) #0 { +define float @rsqrt_fast(float %a) { ; CHECK-LABEL: rsqrt_fast( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -182,12 +170,12 @@ define float @rsqrt_fast(float %a) #0 { ; CHECK-NEXT: rsqrt.approx.f32 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; - %b = tail call float @llvm.sqrt.f32(float %a) - %ret = fdiv float 1.0, %b + %b = tail call afn float @llvm.sqrt.f32(float %a) + %ret = fdiv afn float 1.0, %b ret float %ret } -define float @rsqrt_fast_ftz(float %a) #0 #1 { +define float @rsqrt_fast_ftz(float %a) #1 { ; CHECK-LABEL: rsqrt_fast_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -197,8 +185,8 @@ define float @rsqrt_fast_ftz(float %a) #0 #1 { ; CHECK-NEXT: rsqrt.approx.ftz.f32 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; - %b = tail call float @llvm.sqrt.f32(float %a) - %ret = fdiv float 1.0, %b + %b = tail call afn float @llvm.sqrt.f32(float %a) + %ret = fdiv afn float 1.0, %b ret float %ret } @@ -263,35 +251,7 @@ define float @fcos_approx_afn(float %a) { ret float %r } -define float @fsin_approx(float %a) #0 { -; CHECK-LABEL: fsin_approx( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b32 %r1, [fsin_approx_param_0]; -; CHECK-NEXT: sin.approx.f32 %r2, %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %r = tail call float @llvm.sin.f32(float %a) - ret float %r -} - -define float @fcos_approx(float %a) #0 { -; CHECK-LABEL: fcos_approx( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b32 %r1, [fcos_approx_param_0]; -; CHECK-NEXT: cos.approx.f32 %r2, %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %r = tail call float @llvm.cos.f32(float %a) - ret float %r -} - -define float @fsin_approx_ftz(float %a) #0 #1 { +define float @fsin_approx_ftz(float %a) #1 { ; CHECK-LABEL: fsin_approx_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -301,11 +261,11 @@ define float @fsin_approx_ftz(float %a) #0 #1 { ; CHECK-NEXT: sin.approx.ftz.f32 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; - %r = tail call float @llvm.sin.f32(float %a) + %r = tail call afn float @llvm.sin.f32(float %a) ret float %r } -define float @fcos_approx_ftz(float %a) #0 #1 { +define float @fcos_approx_ftz(float %a) #1 { ; CHECK-LABEL: fcos_approx_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -315,7 +275,7 @@ define float @fcos_approx_ftz(float %a) #0 #1 { ; CHECK-NEXT: cos.approx.ftz.f32 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; - %r = tail call float @llvm.cos.f32(float %a) + %r = tail call afn float @llvm.cos.f32(float %a) ret float %r } @@ -423,7 +383,7 @@ define float @repeated_div_recip_allowed_ftz_sel(i1 %pred, float %a, float %b, f ret float %w } -define float @repeated_div_fast(i1 %pred, float %a, float %b, float %divisor) #0 { +define float @repeated_div_fast(i1 %pred, float %a, float %b, float %divisor) { ; CHECK-LABEL: repeated_div_fast( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -444,14 +404,14 @@ define float @repeated_div_fast(i1 %pred, float %a, float %b, float %divisor) #0 ; CHECK-NEXT: selp.f32 %r8, %r7, %r6, %p1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r8; ; CHECK-NEXT: ret; - %x = fdiv float %a, %divisor - %y = fdiv float %b, %divisor - %z = fmul float %x, %y + %x = fdiv afn arcp float %a, %divisor + %y = fdiv afn arcp contract float %b, %divisor + %z = fmul contract float %x, %y %w = select i1 %pred, float %z, float %y ret float %w } -define float @repeated_div_fast_sel(i1 %pred, float %a, float %b, float %divisor) #0 { +define float @repeated_div_fast_sel(i1 %pred, float %a, float %b, float %divisor) { ; CHECK-LABEL: repeated_div_fast_sel( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -469,13 +429,13 @@ define float @repeated_div_fast_sel(i1 %pred, float %a, float %b, float %divisor ; CHECK-NEXT: div.approx.f32 %r5, %r3, %r4; ; CHECK-NEXT: st.param.b32 [func_retval0], %r5; ; CHECK-NEXT: ret; - %x = fdiv float %a, %divisor - %y = fdiv float %b, %divisor + %x = fdiv afn float %a, %divisor + %y = fdiv afn float %b, %divisor %w = select i1 %pred, float %x, float %y ret float %w } -define float @repeated_div_fast_ftz(i1 %pred, float %a, float %b, float %divisor) #0 #1 { +define float @repeated_div_fast_ftz(i1 %pred, float %a, float %b, float %divisor) #1 { ; CHECK-LABEL: repeated_div_fast_ftz( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -496,14 +456,14 @@ define float @repeated_div_fast_ftz(i1 %pred, float %a, float %b, float %divisor ; CHECK-NEXT: selp.f32 %r8, %r7, %r6, %p1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r8; ; CHECK-NEXT: ret; - %x = fdiv float %a, %divisor - %y = fdiv float %b, %divisor - %z = fmul float %x, %y + %x = fdiv afn arcp float %a, %divisor + %y = fdiv afn arcp contract float %b, %divisor + %z = fmul contract float %x, %y %w = select i1 %pred, float %z, float %y ret float %w } -define float @repeated_div_fast_ftz_sel(i1 %pred, float %a, float %b, float %divisor) #0 #1 { +define float @repeated_div_fast_ftz_sel(i1 %pred, float %a, float %b, float %divisor) #1 { ; CHECK-LABEL: repeated_div_fast_ftz_sel( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -521,13 +481,13 @@ define float @repeated_div_fast_ftz_sel(i1 %pred, float %a, float %b, float %div ; CHECK-NEXT: div.approx.ftz.f32 %r5, %r3, %r4; ; CHECK-NEXT: st.param.b32 [func_retval0], %r5; ; CHECK-NEXT: ret; - %x = fdiv float %a, %divisor - %y = fdiv float %b, %divisor + %x = fdiv afn float %a, %divisor + %y = fdiv afn float %b, %divisor %w = select i1 %pred, float %x, float %y ret float %w } -define float @frem(float %a, float %b) #0 { +define float @frem(float %a, float %b) { ; CHECK-LABEL: frem( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<7>; @@ -541,11 +501,11 @@ define float @frem(float %a, float %b) #0 { ; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-NEXT: ret; - %rem = frem float %a, %b + %rem = frem afn arcp contract ninf float %a, %b ret float %rem } -define float @frem_ftz(float %a, float %b) #0 #1 { +define float @frem_ftz(float %a, float %b) #1 { ; CHECK-LABEL: frem_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<7>; @@ -559,11 +519,11 @@ define float @frem_ftz(float %a, float %b) #0 #1 { ; CHECK-NEXT: fma.rn.ftz.f32 %r6, %r5, %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-NEXT: ret; - %rem = frem float %a, %b + %rem = frem afn contract ninf float %a, %b ret float %rem } -define double @frem_f64(double %a, double %b) #0 { +define double @frem_f64(double %a, double %b) { ; CHECK-LABEL: frem_f64( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<7>; @@ -577,9 +537,8 @@ define double @frem_f64(double %a, double %b) #0 { ; CHECK-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; ; CHECK-NEXT: st.param.b64 [func_retval0], %rd6; ; CHECK-NEXT: ret; - %rem = frem double %a, %b + %rem = frem ninf double %a, %b ret double %rem } -attributes #0 = { "unsafe-fp-math" = "true" } attributes #1 = { "denormal-fp-math-f32" = "preserve-sign" } diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll index 2f1d7d632143..6d983ba6bf0f 100644 --- a/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll +++ b/llvm/test/CodeGen/NVPTX/fma-relu-fma-intrinsic.ll @@ -9,7 +9,7 @@ ; SM < 80 or (which needs PTX version >= 70) should not emit fma{.ftz}.relu ; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_70 | FileCheck %s --check-prefixes=CHECK-SM70 -define half @fma_f16_no_nans(half %a, half %b, half %c) #0 { +define half @fma_f16_no_nans(half %a, half %b, half %c) { ; CHECK-LABEL: fma_f16_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<5>; @@ -49,14 +49,14 @@ define half @fma_f16_no_nans(half %a, half %b, half %c) #0 { ; CHECK-SM70-NEXT: selp.b16 %rs6, %rs4, 0x0000, %p1; ; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs6; ; CHECK-SM70-NEXT: ret; - %1 = call half @llvm.fma.f16(half %a, half %b, half %c) + %1 = call nnan half @llvm.fma.f16(half %a, half %b, half %c) %2 = fcmp ogt half %1, 0.0 - %3 = select i1 %2, half %1, half 0.0 + %3 = select nsz i1 %2, half %1, half 0.0 ret half %3 } ; FMA relu shouldn't be selected if the FMA operation has multiple uses -define half @fma_f16_no_nans_multiple_uses_of_fma(half %a, half %b, half %c) #0 { +define half @fma_f16_no_nans_multiple_uses_of_fma(half %a, half %b, half %c) { ; CHECK-LABEL: fma_f16_no_nans_multiple_uses_of_fma( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<8>; @@ -103,13 +103,13 @@ define half @fma_f16_no_nans_multiple_uses_of_fma(half %a, half %b, half %c) #0 ; CHECK-SM70-NEXT: ret; %1 = call half @llvm.fma.f16(half %a, half %b, half %c) %2 = fcmp ogt half %1, 0.0 - %3 = select i1 %2, half %1, half 0.0 - %4 = fadd half %1, 7.0 - %5 = fadd half %4, %1 + %3 = select i1 %2, half %1, half 0.0 + %4 = fadd contract half %1, 7.0 + %5 = fadd contract half %4, %1 ret half %5 } -define half @fma_f16_maxnum_no_nans(half %a, half %b, half %c) #0 { +define half @fma_f16_maxnum_no_nans(half %a, half %b, half %c) { ; CHECK-LABEL: fma_f16_maxnum_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<5>; @@ -149,12 +149,12 @@ define half @fma_f16_maxnum_no_nans(half %a, half %b, half %c) #0 { ; CHECK-SM70-NEXT: cvt.rn.f16.f32 %rs5, %r2; ; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs5; ; CHECK-SM70-NEXT: ret; - %1 = call half @llvm.fma.f16(half %a, half %b, half %c) - %2 = call half @llvm.maxnum.f16(half %1, half 0.0) + %1 = call nnan half @llvm.fma.f16(half %a, half %b, half %c) + %2 = call nsz half @llvm.maxnum.f16(half %1, half 0.0) ret half %2 } -define bfloat @fma_bf16_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 { +define bfloat @fma_bf16_no_nans(bfloat %a, bfloat %b, bfloat %c) { ; CHECK-LABEL: fma_bf16_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<5>; @@ -205,14 +205,14 @@ define bfloat @fma_bf16_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-SM70-NEXT: selp.b16 %rs2, %rs1, 0x0000, %p2; ; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %rs2; ; CHECK-SM70-NEXT: ret; - %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c) + %1 = call nnan bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c) %2 = fcmp ogt bfloat %1, 0.0 - %3 = select i1 %2, bfloat %1, bfloat 0.0 + %3 = select nsz i1 %2, bfloat %1, bfloat 0.0 ret bfloat %3 } ; FMA_relu shouldn't be selected if the FMA operation has multiple uses -define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) #0 { +define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloat %c) { ; CHECK-LABEL: fma_bf16_no_nans_multiple_uses_of_fma( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<9>; @@ -291,12 +291,12 @@ define bfloat @fma_bf16_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %b, bfloa %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c) %2 = fcmp ogt bfloat %1, 0.0 %3 = select i1 %2, bfloat %1, bfloat 0.0 - %4 = fadd bfloat %1, 7.0 - %5 = fadd bfloat %4, %1 + %4 = fadd contract bfloat %1, 7.0 + %5 = fadd contract bfloat %4, %1 ret bfloat %5 } -define bfloat @fma_bf16_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 { +define bfloat @fma_bf16_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) { ; CHECK-LABEL: fma_bf16_maxnum_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b16 %rs<5>; @@ -351,12 +351,12 @@ define bfloat @fma_bf16_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-SM70-NEXT: shr.u32 %r20, %r19, 16; ; CHECK-SM70-NEXT: st.param.b16 [func_retval0], %r20; ; CHECK-SM70-NEXT: ret; - %1 = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c) - %2 = call bfloat @llvm.maxnum.bf16(bfloat %1, bfloat 0.0) + %1 = call nnan bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c) + %2 = call nsz bfloat @llvm.maxnum.bf16(bfloat %1, bfloat 0.0) ret bfloat %2 } -define <2 x half> @fma_f16x2_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 { +define <2 x half> @fma_f16x2_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) { ; CHECK-LABEL: fma_f16x2_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -399,14 +399,14 @@ define <2 x half> @fma_f16x2_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c ; CHECK-SM70-NEXT: selp.b16 %rs4, %rs1, 0x0000, %p1; ; CHECK-SM70-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3}; ; CHECK-SM70-NEXT: ret; - %1 = call <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c) + %1 = call nnan <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c) %2 = fcmp ogt <2 x half> %1, <half 0.0, half 0.0> - %3 = select <2 x i1> %2, <2 x half> %1, <2 x half> <half 0.0, half 0.0> + %3 = select nsz <2 x i1> %2, <2 x half> %1, <2 x half> <half 0.0, half 0.0> ret <2 x half> %3 } ; FMA relu shouldn't be selected if the FMA operation has multiple uses -define <2 x half> @fma_f16x2_no_nans_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 { +define <2 x half> @fma_f16x2_no_nans_multiple_uses_of_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) { ; CHECK-LABEL: fma_f16x2_no_nans_multiple_uses_of_fma( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<8>; @@ -454,12 +454,12 @@ define <2 x half> @fma_f16x2_no_nans_multiple_uses_of_fma(<2 x half> %a, <2 x ha %1 = call <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c) %2 = fcmp ogt <2 x half> %1, <half 0.0, half 0.0> %3 = select <2 x i1> %2, <2 x half> %1, <2 x half> <half 0.0, half 0.0> - %4 = fadd <2 x half> %1, <half 7.0, half 7.0> - %5 = fadd <2 x half> %4, %1 + %4 = fadd contract <2 x half> %1, <half 7.0, half 7.0> + %5 = fadd contract <2 x half> %4, %1 ret <2 x half> %5 } -define <2 x half> @fma_f16x2_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 { +define <2 x half> @fma_f16x2_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x half> %c) { ; CHECK-LABEL: fma_f16x2_maxnum_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -504,12 +504,12 @@ define <2 x half> @fma_f16x2_maxnum_no_nans(<2 x half> %a, <2 x half> %b, <2 x h ; CHECK-SM70-NEXT: mov.b32 %r9, {%rs4, %rs3}; ; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r9; ; CHECK-SM70-NEXT: ret; - %1 = call <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c) - %2 = call <2 x half> @llvm.maxnum.f16x2(<2 x half> %1, <2 x half> <half 0.0, half 0.0>) + %1 = call nnan <2 x half> @llvm.fma.f16x2(<2 x half> %a, <2 x half> %b, <2 x half> %c) + %2 = call nsz <2 x half> @llvm.maxnum.f16x2(<2 x half> %1, <2 x half> <half 0.0, half 0.0>) ret <2 x half> %2 } -define <2 x bfloat> @fma_bf16x2_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 { +define <2 x bfloat> @fma_bf16x2_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) { ; CHECK-LABEL: fma_bf16x2_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -580,14 +580,14 @@ define <2 x bfloat> @fma_bf16x2_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x b ; CHECK-SM70-NEXT: selp.b16 %rs10, %rs7, 0x0000, %p3; ; CHECK-SM70-NEXT: st.param.v2.b16 [func_retval0], {%rs10, %rs9}; ; CHECK-SM70-NEXT: ret; - %1 = call <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) + %1 = call nnan <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) %2 = fcmp ogt <2 x bfloat> %1, <bfloat 0.0, bfloat 0.0> - %3 = select <2 x i1> %2, <2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0> + %3 = select nsz <2 x i1> %2, <2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0> ret <2 x bfloat> %3 } ; FMA_relu shouldn't be selected if the FMA operation has multiple uses -define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 { +define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) { ; CHECK-LABEL: fma_bf16x2_no_nans_multiple_uses_of_fma( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<9>; @@ -707,12 +707,12 @@ define <2 x bfloat> @fma_bf16x2_no_nans_multiple_uses_of_fma(<2 x bfloat> %a, <2 %1 = call <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) %2 = fcmp ogt <2 x bfloat> %1, <bfloat 0.0, bfloat 0.0> %3 = select <2 x i1> %2, <2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0> - %4 = fadd <2 x bfloat> %1, <bfloat 7.0, bfloat 7.0> - %5 = fadd <2 x bfloat> %4, %1 + %4 = fadd contract <2 x bfloat> %1, <bfloat 7.0, bfloat 7.0> + %5 = fadd contract <2 x bfloat> %4, %1 ret <2 x bfloat> %5 } -define <2 x bfloat> @fma_bf16x2_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 { +define <2 x bfloat> @fma_bf16x2_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) { ; CHECK-LABEL: fma_bf16x2_maxnum_no_nans( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<5>; @@ -792,10 +792,7 @@ define <2 x bfloat> @fma_bf16x2_maxnum_no_nans(<2 x bfloat> %a, <2 x bfloat> %b, ; CHECK-SM70-NEXT: prmt.b32 %r39, %r38, %r31, 0x7632U; ; CHECK-SM70-NEXT: st.param.b32 [func_retval0], %r39; ; CHECK-SM70-NEXT: ret; - %1 = call <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) - %2 = call <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>) + %1 = call nnan <2 x bfloat> @llvm.fma.bf16x2(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) + %2 = call nsz <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %1, <2 x bfloat> <bfloat 0.0, bfloat 0.0>) ret <2 x bfloat> %2 } - -attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "unsafe-fp-math"="true" } -attributes #1 = { "unsafe-fp-math"="true" } diff --git a/llvm/test/CodeGen/NVPTX/frem.ll b/llvm/test/CodeGen/NVPTX/frem.ll index 5805aed1bebe..d30c72cef83d 100644 --- a/llvm/test/CodeGen/NVPTX/frem.ll +++ b/llvm/test/CodeGen/NVPTX/frem.ll @@ -1,313 +1,316 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc < %s --enable-unsafe-fp-math -mcpu=sm_60 | FileCheck %s --check-prefixes=FAST -; RUN: llc < %s -mcpu=sm_60 | FileCheck %s --check-prefixes=NORMAL +; RUN: llc < %s -mcpu=sm_60 | FileCheck %s target triple = "nvptx64-unknown-cuda" define half @frem_f16(half %a, half %b) { -; FAST-LABEL: frem_f16( -; FAST: { -; FAST-NEXT: .reg .b16 %rs<4>; -; FAST-NEXT: .reg .b32 %r<7>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b16 %rs1, [frem_f16_param_0]; -; FAST-NEXT: ld.param.b16 %rs2, [frem_f16_param_1]; -; FAST-NEXT: cvt.f32.f16 %r1, %rs2; -; FAST-NEXT: cvt.f32.f16 %r2, %rs1; -; FAST-NEXT: div.approx.f32 %r3, %r2, %r1; -; FAST-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; FAST-NEXT: neg.f32 %r5, %r4; -; FAST-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; -; FAST-NEXT: cvt.rn.f16.f32 %rs3, %r6; -; FAST-NEXT: st.param.b16 [func_retval0], %rs3; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f16( -; NORMAL: { -; NORMAL-NEXT: .reg .pred %p<2>; -; NORMAL-NEXT: .reg .b16 %rs<4>; -; NORMAL-NEXT: .reg .b32 %r<8>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b16 %rs1, [frem_f16_param_0]; -; NORMAL-NEXT: ld.param.b16 %rs2, [frem_f16_param_1]; -; NORMAL-NEXT: cvt.f32.f16 %r1, %rs2; -; NORMAL-NEXT: cvt.f32.f16 %r2, %rs1; -; NORMAL-NEXT: div.rn.f32 %r3, %r2, %r1; -; NORMAL-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; NORMAL-NEXT: neg.f32 %r5, %r4; -; NORMAL-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; -; NORMAL-NEXT: testp.infinite.f32 %p1, %r1; -; NORMAL-NEXT: selp.f32 %r7, %r2, %r6, %p1; -; NORMAL-NEXT: cvt.rn.f16.f32 %rs3, %r7; -; NORMAL-NEXT: st.param.b16 [func_retval0], %rs3; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f16( +; CHECK: { +; CHECK-NEXT: .reg .pred %p<2>; +; CHECK-NEXT: .reg .b16 %rs<4>; +; CHECK-NEXT: .reg .b32 %r<8>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b16 %rs1, [frem_f16_param_0]; +; CHECK-NEXT: ld.param.b16 %rs2, [frem_f16_param_1]; +; CHECK-NEXT: cvt.f32.f16 %r1, %rs2; +; CHECK-NEXT: cvt.f32.f16 %r2, %rs1; +; CHECK-NEXT: div.rn.f32 %r3, %r2, %r1; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; +; CHECK-NEXT: testp.infinite.f32 %p1, %r1; +; CHECK-NEXT: selp.f32 %r7, %r2, %r6, %p1; +; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r7; +; CHECK-NEXT: st.param.b16 [func_retval0], %rs3; +; CHECK-NEXT: ret; %r = frem half %a, %b ret half %r } +define half @frem_f16_fast(half %a, half %b) { +; CHECK-LABEL: frem_f16_fast( +; CHECK: { +; CHECK-NEXT: .reg .b16 %rs<4>; +; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b16 %rs1, [frem_f16_fast_param_0]; +; CHECK-NEXT: ld.param.b16 %rs2, [frem_f16_fast_param_1]; +; CHECK-NEXT: cvt.f32.f16 %r1, %rs2; +; CHECK-NEXT: cvt.f32.f16 %r2, %rs1; +; CHECK-NEXT: div.approx.f32 %r3, %r2, %r1; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; +; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r6; +; CHECK-NEXT: st.param.b16 [func_retval0], %rs3; +; CHECK-NEXT: ret; + %r = frem afn ninf half %a, %b + ret half %r +} + define float @frem_f32(float %a, float %b) { -; FAST-LABEL: frem_f32( -; FAST: { -; FAST-NEXT: .reg .b32 %r<7>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b32 %r1, [frem_f32_param_0]; -; FAST-NEXT: ld.param.b32 %r2, [frem_f32_param_1]; -; FAST-NEXT: div.approx.f32 %r3, %r1, %r2; -; FAST-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; FAST-NEXT: neg.f32 %r5, %r4; -; FAST-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; -; FAST-NEXT: st.param.b32 [func_retval0], %r6; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f32( -; NORMAL: { -; NORMAL-NEXT: .reg .pred %p<2>; -; NORMAL-NEXT: .reg .b32 %r<8>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b32 %r1, [frem_f32_param_0]; -; NORMAL-NEXT: ld.param.b32 %r2, [frem_f32_param_1]; -; NORMAL-NEXT: div.rn.f32 %r3, %r1, %r2; -; NORMAL-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; NORMAL-NEXT: neg.f32 %r5, %r4; -; NORMAL-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; -; NORMAL-NEXT: testp.infinite.f32 %p1, %r2; -; NORMAL-NEXT: selp.f32 %r7, %r1, %r6, %p1; -; NORMAL-NEXT: st.param.b32 [func_retval0], %r7; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f32( +; CHECK: { +; CHECK-NEXT: .reg .pred %p<2>; +; CHECK-NEXT: .reg .b32 %r<8>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_param_0]; +; CHECK-NEXT: ld.param.b32 %r2, [frem_f32_param_1]; +; CHECK-NEXT: div.rn.f32 %r3, %r1, %r2; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; +; CHECK-NEXT: testp.infinite.f32 %p1, %r2; +; CHECK-NEXT: selp.f32 %r7, %r1, %r6, %p1; +; CHECK-NEXT: st.param.b32 [func_retval0], %r7; +; CHECK-NEXT: ret; %r = frem float %a, %b ret float %r } +define float @frem_f32_fast(float %a, float %b) { +; CHECK-LABEL: frem_f32_fast( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_fast_param_0]; +; CHECK-NEXT: ld.param.b32 %r2, [frem_f32_fast_param_1]; +; CHECK-NEXT: div.approx.f32 %r3, %r1, %r2; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; +; CHECK-NEXT: st.param.b32 [func_retval0], %r6; +; CHECK-NEXT: ret; + %r = frem afn ninf float %a, %b + ret float %r +} + define double @frem_f64(double %a, double %b) { -; FAST-LABEL: frem_f64( -; FAST: { -; FAST-NEXT: .reg .b64 %rd<7>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b64 %rd1, [frem_f64_param_0]; -; FAST-NEXT: ld.param.b64 %rd2, [frem_f64_param_1]; -; FAST-NEXT: div.rn.f64 %rd3, %rd1, %rd2; -; FAST-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; -; FAST-NEXT: neg.f64 %rd5, %rd4; -; FAST-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; -; FAST-NEXT: st.param.b64 [func_retval0], %rd6; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f64( -; NORMAL: { -; NORMAL-NEXT: .reg .pred %p<2>; -; NORMAL-NEXT: .reg .b64 %rd<8>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b64 %rd1, [frem_f64_param_0]; -; NORMAL-NEXT: ld.param.b64 %rd2, [frem_f64_param_1]; -; NORMAL-NEXT: div.rn.f64 %rd3, %rd1, %rd2; -; NORMAL-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; -; NORMAL-NEXT: neg.f64 %rd5, %rd4; -; NORMAL-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; -; NORMAL-NEXT: testp.infinite.f64 %p1, %rd2; -; NORMAL-NEXT: selp.f64 %rd7, %rd1, %rd6, %p1; -; NORMAL-NEXT: st.param.b64 [func_retval0], %rd7; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f64( +; CHECK: { +; CHECK-NEXT: .reg .pred %p<2>; +; CHECK-NEXT: .reg .b64 %rd<8>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b64 %rd1, [frem_f64_param_0]; +; CHECK-NEXT: ld.param.b64 %rd2, [frem_f64_param_1]; +; CHECK-NEXT: div.rn.f64 %rd3, %rd1, %rd2; +; CHECK-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; +; CHECK-NEXT: neg.f64 %rd5, %rd4; +; CHECK-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; +; CHECK-NEXT: testp.infinite.f64 %p1, %rd2; +; CHECK-NEXT: selp.f64 %rd7, %rd1, %rd6, %p1; +; CHECK-NEXT: st.param.b64 [func_retval0], %rd7; +; CHECK-NEXT: ret; %r = frem double %a, %b ret double %r } +define double @frem_f64_fast(double %a, double %b) { +; CHECK-LABEL: frem_f64_fast( +; CHECK: { +; CHECK-NEXT: .reg .b64 %rd<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b64 %rd1, [frem_f64_fast_param_0]; +; CHECK-NEXT: ld.param.b64 %rd2, [frem_f64_fast_param_1]; +; CHECK-NEXT: div.rn.f64 %rd3, %rd1, %rd2; +; CHECK-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; +; CHECK-NEXT: neg.f64 %rd5, %rd4; +; CHECK-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; +; CHECK-NEXT: st.param.b64 [func_retval0], %rd6; +; CHECK-NEXT: ret; + %r = frem afn ninf double %a, %b + ret double %r +} + define half @frem_f16_ninf(half %a, half %b) { -; FAST-LABEL: frem_f16_ninf( -; FAST: { -; FAST-NEXT: .reg .b16 %rs<4>; -; FAST-NEXT: .reg .b32 %r<7>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b16 %rs1, [frem_f16_ninf_param_0]; -; FAST-NEXT: ld.param.b16 %rs2, [frem_f16_ninf_param_1]; -; FAST-NEXT: cvt.f32.f16 %r1, %rs2; -; FAST-NEXT: cvt.f32.f16 %r2, %rs1; -; FAST-NEXT: div.approx.f32 %r3, %r2, %r1; -; FAST-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; FAST-NEXT: neg.f32 %r5, %r4; -; FAST-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; -; FAST-NEXT: cvt.rn.f16.f32 %rs3, %r6; -; FAST-NEXT: st.param.b16 [func_retval0], %rs3; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f16_ninf( -; NORMAL: { -; NORMAL-NEXT: .reg .b16 %rs<4>; -; NORMAL-NEXT: .reg .b32 %r<7>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b16 %rs1, [frem_f16_ninf_param_0]; -; NORMAL-NEXT: ld.param.b16 %rs2, [frem_f16_ninf_param_1]; -; NORMAL-NEXT: cvt.f32.f16 %r1, %rs2; -; NORMAL-NEXT: cvt.f32.f16 %r2, %rs1; -; NORMAL-NEXT: div.rn.f32 %r3, %r2, %r1; -; NORMAL-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; NORMAL-NEXT: neg.f32 %r5, %r4; -; NORMAL-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; -; NORMAL-NEXT: cvt.rn.f16.f32 %rs3, %r6; -; NORMAL-NEXT: st.param.b16 [func_retval0], %rs3; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f16_ninf( +; CHECK: { +; CHECK-NEXT: .reg .b16 %rs<4>; +; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b16 %rs1, [frem_f16_ninf_param_0]; +; CHECK-NEXT: ld.param.b16 %rs2, [frem_f16_ninf_param_1]; +; CHECK-NEXT: cvt.f32.f16 %r1, %rs2; +; CHECK-NEXT: cvt.f32.f16 %r2, %rs1; +; CHECK-NEXT: div.rn.f32 %r3, %r2, %r1; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; +; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r6; +; CHECK-NEXT: st.param.b16 [func_retval0], %rs3; +; CHECK-NEXT: ret; %r = frem ninf half %a, %b ret half %r } +define half @frem_f16_ninf_fast(half %a, half %b) { +; CHECK-LABEL: frem_f16_ninf_fast( +; CHECK: { +; CHECK-NEXT: .reg .b16 %rs<4>; +; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b16 %rs1, [frem_f16_ninf_fast_param_0]; +; CHECK-NEXT: ld.param.b16 %rs2, [frem_f16_ninf_fast_param_1]; +; CHECK-NEXT: cvt.f32.f16 %r1, %rs2; +; CHECK-NEXT: cvt.f32.f16 %r2, %rs1; +; CHECK-NEXT: div.approx.f32 %r3, %r2, %r1; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r1, %r2; +; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r6; +; CHECK-NEXT: st.param.b16 [func_retval0], %rs3; +; CHECK-NEXT: ret; + %r = frem afn ninf half %a, %b + ret half %r +} + define float @frem_f32_ninf(float %a, float %b) { -; FAST-LABEL: frem_f32_ninf( -; FAST: { -; FAST-NEXT: .reg .b32 %r<7>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b32 %r1, [frem_f32_ninf_param_0]; -; FAST-NEXT: ld.param.b32 %r2, [frem_f32_ninf_param_1]; -; FAST-NEXT: div.approx.f32 %r3, %r1, %r2; -; FAST-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; FAST-NEXT: neg.f32 %r5, %r4; -; FAST-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; -; FAST-NEXT: st.param.b32 [func_retval0], %r6; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f32_ninf( -; NORMAL: { -; NORMAL-NEXT: .reg .b32 %r<7>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b32 %r1, [frem_f32_ninf_param_0]; -; NORMAL-NEXT: ld.param.b32 %r2, [frem_f32_ninf_param_1]; -; NORMAL-NEXT: div.rn.f32 %r3, %r1, %r2; -; NORMAL-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; NORMAL-NEXT: neg.f32 %r5, %r4; -; NORMAL-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; -; NORMAL-NEXT: st.param.b32 [func_retval0], %r6; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f32_ninf( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_ninf_param_0]; +; CHECK-NEXT: ld.param.b32 %r2, [frem_f32_ninf_param_1]; +; CHECK-NEXT: div.rn.f32 %r3, %r1, %r2; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; +; CHECK-NEXT: st.param.b32 [func_retval0], %r6; +; CHECK-NEXT: ret; %r = frem ninf float %a, %b ret float %r } +define float @frem_f32_ninf_fast(float %a, float %b) { +; CHECK-LABEL: frem_f32_ninf_fast( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_ninf_fast_param_0]; +; CHECK-NEXT: ld.param.b32 %r2, [frem_f32_ninf_fast_param_1]; +; CHECK-NEXT: div.approx.f32 %r3, %r1, %r2; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r2, %r1; +; CHECK-NEXT: st.param.b32 [func_retval0], %r6; +; CHECK-NEXT: ret; + %r = frem afn ninf float %a, %b + ret float %r +} + define double @frem_f64_ninf(double %a, double %b) { -; FAST-LABEL: frem_f64_ninf( -; FAST: { -; FAST-NEXT: .reg .b64 %rd<7>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b64 %rd1, [frem_f64_ninf_param_0]; -; FAST-NEXT: ld.param.b64 %rd2, [frem_f64_ninf_param_1]; -; FAST-NEXT: div.rn.f64 %rd3, %rd1, %rd2; -; FAST-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; -; FAST-NEXT: neg.f64 %rd5, %rd4; -; FAST-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; -; FAST-NEXT: st.param.b64 [func_retval0], %rd6; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f64_ninf( -; NORMAL: { -; NORMAL-NEXT: .reg .b64 %rd<7>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b64 %rd1, [frem_f64_ninf_param_0]; -; NORMAL-NEXT: ld.param.b64 %rd2, [frem_f64_ninf_param_1]; -; NORMAL-NEXT: div.rn.f64 %rd3, %rd1, %rd2; -; NORMAL-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; -; NORMAL-NEXT: neg.f64 %rd5, %rd4; -; NORMAL-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; -; NORMAL-NEXT: st.param.b64 [func_retval0], %rd6; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f64_ninf( +; CHECK: { +; CHECK-NEXT: .reg .b64 %rd<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b64 %rd1, [frem_f64_ninf_param_0]; +; CHECK-NEXT: ld.param.b64 %rd2, [frem_f64_ninf_param_1]; +; CHECK-NEXT: div.rn.f64 %rd3, %rd1, %rd2; +; CHECK-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; +; CHECK-NEXT: neg.f64 %rd5, %rd4; +; CHECK-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; +; CHECK-NEXT: st.param.b64 [func_retval0], %rd6; +; CHECK-NEXT: ret; %r = frem ninf double %a, %b ret double %r } +define double @frem_f64_ninf_fast(double %a, double %b) { +; CHECK-LABEL: frem_f64_ninf_fast( +; CHECK: { +; CHECK-NEXT: .reg .b64 %rd<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b64 %rd1, [frem_f64_ninf_fast_param_0]; +; CHECK-NEXT: ld.param.b64 %rd2, [frem_f64_ninf_fast_param_1]; +; CHECK-NEXT: div.rn.f64 %rd3, %rd1, %rd2; +; CHECK-NEXT: cvt.rzi.f64.f64 %rd4, %rd3; +; CHECK-NEXT: neg.f64 %rd5, %rd4; +; CHECK-NEXT: fma.rn.f64 %rd6, %rd5, %rd2, %rd1; +; CHECK-NEXT: st.param.b64 [func_retval0], %rd6; +; CHECK-NEXT: ret; + %r = frem afn ninf double %a, %b + ret double %r +} + define float @frem_f32_imm1_fast(float %a) { -; FAST-LABEL: frem_f32_imm1_fast( -; FAST: { -; FAST-NEXT: .reg .b32 %r<5>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b32 %r1, [frem_f32_imm1_fast_param_0]; -; FAST-NEXT: mul.f32 %r2, %r1, 0f3E124925; -; FAST-NEXT: cvt.rzi.f32.f32 %r3, %r2; -; FAST-NEXT: fma.rn.f32 %r4, %r3, 0fC0E00000, %r1; -; FAST-NEXT: st.param.b32 [func_retval0], %r4; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f32_imm1_fast( -; NORMAL: { -; NORMAL-NEXT: .reg .b32 %r<5>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b32 %r1, [frem_f32_imm1_fast_param_0]; -; NORMAL-NEXT: mul.rn.f32 %r2, %r1, 0f3E124925; -; NORMAL-NEXT: cvt.rzi.f32.f32 %r3, %r2; -; NORMAL-NEXT: fma.rn.f32 %r4, %r3, 0fC0E00000, %r1; -; NORMAL-NEXT: st.param.b32 [func_retval0], %r4; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f32_imm1_fast( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<5>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_imm1_fast_param_0]; +; CHECK-NEXT: mul.rn.f32 %r2, %r1, 0f3E124925; +; CHECK-NEXT: cvt.rzi.f32.f32 %r3, %r2; +; CHECK-NEXT: fma.rn.f32 %r4, %r3, 0fC0E00000, %r1; +; CHECK-NEXT: st.param.b32 [func_retval0], %r4; +; CHECK-NEXT: ret; %r = frem arcp float %a, 7.0 ret float %r } define float @frem_f32_imm1_normal(float %a) { -; FAST-LABEL: frem_f32_imm1_normal( -; FAST: { -; FAST-NEXT: .reg .b32 %r<5>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b32 %r1, [frem_f32_imm1_normal_param_0]; -; FAST-NEXT: div.approx.f32 %r2, %r1, 0f40E00000; -; FAST-NEXT: cvt.rzi.f32.f32 %r3, %r2; -; FAST-NEXT: fma.rn.f32 %r4, %r3, 0fC0E00000, %r1; -; FAST-NEXT: st.param.b32 [func_retval0], %r4; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f32_imm1_normal( -; NORMAL: { -; NORMAL-NEXT: .reg .b32 %r<5>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b32 %r1, [frem_f32_imm1_normal_param_0]; -; NORMAL-NEXT: div.rn.f32 %r2, %r1, 0f40E00000; -; NORMAL-NEXT: cvt.rzi.f32.f32 %r3, %r2; -; NORMAL-NEXT: fma.rn.f32 %r4, %r3, 0fC0E00000, %r1; -; NORMAL-NEXT: st.param.b32 [func_retval0], %r4; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f32_imm1_normal( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<5>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_imm1_normal_param_0]; +; CHECK-NEXT: div.rn.f32 %r2, %r1, 0f40E00000; +; CHECK-NEXT: cvt.rzi.f32.f32 %r3, %r2; +; CHECK-NEXT: fma.rn.f32 %r4, %r3, 0fC0E00000, %r1; +; CHECK-NEXT: st.param.b32 [func_retval0], %r4; +; CHECK-NEXT: ret; %r = frem float %a, 7.0 ret float %r } define float @frem_f32_imm2(float %a) { -; FAST-LABEL: frem_f32_imm2( -; FAST: { -; FAST-NEXT: .reg .b32 %r<7>; -; FAST-EMPTY: -; FAST-NEXT: // %bb.0: -; FAST-NEXT: ld.param.b32 %r1, [frem_f32_imm2_param_0]; -; FAST-NEXT: mov.b32 %r2, 0f40E00000; -; FAST-NEXT: div.approx.f32 %r3, %r2, %r1; -; FAST-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; FAST-NEXT: neg.f32 %r5, %r4; -; FAST-NEXT: fma.rn.f32 %r6, %r5, %r1, 0f40E00000; -; FAST-NEXT: st.param.b32 [func_retval0], %r6; -; FAST-NEXT: ret; -; -; NORMAL-LABEL: frem_f32_imm2( -; NORMAL: { -; NORMAL-NEXT: .reg .pred %p<2>; -; NORMAL-NEXT: .reg .b32 %r<8>; -; NORMAL-EMPTY: -; NORMAL-NEXT: // %bb.0: -; NORMAL-NEXT: ld.param.b32 %r1, [frem_f32_imm2_param_0]; -; NORMAL-NEXT: mov.b32 %r2, 0f40E00000; -; NORMAL-NEXT: div.rn.f32 %r3, %r2, %r1; -; NORMAL-NEXT: cvt.rzi.f32.f32 %r4, %r3; -; NORMAL-NEXT: neg.f32 %r5, %r4; -; NORMAL-NEXT: fma.rn.f32 %r6, %r5, %r1, 0f40E00000; -; NORMAL-NEXT: testp.infinite.f32 %p1, %r1; -; NORMAL-NEXT: selp.f32 %r7, 0f40E00000, %r6, %p1; -; NORMAL-NEXT: st.param.b32 [func_retval0], %r7; -; NORMAL-NEXT: ret; +; CHECK-LABEL: frem_f32_imm2( +; CHECK: { +; CHECK-NEXT: .reg .pred %p<2>; +; CHECK-NEXT: .reg .b32 %r<8>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_imm2_param_0]; +; CHECK-NEXT: mov.b32 %r2, 0f40E00000; +; CHECK-NEXT: div.rn.f32 %r3, %r2, %r1; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r1, 0f40E00000; +; CHECK-NEXT: testp.infinite.f32 %p1, %r1; +; CHECK-NEXT: selp.f32 %r7, 0f40E00000, %r6, %p1; +; CHECK-NEXT: st.param.b32 [func_retval0], %r7; +; CHECK-NEXT: ret; %r = frem float 7.0, %a ret float %r } + +define float @frem_f32_imm2_fast(float %a) { +; CHECK-LABEL: frem_f32_imm2_fast( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<7>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.b32 %r1, [frem_f32_imm2_fast_param_0]; +; CHECK-NEXT: mov.b32 %r2, 0f40E00000; +; CHECK-NEXT: div.approx.f32 %r3, %r2, %r1; +; CHECK-NEXT: cvt.rzi.f32.f32 %r4, %r3; +; CHECK-NEXT: neg.f32 %r5, %r4; +; CHECK-NEXT: fma.rn.f32 %r6, %r5, %r1, 0f40E00000; +; CHECK-NEXT: st.param.b32 [func_retval0], %r6; +; CHECK-NEXT: ret; + %r = frem afn ninf float 7.0, %a + ret float %r +} diff --git a/llvm/test/CodeGen/NVPTX/sqrt-approx.ll b/llvm/test/CodeGen/NVPTX/sqrt-approx.ll index 3989c8e32e45..7e4e701af4cd 100644 --- a/llvm/test/CodeGen/NVPTX/sqrt-approx.ll +++ b/llvm/test/CodeGen/NVPTX/sqrt-approx.ll @@ -13,7 +13,7 @@ declare double @llvm.sqrt.f64(double) ; -- reciprocal sqrt -- -define float @test_rsqrt32(float %a) #0 { +define float @test_rsqrt32(float %a) { ; CHECK-LABEL: test_rsqrt32( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -28,7 +28,7 @@ define float @test_rsqrt32(float %a) #0 { ret float %ret } -define float @test_rsqrt_ftz(float %a) #0 #1 { +define float @test_rsqrt_ftz(float %a) #1 { ; CHECK-LABEL: test_rsqrt_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -76,7 +76,7 @@ define double @test_rsqrt64_ftz(double %a) #1 { ; -- sqrt -- -define float @test_sqrt32(float %a) #0 { +define float @test_sqrt32(float %a) { ; CHECK-LABEL: test_sqrt32( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -90,7 +90,7 @@ define float @test_sqrt32(float %a) #0 { ret float %ret } -define float @test_sqrt32_ninf(float %a) #0 { +define float @test_sqrt32_ninf(float %a) { ; CHECK-LABEL: test_sqrt32_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -108,7 +108,7 @@ define float @test_sqrt32_ninf(float %a) #0 { ret float %ret } -define float @test_sqrt_ftz(float %a) #0 #1 { +define float @test_sqrt_ftz(float %a) #1 { ; CHECK-LABEL: test_sqrt_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -122,7 +122,7 @@ define float @test_sqrt_ftz(float %a) #0 #1 { ret float %ret } -define float @test_sqrt_ftz_ninf(float %a) #0 #1 { +define float @test_sqrt_ftz_ninf(float %a) #1 { ; CHECK-LABEL: test_sqrt_ftz_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -139,7 +139,7 @@ define float @test_sqrt_ftz_ninf(float %a) #0 #1 { ret float %ret } -define double @test_sqrt64(double %a) #0 { +define double @test_sqrt64(double %a) { ; CHECK-LABEL: test_sqrt64( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<3>; @@ -156,7 +156,7 @@ define double @test_sqrt64(double %a) #0 { ; There's no sqrt.approx.f64 instruction; we emit ; reciprocal(rsqrt.approx.f64(x)). There's no non-ftz approximate reciprocal, ; so we just use the ftz version. -define double @test_sqrt64_ninf(double %a) #0 { +define double @test_sqrt64_ninf(double %a) { ; CHECK-LABEL: test_sqrt64_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -175,7 +175,7 @@ define double @test_sqrt64_ninf(double %a) #0 { ret double %ret } -define double @test_sqrt64_ftz(double %a) #0 #1 { +define double @test_sqrt64_ftz(double %a) #1 { ; CHECK-LABEL: test_sqrt64_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<3>; @@ -190,7 +190,7 @@ define double @test_sqrt64_ftz(double %a) #0 #1 { } ; There's no sqrt.approx.ftz.f64 instruction; we just use the non-ftz version. -define double @test_sqrt64_ftz_ninf(double %a) #0 #1 { +define double @test_sqrt64_ftz_ninf(double %a) #1 { ; CHECK-LABEL: test_sqrt64_ftz_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -214,7 +214,7 @@ define double @test_sqrt64_ftz_ninf(double %a) #0 #1 { ; The sqrt and rsqrt refinement algorithms both emit an rsqrt.approx, followed ; by some math. -define float @test_rsqrt32_refined(float %a) #0 #2 { +define float @test_rsqrt32_refined(float %a) #2 { ; CHECK-LABEL: test_rsqrt32_refined( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<7>; @@ -229,11 +229,11 @@ define float @test_rsqrt32_refined(float %a) #0 #2 { ; CHECK-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-NEXT: ret; %val = tail call float @llvm.sqrt.f32(float %a) - %ret = fdiv arcp float 1.0, %val + %ret = fdiv arcp contract float 1.0, %val ret float %ret } -define float @test_sqrt32_refined(float %a) #0 #2 { +define float @test_sqrt32_refined(float %a) #2 { ; CHECK-LABEL: test_sqrt32_refined( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -247,7 +247,7 @@ define float @test_sqrt32_refined(float %a) #0 #2 { ret float %ret } -define float @test_sqrt32_refined_ninf(float %a) #0 #2 { +define float @test_sqrt32_refined_ninf(float %a) #2 { ; CHECK-LABEL: test_sqrt32_refined_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -265,11 +265,11 @@ define float @test_sqrt32_refined_ninf(float %a) #0 #2 { ; CHECK-NEXT: selp.f32 %r8, 0f00000000, %r6, %p1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r8; ; CHECK-NEXT: ret; - %ret = tail call ninf afn float @llvm.sqrt.f32(float %a) + %ret = tail call ninf afn contract float @llvm.sqrt.f32(float %a) ret float %ret } -define double @test_rsqrt64_refined(double %a) #0 #2 { +define double @test_rsqrt64_refined(double %a) #2 { ; CHECK-LABEL: test_rsqrt64_refined( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<7>; @@ -284,11 +284,11 @@ define double @test_rsqrt64_refined(double %a) #0 #2 { ; CHECK-NEXT: st.param.b64 [func_retval0], %rd6; ; CHECK-NEXT: ret; %val = tail call double @llvm.sqrt.f64(double %a) - %ret = fdiv arcp double 1.0, %val + %ret = fdiv arcp contract double 1.0, %val ret double %ret } -define double @test_sqrt64_refined(double %a) #0 #2 { +define double @test_sqrt64_refined(double %a) #2 { ; CHECK-LABEL: test_sqrt64_refined( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<3>; @@ -302,7 +302,7 @@ define double @test_sqrt64_refined(double %a) #0 #2 { ret double %ret } -define double @test_sqrt64_refined_ninf(double %a) #0 #2 { +define double @test_sqrt64_refined_ninf(double %a) #2 { ; CHECK-LABEL: test_sqrt64_refined_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -320,13 +320,13 @@ define double @test_sqrt64_refined_ninf(double %a) #0 #2 { ; CHECK-NEXT: selp.f64 %rd8, 0d0000000000000000, %rd6, %p1; ; CHECK-NEXT: st.param.b64 [func_retval0], %rd8; ; CHECK-NEXT: ret; - %ret = tail call ninf afn double @llvm.sqrt.f64(double %a) + %ret = tail call ninf afn contract double @llvm.sqrt.f64(double %a) ret double %ret } ; -- refined sqrt and rsqrt with ftz enabled -- -define float @test_rsqrt32_refined_ftz(float %a) #0 #1 #2 { +define float @test_rsqrt32_refined_ftz(float %a) #1 #2 { ; CHECK-LABEL: test_rsqrt32_refined_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<7>; @@ -341,11 +341,11 @@ define float @test_rsqrt32_refined_ftz(float %a) #0 #1 #2 { ; CHECK-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-NEXT: ret; %val = tail call float @llvm.sqrt.f32(float %a) - %ret = fdiv arcp float 1.0, %val + %ret = fdiv arcp contract float 1.0, %val ret float %ret } -define float @test_sqrt32_refined_ftz(float %a) #0 #1 #2 { +define float @test_sqrt32_refined_ftz(float %a) #1 #2 { ; CHECK-LABEL: test_sqrt32_refined_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -359,7 +359,7 @@ define float @test_sqrt32_refined_ftz(float %a) #0 #1 #2 { ret float %ret } -define float @test_sqrt32_refined_ftz_ninf(float %a) #0 #1 #2 { +define float @test_sqrt32_refined_ftz_ninf(float %a) #1 #2 { ; CHECK-LABEL: test_sqrt32_refined_ftz_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -376,12 +376,12 @@ define float @test_sqrt32_refined_ftz_ninf(float %a) #0 #1 #2 { ; CHECK-NEXT: selp.f32 %r7, 0f00000000, %r6, %p1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r7; ; CHECK-NEXT: ret; - %ret = tail call ninf afn float @llvm.sqrt.f32(float %a) + %ret = tail call ninf afn contract float @llvm.sqrt.f32(float %a) ret float %ret } ; There's no rsqrt.approx.ftz.f64, so we just use the non-ftz version. -define double @test_rsqrt64_refined_ftz(double %a) #0 #1 #2 { +define double @test_rsqrt64_refined_ftz(double %a) #1 #2 { ; CHECK-LABEL: test_rsqrt64_refined_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<7>; @@ -396,11 +396,11 @@ define double @test_rsqrt64_refined_ftz(double %a) #0 #1 #2 { ; CHECK-NEXT: st.param.b64 [func_retval0], %rd6; ; CHECK-NEXT: ret; %val = tail call double @llvm.sqrt.f64(double %a) - %ret = fdiv arcp double 1.0, %val + %ret = fdiv arcp contract double 1.0, %val ret double %ret } -define double @test_sqrt64_refined_ftz(double %a) #0 #1 #2 { +define double @test_sqrt64_refined_ftz(double %a) #1 #2 { ; CHECK-LABEL: test_sqrt64_refined_ftz( ; CHECK: { ; CHECK-NEXT: .reg .b64 %rd<3>; @@ -414,7 +414,7 @@ define double @test_sqrt64_refined_ftz(double %a) #0 #1 #2 { ret double %ret } -define double @test_sqrt64_refined_ftz_ninf(double %a) #0 #1 #2 { +define double @test_sqrt64_refined_ftz_ninf(double %a) #1 #2 { ; CHECK-LABEL: test_sqrt64_refined_ftz_ninf( ; CHECK: { ; CHECK-NEXT: .reg .pred %p<2>; @@ -432,10 +432,9 @@ define double @test_sqrt64_refined_ftz_ninf(double %a) #0 #1 #2 { ; CHECK-NEXT: selp.f64 %rd8, 0d0000000000000000, %rd6, %p1; ; CHECK-NEXT: st.param.b64 [func_retval0], %rd8; ; CHECK-NEXT: ret; - %ret = tail call ninf afn double @llvm.sqrt.f64(double %a) + %ret = tail call ninf afn contract double @llvm.sqrt.f64(double %a) ret double %ret } -attributes #0 = { "unsafe-fp-math" = "true" } attributes #1 = { "denormal-fp-math-f32" = "preserve-sign,preserve-sign" } attributes #2 = { "reciprocal-estimates" = "rsqrtf:1,rsqrtd:1,sqrtf:1,sqrtd:1" } diff --git a/llvm/test/CodeGen/PowerPC/memintr32.ll b/llvm/test/CodeGen/PowerPC/milicode32.ll index 4f0a9960a546..a2af6d413b4b 100644 --- a/llvm/test/CodeGen/PowerPC/memintr32.ll +++ b/llvm/test/CodeGen/PowerPC/milicode32.ll @@ -35,5 +35,37 @@ entry: declare i32 @memcmp(ptr noundef captures(none), ptr noundef captures(none), i32 noundef) nounwind +define i32 @strlen_test(ptr noundef %str) nounwind { +; CHECK-AIX-32-P9-LABEL: strlen_test: +; CHECK-AIX-32-P9: # %bb.0: # %entry +; CHECK-AIX-32-P9-NEXT: mflr r0 +; CHECK-AIX-32-P9-NEXT: stwu r1, -64(r1) +; CHECK-AIX-32-P9-NEXT: stw r0, 72(r1) +; CHECK-AIX-32-P9-NEXT: stw r3, 60(r1) +; CHECK-AIX-32-P9-NEXT: bl .strlen[PR] +; CHECK-AIX-32-P9-NEXT: nop +; CHECK-AIX-32-P9-NEXT: addi r1, r1, 64 +; CHECK-AIX-32-P9-NEXT: lwz r0, 8(r1) +; CHECK-AIX-32-P9-NEXT: mtlr r0 +; CHECK-AIX-32-P9-NEXT: blr +; +; CHECK-LINUX32-P9-LABEL: strlen_test: +; CHECK-LINUX32-P9: # %bb.0: # %entry +; CHECK-LINUX32-P9-NEXT: mflr r0 +; CHECK-LINUX32-P9-NEXT: stwu r1, -16(r1) +; CHECK-LINUX32-P9-NEXT: stw r0, 20(r1) +; CHECK-LINUX32-P9-NEXT: stw r3, 12(r1) +; CHECK-LINUX32-P9-NEXT: bl strlen +; CHECK-LINUX32-P9-NEXT: lwz r0, 20(r1) +; CHECK-LINUX32-P9-NEXT: addi r1, r1, 16 +; CHECK-LINUX32-P9-NEXT: mtlr r0 +; CHECK-LINUX32-P9-NEXT: blr +entry: + %str.addr = alloca ptr, align 4 + store ptr %str, ptr %str.addr, align 4 + %0 = load ptr, ptr %str.addr, align 4 + %call = call i32 @strlen(ptr noundef %0) + ret i32 %call +} - +declare i32 @strlen(ptr noundef) nounwind diff --git a/llvm/test/CodeGen/PowerPC/memintr64.ll b/llvm/test/CodeGen/PowerPC/milicode64.ll index 0b0e556e89b5..0f0585d9028a 100644 --- a/llvm/test/CodeGen/PowerPC/memintr64.ll +++ b/llvm/test/CodeGen/PowerPC/milicode64.ll @@ -52,4 +52,51 @@ entry: declare i32 @memcmp(ptr noundef captures(none), ptr noundef captures(none), i64 noundef) nounwind +define i64 @strlen_test(ptr noundef %str) nounwind { +; CHECK-LE-P9-LABEL: strlen_test: +; CHECK-LE-P9: # %bb.0: # %entry +; CHECK-LE-P9-NEXT: mflr r0 +; CHECK-LE-P9-NEXT: stdu r1, -48(r1) +; CHECK-LE-P9-NEXT: std r0, 64(r1) +; CHECK-LE-P9-NEXT: std r3, 40(r1) +; CHECK-LE-P9-NEXT: bl strlen +; CHECK-LE-P9-NEXT: nop +; CHECK-LE-P9-NEXT: addi r1, r1, 48 +; CHECK-LE-P9-NEXT: ld r0, 16(r1) +; CHECK-LE-P9-NEXT: mtlr r0 +; CHECK-LE-P9-NEXT: blr +; +; CHECK-BE-P9-LABEL: strlen_test: +; CHECK-BE-P9: # %bb.0: # %entry +; CHECK-BE-P9-NEXT: mflr r0 +; CHECK-BE-P9-NEXT: stdu r1, -128(r1) +; CHECK-BE-P9-NEXT: std r0, 144(r1) +; CHECK-BE-P9-NEXT: std r3, 120(r1) +; CHECK-BE-P9-NEXT: bl strlen +; CHECK-BE-P9-NEXT: nop +; CHECK-BE-P9-NEXT: addi r1, r1, 128 +; CHECK-BE-P9-NEXT: ld r0, 16(r1) +; CHECK-BE-P9-NEXT: mtlr r0 +; CHECK-BE-P9-NEXT: blr +; +; CHECK-AIX-64-P9-LABEL: strlen_test: +; CHECK-AIX-64-P9: # %bb.0: # %entry +; CHECK-AIX-64-P9-NEXT: mflr r0 +; CHECK-AIX-64-P9-NEXT: stdu r1, -128(r1) +; CHECK-AIX-64-P9-NEXT: std r0, 144(r1) +; CHECK-AIX-64-P9-NEXT: std r3, 120(r1) +; CHECK-AIX-64-P9-NEXT: bl .strlen[PR] +; CHECK-AIX-64-P9-NEXT: nop +; CHECK-AIX-64-P9-NEXT: addi r1, r1, 128 +; CHECK-AIX-64-P9-NEXT: ld r0, 16(r1) +; CHECK-AIX-64-P9-NEXT: mtlr r0 +; CHECK-AIX-64-P9-NEXT: blr +entry: + %str.addr = alloca ptr, align 8 + store ptr %str, ptr %str.addr, align 8 + %0 = load ptr, ptr %str.addr, align 8 + %call = call i64 @strlen(ptr noundef %0) + ret i64 %call +} +declare i64 @strlen(ptr noundef) nounwind diff --git a/llvm/test/CodeGen/PowerPC/nofpclass.ll b/llvm/test/CodeGen/PowerPC/nofpclass.ll new file mode 100644 index 000000000000..b08e810cd1cc --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/nofpclass.ll @@ -0,0 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s + +; TODO: Update this test after adding the proper expansion of nofpclass for +; ppc_fp128 to test with more masks and to demonstrate preserving nofpclass +; after legalization. + +define ppc_fp128 @f(ppc_fp128 nofpclass(nan) %s) { +; CHECK-LABEL: f: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: blr +entry: + ret ppc_fp128 %s +} diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll index c733a0195060..4b032781c376 100644 --- a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll +++ b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll @@ -30,16 +30,14 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr { ; CHECK-NEXT: mflr r0 ; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: stw r12, 8(r1) -; CHECK-NEXT: stdu r1, -64(r1) -; CHECK-NEXT: .cfi_def_cfa_offset 64 +; CHECK-NEXT: stdu r1, -48(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_offset lr, 16 -; CHECK-NEXT: .cfi_offset r29, -24 ; CHECK-NEXT: .cfi_offset r30, -16 ; CHECK-NEXT: .cfi_offset cr2, 8 ; CHECK-NEXT: .cfi_offset cr3, 8 ; CHECK-NEXT: .cfi_offset cr4, 8 -; CHECK-NEXT: std r29, 40(r1) # 8-byte Folded Spill -; CHECK-NEXT: std r30, 48(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill ; CHECK-NEXT: bl call_2@notoc ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_13 ; CHECK-NEXT: # %bb.1: # %bb @@ -67,11 +65,10 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr { ; CHECK-NEXT: bc 12, 4*cr3+eq, .LBB0_11 ; CHECK-NEXT: # %bb.6: # %bb32 ; CHECK-NEXT: # +; CHECK-NEXT: rlwinm r30, r30, 0, 24, 22 ; CHECK-NEXT: andi. r3, r30, 2 -; CHECK-NEXT: rlwinm r29, r30, 0, 24, 22 ; CHECK-NEXT: mcrf cr2, cr0 ; CHECK-NEXT: bl call_4@notoc -; CHECK-NEXT: mr r30, r29 ; CHECK-NEXT: beq+ cr2, .LBB0_3 ; CHECK-NEXT: # %bb.7: # %bb37 ; CHECK-NEXT: .LBB0_8: # %bb22 @@ -92,13 +89,11 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr { ; CHECK-BE-NEXT: stdu r1, -144(r1) ; CHECK-BE-NEXT: .cfi_def_cfa_offset 144 ; CHECK-BE-NEXT: .cfi_offset lr, 16 -; CHECK-BE-NEXT: .cfi_offset r28, -32 ; CHECK-BE-NEXT: .cfi_offset r29, -24 ; CHECK-BE-NEXT: .cfi_offset r30, -16 ; CHECK-BE-NEXT: .cfi_offset cr2, 8 ; CHECK-BE-NEXT: .cfi_offset cr2, 8 ; CHECK-BE-NEXT: .cfi_offset cr2, 8 -; CHECK-BE-NEXT: std r28, 112(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: std r29, 120(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: std r30, 128(r1) # 8-byte Folded Spill ; CHECK-BE-NEXT: bl call_2 @@ -131,12 +126,11 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr { ; CHECK-BE-NEXT: bc 12, 4*cr3+eq, .LBB0_11 ; CHECK-BE-NEXT: # %bb.6: # %bb32 ; CHECK-BE-NEXT: # +; CHECK-BE-NEXT: rlwinm r29, r29, 0, 24, 22 ; CHECK-BE-NEXT: andi. r3, r29, 2 -; CHECK-BE-NEXT: rlwinm r28, r29, 0, 24, 22 ; CHECK-BE-NEXT: mcrf cr2, cr0 ; CHECK-BE-NEXT: bl call_4 ; CHECK-BE-NEXT: nop -; CHECK-BE-NEXT: mr r29, r28 ; CHECK-BE-NEXT: beq+ cr2, .LBB0_3 ; CHECK-BE-NEXT: # %bb.7: # %bb37 ; CHECK-BE-NEXT: .LBB0_8: # %bb22 diff --git a/llvm/test/CodeGen/PowerPC/swaps-le-1.ll b/llvm/test/CodeGen/PowerPC/swaps-le-1.ll index f3e34101efa2..5d5445f9f473 100644 --- a/llvm/test/CodeGen/PowerPC/swaps-le-1.ll +++ b/llvm/test/CodeGen/PowerPC/swaps-le-1.ll @@ -187,34 +187,34 @@ define void @foo() { ; CHECK-P9-NEXT: .p2align 4 ; CHECK-P9-NEXT: .LBB0_1: # %vector.body ; CHECK-P9-NEXT: # -; CHECK-P9-NEXT: lxv 2, -32(6) -; CHECK-P9-NEXT: lxv 3, -32(5) -; CHECK-P9-NEXT: lxv 4, -16(5) -; CHECK-P9-NEXT: vadduwm 2, 3, 2 +; CHECK-P9-NEXT: lxv 2, -32(3) ; CHECK-P9-NEXT: lxv 3, -32(4) +; CHECK-P9-NEXT: lxv 4, -16(4) +; CHECK-P9-NEXT: vadduwm 2, 3, 2 +; CHECK-P9-NEXT: lxv 3, -32(5) ; CHECK-P9-NEXT: vmuluwm 2, 2, 3 -; CHECK-P9-NEXT: lxv 3, -16(6) -; CHECK-P9-NEXT: vadduwm 3, 4, 3 -; CHECK-P9-NEXT: lxv 4, 0(5) -; CHECK-P9-NEXT: stxv 2, -32(3) -; CHECK-P9-NEXT: lxv 2, -16(4) -; CHECK-P9-NEXT: vmuluwm 2, 3, 2 -; CHECK-P9-NEXT: lxv 3, 0(6) +; CHECK-P9-NEXT: lxv 3, -16(3) ; CHECK-P9-NEXT: vadduwm 3, 4, 3 -; CHECK-P9-NEXT: lxv 4, 16(5) -; CHECK-P9-NEXT: addi 5, 5, 64 -; CHECK-P9-NEXT: stxv 2, -16(3) -; CHECK-P9-NEXT: lxv 2, 0(4) +; CHECK-P9-NEXT: lxv 4, 0(4) +; CHECK-P9-NEXT: stxv 2, -32(6) +; CHECK-P9-NEXT: lxv 2, -16(5) ; CHECK-P9-NEXT: vmuluwm 2, 3, 2 -; CHECK-P9-NEXT: lxv 3, 16(6) -; CHECK-P9-NEXT: addi 6, 6, 64 +; CHECK-P9-NEXT: lxv 3, 0(3) ; CHECK-P9-NEXT: vadduwm 3, 4, 3 -; CHECK-P9-NEXT: stxv 2, 0(3) -; CHECK-P9-NEXT: lxv 2, 16(4) +; CHECK-P9-NEXT: lxv 4, 16(4) ; CHECK-P9-NEXT: addi 4, 4, 64 +; CHECK-P9-NEXT: stxv 2, -16(6) +; CHECK-P9-NEXT: lxv 2, 0(5) ; CHECK-P9-NEXT: vmuluwm 2, 3, 2 -; CHECK-P9-NEXT: stxv 2, 16(3) +; CHECK-P9-NEXT: lxv 3, 16(3) ; CHECK-P9-NEXT: addi 3, 3, 64 +; CHECK-P9-NEXT: vadduwm 3, 4, 3 +; CHECK-P9-NEXT: stxv 2, 0(6) +; CHECK-P9-NEXT: lxv 2, 16(5) +; CHECK-P9-NEXT: addi 5, 5, 64 +; CHECK-P9-NEXT: vmuluwm 2, 3, 2 +; CHECK-P9-NEXT: stxv 2, 16(6) +; CHECK-P9-NEXT: addi 6, 6, 64 ; CHECK-P9-NEXT: bdnz .LBB0_1 ; CHECK-P9-NEXT: # %bb.2: # %for.end ; CHECK-P9-NEXT: blr diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll index dfa76a2e1531..9ec8c32e989b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-fcmp.ll @@ -138,7 +138,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -148,8 +148,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2 -; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srliw a0, a0, 31 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -446,7 +445,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -456,8 +455,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srliw a0, a0, 31 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll index 475b67bda9ae..380751c907c0 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-fcmp.ll @@ -138,7 +138,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -148,8 +148,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2 -; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srliw a0, a0, 31 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -431,7 +430,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -441,8 +440,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srliw a0, a0, 31 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll index f032756e007b..c7938a718de7 100644 --- a/llvm/test/CodeGen/RISCV/alu64.ll +++ b/llvm/test/CodeGen/RISCV/alu64.ll @@ -37,7 +37,7 @@ define i64 @slti(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: beqz a1, .LBB1_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: slti a0, a1, 0 +; RV32I-NEXT: srli a0, a1, 31 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB1_2: diff --git a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll index 4efc224ab1ca..551d8864033f 100644 --- a/llvm/test/CodeGen/RISCV/arith-with-overflow.ll +++ b/llvm/test/CodeGen/RISCV/arith-with-overflow.ll @@ -12,7 +12,7 @@ define i1 @sadd(i32 %a, i32 %b, ptr %c) nounwind { ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: add a3, a0, a1 ; RV32I-NEXT: slt a0, a3, a0 -; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: srli a1, a1, 31 ; RV32I-NEXT: xor a0, a1, a0 ; RV32I-NEXT: sw a3, 0(a2) ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/bittest.ll b/llvm/test/CodeGen/RISCV/bittest.ll index fa6892be44d9..95c577f833a3 100644 --- a/llvm/test/CodeGen/RISCV/bittest.ll +++ b/llvm/test/CodeGen/RISCV/bittest.ll @@ -187,14 +187,14 @@ define i64 @bittest_31_i64(i64 %a) nounwind { ; ; RV64ZBS-LABEL: bittest_31_i64: ; RV64ZBS: # %bb.0: -; RV64ZBS-NEXT: not a0, a0 -; RV64ZBS-NEXT: bexti a0, a0, 31 +; RV64ZBS-NEXT: srliw a0, a0, 31 +; RV64ZBS-NEXT: xori a0, a0, 1 ; RV64ZBS-NEXT: ret ; ; RV64XTHEADBS-LABEL: bittest_31_i64: ; RV64XTHEADBS: # %bb.0: -; RV64XTHEADBS-NEXT: not a0, a0 -; RV64XTHEADBS-NEXT: th.tst a0, a0, 31 +; RV64XTHEADBS-NEXT: srliw a0, a0, 31 +; RV64XTHEADBS-NEXT: xori a0, a0, 1 ; RV64XTHEADBS-NEXT: ret %shr = lshr i64 %a, 31 %not = xor i64 %shr, -1 @@ -3507,3 +3507,77 @@ define void @bit_64_1_nz_branch_i64(i64 %0) { 5: ret void } + +define i32 @bittest_31_andeq0_i64(i64 %x) { +; RV32-LABEL: bittest_31_andeq0_i64: +; RV32: # %bb.0: +; RV32-NEXT: srli a0, a0, 31 +; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: ret +; +; RV64-LABEL: bittest_31_andeq0_i64: +; RV64: # %bb.0: +; RV64-NEXT: srliw a0, a0, 31 +; RV64-NEXT: xori a0, a0, 1 +; RV64-NEXT: ret + %and = and i64 %x, 2147483648 + %cmp = icmp eq i64 %and, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define i32 @bittest_63_andeq0_i64(i64 %x) { +; RV32-LABEL: bittest_63_andeq0_i64: +; RV32: # %bb.0: +; RV32-NEXT: srli a1, a1, 31 +; RV32-NEXT: xori a0, a1, 1 +; RV32-NEXT: ret +; +; RV64-LABEL: bittest_63_andeq0_i64: +; RV64: # %bb.0: +; RV64-NEXT: srli a0, a0, 63 +; RV64-NEXT: xori a0, a0, 1 +; RV64-NEXT: ret + %and = and i64 %x, 9223372036854775808 + %cmp = icmp eq i64 %and, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define i32 @bittest_31_slt0_i32(i32 %x, i1 %y) { +; RV32-LABEL: bittest_31_slt0_i32: +; RV32: # %bb.0: +; RV32-NEXT: srli a0, a0, 31 +; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: ret +; +; RV64-LABEL: bittest_31_slt0_i32: +; RV64: # %bb.0: +; RV64-NEXT: srliw a0, a0, 31 +; RV64-NEXT: and a0, a0, a1 +; RV64-NEXT: ret + %cmp = icmp slt i32 %x, 0 + %and = and i1 %cmp, %y + %ext = zext i1 %and to i32 + ret i32 %ext +} + +define i32 @bittest_63_slt0_i64(i32 %x, i1 %y) { +; RV32-LABEL: bittest_63_slt0_i64: +; RV32: # %bb.0: +; RV32-NEXT: srai a0, a0, 31 +; RV32-NEXT: srli a0, a0, 31 +; RV32-NEXT: and a0, a0, a1 +; RV32-NEXT: ret +; +; RV64-LABEL: bittest_63_slt0_i64: +; RV64: # %bb.0: +; RV64-NEXT: srliw a0, a0, 31 +; RV64-NEXT: and a0, a0, a1 +; RV64-NEXT: ret + %ext = sext i32 %x to i64 + %cmp = icmp slt i64 %ext, 0 + %and = and i1 %cmp, %y + %cond = zext i1 %and to i32 + ret i32 %cond +} diff --git a/llvm/test/CodeGen/RISCV/condbinops.ll b/llvm/test/CodeGen/RISCV/condbinops.ll index dc81c13bfb6a..91052bce9704 100644 --- a/llvm/test/CodeGen/RISCV/condbinops.ll +++ b/llvm/test/CodeGen/RISCV/condbinops.ll @@ -459,7 +459,7 @@ define i64 @shl64(i64 %x, i64 %y, i1 %c) { ; RV32ZICOND-NEXT: addi a4, a2, -32 ; RV32ZICOND-NEXT: sll a1, a1, a2 ; RV32ZICOND-NEXT: not a2, a2 -; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: srli a4, a4, 31 ; RV32ZICOND-NEXT: srl a2, a3, a2 ; RV32ZICOND-NEXT: czero.nez a3, a0, a4 ; RV32ZICOND-NEXT: or a1, a1, a2 @@ -534,7 +534,7 @@ define i64 @ashr64(i64 %x, i64 %y, i1 %c) { ; RV32ZICOND-NEXT: addi a4, a2, -32 ; RV32ZICOND-NEXT: srl a0, a0, a2 ; RV32ZICOND-NEXT: not a2, a2 -; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: srli a4, a4, 31 ; RV32ZICOND-NEXT: sll a2, a3, a2 ; RV32ZICOND-NEXT: czero.nez a3, a1, a4 ; RV32ZICOND-NEXT: or a0, a0, a2 @@ -610,7 +610,7 @@ define i64 @lshr64(i64 %x, i64 %y, i1 %c) { ; RV32ZICOND-NEXT: addi a4, a2, -32 ; RV32ZICOND-NEXT: srl a0, a0, a2 ; RV32ZICOND-NEXT: not a2, a2 -; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: srli a4, a4, 31 ; RV32ZICOND-NEXT: sll a2, a3, a2 ; RV32ZICOND-NEXT: czero.nez a3, a1, a4 ; RV32ZICOND-NEXT: or a0, a0, a2 diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll index a2e6186e051b..9c81bc285134 100644 --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -405,7 +405,7 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind { ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 @@ -446,8 +446,8 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: j .LBB6_3 ; RV64I-NEXT: .LBB6_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB6_3: # %start ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -819,7 +819,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: slti a1, s4, 0 +; RV32I-NEXT: srli a1, s4, 31 ; RV32I-NEXT: sgtz a2, s2 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a3, a1, -1 @@ -1029,7 +1029,7 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 @@ -1055,7 +1055,7 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: addi s1, a0, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __fixunsdfdi @@ -1898,9 +1898,9 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind { ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: j .LBB28_3 ; RV32I-NEXT: .LBB28_2: -; RV32I-NEXT: slti a2, s0, 0 -; RV32I-NEXT: addi a2, a2, -1 -; RV32I-NEXT: and a0, a2, a0 +; RV32I-NEXT: srli s0, s0, 31 +; RV32I-NEXT: addi s0, s0, -1 +; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: .LBB28_3: # %start ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -1937,8 +1937,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind { ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: j .LBB28_3 ; RV64I-NEXT: .LBB28_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB28_3: # %start ; RV64I-NEXT: and a0, a0, a1 @@ -2271,9 +2271,9 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind { ; RV32I-NEXT: li a0, 255 ; RV32I-NEXT: j .LBB32_3 ; RV32I-NEXT: .LBB32_2: -; RV32I-NEXT: slti a1, s0, 0 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: and a0, a1, a0 +; RV32I-NEXT: srli s0, s0, 31 +; RV32I-NEXT: addi s0, s0, -1 +; RV32I-NEXT: and a0, s0, a0 ; RV32I-NEXT: .LBB32_3: # %start ; RV32I-NEXT: zext.b a0, a0 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload @@ -2307,8 +2307,8 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind { ; RV64I-NEXT: li a0, 255 ; RV64I-NEXT: j .LBB32_3 ; RV64I-NEXT: .LBB32_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB32_3: # %start ; RV64I-NEXT: zext.b a0, a0 @@ -2386,7 +2386,7 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind { ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 @@ -2427,8 +2427,8 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: j .LBB33_3 ; RV64I-NEXT: .LBB33_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB33_3: # %start ; RV64I-NEXT: slli a0, a0, 32 diff --git a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll index 7c5332f71986..b1c63af3e7e0 100644 --- a/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll +++ b/llvm/test/CodeGen/RISCV/double-fcmp-strict.ll @@ -140,7 +140,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -151,7 +151,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -193,7 +193,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -203,7 +203,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -605,7 +605,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -616,7 +616,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -661,7 +661,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -671,7 +671,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -934,7 +934,7 @@ define i32 @fcmps_oge(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -945,7 +945,7 @@ define i32 @fcmps_oge(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -976,7 +976,7 @@ define i32 @fcmps_olt(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -986,7 +986,7 @@ define i32 @fcmps_olt(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1311,7 +1311,7 @@ define i32 @fcmps_uge(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1322,7 +1322,7 @@ define i32 @fcmps_uge(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1356,7 +1356,7 @@ define i32 @fcmps_ult(double %a, double %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1366,7 +1366,7 @@ define i32 @fcmps_ult(double %a, double %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll index f73e6865cf47..31c858917743 100644 --- a/llvm/test/CodeGen/RISCV/double-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll @@ -138,7 +138,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -149,7 +149,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -180,7 +180,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -190,7 +190,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -515,7 +515,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltdf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -526,7 +526,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltdf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -560,7 +560,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -570,7 +570,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll index 60349a0e3995..6e49d479cf0b 100644 --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -278,7 +278,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind { ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi @@ -320,8 +320,8 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: j .LBB4_3 ; RV64I-NEXT: .LBB4_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB4_3: # %start ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -736,7 +736,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: slti a1, s2, 0 +; RV32I-NEXT: srli a1, s2, 31 ; RV32I-NEXT: sgtz a2, s4 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a3, a1, -1 @@ -932,7 +932,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfdi @@ -971,7 +971,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: addi s2, a0, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __fixunssfdi @@ -1651,8 +1651,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind { ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: j .LBB26_3 ; RV32I-NEXT: .LBB26_2: -; RV32I-NEXT: slti a0, s0, 0 -; RV32I-NEXT: addi a0, a0, -1 +; RV32I-NEXT: srli s0, s0, 31 +; RV32I-NEXT: addi a0, s0, -1 ; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: .LBB26_3: # %start ; RV32I-NEXT: and a0, a0, a1 @@ -1688,8 +1688,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind { ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: j .LBB26_3 ; RV64I-NEXT: .LBB26_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB26_3: # %start ; RV64I-NEXT: and a0, a0, a1 @@ -1986,8 +1986,8 @@ define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind { ; RV32I-NEXT: li a0, 255 ; RV32I-NEXT: j .LBB30_3 ; RV32I-NEXT: .LBB30_2: -; RV32I-NEXT: slti a0, s0, 0 -; RV32I-NEXT: addi a0, a0, -1 +; RV32I-NEXT: srli s0, s0, 31 +; RV32I-NEXT: addi a0, s0, -1 ; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: .LBB30_3: # %start ; RV32I-NEXT: zext.b a0, a0 @@ -2020,8 +2020,8 @@ define zeroext i8 @fcvt_wu_s_sat_i8(float %a) nounwind { ; RV64I-NEXT: li a0, 255 ; RV64I-NEXT: j .LBB30_3 ; RV64I-NEXT: .LBB30_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB30_3: # %start ; RV64I-NEXT: zext.b a0, a0 @@ -2087,7 +2087,7 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi @@ -2129,8 +2129,8 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: j .LBB31_3 ; RV64I-NEXT: .LBB31_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB31_3: # %start ; RV64I-NEXT: slli a0, a0, 32 diff --git a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll index fd3baa057525..7cdd1826b452 100644 --- a/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp-strict.ll @@ -117,7 +117,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -128,7 +128,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -161,7 +161,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -171,7 +171,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -492,7 +492,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -503,7 +503,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -538,7 +538,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -548,7 +548,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -770,7 +770,7 @@ define i32 @fcmps_oge(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -781,7 +781,7 @@ define i32 @fcmps_oge(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -807,7 +807,7 @@ define i32 @fcmps_olt(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -817,7 +817,7 @@ define i32 @fcmps_olt(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -1087,7 +1087,7 @@ define i32 @fcmps_uge(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1098,7 +1098,7 @@ define i32 @fcmps_uge(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1126,7 +1126,7 @@ define i32 @fcmps_ult(float %a, float %b) nounwind strictfp { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -1136,7 +1136,7 @@ define i32 @fcmps_ult(float %a, float %b) nounwind strictfp { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll index 2e9c39f331bb..cec658024762 100644 --- a/llvm/test/CodeGen/RISCV/float-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll @@ -123,7 +123,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -134,7 +134,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -160,7 +160,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -170,7 +170,7 @@ define i32 @fcmp_olt(float %a, float %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret @@ -440,7 +440,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __ltsf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -451,7 +451,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __ltsf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: xori a0, a0, 1 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -479,7 +479,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -489,7 +489,7 @@ define i32 @fcmp_ult(float %a, float %b) nounwind { ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll index ed50042f54ab..8b8a3257a002 100644 --- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll @@ -1634,7 +1634,7 @@ define i1 @fpclass(float %x) { ; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: addi a5, a5, -1 ; RV32I-NEXT: sltu a2, a5, a2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: seqz a1, a1 ; RV32I-NEXT: seqz a5, a6 ; RV32I-NEXT: srli a4, a4, 24 @@ -1660,8 +1660,7 @@ define i1 @fpclass(float %x) { ; RV64I-NEXT: add a4, a5, a4 ; RV64I-NEXT: addi a5, a5, -1 ; RV64I-NEXT: sltu a2, a5, a2 -; RV64I-NEXT: sext.w a0, a0 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srliw a0, a0, 31 ; RV64I-NEXT: seqz a1, a1 ; RV64I-NEXT: seqz a5, a6 ; RV64I-NEXT: srliw a4, a4, 24 @@ -2092,19 +2091,18 @@ define i1 @isnegfinite_fpclass(float %x) { ; RV32I-NEXT: lui a2, 522240 ; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: slt a1, a1, a2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: isnegfinite_fpclass: ; RV64I: # %bb.0: -; RV64I-NEXT: sext.w a1, a0 -; RV64I-NEXT: slli a0, a0, 33 +; RV64I-NEXT: slli a1, a0, 33 ; RV64I-NEXT: lui a2, 522240 -; RV64I-NEXT: srli a0, a0, 33 -; RV64I-NEXT: slt a0, a0, a2 -; RV64I-NEXT: slti a1, a1, 0 -; RV64I-NEXT: and a0, a0, a1 +; RV64I-NEXT: srli a1, a1, 33 +; RV64I-NEXT: slt a1, a1, a2 +; RV64I-NEXT: srliw a0, a0, 31 +; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 56) ; 0x38 = "-finite" ret i1 %1 diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll index 477a7d1ce7b6..aa65ebecbe56 100644 --- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll +++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll @@ -909,7 +909,7 @@ define i64 @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind { ; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: beqz a3, .LBB20_3 ; RV32I-NEXT: # %bb.1: # %entry -; RV32I-NEXT: slti a1, s1, 0 +; RV32I-NEXT: srli a1, s1, 31 ; RV32I-NEXT: beqz a1, .LBB20_4 ; RV32I-NEXT: .LBB20_2: ; RV32I-NEXT: li s3, 0 @@ -974,7 +974,7 @@ define i64 @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind { ; RV32I-MEDIUM-NEXT: mv s2, a2 ; RV32I-MEDIUM-NEXT: beqz a3, .LBB20_3 ; RV32I-MEDIUM-NEXT: # %bb.1: # %entry -; RV32I-MEDIUM-NEXT: slti a1, s1, 0 +; RV32I-MEDIUM-NEXT: srli a1, s1, 31 ; RV32I-MEDIUM-NEXT: beqz a1, .LBB20_4 ; RV32I-MEDIUM-NEXT: .LBB20_2: ; RV32I-MEDIUM-NEXT: li s3, 0 diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll index e7719dc70660..1a69106a485e 100644 --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -3475,7 +3475,7 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind { ; RV32-NEXT: beqz a1, .LBB50_4 ; RV32-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NEXT: # in Loop: Header=BB50_2 Depth=1 -; RV32-NEXT: slti a0, a1, 0 +; RV32-NEXT: srli a0, a1, 31 ; RV32-NEXT: mv a2, a4 ; RV32-NEXT: bnez a0, .LBB50_1 ; RV32-NEXT: j .LBB50_5 diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll index 519f1e851a83..18d071cc39bb 100644 --- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll +++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll @@ -22,7 +22,7 @@ define i32 @stest_f64i32(double %x) { ; RV32IF-NEXT: addi a3, a2, -1 ; RV32IF-NEXT: beqz a1, .LBB0_2 ; RV32IF-NEXT: # %bb.1: # %entry -; RV32IF-NEXT: slti a4, a1, 0 +; RV32IF-NEXT: srli a4, a1, 31 ; RV32IF-NEXT: j .LBB0_3 ; RV32IF-NEXT: .LBB0_2: ; RV32IF-NEXT: sltu a4, a0, a3 @@ -36,7 +36,7 @@ define i32 @stest_f64i32(double %x) { ; RV32IF-NEXT: li a3, -1 ; RV32IF-NEXT: beq a1, a3, .LBB0_7 ; RV32IF-NEXT: # %bb.6: # %entry -; RV32IF-NEXT: slti a1, a1, 0 +; RV32IF-NEXT: srli a1, a1, 31 ; RV32IF-NEXT: xori a1, a1, 1 ; RV32IF-NEXT: beqz a1, .LBB0_8 ; RV32IF-NEXT: j .LBB0_9 @@ -185,7 +185,7 @@ define i32 @ustest_f64i32(double %x) { ; RV32IF-NEXT: call __fixdfdi ; RV32IF-NEXT: beqz a1, .LBB2_2 ; RV32IF-NEXT: # %bb.1: # %entry -; RV32IF-NEXT: slti a2, a1, 0 +; RV32IF-NEXT: srli a2, a1, 31 ; RV32IF-NEXT: j .LBB2_3 ; RV32IF-NEXT: .LBB2_2: ; RV32IF-NEXT: sltiu a2, a0, -1 @@ -373,7 +373,7 @@ define i32 @stest_f16i32(half %x) { ; RV32-NEXT: addi a3, a2, -1 ; RV32-NEXT: beqz a1, .LBB6_2 ; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: slti a4, a1, 0 +; RV32-NEXT: srli a4, a1, 31 ; RV32-NEXT: j .LBB6_3 ; RV32-NEXT: .LBB6_2: ; RV32-NEXT: sltu a4, a0, a3 @@ -387,7 +387,7 @@ define i32 @stest_f16i32(half %x) { ; RV32-NEXT: li a3, -1 ; RV32-NEXT: beq a1, a3, .LBB6_7 ; RV32-NEXT: # %bb.6: # %entry -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: xori a1, a1, 1 ; RV32-NEXT: beqz a1, .LBB6_8 ; RV32-NEXT: j .LBB6_9 @@ -494,7 +494,7 @@ define i32 @ustest_f16i32(half %x) { ; RV32-NEXT: call __fixsfdi ; RV32-NEXT: beqz a1, .LBB8_2 ; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: slti a2, a1, 0 +; RV32-NEXT: srli a2, a1, 31 ; RV32-NEXT: j .LBB8_3 ; RV32-NEXT: .LBB8_2: ; RV32-NEXT: sltiu a2, a0, -1 @@ -1108,7 +1108,7 @@ define i64 @stest_f64i64(double %x) { ; RV32IF-NEXT: or a7, a2, a4 ; RV32IF-NEXT: beqz a7, .LBB18_4 ; RV32IF-NEXT: .LBB18_3: # %entry -; RV32IF-NEXT: slti a6, a4, 0 +; RV32IF-NEXT: srli a6, a4, 31 ; RV32IF-NEXT: .LBB18_4: # %entry ; RV32IF-NEXT: neg a7, a6 ; RV32IF-NEXT: addi t0, a6, -1 @@ -1130,8 +1130,8 @@ define i64 @stest_f64i64(double %x) { ; RV32IF-NEXT: li a5, -1 ; RV32IF-NEXT: beq a2, a5, .LBB18_11 ; RV32IF-NEXT: # %bb.10: # %entry -; RV32IF-NEXT: slti a0, a4, 0 -; RV32IF-NEXT: xori a0, a0, 1 +; RV32IF-NEXT: srli a4, a4, 31 +; RV32IF-NEXT: xori a0, a4, 1 ; RV32IF-NEXT: .LBB18_11: # %entry ; RV32IF-NEXT: bnez a0, .LBB18_13 ; RV32IF-NEXT: # %bb.12: # %entry @@ -1156,7 +1156,7 @@ define i64 @stest_f64i64(double %x) { ; RV64IF-NEXT: srli a3, a2, 1 ; RV64IF-NEXT: beqz a1, .LBB18_2 ; RV64IF-NEXT: # %bb.1: # %entry -; RV64IF-NEXT: slti a4, a1, 0 +; RV64IF-NEXT: srli a4, a1, 63 ; RV64IF-NEXT: j .LBB18_3 ; RV64IF-NEXT: .LBB18_2: ; RV64IF-NEXT: sltu a4, a0, a3 @@ -1170,8 +1170,8 @@ define i64 @stest_f64i64(double %x) { ; RV64IF-NEXT: slli a1, a2, 63 ; RV64IF-NEXT: beq a5, a2, .LBB18_7 ; RV64IF-NEXT: # %bb.6: # %entry -; RV64IF-NEXT: slti a2, a5, 0 -; RV64IF-NEXT: xori a2, a2, 1 +; RV64IF-NEXT: srli a5, a5, 63 +; RV64IF-NEXT: xori a2, a5, 1 ; RV64IF-NEXT: beqz a2, .LBB18_8 ; RV64IF-NEXT: j .LBB18_9 ; RV64IF-NEXT: .LBB18_7: @@ -1211,7 +1211,7 @@ define i64 @stest_f64i64(double %x) { ; RV32IFD-NEXT: or a7, a2, a4 ; RV32IFD-NEXT: beqz a7, .LBB18_4 ; RV32IFD-NEXT: .LBB18_3: # %entry -; RV32IFD-NEXT: slti a6, a4, 0 +; RV32IFD-NEXT: srli a6, a4, 31 ; RV32IFD-NEXT: .LBB18_4: # %entry ; RV32IFD-NEXT: neg a7, a6 ; RV32IFD-NEXT: addi t0, a6, -1 @@ -1233,8 +1233,8 @@ define i64 @stest_f64i64(double %x) { ; RV32IFD-NEXT: li a5, -1 ; RV32IFD-NEXT: beq a2, a5, .LBB18_11 ; RV32IFD-NEXT: # %bb.10: # %entry -; RV32IFD-NEXT: slti a0, a4, 0 -; RV32IFD-NEXT: xori a0, a0, 1 +; RV32IFD-NEXT: srli a4, a4, 31 +; RV32IFD-NEXT: xori a0, a4, 1 ; RV32IFD-NEXT: .LBB18_11: # %entry ; RV32IFD-NEXT: bnez a0, .LBB18_13 ; RV32IFD-NEXT: # %bb.12: # %entry @@ -1363,7 +1363,7 @@ define i64 @ustest_f64i64(double %x) { ; RV32IF-NEXT: lw a0, 16(sp) ; RV32IF-NEXT: beqz a1, .LBB20_2 ; RV32IF-NEXT: # %bb.1: # %entry -; RV32IF-NEXT: slti a2, a1, 0 +; RV32IF-NEXT: srli a2, a1, 31 ; RV32IF-NEXT: j .LBB20_3 ; RV32IF-NEXT: .LBB20_2: ; RV32IF-NEXT: seqz a2, a0 @@ -1446,7 +1446,7 @@ define i64 @ustest_f64i64(double %x) { ; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: beqz a1, .LBB20_2 ; RV32IFD-NEXT: # %bb.1: # %entry -; RV32IFD-NEXT: slti a2, a1, 0 +; RV32IFD-NEXT: srli a2, a1, 31 ; RV32IFD-NEXT: j .LBB20_3 ; RV32IFD-NEXT: .LBB20_2: ; RV32IFD-NEXT: seqz a2, a0 @@ -1523,7 +1523,7 @@ define i64 @stest_f32i64(float %x) { ; RV32-NEXT: or a7, a2, a4 ; RV32-NEXT: beqz a7, .LBB21_4 ; RV32-NEXT: .LBB21_3: # %entry -; RV32-NEXT: slti a6, a4, 0 +; RV32-NEXT: srli a6, a4, 31 ; RV32-NEXT: .LBB21_4: # %entry ; RV32-NEXT: neg a7, a6 ; RV32-NEXT: addi t0, a6, -1 @@ -1545,8 +1545,8 @@ define i64 @stest_f32i64(float %x) { ; RV32-NEXT: li a5, -1 ; RV32-NEXT: beq a2, a5, .LBB21_11 ; RV32-NEXT: # %bb.10: # %entry -; RV32-NEXT: slti a0, a4, 0 -; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: srli a4, a4, 31 +; RV32-NEXT: xori a0, a4, 1 ; RV32-NEXT: .LBB21_11: # %entry ; RV32-NEXT: bnez a0, .LBB21_13 ; RV32-NEXT: # %bb.12: # %entry @@ -1643,7 +1643,7 @@ define i64 @ustest_f32i64(float %x) { ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: beqz a1, .LBB23_2 ; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: slti a2, a1, 0 +; RV32-NEXT: srli a2, a1, 31 ; RV32-NEXT: j .LBB23_3 ; RV32-NEXT: .LBB23_2: ; RV32-NEXT: seqz a2, a0 @@ -1750,7 +1750,7 @@ define i64 @stest_f16i64(half %x) { ; RV32-NEXT: or a7, a2, a4 ; RV32-NEXT: beqz a7, .LBB24_4 ; RV32-NEXT: .LBB24_3: # %entry -; RV32-NEXT: slti a6, a4, 0 +; RV32-NEXT: srli a6, a4, 31 ; RV32-NEXT: .LBB24_4: # %entry ; RV32-NEXT: neg a7, a6 ; RV32-NEXT: addi t0, a6, -1 @@ -1772,8 +1772,8 @@ define i64 @stest_f16i64(half %x) { ; RV32-NEXT: li a5, -1 ; RV32-NEXT: beq a2, a5, .LBB24_11 ; RV32-NEXT: # %bb.10: # %entry -; RV32-NEXT: slti a0, a4, 0 -; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: srli a4, a4, 31 +; RV32-NEXT: xori a0, a4, 1 ; RV32-NEXT: .LBB24_11: # %entry ; RV32-NEXT: bnez a0, .LBB24_13 ; RV32-NEXT: # %bb.12: # %entry @@ -1799,7 +1799,7 @@ define i64 @stest_f16i64(half %x) { ; RV64-NEXT: srli a3, a2, 1 ; RV64-NEXT: beqz a1, .LBB24_2 ; RV64-NEXT: # %bb.1: # %entry -; RV64-NEXT: slti a4, a1, 0 +; RV64-NEXT: srli a4, a1, 63 ; RV64-NEXT: j .LBB24_3 ; RV64-NEXT: .LBB24_2: ; RV64-NEXT: sltu a4, a0, a3 @@ -1813,8 +1813,8 @@ define i64 @stest_f16i64(half %x) { ; RV64-NEXT: slli a1, a2, 63 ; RV64-NEXT: beq a5, a2, .LBB24_7 ; RV64-NEXT: # %bb.6: # %entry -; RV64-NEXT: slti a2, a5, 0 -; RV64-NEXT: xori a2, a2, 1 +; RV64-NEXT: srli a5, a5, 63 +; RV64-NEXT: xori a2, a5, 1 ; RV64-NEXT: beqz a2, .LBB24_8 ; RV64-NEXT: j .LBB24_9 ; RV64-NEXT: .LBB24_7: @@ -1906,7 +1906,7 @@ define i64 @ustest_f16i64(half %x) { ; RV32-NEXT: lw a0, 16(sp) ; RV32-NEXT: beqz a1, .LBB26_2 ; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: slti a2, a1, 0 +; RV32-NEXT: srli a2, a1, 31 ; RV32-NEXT: j .LBB26_3 ; RV32-NEXT: .LBB26_2: ; RV32-NEXT: seqz a2, a0 @@ -2004,7 +2004,7 @@ define i32 @stest_f64i32_mm(double %x) { ; RV32IF-NEXT: addi a3, a2, -1 ; RV32IF-NEXT: beqz a1, .LBB27_2 ; RV32IF-NEXT: # %bb.1: # %entry -; RV32IF-NEXT: slti a4, a1, 0 +; RV32IF-NEXT: srli a4, a1, 31 ; RV32IF-NEXT: j .LBB27_3 ; RV32IF-NEXT: .LBB27_2: ; RV32IF-NEXT: sltu a4, a0, a3 @@ -2018,7 +2018,7 @@ define i32 @stest_f64i32_mm(double %x) { ; RV32IF-NEXT: li a3, -1 ; RV32IF-NEXT: beq a1, a3, .LBB27_7 ; RV32IF-NEXT: # %bb.6: # %entry -; RV32IF-NEXT: slti a1, a1, 0 +; RV32IF-NEXT: srli a1, a1, 31 ; RV32IF-NEXT: xori a1, a1, 1 ; RV32IF-NEXT: beqz a1, .LBB27_8 ; RV32IF-NEXT: j .LBB27_9 @@ -2171,7 +2171,7 @@ define i32 @ustest_f64i32_mm(double %x) { ; RV32IF-NEXT: neg a2, a2 ; RV32IF-NEXT: or a0, a3, a0 ; RV32IF-NEXT: and a1, a2, a1 -; RV32IF-NEXT: slti a1, a1, 0 +; RV32IF-NEXT: srli a1, a1, 31 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2337,7 +2337,7 @@ define i32 @stest_f16i32_mm(half %x) { ; RV32-NEXT: addi a3, a2, -1 ; RV32-NEXT: beqz a1, .LBB33_2 ; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: slti a4, a1, 0 +; RV32-NEXT: srli a4, a1, 31 ; RV32-NEXT: j .LBB33_3 ; RV32-NEXT: .LBB33_2: ; RV32-NEXT: sltu a4, a0, a3 @@ -2351,7 +2351,7 @@ define i32 @stest_f16i32_mm(half %x) { ; RV32-NEXT: li a3, -1 ; RV32-NEXT: beq a1, a3, .LBB33_7 ; RV32-NEXT: # %bb.6: # %entry -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: xori a1, a1, 1 ; RV32-NEXT: beqz a1, .LBB33_8 ; RV32-NEXT: j .LBB33_9 @@ -2462,7 +2462,7 @@ define i32 @ustest_f16i32_mm(half %x) { ; RV32-NEXT: neg a2, a2 ; RV32-NEXT: or a0, a3, a0 ; RV32-NEXT: and a1, a2, a1 -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3044,7 +3044,7 @@ define i64 @stest_f64i64_mm(double %x) { ; RV32IF-NEXT: or a7, a2, a4 ; RV32IF-NEXT: beqz a7, .LBB45_4 ; RV32IF-NEXT: .LBB45_3: # %entry -; RV32IF-NEXT: slti a6, a4, 0 +; RV32IF-NEXT: srli a6, a4, 31 ; RV32IF-NEXT: .LBB45_4: # %entry ; RV32IF-NEXT: neg a7, a6 ; RV32IF-NEXT: addi t0, a6, -1 @@ -3066,8 +3066,8 @@ define i64 @stest_f64i64_mm(double %x) { ; RV32IF-NEXT: li a5, -1 ; RV32IF-NEXT: beq a2, a5, .LBB45_11 ; RV32IF-NEXT: # %bb.10: # %entry -; RV32IF-NEXT: slti a0, a4, 0 -; RV32IF-NEXT: xori a0, a0, 1 +; RV32IF-NEXT: srli a4, a4, 31 +; RV32IF-NEXT: xori a0, a4, 1 ; RV32IF-NEXT: .LBB45_11: # %entry ; RV32IF-NEXT: bnez a0, .LBB45_13 ; RV32IF-NEXT: # %bb.12: # %entry @@ -3092,7 +3092,7 @@ define i64 @stest_f64i64_mm(double %x) { ; RV64IF-NEXT: srli a3, a2, 1 ; RV64IF-NEXT: beqz a1, .LBB45_2 ; RV64IF-NEXT: # %bb.1: # %entry -; RV64IF-NEXT: slti a4, a1, 0 +; RV64IF-NEXT: srli a4, a1, 63 ; RV64IF-NEXT: j .LBB45_3 ; RV64IF-NEXT: .LBB45_2: ; RV64IF-NEXT: sltu a4, a0, a3 @@ -3106,8 +3106,8 @@ define i64 @stest_f64i64_mm(double %x) { ; RV64IF-NEXT: slli a1, a2, 63 ; RV64IF-NEXT: beq a5, a2, .LBB45_7 ; RV64IF-NEXT: # %bb.6: # %entry -; RV64IF-NEXT: slti a2, a5, 0 -; RV64IF-NEXT: xori a2, a2, 1 +; RV64IF-NEXT: srli a5, a5, 63 +; RV64IF-NEXT: xori a2, a5, 1 ; RV64IF-NEXT: beqz a2, .LBB45_8 ; RV64IF-NEXT: j .LBB45_9 ; RV64IF-NEXT: .LBB45_7: @@ -3147,7 +3147,7 @@ define i64 @stest_f64i64_mm(double %x) { ; RV32IFD-NEXT: or a7, a2, a4 ; RV32IFD-NEXT: beqz a7, .LBB45_4 ; RV32IFD-NEXT: .LBB45_3: # %entry -; RV32IFD-NEXT: slti a6, a4, 0 +; RV32IFD-NEXT: srli a6, a4, 31 ; RV32IFD-NEXT: .LBB45_4: # %entry ; RV32IFD-NEXT: neg a7, a6 ; RV32IFD-NEXT: addi t0, a6, -1 @@ -3169,8 +3169,8 @@ define i64 @stest_f64i64_mm(double %x) { ; RV32IFD-NEXT: li a5, -1 ; RV32IFD-NEXT: beq a2, a5, .LBB45_11 ; RV32IFD-NEXT: # %bb.10: # %entry -; RV32IFD-NEXT: slti a0, a4, 0 -; RV32IFD-NEXT: xori a0, a0, 1 +; RV32IFD-NEXT: srli a4, a4, 31 +; RV32IFD-NEXT: xori a0, a4, 1 ; RV32IFD-NEXT: .LBB45_11: # %entry ; RV32IFD-NEXT: bnez a0, .LBB45_13 ; RV32IFD-NEXT: # %bb.12: # %entry @@ -3298,7 +3298,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV32IF-NEXT: lw a3, 16(sp) ; RV32IF-NEXT: beqz a2, .LBB47_2 ; RV32IF-NEXT: # %bb.1: # %entry -; RV32IF-NEXT: slti a4, a2, 0 +; RV32IF-NEXT: srli a4, a2, 31 ; RV32IF-NEXT: j .LBB47_3 ; RV32IF-NEXT: .LBB47_2: ; RV32IF-NEXT: seqz a4, a3 @@ -3312,7 +3312,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV32IF-NEXT: and a1, a3, a1 ; RV32IF-NEXT: and a0, a3, a0 ; RV32IF-NEXT: and a2, a3, a2 -; RV32IF-NEXT: slti a2, a2, 0 +; RV32IF-NEXT: srli a2, a2, 31 ; RV32IF-NEXT: addi a2, a2, -1 ; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: and a1, a2, a1 @@ -3335,7 +3335,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV64-NEXT: li a2, 1 ; RV64-NEXT: .LBB47_2: # %entry ; RV64-NEXT: slti a1, a1, 1 -; RV64-NEXT: slti a2, a2, 0 +; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: neg a1, a1 ; RV64-NEXT: and a0, a1, a0 ; RV64-NEXT: addi a2, a2, -1 @@ -3360,7 +3360,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV32IFD-NEXT: lw a3, 16(sp) ; RV32IFD-NEXT: beqz a2, .LBB47_2 ; RV32IFD-NEXT: # %bb.1: # %entry -; RV32IFD-NEXT: slti a4, a2, 0 +; RV32IFD-NEXT: srli a4, a2, 31 ; RV32IFD-NEXT: j .LBB47_3 ; RV32IFD-NEXT: .LBB47_2: ; RV32IFD-NEXT: seqz a4, a3 @@ -3374,7 +3374,7 @@ define i64 @ustest_f64i64_mm(double %x) { ; RV32IFD-NEXT: and a1, a3, a1 ; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: and a2, a3, a2 -; RV32IFD-NEXT: slti a2, a2, 0 +; RV32IFD-NEXT: srli a2, a2, 31 ; RV32IFD-NEXT: addi a2, a2, -1 ; RV32IFD-NEXT: and a0, a2, a0 ; RV32IFD-NEXT: and a1, a2, a1 @@ -3417,7 +3417,7 @@ define i64 @stest_f32i64_mm(float %x) { ; RV32-NEXT: or a7, a2, a4 ; RV32-NEXT: beqz a7, .LBB48_4 ; RV32-NEXT: .LBB48_3: # %entry -; RV32-NEXT: slti a6, a4, 0 +; RV32-NEXT: srli a6, a4, 31 ; RV32-NEXT: .LBB48_4: # %entry ; RV32-NEXT: neg a7, a6 ; RV32-NEXT: addi t0, a6, -1 @@ -3439,8 +3439,8 @@ define i64 @stest_f32i64_mm(float %x) { ; RV32-NEXT: li a5, -1 ; RV32-NEXT: beq a2, a5, .LBB48_11 ; RV32-NEXT: # %bb.10: # %entry -; RV32-NEXT: slti a0, a4, 0 -; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: srli a4, a4, 31 +; RV32-NEXT: xori a0, a4, 1 ; RV32-NEXT: .LBB48_11: # %entry ; RV32-NEXT: bnez a0, .LBB48_13 ; RV32-NEXT: # %bb.12: # %entry @@ -3536,7 +3536,7 @@ define i64 @ustest_f32i64_mm(float %x) { ; RV32-NEXT: lw a3, 16(sp) ; RV32-NEXT: beqz a2, .LBB50_2 ; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: slti a4, a2, 0 +; RV32-NEXT: srli a4, a2, 31 ; RV32-NEXT: j .LBB50_3 ; RV32-NEXT: .LBB50_2: ; RV32-NEXT: seqz a4, a3 @@ -3550,7 +3550,7 @@ define i64 @ustest_f32i64_mm(float %x) { ; RV32-NEXT: and a1, a3, a1 ; RV32-NEXT: and a0, a3, a0 ; RV32-NEXT: and a2, a3, a2 -; RV32-NEXT: slti a2, a2, 0 +; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a1, a2, a1 @@ -3573,7 +3573,7 @@ define i64 @ustest_f32i64_mm(float %x) { ; RV64-NEXT: li a2, 1 ; RV64-NEXT: .LBB50_2: # %entry ; RV64-NEXT: slti a1, a1, 1 -; RV64-NEXT: slti a2, a2, 0 +; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: neg a1, a1 ; RV64-NEXT: and a0, a1, a0 ; RV64-NEXT: addi a2, a2, -1 @@ -3618,7 +3618,7 @@ define i64 @stest_f16i64_mm(half %x) { ; RV32-NEXT: or a7, a2, a4 ; RV32-NEXT: beqz a7, .LBB51_4 ; RV32-NEXT: .LBB51_3: # %entry -; RV32-NEXT: slti a6, a4, 0 +; RV32-NEXT: srli a6, a4, 31 ; RV32-NEXT: .LBB51_4: # %entry ; RV32-NEXT: neg a7, a6 ; RV32-NEXT: addi t0, a6, -1 @@ -3640,8 +3640,8 @@ define i64 @stest_f16i64_mm(half %x) { ; RV32-NEXT: li a5, -1 ; RV32-NEXT: beq a2, a5, .LBB51_11 ; RV32-NEXT: # %bb.10: # %entry -; RV32-NEXT: slti a0, a4, 0 -; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: srli a4, a4, 31 +; RV32-NEXT: xori a0, a4, 1 ; RV32-NEXT: .LBB51_11: # %entry ; RV32-NEXT: bnez a0, .LBB51_13 ; RV32-NEXT: # %bb.12: # %entry @@ -3667,7 +3667,7 @@ define i64 @stest_f16i64_mm(half %x) { ; RV64-NEXT: srli a3, a2, 1 ; RV64-NEXT: beqz a1, .LBB51_2 ; RV64-NEXT: # %bb.1: # %entry -; RV64-NEXT: slti a4, a1, 0 +; RV64-NEXT: srli a4, a1, 63 ; RV64-NEXT: j .LBB51_3 ; RV64-NEXT: .LBB51_2: ; RV64-NEXT: sltu a4, a0, a3 @@ -3681,8 +3681,8 @@ define i64 @stest_f16i64_mm(half %x) { ; RV64-NEXT: slli a1, a2, 63 ; RV64-NEXT: beq a5, a2, .LBB51_7 ; RV64-NEXT: # %bb.6: # %entry -; RV64-NEXT: slti a2, a5, 0 -; RV64-NEXT: xori a2, a2, 1 +; RV64-NEXT: srli a5, a5, 63 +; RV64-NEXT: xori a2, a5, 1 ; RV64-NEXT: beqz a2, .LBB51_8 ; RV64-NEXT: j .LBB51_9 ; RV64-NEXT: .LBB51_7: @@ -3773,7 +3773,7 @@ define i64 @ustest_f16i64_mm(half %x) { ; RV32-NEXT: lw a3, 16(sp) ; RV32-NEXT: beqz a2, .LBB53_2 ; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: slti a4, a2, 0 +; RV32-NEXT: srli a4, a2, 31 ; RV32-NEXT: j .LBB53_3 ; RV32-NEXT: .LBB53_2: ; RV32-NEXT: seqz a4, a3 @@ -3787,7 +3787,7 @@ define i64 @ustest_f16i64_mm(half %x) { ; RV32-NEXT: and a1, a3, a1 ; RV32-NEXT: and a0, a3, a0 ; RV32-NEXT: and a2, a3, a2 -; RV32-NEXT: slti a2, a2, 0 +; RV32-NEXT: srli a2, a2, 31 ; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: and a0, a2, a0 ; RV32-NEXT: and a1, a2, a1 @@ -3811,7 +3811,7 @@ define i64 @ustest_f16i64_mm(half %x) { ; RV64-NEXT: li a2, 1 ; RV64-NEXT: .LBB53_2: # %entry ; RV64-NEXT: slti a1, a1, 1 -; RV64-NEXT: slti a2, a2, 0 +; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: neg a1, a1 ; RV64-NEXT: and a0, a1, a0 ; RV64-NEXT: addi a2, a2, -1 diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index 0c152e611929..961c6cd78212 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -818,7 +818,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV32I-NEXT: call __gtsf2 ; RV32I-NEXT: bgtz a0, .LBB3_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: slti a0, s2, 0 +; RV32I-NEXT: srli a0, s2, 31 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and s0, a0, s1 ; RV32I-NEXT: .LBB3_2: # %start @@ -856,7 +856,7 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind { ; RV64I-NEXT: call __gtsf2 ; RV64I-NEXT: bgtz a0, .LBB3_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: slti a0, s2, 0 +; RV64I-NEXT: srli a0, s2, 63 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and s0, a0, s1 ; RV64I-NEXT: .LBB3_2: # %start @@ -1788,7 +1788,7 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi @@ -1828,8 +1828,8 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: j .LBB8_3 ; RV64I-NEXT: .LBB8_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB8_3: # %start ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -2369,13 +2369,13 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32I-NEXT: call __unordsf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: sgtz a1, s4 -; RV32I-NEXT: slti a2, s0, 0 +; RV32I-NEXT: srli s0, s0, 31 ; RV32I-NEXT: addi a0, a0, -1 -; RV32I-NEXT: neg a3, a1 -; RV32I-NEXT: addi a2, a2, -1 +; RV32I-NEXT: neg a2, a1 +; RV32I-NEXT: addi s0, s0, -1 ; RV32I-NEXT: and a1, a0, s3 -; RV32I-NEXT: and a2, a2, s1 -; RV32I-NEXT: or a2, a3, a2 +; RV32I-NEXT: and s0, s0, s1 +; RV32I-NEXT: or a2, a2, s0 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload @@ -3051,7 +3051,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfdi @@ -3085,7 +3085,7 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: addi s2, a0, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __fixunssfdi @@ -6912,8 +6912,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: j .LBB34_3 ; RV32I-NEXT: .LBB34_2: -; RV32I-NEXT: slti a0, s1, 0 -; RV32I-NEXT: addi a0, a0, -1 +; RV32I-NEXT: srli s1, s1, 31 +; RV32I-NEXT: addi a0, s1, -1 ; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: .LBB34_3: # %start ; RV32I-NEXT: and a0, a0, s3 @@ -6953,8 +6953,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind { ; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: j .LBB34_3 ; RV64I-NEXT: .LBB34_2: -; RV64I-NEXT: slti a0, s1, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s1, s1, 63 +; RV64I-NEXT: addi a0, s1, -1 ; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: .LBB34_3: # %start ; RV64I-NEXT: and a0, a0, s3 @@ -7856,8 +7856,8 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV32I-NEXT: li a0, 255 ; RV32I-NEXT: j .LBB38_3 ; RV32I-NEXT: .LBB38_2: -; RV32I-NEXT: slti a0, s0, 0 -; RV32I-NEXT: addi a0, a0, -1 +; RV32I-NEXT: srli s0, s0, 31 +; RV32I-NEXT: addi a0, s0, -1 ; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: .LBB38_3: # %start ; RV32I-NEXT: zext.b a0, a0 @@ -7893,8 +7893,8 @@ define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind { ; RV64I-NEXT: li a0, 255 ; RV64I-NEXT: j .LBB38_3 ; RV64I-NEXT: .LBB38_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB38_3: # %start ; RV64I-NEXT: zext.b a0, a0 @@ -8130,7 +8130,7 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi @@ -8170,8 +8170,8 @@ define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind { ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: j .LBB39_3 ; RV64I-NEXT: .LBB39_2: -; RV64I-NEXT: slti a0, s0, 0 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: srli s0, s0, 63 +; RV64I-NEXT: addi a0, s0, -1 ; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: .LBB39_3: # %start ; RV64I-NEXT: slli a0, a0, 32 diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll index cd9357994742..afc8e3553f8b 100644 --- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll +++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll @@ -2741,7 +2741,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-NEXT: call bcmp -; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-NEXT: ret @@ -2763,7 +2763,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBB-NEXT: call bcmp -; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ret @@ -2785,7 +2785,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: call bcmp -; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret @@ -2807,7 +2807,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-V-NEXT: call bcmp -; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-V-NEXT: ret @@ -5549,7 +5549,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-NEXT: call memcmp -; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-NEXT: ret @@ -5571,7 +5571,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBB-NEXT: call memcmp -; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ret @@ -5593,7 +5593,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: call memcmp -; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret @@ -5615,7 +5615,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-V-NEXT: call memcmp -; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-V-NEXT: ret @@ -5637,7 +5637,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-UNALIGNED-RV64-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV64-NEXT: call memcmp -; CHECK-UNALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-UNALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-UNALIGNED-RV64-NEXT: addi sp, sp, 16 ; CHECK-UNALIGNED-RV64-NEXT: ret @@ -5699,7 +5699,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-UNALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV64-V-NEXT: call memcmp -; CHECK-UNALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-UNALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-UNALIGNED-RV64-V-NEXT: addi sp, sp, 16 ; CHECK-UNALIGNED-RV64-V-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/memcmp.ll b/llvm/test/CodeGen/RISCV/memcmp.ll index a5bdb13d37fb..c737edb9acce 100644 --- a/llvm/test/CodeGen/RISCV/memcmp.ll +++ b/llvm/test/CodeGen/RISCV/memcmp.ll @@ -3161,7 +3161,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-NEXT: call bcmp -; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-NEXT: ret @@ -3183,7 +3183,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBB-NEXT: call bcmp -; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ret @@ -3205,7 +3205,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: call bcmp -; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret @@ -3227,7 +3227,7 @@ define i1 @bcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-V-NEXT: call bcmp -; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-V-NEXT: ret @@ -3454,7 +3454,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-NEXT: call bcmp -; CHECK-ALIGNED-RV32-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, 16 @@ -3466,7 +3466,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-NEXT: call bcmp -; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 @@ -3478,7 +3478,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-ZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-ZBB-NEXT: call bcmp -; CHECK-ALIGNED-RV32-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBB-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-ZBB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-ZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, 16 @@ -3490,7 +3490,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBB-NEXT: call bcmp -; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 @@ -3502,7 +3502,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-ZBKB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-ZBKB-NEXT: call bcmp -; CHECK-ALIGNED-RV32-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-ZBKB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-ZBKB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, 16 @@ -3514,7 +3514,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: call bcmp -; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 @@ -3526,7 +3526,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-V-NEXT: call bcmp -; CHECK-ALIGNED-RV32-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-V-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-V-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, 16 @@ -3538,7 +3538,7 @@ define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-V-NEXT: call bcmp -; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-V-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 @@ -6839,7 +6839,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-NEXT: call memcmp -; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-NEXT: ret @@ -6861,7 +6861,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBB-NEXT: call memcmp -; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ret @@ -6883,7 +6883,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: call memcmp -; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret @@ -6905,7 +6905,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-V-NEXT: call memcmp -; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 ; CHECK-ALIGNED-RV64-V-NEXT: ret @@ -6927,7 +6927,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-UNALIGNED-RV64-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV64-NEXT: call memcmp -; CHECK-UNALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-UNALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-UNALIGNED-RV64-NEXT: addi sp, sp, 16 ; CHECK-UNALIGNED-RV64-NEXT: ret @@ -6989,7 +6989,7 @@ define i1 @memcmp_lt_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-UNALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV64-V-NEXT: call memcmp -; CHECK-UNALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-UNALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-UNALIGNED-RV64-V-NEXT: addi sp, sp, 16 ; CHECK-UNALIGNED-RV64-V-NEXT: ret @@ -7366,7 +7366,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-NEXT: call memcmp -; CHECK-ALIGNED-RV32-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, 16 @@ -7378,7 +7378,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-NEXT: call memcmp -; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 @@ -7390,7 +7390,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-ZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-ZBB-NEXT: call memcmp -; CHECK-ALIGNED-RV32-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBB-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-ZBB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-ZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, 16 @@ -7402,7 +7402,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBB-NEXT: call memcmp -; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 @@ -7414,7 +7414,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-ZBKB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-ZBKB-NEXT: call memcmp -; CHECK-ALIGNED-RV32-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-ZBKB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-ZBKB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, 16 @@ -7426,7 +7426,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: call memcmp -; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 @@ -7438,7 +7438,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-ALIGNED-RV32-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV32-V-NEXT: call memcmp -; CHECK-ALIGNED-RV32-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-V-NEXT: srli a0, a0, 31 ; CHECK-ALIGNED-RV32-V-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, 16 @@ -7450,7 +7450,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-ALIGNED-RV64-V-NEXT: call memcmp -; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-ALIGNED-RV64-V-NEXT: xori a0, a0, 1 ; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 @@ -7462,7 +7462,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-UNALIGNED-RV32-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV32-NEXT: call memcmp -; CHECK-UNALIGNED-RV32-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV32-NEXT: srli a0, a0, 31 ; CHECK-UNALIGNED-RV32-NEXT: xori a0, a0, 1 ; CHECK-UNALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-UNALIGNED-RV32-NEXT: addi sp, sp, 16 @@ -7474,7 +7474,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-UNALIGNED-RV64-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV64-NEXT: call memcmp -; CHECK-UNALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-NEXT: srli a0, a0, 63 ; CHECK-UNALIGNED-RV64-NEXT: xori a0, a0, 1 ; CHECK-UNALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-UNALIGNED-RV64-NEXT: addi sp, sp, 16 @@ -7530,7 +7530,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; CHECK-UNALIGNED-RV32-V-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV32-V-NEXT: call memcmp -; CHECK-UNALIGNED-RV32-V-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV32-V-NEXT: srli a0, a0, 31 ; CHECK-UNALIGNED-RV32-V-NEXT: xori a0, a0, 1 ; CHECK-UNALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; CHECK-UNALIGNED-RV32-V-NEXT: addi sp, sp, 16 @@ -7542,7 +7542,7 @@ define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-UNALIGNED-RV64-V-NEXT: li a2, 4 ; CHECK-UNALIGNED-RV64-V-NEXT: call memcmp -; CHECK-UNALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-V-NEXT: srli a0, a0, 63 ; CHECK-UNALIGNED-RV64-V-NEXT: xori a0, a0, 1 ; CHECK-UNALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-UNALIGNED-RV64-V-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/min-max.ll b/llvm/test/CodeGen/RISCV/min-max.ll index 0115b48b7124..acde8adf5d08 100644 --- a/llvm/test/CodeGen/RISCV/min-max.ll +++ b/llvm/test/CodeGen/RISCV/min-max.ll @@ -642,7 +642,7 @@ define signext i32 @smin_i32_negone(i32 signext %a) { define i64 @smin_i64_negone(i64 %a) { ; RV32I-LABEL: smin_i64_negone: ; RV32I: # %bb.0: -; RV32I-NEXT: slti a2, a1, 0 +; RV32I-NEXT: srli a2, a1, 31 ; RV32I-NEXT: addi a2, a2, -1 ; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: slti a2, a1, -1 @@ -661,7 +661,7 @@ define i64 @smin_i64_negone(i64 %a) { ; RV32ZBB: # %bb.0: ; RV32ZBB-NEXT: li a2, -1 ; RV32ZBB-NEXT: min a2, a1, a2 -; RV32ZBB-NEXT: slti a1, a1, 0 +; RV32ZBB-NEXT: srli a1, a1, 31 ; RV32ZBB-NEXT: addi a1, a1, -1 ; RV32ZBB-NEXT: or a0, a1, a0 ; RV32ZBB-NEXT: mv a1, a2 diff --git a/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll b/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll index 30a935573477..f84673635fbb 100644 --- a/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll +++ b/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll @@ -39,7 +39,7 @@ define i1 @pr85190(i64 %a) { ; CHECK-NOZBB-LABEL: pr85190: ; CHECK-NOZBB: # %bb.0: ; CHECK-NOZBB-NEXT: ori a1, a0, 7 -; CHECK-NOZBB-NEXT: slti a2, a0, 0 +; CHECK-NOZBB-NEXT: srli a2, a0, 63 ; CHECK-NOZBB-NEXT: li a3, -1 ; CHECK-NOZBB-NEXT: slli a3, a3, 63 ; CHECK-NOZBB-NEXT: sub a3, a3, a1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll index 1736074ab186..7ab3d7c69456 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll @@ -431,7 +431,7 @@ define i64 @not_shl_one_i64(i64 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: addi a1, a0, -32 ; CHECK-NEXT: li a2, 1 -; CHECK-NEXT: slti a1, a1, 0 +; CHECK-NEXT: srli a1, a1, 31 ; CHECK-NEXT: sll a0, a2, a0 ; CHECK-NEXT: neg a2, a1 ; CHECK-NEXT: addi a1, a1, -1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll index e3728bffacf8..dcb70f88fd4a 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -53,11 +53,11 @@ define i64 @bclr_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: addi a5, a3, -32 ; RV32I-NEXT: sll a2, a4, a2 ; RV32I-NEXT: sll a3, a4, a3 -; RV32I-NEXT: slti a4, a5, 0 -; RV32I-NEXT: neg a5, a4 -; RV32I-NEXT: addi a4, a4, -1 -; RV32I-NEXT: and a2, a5, a2 -; RV32I-NEXT: and a3, a4, a3 +; RV32I-NEXT: srli a5, a5, 31 +; RV32I-NEXT: neg a4, a5 +; RV32I-NEXT: addi a5, a5, -1 +; RV32I-NEXT: and a2, a4, a2 +; RV32I-NEXT: and a3, a5, a3 ; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: not a3, a3 ; RV32I-NEXT: and a0, a2, a0 @@ -70,7 +70,7 @@ define i64 @bclr_i64(i64 %a, i64 %b) nounwind { ; RV32ZBSNOZBB-NEXT: bset a2, zero, a2 ; RV32ZBSNOZBB-NEXT: addi a4, a3, -32 ; RV32ZBSNOZBB-NEXT: bset a3, zero, a3 -; RV32ZBSNOZBB-NEXT: slti a4, a4, 0 +; RV32ZBSNOZBB-NEXT: srli a4, a4, 31 ; RV32ZBSNOZBB-NEXT: neg a5, a4 ; RV32ZBSNOZBB-NEXT: addi a4, a4, -1 ; RV32ZBSNOZBB-NEXT: and a2, a5, a2 @@ -87,7 +87,7 @@ define i64 @bclr_i64(i64 %a, i64 %b) nounwind { ; RV32ZBSZBB-NEXT: bset a2, zero, a2 ; RV32ZBSZBB-NEXT: bset a4, zero, a3 ; RV32ZBSZBB-NEXT: addi a3, a3, -32 -; RV32ZBSZBB-NEXT: slti a3, a3, 0 +; RV32ZBSZBB-NEXT: srli a3, a3, 31 ; RV32ZBSZBB-NEXT: addi a5, a3, -1 ; RV32ZBSZBB-NEXT: neg a3, a3 ; RV32ZBSZBB-NEXT: and a4, a5, a4 @@ -188,7 +188,7 @@ define signext i64 @bset_i64_zero(i64 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, a0, -32 ; RV32I-NEXT: li a2, 1 -; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: srli a1, a1, 31 ; RV32I-NEXT: sll a2, a2, a0 ; RV32I-NEXT: neg a0, a1 ; RV32I-NEXT: addi a1, a1, -1 @@ -200,11 +200,11 @@ define signext i64 @bset_i64_zero(i64 signext %a) nounwind { ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: addi a1, a0, -32 ; RV32ZBS-NEXT: bset a2, zero, a0 -; RV32ZBS-NEXT: slti a0, a1, 0 -; RV32ZBS-NEXT: neg a1, a0 -; RV32ZBS-NEXT: addi a3, a0, -1 -; RV32ZBS-NEXT: and a0, a1, a2 -; RV32ZBS-NEXT: and a1, a3, a2 +; RV32ZBS-NEXT: srli a1, a1, 31 +; RV32ZBS-NEXT: neg a0, a1 +; RV32ZBS-NEXT: addi a1, a1, -1 +; RV32ZBS-NEXT: and a0, a0, a2 +; RV32ZBS-NEXT: and a1, a1, a2 ; RV32ZBS-NEXT: ret %shl = shl i64 1, %a ret i64 %shl diff --git a/llvm/test/CodeGen/RISCV/rv64-double-convert.ll b/llvm/test/CodeGen/RISCV/rv64-double-convert.ll index dd49d9e3e2dc..caa6c2f8ff96 100644 --- a/llvm/test/CodeGen/RISCV/rv64-double-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64-double-convert.ll @@ -97,7 +97,7 @@ define i128 @fptosi_sat_f64_to_i128(double %a) nounwind { ; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: call __unorddf2 ; RV64I-NEXT: snez a0, a0 -; RV64I-NEXT: slti a1, s2, 0 +; RV64I-NEXT: srli a1, s2, 63 ; RV64I-NEXT: sgtz a2, s4 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a3, a1, -1 @@ -207,7 +207,7 @@ define i128 @fptoui_sat_f64_to_i128(double %a) nounwind { ; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: call __gedf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: addi s2, a0, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __fixunsdfti diff --git a/llvm/test/CodeGen/RISCV/rv64-float-convert.ll b/llvm/test/CodeGen/RISCV/rv64-float-convert.ll index 896e371452db..ebda78528810 100644 --- a/llvm/test/CodeGen/RISCV/rv64-float-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64-float-convert.ll @@ -95,7 +95,7 @@ define i128 @fptosi_sat_f32_to_i128(float %a) nounwind { ; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 -; RV64I-NEXT: slti a1, s2, 0 +; RV64I-NEXT: srli a1, s2, 63 ; RV64I-NEXT: sgtz a2, s4 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a3, a1, -1 @@ -209,7 +209,7 @@ define i128 @fptoui_sat_f32_to_i128(float %a) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: addi s2, a0, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __fixunssfti diff --git a/llvm/test/CodeGen/RISCV/rv64-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64-half-convert.ll index f89d1abfb2ea..648f3789953a 100644 --- a/llvm/test/CodeGen/RISCV/rv64-half-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64-half-convert.ll @@ -173,13 +173,13 @@ define i128 @fptosi_sat_f16_to_i128(half %a) nounwind { ; RV64I-NEXT: call __unordsf2 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: sgtz a1, s4 -; RV64I-NEXT: slti a2, s0, 0 +; RV64I-NEXT: srli s0, s0, 63 ; RV64I-NEXT: addi a0, a0, -1 -; RV64I-NEXT: neg a3, a1 -; RV64I-NEXT: addi a2, a2, -1 +; RV64I-NEXT: neg a2, a1 +; RV64I-NEXT: addi s0, s0, -1 ; RV64I-NEXT: and a1, a0, s3 -; RV64I-NEXT: and a2, a2, s1 -; RV64I-NEXT: or a2, a3, a2 +; RV64I-NEXT: and s0, s0, s1 +; RV64I-NEXT: or a2, a2, s0 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload @@ -288,7 +288,7 @@ define i128 @fptoui_sat_f16_to_i128(half %a) nounwind { ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: call __gesf2 -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: addi s2, a0, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __fixunssfti diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll index 9ef7f9441171..aba9d37bfaa0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll @@ -2327,7 +2327,7 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: srli a3, a0, 1 ; CHECK-NOV-NEXT: beqz a1, .LBB18_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: srli a4, a1, 63 ; CHECK-NOV-NEXT: bnez s1, .LBB18_4 ; CHECK-NOV-NEXT: .LBB18_2: ; CHECK-NOV-NEXT: sltu a5, s0, a3 @@ -2337,7 +2337,7 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: sltu a4, a2, a3 ; CHECK-NOV-NEXT: beqz s1, .LBB18_2 ; CHECK-NOV-NEXT: .LBB18_4: # %entry -; CHECK-NOV-NEXT: slti a5, s1, 0 +; CHECK-NOV-NEXT: srli a5, s1, 63 ; CHECK-NOV-NEXT: bnez a5, .LBB18_6 ; CHECK-NOV-NEXT: .LBB18_5: # %entry ; CHECK-NOV-NEXT: mv s0, a3 @@ -2353,8 +2353,8 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: slli a1, a0, 63 ; CHECK-NOV-NEXT: beq a5, a0, .LBB18_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry -; CHECK-NOV-NEXT: slti a3, a5, 0 -; CHECK-NOV-NEXT: xori a3, a3, 1 +; CHECK-NOV-NEXT: srli a5, a5, 63 +; CHECK-NOV-NEXT: xori a3, a5, 1 ; CHECK-NOV-NEXT: bne a4, a0, .LBB18_12 ; CHECK-NOV-NEXT: .LBB18_10: ; CHECK-NOV-NEXT: sltu a0, a1, s0 @@ -2364,8 +2364,8 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: sltu a3, a1, a2 ; CHECK-NOV-NEXT: beq a4, a0, .LBB18_10 ; CHECK-NOV-NEXT: .LBB18_12: # %entry -; CHECK-NOV-NEXT: slti a0, a4, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: srli a4, a4, 63 +; CHECK-NOV-NEXT: xori a0, a4, 1 ; CHECK-NOV-NEXT: bnez a0, .LBB18_14 ; CHECK-NOV-NEXT: .LBB18_13: # %entry ; CHECK-NOV-NEXT: mv s0, a1 @@ -2415,7 +2415,7 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB18_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: srli a4, a1, 63 ; CHECK-V-NEXT: bnez s1, .LBB18_4 ; CHECK-V-NEXT: .LBB18_2: ; CHECK-V-NEXT: sltu a5, s0, a3 @@ -2425,7 +2425,7 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: sltu a4, a0, a3 ; CHECK-V-NEXT: beqz s1, .LBB18_2 ; CHECK-V-NEXT: .LBB18_4: # %entry -; CHECK-V-NEXT: slti a5, s1, 0 +; CHECK-V-NEXT: srli a5, s1, 63 ; CHECK-V-NEXT: bnez a5, .LBB18_6 ; CHECK-V-NEXT: .LBB18_5: # %entry ; CHECK-V-NEXT: mv s0, a3 @@ -2441,8 +2441,8 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB18_11 ; CHECK-V-NEXT: # %bb.9: # %entry -; CHECK-V-NEXT: slti a3, a5, 0 -; CHECK-V-NEXT: xori a3, a3, 1 +; CHECK-V-NEXT: srli a5, a5, 63 +; CHECK-V-NEXT: xori a3, a5, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB18_12 ; CHECK-V-NEXT: .LBB18_10: ; CHECK-V-NEXT: sltu a2, a1, s0 @@ -2452,8 +2452,8 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB18_10 ; CHECK-V-NEXT: .LBB18_12: # %entry -; CHECK-V-NEXT: slti a2, a4, 0 -; CHECK-V-NEXT: xori a2, a2, 1 +; CHECK-V-NEXT: srli a4, a4, 63 +; CHECK-V-NEXT: xori a2, a4, 1 ; CHECK-V-NEXT: bnez a2, .LBB18_14 ; CHECK-V-NEXT: .LBB18_13: # %entry ; CHECK-V-NEXT: mv s0, a1 @@ -2749,7 +2749,7 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: srli a3, a0, 1 ; CHECK-NOV-NEXT: beqz a1, .LBB21_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: srli a4, a1, 63 ; CHECK-NOV-NEXT: bnez s1, .LBB21_4 ; CHECK-NOV-NEXT: .LBB21_2: ; CHECK-NOV-NEXT: sltu a5, s0, a3 @@ -2759,7 +2759,7 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: sltu a4, a2, a3 ; CHECK-NOV-NEXT: beqz s1, .LBB21_2 ; CHECK-NOV-NEXT: .LBB21_4: # %entry -; CHECK-NOV-NEXT: slti a5, s1, 0 +; CHECK-NOV-NEXT: srli a5, s1, 63 ; CHECK-NOV-NEXT: bnez a5, .LBB21_6 ; CHECK-NOV-NEXT: .LBB21_5: # %entry ; CHECK-NOV-NEXT: mv s0, a3 @@ -2775,8 +2775,8 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: slli a1, a0, 63 ; CHECK-NOV-NEXT: beq a5, a0, .LBB21_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry -; CHECK-NOV-NEXT: slti a3, a5, 0 -; CHECK-NOV-NEXT: xori a3, a3, 1 +; CHECK-NOV-NEXT: srli a5, a5, 63 +; CHECK-NOV-NEXT: xori a3, a5, 1 ; CHECK-NOV-NEXT: bne a4, a0, .LBB21_12 ; CHECK-NOV-NEXT: .LBB21_10: ; CHECK-NOV-NEXT: sltu a0, a1, s0 @@ -2786,8 +2786,8 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: sltu a3, a1, a2 ; CHECK-NOV-NEXT: beq a4, a0, .LBB21_10 ; CHECK-NOV-NEXT: .LBB21_12: # %entry -; CHECK-NOV-NEXT: slti a0, a4, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: srli a4, a4, 63 +; CHECK-NOV-NEXT: xori a0, a4, 1 ; CHECK-NOV-NEXT: bnez a0, .LBB21_14 ; CHECK-NOV-NEXT: .LBB21_13: # %entry ; CHECK-NOV-NEXT: mv s0, a1 @@ -2837,7 +2837,7 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB21_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: srli a4, a1, 63 ; CHECK-V-NEXT: bnez s1, .LBB21_4 ; CHECK-V-NEXT: .LBB21_2: ; CHECK-V-NEXT: sltu a5, s0, a3 @@ -2847,7 +2847,7 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: sltu a4, a0, a3 ; CHECK-V-NEXT: beqz s1, .LBB21_2 ; CHECK-V-NEXT: .LBB21_4: # %entry -; CHECK-V-NEXT: slti a5, s1, 0 +; CHECK-V-NEXT: srli a5, s1, 63 ; CHECK-V-NEXT: bnez a5, .LBB21_6 ; CHECK-V-NEXT: .LBB21_5: # %entry ; CHECK-V-NEXT: mv s0, a3 @@ -2863,8 +2863,8 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB21_11 ; CHECK-V-NEXT: # %bb.9: # %entry -; CHECK-V-NEXT: slti a3, a5, 0 -; CHECK-V-NEXT: xori a3, a3, 1 +; CHECK-V-NEXT: srli a5, a5, 63 +; CHECK-V-NEXT: xori a3, a5, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB21_12 ; CHECK-V-NEXT: .LBB21_10: ; CHECK-V-NEXT: sltu a2, a1, s0 @@ -2874,8 +2874,8 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB21_10 ; CHECK-V-NEXT: .LBB21_12: # %entry -; CHECK-V-NEXT: slti a2, a4, 0 -; CHECK-V-NEXT: xori a2, a2, 1 +; CHECK-V-NEXT: srli a4, a4, 63 +; CHECK-V-NEXT: xori a2, a4, 1 ; CHECK-V-NEXT: bnez a2, .LBB21_14 ; CHECK-V-NEXT: .LBB21_13: # %entry ; CHECK-V-NEXT: mv s0, a1 @@ -3174,7 +3174,7 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: srli a3, a0, 1 ; CHECK-NOV-NEXT: beqz a1, .LBB24_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: srli a4, a1, 63 ; CHECK-NOV-NEXT: bnez s1, .LBB24_4 ; CHECK-NOV-NEXT: .LBB24_2: ; CHECK-NOV-NEXT: sltu a5, s0, a3 @@ -3184,7 +3184,7 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: sltu a4, a2, a3 ; CHECK-NOV-NEXT: beqz s1, .LBB24_2 ; CHECK-NOV-NEXT: .LBB24_4: # %entry -; CHECK-NOV-NEXT: slti a5, s1, 0 +; CHECK-NOV-NEXT: srli a5, s1, 63 ; CHECK-NOV-NEXT: bnez a5, .LBB24_6 ; CHECK-NOV-NEXT: .LBB24_5: # %entry ; CHECK-NOV-NEXT: mv s0, a3 @@ -3200,8 +3200,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: slli a1, a0, 63 ; CHECK-NOV-NEXT: beq a5, a0, .LBB24_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry -; CHECK-NOV-NEXT: slti a3, a5, 0 -; CHECK-NOV-NEXT: xori a3, a3, 1 +; CHECK-NOV-NEXT: srli a5, a5, 63 +; CHECK-NOV-NEXT: xori a3, a5, 1 ; CHECK-NOV-NEXT: bne a4, a0, .LBB24_12 ; CHECK-NOV-NEXT: .LBB24_10: ; CHECK-NOV-NEXT: sltu a0, a1, s0 @@ -3211,8 +3211,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: sltu a3, a1, a2 ; CHECK-NOV-NEXT: beq a4, a0, .LBB24_10 ; CHECK-NOV-NEXT: .LBB24_12: # %entry -; CHECK-NOV-NEXT: slti a0, a4, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: srli a4, a4, 63 +; CHECK-NOV-NEXT: xori a0, a4, 1 ; CHECK-NOV-NEXT: bnez a0, .LBB24_14 ; CHECK-NOV-NEXT: .LBB24_13: # %entry ; CHECK-NOV-NEXT: mv s0, a1 @@ -3260,7 +3260,7 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB24_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: srli a4, a1, 63 ; CHECK-V-NEXT: bnez s1, .LBB24_4 ; CHECK-V-NEXT: .LBB24_2: ; CHECK-V-NEXT: sltu a5, s0, a3 @@ -3270,7 +3270,7 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: sltu a4, a0, a3 ; CHECK-V-NEXT: beqz s1, .LBB24_2 ; CHECK-V-NEXT: .LBB24_4: # %entry -; CHECK-V-NEXT: slti a5, s1, 0 +; CHECK-V-NEXT: srli a5, s1, 63 ; CHECK-V-NEXT: bnez a5, .LBB24_6 ; CHECK-V-NEXT: .LBB24_5: # %entry ; CHECK-V-NEXT: mv s0, a3 @@ -3286,8 +3286,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB24_11 ; CHECK-V-NEXT: # %bb.9: # %entry -; CHECK-V-NEXT: slti a3, a5, 0 -; CHECK-V-NEXT: xori a3, a3, 1 +; CHECK-V-NEXT: srli a5, a5, 63 +; CHECK-V-NEXT: xori a3, a5, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB24_12 ; CHECK-V-NEXT: .LBB24_10: ; CHECK-V-NEXT: sltu a2, a1, s0 @@ -3297,8 +3297,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB24_10 ; CHECK-V-NEXT: .LBB24_12: # %entry -; CHECK-V-NEXT: slti a2, a4, 0 -; CHECK-V-NEXT: xori a2, a2, 1 +; CHECK-V-NEXT: srli a4, a4, 63 +; CHECK-V-NEXT: xori a2, a4, 1 ; CHECK-V-NEXT: bnez a2, .LBB24_14 ; CHECK-V-NEXT: .LBB24_13: # %entry ; CHECK-V-NEXT: mv s0, a1 @@ -5864,7 +5864,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: srli a3, a0, 1 ; CHECK-NOV-NEXT: beqz a1, .LBB45_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: srli a4, a1, 63 ; CHECK-NOV-NEXT: beqz a4, .LBB45_3 ; CHECK-NOV-NEXT: j .LBB45_4 ; CHECK-NOV-NEXT: .LBB45_2: @@ -5875,7 +5875,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: .LBB45_4: # %entry ; CHECK-NOV-NEXT: beqz s1, .LBB45_6 ; CHECK-NOV-NEXT: # %bb.5: # %entry -; CHECK-NOV-NEXT: slti a6, s1, 0 +; CHECK-NOV-NEXT: srli a6, s1, 63 ; CHECK-NOV-NEXT: j .LBB45_7 ; CHECK-NOV-NEXT: .LBB45_6: ; CHECK-NOV-NEXT: sltu a6, s0, a3 @@ -5890,7 +5890,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: slli a3, a0, 63 ; CHECK-NOV-NEXT: beq a5, a0, .LBB45_11 ; CHECK-NOV-NEXT: # %bb.10: # %entry -; CHECK-NOV-NEXT: slti a5, a5, 0 +; CHECK-NOV-NEXT: srli a5, a5, 63 ; CHECK-NOV-NEXT: xori a5, a5, 1 ; CHECK-NOV-NEXT: and a1, a4, a1 ; CHECK-NOV-NEXT: beqz a5, .LBB45_12 @@ -5904,8 +5904,8 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: .LBB45_13: # %entry ; CHECK-NOV-NEXT: beq a1, a0, .LBB45_15 ; CHECK-NOV-NEXT: # %bb.14: # %entry -; CHECK-NOV-NEXT: slti a0, a1, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: srli a1, a1, 63 +; CHECK-NOV-NEXT: xori a0, a1, 1 ; CHECK-NOV-NEXT: beqz a0, .LBB45_16 ; CHECK-NOV-NEXT: j .LBB45_17 ; CHECK-NOV-NEXT: .LBB45_15: @@ -5955,7 +5955,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB45_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: srli a4, a1, 63 ; CHECK-V-NEXT: beqz a4, .LBB45_3 ; CHECK-V-NEXT: j .LBB45_4 ; CHECK-V-NEXT: .LBB45_2: @@ -5966,7 +5966,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: .LBB45_4: # %entry ; CHECK-V-NEXT: beqz s1, .LBB45_6 ; CHECK-V-NEXT: # %bb.5: # %entry -; CHECK-V-NEXT: slti a6, s1, 0 +; CHECK-V-NEXT: srli a6, s1, 63 ; CHECK-V-NEXT: j .LBB45_7 ; CHECK-V-NEXT: .LBB45_6: ; CHECK-V-NEXT: sltu a6, s0, a3 @@ -5981,7 +5981,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: slli a3, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB45_11 ; CHECK-V-NEXT: # %bb.10: # %entry -; CHECK-V-NEXT: slti a5, a5, 0 +; CHECK-V-NEXT: srli a5, a5, 63 ; CHECK-V-NEXT: xori a5, a5, 1 ; CHECK-V-NEXT: and a1, a4, a1 ; CHECK-V-NEXT: beqz a5, .LBB45_12 @@ -5995,7 +5995,7 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: .LBB45_13: # %entry ; CHECK-V-NEXT: beq a1, a2, .LBB45_15 ; CHECK-V-NEXT: # %bb.14: # %entry -; CHECK-V-NEXT: slti a1, a1, 0 +; CHECK-V-NEXT: srli a1, a1, 63 ; CHECK-V-NEXT: xori a1, a1, 1 ; CHECK-V-NEXT: beqz a1, .LBB45_16 ; CHECK-V-NEXT: j .LBB45_17 @@ -6153,8 +6153,8 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: .LBB47_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: slti a4, s1, 1 -; CHECK-NOV-NEXT: slti a3, a3, 0 -; CHECK-NOV-NEXT: slti a2, a2, 0 +; CHECK-NOV-NEXT: srli a3, a3, 63 +; CHECK-NOV-NEXT: srli a2, a2, 63 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: addi a3, a3, -1 @@ -6210,8 +6210,8 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: .LBB47_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: slti a4, s1, 1 -; CHECK-V-NEXT: slti a3, a3, 0 -; CHECK-V-NEXT: slti a2, a2, 0 +; CHECK-V-NEXT: srli a3, a3, 63 +; CHECK-V-NEXT: srli a2, a2, 63 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: addi a3, a3, -1 @@ -6268,7 +6268,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: srli a3, a0, 1 ; CHECK-NOV-NEXT: beqz a1, .LBB48_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: srli a4, a1, 63 ; CHECK-NOV-NEXT: beqz a4, .LBB48_3 ; CHECK-NOV-NEXT: j .LBB48_4 ; CHECK-NOV-NEXT: .LBB48_2: @@ -6279,7 +6279,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: .LBB48_4: # %entry ; CHECK-NOV-NEXT: beqz s1, .LBB48_6 ; CHECK-NOV-NEXT: # %bb.5: # %entry -; CHECK-NOV-NEXT: slti a6, s1, 0 +; CHECK-NOV-NEXT: srli a6, s1, 63 ; CHECK-NOV-NEXT: j .LBB48_7 ; CHECK-NOV-NEXT: .LBB48_6: ; CHECK-NOV-NEXT: sltu a6, s0, a3 @@ -6294,7 +6294,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: slli a3, a0, 63 ; CHECK-NOV-NEXT: beq a5, a0, .LBB48_11 ; CHECK-NOV-NEXT: # %bb.10: # %entry -; CHECK-NOV-NEXT: slti a5, a5, 0 +; CHECK-NOV-NEXT: srli a5, a5, 63 ; CHECK-NOV-NEXT: xori a5, a5, 1 ; CHECK-NOV-NEXT: and a1, a4, a1 ; CHECK-NOV-NEXT: beqz a5, .LBB48_12 @@ -6308,8 +6308,8 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: .LBB48_13: # %entry ; CHECK-NOV-NEXT: beq a1, a0, .LBB48_15 ; CHECK-NOV-NEXT: # %bb.14: # %entry -; CHECK-NOV-NEXT: slti a0, a1, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: srli a1, a1, 63 +; CHECK-NOV-NEXT: xori a0, a1, 1 ; CHECK-NOV-NEXT: beqz a0, .LBB48_16 ; CHECK-NOV-NEXT: j .LBB48_17 ; CHECK-NOV-NEXT: .LBB48_15: @@ -6359,7 +6359,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB48_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: srli a4, a1, 63 ; CHECK-V-NEXT: beqz a4, .LBB48_3 ; CHECK-V-NEXT: j .LBB48_4 ; CHECK-V-NEXT: .LBB48_2: @@ -6370,7 +6370,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: .LBB48_4: # %entry ; CHECK-V-NEXT: beqz s1, .LBB48_6 ; CHECK-V-NEXT: # %bb.5: # %entry -; CHECK-V-NEXT: slti a6, s1, 0 +; CHECK-V-NEXT: srli a6, s1, 63 ; CHECK-V-NEXT: j .LBB48_7 ; CHECK-V-NEXT: .LBB48_6: ; CHECK-V-NEXT: sltu a6, s0, a3 @@ -6385,7 +6385,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: slli a3, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB48_11 ; CHECK-V-NEXT: # %bb.10: # %entry -; CHECK-V-NEXT: slti a5, a5, 0 +; CHECK-V-NEXT: srli a5, a5, 63 ; CHECK-V-NEXT: xori a5, a5, 1 ; CHECK-V-NEXT: and a1, a4, a1 ; CHECK-V-NEXT: beqz a5, .LBB48_12 @@ -6399,7 +6399,7 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: .LBB48_13: # %entry ; CHECK-V-NEXT: beq a1, a2, .LBB48_15 ; CHECK-V-NEXT: # %bb.14: # %entry -; CHECK-V-NEXT: slti a1, a1, 0 +; CHECK-V-NEXT: srli a1, a1, 63 ; CHECK-V-NEXT: xori a1, a1, 1 ; CHECK-V-NEXT: beqz a1, .LBB48_16 ; CHECK-V-NEXT: j .LBB48_17 @@ -6557,8 +6557,8 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: .LBB50_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: slti a4, s1, 1 -; CHECK-NOV-NEXT: slti a3, a3, 0 -; CHECK-NOV-NEXT: slti a2, a2, 0 +; CHECK-NOV-NEXT: srli a3, a3, 63 +; CHECK-NOV-NEXT: srli a2, a2, 63 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: addi a3, a3, -1 @@ -6614,8 +6614,8 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: .LBB50_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: slti a4, s1, 1 -; CHECK-V-NEXT: slti a3, a3, 0 -; CHECK-V-NEXT: slti a2, a2, 0 +; CHECK-V-NEXT: srli a3, a3, 63 +; CHECK-V-NEXT: srli a2, a2, 63 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: addi a3, a3, -1 @@ -6675,7 +6675,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: srli a3, a0, 1 ; CHECK-NOV-NEXT: beqz a1, .LBB51_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: srli a4, a1, 63 ; CHECK-NOV-NEXT: beqz a4, .LBB51_3 ; CHECK-NOV-NEXT: j .LBB51_4 ; CHECK-NOV-NEXT: .LBB51_2: @@ -6686,7 +6686,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: .LBB51_4: # %entry ; CHECK-NOV-NEXT: beqz s1, .LBB51_6 ; CHECK-NOV-NEXT: # %bb.5: # %entry -; CHECK-NOV-NEXT: slti a6, s1, 0 +; CHECK-NOV-NEXT: srli a6, s1, 63 ; CHECK-NOV-NEXT: j .LBB51_7 ; CHECK-NOV-NEXT: .LBB51_6: ; CHECK-NOV-NEXT: sltu a6, s0, a3 @@ -6701,7 +6701,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: slli a3, a0, 63 ; CHECK-NOV-NEXT: beq a5, a0, .LBB51_11 ; CHECK-NOV-NEXT: # %bb.10: # %entry -; CHECK-NOV-NEXT: slti a5, a5, 0 +; CHECK-NOV-NEXT: srli a5, a5, 63 ; CHECK-NOV-NEXT: xori a5, a5, 1 ; CHECK-NOV-NEXT: and a1, a4, a1 ; CHECK-NOV-NEXT: beqz a5, .LBB51_12 @@ -6715,8 +6715,8 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: .LBB51_13: # %entry ; CHECK-NOV-NEXT: beq a1, a0, .LBB51_15 ; CHECK-NOV-NEXT: # %bb.14: # %entry -; CHECK-NOV-NEXT: slti a0, a1, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: srli a1, a1, 63 +; CHECK-NOV-NEXT: xori a0, a1, 1 ; CHECK-NOV-NEXT: beqz a0, .LBB51_16 ; CHECK-NOV-NEXT: j .LBB51_17 ; CHECK-NOV-NEXT: .LBB51_15: @@ -6764,7 +6764,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: beqz a1, .LBB51_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: srli a4, a1, 63 ; CHECK-V-NEXT: beqz a4, .LBB51_3 ; CHECK-V-NEXT: j .LBB51_4 ; CHECK-V-NEXT: .LBB51_2: @@ -6775,7 +6775,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: .LBB51_4: # %entry ; CHECK-V-NEXT: beqz s1, .LBB51_6 ; CHECK-V-NEXT: # %bb.5: # %entry -; CHECK-V-NEXT: slti a6, s1, 0 +; CHECK-V-NEXT: srli a6, s1, 63 ; CHECK-V-NEXT: j .LBB51_7 ; CHECK-V-NEXT: .LBB51_6: ; CHECK-V-NEXT: sltu a6, s0, a3 @@ -6790,7 +6790,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: slli a3, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB51_11 ; CHECK-V-NEXT: # %bb.10: # %entry -; CHECK-V-NEXT: slti a5, a5, 0 +; CHECK-V-NEXT: srli a5, a5, 63 ; CHECK-V-NEXT: xori a5, a5, 1 ; CHECK-V-NEXT: and a1, a4, a1 ; CHECK-V-NEXT: beqz a5, .LBB51_12 @@ -6804,7 +6804,7 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: .LBB51_13: # %entry ; CHECK-V-NEXT: beq a1, a2, .LBB51_15 ; CHECK-V-NEXT: # %bb.14: # %entry -; CHECK-V-NEXT: slti a1, a1, 0 +; CHECK-V-NEXT: srli a1, a1, 63 ; CHECK-V-NEXT: xori a1, a1, 1 ; CHECK-V-NEXT: beqz a1, .LBB51_16 ; CHECK-V-NEXT: j .LBB51_17 @@ -6960,8 +6960,8 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: .LBB53_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: slti a4, s1, 1 -; CHECK-NOV-NEXT: slti a3, a3, 0 -; CHECK-NOV-NEXT: slti a2, a2, 0 +; CHECK-NOV-NEXT: srli a3, a3, 63 +; CHECK-NOV-NEXT: srli a2, a2, 63 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: addi a3, a3, -1 @@ -7015,8 +7015,8 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: .LBB53_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: slti a4, s1, 1 -; CHECK-V-NEXT: slti a3, a3, 0 -; CHECK-V-NEXT: slti a2, a2, 0 +; CHECK-V-NEXT: srli a3, a3, 63 +; CHECK-V-NEXT: srli a2, a2, 63 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: addi a3, a3, -1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll index d91670214513..e7baffd8bf8d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll @@ -3438,9 +3438,8 @@ define <vscale x 4 x i32> @vbrev_v(<vscale x 4 x i32> %a, iXLen %vl) { define <vscale x 4 x i32> @vbrev8_v(<vscale x 4 x i32> %a, iXLen %vl) { ; CHECK-LABEL: vbrev8_v: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-NEXT: vbrev8.v v10, v8 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; CHECK-NEXT: vbrev8.v v10, v8 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call <vscale x 4 x i32> @llvm.riscv.vbrev8.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> %a, iXLen -1) @@ -3451,9 +3450,8 @@ define <vscale x 4 x i32> @vbrev8_v(<vscale x 4 x i32> %a, iXLen %vl) { define <vscale x 4 x i32> @vrev8_v(<vscale x 4 x i32> %a, iXLen %vl) { ; CHECK-LABEL: vrev8_v: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-NEXT: vrev8.v v10, v8 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; CHECK-NEXT: vrev8.v v10, v8 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call <vscale x 4 x i32> @llvm.riscv.vrev8.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> %a, iXLen -1) @@ -3560,9 +3558,8 @@ define <vscale x 4 x i32> @vrol_vx(<vscale x 4 x i32> %a, iXLen %b, iXLen %vl) { define <vscale x 2 x i64> @vclmul_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen %vl) { ; CHECK-LABEL: vclmul_vv: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmul.vv v10, v8, v10 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; CHECK-NEXT: vclmul.vv v10, v8, v10 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen -1) @@ -3573,9 +3570,8 @@ define <vscale x 2 x i64> @vclmul_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> % define <vscale x 2 x i64> @vclmul_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) { ; CHECK-LABEL: vclmul_vx: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmul.vx v10, v8, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma +; CHECK-NEXT: vclmul.vx v10, v8, a0 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call <vscale x 2 x i64> @llvm.riscv.vclmul.nxv2i64.i32(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, i32 %b, iXLen -1) @@ -3586,9 +3582,8 @@ define <vscale x 2 x i64> @vclmul_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) { define <vscale x 2 x i64> @vclmulh_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen %vl) { ; CHECK-LABEL: vclmulh_vv: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmulh.vv v10, v8, v10 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; CHECK-NEXT: vclmulh.vv v10, v8, v10 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, iXLen -1) @@ -3599,9 +3594,8 @@ define <vscale x 2 x i64> @vclmulh_vv(<vscale x 2 x i64> %a, <vscale x 2 x i64> define <vscale x 2 x i64> @vclmulh_vx(<vscale x 2 x i64> %a, i32 %b, iXLen %vl) { ; CHECK-LABEL: vclmulh_vx: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmulh.vx v10, v8, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma +; CHECK-NEXT: vclmulh.vx v10, v8, a0 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i32(<vscale x 2 x i64> undef, <vscale x 2 x i64> %a, i32 %b, iXLen -1) diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll index 4c84304405cb..dddcd4f107e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll @@ -61,11 +61,11 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: sltu t3, a4, t3 ; RV32-NEXT: and t3, t4, t3 ; RV32-NEXT: or t4, a1, a3 -; RV32-NEXT: slti t4, t4, 0 +; RV32-NEXT: srli t4, t4, 31 ; RV32-NEXT: or t4, t5, t4 ; RV32-NEXT: or t5, a1, a5 ; RV32-NEXT: sltu t1, a6, t1 -; RV32-NEXT: slti t5, t5, 0 +; RV32-NEXT: srli t5, t5, 31 ; RV32-NEXT: or t3, t3, t5 ; RV32-NEXT: or t3, t4, t3 ; RV32-NEXT: or t1, t1, t3 @@ -186,14 +186,14 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV64P670-NEXT: slli t3, t2, 1 ; RV64P670-NEXT: and s0, s0, s1 ; RV64P670-NEXT: or s1, a1, a3 -; RV64P670-NEXT: slti s1, s1, 0 +; RV64P670-NEXT: srli s1, s1, 63 ; RV64P670-NEXT: or t6, s0, s1 ; RV64P670-NEXT: sltu s1, a0, t5 ; RV64P670-NEXT: sltu s0, a4, t4 ; RV64P670-NEXT: mv t5, a0 ; RV64P670-NEXT: and s0, s0, s1 ; RV64P670-NEXT: or s1, a1, a5 -; RV64P670-NEXT: slti s1, s1, 0 +; RV64P670-NEXT: srli s1, s1, 63 ; RV64P670-NEXT: or s0, s0, s1 ; RV64P670-NEXT: li s1, 32 ; RV64P670-NEXT: maxu s1, t3, s1 @@ -321,12 +321,12 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV64X60-NEXT: or s2, a1, a3 ; RV64X60-NEXT: sltu s0, a0, t5 ; RV64X60-NEXT: sltu s1, a4, t3 -; RV64X60-NEXT: slti t3, s2, 0 +; RV64X60-NEXT: srli t3, s2, 63 ; RV64X60-NEXT: and s0, s0, s1 ; RV64X60-NEXT: or s1, a1, a5 ; RV64X60-NEXT: or t4, t4, t3 ; RV64X60-NEXT: slli t3, t2, 1 -; RV64X60-NEXT: slti s1, s1, 0 +; RV64X60-NEXT: srli s1, s1, 63 ; RV64X60-NEXT: or s0, s0, s1 ; RV64X60-NEXT: maxu s1, t3, t6 ; RV64X60-NEXT: or s0, t4, s0 @@ -461,10 +461,10 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV64-NEXT: sltu t5, a4, t5 ; RV64-NEXT: and t5, t6, t5 ; RV64-NEXT: or t6, a1, a3 -; RV64-NEXT: slti t6, t6, 0 +; RV64-NEXT: srli t6, t6, 63 ; RV64-NEXT: or t6, s0, t6 ; RV64-NEXT: or s0, a1, a5 -; RV64-NEXT: slti s0, s0, 0 +; RV64-NEXT: srli s0, s0, 63 ; RV64-NEXT: or t5, t5, s0 ; RV64-NEXT: or t5, t6, t5 ; RV64-NEXT: sltu t4, a6, t4 diff --git a/llvm/test/CodeGen/RISCV/sadd_sat.ll b/llvm/test/CodeGen/RISCV/sadd_sat.ll index 04f2436201e9..1d6d07aa6733 100644 --- a/llvm/test/CodeGen/RISCV/sadd_sat.ll +++ b/llvm/test/CodeGen/RISCV/sadd_sat.ll @@ -16,7 +16,7 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind { ; RV32-NEXT: mv a2, a0 ; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: slt a2, a0, a2 -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: beq a1, a2, .LBB0_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: srai a0, a0, 31 @@ -77,7 +77,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind { ; RV64-NEXT: mv a2, a0 ; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: slt a2, a0, a2 -; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: srli a1, a1, 63 ; RV64-NEXT: beq a1, a2, .LBB1_2 ; RV64-NEXT: # %bb.1: ; RV64-NEXT: srai a0, a0, 63 diff --git a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll index 857026cce0d4..9200a77915c5 100644 --- a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll +++ b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll @@ -17,7 +17,7 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind { ; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: slt a2, a0, a3 -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: beq a1, a2, .LBB0_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: srai a0, a0, 31 @@ -81,7 +81,7 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { ; RV64-NEXT: mv a1, a0 ; RV64-NEXT: add a0, a0, a2 ; RV64-NEXT: slt a1, a0, a1 -; RV64-NEXT: slti a2, a2, 0 +; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: beq a2, a1, .LBB1_2 ; RV64-NEXT: # %bb.1: ; RV64-NEXT: srai a0, a0, 63 diff --git a/llvm/test/CodeGen/RISCV/select-binop-identity.ll b/llvm/test/CodeGen/RISCV/select-binop-identity.ll index 325e4b54c1d6..8ab66ba3f25f 100644 --- a/llvm/test/CodeGen/RISCV/select-binop-identity.ll +++ b/llvm/test/CodeGen/RISCV/select-binop-identity.ll @@ -260,14 +260,14 @@ define i64 @and_select_all_ones_i64_cmp2(i64 %x, i64 %y, i64 %z) { ; RV32I: # %bb.0: ; RV32I-NEXT: beqz a5, .LBB5_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: slti a4, a5, 0 +; RV32I-NEXT: srli a5, a5, 31 ; RV32I-NEXT: j .LBB5_3 ; RV32I-NEXT: .LBB5_2: -; RV32I-NEXT: sltiu a4, a4, 4 +; RV32I-NEXT: sltiu a5, a4, 4 ; RV32I-NEXT: .LBB5_3: -; RV32I-NEXT: addi a4, a4, -1 -; RV32I-NEXT: or a1, a4, a1 -; RV32I-NEXT: or a0, a4, a0 +; RV32I-NEXT: addi a5, a5, -1 +; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: ret @@ -300,7 +300,7 @@ define i64 @and_select_all_ones_i64_cmp2(i64 %x, i64 %y, i64 %z) { ; ; ZICOND32-LABEL: and_select_all_ones_i64_cmp2: ; ZICOND32: # %bb.0: -; ZICOND32-NEXT: slti a6, a5, 0 +; ZICOND32-NEXT: srli a6, a5, 31 ; ZICOND32-NEXT: sltiu a4, a4, 4 ; ZICOND32-NEXT: czero.eqz a6, a6, a5 ; ZICOND32-NEXT: czero.nez a4, a4, a5 diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll index ec1f8aeddcaa..3df07073e0ed 100644 --- a/llvm/test/CodeGen/RISCV/select-cc.ll +++ b/llvm/test/CodeGen/RISCV/select-cc.ll @@ -200,7 +200,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind { ; RV64I-CCMOV-NEXT: lw a4, 0(a1) ; RV64I-CCMOV-NEXT: slti a5, a2, 1 ; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a2 -; RV64I-CCMOV-NEXT: slti a5, a2, 0 +; RV64I-CCMOV-NEXT: srli a5, a2, 63 ; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a3, a0 ; RV64I-CCMOV-NEXT: lw a1, 0(a1) ; RV64I-CCMOV-NEXT: slti a3, a4, 1025 @@ -384,11 +384,11 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) { ; RV32I-NEXT: li a6, -1 ; RV32I-NEXT: bne a1, a6, .LBB3_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: .LBB3_2: -; RV32I-NEXT: slti a0, a1, 0 -; RV32I-NEXT: xori a0, a0, 1 +; RV32I-NEXT: srli a1, a1, 31 +; RV32I-NEXT: xori a0, a1, 1 ; RV32I-NEXT: .LBB3_3: ; RV32I-NEXT: bnez a0, .LBB3_5 ; RV32I-NEXT: # %bb.4: diff --git a/llvm/test/CodeGen/RISCV/select-constant-xor.ll b/llvm/test/CodeGen/RISCV/select-constant-xor.ll index 72313a82b3d3..f11fb617c3b1 100644 --- a/llvm/test/CodeGen/RISCV/select-constant-xor.ll +++ b/llvm/test/CodeGen/RISCV/select-constant-xor.ll @@ -48,8 +48,8 @@ define i64 @selecti64i64(i64 %a) { define i32 @selecti64i32(i64 %a) { ; RV32-LABEL: selecti64i32: ; RV32: # %bb.0: -; RV32-NEXT: slti a0, a1, 0 -; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: srli a1, a1, 31 +; RV32-NEXT: xori a0, a1, 1 ; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: sub a0, a1, a0 ; RV32-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll index 3fbaefffac2e..fa1807cd7d91 100644 --- a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll +++ b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll @@ -76,12 +76,19 @@ define i32 @not_pos_sel_same_variable(i32 signext %a) { ; Compare if positive and select of constants where one constant is zero. define i32 @pos_sel_constants(i32 signext %a) { -; CHECK-LABEL: pos_sel_constants: -; CHECK: # %bb.0: -; CHECK-NEXT: slti a0, a0, 0 -; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: andi a0, a0, 5 -; CHECK-NEXT: ret +; RV32-LABEL: pos_sel_constants: +; RV32: # %bb.0: +; RV32-NEXT: srli a0, a0, 31 +; RV32-NEXT: addi a0, a0, -1 +; RV32-NEXT: andi a0, a0, 5 +; RV32-NEXT: ret +; +; RV64-LABEL: pos_sel_constants: +; RV64: # %bb.0: +; RV64-NEXT: srli a0, a0, 63 +; RV64-NEXT: addi a0, a0, -1 +; RV64-NEXT: andi a0, a0, 5 +; RV64-NEXT: ret %tmp.1 = icmp sgt i32 %a, -1 %retval = select i1 %tmp.1, i32 5, i32 0 ret i32 %retval @@ -101,7 +108,7 @@ define i32 @pos_sel_special_constant(i32 signext %a) { ; ; RV64-LABEL: pos_sel_special_constant: ; RV64: # %bb.0: -; RV64-NEXT: slti a0, a0, 0 +; RV64-NEXT: srli a0, a0, 63 ; RV64-NEXT: xori a0, a0, 1 ; RV64-NEXT: slli a0, a0, 9 ; RV64-NEXT: ret @@ -114,14 +121,14 @@ define i32 @pos_sel_special_constant(i32 signext %a) { define i32 @pos_sel_variable_and_zero(i32 signext %a, i32 signext %b) { ; RV32I-LABEL: pos_sel_variable_and_zero: ; RV32I: # %bb.0: -; RV32I-NEXT: slti a0, a0, 0 +; RV32I-NEXT: srli a0, a0, 31 ; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: pos_sel_variable_and_zero: ; RV64I: # %bb.0: -; RV64I-NEXT: slti a0, a0, 0 +; RV64I-NEXT: srli a0, a0, 63 ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/stack-folding.ll b/llvm/test/CodeGen/RISCV/stack-folding.ll index 8373a745e45c..0e3291167d0e 100644 --- a/llvm/test/CodeGen/RISCV/stack-folding.ll +++ b/llvm/test/CodeGen/RISCV/stack-folding.ll @@ -31,8 +31,8 @@ define i1 @test_sext_w(i64 %x, i32 %y) nounwind { ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: j .LBB0_3 ; CHECK-NEXT: .LBB0_2: # %truebb -; CHECK-NEXT: lw a0, 8(sp) # 8-byte Folded Reload -; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: srliw a0, a0, 31 ; CHECK-NEXT: .LBB0_3: # %falsebb ; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll index a30593d7d7af..2751332c9e3a 100644 --- a/llvm/test/CodeGen/RISCV/xaluo.ll +++ b/llvm/test/CodeGen/RISCV/xaluo.ll @@ -14,7 +14,7 @@ define zeroext i1 @saddo1.i32(i32 signext %v1, i32 signext %v2, ptr %res) { ; RV32: # %bb.0: # %entry ; RV32-NEXT: add a3, a0, a1 ; RV32-NEXT: slt a0, a3, a0 -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: ret @@ -32,7 +32,7 @@ define zeroext i1 @saddo1.i32(i32 signext %v1, i32 signext %v2, ptr %res) { ; RV32ZBA: # %bb.0: # %entry ; RV32ZBA-NEXT: add a3, a0, a1 ; RV32ZBA-NEXT: slt a0, a3, a0 -; RV32ZBA-NEXT: slti a1, a1, 0 +; RV32ZBA-NEXT: srli a1, a1, 31 ; RV32ZBA-NEXT: xor a0, a1, a0 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: ret @@ -50,7 +50,7 @@ define zeroext i1 @saddo1.i32(i32 signext %v1, i32 signext %v2, ptr %res) { ; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND-NEXT: add a3, a0, a1 ; RV32ZICOND-NEXT: slt a0, a3, a0 -; RV32ZICOND-NEXT: slti a1, a1, 0 +; RV32ZICOND-NEXT: srli a1, a1, 31 ; RV32ZICOND-NEXT: xor a0, a1, a0 ; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: ret @@ -252,8 +252,8 @@ define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32-NEXT: not a3, a3 ; RV32-NEXT: add a5, a5, a0 ; RV32-NEXT: xor a1, a1, a5 -; RV32-NEXT: and a1, a3, a1 -; RV32-NEXT: slti a0, a1, 0 +; RV32-NEXT: and a0, a3, a1 +; RV32-NEXT: srli a0, a0, 31 ; RV32-NEXT: sw a2, 0(a4) ; RV32-NEXT: sw a5, 4(a4) ; RV32-NEXT: ret @@ -262,7 +262,7 @@ define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) { ; RV64: # %bb.0: # %entry ; RV64-NEXT: add a3, a0, a1 ; RV64-NEXT: slt a0, a3, a0 -; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: srli a1, a1, 63 ; RV64-NEXT: xor a0, a1, a0 ; RV64-NEXT: sd a3, 0(a2) ; RV64-NEXT: ret @@ -276,8 +276,8 @@ define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32ZBA-NEXT: not a3, a3 ; RV32ZBA-NEXT: add a5, a5, a0 ; RV32ZBA-NEXT: xor a1, a1, a5 -; RV32ZBA-NEXT: and a1, a3, a1 -; RV32ZBA-NEXT: slti a0, a1, 0 +; RV32ZBA-NEXT: and a0, a3, a1 +; RV32ZBA-NEXT: srli a0, a0, 31 ; RV32ZBA-NEXT: sw a2, 0(a4) ; RV32ZBA-NEXT: sw a5, 4(a4) ; RV32ZBA-NEXT: ret @@ -286,7 +286,7 @@ define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) { ; RV64ZBA: # %bb.0: # %entry ; RV64ZBA-NEXT: add a3, a0, a1 ; RV64ZBA-NEXT: slt a0, a3, a0 -; RV64ZBA-NEXT: slti a1, a1, 0 +; RV64ZBA-NEXT: srli a1, a1, 63 ; RV64ZBA-NEXT: xor a0, a1, a0 ; RV64ZBA-NEXT: sd a3, 0(a2) ; RV64ZBA-NEXT: ret @@ -300,8 +300,8 @@ define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32ZICOND-NEXT: not a3, a3 ; RV32ZICOND-NEXT: add a5, a5, a0 ; RV32ZICOND-NEXT: xor a1, a1, a5 -; RV32ZICOND-NEXT: and a1, a3, a1 -; RV32ZICOND-NEXT: slti a0, a1, 0 +; RV32ZICOND-NEXT: and a0, a3, a1 +; RV32ZICOND-NEXT: srli a0, a0, 31 ; RV32ZICOND-NEXT: sw a2, 0(a4) ; RV32ZICOND-NEXT: sw a5, 4(a4) ; RV32ZICOND-NEXT: ret @@ -310,7 +310,7 @@ define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, ptr %res) { ; RV64ZICOND: # %bb.0: # %entry ; RV64ZICOND-NEXT: add a3, a0, a1 ; RV64ZICOND-NEXT: slt a0, a3, a0 -; RV64ZICOND-NEXT: slti a1, a1, 0 +; RV64ZICOND-NEXT: srli a1, a1, 63 ; RV64ZICOND-NEXT: xor a0, a1, a0 ; RV64ZICOND-NEXT: sd a3, 0(a2) ; RV64ZICOND-NEXT: ret @@ -330,8 +330,8 @@ define zeroext i1 @saddo2.i64(i64 %v1, ptr %res) { ; RV32-NEXT: sltu a0, a3, a0 ; RV32-NEXT: add a5, a1, a0 ; RV32-NEXT: xor a1, a1, a5 -; RV32-NEXT: and a1, a4, a1 -; RV32-NEXT: slti a0, a1, 0 +; RV32-NEXT: and a0, a4, a1 +; RV32-NEXT: srli a0, a0, 31 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a5, 4(a2) ; RV32-NEXT: ret @@ -350,8 +350,8 @@ define zeroext i1 @saddo2.i64(i64 %v1, ptr %res) { ; RV32ZBA-NEXT: sltu a0, a3, a0 ; RV32ZBA-NEXT: add a5, a1, a0 ; RV32ZBA-NEXT: xor a1, a1, a5 -; RV32ZBA-NEXT: and a1, a4, a1 -; RV32ZBA-NEXT: slti a0, a1, 0 +; RV32ZBA-NEXT: and a0, a4, a1 +; RV32ZBA-NEXT: srli a0, a0, 31 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a5, 4(a2) ; RV32ZBA-NEXT: ret @@ -370,8 +370,8 @@ define zeroext i1 @saddo2.i64(i64 %v1, ptr %res) { ; RV32ZICOND-NEXT: sltu a0, a3, a0 ; RV32ZICOND-NEXT: add a5, a1, a0 ; RV32ZICOND-NEXT: xor a1, a1, a5 -; RV32ZICOND-NEXT: and a1, a4, a1 -; RV32ZICOND-NEXT: slti a0, a1, 0 +; RV32ZICOND-NEXT: and a0, a4, a1 +; RV32ZICOND-NEXT: srli a0, a0, 31 ; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a5, 4(a2) ; RV32ZICOND-NEXT: ret @@ -399,7 +399,7 @@ define zeroext i1 @saddo3.i64(i64 %v1, ptr %res) { ; RV32-NEXT: addi a4, a0, -1 ; RV32-NEXT: xor a0, a1, a4 ; RV32-NEXT: and a0, a1, a0 -; RV32-NEXT: slti a0, a0, 0 +; RV32-NEXT: srli a0, a0, 31 ; RV32-NEXT: sw a3, 0(a2) ; RV32-NEXT: sw a4, 4(a2) ; RV32-NEXT: ret @@ -420,7 +420,7 @@ define zeroext i1 @saddo3.i64(i64 %v1, ptr %res) { ; RV32ZBA-NEXT: addi a4, a0, -1 ; RV32ZBA-NEXT: xor a0, a1, a4 ; RV32ZBA-NEXT: and a0, a1, a0 -; RV32ZBA-NEXT: slti a0, a0, 0 +; RV32ZBA-NEXT: srli a0, a0, 31 ; RV32ZBA-NEXT: sw a3, 0(a2) ; RV32ZBA-NEXT: sw a4, 4(a2) ; RV32ZBA-NEXT: ret @@ -441,7 +441,7 @@ define zeroext i1 @saddo3.i64(i64 %v1, ptr %res) { ; RV32ZICOND-NEXT: addi a4, a0, -1 ; RV32ZICOND-NEXT: xor a0, a1, a4 ; RV32ZICOND-NEXT: and a0, a1, a0 -; RV32ZICOND-NEXT: slti a0, a0, 0 +; RV32ZICOND-NEXT: srli a0, a0, 31 ; RV32ZICOND-NEXT: sw a3, 0(a2) ; RV32ZICOND-NEXT: sw a4, 4(a2) ; RV32ZICOND-NEXT: ret @@ -866,8 +866,8 @@ define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32-NEXT: sub a2, a0, a2 ; RV32-NEXT: sub a5, a6, a5 ; RV32-NEXT: xor a1, a1, a5 -; RV32-NEXT: and a1, a3, a1 -; RV32-NEXT: slti a0, a1, 0 +; RV32-NEXT: and a0, a3, a1 +; RV32-NEXT: srli a0, a0, 31 ; RV32-NEXT: sw a2, 0(a4) ; RV32-NEXT: sw a5, 4(a4) ; RV32-NEXT: ret @@ -889,8 +889,8 @@ define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32ZBA-NEXT: sub a2, a0, a2 ; RV32ZBA-NEXT: sub a5, a6, a5 ; RV32ZBA-NEXT: xor a1, a1, a5 -; RV32ZBA-NEXT: and a1, a3, a1 -; RV32ZBA-NEXT: slti a0, a1, 0 +; RV32ZBA-NEXT: and a0, a3, a1 +; RV32ZBA-NEXT: srli a0, a0, 31 ; RV32ZBA-NEXT: sw a2, 0(a4) ; RV32ZBA-NEXT: sw a5, 4(a4) ; RV32ZBA-NEXT: ret @@ -912,8 +912,8 @@ define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32ZICOND-NEXT: sub a2, a0, a2 ; RV32ZICOND-NEXT: sub a5, a6, a5 ; RV32ZICOND-NEXT: xor a1, a1, a5 -; RV32ZICOND-NEXT: and a1, a3, a1 -; RV32ZICOND-NEXT: slti a0, a1, 0 +; RV32ZICOND-NEXT: and a0, a3, a1 +; RV32ZICOND-NEXT: srli a0, a0, 31 ; RV32ZICOND-NEXT: sw a2, 0(a4) ; RV32ZICOND-NEXT: sw a5, 4(a4) ; RV32ZICOND-NEXT: ret @@ -1963,7 +1963,7 @@ define i32 @saddo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32: # %bb.0: # %entry ; RV32-NEXT: add a2, a0, a1 ; RV32-NEXT: slt a2, a2, a0 -; RV32-NEXT: slti a3, a1, 0 +; RV32-NEXT: srli a3, a1, 31 ; RV32-NEXT: bne a3, a2, .LBB28_2 ; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: mv a0, a1 @@ -1984,7 +1984,7 @@ define i32 @saddo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZBA: # %bb.0: # %entry ; RV32ZBA-NEXT: add a2, a0, a1 ; RV32ZBA-NEXT: slt a2, a2, a0 -; RV32ZBA-NEXT: slti a3, a1, 0 +; RV32ZBA-NEXT: srli a3, a1, 31 ; RV32ZBA-NEXT: bne a3, a2, .LBB28_2 ; RV32ZBA-NEXT: # %bb.1: # %entry ; RV32ZBA-NEXT: mv a0, a1 @@ -2004,7 +2004,7 @@ define i32 @saddo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND-LABEL: saddo.select.i32: ; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND-NEXT: add a2, a0, a1 -; RV32ZICOND-NEXT: slti a3, a1, 0 +; RV32ZICOND-NEXT: srli a3, a1, 31 ; RV32ZICOND-NEXT: slt a2, a2, a0 ; RV32ZICOND-NEXT: xor a2, a3, a2 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 @@ -2033,7 +2033,7 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) { ; RV32: # %bb.0: # %entry ; RV32-NEXT: add a2, a0, a1 ; RV32-NEXT: slt a0, a2, a0 -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: ret @@ -2050,7 +2050,7 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZBA: # %bb.0: # %entry ; RV32ZBA-NEXT: add a2, a0, a1 ; RV32ZBA-NEXT: slt a0, a2, a0 -; RV32ZBA-NEXT: slti a1, a1, 0 +; RV32ZBA-NEXT: srli a1, a1, 31 ; RV32ZBA-NEXT: xor a0, a1, a0 ; RV32ZBA-NEXT: xori a0, a0, 1 ; RV32ZBA-NEXT: ret @@ -2067,7 +2067,7 @@ define i1 @saddo.not.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND-NEXT: add a2, a0, a1 ; RV32ZICOND-NEXT: slt a0, a2, a0 -; RV32ZICOND-NEXT: slti a1, a1, 0 +; RV32ZICOND-NEXT: srli a1, a1, 31 ; RV32ZICOND-NEXT: xor a0, a1, a0 ; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: ret @@ -2108,7 +2108,7 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) { ; RV64: # %bb.0: # %entry ; RV64-NEXT: add a2, a0, a1 ; RV64-NEXT: slt a2, a2, a0 -; RV64-NEXT: slti a3, a1, 0 +; RV64-NEXT: srli a3, a1, 63 ; RV64-NEXT: bne a3, a2, .LBB30_2 ; RV64-NEXT: # %bb.1: # %entry ; RV64-NEXT: mv a0, a1 @@ -2136,7 +2136,7 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) { ; RV64ZBA: # %bb.0: # %entry ; RV64ZBA-NEXT: add a2, a0, a1 ; RV64ZBA-NEXT: slt a2, a2, a0 -; RV64ZBA-NEXT: slti a3, a1, 0 +; RV64ZBA-NEXT: srli a3, a1, 63 ; RV64ZBA-NEXT: bne a3, a2, .LBB30_2 ; RV64ZBA-NEXT: # %bb.1: # %entry ; RV64ZBA-NEXT: mv a0, a1 @@ -2153,7 +2153,7 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: not a5, a5 ; RV32ZICOND-NEXT: xor a4, a1, a4 ; RV32ZICOND-NEXT: and a4, a5, a4 -; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: srli a4, a4, 31 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 @@ -2165,7 +2165,7 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) { ; RV64ZICOND-LABEL: saddo.select.i64: ; RV64ZICOND: # %bb.0: # %entry ; RV64ZICOND-NEXT: add a2, a0, a1 -; RV64ZICOND-NEXT: slti a3, a1, 0 +; RV64ZICOND-NEXT: srli a3, a1, 63 ; RV64ZICOND-NEXT: slt a2, a2, a0 ; RV64ZICOND-NEXT: xor a2, a3, a2 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 @@ -2190,7 +2190,7 @@ define i1 @saddo.not.i64(i64 %v1, i64 %v2) { ; RV32-NEXT: xor a0, a1, a0 ; RV32-NEXT: not a1, a3 ; RV32-NEXT: and a0, a1, a0 -; RV32-NEXT: slti a0, a0, 0 +; RV32-NEXT: srli a0, a0, 31 ; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: ret ; @@ -2198,7 +2198,7 @@ define i1 @saddo.not.i64(i64 %v1, i64 %v2) { ; RV64: # %bb.0: # %entry ; RV64-NEXT: add a2, a0, a1 ; RV64-NEXT: slt a0, a2, a0 -; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: srli a1, a1, 63 ; RV64-NEXT: xor a0, a1, a0 ; RV64-NEXT: xori a0, a0, 1 ; RV64-NEXT: ret @@ -2213,7 +2213,7 @@ define i1 @saddo.not.i64(i64 %v1, i64 %v2) { ; RV32ZBA-NEXT: xor a0, a1, a0 ; RV32ZBA-NEXT: not a1, a3 ; RV32ZBA-NEXT: and a0, a1, a0 -; RV32ZBA-NEXT: slti a0, a0, 0 +; RV32ZBA-NEXT: srli a0, a0, 31 ; RV32ZBA-NEXT: xori a0, a0, 1 ; RV32ZBA-NEXT: ret ; @@ -2221,7 +2221,7 @@ define i1 @saddo.not.i64(i64 %v1, i64 %v2) { ; RV64ZBA: # %bb.0: # %entry ; RV64ZBA-NEXT: add a2, a0, a1 ; RV64ZBA-NEXT: slt a0, a2, a0 -; RV64ZBA-NEXT: slti a1, a1, 0 +; RV64ZBA-NEXT: srli a1, a1, 63 ; RV64ZBA-NEXT: xor a0, a1, a0 ; RV64ZBA-NEXT: xori a0, a0, 1 ; RV64ZBA-NEXT: ret @@ -2236,7 +2236,7 @@ define i1 @saddo.not.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: xor a0, a1, a0 ; RV32ZICOND-NEXT: not a1, a3 ; RV32ZICOND-NEXT: and a0, a1, a0 -; RV32ZICOND-NEXT: slti a0, a0, 0 +; RV32ZICOND-NEXT: srli a0, a0, 31 ; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: ret ; @@ -2244,7 +2244,7 @@ define i1 @saddo.not.i64(i64 %v1, i64 %v2) { ; RV64ZICOND: # %bb.0: # %entry ; RV64ZICOND-NEXT: add a2, a0, a1 ; RV64ZICOND-NEXT: slt a0, a2, a0 -; RV64ZICOND-NEXT: slti a1, a1, 0 +; RV64ZICOND-NEXT: srli a1, a1, 63 ; RV64ZICOND-NEXT: xor a0, a1, a0 ; RV64ZICOND-NEXT: xori a0, a0, 1 ; RV64ZICOND-NEXT: ret @@ -2713,7 +2713,7 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: xor a4, a1, a3 ; RV32ZICOND-NEXT: xor a5, a1, a5 ; RV32ZICOND-NEXT: and a4, a4, a5 -; RV32ZICOND-NEXT: slti a4, a4, 0 +; RV32ZICOND-NEXT: srli a4, a4, 31 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 @@ -2748,8 +2748,8 @@ define i1 @ssub.not.i64(i64 %v1, i64 %v2) { ; RV32-NEXT: xor a2, a1, a2 ; RV32-NEXT: xor a1, a1, a3 ; RV32-NEXT: and a1, a1, a2 -; RV32-NEXT: slti a0, a1, 0 -; RV32-NEXT: xori a0, a0, 1 +; RV32-NEXT: srli a1, a1, 31 +; RV32-NEXT: xori a0, a1, 1 ; RV32-NEXT: ret ; ; RV64-LABEL: ssub.not.i64: @@ -2769,8 +2769,8 @@ define i1 @ssub.not.i64(i64 %v1, i64 %v2) { ; RV32ZBA-NEXT: xor a2, a1, a2 ; RV32ZBA-NEXT: xor a1, a1, a3 ; RV32ZBA-NEXT: and a1, a1, a2 -; RV32ZBA-NEXT: slti a0, a1, 0 -; RV32ZBA-NEXT: xori a0, a0, 1 +; RV32ZBA-NEXT: srli a1, a1, 31 +; RV32ZBA-NEXT: xori a0, a1, 1 ; RV32ZBA-NEXT: ret ; ; RV64ZBA-LABEL: ssub.not.i64: @@ -2790,8 +2790,8 @@ define i1 @ssub.not.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: xor a2, a1, a2 ; RV32ZICOND-NEXT: xor a1, a1, a3 ; RV32ZICOND-NEXT: and a1, a1, a2 -; RV32ZICOND-NEXT: slti a0, a1, 0 -; RV32ZICOND-NEXT: xori a0, a0, 1 +; RV32ZICOND-NEXT: srli a1, a1, 31 +; RV32ZICOND-NEXT: xori a0, a1, 1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: ssub.not.i64: @@ -3821,7 +3821,7 @@ define zeroext i1 @saddo.br.i32(i32 signext %v1, i32 signext %v2) { ; RV32: # %bb.0: # %entry ; RV32-NEXT: add a2, a0, a1 ; RV32-NEXT: slt a0, a2, a0 -; RV32-NEXT: slti a1, a1, 0 +; RV32-NEXT: srli a1, a1, 31 ; RV32-NEXT: beq a1, a0, .LBB52_2 ; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: li a0, 0 @@ -3846,7 +3846,7 @@ define zeroext i1 @saddo.br.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZBA: # %bb.0: # %entry ; RV32ZBA-NEXT: add a2, a0, a1 ; RV32ZBA-NEXT: slt a0, a2, a0 -; RV32ZBA-NEXT: slti a1, a1, 0 +; RV32ZBA-NEXT: srli a1, a1, 31 ; RV32ZBA-NEXT: beq a1, a0, .LBB52_2 ; RV32ZBA-NEXT: # %bb.1: # %overflow ; RV32ZBA-NEXT: li a0, 0 @@ -3871,7 +3871,7 @@ define zeroext i1 @saddo.br.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND: # %bb.0: # %entry ; RV32ZICOND-NEXT: add a2, a0, a1 ; RV32ZICOND-NEXT: slt a0, a2, a0 -; RV32ZICOND-NEXT: slti a1, a1, 0 +; RV32ZICOND-NEXT: srli a1, a1, 31 ; RV32ZICOND-NEXT: beq a1, a0, .LBB52_2 ; RV32ZICOND-NEXT: # %bb.1: # %overflow ; RV32ZICOND-NEXT: li a0, 0 @@ -3927,7 +3927,7 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) { ; RV64: # %bb.0: # %entry ; RV64-NEXT: add a2, a0, a1 ; RV64-NEXT: slt a0, a2, a0 -; RV64-NEXT: slti a1, a1, 0 +; RV64-NEXT: srli a1, a1, 63 ; RV64-NEXT: beq a1, a0, .LBB53_2 ; RV64-NEXT: # %bb.1: # %overflow ; RV64-NEXT: li a0, 0 @@ -3958,7 +3958,7 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) { ; RV64ZBA: # %bb.0: # %entry ; RV64ZBA-NEXT: add a2, a0, a1 ; RV64ZBA-NEXT: slt a0, a2, a0 -; RV64ZBA-NEXT: slti a1, a1, 0 +; RV64ZBA-NEXT: srli a1, a1, 63 ; RV64ZBA-NEXT: beq a1, a0, .LBB53_2 ; RV64ZBA-NEXT: # %bb.1: # %overflow ; RV64ZBA-NEXT: li a0, 0 @@ -3989,7 +3989,7 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) { ; RV64ZICOND: # %bb.0: # %entry ; RV64ZICOND-NEXT: add a2, a0, a1 ; RV64ZICOND-NEXT: slt a0, a2, a0 -; RV64ZICOND-NEXT: slti a1, a1, 0 +; RV64ZICOND-NEXT: srli a1, a1, 63 ; RV64ZICOND-NEXT: beq a1, a0, .LBB53_2 ; RV64ZICOND-NEXT: # %bb.1: # %overflow ; RV64ZICOND-NEXT: li a0, 0 diff --git a/llvm/test/CodeGen/RISCV/xqcia.ll b/llvm/test/CodeGen/RISCV/xqcia.ll index c75bb9daefcf..3bbf33328f52 100644 --- a/llvm/test/CodeGen/RISCV/xqcia.ll +++ b/llvm/test/CodeGen/RISCV/xqcia.ll @@ -11,7 +11,7 @@ define i32 @addsat(i32 %a, i32 %b) { ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: slt a2, a0, a2 -; RV32I-NEXT: slti a1, a1, 0 +; RV32I-NEXT: srli a1, a1, 31 ; RV32I-NEXT: beq a1, a2, .LBB0_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srai a0, a0, 31 diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insbi.ll b/llvm/test/CodeGen/RISCV/xqcibm-insbi.ll new file mode 100644 index 000000000000..e4a545169d21 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/xqcibm-insbi.ll @@ -0,0 +1,262 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv32 --verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32I +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm --verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32XQCIBM + +define i32 @insbi(i32 %in1) nounwind { +; RV32I-LABEL: insbi: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a1, a0, 176 +; RV32I-NEXT: andi a1, a1, 496 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: qc.insbi a0, 11, 5, 4 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 176 + %and1 = and i32 %xor1, 496 + %xor2 = xor i32 %and1, %in1 + ret i32 %xor2 +} + +define i32 @insbi_comm_xor(i32 %in1) nounwind { +; RV32I-LABEL: insbi_comm_xor: +; RV32I: # %bb.0: +; RV32I-NEXT: li a1, 9 +; RV32I-NEXT: li a2, 15 +; RV32I-NEXT: slli a1, a1, 9 +; RV32I-NEXT: xor a1, a0, a1 +; RV32I-NEXT: slli a2, a2, 9 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_comm_xor: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: qc.insbi a0, 9, 4, 9 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 4608, %in1 + %and1 = and i32 %xor1, 7680 + %xor2 = xor i32 %and1, %in1 + ret i32 %xor2 +} + +define i32 @insbi_comm_and(i32 %in1) nounwind { +; RV32I-LABEL: insbi_comm_and: +; RV32I: # %bb.0: +; RV32I-NEXT: li a1, 11 +; RV32I-NEXT: li a2, 15 +; RV32I-NEXT: slli a1, a1, 9 +; RV32I-NEXT: xor a1, a0, a1 +; RV32I-NEXT: slli a2, a2, 9 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_comm_and: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: qc.insbi a0, 11, 4, 9 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 5632 + %and1 = and i32 7680, %xor1 + %xor2 = xor i32 %and1, %in1 + ret i32 %xor2 +} + +define i32 @insbi_comm_xor2(i32 %in1) nounwind { +; RV32I-LABEL: insbi_comm_xor2: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a1, a0, 176 +; RV32I-NEXT: andi a1, a1, 496 +; RV32I-NEXT: xor a0, a0, a1 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_comm_xor2: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: qc.insbi a0, 11, 5, 4 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 176 + %and1 = and i32 %xor1, 496 + %xor2 = xor i32 %in1, %and1 + ret i32 %xor2 +} + +define i32 @insbi_immg(i32 %in1) nounwind { +; RV32I-LABEL: insbi_immg: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a1, a0, 256 +; RV32I-NEXT: andi a1, a1, 496 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_immg: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: li a1, 16 +; RV32XQCIBM-NEXT: qc.insb a0, a1, 5, 4 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 256 + %and1 = and i32 %xor1, 496 + %xor2 = xor i32 %and1, %in1 + ret i32 %xor2 +} + +define i32 @insbi_not_shifted_mask(i32 %in1) nounwind { +; RV32I-LABEL: insbi_not_shifted_mask: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a1, a0, 128 +; RV32I-NEXT: andi a1, a1, 716 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_not_shifted_mask: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: xori a1, a0, 128 +; RV32XQCIBM-NEXT: andi a1, a1, 716 +; RV32XQCIBM-NEXT: xor a0, a0, a1 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 176 + %and1 = and i32 %xor1, 716 + %xor2 = xor i32 %and1, %in1 + ret i32 %xor2 +} + +define i32 @insbi_width_z(i32 %in1) nounwind { +; RV32I-LABEL: insbi_width_z: +; RV32I: # %bb.0: +; RV32I-NEXT: andi a1, a0, 256 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_width_z: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: andi a1, a0, 256 +; RV32XQCIBM-NEXT: xor a0, a0, a1 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 176 + %and1 = and i32 %xor1, 256 + %xor2 = xor i32 %and1, %in1 + ret i32 %xor2 +} + +define i32 @insbi_mul_use_and(i32 %in1, i32 %in2) nounwind { +; RV32I-LABEL: insbi_mul_use_and: +; RV32I: # %bb.0: +; RV32I-NEXT: li a1, 11 +; RV32I-NEXT: li a2, 15 +; RV32I-NEXT: slli a1, a1, 9 +; RV32I-NEXT: slli a2, a2, 9 +; RV32I-NEXT: xor a1, a0, a1 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: xor a2, a1, a0 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_mul_use_and: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: li a1, 11 +; RV32XQCIBM-NEXT: li a2, 15 +; RV32XQCIBM-NEXT: slli a1, a1, 9 +; RV32XQCIBM-NEXT: slli a2, a2, 9 +; RV32XQCIBM-NEXT: xor a1, a1, a0 +; RV32XQCIBM-NEXT: and a1, a1, a2 +; RV32XQCIBM-NEXT: xor a2, a1, a0 +; RV32XQCIBM-NEXT: add a0, a0, a1 +; RV32XQCIBM-NEXT: add a0, a0, a2 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 5632 + %and1 = and i32 %xor1, 7680 + %xor2 = xor i32 %and1, %in1 + %add1 = add i32 %in1, %and1 + %add2 = add i32 %add1, %xor2 + ret i32 %add2 +} + +define i32 @insbi_mul_use_xor(i32 %in1, i32 %in2) nounwind { +; RV32I-LABEL: insbi_mul_use_xor: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a1, a0, 176 +; RV32I-NEXT: andi a2, a1, 496 +; RV32I-NEXT: xor a2, a2, a0 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_mul_use_xor: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: xori a1, a0, 176 +; RV32XQCIBM-NEXT: andi a2, a1, 496 +; RV32XQCIBM-NEXT: xor a2, a2, a0 +; RV32XQCIBM-NEXT: add a0, a0, a1 +; RV32XQCIBM-NEXT: add a0, a0, a2 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, 176 + %and1 = and i32 %xor1, 496 + %xor2 = xor i32 %and1, %in1 + %add1 = add i32 %in1, %xor1 + %add2 = add i32 %add1, %xor2 + ret i32 %add2 +} + +define i32 @insbi_imm_too_neg(i32 %in1) nounwind { +; RV32I-LABEL: insbi_imm_too_neg: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a1, a0, -34 +; RV32I-NEXT: andi a1, a1, -2 +; RV32I-NEXT: xor a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_imm_too_neg: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: li a1, -17 +; RV32XQCIBM-NEXT: qc.insb a0, a1, 31, 1 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i32 %in1, -34 + %and1 = and i32 %xor1, -2 + %xor2 = xor i32 %and1, %in1 + ret i32 %xor2 +} + +define i64 @insbi_i64(i64 %in1) nounwind { +; RV32I-LABEL: insbi_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: lui a2, 57344 +; RV32I-NEXT: lui a3, 1044480 +; RV32I-NEXT: xor a2, a0, a2 +; RV32I-NEXT: and a2, a2, a3 +; RV32I-NEXT: zext.b a3, a1 +; RV32I-NEXT: xor a1, a3, a1 +; RV32I-NEXT: xor a0, a2, a0 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_i64: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: qc.extu a2, a1, 8, 0 +; RV32XQCIBM-NEXT: xor a1, a1, a2 +; RV32XQCIBM-NEXT: qc.insbi a0, 14, 8, 24 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i64 %in1, 234881024 + %and1 = and i64 %xor1, 1099494850560 + %xor2 = xor i64 %and1, %in1 + ret i64 %xor2 +} +define i64 @insbi_i64_large_mask(i64 %in1) nounwind { +; RV32I-LABEL: insbi_i64_large_mask: +; RV32I: # %bb.0: +; RV32I-NEXT: xori a2, a1, 9 +; RV32I-NEXT: andi a2, a2, 15 +; RV32I-NEXT: xor a1, a2, a1 +; RV32I-NEXT: ret +; +; RV32XQCIBM-LABEL: insbi_i64_large_mask: +; RV32XQCIBM: # %bb.0: +; RV32XQCIBM-NEXT: qc.insbi a1, 9, 4, 0 +; RV32XQCIBM-NEXT: ret + %xor1 = xor i64 %in1, 38654705664 + %and1 = and i64 %xor1, 64424509440 + %xor2 = xor i64 %and1, %in1 + ret i64 %xor2 +} diff --git a/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll b/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll index 2d48f2b49822..17b35343d079 100644 --- a/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll +++ b/llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll @@ -224,7 +224,7 @@ define i1 @flo(float %c, float %a, float %b) { ; CHECK-RV64I-NEXT: mv a1, s1 ; CHECK-RV64I-NEXT: call __gesf2 ; CHECK-RV64I-NEXT: or a0, s2, a0 -; CHECK-RV64I-NEXT: slti a0, a0, 0 +; CHECK-RV64I-NEXT: srli a0, a0, 63 ; CHECK-RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -275,7 +275,7 @@ define i1 @dlo(double %c, double %a, double %b) { ; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: call __gedf2 ; CHECK-NEXT: or a0, s2, a0 -; CHECK-NEXT: slti a0, a0, 0 +; CHECK-NEXT: srli a0, a0, 63 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/X86/callbr-asm-loop.ll b/llvm/test/CodeGen/X86/callbr-asm-loop.ll index 999b04c4f483..0b6898815f8c 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-loop.ll +++ b/llvm/test/CodeGen/X86/callbr-asm-loop.ll @@ -1,35 +1,28 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -O0 -mtriple=i686-- < %s | FileCheck %s +; RUN: llc -O1 -mtriple=i686-- < %s | FileCheck %s ; Test that causes multiple defs of %eax. -; FIXME: The testcase hangs with -O1/2/3 enabled. define i32 @loop1() nounwind { ; CHECK-LABEL: loop1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: pushl %esi -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_1: # %tailrecurse ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movl $1, %edx ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: movl %eax, %ecx -; CHECK-NEXT: movl %edx, %esi -; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .LBB0_2: # Inline asm indirect target -; CHECK-NEXT: # %tailrecurse.tailrecurse.backedge_crit_edge +; CHECK-NEXT: # %tailrecurse.tailrecurse_crit_edge ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: .LBB0_3: # %tailrecurse.backedge -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: jmp .LBB0_1 -; CHECK-NEXT: .LBB0_4: # Inline asm indirect target +; CHECK-NEXT: .LBB0_3: # Inline asm indirect target ; CHECK-NEXT: # %lab2.split ; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: movl %edx, %eax -; CHECK-NEXT: popl %esi ; CHECK-NEXT: retl entry: br label %tailrecurse diff --git a/llvm/test/CodeGen/X86/pr62286.ll b/llvm/test/CodeGen/X86/pr62286.ll index 9728e130333c..ce03f8fad4a1 100644 --- a/llvm/test/CodeGen/X86/pr62286.ll +++ b/llvm/test/CodeGen/X86/pr62286.ll @@ -28,8 +28,9 @@ define i64 @PR62286(i32 %a) { ; AVX1-NEXT: vmovd %edi, %xmm0 ; AVX1-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] ; AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 +; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7] ; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] ; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; AVX1-NEXT: vpmovsxdq %xmm1, %xmm1 @@ -42,10 +43,10 @@ define i64 @PR62286(i32 %a) { ; AVX2-LABEL: PR62286: ; AVX2: # %bb.0: ; AVX2-NEXT: vmovd %edi, %xmm0 -; AVX2-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] -; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm1 +; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 @@ -58,12 +59,13 @@ define i64 @PR62286(i32 %a) { ; AVX512-LABEL: PR62286: ; AVX512: # %bb.0: ; AVX512-NEXT: vmovd %edi, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0] -; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 -; AVX512-NEXT: movw $4369, %ax # imm = 0x1111 +; AVX512-NEXT: movb $8, %al ; AVX512-NEXT: kmovd %eax, %k1 -; AVX512-NEXT: vpaddd %zmm0, %zmm0, %zmm1 {%k1} -; AVX512-NEXT: vpmovsxdq %ymm1, %zmm0 +; AVX512-NEXT: vpexpandd %ymm0, %ymm1 {%k1} {z} +; AVX512-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 +; AVX512-NEXT: vpaddd %ymm0, %ymm0, %ymm0 +; AVX512-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7] +; AVX512-NEXT: vpmovsxdq %ymm0, %zmm0 ; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1 ; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 diff --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll index 87c135ddcec9..ef20cf2a09bb 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll @@ -1724,6 +1724,269 @@ define void @PR54562_mem(ptr %src, ptr %dst) { ret void } +define <512 x i8> @PR153457(<512 x i8> %a0, <512 x i8> %a1) nounwind { +; AVX512F-LABEL: PR153457: +; AVX512F: # %bb.0: +; AVX512F-NEXT: pushq %rbp +; AVX512F-NEXT: movq %rsp, %rbp +; AVX512F-NEXT: andq $-64, %rsp +; AVX512F-NEXT: subq $64, %rsp +; AVX512F-NEXT: movq %rdi, %rax +; AVX512F-NEXT: vpbroadcastq %xmm0, %ymm7 +; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [u,u,u,u,u,u,u,u,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0] +; AVX512F-NEXT: vpblendvb %ymm8, %ymm6, %ymm7, %ymm6 +; AVX512F-NEXT: vextracti64x4 $1, %zmm2, %ymm7 +; AVX512F-NEXT: vpbroadcastd %xmm0, %ymm9 +; AVX512F-NEXT: vpblendvb %ymm8, %ymm7, %ymm9, %ymm8 +; AVX512F-NEXT: vextracti32x4 $2, %zmm5, %xmm7 +; AVX512F-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm7[0],xmm0[0],xmm7[1],xmm0[1],xmm7[2],xmm0[2],xmm7[3],xmm0[3],xmm7[4],xmm0[4],xmm7[5],xmm0[5],xmm7[6],xmm0[6],xmm7[7],xmm0[7] +; AVX512F-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[0,2,4,6,8,10,12,13,u,u,u,u,u,u,u,u] +; AVX512F-NEXT: vextracti32x4 $2, %zmm4, %xmm9 +; AVX512F-NEXT: vmovdqa {{.*#+}} xmm10 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,128] +; AVX512F-NEXT: vpshufb %xmm10, %xmm9, %xmm9 +; AVX512F-NEXT: vpshufb {{.*#+}} xmm11 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[5] +; AVX512F-NEXT: vpor %xmm11, %xmm9, %xmm9 +; AVX512F-NEXT: vpshufb %xmm10, %xmm1, %xmm10 +; AVX512F-NEXT: vpshufb {{.*#+}} xmm11 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[1] +; AVX512F-NEXT: vpor %xmm11, %xmm10, %xmm10 +; AVX512F-NEXT: vpslld $24, %xmm0, %xmm11 +; AVX512F-NEXT: vinserti128 $1, %xmm11, %ymm0, %ymm11 +; AVX512F-NEXT: vextracti64x4 $1, %zmm3, %ymm3 +; AVX512F-NEXT: vmovdqa {{.*#+}} ymm12 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,u,u,u,u,u,u,u,u] +; AVX512F-NEXT: vpblendvb %ymm12, %ymm3, %ymm11, %ymm3 +; AVX512F-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] +; AVX512F-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,5,u,u,u,u,u,u,u,u] +; AVX512F-NEXT: vmovdqa 16(%rbp), %xmm11 +; AVX512F-NEXT: vpsrld $16, %xmm11, %xmm12 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm12[0] +; AVX512F-NEXT: vinserti64x4 $1, %ymm8, %zmm2, %zmm2 +; AVX512F-NEXT: vpmovzxdq {{.*#+}} xmm8 = xmm11[0],zero,xmm11[1],zero +; AVX512F-NEXT: vinserti128 $1, %xmm8, %ymm0, %ymm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm8[6,7] +; AVX512F-NEXT: vpsrld $24, %xmm11, %xmm8 +; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm8, %zmm3 +; AVX512F-NEXT: vinserti128 $1, %xmm11, %ymm10, %ymm8 +; AVX512F-NEXT: vpshufb {{.*#+}} ymm8 = ymm8[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,17,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm8[0,1,2,3],zmm1[4,5,6,7] +; AVX512F-NEXT: vinserti128 $1, %xmm11, %ymm9, %ymm8 +; AVX512F-NEXT: vpshufb {{.*#+}} ymm8 = ymm8[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,21,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-NEXT: vinserti64x4 $1, %ymm8, %zmm4, %zmm4 +; AVX512F-NEXT: vpsrlq $48, %xmm11, %xmm8 +; AVX512F-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm8[0] +; AVX512F-NEXT: vinserti64x4 $1, %ymm7, %zmm5, %zmm5 +; AVX512F-NEXT: vpermq {{.*#+}} ymm7 = ymm0[0,1,2,0] +; AVX512F-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,u,u,u,u,u,u,u,u] +; AVX512F-NEXT: vpbroadcastb 16(%rbp), %ymm8 +; AVX512F-NEXT: vpblendd {{.*#+}} ymm7 = ymm7[0,1,2,3,4,5],ymm8[6,7] +; AVX512F-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm7[0,1,2,3],zmm0[4,5,6,7] +; AVX512F-NEXT: vpsrlq $56, %xmm11, %xmm7 +; AVX512F-NEXT: vmovdqa %ymm7, 416(%rdi) +; AVX512F-NEXT: vmovdqa %ymm6, 384(%rdi) +; AVX512F-NEXT: vmovdqa64 %zmm0, (%rdi) +; AVX512F-NEXT: vmovdqa64 %zmm5, 320(%rdi) +; AVX512F-NEXT: vmovdqa64 %zmm3, 192(%rdi) +; AVX512F-NEXT: vmovdqa64 %zmm2, 128(%rdi) +; AVX512F-NEXT: vmovdqa64 %zmm4, 256(%rdi) +; AVX512F-NEXT: vmovdqa64 %zmm1, 64(%rdi) +; AVX512F-NEXT: movq %rbp, %rsp +; AVX512F-NEXT: popq %rbp +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512BW-LABEL: PR153457: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: pushq %rbp +; AVX512BW-NEXT: movq %rsp, %rbp +; AVX512BW-NEXT: andq $-64, %rsp +; AVX512BW-NEXT: subq $64, %rsp +; AVX512BW-NEXT: movq %rdi, %rax +; AVX512BW-NEXT: vmovdqa64 16(%rbp), %zmm7 +; AVX512BW-NEXT: vpbroadcastq %xmm0, %ymm8 +; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm9 = [u,u,u,u,u,u,u,u,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0] +; AVX512BW-NEXT: vpblendvb %ymm9, %ymm6, %ymm8, %ymm6 +; AVX512BW-NEXT: vextracti64x4 $1, %zmm2, %ymm8 +; AVX512BW-NEXT: vpbroadcastd %xmm0, %ymm10 +; AVX512BW-NEXT: vpblendvb %ymm9, %ymm8, %ymm10, %ymm8 +; AVX512BW-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] +; AVX512BW-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,5,u,u,u,u,u,u,u,u] +; AVX512BW-NEXT: vinserti64x4 $1, %ymm8, %zmm2, %zmm2 +; AVX512BW-NEXT: vextracti32x4 $2, %zmm5, %xmm8 +; AVX512BW-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm8[0],xmm0[0],xmm8[1],xmm0[1],xmm8[2],xmm0[2],xmm8[3],xmm0[3],xmm8[4],xmm0[4],xmm8[5],xmm0[5],xmm8[6],xmm0[6],xmm8[7],xmm0[7] +; AVX512BW-NEXT: vpshufb {{.*#+}} xmm8 = xmm8[0,2,4,6,8,10,12,13,u,u,u,u,u,u,u,u] +; AVX512BW-NEXT: vinserti32x4 $2, %xmm8, %zmm5, %zmm5 +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm8 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,128,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,128,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63] +; AVX512BW-NEXT: # zmm8 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vextracti32x4 $2, %zmm4, %xmm9 +; AVX512BW-NEXT: vpshufb %xmm8, %xmm9, %xmm9 +; AVX512BW-NEXT: vpshufb {{.*#+}} xmm10 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[5] +; AVX512BW-NEXT: vpor %xmm10, %xmm9, %xmm9 +; AVX512BW-NEXT: vinserti32x4 $2, %xmm9, %zmm4, %zmm4 +; AVX512BW-NEXT: vpslld $24, %xmm0, %xmm9 +; AVX512BW-NEXT: vinserti128 $1, %xmm9, %ymm0, %ymm9 +; AVX512BW-NEXT: vextracti64x4 $1, %zmm3, %ymm3 +; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm10 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,u,u,u,u,u,u,u,u] +; AVX512BW-NEXT: vpblendvb %ymm10, %ymm3, %ymm9, %ymm3 +; AVX512BW-NEXT: vpshufb %zmm8, %zmm1, %zmm1 +; AVX512BW-NEXT: vpshufb {{.*#+}} zmm8 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zmm0[1,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512BW-NEXT: vporq %zmm8, %zmm1, %zmm1 +; AVX512BW-NEXT: vinserti128 $1, %xmm7, %ymm1, %ymm8 +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm8[0,1,2,3],zmm1[4,5,6,7] +; AVX512BW-NEXT: vpshufb {{.*#+}} zmm1 = zmm1[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,17,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63] +; AVX512BW-NEXT: vpmovsxbw {{.*#+}} zmm8 = [0,1,2,3,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28,29,30,31] +; AVX512BW-NEXT: vpermi2w %zmm7, %zmm2, %zmm8 +; AVX512BW-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm7[0],zero,xmm7[1],zero +; AVX512BW-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3,4,5],ymm2[6,7] +; AVX512BW-NEXT: vpsrld $24, %xmm7, %xmm3 +; AVX512BW-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 +; AVX512BW-NEXT: vinserti64x4 $1, %ymm7, %zmm6, %zmm3 +; AVX512BW-NEXT: vpshufb {{.*#+}} zmm3 = zmm3[u,u,u,u,u,u,u,u,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,39,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512BW-NEXT: vinserti32x4 $3, %xmm7, %zmm4, %zmm4 +; AVX512BW-NEXT: vpshufb {{.*#+}} zmm4 = zmm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,53,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512BW-NEXT: vpermq {{.*#+}} ymm6 = ymm0[0,1,2,0] +; AVX512BW-NEXT: vpshufb {{.*#+}} ymm6 = ymm6[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,u,u,u,u,u,u,u,u] +; AVX512BW-NEXT: vpbroadcastb 16(%rbp), %ymm9 +; AVX512BW-NEXT: vpblendd {{.*#+}} ymm6 = ymm6[0,1,2,3,4,5],ymm9[6,7] +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm6[0,1,2,3],zmm0[4,5,6,7] +; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm6 = [16,17,18,19,35,0,0,0,8,9,10,11,12,13,14,15,16,17,18,19,35,0,0,0,8,9,10,11,12,13,14,15] +; AVX512BW-NEXT: # zmm6 = mem[0,1,2,3,0,1,2,3] +; AVX512BW-NEXT: vpermi2w %zmm7, %zmm5, %zmm6 +; AVX512BW-NEXT: vmovdqa64 %zmm6, 320(%rdi) +; AVX512BW-NEXT: vmovdqa64 %zmm3, 384(%rdi) +; AVX512BW-NEXT: vmovdqa64 %zmm0, (%rdi) +; AVX512BW-NEXT: vmovdqa64 %zmm4, 256(%rdi) +; AVX512BW-NEXT: vmovdqa64 %zmm2, 192(%rdi) +; AVX512BW-NEXT: vmovdqa64 %zmm8, 128(%rdi) +; AVX512BW-NEXT: vmovdqa64 %zmm1, 64(%rdi) +; AVX512BW-NEXT: movq %rbp, %rsp +; AVX512BW-NEXT: popq %rbp +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq +; +; AVX512DQ-LABEL: PR153457: +; AVX512DQ: # %bb.0: +; AVX512DQ-NEXT: pushq %rbp +; AVX512DQ-NEXT: movq %rsp, %rbp +; AVX512DQ-NEXT: andq $-64, %rsp +; AVX512DQ-NEXT: subq $64, %rsp +; AVX512DQ-NEXT: movq %rdi, %rax +; AVX512DQ-NEXT: vpbroadcastq %xmm0, %ymm7 +; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm8 = [u,u,u,u,u,u,u,u,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0] +; AVX512DQ-NEXT: vpblendvb %ymm8, %ymm6, %ymm7, %ymm6 +; AVX512DQ-NEXT: vextracti64x4 $1, %zmm2, %ymm7 +; AVX512DQ-NEXT: vpbroadcastd %xmm0, %ymm9 +; AVX512DQ-NEXT: vpblendvb %ymm8, %ymm7, %ymm9, %ymm8 +; AVX512DQ-NEXT: vextracti32x4 $2, %zmm5, %xmm7 +; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} xmm7 = xmm7[0],xmm0[0],xmm7[1],xmm0[1],xmm7[2],xmm0[2],xmm7[3],xmm0[3],xmm7[4],xmm0[4],xmm7[5],xmm0[5],xmm7[6],xmm0[6],xmm7[7],xmm0[7] +; AVX512DQ-NEXT: vpshufb {{.*#+}} xmm7 = xmm7[0,2,4,6,8,10,12,13,u,u,u,u,u,u,u,u] +; AVX512DQ-NEXT: vextracti32x4 $2, %zmm4, %xmm9 +; AVX512DQ-NEXT: vmovdqa {{.*#+}} xmm10 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,128] +; AVX512DQ-NEXT: vpshufb %xmm10, %xmm9, %xmm9 +; AVX512DQ-NEXT: vpshufb {{.*#+}} xmm11 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[5] +; AVX512DQ-NEXT: vpor %xmm11, %xmm9, %xmm9 +; AVX512DQ-NEXT: vpshufb %xmm10, %xmm1, %xmm10 +; AVX512DQ-NEXT: vpshufb {{.*#+}} xmm11 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[1] +; AVX512DQ-NEXT: vpor %xmm11, %xmm10, %xmm10 +; AVX512DQ-NEXT: vpslld $24, %xmm0, %xmm11 +; AVX512DQ-NEXT: vinserti128 $1, %xmm11, %ymm0, %ymm11 +; AVX512DQ-NEXT: vextracti64x4 $1, %zmm3, %ymm3 +; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm12 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,u,u,u,u,u,u,u,u] +; AVX512DQ-NEXT: vpblendvb %ymm12, %ymm3, %ymm11, %ymm3 +; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] +; AVX512DQ-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,5,u,u,u,u,u,u,u,u] +; AVX512DQ-NEXT: vmovdqa 16(%rbp), %xmm11 +; AVX512DQ-NEXT: vpsrld $16, %xmm11, %xmm12 +; AVX512DQ-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm12[0] +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm8, %zmm2, %zmm2 +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm8 = xmm11[0],zero,xmm11[1],zero +; AVX512DQ-NEXT: vinserti128 $1, %xmm8, %ymm0, %ymm8 +; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm8[6,7] +; AVX512DQ-NEXT: vpsrld $24, %xmm11, %xmm8 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm3, %zmm8, %zmm3 +; AVX512DQ-NEXT: vinserti128 $1, %xmm11, %ymm10, %ymm8 +; AVX512DQ-NEXT: vpshufb {{.*#+}} ymm8 = ymm8[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,17,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512DQ-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm8[0,1,2,3],zmm1[4,5,6,7] +; AVX512DQ-NEXT: vinserti128 $1, %xmm11, %ymm9, %ymm8 +; AVX512DQ-NEXT: vpshufb {{.*#+}} ymm8 = ymm8[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,21,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm8, %zmm4, %zmm4 +; AVX512DQ-NEXT: vpsrlq $48, %xmm11, %xmm8 +; AVX512DQ-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm8[0] +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm7, %zmm5, %zmm5 +; AVX512DQ-NEXT: vpermq {{.*#+}} ymm7 = ymm0[0,1,2,0] +; AVX512DQ-NEXT: vpshufb {{.*#+}} ymm7 = ymm7[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,u,u,u,u,u,u,u,u] +; AVX512DQ-NEXT: vpbroadcastb 16(%rbp), %ymm8 +; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm7 = ymm7[0,1,2,3,4,5],ymm8[6,7] +; AVX512DQ-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm7[0,1,2,3],zmm0[4,5,6,7] +; AVX512DQ-NEXT: vpsrlq $56, %xmm11, %xmm7 +; AVX512DQ-NEXT: vmovdqa %ymm7, 416(%rdi) +; AVX512DQ-NEXT: vmovdqa %ymm6, 384(%rdi) +; AVX512DQ-NEXT: vmovdqa64 %zmm0, (%rdi) +; AVX512DQ-NEXT: vmovdqa64 %zmm5, 320(%rdi) +; AVX512DQ-NEXT: vmovdqa64 %zmm3, 192(%rdi) +; AVX512DQ-NEXT: vmovdqa64 %zmm2, 128(%rdi) +; AVX512DQ-NEXT: vmovdqa64 %zmm4, 256(%rdi) +; AVX512DQ-NEXT: vmovdqa64 %zmm1, 64(%rdi) +; AVX512DQ-NEXT: movq %rbp, %rsp +; AVX512DQ-NEXT: popq %rbp +; AVX512DQ-NEXT: vzeroupper +; AVX512DQ-NEXT: retq +; +; AVX512VBMI-LABEL: PR153457: +; AVX512VBMI: # %bb.0: +; AVX512VBMI-NEXT: pushq %rbp +; AVX512VBMI-NEXT: movq %rsp, %rbp +; AVX512VBMI-NEXT: andq $-64, %rsp +; AVX512VBMI-NEXT: subq $64, %rsp +; AVX512VBMI-NEXT: movq %rdi, %rax +; AVX512VBMI-NEXT: vmovdqa64 16(%rbp), %zmm7 +; AVX512VBMI-NEXT: vbroadcasti64x4 {{.*#+}} zmm8 = [32,33,34,35,36,37,38,70,0,0,0,0,0,0,0,0,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,70,0,0,0,0,0,0,0,0,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31] +; AVX512VBMI-NEXT: # zmm8 = mem[0,1,2,3,0,1,2,3] +; AVX512VBMI-NEXT: vpermi2b %zmm0, %zmm5, %zmm8 +; AVX512VBMI-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,69,0,0,0,0,0,0,0,0,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,69,0,0,0,0,0,0,0,0,24,25,26,27,28,29,30,31] +; AVX512VBMI-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] +; AVX512VBMI-NEXT: vpermi2b %zmm0, %zmm4, %zmm5 +; AVX512VBMI-NEXT: vbroadcasti64x4 {{.*#+}} zmm4 = [32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,68,0,0,0,0,0,0,0,0,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,68,0,0,0,0,0,0,0,0] +; AVX512VBMI-NEXT: # zmm4 = mem[0,1,2,3,0,1,2,3] +; AVX512VBMI-NEXT: vpermi2b %zmm0, %zmm3, %zmm4 +; AVX512VBMI-NEXT: vbroadcasti64x4 {{.*#+}} zmm3 = [0,1,2,3,4,5,6,66,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,67,0,1,2,3,4,5,6,66,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,67] +; AVX512VBMI-NEXT: # zmm3 = mem[0,1,2,3,0,1,2,3] +; AVX512VBMI-NEXT: vpermi2b %zmm0, %zmm2, %zmm3 +; AVX512VBMI-NEXT: vpshufb {{.*#+}} zmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zmm0[1,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512VBMI-NEXT: vpshufb {{.*#+}} zmm1 = zmm1[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14],zero,zmm1[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63] +; AVX512VBMI-NEXT: vporq %zmm2, %zmm1, %zmm1 +; AVX512VBMI-NEXT: vmovdqa {{.*#+}} ymm2 = [u,u,u,u,u,u,u,u,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,71] +; AVX512VBMI-NEXT: vpermi2b %zmm0, %zmm6, %zmm2 +; AVX512VBMI-NEXT: vmovdqa64 {{.*#+}} zmm6 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,0,64,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,56,57,58,59,60,61,62,63] +; AVX512VBMI-NEXT: vpermi2b %zmm7, %zmm0, %zmm6 +; AVX512VBMI-NEXT: vpmovsxbw {{.*#+}} zmm0 = [0,1,2,3,33,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,20,21,22,23,24,25,26,27,28,29,30,31] +; AVX512VBMI-NEXT: vpermi2w %zmm7, %zmm3, %zmm0 +; AVX512VBMI-NEXT: vmovdqa64 {{.*#+}} zmm3 = [67,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,68,u,u,u,u,u,u,u] +; AVX512VBMI-NEXT: vpermi2b %zmm7, %zmm4, %zmm3 +; AVX512VBMI-NEXT: vinserti32x4 $3, %xmm7, %zmm5, %zmm4 +; AVX512VBMI-NEXT: vpshufb {{.*#+}} zmm4 = zmm4[u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,53,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512VBMI-NEXT: vbroadcasti64x4 {{.*#+}} zmm5 = [16,17,18,19,35,0,0,0,8,9,10,11,12,13,14,15,16,17,18,19,35,0,0,0,8,9,10,11,12,13,14,15] +; AVX512VBMI-NEXT: # zmm5 = mem[0,1,2,3,0,1,2,3] +; AVX512VBMI-NEXT: vpermi2w %zmm7, %zmm8, %zmm5 +; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm7, %zmm2, %zmm2 +; AVX512VBMI-NEXT: vpshufb {{.*#+}} zmm2 = zmm2[u,u,u,u,u,u,u,u,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,39,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512VBMI-NEXT: vmovdqa64 {{.*#+}} zmm8 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,65,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63] +; AVX512VBMI-NEXT: vpermi2b %zmm7, %zmm1, %zmm8 +; AVX512VBMI-NEXT: vmovdqa64 %zmm5, 320(%rdi) +; AVX512VBMI-NEXT: vmovdqa64 %zmm4, 256(%rdi) +; AVX512VBMI-NEXT: vmovdqa64 %zmm3, 192(%rdi) +; AVX512VBMI-NEXT: vmovdqa64 %zmm0, 128(%rdi) +; AVX512VBMI-NEXT: vmovdqa64 %zmm8, 64(%rdi) +; AVX512VBMI-NEXT: vmovdqa64 %zmm6, (%rdi) +; AVX512VBMI-NEXT: vmovdqa64 %zmm2, 384(%rdi) +; AVX512VBMI-NEXT: movq %rbp, %rsp +; AVX512VBMI-NEXT: popq %rbp +; AVX512VBMI-NEXT: vzeroupper +; AVX512VBMI-NEXT: retq + %shuffle1 = shufflevector <512 x i8> %a0, <512 x i8> zeroinitializer, <512 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, i32 4, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 280, i32 281, i32 282, i32 283, i32 284, i32 285, i32 286, i32 287, i32 288, i32 289, i32 290, i32 291, i32 292, i32 293, i32 294, i32 295, i32 296, i32 297, i32 298, i32 299, i32 300, i32 301, i32 302, i32 5, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 336, i32 337, i32 338, i32 339, i32 340, i32 341, i32 342, i32 343, i32 344, i32 345, i32 346, i32 347, i32 348, i32 349, i32 350, i32 351, i32 352, i32 353, i32 354, i32 355, i32 356, i32 357, i32 358, i32 6, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 392, i32 393, i32 394, i32 395, i32 396, i32 397, i32 398, i32 399, i32 400, i32 401, i32 402, i32 403, i32 404, i32 405, i32 406, i32 407, i32 408, i32 409, i32 410, i32 411, i32 412, i32 413, i32 414, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %shuffle2 = shufflevector <512 x i8> %shuffle1, <512 x i8> %a1, <512 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 512, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79, i32 513, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127, i32 128, i32 129, i32 130, i32 131, i32 132, i32 133, i32 134, i32 135, i32 514, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 168, i32 169, i32 170, i32 171, i32 172, i32 173, i32 174, i32 175, i32 176, i32 177, i32 178, i32 179, i32 180, i32 181, i32 182, i32 183, i32 184, i32 185, i32 186, i32 187, i32 188, i32 189, i32 190, i32 191, i32 515, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 224, i32 225, i32 226, i32 227, i32 228, i32 229, i32 230, i32 231, i32 232, i32 233, i32 234, i32 235, i32 236, i32 237, i32 238, i32 239, i32 240, i32 241, i32 242, i32 243, i32 244, i32 245, i32 246, i32 247, i32 516, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 280, i32 281, i32 282, i32 283, i32 284, i32 285, i32 286, i32 287, i32 288, i32 289, i32 290, i32 291, i32 292, i32 293, i32 294, i32 295, i32 296, i32 297, i32 298, i32 299, i32 300, i32 301, i32 302, i32 303, i32 517, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 336, i32 337, i32 338, i32 339, i32 340, i32 341, i32 342, i32 343, i32 344, i32 345, i32 346, i32 347, i32 348, i32 349, i32 350, i32 351, i32 352, i32 353, i32 354, i32 355, i32 356, i32 357, i32 358, i32 359, i32 518, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 392, i32 393, i32 394, i32 395, i32 396, i32 397, i32 398, i32 399, i32 400, i32 401, i32 402, i32 403, i32 404, i32 405, i32 406, i32 407, i32 408, i32 409, i32 410, i32 411, i32 412, i32 413, i32 414, i32 415, i32 519, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + ret <512 x i8> %shuffle2 +} + define <64 x i8> @shuffle_v32i16_zextinreg_to_v16i32(<64 x i8> %a) { ; ALL-LABEL: shuffle_v32i16_zextinreg_to_v16i32: ; ALL: # %bb.0: diff --git a/llvm/test/MC/AArch64/armv8.6a-fgt.s b/llvm/test/MC/AArch64/armv8.6a-fgt.s index 11002aca5e1a..632a531bfaee 100644 --- a/llvm/test/MC/AArch64/armv8.6a-fgt.s +++ b/llvm/test/MC/AArch64/armv8.6a-fgt.s @@ -1,75 +1,149 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+fgt < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=NOFGT +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.6a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fgt < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fgt < %s \ +// RUN: | llvm-objdump -d --mattr=+fgt - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fgt < %s \ +// RUN: | llvm-objdump -d --mattr=-fgt - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fgt < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+fgt -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + msr HFGRTR_EL2, x0 +// CHECK-INST: msr HFGRTR_EL2, x0 +// CHECK-ENCODING: encoding: [0x80,0x11,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c1180 msr S3_4_C1_C1_4, x0 + msr HFGWTR_EL2, x5 +// CHECK-INST: msr HFGWTR_EL2, x5 +// CHECK-ENCODING: encoding: [0xa5,0x11,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c11a5 msr S3_4_C1_C1_5, x5 + msr HFGITR_EL2, x10 +// CHECK-INST: msr HFGITR_EL2, x10 +// CHECK-ENCODING: encoding: [0xca,0x11,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c11ca msr S3_4_C1_C1_6, x10 + msr HDFGRTR_EL2, x15 +// CHECK-INST: msr HDFGRTR_EL2, x15 +// CHECK-ENCODING: encoding: [0x8f,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c318f msr S3_4_C3_C1_4, x15 + msr HDFGWTR_EL2, x20 +// CHECK-INST: msr HDFGWTR_EL2, x20 +// CHECK-ENCODING: encoding: [0xb4,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c31b4 msr S3_4_C3_C1_5, x20 + msr HAFGRTR_EL2, x25 -// CHECK: msr HFGRTR_EL2, x0 // encoding: [0x80,0x11,0x1c,0xd5] -// CHECK: msr HFGWTR_EL2, x5 // encoding: [0xa5,0x11,0x1c,0xd5] -// CHECK: msr HFGITR_EL2, x10 // encoding: [0xca,0x11,0x1c,0xd5] -// CHECK: msr HDFGRTR_EL2, x15 // encoding: [0x8f,0x31,0x1c,0xd5] -// CHECK: msr HDFGWTR_EL2, x20 // encoding: [0xb4,0x31,0x1c,0xd5] -// CHECK: msr HAFGRTR_EL2, x25 // encoding: [0xd9,0x31,0x1c,0xd5] -// NOFGT: error: expected writable system register or pstate -// NOFGT: error: expected writable system register or pstate -// NOFGT: error: expected writable system register or pstate -// NOFGT: error: expected writable system register or pstate -// NOFGT: error: expected writable system register or pstate -// NOFGT: error: expected writable system register or pstate +// CHECK-INST: msr HAFGRTR_EL2, x25 +// CHECK-ENCODING: encoding: [0xd9,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c31d9 msr S3_4_C3_C1_6, x25 mrs x30, HFGRTR_EL2 +// CHECK-INST: mrs x30, HFGRTR_EL2 +// CHECK-ENCODING: encoding: [0x9e,0x11,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register +// CHECK-UNKNOWN: d53c119e mrs x30, S3_4_C1_C1_4 + mrs x25, HFGWTR_EL2 +// CHECK-INST: mrs x25, HFGWTR_EL2 +// CHECK-ENCODING: encoding: [0xb9,0x11,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register +// CHECK-UNKNOWN: d53c11b9 mrs x25, S3_4_C1_C1_5 + mrs x20, HFGITR_EL2 +// CHECK-INST: mrs x20, HFGITR_EL2 +// CHECK-ENCODING: encoding: [0xd4,0x11,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register +// CHECK-UNKNOWN: d53c11d4 mrs x20, S3_4_C1_C1_6 + mrs x15, HDFGRTR_EL2 +// CHECK-INST: mrs x15, HDFGRTR_EL2 +// CHECK-ENCODING: encoding: [0x8f,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register +// CHECK-UNKNOWN: d53c318f mrs x15, S3_4_C3_C1_4 + mrs x10, HDFGWTR_EL2 -mrs x5, HAFGRTR_EL2 -// CHECK: mrs x30, HFGRTR_EL2 // encoding: [0x9e,0x11,0x3c,0xd5] -// CHECK: mrs x25, HFGWTR_EL2 // encoding: [0xb9,0x11,0x3c,0xd5] -// CHECK: mrs x20, HFGITR_EL2 // encoding: [0xd4,0x11,0x3c,0xd5] -// CHECK: mrs x15, HDFGRTR_EL2 // encoding: [0x8f,0x31,0x3c,0xd5] -// CHECK: mrs x10, HDFGWTR_EL2 // encoding: [0xaa,0x31,0x3c,0xd5] -// CHECK: mrs x5, HAFGRTR_EL2 // encoding: [0xc5,0x31,0x3c,0xd5] -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register +// CHECK-INST: mrs x10, HDFGWTR_EL2 +// CHECK-ENCODING: encoding: [0xaa,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register +// CHECK-UNKNOWN: d53c31aa mrs x10, S3_4_C3_C1_5 +mrs x5, HAFGRTR_EL2 +// CHECK-INST: mrs x5, HAFGRTR_EL2 +// CHECK-ENCODING: encoding: [0xc5,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:11: error: expected readable system register +// CHECK-UNKNOWN: d53c31c5 mrs x5, S3_4_C3_C1_6 mrs x3, HDFGRTR2_EL2 +// CHECK-INST: mrs x3, HDFGRTR2_EL2 +// CHECK-ENCODING: encoding: [0x03,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register +// CHECK-UNKNOWN: d53c3103 mrs x3, S3_4_C3_C1_0 + mrs x3, HDFGWTR2_EL2 +// CHECK-INST: mrs x3, HDFGWTR2_EL2 +// CHECK-ENCODING: encoding: [0x23,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register +// CHECK-UNKNOWN: d53c3123 mrs x3, S3_4_C3_C1_1 + mrs x3, HFGRTR2_EL2 +// CHECK-INST: mrs x3, HFGRTR2_EL2 +// CHECK-ENCODING: encoding: [0x43,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register +// CHECK-UNKNOWN: d53c3143 mrs x3, S3_4_C3_C1_2 + mrs x3, HFGWTR2_EL2 -mrs x3, HFGITR2_EL2 -// CHECK: mrs x3, HDFGRTR2_EL2 // encoding: [0x03,0x31,0x3c,0xd5] -// CHECK: mrs x3, HDFGWTR2_EL2 // encoding: [0x23,0x31,0x3c,0xd5] -// CHECK: mrs x3, HFGRTR2_EL2 // encoding: [0x43,0x31,0x3c,0xd5] -// CHECK: mrs x3, HFGWTR2_EL2 // encoding: [0x63,0x31,0x3c,0xd5] -// CHECK: mrs x3, HFGITR2_EL2 // encoding: [0xe3,0x31,0x3c,0xd5] -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register -// NOFGT: error: expected readable system register +// CHECK-INST: mrs x3, HFGWTR2_EL2 +// CHECK-ENCODING: encoding: [0x63,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register +// CHECK-UNKNOWN: d53c3163 mrs x3, S3_4_C3_C1_3 +mrs x3, HFGITR2_EL2 +// CHECK-INST: mrs x3, HFGITR2_EL2 +// CHECK-ENCODING: encoding: [0xe3,0x31,0x3c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:9: error: expected readable system register +// CHECK-UNKNOWN: d53c31e3 mrs x3, S3_4_C3_C1_7 msr HDFGRTR2_EL2, x3 +// CHECK-INST: msr HDFGRTR2_EL2, x3 +// CHECK-ENCODING: encoding: [0x03,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c3103 msr S3_4_C3_C1_0, x3 + msr HDFGWTR2_EL2, x3 +// CHECK-INST: msr HDFGWTR2_EL2, x3 +// CHECK-ENCODING: encoding: [0x23,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c3123 msr S3_4_C3_C1_1, x3 + msr HFGRTR2_EL2, x3 +// CHECK-INST: msr HFGRTR2_EL2, x3 +// CHECK-ENCODING: encoding: [0x43,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c3143 msr S3_4_C3_C1_2, x3 + msr HFGWTR2_EL2, x3 +// CHECK-INST: msr HFGWTR2_EL2, x3 +// CHECK-ENCODING: encoding: [0x63,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c3163 msr S3_4_C3_C1_3, x3 + msr HFGITR2_EL2, x3 -// CHECK: msr HDFGRTR2_EL2, x3 // encoding: [0x03,0x31,0x1c,0xd5] -// CHECK: msr HDFGWTR2_EL2, x3 // encoding: [0x23,0x31,0x1c,0xd5] -// CHECK: msr HFGRTR2_EL2, x3 // encoding: [0x43,0x31,0x1c,0xd5] -// CHECK: msr HFGWTR2_EL2, x3 // encoding: [0x63,0x31,0x1c,0xd5] -// CHECK: msr HFGITR2_EL2, x3 // encoding: [0xe3,0x31,0x1c,0xd5] -// NOFGT: error: expected writable system register -// NOFGT: error: expected writable system register -// NOFGT: error: expected writable system register -// NOFGT: error: expected writable system register -// NOFGT: error: expected writable system register +// CHECK-INST: msr HFGITR2_EL2, x3 +// CHECK-ENCODING: encoding: [0xe3,0x31,0x1c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:5: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c31e3 msr S3_4_C3_C1_7, x3 diff --git a/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s b/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s new file mode 100644 index 000000000000..a9a8612bc048 --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.8a-mops-diagnostics.s @@ -0,0 +1,227 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops,+mte < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a,+mte < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + + +// All operand must be different from each other + +// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same +cpyfp [x0]!, [x0]!, x1! +cpyfp [x0]!, [x1]!, x0! +cpyfp [x1]!, [x0]!, x0! + +// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same +cpyfm [x0]!, [x0]!, x1! +cpyfm [x0]!, [x1]!, x0! +cpyfm [x1]!, [x0]!, x0! + +// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same +cpyfe [x0]!, [x0]!, x1! +cpyfe [x0]!, [x1]!, x0! +cpyfe [x1]!, [x0]!, x0! + +// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same +cpyp [x0]!, [x0]!, x1! +cpyp [x0]!, [x1]!, x0! +cpyp [x1]!, [x0]!, x0! + +// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same +cpym [x0]!, [x0]!, x1! +cpym [x0]!, [x1]!, x0! +cpym [x1]!, [x0]!, x0! + +// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same +cpye [x0]!, [x0]!, x1! +cpye [x0]!, [x1]!, x0! +cpye [x1]!, [x0]!, x0! + +// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same +setp [x0]!, x0!, x1 +setp [x0]!, x1!, x0 +setp [x1]!, x0!, x0 + +// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same +setm [x0]!, x0!, x1 +setm [x0]!, x1!, x0 +setm [x1]!, x0!, x0 + +// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same +sete [x0]!, x0!, x1 +sete [x0]!, x1!, x0 +sete [x1]!, x0!, x0 + +// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same +setgp [x0]!, x0!, x1 +setgp [x0]!, x1!, x0 +setgp [x1]!, x0!, x0 + +// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same +setgm [x0]!, x0!, x1 +setgm [x0]!, x1!, x0 +setgm [x1]!, x0!, x0 + +// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same +// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same +// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same +setge [x0]!, x0!, x1 +setge [x0]!, x1!, x0 +setge [x1]!, x0!, x0 + +// SP cannot be used as argument at any position + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyfp [sp]!, [x1]!, x2! +cpyfp [x0]!, [sp]!, x2! +cpyfp [x0]!, [x1]!, sp! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyfm [sp]!, [x1]!, x2! +cpyfm [x0]!, [sp]!, x2! +cpyfm [x0]!, [x1]!, sp! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyfe [sp]!, [x1]!, x2! +cpyfe [x0]!, [sp]!, x2! +cpyfe [x0]!, [x1]!, sp! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyp [sp]!, [x2]!, x2! +cpyp [x0]!, [sp]!, x2! +cpyp [x0]!, [x1]!, sp! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpym [sp]!, [x2]!, x2! +cpym [x0]!, [sp]!, x2! +cpym [x0]!, [x1]!, sp! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpye [sp]!, [x2]!, x2! +cpye [x0]!, [sp]!, x2! +cpye [x0]!, [x1]!, sp! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +setp [sp]!, x1!, x2 +setp [x0]!, sp!, x2 +setp [x0]!, x1!, sp + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +setm [sp]!, x1!, x2 +setm [x0]!, sp!, x2 +setm [x0]!, x1!, sp + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +sete [sp]!, x1!, x2 +sete [x0]!, sp!, x2 +sete [x0]!, x1!, sp + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +setgp [sp]!, x1!, x2 +setgp [x0]!, sp!, x2 +setgp [x0]!, x1!, sp + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +setgm [sp]!, x1!, x2 +setgm [x0]!, sp!, x2 +setgm [x0]!, x1!, sp + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +setge [sp]!, x1!, x2 +setge [x0]!, sp!, x2 +setge [x0]!, x1!, sp + +// XZR can only be used at: +// - the size operand in CPY. +// - the size or source operands in SET. + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyfp [xzr]!, [x1]!, x2! +cpyfp [x0]!, [xzr]!, x2! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyfm [xzr]!, [x1]!, x2! +cpyfm [x0]!, [xzr]!, x2! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyfe [xzr]!, [x1]!, x2! +cpyfe [x0]!, [xzr]!, x2! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpyp [xzr]!, [x2]!, x2! +cpyp [x0]!, [xzr]!, x2! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpym [xzr]!, [x2]!, x2! +cpym [x0]!, [xzr]!, x2! + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: error: invalid operand for instruction +cpye [xzr]!, [x2]!, x2! +cpye [x0]!, [xzr]!, x2! + +// CHECK-ERROR: error: invalid operand for instruction +setp [xzr]!, x1!, x2 + +// CHECK-ERROR: error: invalid operand for instruction +setm [xzr]!, x1!, x2 + +// CHECK-ERROR: error: invalid operand for instruction +sete [xzr]!, x1!, x2 + +// CHECK-ERROR: error: invalid operand for instruction +setgp [xzr]!, x1!, x2 + +// CHECK-ERROR: error: invalid operand for instruction +setgm [xzr]!, x1!, x2 + +// CHECK-ERROR: error: invalid operand for instruction +setge [xzr]!, x1!, x2 diff --git a/llvm/test/MC/AArch64/armv8.8a-mops.s b/llvm/test/MC/AArch64/armv8.8a-mops.s index f8d75e73d47d..10a551d05251 100644 --- a/llvm/test/MC/AArch64/armv8.8a-mops.s +++ b/llvm/test/MC/AArch64/armv8.8a-mops.s @@ -1,654 +1,849 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops,+mte < %s 2> %t | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MTE -// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a,+mte < %s 2> %t | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MTE -// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mops < %s 2> %t | FileCheck %s --check-prefix=CHECK -// RUN: FileCheck --check-prefix=CHECK-NO-MTE-ERR %s < %t -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a < %s 2> %t | FileCheck %s --check-prefix=CHECK -// RUN: FileCheck --check-prefix=CHECK-NO-MTE-ERR %s < %t -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-NO-MOPS-ERR --check-prefix=CHECK-NO-MOPSMTE-ERR %s < %t - -// CHECK: [0x40,0x04,0x01,0x19] -// CHECK-NEXT: [0x40,0x44,0x01,0x19] -// CHECK-NEXT: [0x40,0x84,0x01,0x19] -// CHECK-NEXT: [0x40,0xc4,0x01,0x19] -// CHECK-NEXT: [0x40,0x14,0x01,0x19] -// CHECK-NEXT: [0x40,0x54,0x01,0x19] -// CHECK-NEXT: [0x40,0x94,0x01,0x19] -// CHECK-NEXT: [0x40,0xd4,0x01,0x19] -// CHECK-NEXT: [0x40,0x24,0x01,0x19] -// CHECK-NEXT: [0x40,0x64,0x01,0x19] -// CHECK-NEXT: [0x40,0xa4,0x01,0x19] -// CHECK-NEXT: [0x40,0xe4,0x01,0x19] -// CHECK-NEXT: [0x40,0x34,0x01,0x19] -// CHECK-NEXT: [0x40,0x74,0x01,0x19] -// CHECK-NEXT: [0x40,0xb4,0x01,0x19] -// CHECK-NEXT: [0x40,0xf4,0x01,0x19] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mops,+mte < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.8a,+mte < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mops,+mte < %s \ +// RUN: | llvm-objdump -d --mattr=+mops,+mte - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mops,+mte < %s \ +// RUN: | llvm-objdump -d --mattr=-mops,-mte - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mops,+mte < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+mops,+mte -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + cpyfp [x0]!, [x1]!, x2! +// CHECK-INST: cpyfp [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x04,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19010440 <unknown> + cpyfpwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfpwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x44,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19014440 <unknown> + cpyfprn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfprn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x84,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19018440 <unknown> + cpyfpn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfpn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xc4,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1901c440 <unknown> + cpyfpwt [x0]!, [x1]!, x2! +// CHECK-INST: cpyfpwt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x14,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19011440 <unknown> + cpyfpwtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfpwtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x54,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19015440 <unknown> + cpyfpwtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfpwtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x94,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19019440 <unknown> + cpyfpwtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfpwtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xd4,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1901d440 <unknown> + cpyfprt [x0]!, [x1]!, x2! +// CHECK-INST: cpyfprt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x24,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19012440 <unknown> + cpyfprtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfprtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x64,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19016440 <unknown> + cpyfprtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfprtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xa4,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1901a440 <unknown> + cpyfprtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfprtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xe4,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1901e440 <unknown> + cpyfpt [x0]!, [x1]!, x2! +// CHECK-INST: cpyfpt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x34,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19013440 <unknown> + cpyfptwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfptwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x74,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19017440 <unknown> + cpyfptrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfptrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xb4,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1901b440 <unknown> + cpyfptn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfptn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xf4,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1901f440 <unknown> -// CHECK: [0x40,0x04,0x41,0x19] -// CHECK-NEXT: [0x40,0x44,0x41,0x19] -// CHECK-NEXT: [0x40,0x84,0x41,0x19] -// CHECK-NEXT: [0x40,0xc4,0x41,0x19] -// CHECK-NEXT: [0x40,0x14,0x41,0x19] -// CHECK-NEXT: [0x40,0x54,0x41,0x19] -// CHECK-NEXT: [0x40,0x94,0x41,0x19] -// CHECK-NEXT: [0x40,0xd4,0x41,0x19] -// CHECK-NEXT: [0x40,0x24,0x41,0x19] -// CHECK-NEXT: [0x40,0x64,0x41,0x19] -// CHECK-NEXT: [0x40,0xa4,0x41,0x19] -// CHECK-NEXT: [0x40,0xe4,0x41,0x19] -// CHECK-NEXT: [0x40,0x34,0x41,0x19] -// CHECK-NEXT: [0x40,0x74,0x41,0x19] -// CHECK-NEXT: [0x40,0xb4,0x41,0x19] -// CHECK-NEXT: [0x40,0xf4,0x41,0x19] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops cpyfm [x0]!, [x1]!, x2! +// CHECK-INST: cpyfm [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x04,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19410440 <unknown> + cpyfmwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x44,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19414440 <unknown> + cpyfmrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x84,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19418440 <unknown> + cpyfmn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xc4,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1941c440 <unknown> + cpyfmwt [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmwt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x14,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19411440 <unknown> + cpyfmwtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmwtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x54,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19415440 <unknown> + cpyfmwtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmwtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x94,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19419440 <unknown> + cpyfmwtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmwtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xd4,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1941d440 <unknown> + cpyfmrt [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmrt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x24,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19412440 <unknown> + cpyfmrtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmrtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x64,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19416440 <unknown> + cpyfmrtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmrtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xa4,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1941a440 <unknown> + cpyfmrtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmrtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xe4,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1941e440 <unknown> + cpyfmt [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x34,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19413440 <unknown> + cpyfmtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x74,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19417440 <unknown> + cpyfmtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xb4,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1941b440 <unknown> + cpyfmtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfmtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xf4,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1941f440 <unknown> -// CHECK: [0x40,0x04,0x81,0x19] -// CHECK-NEXT: [0x40,0x44,0x81,0x19] -// CHECK-NEXT: [0x40,0x84,0x81,0x19] -// CHECK-NEXT: [0x40,0xc4,0x81,0x19] -// CHECK-NEXT: [0x40,0x14,0x81,0x19] -// CHECK-NEXT: [0x40,0x54,0x81,0x19] -// CHECK-NEXT: [0x40,0x94,0x81,0x19] -// CHECK-NEXT: [0x40,0xd4,0x81,0x19] -// CHECK-NEXT: [0x40,0x24,0x81,0x19] -// CHECK-NEXT: [0x40,0x64,0x81,0x19] -// CHECK-NEXT: [0x40,0xa4,0x81,0x19] -// CHECK-NEXT: [0x40,0xe4,0x81,0x19] -// CHECK-NEXT: [0x40,0x34,0x81,0x19] -// CHECK-NEXT: [0x40,0x74,0x81,0x19] -// CHECK-NEXT: [0x40,0xb4,0x81,0x19] -// CHECK-NEXT: [0x40,0xf4,0x81,0x19] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops cpyfe [x0]!, [x1]!, x2! +// CHECK-INST: cpyfe [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x04,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19810440 <unknown> + cpyfewn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfewn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x44,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19814440 <unknown> + cpyfern [x0]!, [x1]!, x2! +// CHECK-INST: cpyfern [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x84,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19818440 <unknown> + cpyfen [x0]!, [x1]!, x2! +// CHECK-INST: cpyfen [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xc4,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1981c440 <unknown> + cpyfewt [x0]!, [x1]!, x2! +// CHECK-INST: cpyfewt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x14,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19811440 <unknown> + cpyfewtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfewtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x54,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19815440 <unknown> + cpyfewtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfewtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x94,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19819440 <unknown> + cpyfewtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfewtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xd4,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1981d440 <unknown> + cpyfert [x0]!, [x1]!, x2! +// CHECK-INST: cpyfert [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x24,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19812440 <unknown> + cpyfertwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfertwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x64,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19816440 <unknown> + cpyfertrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfertrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xa4,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1981a440 <unknown> + cpyfertn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfertn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xe4,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1981e440 <unknown> + cpyfet [x0]!, [x1]!, x2! +// CHECK-INST: cpyfet [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x34,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19813440 <unknown> + cpyfetwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfetwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x74,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19817440 <unknown> + cpyfetrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfetrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xb4,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1981b440 <unknown> + cpyfetn [x0]!, [x1]!, x2! +// CHECK-INST: cpyfetn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xf4,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1981f440 <unknown> -// CHECK: [0x40,0x04,0x01,0x1d] -// CHECK-NEXT: [0x40,0x44,0x01,0x1d] -// CHECK-NEXT: [0x40,0x84,0x01,0x1d] -// CHECK-NEXT: [0x40,0xc4,0x01,0x1d] -// CHECK-NEXT: [0x40,0x14,0x01,0x1d] -// CHECK-NEXT: [0x40,0x54,0x01,0x1d] -// CHECK-NEXT: [0x40,0x94,0x01,0x1d] -// CHECK-NEXT: [0x40,0xd4,0x01,0x1d] -// CHECK-NEXT: [0x40,0x24,0x01,0x1d] -// CHECK-NEXT: [0x40,0x64,0x01,0x1d] -// CHECK-NEXT: [0x40,0xa4,0x01,0x1d] -// CHECK-NEXT: [0x40,0xe4,0x01,0x1d] -// CHECK-NEXT: [0x40,0x34,0x01,0x1d] -// CHECK-NEXT: [0x40,0x74,0x01,0x1d] -// CHECK-NEXT: [0x40,0xb4,0x01,0x1d] -// CHECK-NEXT: [0x40,0xf4,0x01,0x1d] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops cpyp [x0]!, [x1]!, x2! +// CHECK-INST: cpyp [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x04,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d010440 <unknown> + cpypwn [x0]!, [x1]!, x2! +// CHECK-INST: cpypwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x44,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d014440 <unknown> + cpyprn [x0]!, [x1]!, x2! +// CHECK-INST: cpyprn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x84,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d018440 <unknown> + cpypn [x0]!, [x1]!, x2! +// CHECK-INST: cpypn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xc4,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d01c440 <unknown> + cpypwt [x0]!, [x1]!, x2! +// CHECK-INST: cpypwt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x14,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d011440 <unknown> + cpypwtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpypwtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x54,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d015440 <unknown> + cpypwtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpypwtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x94,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d019440 <unknown> + cpypwtn [x0]!, [x1]!, x2! +// CHECK-INST: cpypwtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xd4,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d01d440 <unknown> + cpyprt [x0]!, [x1]!, x2! +// CHECK-INST: cpyprt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x24,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d012440 <unknown> + cpyprtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyprtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x64,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d016440 <unknown> + cpyprtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyprtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xa4,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d01a440 <unknown> + cpyprtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyprtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xe4,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d01e440 <unknown> + cpypt [x0]!, [x1]!, x2! +// CHECK-INST: cpypt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x34,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d013440 <unknown> + cpyptwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyptwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x74,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d017440 <unknown> + cpyptrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyptrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xb4,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d01b440 <unknown> + cpyptn [x0]!, [x1]!, x2! +// CHECK-INST: cpyptn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xf4,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d01f440 <unknown> -// CHECK: [0x40,0x04,0x41,0x1d] -// CHECK-NEXT: [0x40,0x44,0x41,0x1d] -// CHECK-NEXT: [0x40,0x84,0x41,0x1d] -// CHECK-NEXT: [0x40,0xc4,0x41,0x1d] -// CHECK-NEXT: [0x40,0x14,0x41,0x1d] -// CHECK-NEXT: [0x40,0x54,0x41,0x1d] -// CHECK-NEXT: [0x40,0x94,0x41,0x1d] -// CHECK-NEXT: [0x40,0xd4,0x41,0x1d] -// CHECK-NEXT: [0x40,0x24,0x41,0x1d] -// CHECK-NEXT: [0x40,0x64,0x41,0x1d] -// CHECK-NEXT: [0x40,0xa4,0x41,0x1d] -// CHECK-NEXT: [0x40,0xe4,0x41,0x1d] -// CHECK-NEXT: [0x40,0x34,0x41,0x1d] -// CHECK-NEXT: [0x40,0x74,0x41,0x1d] -// CHECK-NEXT: [0x40,0xb4,0x41,0x1d] -// CHECK-NEXT: [0x40,0xf4,0x41,0x1d] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops cpym [x0]!, [x1]!, x2! +// CHECK-INST: cpym [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x04,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d410440 <unknown> + cpymwn [x0]!, [x1]!, x2! +// CHECK-INST: cpymwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x44,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d414440 <unknown> + cpymrn [x0]!, [x1]!, x2! +// CHECK-INST: cpymrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x84,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d418440 <unknown> + cpymn [x0]!, [x1]!, x2! +// CHECK-INST: cpymn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xc4,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d41c440 <unknown> + cpymwt [x0]!, [x1]!, x2! +// CHECK-INST: cpymwt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x14,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d411440 <unknown> + cpymwtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpymwtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x54,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d415440 <unknown> + cpymwtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpymwtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x94,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d419440 <unknown> + cpymwtn [x0]!, [x1]!, x2! +// CHECK-INST: cpymwtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xd4,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d41d440 <unknown> + cpymrt [x0]!, [x1]!, x2! +// CHECK-INST: cpymrt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x24,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d412440 <unknown> + cpymrtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpymrtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x64,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d416440 <unknown> + cpymrtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpymrtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xa4,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d41a440 <unknown> + cpymrtn [x0]!, [x1]!, x2! +// CHECK-INST: cpymrtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xe4,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d41e440 <unknown> + cpymt [x0]!, [x1]!, x2! +// CHECK-INST: cpymt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x34,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d413440 <unknown> + cpymtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpymtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x74,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d417440 <unknown> + cpymtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpymtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xb4,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d41b440 <unknown> + cpymtn [x0]!, [x1]!, x2! +// CHECK-INST: cpymtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xf4,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d41f440 <unknown> -// CHECK: [0x40,0x04,0x81,0x1d] -// CHECK-NEXT: [0x40,0x44,0x81,0x1d] -// CHECK-NEXT: [0x40,0x84,0x81,0x1d] -// CHECK-NEXT: [0x40,0xc4,0x81,0x1d] -// CHECK-NEXT: [0x40,0x14,0x81,0x1d] -// CHECK-NEXT: [0x40,0x54,0x81,0x1d] -// CHECK-NEXT: [0x40,0x94,0x81,0x1d] -// CHECK-NEXT: [0x40,0xd4,0x81,0x1d] -// CHECK-NEXT: [0x40,0x24,0x81,0x1d] -// CHECK-NEXT: [0x40,0x64,0x81,0x1d] -// CHECK-NEXT: [0x40,0xa4,0x81,0x1d] -// CHECK-NEXT: [0x40,0xe4,0x81,0x1d] -// CHECK-NEXT: [0x40,0x34,0x81,0x1d] -// CHECK-NEXT: [0x40,0x74,0x81,0x1d] -// CHECK-NEXT: [0x40,0xb4,0x81,0x1d] -// CHECK-NEXT: [0x40,0xf4,0x81,0x1d] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops cpye [x0]!, [x1]!, x2! +// CHECK-INST: cpye [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x04,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d810440 <unknown> + cpyewn [x0]!, [x1]!, x2! +// CHECK-INST: cpyewn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x44,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d814440 <unknown> + cpyern [x0]!, [x1]!, x2! +// CHECK-INST: cpyern [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x84,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d818440 <unknown> + cpyen [x0]!, [x1]!, x2! +// CHECK-INST: cpyen [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xc4,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d81c440 <unknown> + cpyewt [x0]!, [x1]!, x2! +// CHECK-INST: cpyewt [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x14,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d811440 <unknown> + cpyewtwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyewtwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x54,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d815440 <unknown> + cpyewtrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyewtrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x94,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d819440 <unknown> + cpyewtn [x0]!, [x1]!, x2! +// CHECK-INST: cpyewtn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xd4,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d81d440 <unknown> + cpyert [x0]!, [x1]!, x2! +// CHECK-INST: cpyert [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x24,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d812440 <unknown> + cpyertwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyertwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x64,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d816440 <unknown> + cpyertrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyertrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xa4,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d81a440 <unknown> + cpyertn [x0]!, [x1]!, x2! +// CHECK-INST: cpyertn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xe4,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d81e440 <unknown> + cpyet [x0]!, [x1]!, x2! +// CHECK-INST: cpyet [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x34,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d813440 <unknown> + cpyetwn [x0]!, [x1]!, x2! +// CHECK-INST: cpyetwn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0x74,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d817440 <unknown> + cpyetrn [x0]!, [x1]!, x2! +// CHECK-INST: cpyetrn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xb4,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d81b440 <unknown> + cpyetn [x0]!, [x1]!, x2! +// CHECK-INST: cpyetn [x0]!, [x1]!, x2! +// CHECK-ENCODING: encoding: [0x40,0xf4,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d81f440 <unknown> -// CHECK: [0x20,0x04,0xc2,0x19] -// CHECK-NEXT: [0x20,0x14,0xc2,0x19] -// CHECK-NEXT: [0x20,0x24,0xc2,0x19] -// CHECK-NEXT: [0x20,0x34,0xc2,0x19] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops setp [x0]!, x1!, x2 +// CHECK-INST: setp [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x04,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c20420 <unknown> + setpt [x0]!, x1!, x2 +// CHECK-INST: setpt [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x14,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c21420 <unknown> + setpn [x0]!, x1!, x2 +// CHECK-INST: setpn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x24,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c22420 <unknown> + setptn [x0]!, x1!, x2 +// CHECK-INST: setptn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x34,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c23420 <unknown> -// CHECK: [0x20,0x44,0xc2,0x19] -// CHECK: [0x20,0x54,0xc2,0x19] -// CHECK: [0x20,0x64,0xc2,0x19] -// CHECK: [0x20,0x74,0xc2,0x19] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops setm [x0]!, x1!, x2 +// CHECK-INST: setm [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x44,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c24420 <unknown> + setmt [x0]!, x1!, x2 +// CHECK-INST: setmt [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x54,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c25420 <unknown> + setmn [x0]!, x1!, x2 +// CHECK-INST: setmn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x64,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c26420 <unknown> + setmtn [x0]!, x1!, x2 +// CHECK-INST: setmtn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x74,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c27420 <unknown> -// CHECK: [0x20,0x84,0xc2,0x19] -// CHECK: [0x20,0x94,0xc2,0x19] -// CHECK: [0x20,0xa4,0xc2,0x19] -// CHECK: [0x20,0xb4,0xc2,0x19] -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops -// CHECK-NO-MOPS-ERR: error: instruction requires: mops sete [x0]!, x1!, x2 +// CHECK-INST: sete [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x84,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c28420 <unknown> + setet [x0]!, x1!, x2 +// CHECK-INST: setet [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x94,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c29420 <unknown> + seten [x0]!, x1!, x2 +// CHECK-INST: seten [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0xa4,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c2a420 <unknown> + setetn [x0]!, x1!, x2 +// CHECK-INST: setetn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0xb4,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c2b420 <unknown> -// CHECK-MTE: [0x20,0x04,0xc2,0x1d] -// CHECK-MTE: [0x20,0x14,0xc2,0x1d] -// CHECK-MTE: [0x20,0x24,0xc2,0x1d] -// CHECK-MTE: [0x20,0x34,0xc2,0x1d] -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte setgp [x0]!, x1!, x2 +// CHECK-INST: setgp [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x04,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc20420 <unknown> + setgpt [x0]!, x1!, x2 +// CHECK-INST: setgpt [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x14,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc21420 <unknown> + setgpn [x0]!, x1!, x2 +// CHECK-INST: setgpn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x24,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc22420 <unknown> + setgptn [x0]!, x1!, x2 +// CHECK-INST: setgptn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x34,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc23420 <unknown> -// CHECK-MTE: [0x20,0x44,0xc2,0x1d] -// CHECK-MTE: [0x20,0x54,0xc2,0x1d] -// CHECK-MTE: [0x20,0x64,0xc2,0x1d] -// CHECK-MTE: [0x20,0x74,0xc2,0x1d] -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte setgm [x0]!, x1!, x2 +// CHECK-INST: setgm [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x44,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc24420 <unknown> + setgmt [x0]!, x1!, x2 +// CHECK-INST: setgmt [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x54,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc25420 <unknown> + setgmn [x0]!, x1!, x2 +// CHECK-INST: setgmn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x64,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc26420 <unknown> + setgmtn [x0]!, x1!, x2 +// CHECK-INST: setgmtn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x74,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc27420 <unknown> -// CHECK-MTE: [0x20,0x84,0xc2,0x1d] -// CHECK-MTE: [0x20,0x94,0xc2,0x1d] -// CHECK-MTE: [0x20,0xa4,0xc2,0x1d] -// CHECK-MTE: [0x20,0xb4,0xc2,0x1d] -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MTE-ERR: error: instruction requires: mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte -// CHECK-NO-MOPSMTE-ERR: error: instruction requires: mops mte setge [x0]!, x1!, x2 +// CHECK-INST: setge [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x84,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc28420 <unknown> + setget [x0]!, x1!, x2 +// CHECK-INST: setget [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0x94,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc29420 <unknown> + setgen [x0]!, x1!, x2 -setgetn [x0]!, x1!, x2 +// CHECK-INST: setgen [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0xa4,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc2a420 <unknown> -// All operand must be different from each other - -// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same -cpyfp [x0]!, [x0]!, x1! -cpyfp [x0]!, [x1]!, x0! -cpyfp [x1]!, [x0]!, x0! - -// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same -cpyfm [x0]!, [x0]!, x1! -cpyfm [x0]!, [x1]!, x0! -cpyfm [x1]!, [x0]!, x0! - -// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same -cpyfe [x0]!, [x0]!, x1! -cpyfe [x0]!, [x1]!, x0! -cpyfe [x1]!, [x0]!, x0! - -// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same -cpyp [x0]!, [x0]!, x1! -cpyp [x0]!, [x1]!, x0! -cpyp [x1]!, [x0]!, x0! - -// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same -cpym [x0]!, [x0]!, x1! -cpym [x0]!, [x1]!, x0! -cpym [x1]!, [x0]!, x0! - -// CHECK-ERROR: error: invalid CPY instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid CPY instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid CPY instruction, source and size registers are the same -cpye [x0]!, [x0]!, x1! -cpye [x0]!, [x1]!, x0! -cpye [x1]!, [x0]!, x0! - -// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same -setp [x0]!, x0!, x1 -setp [x0]!, x1!, x0 -setp [x1]!, x0!, x0 - -// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same -setm [x0]!, x0!, x1 -setm [x0]!, x1!, x0 -setm [x1]!, x0!, x0 - -// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same -sete [x0]!, x0!, x1 -sete [x0]!, x1!, x0 -sete [x1]!, x0!, x0 - -// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same -setgp [x0]!, x0!, x1 -setgp [x0]!, x1!, x0 -setgp [x1]!, x0!, x0 - -// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same -setgm [x0]!, x0!, x1 -setgm [x0]!, x1!, x0 -setgm [x1]!, x0!, x0 - -// CHECK-ERROR: error: invalid SET instruction, destination and size registers are the same -// CHECK-ERROR: error: invalid SET instruction, destination and source registers are the same -// CHECK-ERROR: error: invalid SET instruction, source and size registers are the same -setge [x0]!, x0!, x1 -setge [x0]!, x1!, x0 -setge [x1]!, x0!, x0 - -// SP cannot be used as argument at any position - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -cpyfp [sp]!, [x1]!, x2! -cpyfp [x0]!, [sp]!, x2! -cpyfp [x0]!, [x1]!, sp! - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -cpyfm [sp]!, [x1]!, x2! -cpyfm [x0]!, [sp]!, x2! -cpyfm [x0]!, [x1]!, sp! - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -cpyfe [sp]!, [x1]!, x2! -cpyfe [x0]!, [sp]!, x2! -cpyfe [x0]!, [x1]!, sp! - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -cpyp [sp]!, [x2]!, x2! -cpyp [x0]!, [sp]!, x2! -cpyp [x0]!, [x1]!, sp! - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -cpym [sp]!, [x2]!, x2! -cpym [x0]!, [sp]!, x2! -cpym [x0]!, [x1]!, sp! - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -cpye [sp]!, [x2]!, x2! -cpye [x0]!, [sp]!, x2! -cpye [x0]!, [x1]!, sp! - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -setp [sp]!, x1!, x2 -setp [x0]!, sp!, x2 -setp [x0]!, x1!, sp - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -setm [sp]!, x1!, x2 -setm [x0]!, sp!, x2 -setm [x0]!, x1!, sp - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -sete [sp]!, x1!, x2 -sete [x0]!, sp!, x2 -sete [x0]!, x1!, sp - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -setgp [sp]!, x1!, x2 -setgp [x0]!, sp!, x2 -setgp [x0]!, x1!, sp - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -setgm [sp]!, x1!, x2 -setgm [x0]!, sp!, x2 -setgm [x0]!, x1!, sp - -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -setge [sp]!, x1!, x2 -setge [x0]!, sp!, x2 -setge [x0]!, x1!, sp +setgetn [x0]!, x1!, x2 +// CHECK-INST: setgetn [x0]!, x1!, x2 +// CHECK-ENCODING: encoding: [0x20,0xb4,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops mte +// CHECK-UNKNOWN: 1dc2b420 <unknown> // XZR can only be used at: // - the size operand in CPY. // - the size or source operands in SET. -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: cpyfp [x0]!, [x1]!, xzr! -cpyfp [xzr]!, [x1]!, x2! -cpyfp [x0]!, [xzr]!, x2! cpyfp [x0]!, [x1]!, xzr! +// CHECK-INST: cpyfp [x0]!, [x1]!, xzr! +// CHECK-ENCODING: encoding: [0xe0,0x07,0x01,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 190107e0 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: cpyfm [x0]!, [x1]!, xzr! -cpyfm [xzr]!, [x1]!, x2! -cpyfm [x0]!, [xzr]!, x2! cpyfm [x0]!, [x1]!, xzr! +// CHECK-INST: cpyfm [x0]!, [x1]!, xzr! +// CHECK-ENCODING: encoding: [0xe0,0x07,0x41,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 194107e0 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: cpyfe [x0]!, [x1]!, xzr! -cpyfe [xzr]!, [x1]!, x2! -cpyfe [x0]!, [xzr]!, x2! cpyfe [x0]!, [x1]!, xzr! +// CHECK-INST: cpyfe [x0]!, [x1]!, xzr! +// CHECK-ENCODING: encoding: [0xe0,0x07,0x81,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 198107e0 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: cpyp [x0]!, [x1]!, xzr! -cpyp [xzr]!, [x2]!, x2! -cpyp [x0]!, [xzr]!, x2! cpyp [x0]!, [x1]!, xzr! +// CHECK-INST: cpyp [x0]!, [x1]!, xzr! +// CHECK-ENCODING: encoding: [0xe0,0x07,0x01,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d0107e0 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: cpym [x0]!, [x1]!, xzr! -cpym [xzr]!, [x2]!, x2! -cpym [x0]!, [xzr]!, x2! cpym [x0]!, [x1]!, xzr! +// CHECK-INST: cpym [x0]!, [x1]!, xzr! +// CHECK-ENCODING: encoding: [0xe0,0x07,0x41,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d4107e0 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: cpye [x0]!, [x1]!, xzr! -cpye [xzr]!, [x2]!, x2! -cpye [x0]!, [xzr]!, x2! cpye [x0]!, [x1]!, xzr! +// CHECK-INST: cpye [x0]!, [x1]!, xzr! +// CHECK-ENCODING: encoding: [0xe0,0x07,0x81,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1d8107e0 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: setp [x0]!, xzr!, x2 -// CHECK: setp [x0]!, x1!, xzr -setp [xzr]!, x1!, x2 setp [x0]!, xzr!, x2 +// CHECK-INST: setp [x0]!, xzr!, x2 +// CHECK-ENCODING: encoding: [0xe0,0x07,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c207e0 <unknown> + setp [x0]!, x1!, xzr +// CHECK-INST: setp [x0]!, x1!, xzr +// CHECK-ENCODING: encoding: [0x20,0x04,0xdf,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19df0420 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: setm [x0]!, xzr!, x2 -// CHECK: setm [x0]!, x1!, xzr -setm [xzr]!, x1!, x2 setm [x0]!, xzr!, x2 +// CHECK-INST: setm [x0]!, xzr!, x2 +// CHECK-ENCODING: encoding: [0xe0,0x47,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c247e0 <unknown> + setm [x0]!, x1!, xzr +// CHECK-INST: setm [x0]!, x1!, xzr +// CHECK-ENCODING: encoding: [0x20,0x44,0xdf,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19df4420 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK: sete [x0]!, xzr!, x2 -// CHECK: sete [x0]!, x1!, xzr -sete [xzr]!, x1!, x2 sete [x0]!, xzr!, x2 +// CHECK-INST: sete [x0]!, xzr!, x2 +// CHECK-ENCODING: encoding: [0xe0,0x87,0xc2,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19c287e0 <unknown> + sete [x0]!, x1!, xzr +// CHECK-INST: sete [x0]!, x1!, xzr +// CHECK-ENCODING: encoding: [0x20,0x84,0xdf,0x19] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 19df8420 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-MTE: setgp [x0]!, xzr!, x2 -// CHECK-MTE: setgp [x0]!, x1!, xzr -setgp [xzr]!, x1!, x2 setgp [x0]!, xzr!, x2 +// CHECK-INST: setgp [x0]!, xzr!, x2 +// CHECK-ENCODING: encoding: [0xe0,0x07,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1dc207e0 <unknown> + setgp [x0]!, x1!, xzr +// CHECK-INST: setgp [x0]!, x1!, xzr +// CHECK-ENCODING: encoding: [0x20,0x04,0xdf,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1ddf0420 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-MTE: setgm [x0]!, xzr!, x2 -// CHECK-MTE: setgm [x0]!, x1!, xzr -setgm [xzr]!, x1!, x2 setgm [x0]!, xzr!, x2 +// CHECK-INST: setgm [x0]!, xzr!, x2 +// CHECK-ENCODING: encoding: [0xe0,0x47,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1dc247e0 <unknown> + setgm [x0]!, x1!, xzr +// CHECK-INST: setgm [x0]!, x1!, xzr +// CHECK-ENCODING: encoding: [0x20,0x44,0xdf,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1ddf4420 <unknown> -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-MTE: setge [x0]!, xzr!, x2 -// CHECK-MTE: setge [x0]!, x1!, xzr -setge [xzr]!, x1!, x2 setge [x0]!, xzr!, x2 +// CHECK-INST: setge [x0]!, xzr!, x2 +// CHECK-ENCODING: encoding: [0xe0,0x87,0xc2,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1dc287e0 <unknown> + setge [x0]!, x1!, xzr +// CHECK-INST: setge [x0]!, x1!, xzr +// CHECK-ENCODING: encoding: [0x20,0x84,0xdf,0x1d] +// CHECK-ERROR: error: instruction requires: mops +// CHECK-UNKNOWN: 1ddf8420 <unknown> diff --git a/llvm/test/MC/AArch64/armv8.9a-ats1a.s b/llvm/test/MC/AArch64/armv8.9a-ats1a.s index a30d20663942..21b960e55d62 100644 --- a/llvm/test/MC/AArch64/armv8.9a-ats1a.s +++ b/llvm/test/MC/AArch64/armv8.9a-ats1a.s @@ -1,10 +1,26 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefixes=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + at s1e1a, x1 -// CHECK: at s1e1a, x1 // encoding: [0x41,0x79,0x08,0xd5] +// CHECK-INST: at s1e1a, x1 +// CHECK-ENCODING: encoding: [0x41,0x79,0x08,0xd5] +// CHECK-UNKNOWN: d5087941 at s1e1a, x1 at s1e2a, x1 -// CHECK: at s1e2a, x1 // encoding: [0x41,0x79,0x0c,0xd5] +// CHECK-INST: at s1e2a, x1 +// CHECK-ENCODING: encoding: [0x41,0x79,0x0c,0xd5] +// CHECK-UNKNOWN: d50c7941 at s1e2a, x1 at s1e3a, x1 -// CHECK: at s1e3a, x1 // encoding: [0x41,0x79,0x0e,0xd5] +// CHECK-INST: at s1e3a, x1 +// CHECK-ENCODING: encoding: [0x41,0x79,0x0e,0xd5] +// CHECK-UNKNOWN: d50e7941 at s1e3a, x1 diff --git a/llvm/test/MC/AArch64/armv8.9a-clrbhb.s b/llvm/test/MC/AArch64/armv8.9a-clrbhb.s index 96de61f50f58..9b5bfec86185 100644 --- a/llvm/test/MC/AArch64/armv8.9a-clrbhb.s +++ b/llvm/test/MC/AArch64/armv8.9a-clrbhb.s @@ -2,42 +2,56 @@ // Assembly is always permitted for instructions in the hint space. // Optional, off by default -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8a < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8.8a < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9a < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9.3a < %s | FileCheck %s --check-prefix=HINT_22 // Optional, off by default, doubly disabled -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8.8a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9.3a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 // Optional, off by default, manually enabled -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8.8a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9.3a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // Mandatory, enabled by default -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.9a < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.4a < %s | FileCheck %s --check-prefix=CLRBHB +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8.9a < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9.4a < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // Mandatory, on by default, doubly enabled -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.9a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.4a,+clrbhb < %s | FileCheck %s --check-prefix=CLRBHB +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8.9a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9.4a,+clrbhb < %s | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // Mandatory, can't prevent disabling in LLVM -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v8.9a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 -// RUN: llvm-mc -show-encoding -triple aarch64-none-elf -mattr=+v9.4a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 - - clrbhb - hint #22 - -// CLRBHB: clrbhb // encoding: [0xdf,0x22,0x03,0xd5] -// CLRBHB: clrbhb // encoding: [0xdf,0x22,0x03,0xd5] -// HINT_22: hint #22 // encoding: [0xdf,0x22,0x03,0xd5] -// HINT_22: hint #22 // encoding: [0xdf,0x22,0x03,0xd5] +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v8.9a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 +// RUN: llvm-mc -show-encoding -triple aarch64 -mattr=+v9.4a,-clrbhb < %s | FileCheck %s --check-prefix=HINT_22 + +// Check Unknown +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+clrbhb < %s \ +// RUN: | llvm-objdump -d --mattr=-clrbhb --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+clrbhb < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+clrbhb -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +clrbhb +// HINT_22: hint #22 // encoding: [0xdf,0x22,0x03,0xd5] +// CHECK-INST: clrbhb +// CHECK-ENCODING: encoding: [0xdf,0x22,0x03,0xd5] +// CHECK-UNKNOWN: d50322df hint #22 + +hint #22 +// HINT_22: hint #22 // encoding: [0xdf,0x22,0x03,0xd5] +// CHECK-INST: clrbhb +// CHECK-ENCODING: encoding: [0xdf,0x22,0x03,0xd5] +// CHECK-UNKNOWN: d50322df hint #22 diff --git a/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s b/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s index 0b74905c27fb..db5cb0701036 100644 --- a/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s +++ b/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s @@ -1,485 +1,1785 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ite < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a -mattr=+ite < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+ite < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a -mattr=+ite < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+ite < %s | FileCheck %s - -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.8a,+ite < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.9a,+ite < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.3a,+ite < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a,+ite < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+ite < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+ite < %s \ +// RUN: | llvm-objdump -d --mattr=+ite --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+ite < %s \ +// RUN: | llvm-objdump -d --mattr=-ite --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+ite < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+ite -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +mrs x3, DBGBVR0_EL1 +// CHECK-INST: mrs x3, DBGBVR0_EL1 +// CHECK-ENCODING: encoding: [0x83,0x00,0x30,0xd5] +// CHECK-UNKNOWN: d5300083 mrs x3, DBGBVR0_EL1 + +msr DBGBVR0_EL1, x1 +// CHECK-INST: msr DBGBVR0_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x00,0x10,0xd5] +// CHECK-UNKNOWN: d5100081 msr DBGBVR0_EL1, x1 + +mrs x3, DBGBVR1_EL1 +// CHECK-INST: mrs x3, DBGBVR1_EL1 +// CHECK-ENCODING: encoding: [0x83,0x01,0x30,0xd5] +// CHECK-UNKNOWN: d5300183 mrs x3, DBGBVR1_EL1 + +msr DBGBVR1_EL1, x1 +// CHECK-INST: msr DBGBVR1_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x01,0x10,0xd5] +// CHECK-UNKNOWN: d5100181 msr DBGBVR1_EL1, x1 + +mrs x3, DBGBVR2_EL1 +// CHECK-INST: mrs x3, DBGBVR2_EL1 +// CHECK-ENCODING: encoding: [0x83,0x02,0x30,0xd5] +// CHECK-UNKNOWN: d5300283 mrs x3, DBGBVR2_EL1 + +msr DBGBVR2_EL1, x1 +// CHECK-INST: msr DBGBVR2_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x02,0x10,0xd5] +// CHECK-UNKNOWN: d5100281 msr DBGBVR2_EL1, x1 + +mrs x3, DBGBVR3_EL1 +// CHECK-INST: mrs x3, DBGBVR3_EL1 +// CHECK-ENCODING: encoding: [0x83,0x03,0x30,0xd5] +// CHECK-UNKNOWN: d5300383 mrs x3, DBGBVR3_EL1 + +msr DBGBVR3_EL1, x1 +// CHECK-INST: msr DBGBVR3_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x03,0x10,0xd5] +// CHECK-UNKNOWN: d5100381 msr DBGBVR3_EL1, x1 + +mrs x3, DBGBVR4_EL1 +// CHECK-INST: mrs x3, DBGBVR4_EL1 +// CHECK-ENCODING: encoding: [0x83,0x04,0x30,0xd5] +// CHECK-UNKNOWN: d5300483 mrs x3, DBGBVR4_EL1 + +msr DBGBVR4_EL1, x1 +// CHECK-INST: msr DBGBVR4_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x04,0x10,0xd5] +// CHECK-UNKNOWN: d5100481 msr DBGBVR4_EL1, x1 + +mrs x3, DBGBVR5_EL1 +// CHECK-INST: mrs x3, DBGBVR5_EL1 +// CHECK-ENCODING: encoding: [0x83,0x05,0x30,0xd5] +// CHECK-UNKNOWN: d5300583 mrs x3, DBGBVR5_EL1 + +msr DBGBVR5_EL1, x1 +// CHECK-INST: msr DBGBVR5_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x05,0x10,0xd5] +// CHECK-UNKNOWN: d5100581 msr DBGBVR5_EL1, x1 + +mrs x3, DBGBVR6_EL1 +// CHECK-INST: mrs x3, DBGBVR6_EL1 +// CHECK-ENCODING: encoding: [0x83,0x06,0x30,0xd5] +// CHECK-UNKNOWN: d5300683 mrs x3, DBGBVR6_EL1 + +msr DBGBVR6_EL1, x1 +// CHECK-INST: msr DBGBVR6_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x06,0x10,0xd5] +// CHECK-UNKNOWN: d5100681 msr DBGBVR6_EL1, x1 + +mrs x3, DBGBVR7_EL1 +// CHECK-INST: mrs x3, DBGBVR7_EL1 +// CHECK-ENCODING: encoding: [0x83,0x07,0x30,0xd5] +// CHECK-UNKNOWN: d5300783 mrs x3, DBGBVR7_EL1 + +msr DBGBVR7_EL1, x1 +// CHECK-INST: msr DBGBVR7_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x07,0x10,0xd5] +// CHECK-UNKNOWN: d5100781 msr DBGBVR7_EL1, x1 + +mrs x3, DBGBVR8_EL1 +// CHECK-INST: mrs x3, DBGBVR8_EL1 +// CHECK-ENCODING: encoding: [0x83,0x08,0x30,0xd5] +// CHECK-UNKNOWN: d5300883 mrs x3, DBGBVR8_EL1 + +msr DBGBVR8_EL1, x1 +// CHECK-INST: msr DBGBVR8_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x08,0x10,0xd5] +// CHECK-UNKNOWN: d5100881 msr DBGBVR8_EL1, x1 + +mrs x3, DBGBVR9_EL1 +// CHECK-INST: mrs x3, DBGBVR9_EL1 +// CHECK-ENCODING: encoding: [0x83,0x09,0x30,0xd5] +// CHECK-UNKNOWN: d5300983 mrs x3, DBGBVR9_EL1 + +msr DBGBVR9_EL1, x1 +// CHECK-INST: msr DBGBVR9_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x09,0x10,0xd5] +// CHECK-UNKNOWN: d5100981 msr DBGBVR9_EL1, x1 + +mrs x3, DBGBVR10_EL1 +// CHECK-INST: mrs x3, DBGBVR10_EL1 +// CHECK-ENCODING: encoding: [0x83,0x0a,0x30,0xd5] +// CHECK-UNKNOWN: d5300a83 mrs x3, DBGBVR10_EL1 + +msr DBGBVR10_EL1, x1 +// CHECK-INST: msr DBGBVR10_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x0a,0x10,0xd5] +// CHECK-UNKNOWN: d5100a81 msr DBGBVR10_EL1, x1 + +mrs x3, DBGBVR11_EL1 +// CHECK-INST: mrs x3, DBGBVR11_EL1 +// CHECK-ENCODING: encoding: [0x83,0x0b,0x30,0xd5] +// CHECK-UNKNOWN: d5300b83 mrs x3, DBGBVR11_EL1 + +msr DBGBVR11_EL1, x1 +// CHECK-INST: msr DBGBVR11_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x0b,0x10,0xd5] +// CHECK-UNKNOWN: d5100b81 msr DBGBVR11_EL1, x1 + +mrs x3, DBGBVR12_EL1 +// CHECK-INST: mrs x3, DBGBVR12_EL1 +// CHECK-ENCODING: encoding: [0x83,0x0c,0x30,0xd5] +// CHECK-UNKNOWN: d5300c83 mrs x3, DBGBVR12_EL1 + +msr DBGBVR12_EL1, x1 +// CHECK-INST: msr DBGBVR12_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x0c,0x10,0xd5] +// CHECK-UNKNOWN: d5100c81 msr DBGBVR12_EL1, x1 + +mrs x3, DBGBVR13_EL1 +// CHECK-INST: mrs x3, DBGBVR13_EL1 +// CHECK-ENCODING: encoding: [0x83,0x0d,0x30,0xd5] +// CHECK-UNKNOWN: d5300d83 mrs x3, DBGBVR13_EL1 + +msr DBGBVR13_EL1, x1 +// CHECK-INST: msr DBGBVR13_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x0d,0x10,0xd5] +// CHECK-UNKNOWN: d5100d81 msr DBGBVR13_EL1, x1 + +mrs x3, DBGBVR14_EL1 +// CHECK-INST: mrs x3, DBGBVR14_EL1 +// CHECK-ENCODING: encoding: [0x83,0x0e,0x30,0xd5] +// CHECK-UNKNOWN: d5300e83 mrs x3, DBGBVR14_EL1 + +msr DBGBVR14_EL1, x1 +// CHECK-INST: msr DBGBVR14_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x0e,0x10,0xd5] +// CHECK-UNKNOWN: d5100e81 msr DBGBVR14_EL1, x1 + +mrs x3, DBGBVR15_EL1 +// CHECK-INST: mrs x3, DBGBVR15_EL1 +// CHECK-ENCODING: encoding: [0x83,0x0f,0x30,0xd5] +// CHECK-UNKNOWN: d5300f83 mrs x3, DBGBVR15_EL1 + +msr DBGBVR15_EL1, x1 +// CHECK-INST: msr DBGBVR15_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x0f,0x10,0xd5] +// CHECK-UNKNOWN: d5100f81 msr DBGBVR15_EL1, x1 + +mrs x3, DBGBCR0_EL1 +// CHECK-INST: mrs x3, DBGBCR0_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x00,0x30,0xd5] +// CHECK-UNKNOWN: d53000a3 mrs x3, DBGBCR0_EL1 + +msr DBGBCR0_EL1, x1 +// CHECK-INST: msr DBGBCR0_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x00,0x10,0xd5] +// CHECK-UNKNOWN: d51000a1 msr DBGBCR0_EL1, x1 + +mrs x3, DBGBCR1_EL1 +// CHECK-INST: mrs x3, DBGBCR1_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x01,0x30,0xd5] +// CHECK-UNKNOWN: d53001a3 mrs x3, DBGBCR1_EL1 + +msr DBGBCR1_EL1, x1 +// CHECK-INST: msr DBGBCR1_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x01,0x10,0xd5] +// CHECK-UNKNOWN: d51001a1 msr DBGBCR1_EL1, x1 + +mrs x3, DBGBCR2_EL1 +// CHECK-INST: mrs x3, DBGBCR2_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x02,0x30,0xd5] +// CHECK-UNKNOWN: d53002a3 mrs x3, DBGBCR2_EL1 + +msr DBGBCR2_EL1, x1 +// CHECK-INST: msr DBGBCR2_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x02,0x10,0xd5] +// CHECK-UNKNOWN: d51002a1 msr DBGBCR2_EL1, x1 + +mrs x3, DBGBCR3_EL1 +// CHECK-INST: mrs x3, DBGBCR3_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x03,0x30,0xd5] +// CHECK-UNKNOWN: d53003a3 mrs x3, DBGBCR3_EL1 + +msr DBGBCR3_EL1, x1 +// CHECK-INST: msr DBGBCR3_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x03,0x10,0xd5] +// CHECK-UNKNOWN: d51003a1 msr DBGBCR3_EL1, x1 + +mrs x3, DBGBCR4_EL1 +// CHECK-INST: mrs x3, DBGBCR4_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x04,0x30,0xd5] +// CHECK-UNKNOWN: d53004a3 mrs x3, DBGBCR4_EL1 + +msr DBGBCR4_EL1, x1 +// CHECK-INST: msr DBGBCR4_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x04,0x10,0xd5] +// CHECK-UNKNOWN: d51004a1 msr DBGBCR4_EL1, x1 + +mrs x3, DBGBCR5_EL1 +// CHECK-INST: mrs x3, DBGBCR5_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x05,0x30,0xd5] +// CHECK-UNKNOWN: d53005a3 mrs x3, DBGBCR5_EL1 + +msr DBGBCR5_EL1, x1 +// CHECK-INST: msr DBGBCR5_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x05,0x10,0xd5] +// CHECK-UNKNOWN: d51005a1 msr DBGBCR5_EL1, x1 + +mrs x3, DBGBCR6_EL1 +// CHECK-INST: mrs x3, DBGBCR6_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x06,0x30,0xd5] +// CHECK-UNKNOWN: d53006a3 mrs x3, DBGBCR6_EL1 + +msr DBGBCR6_EL1, x1 +// CHECK-INST: msr DBGBCR6_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x06,0x10,0xd5] +// CHECK-UNKNOWN: d51006a1 msr DBGBCR6_EL1, x1 + +mrs x3, DBGBCR7_EL1 +// CHECK-INST: mrs x3, DBGBCR7_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x07,0x30,0xd5] +// CHECK-UNKNOWN: d53007a3 mrs x3, DBGBCR7_EL1 + +msr DBGBCR7_EL1, x1 +// CHECK-INST: msr DBGBCR7_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x07,0x10,0xd5] +// CHECK-UNKNOWN: d51007a1 msr DBGBCR7_EL1, x1 + +mrs x3, DBGBCR8_EL1 +// CHECK-INST: mrs x3, DBGBCR8_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x08,0x30,0xd5] +// CHECK-UNKNOWN: d53008a3 mrs x3, DBGBCR8_EL1 + +msr DBGBCR8_EL1, x1 +// CHECK-INST: msr DBGBCR8_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x08,0x10,0xd5] +// CHECK-UNKNOWN: d51008a1 msr DBGBCR8_EL1, x1 + +mrs x3, DBGBCR9_EL1 +// CHECK-INST: mrs x3, DBGBCR9_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x09,0x30,0xd5] +// CHECK-UNKNOWN: d53009a3 mrs x3, DBGBCR9_EL1 + +msr DBGBCR9_EL1, x1 +// CHECK-INST: msr DBGBCR9_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x09,0x10,0xd5] +// CHECK-UNKNOWN: d51009a1 msr DBGBCR9_EL1, x1 + +mrs x3, DBGBCR10_EL1 +// CHECK-INST: mrs x3, DBGBCR10_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x0a,0x30,0xd5] +// CHECK-UNKNOWN: d5300aa3 mrs x3, DBGBCR10_EL1 + +msr DBGBCR10_EL1, x1 +// CHECK-INST: msr DBGBCR10_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x0a,0x10,0xd5] +// CHECK-UNKNOWN: d5100aa1 msr DBGBCR10_EL1, x1 + +mrs x3, DBGBCR11_EL1 +// CHECK-INST: mrs x3, DBGBCR11_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x0b,0x30,0xd5] +// CHECK-UNKNOWN: d5300ba3 mrs x3, DBGBCR11_EL1 + +msr DBGBCR11_EL1, x1 +// CHECK-INST: msr DBGBCR11_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x0b,0x10,0xd5] +// CHECK-UNKNOWN: d5100ba1 msr DBGBCR11_EL1, x1 + +mrs x3, DBGBCR12_EL1 +// CHECK-INST: mrs x3, DBGBCR12_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x0c,0x30,0xd5] +// CHECK-UNKNOWN: d5300ca3 mrs x3, DBGBCR12_EL1 + +msr DBGBCR12_EL1, x1 +// CHECK-INST: msr DBGBCR12_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x0c,0x10,0xd5] +// CHECK-UNKNOWN: d5100ca1 msr DBGBCR12_EL1, x1 + +mrs x3, DBGBCR13_EL1 +// CHECK-INST: mrs x3, DBGBCR13_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x0d,0x30,0xd5] +// CHECK-UNKNOWN: d5300da3 mrs x3, DBGBCR13_EL1 + +msr DBGBCR13_EL1, x1 +// CHECK-INST: msr DBGBCR13_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x0d,0x10,0xd5] +// CHECK-UNKNOWN: d5100da1 msr DBGBCR13_EL1, x1 + +mrs x3, DBGBCR14_EL1 +// CHECK-INST: mrs x3, DBGBCR14_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x0e,0x30,0xd5] +// CHECK-UNKNOWN: d5300ea3 mrs x3, DBGBCR14_EL1 + +msr DBGBCR14_EL1, x1 +// CHECK-INST: msr DBGBCR14_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x0e,0x10,0xd5] +// CHECK-UNKNOWN: d5100ea1 msr DBGBCR14_EL1, x1 + +mrs x3, DBGBCR15_EL1 +// CHECK-INST: mrs x3, DBGBCR15_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x0f,0x30,0xd5] +// CHECK-UNKNOWN: d5300fa3 mrs x3, DBGBCR15_EL1 + +msr DBGBCR15_EL1, x1 +// CHECK-INST: msr DBGBCR15_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x0f,0x10,0xd5] +// CHECK-UNKNOWN: d5100fa1 msr DBGBCR15_EL1, x1 + +mrs x3, DBGWVR0_EL1 +// CHECK-INST: mrs x3, DBGWVR0_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x00,0x30,0xd5] +// CHECK-UNKNOWN: d53000c3 mrs x3, DBGWVR0_EL1 + +msr DBGWVR0_EL1, x1 +// CHECK-INST: msr DBGWVR0_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x00,0x10,0xd5] +// CHECK-UNKNOWN: d51000c1 msr DBGWVR0_EL1, x1 + +mrs x3, DBGWVR1_EL1 +// CHECK-INST: mrs x3, DBGWVR1_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x01,0x30,0xd5] +// CHECK-UNKNOWN: d53001c3 mrs x3, DBGWVR1_EL1 + +msr DBGWVR1_EL1, x1 +// CHECK-INST: msr DBGWVR1_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x01,0x10,0xd5] +// CHECK-UNKNOWN: d51001c1 msr DBGWVR1_EL1, x1 + +mrs x3, DBGWVR2_EL1 +// CHECK-INST: mrs x3, DBGWVR2_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x02,0x30,0xd5] +// CHECK-UNKNOWN: d53002c3 mrs x3, DBGWVR2_EL1 + +msr DBGWVR2_EL1, x1 +// CHECK-INST: msr DBGWVR2_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x02,0x10,0xd5] +// CHECK-UNKNOWN: d51002c1 msr DBGWVR2_EL1, x1 + +mrs x3, DBGWVR3_EL1 +// CHECK-INST: mrs x3, DBGWVR3_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x03,0x30,0xd5] +// CHECK-UNKNOWN: d53003c3 mrs x3, DBGWVR3_EL1 + +msr DBGWVR3_EL1, x1 +// CHECK-INST: msr DBGWVR3_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x03,0x10,0xd5] +// CHECK-UNKNOWN: d51003c1 msr DBGWVR3_EL1, x1 + +mrs x3, DBGWVR4_EL1 +// CHECK-INST: mrs x3, DBGWVR4_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x04,0x30,0xd5] +// CHECK-UNKNOWN: d53004c3 mrs x3, DBGWVR4_EL1 + +msr DBGWVR4_EL1, x1 +// CHECK-INST: msr DBGWVR4_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x04,0x10,0xd5] +// CHECK-UNKNOWN: d51004c1 msr DBGWVR4_EL1, x1 + +mrs x3, DBGWVR5_EL1 +// CHECK-INST: mrs x3, DBGWVR5_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x05,0x30,0xd5] +// CHECK-UNKNOWN: d53005c3 mrs x3, DBGWVR5_EL1 + +msr DBGWVR5_EL1, x1 +// CHECK-INST: msr DBGWVR5_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x05,0x10,0xd5] +// CHECK-UNKNOWN: d51005c1 msr DBGWVR5_EL1, x1 + +mrs x3, DBGWVR6_EL1 +// CHECK-INST: mrs x3, DBGWVR6_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x06,0x30,0xd5] +// CHECK-UNKNOWN: d53006c3 mrs x3, DBGWVR6_EL1 + +msr DBGWVR6_EL1, x1 +// CHECK-INST: msr DBGWVR6_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x06,0x10,0xd5] +// CHECK-UNKNOWN: d51006c1 msr DBGWVR6_EL1, x1 + +mrs x3, DBGWVR7_EL1 +// CHECK-INST: mrs x3, DBGWVR7_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x07,0x30,0xd5] +// CHECK-UNKNOWN: d53007c3 mrs x3, DBGWVR7_EL1 + +msr DBGWVR7_EL1, x1 +// CHECK-INST: msr DBGWVR7_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x07,0x10,0xd5] +// CHECK-UNKNOWN: d51007c1 msr DBGWVR7_EL1, x1 + +mrs x3, DBGWVR8_EL1 +// CHECK-INST: mrs x3, DBGWVR8_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x08,0x30,0xd5] +// CHECK-UNKNOWN: d53008c3 mrs x3, DBGWVR8_EL1 + +msr DBGWVR8_EL1, x1 +// CHECK-INST: msr DBGWVR8_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x08,0x10,0xd5] +// CHECK-UNKNOWN: d51008c1 msr DBGWVR8_EL1, x1 + +mrs x3, DBGWVR9_EL1 +// CHECK-INST: mrs x3, DBGWVR9_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x09,0x30,0xd5] +// CHECK-UNKNOWN: d53009c3 mrs x3, DBGWVR9_EL1 + +msr DBGWVR9_EL1, x1 +// CHECK-INST: msr DBGWVR9_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x09,0x10,0xd5] +// CHECK-UNKNOWN: d51009c1 msr DBGWVR9_EL1, x1 + +mrs x3, DBGWVR10_EL1 +// CHECK-INST: mrs x3, DBGWVR10_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x0a,0x30,0xd5] +// CHECK-UNKNOWN: d5300ac3 mrs x3, DBGWVR10_EL1 + +msr DBGWVR10_EL1, x1 +// CHECK-INST: msr DBGWVR10_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x0a,0x10,0xd5] +// CHECK-UNKNOWN: d5100ac1 msr DBGWVR10_EL1, x1 + +mrs x3, DBGWVR11_EL1 +// CHECK-INST: mrs x3, DBGWVR11_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x0b,0x30,0xd5] +// CHECK-UNKNOWN: d5300bc3 mrs x3, DBGWVR11_EL1 + +msr DBGWVR11_EL1, x1 +// CHECK-INST: msr DBGWVR11_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x0b,0x10,0xd5] +// CHECK-UNKNOWN: d5100bc1 msr DBGWVR11_EL1, x1 + +mrs x3, DBGWVR12_EL1 +// CHECK-INST: mrs x3, DBGWVR12_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x0c,0x30,0xd5] +// CHECK-UNKNOWN: d5300cc3 mrs x3, DBGWVR12_EL1 + +msr DBGWVR12_EL1, x1 +// CHECK-INST: msr DBGWVR12_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x0c,0x10,0xd5] +// CHECK-UNKNOWN: d5100cc1 msr DBGWVR12_EL1, x1 + +mrs x3, DBGWVR13_EL1 +// CHECK-INST: mrs x3, DBGWVR13_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x0d,0x30,0xd5] +// CHECK-UNKNOWN: d5300dc3 mrs x3, DBGWVR13_EL1 + +msr DBGWVR13_EL1, x1 +// CHECK-INST: msr DBGWVR13_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x0d,0x10,0xd5] +// CHECK-UNKNOWN: d5100dc1 msr DBGWVR13_EL1, x1 + +mrs x3, DBGWVR14_EL1 +// CHECK-INST: mrs x3, DBGWVR14_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x0e,0x30,0xd5] +// CHECK-UNKNOWN: d5300ec3 mrs x3, DBGWVR14_EL1 + +msr DBGWVR14_EL1, x1 +// CHECK-INST: msr DBGWVR14_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x0e,0x10,0xd5] +// CHECK-UNKNOWN: d5100ec1 msr DBGWVR14_EL1, x1 + +mrs x3, DBGWVR15_EL1 +// CHECK-INST: mrs x3, DBGWVR15_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x0f,0x30,0xd5] +// CHECK-UNKNOWN: d5300fc3 mrs x3, DBGWVR15_EL1 + +msr DBGWVR15_EL1, x1 +// CHECK-INST: msr DBGWVR15_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0x0f,0x10,0xd5] +// CHECK-UNKNOWN: d5100fc1 msr DBGWVR15_EL1, x1 + +mrs x3, DBGWCR0_EL1 +// CHECK-INST: mrs x3, DBGWCR0_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x00,0x30,0xd5] +// CHECK-UNKNOWN: d53000e3 mrs x3, DBGWCR0_EL1 + +msr DBGWCR0_EL1, x1 +// CHECK-INST: msr DBGWCR0_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x00,0x10,0xd5] +// CHECK-UNKNOWN: d51000e1 msr DBGWCR0_EL1, x1 + +mrs x3, DBGWCR1_EL1 +// CHECK-INST: mrs x3, DBGWCR1_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x01,0x30,0xd5] +// CHECK-UNKNOWN: d53001e3 mrs x3, DBGWCR1_EL1 + +msr DBGWCR1_EL1, x1 +// CHECK-INST: msr DBGWCR1_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x01,0x10,0xd5] +// CHECK-UNKNOWN: d51001e1 msr DBGWCR1_EL1, x1 + +mrs x3, DBGWCR2_EL1 +// CHECK-INST: mrs x3, DBGWCR2_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x02,0x30,0xd5] +// CHECK-UNKNOWN: d53002e3 mrs x3, DBGWCR2_EL1 + +msr DBGWCR2_EL1, x1 +// CHECK-INST: msr DBGWCR2_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x02,0x10,0xd5] +// CHECK-UNKNOWN: d51002e1 msr DBGWCR2_EL1, x1 + +mrs x3, DBGWCR3_EL1 +// CHECK-INST: mrs x3, DBGWCR3_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x03,0x30,0xd5] +// CHECK-UNKNOWN: d53003e3 mrs x3, DBGWCR3_EL1 + +msr DBGWCR3_EL1, x1 +// CHECK-INST: msr DBGWCR3_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x03,0x10,0xd5] +// CHECK-UNKNOWN: d51003e1 msr DBGWCR3_EL1, x1 + +mrs x3, DBGWCR4_EL1 +// CHECK-INST: mrs x3, DBGWCR4_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x04,0x30,0xd5] +// CHECK-UNKNOWN: d53004e3 mrs x3, DBGWCR4_EL1 + +msr DBGWCR4_EL1, x1 +// CHECK-INST: msr DBGWCR4_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x04,0x10,0xd5] +// CHECK-UNKNOWN: d51004e1 msr DBGWCR4_EL1, x1 + +mrs x3, DBGWCR5_EL1 +// CHECK-INST: mrs x3, DBGWCR5_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x05,0x30,0xd5] +// CHECK-UNKNOWN: d53005e3 mrs x3, DBGWCR5_EL1 + +msr DBGWCR5_EL1, x1 +// CHECK-INST: msr DBGWCR5_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x05,0x10,0xd5] +// CHECK-UNKNOWN: d51005e1 msr DBGWCR5_EL1, x1 + +mrs x3, DBGWCR6_EL1 +// CHECK-INST: mrs x3, DBGWCR6_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x06,0x30,0xd5] +// CHECK-UNKNOWN: d53006e3 mrs x3, DBGWCR6_EL1 + +msr DBGWCR6_EL1, x1 +// CHECK-INST: msr DBGWCR6_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x06,0x10,0xd5] +// CHECK-UNKNOWN: d51006e1 msr DBGWCR6_EL1, x1 + +mrs x3, DBGWCR7_EL1 +// CHECK-INST: mrs x3, DBGWCR7_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x07,0x30,0xd5] +// CHECK-UNKNOWN: d53007e3 mrs x3, DBGWCR7_EL1 + +msr DBGWCR7_EL1, x1 +// CHECK-INST: msr DBGWCR7_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x07,0x10,0xd5] +// CHECK-UNKNOWN: d51007e1 msr DBGWCR7_EL1, x1 + +mrs x3, DBGWCR8_EL1 +// CHECK-INST: mrs x3, DBGWCR8_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x08,0x30,0xd5] +// CHECK-UNKNOWN: d53008e3 mrs x3, DBGWCR8_EL1 + +msr DBGWCR8_EL1, x1 +// CHECK-INST: msr DBGWCR8_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x08,0x10,0xd5] +// CHECK-UNKNOWN: d51008e1 msr DBGWCR8_EL1, x1 + +mrs x3, DBGWCR9_EL1 +// CHECK-INST: mrs x3, DBGWCR9_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x09,0x30,0xd5] +// CHECK-UNKNOWN: d53009e3 mrs x3, DBGWCR9_EL1 + +msr DBGWCR9_EL1, x1 +// CHECK-INST: msr DBGWCR9_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x09,0x10,0xd5] +// CHECK-UNKNOWN: d51009e1 msr DBGWCR9_EL1, x1 + +mrs x3, DBGWCR10_EL1 +// CHECK-INST: mrs x3, DBGWCR10_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x0a,0x30,0xd5] +// CHECK-UNKNOWN: d5300ae3 mrs x3, DBGWCR10_EL1 + +msr DBGWCR10_EL1, x1 +// CHECK-INST: msr DBGWCR10_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x0a,0x10,0xd5] +// CHECK-UNKNOWN: d5100ae1 msr DBGWCR10_EL1, x1 + +mrs x3, DBGWCR11_EL1 +// CHECK-INST: mrs x3, DBGWCR11_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x0b,0x30,0xd5] +// CHECK-UNKNOWN: d5300be3 mrs x3, DBGWCR11_EL1 + +msr DBGWCR11_EL1, x1 +// CHECK-INST: msr DBGWCR11_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x0b,0x10,0xd5] +// CHECK-UNKNOWN: d5100be1 msr DBGWCR11_EL1, x1 + +mrs x3, DBGWCR12_EL1 +// CHECK-INST: mrs x3, DBGWCR12_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x0c,0x30,0xd5] +// CHECK-UNKNOWN: d5300ce3 mrs x3, DBGWCR12_EL1 + +msr DBGWCR12_EL1, x1 +// CHECK-INST: msr DBGWCR12_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x0c,0x10,0xd5] +// CHECK-UNKNOWN: d5100ce1 msr DBGWCR12_EL1, x1 + +mrs x3, DBGWCR13_EL1 +// CHECK-INST: mrs x3, DBGWCR13_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x0d,0x30,0xd5] +// CHECK-UNKNOWN: d5300de3 mrs x3, DBGWCR13_EL1 + +msr DBGWCR13_EL1, x1 +// CHECK-INST: msr DBGWCR13_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x0d,0x10,0xd5] +// CHECK-UNKNOWN: d5100de1 msr DBGWCR13_EL1, x1 + +mrs x3, DBGWCR14_EL1 +// CHECK-INST: mrs x3, DBGWCR14_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x0e,0x30,0xd5] +// CHECK-UNKNOWN: d5300ee3 mrs x3, DBGWCR14_EL1 + +msr DBGWCR14_EL1, x1 +// CHECK-INST: msr DBGWCR14_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x0e,0x10,0xd5] +// CHECK-UNKNOWN: d5100ee1 msr DBGWCR14_EL1, x1 + +mrs x3, DBGWCR15_EL1 +// CHECK-INST: mrs x3, DBGWCR15_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x0f,0x30,0xd5] +// CHECK-UNKNOWN: d5300fe3 mrs x3, DBGWCR15_EL1 + +msr DBGWCR15_EL1, x1 +// CHECK-INST: msr DBGWCR15_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x0f,0x10,0xd5] +// CHECK-UNKNOWN: d5100fe1 msr DBGWCR15_EL1, x1 // FEAT_DEBUGv8p9 - mrs x3, MDSELR_EL1 -// CHECK: mrs x3, MDSELR_EL1 // encoding: [0x43,0x04,0x30,0xd5] - msr MDSELR_EL1, x1 -// CHECK: msr MDSELR_EL1, x1 // encoding: [0x41,0x04,0x10,0xd5] +mrs x3, MDSELR_EL1 +// CHECK-INST: mrs x3, MDSELR_EL1 +// CHECK-ENCODING: encoding: [0x43,0x04,0x30,0xd5] +// CHECK-UNKNOWN: d5300443 mrs x3, MDSELR_EL1 + +msr MDSELR_EL1, x1 +// CHECK-INST: msr MDSELR_EL1, x1 +// CHECK-ENCODING: encoding: [0x41,0x04,0x10,0xd5] +// CHECK-UNKNOWN: d5100441 msr MDSELR_EL1, x1 // FEAT_PMUv3p9 - mrs x3, PMUACR_EL1 -// CHECK: mrs x3, PMUACR_EL1 // encoding: [0x83,0x9e,0x38,0xd5] - msr PMUACR_EL1, x1 -// CHECK: msr PMUACR_EL1, x1 // encoding: [0x81,0x9e,0x18,0xd5] +mrs x3, PMUACR_EL1 +// CHECK-INST: mrs x3, PMUACR_EL1 +// CHECK-ENCODING: encoding: [0x83,0x9e,0x38,0xd5] +// CHECK-UNKNOWN: d5389e83 mrs x3, PMUACR_EL1 + +msr PMUACR_EL1, x1 +// CHECK-INST: msr PMUACR_EL1, x1 +// CHECK-ENCODING: encoding: [0x81,0x9e,0x18,0xd5] +// CHECK-UNKNOWN: d5189e81 msr PMUACR_EL1, x1 // FEAT_PMUv3_SS - mrs x3, PMCCNTSVR_EL1 -// CHECK: mrs x3, PMCCNTSVR_EL1 // encoding: [0xe3,0xeb,0x30,0xd5] - mrs x3, PMICNTSVR_EL1 -// CHECK: mrs x3, PMICNTSVR_EL1 // encoding: [0x03,0xec,0x30,0xd5] - mrs x3, PMSSCR_EL1 -// CHECK: mrs x3, PMSSCR_EL1 // encoding: [0x63,0x9d,0x38,0xd5] - msr PMSSCR_EL1, x1 -// CHECK: msr PMSSCR_EL1, x1 // encoding: [0x61,0x9d,0x18,0xd5] - mrs x3, PMEVCNTSVR0_EL1 -// CHECK: mrs x3, PMEVCNTSVR0_EL1 // encoding: [0x03,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR1_EL1 -// CHECK: mrs x3, PMEVCNTSVR1_EL1 // encoding: [0x23,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR2_EL1 -// CHECK: mrs x3, PMEVCNTSVR2_EL1 // encoding: [0x43,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR3_EL1 -// CHECK: mrs x3, PMEVCNTSVR3_EL1 // encoding: [0x63,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR4_EL1 -// CHECK: mrs x3, PMEVCNTSVR4_EL1 // encoding: [0x83,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR5_EL1 -// CHECK: mrs x3, PMEVCNTSVR5_EL1 // encoding: [0xa3,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR6_EL1 -// CHECK: mrs x3, PMEVCNTSVR6_EL1 // encoding: [0xc3,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR7_EL1 -// CHECK: mrs x3, PMEVCNTSVR7_EL1 // encoding: [0xe3,0xe8,0x30,0xd5] - mrs x3, PMEVCNTSVR8_EL1 -// CHECK: mrs x3, PMEVCNTSVR8_EL1 // encoding: [0x03,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR9_EL1 -// CHECK: mrs x3, PMEVCNTSVR9_EL1 // encoding: [0x23,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR10_EL1 -// CHECK: mrs x3, PMEVCNTSVR10_EL1 // encoding: [0x43,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR11_EL1 -// CHECK: mrs x3, PMEVCNTSVR11_EL1 // encoding: [0x63,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR12_EL1 -// CHECK: mrs x3, PMEVCNTSVR12_EL1 // encoding: [0x83,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR13_EL1 -// CHECK: mrs x3, PMEVCNTSVR13_EL1 // encoding: [0xa3,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR14_EL1 -// CHECK: mrs x3, PMEVCNTSVR14_EL1 // encoding: [0xc3,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR15_EL1 -// CHECK: mrs x3, PMEVCNTSVR15_EL1 // encoding: [0xe3,0xe9,0x30,0xd5] - mrs x3, PMEVCNTSVR16_EL1 -// CHECK: mrs x3, PMEVCNTSVR16_EL1 // encoding: [0x03,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR17_EL1 -// CHECK: mrs x3, PMEVCNTSVR17_EL1 // encoding: [0x23,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR18_EL1 -// CHECK: mrs x3, PMEVCNTSVR18_EL1 // encoding: [0x43,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR19_EL1 -// CHECK: mrs x3, PMEVCNTSVR19_EL1 // encoding: [0x63,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR20_EL1 -// CHECK: mrs x3, PMEVCNTSVR20_EL1 // encoding: [0x83,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR21_EL1 -// CHECK: mrs x3, PMEVCNTSVR21_EL1 // encoding: [0xa3,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR22_EL1 -// CHECK: mrs x3, PMEVCNTSVR22_EL1 // encoding: [0xc3,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR23_EL1 -// CHECK: mrs x3, PMEVCNTSVR23_EL1 // encoding: [0xe3,0xea,0x30,0xd5] - mrs x3, PMEVCNTSVR24_EL1 -// CHECK: mrs x3, PMEVCNTSVR24_EL1 // encoding: [0x03,0xeb,0x30,0xd5] - mrs x3, PMEVCNTSVR25_EL1 -// CHECK: mrs x3, PMEVCNTSVR25_EL1 // encoding: [0x23,0xeb,0x30,0xd5] - mrs x3, PMEVCNTSVR26_EL1 -// CHECK: mrs x3, PMEVCNTSVR26_EL1 // encoding: [0x43,0xeb,0x30,0xd5] - mrs x3, PMEVCNTSVR27_EL1 -// CHECK: mrs x3, PMEVCNTSVR27_EL1 // encoding: [0x63,0xeb,0x30,0xd5] - mrs x3, PMEVCNTSVR28_EL1 -// CHECK: mrs x3, PMEVCNTSVR28_EL1 // encoding: [0x83,0xeb,0x30,0xd5] - mrs x3, PMEVCNTSVR29_EL1 -// CHECK: mrs x3, PMEVCNTSVR29_EL1 // encoding: [0xa3,0xeb,0x30,0xd5] - mrs x3, PMEVCNTSVR30_EL1 -// CHECK: mrs x3, PMEVCNTSVR30_EL1 // encoding: [0xc3,0xeb,0x30,0xd5] +mrs x3, PMCCNTSVR_EL1 +// CHECK-INST: mrs x3, PMCCNTSVR_EL1 +// CHECK-ENCODING: encoding: [0xe3,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530ebe3 mrs x3, PMCCNTSVR_EL1 + +mrs x3, PMICNTSVR_EL1 +// CHECK-INST: mrs x3, PMICNTSVR_EL1 +// CHECK-ENCODING: encoding: [0x03,0xec,0x30,0xd5] +// CHECK-UNKNOWN: d530ec03 mrs x3, PMICNTSVR_EL1 + +mrs x3, PMSSCR_EL1 +// CHECK-INST: mrs x3, PMSSCR_EL1 +// CHECK-ENCODING: encoding: [0x63,0x9d,0x38,0xd5] +// CHECK-UNKNOWN: d5389d63 mrs x3, PMSSCR_EL1 + +msr PMSSCR_EL1, x1 +// CHECK-INST: msr PMSSCR_EL1, x1 +// CHECK-ENCODING: encoding: [0x61,0x9d,0x18,0xd5] +// CHECK-UNKNOWN: d5189d61 msr PMSSCR_EL1, x1 + +mrs x3, PMEVCNTSVR0_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR0_EL1 +// CHECK-ENCODING: encoding: [0x03,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e803 mrs x3, PMEVCNTSVR0_EL1 + +mrs x3, PMEVCNTSVR1_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR1_EL1 +// CHECK-ENCODING: encoding: [0x23,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e823 mrs x3, PMEVCNTSVR1_EL1 + +mrs x3, PMEVCNTSVR2_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR2_EL1 +// CHECK-ENCODING: encoding: [0x43,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e843 mrs x3, PMEVCNTSVR2_EL1 + +mrs x3, PMEVCNTSVR3_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR3_EL1 +// CHECK-ENCODING: encoding: [0x63,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e863 mrs x3, PMEVCNTSVR3_EL1 + +mrs x3, PMEVCNTSVR4_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR4_EL1 +// CHECK-ENCODING: encoding: [0x83,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e883 mrs x3, PMEVCNTSVR4_EL1 + +mrs x3, PMEVCNTSVR5_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR5_EL1 +// CHECK-ENCODING: encoding: [0xa3,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e8a3 mrs x3, PMEVCNTSVR5_EL1 + +mrs x3, PMEVCNTSVR6_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR6_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e8c3 mrs x3, PMEVCNTSVR6_EL1 + +mrs x3, PMEVCNTSVR7_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR7_EL1 +// CHECK-ENCODING: encoding: [0xe3,0xe8,0x30,0xd5] +// CHECK-UNKNOWN: d530e8e3 mrs x3, PMEVCNTSVR7_EL1 + +mrs x3, PMEVCNTSVR8_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR8_EL1 +// CHECK-ENCODING: encoding: [0x03,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e903 mrs x3, PMEVCNTSVR8_EL1 + +mrs x3, PMEVCNTSVR9_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR9_EL1 +// CHECK-ENCODING: encoding: [0x23,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e923 mrs x3, PMEVCNTSVR9_EL1 + +mrs x3, PMEVCNTSVR10_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR10_EL1 +// CHECK-ENCODING: encoding: [0x43,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e943 mrs x3, PMEVCNTSVR10_EL1 + +mrs x3, PMEVCNTSVR11_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR11_EL1 +// CHECK-ENCODING: encoding: [0x63,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e963 mrs x3, PMEVCNTSVR11_EL1 + +mrs x3, PMEVCNTSVR12_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR12_EL1 +// CHECK-ENCODING: encoding: [0x83,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e983 mrs x3, PMEVCNTSVR12_EL1 + +mrs x3, PMEVCNTSVR13_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR13_EL1 +// CHECK-ENCODING: encoding: [0xa3,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e9a3 mrs x3, PMEVCNTSVR13_EL1 + +mrs x3, PMEVCNTSVR14_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR14_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e9c3 mrs x3, PMEVCNTSVR14_EL1 + +mrs x3, PMEVCNTSVR15_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR15_EL1 +// CHECK-ENCODING: encoding: [0xe3,0xe9,0x30,0xd5] +// CHECK-UNKNOWN: d530e9e3 mrs x3, PMEVCNTSVR15_EL1 + +mrs x3, PMEVCNTSVR16_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR16_EL1 +// CHECK-ENCODING: encoding: [0x03,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530ea03 mrs x3, PMEVCNTSVR16_EL1 + +mrs x3, PMEVCNTSVR17_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR17_EL1 +// CHECK-ENCODING: encoding: [0x23,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530ea23 mrs x3, PMEVCNTSVR17_EL1 + +mrs x3, PMEVCNTSVR18_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR18_EL1 +// CHECK-ENCODING: encoding: [0x43,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530ea43 mrs x3, PMEVCNTSVR18_EL1 + +mrs x3, PMEVCNTSVR19_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR19_EL1 +// CHECK-ENCODING: encoding: [0x63,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530ea63 mrs x3, PMEVCNTSVR19_EL1 + +mrs x3, PMEVCNTSVR20_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR20_EL1 +// CHECK-ENCODING: encoding: [0x83,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530ea83 mrs x3, PMEVCNTSVR20_EL1 + +mrs x3, PMEVCNTSVR21_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR21_EL1 +// CHECK-ENCODING: encoding: [0xa3,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530eaa3 mrs x3, PMEVCNTSVR21_EL1 + +mrs x3, PMEVCNTSVR22_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR22_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530eac3 mrs x3, PMEVCNTSVR22_EL1 + +mrs x3, PMEVCNTSVR23_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR23_EL1 +// CHECK-ENCODING: encoding: [0xe3,0xea,0x30,0xd5] +// CHECK-UNKNOWN: d530eae3 mrs x3, PMEVCNTSVR23_EL1 + +mrs x3, PMEVCNTSVR24_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR24_EL1 +// CHECK-ENCODING: encoding: [0x03,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530eb03 mrs x3, PMEVCNTSVR24_EL1 + +mrs x3, PMEVCNTSVR25_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR25_EL1 +// CHECK-ENCODING: encoding: [0x23,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530eb23 mrs x3, PMEVCNTSVR25_EL1 + +mrs x3, PMEVCNTSVR26_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR26_EL1 +// CHECK-ENCODING: encoding: [0x43,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530eb43 mrs x3, PMEVCNTSVR26_EL1 + +mrs x3, PMEVCNTSVR27_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR27_EL1 +// CHECK-ENCODING: encoding: [0x63,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530eb63 mrs x3, PMEVCNTSVR27_EL1 + +mrs x3, PMEVCNTSVR28_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR28_EL1 +// CHECK-ENCODING: encoding: [0x83,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530eb83 mrs x3, PMEVCNTSVR28_EL1 + +mrs x3, PMEVCNTSVR29_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR29_EL1 +// CHECK-ENCODING: encoding: [0xa3,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530eba3 mrs x3, PMEVCNTSVR29_EL1 + +mrs x3, PMEVCNTSVR30_EL1 +// CHECK-INST: mrs x3, PMEVCNTSVR30_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xeb,0x30,0xd5] +// CHECK-UNKNOWN: d530ebc3 mrs x3, PMEVCNTSVR30_EL1 // FEAT_PMUv3_ICNTR - mrs x3, PMICNTR_EL0 -// CHECK: mrs x3, PMICNTR_EL0 // encoding: [0x03,0x94,0x3b,0xd5] - msr PMICNTR_EL0, x3 -// CHECK: msr PMICNTR_EL0, x3 // encoding: [0x03,0x94,0x1b,0xd5] - mrs x3, PMICFILTR_EL0 -// CHECK: mrs x3, PMICFILTR_EL0 // encoding: [0x03,0x96,0x3b,0xd5] - msr PMICFILTR_EL0, x3 -// CHECK: msr PMICFILTR_EL0, x3 // encoding: [0x03,0x96,0x1b,0xd5] +mrs x3, PMICNTR_EL0 +// CHECK-INST: mrs x3, PMICNTR_EL0 +// CHECK-ENCODING: encoding: [0x03,0x94,0x3b,0xd5] +// CHECK-UNKNOWN: d53b9403 mrs x3, PMICNTR_EL0 + +msr PMICNTR_EL0, x3 +// CHECK-INST: msr PMICNTR_EL0, x3 +// CHECK-ENCODING: encoding: [0x03,0x94,0x1b,0xd5] +// CHECK-UNKNOWN: d51b9403 msr PMICNTR_EL0, x3 + +mrs x3, PMICFILTR_EL0 +// CHECK-INST: mrs x3, PMICFILTR_EL0 +// CHECK-ENCODING: encoding: [0x03,0x96,0x3b,0xd5] +// CHECK-UNKNOWN: d53b9603 mrs x3, PMICFILTR_EL0 + +msr PMICFILTR_EL0, x3 +// CHECK-INST: msr PMICFILTR_EL0, x3 +// CHECK-ENCODING: encoding: [0x03,0x96,0x1b,0xd5] +// CHECK-UNKNOWN: d51b9603 msr PMICFILTR_EL0, x3 // FEAT_PMUv3p9/FEAT_PMUV3_ICNTR - msr PMZR_EL0, x3 -// CHECK: msr PMZR_EL0, x3 // encoding: [0x83,0x9d,0x1b,0xd5] +msr PMZR_EL0, x3 +// CHECK-INST: msr PMZR_EL0, x3 +// CHECK-ENCODING: encoding: [0x83,0x9d,0x1b,0xd5] +// CHECK-UNKNOWN: d51b9d83 msr PMZR_EL0, x3 // FEAT_SEBEP - mrs x3, PMECR_EL1 -// CHECK: mrs x3, PMECR_EL1 // encoding: [0xa3,0x9e,0x38,0xd5] - msr PMECR_EL1, x1 -// CHECK: msr PMECR_EL1, x1 // encoding: [0xa1,0x9e,0x18,0xd5] - mrs x3, PMIAR_EL1 -// CHECK: mrs x3, PMIAR_EL1 // encoding: [0xe3,0x9e,0x38,0xd5] - msr PMIAR_EL1, x1 -// CHECK: msr PMIAR_EL1, x1 // encoding: [0xe1,0x9e,0x18,0xd5] +mrs x3, PMECR_EL1 +// CHECK-INST: mrs x3, PMECR_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x9e,0x38,0xd5] +// CHECK-UNKNOWN: d5389ea3 mrs x3, PMECR_EL1 + +msr PMECR_EL1, x1 +// CHECK-INST: msr PMECR_EL1, x1 +// CHECK-ENCODING: encoding: [0xa1,0x9e,0x18,0xd5] +// CHECK-UNKNOWN: d5189ea1 msr PMECR_EL1, x1 + +mrs x3, PMIAR_EL1 +// CHECK-INST: mrs x3, PMIAR_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x9e,0x38,0xd5] +// CHECK-UNKNOWN: d5389ee3 mrs x3, PMIAR_EL1 + +msr PMIAR_EL1, x1 +// CHECK-INST: msr PMIAR_EL1, x1 +// CHECK-ENCODING: encoding: [0xe1,0x9e,0x18,0xd5] +// CHECK-UNKNOWN: d5189ee1 msr PMIAR_EL1, x1 // FEAT_SPMU - mrs x3, SPMACCESSR_EL1 -// CHECK: mrs x3, SPMACCESSR_EL1 // encoding: [0x63,0x9d,0x30,0xd5] - msr SPMACCESSR_EL1, x1 -// CHECK: msr SPMACCESSR_EL1, x1 // encoding: [0x61,0x9d,0x10,0xd5] - mrs x3, SPMACCESSR_EL12 -// CHECK: mrs x3, SPMACCESSR_EL12 // encoding: [0x63,0x9d,0x35,0xd5] - msr SPMACCESSR_EL12, x1 -// CHECK: msr SPMACCESSR_EL12, x1 // encoding: [0x61,0x9d,0x15,0xd5] - mrs x3, SPMACCESSR_EL2 -// CHECK: mrs x3, SPMACCESSR_EL2 // encoding: [0x63,0x9d,0x34,0xd5] - msr SPMACCESSR_EL2, x1 -// CHECK: msr SPMACCESSR_EL2, x1 // encoding: [0x61,0x9d,0x14,0xd5] - mrs x3, SPMACCESSR_EL3 -// CHECK: mrs x3, SPMACCESSR_EL3 // encoding: [0x63,0x9d,0x36,0xd5] - msr SPMACCESSR_EL3, x1 -// CHECK: msr SPMACCESSR_EL3, x1 // encoding: [0x61,0x9d,0x16,0xd5] - mrs x3, SPMCNTENCLR_EL0 -// CHECK: mrs x3, SPMCNTENCLR_EL0 // encoding: [0x43,0x9c,0x33,0xd5] - msr SPMCNTENCLR_EL0, x1 -// CHECK: msr SPMCNTENCLR_EL0, x1 // encoding: [0x41,0x9c,0x13,0xd5] - mrs x3, SPMCNTENSET_EL0 -// CHECK: mrs x3, SPMCNTENSET_EL0 // encoding: [0x23,0x9c,0x33,0xd5] - msr SPMCNTENSET_EL0, x1 -// CHECK: msr SPMCNTENSET_EL0, x1 // encoding: [0x21,0x9c,0x13,0xd5] - mrs x3, SPMCR_EL0 -// CHECK: mrs x3, SPMCR_EL0 // encoding: [0x03,0x9c,0x33,0xd5] - msr SPMCR_EL0, x1 -// CHECK: msr SPMCR_EL0, x1 // encoding: [0x01,0x9c,0x13,0xd5] - mrs x3, SPMDEVAFF_EL1 -// CHECK: mrs x3, SPMDEVAFF_EL1 // encoding: [0xc3,0x9d,0x30,0xd5] - mrs x3, SPMDEVARCH_EL1 -// CHECK: mrs x3, SPMDEVARCH_EL1 // encoding: [0xa3,0x9d,0x30,0xd5] - - mrs x3, SPMEVCNTR0_EL0 -// CHECK: mrs x3, SPMEVCNTR0_EL0 // encoding: [0x03,0xe0,0x33,0xd5] - msr SPMEVCNTR0_EL0, x1 -// CHECK: msr SPMEVCNTR0_EL0, x1 // encoding: [0x01,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR1_EL0 -// CHECK: mrs x3, SPMEVCNTR1_EL0 // encoding: [0x23,0xe0,0x33,0xd5] - msr SPMEVCNTR1_EL0, x1 -// CHECK: msr SPMEVCNTR1_EL0, x1 // encoding: [0x21,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR2_EL0 -// CHECK: mrs x3, SPMEVCNTR2_EL0 // encoding: [0x43,0xe0,0x33,0xd5] - msr SPMEVCNTR2_EL0, x1 -// CHECK: msr SPMEVCNTR2_EL0, x1 // encoding: [0x41,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR3_EL0 -// CHECK: mrs x3, SPMEVCNTR3_EL0 // encoding: [0x63,0xe0,0x33,0xd5] - msr SPMEVCNTR3_EL0, x1 -// CHECK: msr SPMEVCNTR3_EL0, x1 // encoding: [0x61,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR4_EL0 -// CHECK: mrs x3, SPMEVCNTR4_EL0 // encoding: [0x83,0xe0,0x33,0xd5] - msr SPMEVCNTR4_EL0, x1 -// CHECK: msr SPMEVCNTR4_EL0, x1 // encoding: [0x81,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR5_EL0 -// CHECK: mrs x3, SPMEVCNTR5_EL0 // encoding: [0xa3,0xe0,0x33,0xd5] - msr SPMEVCNTR5_EL0, x1 -// CHECK: msr SPMEVCNTR5_EL0, x1 // encoding: [0xa1,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR6_EL0 -// CHECK: mrs x3, SPMEVCNTR6_EL0 // encoding: [0xc3,0xe0,0x33,0xd5] - msr SPMEVCNTR6_EL0, x1 -// CHECK: msr SPMEVCNTR6_EL0, x1 // encoding: [0xc1,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR7_EL0 -// CHECK: mrs x3, SPMEVCNTR7_EL0 // encoding: [0xe3,0xe0,0x33,0xd5] - msr SPMEVCNTR7_EL0, x1 -// CHECK: msr SPMEVCNTR7_EL0, x1 // encoding: [0xe1,0xe0,0x13,0xd5] - mrs x3, SPMEVCNTR8_EL0 -// CHECK: mrs x3, SPMEVCNTR8_EL0 // encoding: [0x03,0xe1,0x33,0xd5] - msr SPMEVCNTR8_EL0, x1 -// CHECK: msr SPMEVCNTR8_EL0, x1 // encoding: [0x01,0xe1,0x13,0xd5] - mrs x3, SPMEVCNTR9_EL0 -// CHECK: mrs x3, SPMEVCNTR9_EL0 // encoding: [0x23,0xe1,0x33,0xd5] - msr SPMEVCNTR9_EL0, x1 -// CHECK: msr SPMEVCNTR9_EL0, x1 // encoding: [0x21,0xe1,0x13,0xd5] - mrs x3, SPMEVCNTR10_EL0 -// CHECK: mrs x3, SPMEVCNTR10_EL0 // encoding: [0x43,0xe1,0x33,0xd5] - msr SPMEVCNTR10_EL0, x1 -// CHECK: msr SPMEVCNTR10_EL0, x1 // encoding: [0x41,0xe1,0x13,0xd5] - mrs x3, SPMEVCNTR11_EL0 -// CHECK: mrs x3, SPMEVCNTR11_EL0 // encoding: [0x63,0xe1,0x33,0xd5] - msr SPMEVCNTR11_EL0, x1 -// CHECK: msr SPMEVCNTR11_EL0, x1 // encoding: [0x61,0xe1,0x13,0xd5] - mrs x3, SPMEVCNTR12_EL0 -// CHECK: mrs x3, SPMEVCNTR12_EL0 // encoding: [0x83,0xe1,0x33,0xd5] - msr SPMEVCNTR12_EL0, x1 -// CHECK: msr SPMEVCNTR12_EL0, x1 // encoding: [0x81,0xe1,0x13,0xd5] - mrs x3, SPMEVCNTR13_EL0 -// CHECK: mrs x3, SPMEVCNTR13_EL0 // encoding: [0xa3,0xe1,0x33,0xd5] - msr SPMEVCNTR13_EL0, x1 -// CHECK: msr SPMEVCNTR13_EL0, x1 // encoding: [0xa1,0xe1,0x13,0xd5] - mrs x3, SPMEVCNTR14_EL0 -// CHECK: mrs x3, SPMEVCNTR14_EL0 // encoding: [0xc3,0xe1,0x33,0xd5] - msr SPMEVCNTR14_EL0, x1 -// CHECK: msr SPMEVCNTR14_EL0, x1 // encoding: [0xc1,0xe1,0x13,0xd5] - mrs x3, SPMEVCNTR15_EL0 -// CHECK: mrs x3, SPMEVCNTR15_EL0 // encoding: [0xe3,0xe1,0x33,0xd5] - msr SPMEVCNTR15_EL0, x1 -// CHECK: msr SPMEVCNTR15_EL0, x1 // encoding: [0xe1,0xe1,0x13,0xd5] - - mrs x3, SPMEVFILT2R0_EL0 -// CHECK: mrs x3, SPMEVFILT2R0_EL0 // encoding: [0x03,0xe6,0x33,0xd5] - msr SPMEVFILT2R0_EL0, x1 -// CHECK: msr SPMEVFILT2R0_EL0, x1 // encoding: [0x01,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R1_EL0 -// CHECK: mrs x3, SPMEVFILT2R1_EL0 // encoding: [0x23,0xe6,0x33,0xd5] - msr SPMEVFILT2R1_EL0, x1 -// CHECK: msr SPMEVFILT2R1_EL0, x1 // encoding: [0x21,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R2_EL0 -// CHECK: mrs x3, SPMEVFILT2R2_EL0 // encoding: [0x43,0xe6,0x33,0xd5] - msr SPMEVFILT2R2_EL0, x1 -// CHECK: msr SPMEVFILT2R2_EL0, x1 // encoding: [0x41,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R3_EL0 -// CHECK: mrs x3, SPMEVFILT2R3_EL0 // encoding: [0x63,0xe6,0x33,0xd5] - msr SPMEVFILT2R3_EL0, x1 -// CHECK: msr SPMEVFILT2R3_EL0, x1 // encoding: [0x61,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R4_EL0 -// CHECK: mrs x3, SPMEVFILT2R4_EL0 // encoding: [0x83,0xe6,0x33,0xd5] - msr SPMEVFILT2R4_EL0, x1 -// CHECK: msr SPMEVFILT2R4_EL0, x1 // encoding: [0x81,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R5_EL0 -// CHECK: mrs x3, SPMEVFILT2R5_EL0 // encoding: [0xa3,0xe6,0x33,0xd5] - msr SPMEVFILT2R5_EL0, x1 -// CHECK: msr SPMEVFILT2R5_EL0, x1 // encoding: [0xa1,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R6_EL0 -// CHECK: mrs x3, SPMEVFILT2R6_EL0 // encoding: [0xc3,0xe6,0x33,0xd5] - msr SPMEVFILT2R6_EL0, x1 -// CHECK: msr SPMEVFILT2R6_EL0, x1 // encoding: [0xc1,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R7_EL0 -// CHECK: mrs x3, SPMEVFILT2R7_EL0 // encoding: [0xe3,0xe6,0x33,0xd5] - msr SPMEVFILT2R7_EL0, x1 -// CHECK: msr SPMEVFILT2R7_EL0, x1 // encoding: [0xe1,0xe6,0x13,0xd5] - mrs x3, SPMEVFILT2R8_EL0 -// CHECK: mrs x3, SPMEVFILT2R8_EL0 // encoding: [0x03,0xe7,0x33,0xd5] - msr SPMEVFILT2R8_EL0, x1 -// CHECK: msr SPMEVFILT2R8_EL0, x1 // encoding: [0x01,0xe7,0x13,0xd5] - mrs x3, SPMEVFILT2R9_EL0 -// CHECK: mrs x3, SPMEVFILT2R9_EL0 // encoding: [0x23,0xe7,0x33,0xd5] - msr SPMEVFILT2R9_EL0, x1 -// CHECK: msr SPMEVFILT2R9_EL0, x1 // encoding: [0x21,0xe7,0x13,0xd5] - mrs x3, SPMEVFILT2R10_EL0 -// CHECK: mrs x3, SPMEVFILT2R10_EL0 // encoding: [0x43,0xe7,0x33,0xd5] - msr SPMEVFILT2R10_EL0, x1 -// CHECK: msr SPMEVFILT2R10_EL0, x1 // encoding: [0x41,0xe7,0x13,0xd5] - mrs x3, SPMEVFILT2R11_EL0 -// CHECK: mrs x3, SPMEVFILT2R11_EL0 // encoding: [0x63,0xe7,0x33,0xd5] - msr SPMEVFILT2R11_EL0, x1 -// CHECK: msr SPMEVFILT2R11_EL0, x1 // encoding: [0x61,0xe7,0x13,0xd5] - mrs x3, SPMEVFILT2R12_EL0 -// CHECK: mrs x3, SPMEVFILT2R12_EL0 // encoding: [0x83,0xe7,0x33,0xd5] - msr SPMEVFILT2R12_EL0, x1 -// CHECK: msr SPMEVFILT2R12_EL0, x1 // encoding: [0x81,0xe7,0x13,0xd5] - mrs x3, SPMEVFILT2R13_EL0 -// CHECK: mrs x3, SPMEVFILT2R13_EL0 // encoding: [0xa3,0xe7,0x33,0xd5] - msr SPMEVFILT2R13_EL0, x1 -// CHECK: msr SPMEVFILT2R13_EL0, x1 // encoding: [0xa1,0xe7,0x13,0xd5] - mrs x3, SPMEVFILT2R14_EL0 -// CHECK: mrs x3, SPMEVFILT2R14_EL0 // encoding: [0xc3,0xe7,0x33,0xd5] - msr SPMEVFILT2R14_EL0, x1 -// CHECK: msr SPMEVFILT2R14_EL0, x1 // encoding: [0xc1,0xe7,0x13,0xd5] - mrs x3, SPMEVFILT2R15_EL0 -// CHECK: mrs x3, SPMEVFILT2R15_EL0 // encoding: [0xe3,0xe7,0x33,0xd5] - msr SPMEVFILT2R15_EL0, x1 -// CHECK: msr SPMEVFILT2R15_EL0, x1 // encoding: [0xe1,0xe7,0x13,0xd5] - - mrs x3, SPMEVFILTR0_EL0 -// CHECK: mrs x3, SPMEVFILTR0_EL0 // encoding: [0x03,0xe4,0x33,0xd5] - msr SPMEVFILTR0_EL0, x1 -// CHECK: msr SPMEVFILTR0_EL0, x1 // encoding: [0x01,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR1_EL0 -// CHECK: mrs x3, SPMEVFILTR1_EL0 // encoding: [0x23,0xe4,0x33,0xd5] - msr SPMEVFILTR1_EL0, x1 -// CHECK: msr SPMEVFILTR1_EL0, x1 // encoding: [0x21,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR2_EL0 -// CHECK: mrs x3, SPMEVFILTR2_EL0 // encoding: [0x43,0xe4,0x33,0xd5] - msr SPMEVFILTR2_EL0, x1 -// CHECK: msr SPMEVFILTR2_EL0, x1 // encoding: [0x41,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR3_EL0 -// CHECK: mrs x3, SPMEVFILTR3_EL0 // encoding: [0x63,0xe4,0x33,0xd5] - msr SPMEVFILTR3_EL0, x1 -// CHECK: msr SPMEVFILTR3_EL0, x1 // encoding: [0x61,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR4_EL0 -// CHECK: mrs x3, SPMEVFILTR4_EL0 // encoding: [0x83,0xe4,0x33,0xd5] - msr SPMEVFILTR4_EL0, x1 -// CHECK: msr SPMEVFILTR4_EL0, x1 // encoding: [0x81,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR5_EL0 -// CHECK: mrs x3, SPMEVFILTR5_EL0 // encoding: [0xa3,0xe4,0x33,0xd5] - msr SPMEVFILTR5_EL0, x1 -// CHECK: msr SPMEVFILTR5_EL0, x1 // encoding: [0xa1,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR6_EL0 -// CHECK: mrs x3, SPMEVFILTR6_EL0 // encoding: [0xc3,0xe4,0x33,0xd5] - msr SPMEVFILTR6_EL0, x1 -// CHECK: msr SPMEVFILTR6_EL0, x1 // encoding: [0xc1,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR7_EL0 -// CHECK: mrs x3, SPMEVFILTR7_EL0 // encoding: [0xe3,0xe4,0x33,0xd5] - msr SPMEVFILTR7_EL0, x1 -// CHECK: msr SPMEVFILTR7_EL0, x1 // encoding: [0xe1,0xe4,0x13,0xd5] - mrs x3, SPMEVFILTR8_EL0 -// CHECK: mrs x3, SPMEVFILTR8_EL0 // encoding: [0x03,0xe5,0x33,0xd5] - msr SPMEVFILTR8_EL0, x1 -// CHECK: msr SPMEVFILTR8_EL0, x1 // encoding: [0x01,0xe5,0x13,0xd5] - mrs x3, SPMEVFILTR9_EL0 -// CHECK: mrs x3, SPMEVFILTR9_EL0 // encoding: [0x23,0xe5,0x33,0xd5] - msr SPMEVFILTR9_EL0, x1 -// CHECK: msr SPMEVFILTR9_EL0, x1 // encoding: [0x21,0xe5,0x13,0xd5] - mrs x3, SPMEVFILTR10_EL0 -// CHECK: mrs x3, SPMEVFILTR10_EL0 // encoding: [0x43,0xe5,0x33,0xd5] - msr SPMEVFILTR10_EL0, x1 -// CHECK: msr SPMEVFILTR10_EL0, x1 // encoding: [0x41,0xe5,0x13,0xd5] - mrs x3, SPMEVFILTR11_EL0 -// CHECK: mrs x3, SPMEVFILTR11_EL0 // encoding: [0x63,0xe5,0x33,0xd5] - msr SPMEVFILTR11_EL0, x1 -// CHECK: msr SPMEVFILTR11_EL0, x1 // encoding: [0x61,0xe5,0x13,0xd5] - mrs x3, SPMEVFILTR12_EL0 -// CHECK: mrs x3, SPMEVFILTR12_EL0 // encoding: [0x83,0xe5,0x33,0xd5] - msr SPMEVFILTR12_EL0, x1 -// CHECK: msr SPMEVFILTR12_EL0, x1 // encoding: [0x81,0xe5,0x13,0xd5] - mrs x3, SPMEVFILTR13_EL0 -// CHECK: mrs x3, SPMEVFILTR13_EL0 // encoding: [0xa3,0xe5,0x33,0xd5] - msr SPMEVFILTR13_EL0, x1 -// CHECK: msr SPMEVFILTR13_EL0, x1 // encoding: [0xa1,0xe5,0x13,0xd5] - mrs x3, SPMEVFILTR14_EL0 -// CHECK: mrs x3, SPMEVFILTR14_EL0 // encoding: [0xc3,0xe5,0x33,0xd5] - msr SPMEVFILTR14_EL0, x1 -// CHECK: msr SPMEVFILTR14_EL0, x1 // encoding: [0xc1,0xe5,0x13,0xd5] - mrs x3, SPMEVFILTR15_EL0 -// CHECK: mrs x3, SPMEVFILTR15_EL0 // encoding: [0xe3,0xe5,0x33,0xd5] - msr SPMEVFILTR15_EL0, x1 -// CHECK: msr SPMEVFILTR15_EL0, x1 // encoding: [0xe1,0xe5,0x13,0xd5] - - mrs x3, SPMEVTYPER0_EL0 -// CHECK: mrs x3, SPMEVTYPER0_EL0 // encoding: [0x03,0xe2,0x33,0xd5] - msr SPMEVTYPER0_EL0, x1 -// CHECK: msr SPMEVTYPER0_EL0, x1 // encoding: [0x01,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER1_EL0 -// CHECK: mrs x3, SPMEVTYPER1_EL0 // encoding: [0x23,0xe2,0x33,0xd5] - msr SPMEVTYPER1_EL0, x1 -// CHECK: msr SPMEVTYPER1_EL0, x1 // encoding: [0x21,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER2_EL0 -// CHECK: mrs x3, SPMEVTYPER2_EL0 // encoding: [0x43,0xe2,0x33,0xd5] - msr SPMEVTYPER2_EL0, x1 -// CHECK: msr SPMEVTYPER2_EL0, x1 // encoding: [0x41,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER3_EL0 -// CHECK: mrs x3, SPMEVTYPER3_EL0 // encoding: [0x63,0xe2,0x33,0xd5] - msr SPMEVTYPER3_EL0, x1 -// CHECK: msr SPMEVTYPER3_EL0, x1 // encoding: [0x61,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER4_EL0 -// CHECK: mrs x3, SPMEVTYPER4_EL0 // encoding: [0x83,0xe2,0x33,0xd5] - msr SPMEVTYPER4_EL0, x1 -// CHECK: msr SPMEVTYPER4_EL0, x1 // encoding: [0x81,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER5_EL0 -// CHECK: mrs x3, SPMEVTYPER5_EL0 // encoding: [0xa3,0xe2,0x33,0xd5] - msr SPMEVTYPER5_EL0, x1 -// CHECK: msr SPMEVTYPER5_EL0, x1 // encoding: [0xa1,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER6_EL0 -// CHECK: mrs x3, SPMEVTYPER6_EL0 // encoding: [0xc3,0xe2,0x33,0xd5] - msr SPMEVTYPER6_EL0, x1 -// CHECK: msr SPMEVTYPER6_EL0, x1 // encoding: [0xc1,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER7_EL0 -// CHECK: mrs x3, SPMEVTYPER7_EL0 // encoding: [0xe3,0xe2,0x33,0xd5] - msr SPMEVTYPER7_EL0, x1 -// CHECK: msr SPMEVTYPER7_EL0, x1 // encoding: [0xe1,0xe2,0x13,0xd5] - mrs x3, SPMEVTYPER8_EL0 -// CHECK: mrs x3, SPMEVTYPER8_EL0 // encoding: [0x03,0xe3,0x33,0xd5] - msr SPMEVTYPER8_EL0, x1 -// CHECK: msr SPMEVTYPER8_EL0, x1 // encoding: [0x01,0xe3,0x13,0xd5] - mrs x3, SPMEVTYPER9_EL0 -// CHECK: mrs x3, SPMEVTYPER9_EL0 // encoding: [0x23,0xe3,0x33,0xd5] - msr SPMEVTYPER9_EL0, x1 -// CHECK: msr SPMEVTYPER9_EL0, x1 // encoding: [0x21,0xe3,0x13,0xd5] - mrs x3, SPMEVTYPER10_EL0 -// CHECK: mrs x3, SPMEVTYPER10_EL0 // encoding: [0x43,0xe3,0x33,0xd5] - msr SPMEVTYPER10_EL0, x1 -// CHECK: msr SPMEVTYPER10_EL0, x1 // encoding: [0x41,0xe3,0x13,0xd5] - mrs x3, SPMEVTYPER11_EL0 -// CHECK: mrs x3, SPMEVTYPER11_EL0 // encoding: [0x63,0xe3,0x33,0xd5] - msr SPMEVTYPER11_EL0, x1 -// CHECK: msr SPMEVTYPER11_EL0, x1 // encoding: [0x61,0xe3,0x13,0xd5] - mrs x3, SPMEVTYPER12_EL0 -// CHECK: mrs x3, SPMEVTYPER12_EL0 // encoding: [0x83,0xe3,0x33,0xd5] - msr SPMEVTYPER12_EL0, x1 -// CHECK: msr SPMEVTYPER12_EL0, x1 // encoding: [0x81,0xe3,0x13,0xd5] - mrs x3, SPMEVTYPER13_EL0 -// CHECK: mrs x3, SPMEVTYPER13_EL0 // encoding: [0xa3,0xe3,0x33,0xd5] - msr SPMEVTYPER13_EL0, x1 -// CHECK: msr SPMEVTYPER13_EL0, x1 // encoding: [0xa1,0xe3,0x13,0xd5] - mrs x3, SPMEVTYPER14_EL0 -// CHECK: mrs x3, SPMEVTYPER14_EL0 // encoding: [0xc3,0xe3,0x33,0xd5] - msr SPMEVTYPER14_EL0, x1 -// CHECK: msr SPMEVTYPER14_EL0, x1 // encoding: [0xc1,0xe3,0x13,0xd5] - mrs x3, SPMEVTYPER15_EL0 -// CHECK: mrs x3, SPMEVTYPER15_EL0 // encoding: [0xe3,0xe3,0x33,0xd5] - msr SPMEVTYPER15_EL0, x1 -// CHECK: msr SPMEVTYPER15_EL0, x1 // encoding: [0xe1,0xe3,0x13,0xd5] - - mrs x3, SPMIIDR_EL1 -// CHECK: mrs x3, SPMIIDR_EL1 // encoding: [0x83,0x9d,0x30,0xd5] - mrs x3, SPMINTENCLR_EL1 -// CHECK: mrs x3, SPMINTENCLR_EL1 // encoding: [0x43,0x9e,0x30,0xd5] - msr SPMINTENCLR_EL1, x1 -// CHECK: msr SPMINTENCLR_EL1, x1 // encoding: [0x41,0x9e,0x10,0xd5] - mrs x3, SPMINTENSET_EL1 -// CHECK: mrs x3, SPMINTENSET_EL1 // encoding: [0x23,0x9e,0x30,0xd5] - msr SPMINTENSET_EL1, x1 -// CHECK: msr SPMINTENSET_EL1, x1 // encoding: [0x21,0x9e,0x10,0xd5] - mrs x3, SPMOVSCLR_EL0 -// CHECK: mrs x3, SPMOVSCLR_EL0 // encoding: [0x63,0x9c,0x33,0xd5] - msr SPMOVSCLR_EL0, x1 -// CHECK: msr SPMOVSCLR_EL0, x1 // encoding: [0x61,0x9c,0x13,0xd5] - mrs x3, SPMOVSSET_EL0 -// CHECK: mrs x3, SPMOVSSET_EL0 // encoding: [0x63,0x9e,0x33,0xd5] - msr SPMOVSSET_EL0, x1 -// CHECK: msr SPMOVSSET_EL0, x1 // encoding: [0x61,0x9e,0x13,0xd5] - mrs x3, SPMSELR_EL0 -// CHECK: mrs x3, SPMSELR_EL0 // encoding: [0xa3,0x9c,0x33,0xd5] - msr SPMSELR_EL0, x1 -// CHECK: msr SPMSELR_EL0, x1 // encoding: [0xa1,0x9c,0x13,0xd5] - mrs x3, SPMCGCR0_EL1 -// CHECK: mrs x3, SPMCGCR0_EL1 // encoding: [0x03,0x9d,0x30,0xd5] - mrs x3, SPMCGCR1_EL1 -// CHECK: mrs x3, SPMCGCR1_EL1 // encoding: [0x23,0x9d,0x30,0xd5] - mrs x3, SPMCFGR_EL1 -// CHECK: mrs x3, SPMCFGR_EL1 // encoding: [0xe3,0x9d,0x30,0xd5] - mrs x3, SPMROOTCR_EL3 -// CHECK: mrs x3, SPMROOTCR_EL3 // encoding: [0xe3,0x9e,0x36,0xd5] - msr SPMROOTCR_EL3, x3 -// CHECK: msr SPMROOTCR_EL3, x3 // encoding: [0xe3,0x9e,0x16,0xd5] - mrs x3, SPMSCR_EL1 -// CHECK: mrs x3, SPMSCR_EL1 // encoding: [0xe3,0x9e,0x37,0xd5] - msr SPMSCR_EL1, x3 -// CHECK: msr SPMSCR_EL1, x3 // encoding: [0xe3,0x9e,0x17,0xd5] +mrs x3, SPMACCESSR_EL1 +// CHECK-INST: mrs x3, SPMACCESSR_EL1 +// CHECK-ENCODING: encoding: [0x63,0x9d,0x30,0xd5] +// CHECK-UNKNOWN: d5309d63 mrs x3, SPMACCESSR_EL1 + +msr SPMACCESSR_EL1, x1 +// CHECK-INST: msr SPMACCESSR_EL1, x1 +// CHECK-ENCODING: encoding: [0x61,0x9d,0x10,0xd5] +// CHECK-UNKNOWN: d5109d61 msr SPMACCESSR_EL1, x1 + +mrs x3, SPMACCESSR_EL12 +// CHECK-INST: mrs x3, SPMACCESSR_EL12 +// CHECK-ENCODING: encoding: [0x63,0x9d,0x35,0xd5] +// CHECK-UNKNOWN: d5359d63 mrs x3, SPMACCESSR_EL12 + +msr SPMACCESSR_EL12, x1 +// CHECK-INST: msr SPMACCESSR_EL12, x1 +// CHECK-ENCODING: encoding: [0x61,0x9d,0x15,0xd5] +// CHECK-UNKNOWN: d5159d61 msr SPMACCESSR_EL12, x1 + +mrs x3, SPMACCESSR_EL2 +// CHECK-INST: mrs x3, SPMACCESSR_EL2 +// CHECK-ENCODING: encoding: [0x63,0x9d,0x34,0xd5] +// CHECK-UNKNOWN: d5349d63 mrs x3, SPMACCESSR_EL2 + +msr SPMACCESSR_EL2, x1 +// CHECK-INST: msr SPMACCESSR_EL2, x1 +// CHECK-ENCODING: encoding: [0x61,0x9d,0x14,0xd5] +// CHECK-UNKNOWN: d5149d61 msr SPMACCESSR_EL2, x1 + +mrs x3, SPMACCESSR_EL3 +// CHECK-INST: mrs x3, SPMACCESSR_EL3 +// CHECK-ENCODING: encoding: [0x63,0x9d,0x36,0xd5] +// CHECK-UNKNOWN: d5369d63 mrs x3, SPMACCESSR_EL3 + +msr SPMACCESSR_EL3, x1 +// CHECK-INST: msr SPMACCESSR_EL3, x1 +// CHECK-ENCODING: encoding: [0x61,0x9d,0x16,0xd5] +// CHECK-UNKNOWN: d5169d61 msr SPMACCESSR_EL3, x1 + +mrs x3, SPMCNTENCLR_EL0 +// CHECK-INST: mrs x3, SPMCNTENCLR_EL0 +// CHECK-ENCODING: encoding: [0x43,0x9c,0x33,0xd5] +// CHECK-UNKNOWN: d5339c43 mrs x3, SPMCNTENCLR_EL0 + +msr SPMCNTENCLR_EL0, x1 +// CHECK-INST: msr SPMCNTENCLR_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0x9c,0x13,0xd5] +// CHECK-UNKNOWN: d5139c41 msr SPMCNTENCLR_EL0, x1 + +mrs x3, SPMCNTENSET_EL0 +// CHECK-INST: mrs x3, SPMCNTENSET_EL0 +// CHECK-ENCODING: encoding: [0x23,0x9c,0x33,0xd5] +// CHECK-UNKNOWN: d5339c23 mrs x3, SPMCNTENSET_EL0 + +msr SPMCNTENSET_EL0, x1 +// CHECK-INST: msr SPMCNTENSET_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0x9c,0x13,0xd5] +// CHECK-UNKNOWN: d5139c21 msr SPMCNTENSET_EL0, x1 + +mrs x3, SPMCR_EL0 +// CHECK-INST: mrs x3, SPMCR_EL0 +// CHECK-ENCODING: encoding: [0x03,0x9c,0x33,0xd5] +// CHECK-UNKNOWN: d5339c03 mrs x3, SPMCR_EL0 + +msr SPMCR_EL0, x1 +// CHECK-INST: msr SPMCR_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0x9c,0x13,0xd5] +// CHECK-UNKNOWN: d5139c01 msr SPMCR_EL0, x1 + +mrs x3, SPMDEVAFF_EL1 +// CHECK-INST: mrs x3, SPMDEVAFF_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x9d,0x30,0xd5] +// CHECK-UNKNOWN: d5309dc3 mrs x3, SPMDEVAFF_EL1 + +mrs x3, SPMDEVARCH_EL1 +// CHECK-INST: mrs x3, SPMDEVARCH_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x9d,0x30,0xd5] +// CHECK-UNKNOWN: d5309da3 mrs x3, SPMDEVARCH_EL1 + +mrs x3, SPMEVCNTR0_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR0_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e003 mrs x3, SPMEVCNTR0_EL0 + +msr SPMEVCNTR0_EL0, x1 +// CHECK-INST: msr SPMEVCNTR0_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e001 msr SPMEVCNTR0_EL0, x1 + +mrs x3, SPMEVCNTR1_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR1_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e023 mrs x3, SPMEVCNTR1_EL0 + +msr SPMEVCNTR1_EL0, x1 +// CHECK-INST: msr SPMEVCNTR1_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e021 msr SPMEVCNTR1_EL0, x1 + +mrs x3, SPMEVCNTR2_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR2_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e043 mrs x3, SPMEVCNTR2_EL0 + +msr SPMEVCNTR2_EL0, x1 +// CHECK-INST: msr SPMEVCNTR2_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e041 msr SPMEVCNTR2_EL0, x1 + +mrs x3, SPMEVCNTR3_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR3_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e063 mrs x3, SPMEVCNTR3_EL0 + +msr SPMEVCNTR3_EL0, x1 +// CHECK-INST: msr SPMEVCNTR3_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e061 msr SPMEVCNTR3_EL0, x1 + +mrs x3, SPMEVCNTR4_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR4_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e083 mrs x3, SPMEVCNTR4_EL0 + +msr SPMEVCNTR4_EL0, x1 +// CHECK-INST: msr SPMEVCNTR4_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e081 msr SPMEVCNTR4_EL0, x1 + +mrs x3, SPMEVCNTR5_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR5_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e0a3 mrs x3, SPMEVCNTR5_EL0 + +msr SPMEVCNTR5_EL0, x1 +// CHECK-INST: msr SPMEVCNTR5_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e0a1 msr SPMEVCNTR5_EL0, x1 + +mrs x3, SPMEVCNTR6_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR6_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e0c3 mrs x3, SPMEVCNTR6_EL0 + +msr SPMEVCNTR6_EL0, x1 +// CHECK-INST: msr SPMEVCNTR6_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e0c1 msr SPMEVCNTR6_EL0, x1 + +mrs x3, SPMEVCNTR7_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR7_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe0,0x33,0xd5] +// CHECK-UNKNOWN: d533e0e3 mrs x3, SPMEVCNTR7_EL0 + +msr SPMEVCNTR7_EL0, x1 +// CHECK-INST: msr SPMEVCNTR7_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe0,0x13,0xd5] +// CHECK-UNKNOWN: d513e0e1 msr SPMEVCNTR7_EL0, x1 + +mrs x3, SPMEVCNTR8_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR8_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e103 mrs x3, SPMEVCNTR8_EL0 + +msr SPMEVCNTR8_EL0, x1 +// CHECK-INST: msr SPMEVCNTR8_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e101 msr SPMEVCNTR8_EL0, x1 + +mrs x3, SPMEVCNTR9_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR9_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e123 mrs x3, SPMEVCNTR9_EL0 + +msr SPMEVCNTR9_EL0, x1 +// CHECK-INST: msr SPMEVCNTR9_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e121 msr SPMEVCNTR9_EL0, x1 + +mrs x3, SPMEVCNTR10_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR10_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e143 mrs x3, SPMEVCNTR10_EL0 + +msr SPMEVCNTR10_EL0, x1 +// CHECK-INST: msr SPMEVCNTR10_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e141 msr SPMEVCNTR10_EL0, x1 + +mrs x3, SPMEVCNTR11_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR11_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e163 mrs x3, SPMEVCNTR11_EL0 + +msr SPMEVCNTR11_EL0, x1 +// CHECK-INST: msr SPMEVCNTR11_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e161 msr SPMEVCNTR11_EL0, x1 + +mrs x3, SPMEVCNTR12_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR12_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e183 mrs x3, SPMEVCNTR12_EL0 + +msr SPMEVCNTR12_EL0, x1 +// CHECK-INST: msr SPMEVCNTR12_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e181 msr SPMEVCNTR12_EL0, x1 + +mrs x3, SPMEVCNTR13_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR13_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e1a3 mrs x3, SPMEVCNTR13_EL0 + +msr SPMEVCNTR13_EL0, x1 +// CHECK-INST: msr SPMEVCNTR13_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e1a1 msr SPMEVCNTR13_EL0, x1 + +mrs x3, SPMEVCNTR14_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR14_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e1c3 mrs x3, SPMEVCNTR14_EL0 + +msr SPMEVCNTR14_EL0, x1 +// CHECK-INST: msr SPMEVCNTR14_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e1c1 msr SPMEVCNTR14_EL0, x1 + +mrs x3, SPMEVCNTR15_EL0 +// CHECK-INST: mrs x3, SPMEVCNTR15_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe1,0x33,0xd5] +// CHECK-UNKNOWN: d533e1e3 mrs x3, SPMEVCNTR15_EL0 + +msr SPMEVCNTR15_EL0, x1 +// CHECK-INST: msr SPMEVCNTR15_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe1,0x13,0xd5] +// CHECK-UNKNOWN: d513e1e1 msr SPMEVCNTR15_EL0, x1 + +mrs x3, SPMEVFILT2R0_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R0_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e603 mrs x3, SPMEVFILT2R0_EL0 + +msr SPMEVFILT2R0_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R0_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e601 msr SPMEVFILT2R0_EL0, x1 + +mrs x3, SPMEVFILT2R1_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R1_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e623 mrs x3, SPMEVFILT2R1_EL0 + +msr SPMEVFILT2R1_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R1_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e621 msr SPMEVFILT2R1_EL0, x1 + +mrs x3, SPMEVFILT2R2_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R2_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e643 mrs x3, SPMEVFILT2R2_EL0 + +msr SPMEVFILT2R2_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R2_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e641 msr SPMEVFILT2R2_EL0, x1 + +mrs x3, SPMEVFILT2R3_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R3_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e663 mrs x3, SPMEVFILT2R3_EL0 + +msr SPMEVFILT2R3_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R3_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e661 msr SPMEVFILT2R3_EL0, x1 + +mrs x3, SPMEVFILT2R4_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R4_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e683 mrs x3, SPMEVFILT2R4_EL0 + +msr SPMEVFILT2R4_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R4_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e681 msr SPMEVFILT2R4_EL0, x1 + +mrs x3, SPMEVFILT2R5_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R5_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e6a3 mrs x3, SPMEVFILT2R5_EL0 + +msr SPMEVFILT2R5_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R5_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e6a1 msr SPMEVFILT2R5_EL0, x1 + +mrs x3, SPMEVFILT2R6_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R6_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e6c3 mrs x3, SPMEVFILT2R6_EL0 + +msr SPMEVFILT2R6_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R6_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e6c1 msr SPMEVFILT2R6_EL0, x1 + +mrs x3, SPMEVFILT2R7_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R7_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe6,0x33,0xd5] +// CHECK-UNKNOWN: d533e6e3 mrs x3, SPMEVFILT2R7_EL0 + +msr SPMEVFILT2R7_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R7_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe6,0x13,0xd5] +// CHECK-UNKNOWN: d513e6e1 msr SPMEVFILT2R7_EL0, x1 + +mrs x3, SPMEVFILT2R8_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R8_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e703 mrs x3, SPMEVFILT2R8_EL0 + +msr SPMEVFILT2R8_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R8_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e701 msr SPMEVFILT2R8_EL0, x1 + +mrs x3, SPMEVFILT2R9_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R9_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e723 mrs x3, SPMEVFILT2R9_EL0 + +msr SPMEVFILT2R9_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R9_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e721 msr SPMEVFILT2R9_EL0, x1 + +mrs x3, SPMEVFILT2R10_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R10_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e743 mrs x3, SPMEVFILT2R10_EL0 + +msr SPMEVFILT2R10_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R10_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e741 msr SPMEVFILT2R10_EL0, x1 + +mrs x3, SPMEVFILT2R11_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R11_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e763 mrs x3, SPMEVFILT2R11_EL0 + +msr SPMEVFILT2R11_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R11_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e761 msr SPMEVFILT2R11_EL0, x1 + +mrs x3, SPMEVFILT2R12_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R12_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e783 mrs x3, SPMEVFILT2R12_EL0 + +msr SPMEVFILT2R12_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R12_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e781 msr SPMEVFILT2R12_EL0, x1 + +mrs x3, SPMEVFILT2R13_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R13_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e7a3 mrs x3, SPMEVFILT2R13_EL0 + +msr SPMEVFILT2R13_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R13_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e7a1 msr SPMEVFILT2R13_EL0, x1 + +mrs x3, SPMEVFILT2R14_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R14_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e7c3 mrs x3, SPMEVFILT2R14_EL0 + +msr SPMEVFILT2R14_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R14_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e7c1 msr SPMEVFILT2R14_EL0, x1 + +mrs x3, SPMEVFILT2R15_EL0 +// CHECK-INST: mrs x3, SPMEVFILT2R15_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe7,0x33,0xd5] +// CHECK-UNKNOWN: d533e7e3 mrs x3, SPMEVFILT2R15_EL0 + +msr SPMEVFILT2R15_EL0, x1 +// CHECK-INST: msr SPMEVFILT2R15_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe7,0x13,0xd5] +// CHECK-UNKNOWN: d513e7e1 msr SPMEVFILT2R15_EL0, x1 + +mrs x3, SPMEVFILTR0_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR0_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e403 mrs x3, SPMEVFILTR0_EL0 + +msr SPMEVFILTR0_EL0, x1 +// CHECK-INST: msr SPMEVFILTR0_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e401 msr SPMEVFILTR0_EL0, x1 + +mrs x3, SPMEVFILTR1_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR1_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e423 mrs x3, SPMEVFILTR1_EL0 + +msr SPMEVFILTR1_EL0, x1 +// CHECK-INST: msr SPMEVFILTR1_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e421 msr SPMEVFILTR1_EL0, x1 + +mrs x3, SPMEVFILTR2_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR2_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e443 mrs x3, SPMEVFILTR2_EL0 + +msr SPMEVFILTR2_EL0, x1 +// CHECK-INST: msr SPMEVFILTR2_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e441 msr SPMEVFILTR2_EL0, x1 + +mrs x3, SPMEVFILTR3_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR3_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e463 mrs x3, SPMEVFILTR3_EL0 + +msr SPMEVFILTR3_EL0, x1 +// CHECK-INST: msr SPMEVFILTR3_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e461 msr SPMEVFILTR3_EL0, x1 + +mrs x3, SPMEVFILTR4_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR4_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e483 mrs x3, SPMEVFILTR4_EL0 + +msr SPMEVFILTR4_EL0, x1 +// CHECK-INST: msr SPMEVFILTR4_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e481 msr SPMEVFILTR4_EL0, x1 + +mrs x3, SPMEVFILTR5_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR5_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e4a3 mrs x3, SPMEVFILTR5_EL0 + +msr SPMEVFILTR5_EL0, x1 +// CHECK-INST: msr SPMEVFILTR5_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e4a1 msr SPMEVFILTR5_EL0, x1 + +mrs x3, SPMEVFILTR6_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR6_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e4c3 mrs x3, SPMEVFILTR6_EL0 + +msr SPMEVFILTR6_EL0, x1 +// CHECK-INST: msr SPMEVFILTR6_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e4c1 msr SPMEVFILTR6_EL0, x1 + +mrs x3, SPMEVFILTR7_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR7_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe4,0x33,0xd5] +// CHECK-UNKNOWN: d533e4e3 mrs x3, SPMEVFILTR7_EL0 + +msr SPMEVFILTR7_EL0, x1 +// CHECK-INST: msr SPMEVFILTR7_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe4,0x13,0xd5] +// CHECK-UNKNOWN: d513e4e1 msr SPMEVFILTR7_EL0, x1 + +mrs x3, SPMEVFILTR8_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR8_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e503 mrs x3, SPMEVFILTR8_EL0 + +msr SPMEVFILTR8_EL0, x1 +// CHECK-INST: msr SPMEVFILTR8_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e501 msr SPMEVFILTR8_EL0, x1 + +mrs x3, SPMEVFILTR9_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR9_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e523 mrs x3, SPMEVFILTR9_EL0 + +msr SPMEVFILTR9_EL0, x1 +// CHECK-INST: msr SPMEVFILTR9_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e521 msr SPMEVFILTR9_EL0, x1 + +mrs x3, SPMEVFILTR10_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR10_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e543 mrs x3, SPMEVFILTR10_EL0 + +msr SPMEVFILTR10_EL0, x1 +// CHECK-INST: msr SPMEVFILTR10_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e541 msr SPMEVFILTR10_EL0, x1 + +mrs x3, SPMEVFILTR11_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR11_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e563 mrs x3, SPMEVFILTR11_EL0 + +msr SPMEVFILTR11_EL0, x1 +// CHECK-INST: msr SPMEVFILTR11_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e561 msr SPMEVFILTR11_EL0, x1 + +mrs x3, SPMEVFILTR12_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR12_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e583 mrs x3, SPMEVFILTR12_EL0 + +msr SPMEVFILTR12_EL0, x1 +// CHECK-INST: msr SPMEVFILTR12_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e581 msr SPMEVFILTR12_EL0, x1 + +mrs x3, SPMEVFILTR13_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR13_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e5a3 mrs x3, SPMEVFILTR13_EL0 + +msr SPMEVFILTR13_EL0, x1 +// CHECK-INST: msr SPMEVFILTR13_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e5a1 msr SPMEVFILTR13_EL0, x1 + +mrs x3, SPMEVFILTR14_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR14_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e5c3 mrs x3, SPMEVFILTR14_EL0 + +msr SPMEVFILTR14_EL0, x1 +// CHECK-INST: msr SPMEVFILTR14_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e5c1 msr SPMEVFILTR14_EL0, x1 + +mrs x3, SPMEVFILTR15_EL0 +// CHECK-INST: mrs x3, SPMEVFILTR15_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe5,0x33,0xd5] +// CHECK-UNKNOWN: d533e5e3 mrs x3, SPMEVFILTR15_EL0 + +msr SPMEVFILTR15_EL0, x1 +// CHECK-INST: msr SPMEVFILTR15_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe5,0x13,0xd5] +// CHECK-UNKNOWN: d513e5e1 msr SPMEVFILTR15_EL0, x1 + +mrs x3, SPMEVTYPER0_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER0_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e203 mrs x3, SPMEVTYPER0_EL0 + +msr SPMEVTYPER0_EL0, x1 +// CHECK-INST: msr SPMEVTYPER0_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e201 msr SPMEVTYPER0_EL0, x1 + +mrs x3, SPMEVTYPER1_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER1_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e223 mrs x3, SPMEVTYPER1_EL0 + +msr SPMEVTYPER1_EL0, x1 +// CHECK-INST: msr SPMEVTYPER1_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e221 msr SPMEVTYPER1_EL0, x1 + +mrs x3, SPMEVTYPER2_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER2_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e243 mrs x3, SPMEVTYPER2_EL0 + +msr SPMEVTYPER2_EL0, x1 +// CHECK-INST: msr SPMEVTYPER2_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e241 msr SPMEVTYPER2_EL0, x1 + +mrs x3, SPMEVTYPER3_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER3_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e263 mrs x3, SPMEVTYPER3_EL0 + +msr SPMEVTYPER3_EL0, x1 +// CHECK-INST: msr SPMEVTYPER3_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e261 msr SPMEVTYPER3_EL0, x1 + +mrs x3, SPMEVTYPER4_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER4_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e283 mrs x3, SPMEVTYPER4_EL0 + +msr SPMEVTYPER4_EL0, x1 +// CHECK-INST: msr SPMEVTYPER4_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e281 msr SPMEVTYPER4_EL0, x1 + +mrs x3, SPMEVTYPER5_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER5_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e2a3 mrs x3, SPMEVTYPER5_EL0 + +msr SPMEVTYPER5_EL0, x1 +// CHECK-INST: msr SPMEVTYPER5_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e2a1 msr SPMEVTYPER5_EL0, x1 + +mrs x3, SPMEVTYPER6_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER6_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e2c3 mrs x3, SPMEVTYPER6_EL0 + +msr SPMEVTYPER6_EL0, x1 +// CHECK-INST: msr SPMEVTYPER6_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e2c1 msr SPMEVTYPER6_EL0, x1 + +mrs x3, SPMEVTYPER7_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER7_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe2,0x33,0xd5] +// CHECK-UNKNOWN: d533e2e3 mrs x3, SPMEVTYPER7_EL0 + +msr SPMEVTYPER7_EL0, x1 +// CHECK-INST: msr SPMEVTYPER7_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe2,0x13,0xd5] +// CHECK-UNKNOWN: d513e2e1 msr SPMEVTYPER7_EL0, x1 + +mrs x3, SPMEVTYPER8_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER8_EL0 +// CHECK-ENCODING: encoding: [0x03,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e303 mrs x3, SPMEVTYPER8_EL0 + +msr SPMEVTYPER8_EL0, x1 +// CHECK-INST: msr SPMEVTYPER8_EL0, x1 +// CHECK-ENCODING: encoding: [0x01,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e301 msr SPMEVTYPER8_EL0, x1 + +mrs x3, SPMEVTYPER9_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER9_EL0 +// CHECK-ENCODING: encoding: [0x23,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e323 mrs x3, SPMEVTYPER9_EL0 + +msr SPMEVTYPER9_EL0, x1 +// CHECK-INST: msr SPMEVTYPER9_EL0, x1 +// CHECK-ENCODING: encoding: [0x21,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e321 msr SPMEVTYPER9_EL0, x1 + +mrs x3, SPMEVTYPER10_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER10_EL0 +// CHECK-ENCODING: encoding: [0x43,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e343 mrs x3, SPMEVTYPER10_EL0 + +msr SPMEVTYPER10_EL0, x1 +// CHECK-INST: msr SPMEVTYPER10_EL0, x1 +// CHECK-ENCODING: encoding: [0x41,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e341 msr SPMEVTYPER10_EL0, x1 + +mrs x3, SPMEVTYPER11_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER11_EL0 +// CHECK-ENCODING: encoding: [0x63,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e363 mrs x3, SPMEVTYPER11_EL0 + +msr SPMEVTYPER11_EL0, x1 +// CHECK-INST: msr SPMEVTYPER11_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e361 msr SPMEVTYPER11_EL0, x1 + +mrs x3, SPMEVTYPER12_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER12_EL0 +// CHECK-ENCODING: encoding: [0x83,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e383 mrs x3, SPMEVTYPER12_EL0 + +msr SPMEVTYPER12_EL0, x1 +// CHECK-INST: msr SPMEVTYPER12_EL0, x1 +// CHECK-ENCODING: encoding: [0x81,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e381 msr SPMEVTYPER12_EL0, x1 + +mrs x3, SPMEVTYPER13_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER13_EL0 +// CHECK-ENCODING: encoding: [0xa3,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e3a3 mrs x3, SPMEVTYPER13_EL0 + +msr SPMEVTYPER13_EL0, x1 +// CHECK-INST: msr SPMEVTYPER13_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e3a1 msr SPMEVTYPER13_EL0, x1 + +mrs x3, SPMEVTYPER14_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER14_EL0 +// CHECK-ENCODING: encoding: [0xc3,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e3c3 mrs x3, SPMEVTYPER14_EL0 + +msr SPMEVTYPER14_EL0, x1 +// CHECK-INST: msr SPMEVTYPER14_EL0, x1 +// CHECK-ENCODING: encoding: [0xc1,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e3c1 msr SPMEVTYPER14_EL0, x1 + +mrs x3, SPMEVTYPER15_EL0 +// CHECK-INST: mrs x3, SPMEVTYPER15_EL0 +// CHECK-ENCODING: encoding: [0xe3,0xe3,0x33,0xd5] +// CHECK-UNKNOWN: d533e3e3 mrs x3, SPMEVTYPER15_EL0 + +msr SPMEVTYPER15_EL0, x1 +// CHECK-INST: msr SPMEVTYPER15_EL0, x1 +// CHECK-ENCODING: encoding: [0xe1,0xe3,0x13,0xd5] +// CHECK-UNKNOWN: d513e3e1 msr SPMEVTYPER15_EL0, x1 + +mrs x3, SPMIIDR_EL1 +// CHECK-INST: mrs x3, SPMIIDR_EL1 +// CHECK-ENCODING: encoding: [0x83,0x9d,0x30,0xd5] +// CHECK-UNKNOWN: d5309d83 mrs x3, SPMIIDR_EL1 + +mrs x3, SPMINTENCLR_EL1 +// CHECK-INST: mrs x3, SPMINTENCLR_EL1 +// CHECK-ENCODING: encoding: [0x43,0x9e,0x30,0xd5] +// CHECK-UNKNOWN: d5309e43 mrs x3, SPMINTENCLR_EL1 + +msr SPMINTENCLR_EL1, x1 +// CHECK-INST: msr SPMINTENCLR_EL1, x1 +// CHECK-ENCODING: encoding: [0x41,0x9e,0x10,0xd5] +// CHECK-UNKNOWN: d5109e41 msr SPMINTENCLR_EL1, x1 + +mrs x3, SPMINTENSET_EL1 +// CHECK-INST: mrs x3, SPMINTENSET_EL1 +// CHECK-ENCODING: encoding: [0x23,0x9e,0x30,0xd5] +// CHECK-UNKNOWN: d5309e23 mrs x3, SPMINTENSET_EL1 + +msr SPMINTENSET_EL1, x1 +// CHECK-INST: msr SPMINTENSET_EL1, x1 +// CHECK-ENCODING: encoding: [0x21,0x9e,0x10,0xd5] +// CHECK-UNKNOWN: d5109e21 msr SPMINTENSET_EL1, x1 + +mrs x3, SPMOVSCLR_EL0 +// CHECK-INST: mrs x3, SPMOVSCLR_EL0 +// CHECK-ENCODING: encoding: [0x63,0x9c,0x33,0xd5] +// CHECK-UNKNOWN: d5339c63 mrs x3, SPMOVSCLR_EL0 + +msr SPMOVSCLR_EL0, x1 +// CHECK-INST: msr SPMOVSCLR_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0x9c,0x13,0xd5] +// CHECK-UNKNOWN: d5139c61 msr SPMOVSCLR_EL0, x1 + +mrs x3, SPMOVSSET_EL0 +// CHECK-INST: mrs x3, SPMOVSSET_EL0 +// CHECK-ENCODING: encoding: [0x63,0x9e,0x33,0xd5] +// CHECK-UNKNOWN: d5339e63 mrs x3, SPMOVSSET_EL0 + +msr SPMOVSSET_EL0, x1 +// CHECK-INST: msr SPMOVSSET_EL0, x1 +// CHECK-ENCODING: encoding: [0x61,0x9e,0x13,0xd5] +// CHECK-UNKNOWN: d5139e61 msr SPMOVSSET_EL0, x1 + +mrs x3, SPMSELR_EL0 +// CHECK-INST: mrs x3, SPMSELR_EL0 +// CHECK-ENCODING: encoding: [0xa3,0x9c,0x33,0xd5] +// CHECK-UNKNOWN: d5339ca3 mrs x3, SPMSELR_EL0 + +msr SPMSELR_EL0, x1 +// CHECK-INST: msr SPMSELR_EL0, x1 +// CHECK-ENCODING: encoding: [0xa1,0x9c,0x13,0xd5] +// CHECK-UNKNOWN: d5139ca1 msr SPMSELR_EL0, x1 + +mrs x3, SPMCGCR0_EL1 +// CHECK-INST: mrs x3, SPMCGCR0_EL1 +// CHECK-ENCODING: encoding: [0x03,0x9d,0x30,0xd5] +// CHECK-UNKNOWN: d5309d03 mrs x3, SPMCGCR0_EL1 + +mrs x3, SPMCGCR1_EL1 +// CHECK-INST: mrs x3, SPMCGCR1_EL1 +// CHECK-ENCODING: encoding: [0x23,0x9d,0x30,0xd5] +// CHECK-UNKNOWN: d5309d23 mrs x3, SPMCGCR1_EL1 + +mrs x3, SPMCFGR_EL1 +// CHECK-INST: mrs x3, SPMCFGR_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x9d,0x30,0xd5] +// CHECK-UNKNOWN: d5309de3 mrs x3, SPMCFGR_EL1 + +mrs x3, SPMROOTCR_EL3 +// CHECK-INST: mrs x3, SPMROOTCR_EL3 +// CHECK-ENCODING: encoding: [0xe3,0x9e,0x36,0xd5] +// CHECK-UNKNOWN: d5369ee3 mrs x3, SPMROOTCR_EL3 + +msr SPMROOTCR_EL3, x3 +// CHECK-INST: msr SPMROOTCR_EL3, x3 +// CHECK-ENCODING: encoding: [0xe3,0x9e,0x16,0xd5] +// CHECK-UNKNOWN: d5169ee3 msr SPMROOTCR_EL3, x3 + +mrs x3, SPMSCR_EL1 +// CHECK-INST: mrs x3, SPMSCR_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x9e,0x37,0xd5] +// CHECK-UNKNOWN: d5379ee3 mrs x3, SPMSCR_EL1 + +msr SPMSCR_EL1, x3 +// CHECK-INST: msr SPMSCR_EL1, x3 +// CHECK-ENCODING: encoding: [0xe3,0x9e,0x17,0xd5] +// CHECK-UNKNOWN: d5179ee3 msr SPMSCR_EL1, x3 // FEAT_ITE - mrs x3, TRCITEEDCR -// CHECK: mrs x3, TRCITEEDCR // encoding: [0x23,0x02,0x31,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register - msr TRCITEEDCR, x3 -// CHECK: msr TRCITEEDCR, x3 // encoding: [0x23,0x02,0x11,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register - mrs x3, TRCITECR_EL1 -// CHECK: mrs x3, TRCITECR_EL1 // encoding: [0x63,0x12,0x38,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register - msr TRCITECR_EL1, x1 -// CHECK: msr TRCITECR_EL1, x1 // encoding: [0x61,0x12,0x18,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate - mrs x3, TRCITECR_EL12 -// CHECK: mrs x3, TRCITECR_EL12 // encoding: [0x63,0x12,0x3d,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register - msr TRCITECR_EL12, x1 -// CHECK: msr TRCITECR_EL12, x1 // encoding: [0x61,0x12,0x1d,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate - mrs x3, TRCITECR_EL2 -// CHECK: mrs x3, TRCITECR_EL2 // encoding: [0x63,0x12,0x3c,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register - msr TRCITECR_EL2, x1 -// CHECK: msr TRCITECR_EL2, x1 // encoding: [0x61,0x12,0x1c,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate - trcit x1 -// CHECK: trcit x1 // encoding: [0xe1,0x72,0x0b,0xd5] -// ERROR-NO-ITE: [[@LINE-2]]:13: error: instruction requires: ite +mrs x3, TRCITEEDCR +// CHECK-INST: mrs x3, TRCITEEDCR +// CHECK-ENCODING: encoding: [0x23,0x02,0x31,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d5310223 mrs x3, S2_1_C0_C2_1 + +msr TRCITEEDCR, x3 +// CHECK-INST: msr TRCITEEDCR, x3 +// CHECK-ENCODING: encoding: [0x23,0x02,0x11,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d5110223 msr S2_1_C0_C2_1, x3 + +mrs x3, TRCITECR_EL1 +// CHECK-INST: mrs x3, TRCITECR_EL1 +// CHECK-ENCODING: encoding: [0x63,0x12,0x38,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d5381263 mrs x3, S3_0_C1_C2_3 + +msr TRCITECR_EL1, x1 +// CHECK-INST: msr TRCITECR_EL1, x1 +// CHECK-ENCODING: encoding: [0x61,0x12,0x18,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d5181261 msr S3_0_C1_C2_3, x1 + +mrs x3, TRCITECR_EL12 +// CHECK-INST: mrs x3, TRCITECR_EL12 +// CHECK-ENCODING: encoding: [0x63,0x12,0x3d,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53d1263 mrs x3, S3_5_C1_C2_3 + +msr TRCITECR_EL12, x1 +// CHECK-INST: msr TRCITECR_EL12, x1 +// CHECK-ENCODING: encoding: [0x61,0x12,0x1d,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51d1261 msr S3_5_C1_C2_3, x1 + +mrs x3, TRCITECR_EL2 +// CHECK-INST: mrs x3, TRCITECR_EL2 +// CHECK-ENCODING: encoding: [0x63,0x12,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53c1263 mrs x3, S3_4_C1_C2_3 + +msr TRCITECR_EL2, x1 +// CHECK-INST: msr TRCITECR_EL2, x1 +// CHECK-ENCODING: encoding: [0x61,0x12,0x1c,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51c1261 msr S3_4_C1_C2_3, x1 + +trcit x1 +// CHECK-INST: trcit x1 +// CHECK-ENCODING: encoding: [0xe1,0x72,0x0b,0xd5] +// CHECK-ERROR: error: instruction requires: ite +// CHECK-UNKNOWN: d50b72e1 sys #3, c7, c2, #7, x1 // FEAT_SPE_FDS - mrs x3, PMSDSFR_EL1 -// CHECK: mrs x3, PMSDSFR_EL1 // encoding: [0x83,0x9a,0x38,0xd5] - msr PMSDSFR_EL1, x3 -// CHECK: msr PMSDSFR_EL1, x3 // encoding: [0x83,0x9a,0x18,0xd5] +mrs x3, PMSDSFR_EL1 +// CHECK-INST: mrs x3, PMSDSFR_EL1 +// CHECK-ENCODING: encoding: [0x83,0x9a,0x38,0xd5] +// CHECK-UNKNOWN: d5389a83 mrs x3, PMSDSFR_EL1 + +msr PMSDSFR_EL1, x3 +// CHECK-INST: msr PMSDSFR_EL1, x3 +// CHECK-ENCODING: encoding: [0x83,0x9a,0x18,0xd5] +// CHECK-UNKNOWN: d5189a83 msr PMSDSFR_EL1, x3 diff --git a/llvm/test/MC/AArch64/armv8.9a-lrcpc3.s b/llvm/test/MC/AArch64/armv8.9a-lrcpc3.s index 263f200428b6..4ccc800310f2 100644 --- a/llvm/test/MC/AArch64/armv8.9a-lrcpc3.s +++ b/llvm/test/MC/AArch64/armv8.9a-lrcpc3.s @@ -1,143 +1,282 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+rcpc3 < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+rcpc3 < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+rcpc3 < %s | FileCheck %s - -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s - - stilp w24, w0, [x16, #-8]! -// CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stilp w24, w0, [x16, -8]! -// CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stilp x25, x1, [x17, -16]! -// CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stilp x25, x1, [x17, #-16]! -// CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stilp w26, w2, [x18] -// CHECK: stilp w26, w2, [x18] // encoding: [0x5a,0x1a,0x02,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stilp w26, w2, [x18, #0] -// CHECK: stilp w26, w2, [x18] // encoding: [0x5a,0x1a,0x02,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stilp x27, x3, [sp] -// CHECK: stilp x27, x3, [sp] // encoding: [0xfb,0x1b,0x03,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stilp x27, x3, [sp, 0] -// CHECK: stilp x27, x3, [sp] // encoding: [0xfb,0x1b,0x03,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp w28, w4, [x20], #8 -// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp w28, w4, [x20, #0], #8 -// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp w28, w4, [x20], 8 -// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp w28, w4, [x20, 0], 8 -// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp x29, x5, [x21], #16 -// CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp x29, x5, [x21], 16 -// CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp w30, w6, [sp] -// CHECK: ldiapp w30, w6, [sp] // encoding: [0xfe,0x1b,0x46,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp w30, w6, [sp, #0] -// CHECK: ldiapp w30, w6, [sp] // encoding: [0xfe,0x1b,0x46,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp xzr, x7, [x23] -// CHECK: ldiapp xzr, x7, [x23] // encoding: [0xff,0x1a,0x47,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldiapp xzr, x7, [x23, 0] -// CHECK: ldiapp xzr, x7, [x23] // encoding: [0xff,0x1a,0x47,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - - stlr w3, [x15, #-4]! -// CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stlr w3, [x15, -4]! -// CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stlr x3, [x15, #-8]! -// CHECK: stlr x3, [x15, #-8]! // encoding: [0xe3,0x09,0x80,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stlr x3, [sp, -8]! -// CHECK: stlr x3, [sp, #-8]! // encoding: [0xe3,0x0b,0x80,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapr w3, [sp], #4 -// CHECK: ldapr w3, [sp], #4 // encoding: [0xe3,0x0b,0xc0,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapr w3, [x15], 4 -// CHECK: ldapr w3, [x15], #4 // encoding: [0xe3,0x09,0xc0,0x99] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapr x3, [x15], #8 -// CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapr x3, [x15], 8 -// CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - - stlur b3, [x15, #-1] -// CHECK: stlur b3, [x15, #-1] // encoding: [0xe3,0xf9,0x1f,0x1d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stlur h3, [x15, #2] -// CHECK: stlur h3, [x15, #2] // encoding: [0xe3,0x29,0x00,0x5d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stlur s3, [x15, #-3] -// CHECK: stlur s3, [x15, #-3] // encoding: [0xe3,0xd9,0x1f,0x9d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stlur d3, [sp, #4] -// CHECK: stlur d3, [sp, #4] // encoding: [0xe3,0x4b,0x00,0xdd] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stlur q3, [x15, #-5] -// CHECK: stlur q3, [x15, #-5] // encoding: [0xe3,0xb9,0x9f,0x1d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapur b3, [x15, #6] -// CHECK: ldapur b3, [x15, #6] // encoding: [0xe3,0x69,0x40,0x1d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapur h3, [x15, #-7] -// CHECK: ldapur h3, [x15, #-7] // encoding: [0xe3,0x99,0x5f,0x5d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapur s3, [x15, #8] -// CHECK: ldapur s3, [x15, #8] // encoding: [0xe3,0x89,0x40,0x9d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapur d3, [x15, #-9] -// CHECK: ldapur d3, [x15, #-9] // encoding: [0xe3,0x79,0x5f,0xdd] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldapur q3, [sp, #10] -// CHECK: ldapur q3, [sp, #10] // encoding: [0xe3,0xab,0xc0,0x1d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - - stl1 { v3.d }[0], [x15] -// CHECK: stl1 { v3.d }[0], [x15] // encoding: [0xe3,0x85,0x01,0x0d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stl1 { v3.d }[0], [x15, #0] -// CHECK: stl1 { v3.d }[0], [x15] // encoding: [0xe3,0x85,0x01,0x0d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stl1 { v3.d }[1], [sp] -// CHECK: stl1 { v3.d }[1], [sp] // encoding: [0xe3,0x87,0x01,0x4d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - stl1 { v3.d }[1], [sp, 0] -// CHECK: stl1 { v3.d }[1], [sp] // encoding: [0xe3,0x87,0x01,0x4d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldap1 { v3.d }[0], [sp] -// CHECK: ldap1 { v3.d }[0], [sp] // encoding: [0xe3,0x87,0x41,0x0d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldap1 { v3.d }[0], [sp, #0] -// CHECK: ldap1 { v3.d }[0], [sp] // encoding: [0xe3,0x87,0x41,0x0d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldap1 { v3.d }[1], [x15] -// CHECK: ldap1 { v3.d }[1], [x15] // encoding: [0xe3,0x85,0x41,0x4d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 - ldap1 { v3.d }[1], [x15, 0] -// CHECK: ldap1 { v3.d }[1], [x15] // encoding: [0xe3,0x85,0x41,0x4d] -// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+rcpc3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+rcpc3,+v8.9a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+rcpc3,+v9.4a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+rcpc3 < %s \ +// RUN: | llvm-objdump -d --mattr=+rcpc3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+rcpc3 < %s \ +// RUN: | llvm-objdump -d --mattr=-rcpc3 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+rcpc3 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+rcpc3 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +stilp w24, w0, [x16, #-8]! +// CHECK-INST: stilp w24, w0, [x16, #-8]! +// CHECK-ENCODING: encoding: [0x18,0x0a,0x00,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99000a18 <unknown> + +stilp w24, w0, [x16, -8]! +// CHECK-INST: stilp w24, w0, [x16, #-8]! +// CHECK-ENCODING: encoding: [0x18,0x0a,0x00,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99000a18 <unknown> + +stilp x25, x1, [x17, -16]! +// CHECK-INST: stilp x25, x1, [x17, #-16]! +// CHECK-ENCODING: encoding: [0x39,0x0a,0x01,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9010a39 <unknown> + +stilp x25, x1, [x17, #-16]! +// CHECK-INST: stilp x25, x1, [x17, #-16]! +// CHECK-ENCODING: encoding: [0x39,0x0a,0x01,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9010a39 <unknown> + +stilp w26, w2, [x18] +// CHECK-INST: stilp w26, w2, [x18] +// CHECK-ENCODING: encoding: [0x5a,0x1a,0x02,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99021a5a <unknown> + +stilp w26, w2, [x18, #0] +// CHECK-INST: stilp w26, w2, [x18] +// CHECK-ENCODING: encoding: [0x5a,0x1a,0x02,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99021a5a <unknown> + +stilp x27, x3, [sp] +// CHECK-INST: stilp x27, x3, [sp] +// CHECK-ENCODING: encoding: [0xfb,0x1b,0x03,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9031bfb <unknown> + +stilp x27, x3, [sp, 0] +// CHECK-INST: stilp x27, x3, [sp] +// CHECK-ENCODING: encoding: [0xfb,0x1b,0x03,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9031bfb <unknown> + +ldiapp w28, w4, [x20], #8 +// CHECK-INST: ldiapp w28, w4, [x20], #8 +// CHECK-ENCODING: encoding: [0x9c,0x0a,0x44,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99440a9c <unknown> + +ldiapp w28, w4, [x20, #0], #8 +// CHECK-INST: ldiapp w28, w4, [x20], #8 +// CHECK-ENCODING: encoding: [0x9c,0x0a,0x44,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99440a9c <unknown> + +ldiapp w28, w4, [x20], 8 +// CHECK-INST: ldiapp w28, w4, [x20], #8 +// CHECK-ENCODING: encoding: [0x9c,0x0a,0x44,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99440a9c <unknown> + +ldiapp w28, w4, [x20, 0], 8 +// CHECK-INST: ldiapp w28, w4, [x20], #8 +// CHECK-ENCODING: encoding: [0x9c,0x0a,0x44,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99440a9c <unknown> + +ldiapp x29, x5, [x21], #16 +// CHECK-INST: ldiapp x29, x5, [x21], #16 +// CHECK-ENCODING: encoding: [0xbd,0x0a,0x45,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9450abd <unknown> + +ldiapp x29, x5, [x21], 16 +// CHECK-INST: ldiapp x29, x5, [x21], #16 +// CHECK-ENCODING: encoding: [0xbd,0x0a,0x45,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9450abd <unknown> + +ldiapp w30, w6, [sp] +// CHECK-INST: ldiapp w30, w6, [sp] +// CHECK-ENCODING: encoding: [0xfe,0x1b,0x46,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99461bfe <unknown> + +ldiapp w30, w6, [sp, #0] +// CHECK-INST: ldiapp w30, w6, [sp] +// CHECK-ENCODING: encoding: [0xfe,0x1b,0x46,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99461bfe <unknown> + +ldiapp xzr, x7, [x23] +// CHECK-INST: ldiapp xzr, x7, [x23] +// CHECK-ENCODING: encoding: [0xff,0x1a,0x47,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9471aff <unknown> + +ldiapp xzr, x7, [x23, 0] +// CHECK-INST: ldiapp xzr, x7, [x23] +// CHECK-ENCODING: encoding: [0xff,0x1a,0x47,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9471aff <unknown> + +stlr w3, [x15, #-4]! +// CHECK-INST: stlr w3, [x15, #-4]! +// CHECK-ENCODING: encoding: [0xe3,0x09,0x80,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 998009e3 <unknown> + +stlr w3, [x15, -4]! +// CHECK-INST: stlr w3, [x15, #-4]! +// CHECK-ENCODING: encoding: [0xe3,0x09,0x80,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 998009e3 <unknown> + +stlr x3, [x15, #-8]! +// CHECK-INST: stlr x3, [x15, #-8]! +// CHECK-ENCODING: encoding: [0xe3,0x09,0x80,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d98009e3 <unknown> + +stlr x3, [sp, -8]! +// CHECK-INST: stlr x3, [sp, #-8]! +// CHECK-ENCODING: encoding: [0xe3,0x0b,0x80,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9800be3 <unknown> + +ldapr w3, [sp], #4 +// CHECK-INST: ldapr w3, [sp], #4 +// CHECK-ENCODING: encoding: [0xe3,0x0b,0xc0,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99c00be3 <unknown> + +ldapr w3, [x15], 4 +// CHECK-INST: ldapr w3, [x15], #4 +// CHECK-ENCODING: encoding: [0xe3,0x09,0xc0,0x99] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 99c009e3 <unknown> + +ldapr x3, [x15], #8 +// CHECK-INST: ldapr x3, [x15], #8 +// CHECK-ENCODING: encoding: [0xe3,0x09,0xc0,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9c009e3 <unknown> + +ldapr x3, [x15], 8 +// CHECK-INST: ldapr x3, [x15], #8 +// CHECK-ENCODING: encoding: [0xe3,0x09,0xc0,0xd9] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: d9c009e3 <unknown> + +stlur b3, [x15, #-1] +// CHECK-INST: stlur b3, [x15, #-1] +// CHECK-ENCODING: encoding: [0xe3,0xf9,0x1f,0x1d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 1d1ff9e3 <unknown> + +stlur h3, [x15, #2] +// CHECK-INST: stlur h3, [x15, #2] +// CHECK-ENCODING: encoding: [0xe3,0x29,0x00,0x5d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 5d0029e3 <unknown> + +stlur s3, [x15, #-3] +// CHECK-INST: stlur s3, [x15, #-3] +// CHECK-ENCODING: encoding: [0xe3,0xd9,0x1f,0x9d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 9d1fd9e3 <unknown> + +stlur d3, [sp, #4] +// CHECK-INST: stlur d3, [sp, #4] +// CHECK-ENCODING: encoding: [0xe3,0x4b,0x00,0xdd] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: dd004be3 <unknown> + +stlur q3, [x15, #-5] +// CHECK-INST: stlur q3, [x15, #-5] +// CHECK-ENCODING: encoding: [0xe3,0xb9,0x9f,0x1d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 1d9fb9e3 <unknown> + +ldapur b3, [x15, #6] +// CHECK-INST: ldapur b3, [x15, #6] +// CHECK-ENCODING: encoding: [0xe3,0x69,0x40,0x1d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 1d4069e3 <unknown> + +ldapur h3, [x15, #-7] +// CHECK-INST: ldapur h3, [x15, #-7] +// CHECK-ENCODING: encoding: [0xe3,0x99,0x5f,0x5d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 5d5f99e3 <unknown> + +ldapur s3, [x15, #8] +// CHECK-INST: ldapur s3, [x15, #8] +// CHECK-ENCODING: encoding: [0xe3,0x89,0x40,0x9d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 9d4089e3 <unknown> + +ldapur d3, [x15, #-9] +// CHECK-INST: ldapur d3, [x15, #-9] +// CHECK-ENCODING: encoding: [0xe3,0x79,0x5f,0xdd] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: dd5f79e3 <unknown> + +ldapur q3, [sp, #10] +// CHECK-INST: ldapur q3, [sp, #10] +// CHECK-ENCODING: encoding: [0xe3,0xab,0xc0,0x1d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 1dc0abe3 <unknown> + +stl1 { v3.d }[0], [x15] +// CHECK-INST: stl1 { v3.d }[0], [x15] +// CHECK-ENCODING: encoding: [0xe3,0x85,0x01,0x0d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 0d0185e3 <unknown> + +stl1 { v3.d }[0], [x15, #0] +// CHECK-INST: stl1 { v3.d }[0], [x15] +// CHECK-ENCODING: encoding: [0xe3,0x85,0x01,0x0d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 0d0185e3 <unknown> + +stl1 { v3.d }[1], [sp] +// CHECK-INST: stl1 { v3.d }[1], [sp] +// CHECK-ENCODING: encoding: [0xe3,0x87,0x01,0x4d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 4d0187e3 <unknown> + +stl1 { v3.d }[1], [sp, 0] +// CHECK-INST: stl1 { v3.d }[1], [sp] +// CHECK-ENCODING: encoding: [0xe3,0x87,0x01,0x4d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 4d0187e3 <unknown> + +ldap1 { v3.d }[0], [sp] +// CHECK-INST: ldap1 { v3.d }[0], [sp] +// CHECK-ENCODING: encoding: [0xe3,0x87,0x41,0x0d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 0d4187e3 <unknown> + +ldap1 { v3.d }[0], [sp, #0] +// CHECK-INST: ldap1 { v3.d }[0], [sp] +// CHECK-ENCODING: encoding: [0xe3,0x87,0x41,0x0d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 0d4187e3 <unknown> + +ldap1 { v3.d }[1], [x15] +// CHECK-INST: ldap1 { v3.d }[1], [x15] +// CHECK-ENCODING: encoding: [0xe3,0x85,0x41,0x4d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 4d4185e3 <unknown> + +ldap1 { v3.d }[1], [x15, 0] +// CHECK-INST: ldap1 { v3.d }[1], [x15] +// CHECK-ENCODING: encoding: [0xe3,0x85,0x41,0x4d] +// CHECK-ERROR:error: instruction requires: rcpc3 +// CHECK-UNKNOWN: 4d4185e3 <unknown> diff --git a/llvm/test/MC/AArch64/armv8.9a-specres2.s b/llvm/test/MC/AArch64/armv8.9a-specres2.s index b411ec31580b..b79124d09e92 100644 --- a/llvm/test/MC/AArch64/armv8.9a-specres2.s +++ b/llvm/test/MC/AArch64/armv8.9a-specres2.s @@ -1,13 +1,32 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specres2 < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a < %s | FileCheck %s -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specres2 < %s 2>&1 | FileCheck %s --check-prefix=NOSPECRES2 +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.9a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+specres2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+specres2 < %s \ +// RUN: | llvm-objdump -d --mattr=+specres2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+specres2 < %s \ +// RUN: | llvm-objdump -d --mattr=-specres2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+specres2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+specres2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + cosp rctx, x0 +// CHECK-INST: cosp rctx, x0 +// CHECK-ENCODING: encoding: [0xc0,0x73,0x0b,0xd5] +// CHECK-ERROR: error: COSP requires: predres2 +// CHECK-UNKNOWN: d50b73c0 sys #3, c7, c3, #6, x0 + sys #3, c7, c3, #6, x0 +// CHECK-INST: cosp rctx, x0 +// CHECK-ENCODING: encoding: [0xc0,0x73,0x0b,0xd5] +// CHECK-UNKNOWN: d50b73c0 sys #3, c7, c3, #6, x0 -// CHECK: cosp rctx, x0 // encoding: [0xc0,0x73,0x0b,0xd5] -// CHECK: cosp rctx, x0 // encoding: [0xc0,0x73,0x0b,0xd5] -// NOSPECRES2: COSP requires: predres2 -// NOSPECRES2-NEXT: cosp diff --git a/llvm/test/MC/AArch64/armv8.9a-the-diagnostics.s b/llvm/test/MC/AArch64/armv8.9a-the-diagnostics.s new file mode 100644 index 000000000000..0fccbe1134d0 --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.9a-the-diagnostics.s @@ -0,0 +1,103 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ZXR %s + +rcwswpp xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwswppa xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwswppal xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwswppl xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwswpp x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwswppa x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwswppal x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwswppl x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction + +rcwclrp xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwclrpa xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwclrpal xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwclrpl xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwclrp x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwclrpa x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwclrpal x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwclrpl x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction + +rcwsetp xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsetpa xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsetpal xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsetpl xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsetp x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsetpa x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsetpal x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsetpl x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction + +rcwsswpp xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsswppa xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsswppal xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsswppl xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsswpp x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsswppa x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsswppal x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsswppl x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction + +rcwsclrp xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsclrpa xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsclrpal xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsclrpl xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsclrp x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsclrpa x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsclrpal x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwsclrpl x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction + +rcwssetp xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwssetpa xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwssetpal xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwssetpl xzr, x5, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwssetp x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwssetpa x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwssetpal x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction +rcwssetpl x5, xzr, [x4] +// ERROR-NO-ZXR: error: invalid operand for instruction diff --git a/llvm/test/MC/AArch64/armv8.9a-the.s b/llvm/test/MC/AArch64/armv8.9a-the.s index 33e1b5d27fa7..689b6c9280e7 100644 --- a/llvm/test/MC/AArch64/armv8.9a-the.s +++ b/llvm/test/MC/AArch64/armv8.9a-the.s @@ -1,592 +1,843 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+the -mattr=+d128 < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+the -mattr=+d128 < %s | FileCheck %s - -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-THE %s - -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s - -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+the -mattr=+d128 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ZXR %s - - mrs x3, RCWMASK_EL1 -// CHECK: mrs x3, RCWMASK_EL1 // encoding: [0xc3,0xd0,0x38,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register - msr RCWMASK_EL1, x1 -// CHECK: msr RCWMASK_EL1, x1 // encoding: [0xc1,0xd0,0x18,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate - mrs x3, RCWSMASK_EL1 -// CHECK: mrs x3, RCWSMASK_EL1 // encoding: [0x63,0xd0,0x38,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:21: error: expected readable system register - msr RCWSMASK_EL1, x1 -// CHECK: msr RCWSMASK_EL1, x1 // encoding: [0x61,0xd0,0x18,0xd5] -// ERROR-NO-THE: [[@LINE-2]]:17: error: expected writable system register or pstate - - rcwcas x0, x1, [x4] -// CHECK: rcwcas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwcasa x0, x1, [x4] -// CHECK: rcwcasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwcasal x0, x1, [x4] -// CHECK: rcwcasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwcasl x0, x1, [x4] -// CHECK: rcwcasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwcas x3, x5, [sp] -// CHECK: rcwcas x3, x5, [sp] // encoding: [0xe5,0x0b,0x23,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwcasa x3, x5, [sp] -// CHECK: rcwcasa x3, x5, [sp] // encoding: [0xe5,0x0b,0xa3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwcasal x3, x5, [sp] -// CHECK: rcwcasal x3, x5, [sp] // encoding: [0xe5,0x0b,0xe3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwcasl x3, x5, [sp] -// CHECK: rcwcasl x3, x5, [sp] // encoding: [0xe5,0x0b,0x63,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwscas x0, x1, [x4] -// CHECK: rcwscas x0, x1, [x4] // encoding: [0x81,0x08,0x20,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwscasa x0, x1, [x4] -// CHECK: rcwscasa x0, x1, [x4] // encoding: [0x81,0x08,0xa0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwscasal x0, x1, [x4] -// CHECK: rcwscasal x0, x1, [x4] // encoding: [0x81,0x08,0xe0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwscasl x0, x1, [x4] -// CHECK: rcwscasl x0, x1, [x4] // encoding: [0x81,0x08,0x60,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwscas x3, x5, [sp] -// CHECK: rcwscas x3, x5, [sp] // encoding: [0xe5,0x0b,0x23,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwscasa x3, x5, [sp] -// CHECK: rcwscasa x3, x5, [sp] // encoding: [0xe5,0x0b,0xa3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwscasal x3, x5, [sp] -// CHECK: rcwscasal x3, x5, [sp] // encoding: [0xe5,0x0b,0xe3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwscasl x3, x5, [sp] -// CHECK: rcwscasl x3, x5, [sp] // encoding: [0xe5,0x0b,0x63,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwcasp x0, x1, x6, x7, [x4] -// CHECK: rcwcasp x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x20,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwcaspa x0, x1, x6, x7, [x4] -// CHECK: rcwcaspa x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xa0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwcaspal x0, x1, x6, x7, [x4] -// CHECK: rcwcaspal x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xe0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwcaspl x0, x1, x6, x7, [x4] -// CHECK: rcwcaspl x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x60,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwcasp x4, x5, x6, x7, [sp] -// CHECK: rcwcasp x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x24,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwcaspa x4, x5, x6, x7, [sp] -// CHECK: rcwcaspa x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xa4,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwcaspal x4, x5, x6, x7, [sp] -// CHECK: rcwcaspal x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xe4,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwcaspl x4, x5, x6, x7, [sp] -// CHECK: rcwcaspl x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x64,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwscasp x0, x1, x6, x7, [x4] -// CHECK: rcwscasp x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x20,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwscaspa x0, x1, x6, x7, [x4] -// CHECK: rcwscaspa x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xa0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwscaspal x0, x1, x6, x7, [x4] -// CHECK: rcwscaspal x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0xe0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwscaspl x0, x1, x6, x7, [x4] -// CHECK: rcwscaspl x0, x1, x6, x7, [x4] // encoding: [0x86,0x0c,0x60,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwscasp x4, x5, x6, x7, [sp] -// CHECK: rcwscasp x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x24,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwscaspa x4, x5, x6, x7, [sp] -// CHECK: rcwscaspa x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xa4,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwscaspal x4, x5, x6, x7, [sp] -// CHECK: rcwscaspal x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0xe4,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwscaspl x4, x5, x6, x7, [sp] -// CHECK: rcwscaspl x4, x5, x6, x7, [sp] // encoding: [0xe6,0x0f,0x64,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwclr x0, x1, [x4] -// CHECK: rcwclr x0, x1, [x4] // encoding: [0x81,0x90,0x20,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwclra x0, x1, [x4] -// CHECK: rcwclra x0, x1, [x4] // encoding: [0x81,0x90,0xa0,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwclral x0, x1, [x4] -// CHECK: rcwclral x0, x1, [x4] // encoding: [0x81,0x90,0xe0,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwclrl x0, x1, [x4] -// CHECK: rcwclrl x0, x1, [x4] // encoding: [0x81,0x90,0x60,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwclr x3, x5, [sp] -// CHECK: rcwclr x3, x5, [sp] // encoding: [0xe5,0x93,0x23,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwclra x3, x5, [sp] -// CHECK: rcwclra x3, x5, [sp] // encoding: [0xe5,0x93,0xa3,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwclral x3, x5, [sp] -// CHECK: rcwclral x3, x5, [sp] // encoding: [0xe5,0x93,0xe3,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwclrl x3, x5, [sp] -// CHECK: rcwclrl x3, x5, [sp] // encoding: [0xe5,0x93,0x63,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwsclr x0, x1, [x4] -// CHECK: rcwsclr x0, x1, [x4] // encoding: [0x81,0x90,0x20,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsclra x0, x1, [x4] -// CHECK: rcwsclra x0, x1, [x4] // encoding: [0x81,0x90,0xa0,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsclral x0, x1, [x4] -// CHECK: rcwsclral x0, x1, [x4] // encoding: [0x81,0x90,0xe0,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsclrl x0, x1, [x4] -// CHECK: rcwsclrl x0, x1, [x4] // encoding: [0x81,0x90,0x60,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsclr x3, x5, [sp] -// CHECK: rcwsclr x3, x5, [sp] // encoding: [0xe5,0x93,0x23,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsclra x3, x5, [sp] -// CHECK: rcwsclra x3, x5, [sp] // encoding: [0xe5,0x93,0xa3,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsclral x3, x5, [sp] -// CHECK: rcwsclral x3, x5, [sp] // encoding: [0xe5,0x93,0xe3,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsclrl x3, x5, [sp] -// CHECK: rcwsclrl x3, x5, [sp] // encoding: [0xe5,0x93,0x63,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwclrp x1, x0, [x4] -// CHECK: rcwclrp x1, x0, [x4] // encoding: [0x81,0x90,0x20,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwclrpa x1, x0, [x4] -// CHECK: rcwclrpa x1, x0, [x4] // encoding: [0x81,0x90,0xa0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwclrpal x1, x0, [x4] -// CHECK: rcwclrpal x1, x0, [x4] // encoding: [0x81,0x90,0xe0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwclrpl x1, x0, [x4] -// CHECK: rcwclrpl x1, x0, [x4] // encoding: [0x81,0x90,0x60,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwclrp x5, x3, [sp] -// CHECK: rcwclrp x5, x3, [sp] // encoding: [0xe5,0x93,0x23,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwclrpa x5, x3, [sp] -// CHECK: rcwclrpa x5, x3, [sp] // encoding: [0xe5,0x93,0xa3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwclrpal x5, x3, [sp] -// CHECK: rcwclrpal x5, x3, [sp] // encoding: [0xe5,0x93,0xe3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwclrpl x5, x3, [sp] -// CHECK: rcwclrpl x5, x3, [sp] // encoding: [0xe5,0x93,0x63,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwsclrp x1, x0, [x4] -// CHECK: rcwsclrp x1, x0, [x4] // encoding: [0x81,0x90,0x20,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsclrpa x1, x0, [x4] -// CHECK: rcwsclrpa x1, x0, [x4] // encoding: [0x81,0x90,0xa0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsclrpal x1, x0, [x4] -// CHECK: rcwsclrpal x1, x0, [x4] // encoding: [0x81,0x90,0xe0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsclrpl x1, x0, [x4] -// CHECK: rcwsclrpl x1, x0, [x4] // encoding: [0x81,0x90,0x60,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsclrp x5, x3, [sp] -// CHECK: rcwsclrp x5, x3, [sp] // encoding: [0xe5,0x93,0x23,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsclrpa x5, x3, [sp] -// CHECK: rcwsclrpa x5, x3, [sp] // encoding: [0xe5,0x93,0xa3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsclrpal x5, x3, [sp] -// CHECK: rcwsclrpal x5, x3, [sp] // encoding: [0xe5,0x93,0xe3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsclrpl x5, x3, [sp] -// CHECK: rcwsclrpl x5, x3, [sp] // encoding: [0xe5,0x93,0x63,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwset x0, x1, [x4] -// CHECK: rcwset x0, x1, [x4] // encoding: [0x81,0xb0,0x20,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwseta x0, x1, [x4] -// CHECK: rcwseta x0, x1, [x4] // encoding: [0x81,0xb0,0xa0,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsetal x0, x1, [x4] -// CHECK: rcwsetal x0, x1, [x4] // encoding: [0x81,0xb0,0xe0,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsetl x0, x1, [x4] -// CHECK: rcwsetl x0, x1, [x4] // encoding: [0x81,0xb0,0x60,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwset x3, x5, [sp] -// CHECK: rcwset x3, x5, [sp] // encoding: [0xe5,0xb3,0x23,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwseta x3, x5, [sp] -// CHECK: rcwseta x3, x5, [sp] // encoding: [0xe5,0xb3,0xa3,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsetal x3, x5, [sp] -// CHECK: rcwsetal x3, x5, [sp] // encoding: [0xe5,0xb3,0xe3,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsetl x3, x5, [sp] -// CHECK: rcwsetl x3, x5, [sp] // encoding: [0xe5,0xb3,0x63,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwsset x0, x1, [x4] -// CHECK: rcwsset x0, x1, [x4] // encoding: [0x81,0xb0,0x20,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsseta x0, x1, [x4] -// CHECK: rcwsseta x0, x1, [x4] // encoding: [0x81,0xb0,0xa0,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwssetal x0, x1, [x4] -// CHECK: rcwssetal x0, x1, [x4] // encoding: [0x81,0xb0,0xe0,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwssetl x0, x1, [x4] -// CHECK: rcwssetl x0, x1, [x4] // encoding: [0x81,0xb0,0x60,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsset x3, x5, [sp] -// CHECK: rcwsset x3, x5, [sp] // encoding: [0xe5,0xb3,0x23,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsseta x3, x5, [sp] -// CHECK: rcwsseta x3, x5, [sp] // encoding: [0xe5,0xb3,0xa3,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwssetal x3, x5, [sp] -// CHECK: rcwssetal x3, x5, [sp] // encoding: [0xe5,0xb3,0xe3,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwssetl x3, x5, [sp] -// CHECK: rcwssetl x3, x5, [sp] // encoding: [0xe5,0xb3,0x63,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwsetp x1, x0, [x4] -// CHECK: rcwsetp x1, x0, [x4] // encoding: [0x81,0xb0,0x20,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsetpa x1, x0, [x4] -// CHECK: rcwsetpa x1, x0, [x4] // encoding: [0x81,0xb0,0xa0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsetpal x1, x0, [x4] -// CHECK: rcwsetpal x1, x0, [x4] // encoding: [0x81,0xb0,0xe0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsetpl x1, x0, [x4] -// CHECK: rcwsetpl x1, x0, [x4] // encoding: [0x81,0xb0,0x60,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsetp x5, x3, [sp] -// CHECK: rcwsetp x5, x3, [sp] // encoding: [0xe5,0xb3,0x23,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsetpa x5, x3, [sp] -// CHECK: rcwsetpa x5, x3, [sp] // encoding: [0xe5,0xb3,0xa3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsetpal x5, x3, [sp] -// CHECK: rcwsetpal x5, x3, [sp] // encoding: [0xe5,0xb3,0xe3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsetpl x5, x3, [sp] -// CHECK: rcwsetpl x5, x3, [sp] // encoding: [0xe5,0xb3,0x63,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwssetp x1, x0, [x4] -// CHECK: rcwssetp x1, x0, [x4] // encoding: [0x81,0xb0,0x20,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwssetpa x1, x0, [x4] -// CHECK: rcwssetpa x1, x0, [x4] // encoding: [0x81,0xb0,0xa0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwssetpal x1, x0, [x4] -// CHECK: rcwssetpal x1, x0, [x4] // encoding: [0x81,0xb0,0xe0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwssetpl x1, x0, [x4] -// CHECK: rcwssetpl x1, x0, [x4] // encoding: [0x81,0xb0,0x60,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwssetp x5, x3, [sp] -// CHECK: rcwssetp x5, x3, [sp] // encoding: [0xe5,0xb3,0x23,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwssetpa x5, x3, [sp] -// CHECK: rcwssetpa x5, x3, [sp] // encoding: [0xe5,0xb3,0xa3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwssetpal x5, x3, [sp] -// CHECK: rcwssetpal x5, x3, [sp] // encoding: [0xe5,0xb3,0xe3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwssetpl x5, x3, [sp] -// CHECK: rcwssetpl x5, x3, [sp] // encoding: [0xe5,0xb3,0x63,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwswp x0, x1, [x4] -// CHECK: rcwswp x0, x1, [x4] // encoding: [0x81,0xa0,0x20,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwswpa x0, x1, [x4] -// CHECK: rcwswpa x0, x1, [x4] // encoding: [0x81,0xa0,0xa0,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwswpal x0, x1, [x4] -// CHECK: rcwswpal x0, x1, [x4] // encoding: [0x81,0xa0,0xe0,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwswpl x0, x1, [x4] -// CHECK: rcwswpl x0, x1, [x4] // encoding: [0x81,0xa0,0x60,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwswp x3, x5, [sp] -// CHECK: rcwswp x3, x5, [sp] // encoding: [0xe5,0xa3,0x23,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwswpa x3, x5, [sp] -// CHECK: rcwswpa x3, x5, [sp] // encoding: [0xe5,0xa3,0xa3,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwswpal x3, x5, [sp] -// CHECK: rcwswpal x3, x5, [sp] // encoding: [0xe5,0xa3,0xe3,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwswpl x3, x5, [sp] -// CHECK: rcwswpl x3, x5, [sp] // encoding: [0xe5,0xa3,0x63,0x38] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwsswp x0, x1, [x4] -// CHECK: rcwsswp x0, x1, [x4] // encoding: [0x81,0xa0,0x20,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsswpa x0, x1, [x4] -// CHECK: rcwsswpa x0, x1, [x4] // encoding: [0x81,0xa0,0xa0,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsswpal x0, x1, [x4] -// CHECK: rcwsswpal x0, x1, [x4] // encoding: [0x81,0xa0,0xe0,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsswpl x0, x1, [x4] -// CHECK: rcwsswpl x0, x1, [x4] // encoding: [0x81,0xa0,0x60,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsswp x3, x5, [sp] -// CHECK: rcwsswp x3, x5, [sp] // encoding: [0xe5,0xa3,0x23,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsswpa x3, x5, [sp] -// CHECK: rcwsswpa x3, x5, [sp] // encoding: [0xe5,0xa3,0xa3,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsswpal x3, x5, [sp] -// CHECK: rcwsswpal x3, x5, [sp] // encoding: [0xe5,0xa3,0xe3,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - rcwsswpl x3, x5, [sp] -// CHECK: rcwsswpl x3, x5, [sp] // encoding: [0xe5,0xa3,0x63,0x78] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: the - - rcwswpp x1, x0, [x4] -// CHECK: rcwswpp x1, x0, [x4] // encoding: [0x81,0xa0,0x20,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwswppa x1, x0, [x4] -// CHECK: rcwswppa x1, x0, [x4] // encoding: [0x81,0xa0,0xa0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwswppal x1, x0, [x4] -// CHECK: rcwswppal x1, x0, [x4] // encoding: [0x81,0xa0,0xe0,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwswppl x1, x0, [x4] -// CHECK: rcwswppl x1, x0, [x4] // encoding: [0x81,0xa0,0x60,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwswpp x5, x3, [sp] -// CHECK: rcwswpp x5, x3, [sp] // encoding: [0xe5,0xa3,0x23,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwswppa x5, x3, [sp] -// CHECK: rcwswppa x5, x3, [sp] // encoding: [0xe5,0xa3,0xa3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwswppal x5, x3, [sp] -// CHECK: rcwswppal x5, x3, [sp] // encoding: [0xe5,0xa3,0xe3,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwswppl x5, x3, [sp] -// CHECK: rcwswppl x5, x3, [sp] // encoding: [0xe5,0xa3,0x63,0x19] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwsswpp x1, x0, [x4] -// CHECK: rcwsswpp x1, x0, [x4] // encoding: [0x81,0xa0,0x20,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsswppa x1, x0, [x4] -// CHECK: rcwsswppa x1, x0, [x4] // encoding: [0x81,0xa0,0xa0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsswppal x1, x0, [x4] -// CHECK: rcwsswppal x1, x0, [x4] // encoding: [0x81,0xa0,0xe0,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsswppl x1, x0, [x4] -// CHECK: rcwsswppl x1, x0, [x4] // encoding: [0x81,0xa0,0x60,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsswpp x5, x3, [sp] -// CHECK: rcwsswpp x5, x3, [sp] // encoding: [0xe5,0xa3,0x23,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsswppa x5, x3, [sp] -// CHECK: rcwsswppa x5, x3, [sp] // encoding: [0xe5,0xa3,0xa3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsswppal x5, x3, [sp] -// CHECK: rcwsswppal x5, x3, [sp] // encoding: [0xe5,0xa3,0xe3,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - rcwsswppl x5, x3, [sp] -// CHECK: rcwsswppl x5, x3, [sp] // encoding: [0xe5,0xa3,0x63,0x59] -// ERROR-NO-THE: [[@LINE-2]]:13: error: instruction requires: d128 the -// ERROR-NO-D128: [[@LINE-3]]:13: error: instruction requires: d128 - - rcwswpp xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwswppa xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwswppal xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwswppl xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwswpp x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwswppa x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwswppal x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwswppl x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - - rcwclrp xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwclrpa xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwclrpal xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwclrpl xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwclrp x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwclrpa x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwclrpal x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwclrpl x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - - rcwsetp xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwsetpa xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwsetpal xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwsetpl xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:23: error: invalid operand for instruction - rcwsetp x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwsetpa x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwsetpal x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - rcwsetpl x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:27: error: invalid operand for instruction - - rcwsswpp xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsswppa xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsswppal xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsswppl xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsswpp x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwsswppa x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwsswppal x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwsswppl x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - - rcwsclrp xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsclrpa xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsclrpal xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsclrpl xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwsclrp x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwsclrpa x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwsclrpal x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwsclrpl x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - - rcwssetp xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwssetpa xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwssetpal xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwssetpl xzr, x5, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:24: error: invalid operand for instruction - rcwssetp x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwssetpa x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwssetpal x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction - rcwssetpl x5, xzr, [x4] -// ERROR-NO-ZXR: [[@LINE-1]]:28: error: invalid operand for instruction +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128,v8.9a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128,v9.4a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+d128 < %s \ +// RUN: | llvm-objdump -d --mattr=+the,+d128 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+the,+d128 < %s \ +// RUN: | llvm-objdump -d --mattr=-the,-d128 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+the,+d128 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+the,+d128 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -mattr=+the < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-D128 %s + + +mrs x3, RCWMASK_EL1 +// CHECK-INST: mrs x3, RCWMASK_EL1 +// CHECK-ENCODING: encoding: [0xc3,0xd0,0x38,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d538d0c3 mrs x3, S3_0_C13_C0_6 + +msr RCWMASK_EL1, x1 +// CHECK-INST: msr RCWMASK_EL1, x1 +// CHECK-ENCODING: encoding: [0xc1,0xd0,0x18,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d518d0c1 msr S3_0_C13_C0_6, x1 + +mrs x3, RCWSMASK_EL1 +// CHECK-INST: mrs x3, RCWSMASK_EL1 +// CHECK-ENCODING: encoding: [0x63,0xd0,0x38,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d538d063 mrs x3, S3_0_C13_C0_3 + +msr RCWSMASK_EL1, x1 +// CHECK-INST: msr RCWSMASK_EL1, x1 +// CHECK-ENCODING: encoding: [0x61,0xd0,0x18,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d518d061 msr S3_0_C13_C0_3, x1 + +rcwcas x0, x1, [x4] +// CHECK-INST: rcwcas x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0x20,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19200881 <unknown> + +rcwcasa x0, x1, [x4] +// CHECK-INST: rcwcasa x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0xa0,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19a00881 <unknown> + +rcwcasal x0, x1, [x4] +// CHECK-INST: rcwcasal x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0xe0,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19e00881 <unknown> + +rcwcasl x0, x1, [x4] +// CHECK-INST: rcwcasl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0x60,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19600881 <unknown> + +rcwcas x3, x5, [sp] +// CHECK-INST: rcwcas x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0x23,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19230be5 <unknown> + +rcwcasa x3, x5, [sp] +// CHECK-INST: rcwcasa x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0xa3,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19a30be5 <unknown> + +rcwcasal x3, x5, [sp] +// CHECK-INST: rcwcasal x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0xe3,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19e30be5 <unknown> + +rcwcasl x3, x5, [sp] +// CHECK-INST: rcwcasl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0x63,0x19] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 19630be5 <unknown> + +rcwscas x0, x1, [x4] +// CHECK-INST: rcwscas x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0x20,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59200881 <unknown> + +rcwscasa x0, x1, [x4] +// CHECK-INST: rcwscasa x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0xa0,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59a00881 <unknown> + +rcwscasal x0, x1, [x4] +// CHECK-INST: rcwscasal x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0xe0,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59e00881 <unknown> + +rcwscasl x0, x1, [x4] +// CHECK-INST: rcwscasl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x08,0x60,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59600881 <unknown> + +rcwscas x3, x5, [sp] +// CHECK-INST: rcwscas x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0x23,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59230be5 <unknown> + +rcwscasa x3, x5, [sp] +// CHECK-INST: rcwscasa x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0xa3,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59a30be5 <unknown> + +rcwscasal x3, x5, [sp] +// CHECK-INST: rcwscasal x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0xe3,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59e30be5 <unknown> + +rcwscasl x3, x5, [sp] +// CHECK-INST: rcwscasl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x0b,0x63,0x59] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 59630be5 <unknown> + +rcwcasp x0, x1, x6, x7, [x4] +// CHECK-INST: rcwcasp x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0x20,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19200c86 <unknown> + +rcwcaspa x0, x1, x6, x7, [x4] +// CHECK-INST: rcwcaspa x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0xa0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19a00c86 <unknown> + +rcwcaspal x0, x1, x6, x7, [x4] +// CHECK-INST: rcwcaspal x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0xe0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19e00c86 <unknown> + +rcwcaspl x0, x1, x6, x7, [x4] +// CHECK-INST: rcwcaspl x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0x60,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19600c86 <unknown> + +rcwcasp x4, x5, x6, x7, [sp] +// CHECK-INST: rcwcasp x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0x24,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19240fe6 <unknown> + +rcwcaspa x4, x5, x6, x7, [sp] +// CHECK-INST: rcwcaspa x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0xa4,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19a40fe6 <unknown> + +rcwcaspal x4, x5, x6, x7, [sp] +// CHECK-INST: rcwcaspal x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0xe4,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19e40fe6 <unknown> + +rcwcaspl x4, x5, x6, x7, [sp] +// CHECK-INST: rcwcaspl x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0x64,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19640fe6 <unknown> + +rcwscasp x0, x1, x6, x7, [x4] +// CHECK-INST: rcwscasp x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0x20,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59200c86 <unknown> + +rcwscaspa x0, x1, x6, x7, [x4] +// CHECK-INST: rcwscaspa x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0xa0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59a00c86 <unknown> + +rcwscaspal x0, x1, x6, x7, [x4] +// CHECK-INST: rcwscaspal x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0xe0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59e00c86 <unknown> + +rcwscaspl x0, x1, x6, x7, [x4] +// CHECK-INST: rcwscaspl x0, x1, x6, x7, [x4] +// CHECK-ENCODING: encoding: [0x86,0x0c,0x60,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59600c86 <unknown> + +rcwscasp x4, x5, x6, x7, [sp] +// CHECK-INST: rcwscasp x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0x24,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59240fe6 <unknown> + +rcwscaspa x4, x5, x6, x7, [sp] +// CHECK-INST: rcwscaspa x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0xa4,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59a40fe6 <unknown> + +rcwscaspal x4, x5, x6, x7, [sp] +// CHECK-INST: rcwscaspal x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0xe4,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59e40fe6 <unknown> + +rcwscaspl x4, x5, x6, x7, [sp] +// CHECK-INST: rcwscaspl x4, x5, x6, x7, [sp] +// CHECK-ENCODING: encoding: [0xe6,0x0f,0x64,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59640fe6 <unknown> + +rcwclr x0, x1, [x4] +// CHECK-INST: rcwclr x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x20,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38209081 <unknown> + +rcwclra x0, x1, [x4] +// CHECK-INST: rcwclra x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xa0,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38a09081 <unknown> + +rcwclral x0, x1, [x4] +// CHECK-INST: rcwclral x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xe0,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38e09081 <unknown> + +rcwclrl x0, x1, [x4] +// CHECK-INST: rcwclrl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x60,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38609081 <unknown> + +rcwclr x3, x5, [sp] +// CHECK-INST: rcwclr x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x23,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 382393e5 <unknown> + +rcwclra x3, x5, [sp] +// CHECK-INST: rcwclra x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xa3,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38a393e5 <unknown> + +rcwclral x3, x5, [sp] +// CHECK-INST: rcwclral x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xe3,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38e393e5 <unknown> + +rcwclrl x3, x5, [sp] +// CHECK-INST: rcwclrl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x63,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 386393e5 <unknown> + +rcwsclr x0, x1, [x4] +// CHECK-INST: rcwsclr x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x20,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78209081 <unknown> + +rcwsclra x0, x1, [x4] +// CHECK-INST: rcwsclra x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xa0,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78a09081 <unknown> + +rcwsclral x0, x1, [x4] +// CHECK-INST: rcwsclral x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xe0,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78e09081 <unknown> + +rcwsclrl x0, x1, [x4] +// CHECK-INST: rcwsclrl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x60,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78609081 <unknown> + +rcwsclr x3, x5, [sp] +// CHECK-INST: rcwsclr x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x23,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 782393e5 <unknown> + +rcwsclra x3, x5, [sp] +// CHECK-INST: rcwsclra x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xa3,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78a393e5 <unknown> + +rcwsclral x3, x5, [sp] +// CHECK-INST: rcwsclral x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xe3,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78e393e5 <unknown> + +rcwsclrl x3, x5, [sp] +// CHECK-INST: rcwsclrl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x63,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 786393e5 <unknown> + +rcwclrp x1, x0, [x4] +// CHECK-INST: rcwclrp x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x20,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19209081 <unknown> + +rcwclrpa x1, x0, [x4] +// CHECK-INST: rcwclrpa x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xa0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19a09081 <unknown> + +rcwclrpal x1, x0, [x4] +// CHECK-INST: rcwclrpal x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xe0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19e09081 <unknown> + +rcwclrpl x1, x0, [x4] +// CHECK-INST: rcwclrpl x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x60,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19609081 <unknown> + +rcwclrp x5, x3, [sp] +// CHECK-INST: rcwclrp x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x23,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 192393e5 <unknown> + +rcwclrpa x5, x3, [sp] +// CHECK-INST: rcwclrpa x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xa3,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19a393e5 <unknown> + +rcwclrpal x5, x3, [sp] +// CHECK-INST: rcwclrpal x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xe3,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19e393e5 <unknown> + +rcwclrpl x5, x3, [sp] +// CHECK-INST: rcwclrpl x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x63,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 196393e5 <unknown> + +rcwsclrp x1, x0, [x4] +// CHECK-INST: rcwsclrp x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x20,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59209081 <unknown> + +rcwsclrpa x1, x0, [x4] +// CHECK-INST: rcwsclrpa x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xa0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59a09081 <unknown> + +rcwsclrpal x1, x0, [x4] +// CHECK-INST: rcwsclrpal x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0xe0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59e09081 <unknown> + +rcwsclrpl x1, x0, [x4] +// CHECK-INST: rcwsclrpl x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0x90,0x60,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59609081 <unknown> + +rcwsclrp x5, x3, [sp] +// CHECK-INST: rcwsclrp x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x23,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 592393e5 <unknown> + +rcwsclrpa x5, x3, [sp] +// CHECK-INST: rcwsclrpa x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xa3,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59a393e5 <unknown> + +rcwsclrpal x5, x3, [sp] +// CHECK-INST: rcwsclrpal x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0xe3,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59e393e5 <unknown> + +rcwsclrpl x5, x3, [sp] +// CHECK-INST: rcwsclrpl x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0x93,0x63,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 596393e5 <unknown> + +rcwset x0, x1, [x4] +// CHECK-INST: rcwset x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x20,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3820b081 <unknown> + +rcwseta x0, x1, [x4] +// CHECK-INST: rcwseta x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xa0,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38a0b081 <unknown> + +rcwsetal x0, x1, [x4] +// CHECK-INST: rcwsetal x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xe0,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38e0b081 <unknown> + +rcwsetl x0, x1, [x4] +// CHECK-INST: rcwsetl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x60,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3860b081 <unknown> + +rcwset x3, x5, [sp] +// CHECK-INST: rcwset x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x23,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3823b3e5 <unknown> + +rcwseta x3, x5, [sp] +// CHECK-INST: rcwseta x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xa3,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38a3b3e5 <unknown> + +rcwsetal x3, x5, [sp] +// CHECK-INST: rcwsetal x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xe3,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38e3b3e5 <unknown> + +rcwsetl x3, x5, [sp] +// CHECK-INST: rcwsetl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x63,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3863b3e5 <unknown> + +rcwsset x0, x1, [x4] +// CHECK-INST: rcwsset x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x20,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7820b081 <unknown> + +rcwsseta x0, x1, [x4] +// CHECK-INST: rcwsseta x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xa0,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78a0b081 <unknown> + +rcwssetal x0, x1, [x4] +// CHECK-INST: rcwssetal x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xe0,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78e0b081 <unknown> + +rcwssetl x0, x1, [x4] +// CHECK-INST: rcwssetl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x60,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7860b081 <unknown> + +rcwsset x3, x5, [sp] +// CHECK-INST: rcwsset x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x23,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7823b3e5 <unknown> + +rcwsseta x3, x5, [sp] +// CHECK-INST: rcwsseta x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xa3,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78a3b3e5 <unknown> + +rcwssetal x3, x5, [sp] +// CHECK-INST: rcwssetal x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xe3,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78e3b3e5 <unknown> + +rcwssetl x3, x5, [sp] +// CHECK-INST: rcwssetl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x63,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7863b3e5 <unknown> + +rcwsetp x1, x0, [x4] +// CHECK-INST: rcwsetp x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x20,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 1920b081 <unknown> + +rcwsetpa x1, x0, [x4] +// CHECK-INST: rcwsetpa x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xa0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19a0b081 <unknown> + +rcwsetpal x1, x0, [x4] +// CHECK-INST: rcwsetpal x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xe0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19e0b081 <unknown> + +rcwsetpl x1, x0, [x4] +// CHECK-INST: rcwsetpl x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x60,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 1960b081 <unknown> + +rcwsetp x5, x3, [sp] +// CHECK-INST: rcwsetp x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x23,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 1923b3e5 <unknown> + +rcwsetpa x5, x3, [sp] +// CHECK-INST: rcwsetpa x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xa3,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19a3b3e5 <unknown> + +rcwsetpal x5, x3, [sp] +// CHECK-INST: rcwsetpal x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xe3,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 19e3b3e5 <unknown> + +rcwsetpl x5, x3, [sp] +// CHECK-INST: rcwsetpl x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x63,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 1963b3e5 <unknown> + +rcwssetp x1, x0, [x4] +// CHECK-INST: rcwssetp x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x20,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 5920b081 <unknown> + +rcwssetpa x1, x0, [x4] +// CHECK-INST: rcwssetpa x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xa0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 59a0b081 <unknown> + +rcwssetpal x1, x0, [x4] +// CHECK-INST: rcwssetpal x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0xe0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 59e0b081 <unknown> + +rcwssetpl x1, x0, [x4] +// CHECK-INST: rcwssetpl x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xb0,0x60,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 5960b081 <unknown> + +rcwssetp x5, x3, [sp] +// CHECK-INST: rcwssetp x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x23,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 5923b3e5 <unknown> + +rcwssetpa x5, x3, [sp] +// CHECK-INST: rcwssetpa x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xa3,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 59a3b3e5 <unknown> + +rcwssetpal x5, x3, [sp] +// CHECK-INST: rcwssetpal x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0xe3,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 59e3b3e5 <unknown> + +rcwssetpl x5, x3, [sp] +// CHECK-INST: rcwssetpl x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xb3,0x63,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// ERROR-NO-D128: error: instruction requires: d128 +// CHECK-UNKNOWN: 5963b3e5 <unknown> + +rcwswp x0, x1, [x4] +// CHECK-INST: rcwswp x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x20,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3820a081 <unknown> + +rcwswpa x0, x1, [x4] +// CHECK-INST: rcwswpa x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xa0,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38a0a081 <unknown> + +rcwswpal x0, x1, [x4] +// CHECK-INST: rcwswpal x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xe0,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38e0a081 <unknown> + +rcwswpl x0, x1, [x4] +// CHECK-INST: rcwswpl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x60,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3860a081 <unknown> + +rcwswp x3, x5, [sp] +// CHECK-INST: rcwswp x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x23,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3823a3e5 <unknown> + +rcwswpa x3, x5, [sp] +// CHECK-INST: rcwswpa x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xa3,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38a3a3e5 <unknown> + +rcwswpal x3, x5, [sp] +// CHECK-INST: rcwswpal x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xe3,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 38e3a3e5 <unknown> + +rcwswpl x3, x5, [sp] +// CHECK-INST: rcwswpl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x63,0x38] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 3863a3e5 <unknown> + +rcwsswp x0, x1, [x4] +// CHECK-INST: rcwsswp x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x20,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7820a081 <unknown> + +rcwsswpa x0, x1, [x4] +// CHECK-INST: rcwsswpa x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xa0,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78a0a081 <unknown> + +rcwsswpal x0, x1, [x4] +// CHECK-INST: rcwsswpal x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xe0,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78e0a081 <unknown> + +rcwsswpl x0, x1, [x4] +// CHECK-INST: rcwsswpl x0, x1, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x60,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7860a081 <unknown> + +rcwsswp x3, x5, [sp] +// CHECK-INST: rcwsswp x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x23,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7823a3e5 <unknown> + +rcwsswpa x3, x5, [sp] +// CHECK-INST: rcwsswpa x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xa3,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78a3a3e5 <unknown> + +rcwsswpal x3, x5, [sp] +// CHECK-INST: rcwsswpal x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xe3,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 78e3a3e5 <unknown> + +rcwsswpl x3, x5, [sp] +// CHECK-INST: rcwsswpl x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x63,0x78] +// CHECK-ERROR: error: instruction requires: the +// CHECK-UNKNOWN: 7863a3e5 <unknown> + +rcwswpp x1, x0, [x4] +// CHECK-INST: rcwswpp x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x20,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 1920a081 <unknown> + +rcwswppa x1, x0, [x4] +// CHECK-INST: rcwswppa x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xa0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 19a0a081 <unknown> + +rcwswppal x1, x0, [x4] +// CHECK-INST: rcwswppal x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xe0,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 19e0a081 <unknown> + +rcwswppl x1, x0, [x4] +// CHECK-INST: rcwswppl x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x60,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 1960a081 <unknown> + +rcwswpp x5, x3, [sp] +// CHECK-INST: rcwswpp x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x23,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 1923a3e5 <unknown> + +rcwswppa x5, x3, [sp] +// CHECK-INST: rcwswppa x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xa3,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 19a3a3e5 <unknown> + +rcwswppal x5, x3, [sp] +// CHECK-INST: rcwswppal x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xe3,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 19e3a3e5 <unknown> + +rcwswppl x5, x3, [sp] +// CHECK-INST: rcwswppl x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x63,0x19] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 1963a3e5 <unknown> + +rcwsswpp x1, x0, [x4] +// CHECK-INST: rcwsswpp x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x20,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 5920a081 <unknown> + +rcwsswppa x1, x0, [x4] +// CHECK-INST: rcwsswppa x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xa0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59a0a081 <unknown> + +rcwsswppal x1, x0, [x4] +// CHECK-INST: rcwsswppal x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0xe0,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59e0a081 <unknown> + +rcwsswppl x1, x0, [x4] +// CHECK-INST: rcwsswppl x1, x0, [x4] +// CHECK-ENCODING: encoding: [0x81,0xa0,0x60,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 5960a081 <unknown> + +rcwsswpp x5, x3, [sp] +// CHECK-INST: rcwsswpp x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x23,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 5923a3e5 <unknown> + +rcwsswppa x5, x3, [sp] +// CHECK-INST: rcwsswppa x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xa3,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59a3a3e5 <unknown> + +rcwsswppal x5, x3, [sp] +// CHECK-INST: rcwsswppal x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0xe3,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 59e3a3e5 <unknown> + +rcwsswppl x5, x3, [sp] +// CHECK-INST: rcwsswppl x5, x3, [sp] +// CHECK-ENCODING: encoding: [0xe5,0xa3,0x63,0x59] +// CHECK-ERROR: error: instruction requires: d128 the +// CHECK-UNKNOWN: 5963a3e5 <unknown> diff --git a/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s b/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s new file mode 100644 index 000000000000..4eb886178465 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9-mrrs-diagnostics.s @@ -0,0 +1,30 @@ +// +the required for RCWSMASK_EL1, RCWMASK_EL1 +// +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2 +// +vh required for TTBR1_EL2 + +// RUN: not llvm-mc -triple=aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR + +mrrs x0, x2, TTBR0_EL1 +// CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair + +mrrs x0, TTBR0_EL1 +// CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair + +mrrs x1, x2, TTBR0_EL1 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +mrrs x31, x0, TTBR0_EL1 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +mrrs xzr, x30, TTBR0_EL1 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +mrrs xzr, TTBR0_EL1 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +mrrs S3_0_c2_c0_1 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +mrrs S3_0_c2_c0_1, x0, x1 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair diff --git a/llvm/test/MC/AArch64/armv9-mrrs.s b/llvm/test/MC/AArch64/armv9-mrrs.s index 870127826cb1..1fc7274f64d4 100644 --- a/llvm/test/MC/AArch64/armv9-mrrs.s +++ b/llvm/test/MC/AArch64/armv9-mrrs.s @@ -1,100 +1,282 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | llvm-objdump -d --mattr=+d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | llvm-objdump -d --mattr=-d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+the,+el2vmsa,+vh -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + // +the required for RCWSMASK_EL1, RCWMASK_EL1 // +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2 // +vh required for TTBR1_EL2 -// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding %s -o - 2> %t | FileCheck %s -// RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS - -// RUN: not llvm-mc -triple aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 - - mrrs x0, x1, TTBR0_EL1 -// CHECK: mrrs x0, x1, TTBR0_EL1 // encoding: [0x00,0x20,0x78,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x0, x1, TTBR1_EL1 -// CHECK: mrrs x0, x1, TTBR1_EL1 // encoding: [0x20,0x20,0x78,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x0, x1, PAR_EL1 -// CHECK: mrrs x0, x1, PAR_EL1 // encoding: [0x00,0x74,0x78,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x0, x1, RCWSMASK_EL1 -// CHECK: mrrs x0, x1, RCWSMASK_EL1 // encoding: [0x60,0xd0,0x78,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x0, x1, RCWMASK_EL1 -// CHECK: mrrs x0, x1, RCWMASK_EL1 // encoding: [0xc0,0xd0,0x78,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x0, x1, TTBR0_EL2 -// CHECK: mrrs x0, x1, TTBR0_EL2 // encoding: [0x00,0x20,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x0, x1, TTBR1_EL2 -// CHECK: mrrs x0, x1, TTBR1_EL2 // encoding: [0x20,0x20,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x0, x1, VTTBR_EL2 -// CHECK: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - mrrs x0, x1, VTTBR_EL2 -// CHECK: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x2, x3, VTTBR_EL2 -// CHECK: mrrs x2, x3, VTTBR_EL2 // encoding: [0x02,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x4, x5, VTTBR_EL2 -// CHECK: mrrs x4, x5, VTTBR_EL2 // encoding: [0x04,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x6, x7, VTTBR_EL2 -// CHECK: mrrs x6, x7, VTTBR_EL2 // encoding: [0x06,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x8, x9, VTTBR_EL2 -// CHECK: mrrs x8, x9, VTTBR_EL2 // encoding: [0x08,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x10, x11, VTTBR_EL2 -// CHECK: mrrs x10, x11, VTTBR_EL2 // encoding: [0x0a,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x12, x13, VTTBR_EL2 -// CHECK: mrrs x12, x13, VTTBR_EL2 // encoding: [0x0c,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x14, x15, VTTBR_EL2 -// CHECK: mrrs x14, x15, VTTBR_EL2 // encoding: [0x0e,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x16, x17, VTTBR_EL2 -// CHECK: mrrs x16, x17, VTTBR_EL2 // encoding: [0x10,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x18, x19, VTTBR_EL2 -// CHECK: mrrs x18, x19, VTTBR_EL2 // encoding: [0x12,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x20, x21, VTTBR_EL2 -// CHECK: mrrs x20, x21, VTTBR_EL2 // encoding: [0x14,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x22, x23, VTTBR_EL2 -// CHECK: mrrs x22, x23, VTTBR_EL2 // encoding: [0x16,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x24, x25, VTTBR_EL2 -// CHECK: mrrs x24, x25, VTTBR_EL2 // encoding: [0x18,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - mrrs x26, x27, VTTBR_EL2 -// CHECK: mrrs x26, x27, VTTBR_EL2 // encoding: [0x1a,0x21,0x7c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - mrrs x0, x2, TTBR0_EL1 -// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair - - mrrs x0, TTBR0_EL1 -// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair - - mrrs x1, x2, TTBR0_EL1 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - mrrs x31, x0, TTBR0_EL1 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - mrrs xzr, x30, TTBR0_EL1 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - mrrs xzr, TTBR0_EL1 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - mrrs S3_0_c2_c0_1 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - mrrs S3_0_c2_c0_1, x0, x1 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair +mrrs x0, x1, TTBR0_EL1 +// CHECK-INST: mrrs x0, x1, TTBR0_EL1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x78,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5782000 <unknown> + +mrrs x0, x1, TTBR1_EL1 +// CHECK-INST: mrrs x0, x1, TTBR1_EL1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x78,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5782020 <unknown> + +mrrs x0, x1, PAR_EL1 +// CHECK-INST: mrrs x0, x1, PAR_EL1 +// CHECK-ENCODING: encoding: [0x00,0x74,0x78,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5787400 <unknown> + +mrrs x0, x1, RCWSMASK_EL1 +// CHECK-INST: mrrs x0, x1, RCWSMASK_EL1 +// CHECK-ENCODING: encoding: [0x60,0xd0,0x78,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d578d060 <unknown> + +mrrs x0, x1, RCWMASK_EL1 +// CHECK-INST: mrrs x0, x1, RCWMASK_EL1 +// CHECK-ENCODING: encoding: [0xc0,0xd0,0x78,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d578d0c0 <unknown> + +mrrs x0, x1, TTBR0_EL2 +// CHECK-INST: mrrs x0, x1, TTBR0_EL2 +// CHECK-ENCODING: encoding: [0x00,0x20,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2000 <unknown> + +mrrs x0, x1, TTBR1_EL2 +// CHECK-INST: mrrs x0, x1, TTBR1_EL2 +// CHECK-ENCODING: encoding: [0x20,0x20,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2020 <unknown> + +mrrs x0, x1, VTTBR_EL2 +// CHECK-INST: mrrs x0, x1, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x00,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2100 <unknown> + +mrrs x0, x1, VTTBR_EL2 +// CHECK-INST: mrrs x0, x1, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x00,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2100 <unknown> + +mrrs x2, x3, VTTBR_EL2 +// CHECK-INST: mrrs x2, x3, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x02,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2102 <unknown> + +mrrs x4, x5, VTTBR_EL2 +// CHECK-INST: mrrs x4, x5, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x04,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2104 <unknown> + +mrrs x6, x7, VTTBR_EL2 +// CHECK-INST: mrrs x6, x7, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x06,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2106 <unknown> + +mrrs x8, x9, VTTBR_EL2 +// CHECK-INST: mrrs x8, x9, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x08,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2108 <unknown> + +mrrs x10, x11, VTTBR_EL2 +// CHECK-INST: mrrs x10, x11, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x0a,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c210a <unknown> + +mrrs x12, x13, VTTBR_EL2 +// CHECK-INST: mrrs x12, x13, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x0c,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c210c <unknown> + +mrrs x14, x15, VTTBR_EL2 +// CHECK-INST: mrrs x14, x15, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x0e,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c210e <unknown> + +mrrs x16, x17, VTTBR_EL2 +// CHECK-INST: mrrs x16, x17, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x10,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2110 <unknown> + +mrrs x18, x19, VTTBR_EL2 +// CHECK-INST: mrrs x18, x19, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x12,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2112 <unknown> + +mrrs x20, x21, VTTBR_EL2 +// CHECK-INST: mrrs x20, x21, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x14,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2114 <unknown> + +mrrs x22, x23, VTTBR_EL2 +// CHECK-INST: mrrs x22, x23, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x16,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2116 <unknown> + +mrrs x24, x25, VTTBR_EL2 +// CHECK-INST: mrrs x24, x25, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x18,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c2118 <unknown> + +mrrs x26, x27, VTTBR_EL2 +// CHECK-INST: mrrs x26, x27, VTTBR_EL2 +// CHECK-ENCODING: encoding: [0x1a,0x21,0x7c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d57c211a <unknown> + +msrr TTBR0_EL1, x0, x1 +// CHECK-INST: msrr TTBR0_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d5582000 <unknown> + +msrr TTBR1_EL1, x0, x1 +// CHECK-INST: msrr TTBR1_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d5582020 <unknown> + +msrr PAR_EL1, x0, x1 +// CHECK-INST: msrr PAR_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x74,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d5587400 <unknown> + +msrr RCWSMASK_EL1, x0, x1 +// CHECK-INST: msrr RCWSMASK_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0xd0,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d558d060 <unknown> + +msrr RCWMASK_EL1, x0, x1 +// CHECK-INST: msrr RCWMASK_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0xc0,0xd0,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d558d0c0 <unknown> + +msrr TTBR0_EL2, x0, x1 +// CHECK-INST: msrr TTBR0_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2000 <unknown> + +msrr TTBR1_EL2, x0, x1 +// CHECK-INST: msrr TTBR1_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2020 <unknown> + +msrr VTTBR_EL2, x0, x1 +// CHECK-INST: msrr VTTBR_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2100 <unknown> + +msrr VTTBR_EL2, x0, x1 +// CHECK-INST: msrr VTTBR_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2100 <unknown> + +msrr VTTBR_EL2, x2, x3 +// CHECK-INST: msrr VTTBR_EL2, x2, x3 +// CHECK-ENCODING: encoding: [0x02,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2102 <unknown> + +msrr VTTBR_EL2, x4, x5 +// CHECK-INST: msrr VTTBR_EL2, x4, x5 +// CHECK-ENCODING: encoding: [0x04,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2104 <unknown> + +msrr VTTBR_EL2, x6, x7 +// CHECK-INST: msrr VTTBR_EL2, x6, x7 +// CHECK-ENCODING: encoding: [0x06,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2106 <unknown> + +msrr VTTBR_EL2, x8, x9 +// CHECK-INST: msrr VTTBR_EL2, x8, x9 +// CHECK-ENCODING: encoding: [0x08,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2108 <unknown> + +msrr VTTBR_EL2, x10, x11 +// CHECK-INST: msrr VTTBR_EL2, x10, x11 +// CHECK-ENCODING: encoding: [0x0a,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c210a <unknown> + +msrr VTTBR_EL2, x12, x13 +// CHECK-INST: msrr VTTBR_EL2, x12, x13 +// CHECK-ENCODING: encoding: [0x0c,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c210c <unknown> + +msrr VTTBR_EL2, x14, x15 +// CHECK-INST: msrr VTTBR_EL2, x14, x15 +// CHECK-ENCODING: encoding: [0x0e,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c210e <unknown> + +msrr VTTBR_EL2, x16, x17 +// CHECK-INST: msrr VTTBR_EL2, x16, x17 +// CHECK-ENCODING: encoding: [0x10,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2110 <unknown> + +msrr VTTBR_EL2, x18, x19 +// CHECK-INST: msrr VTTBR_EL2, x18, x19 +// CHECK-ENCODING: encoding: [0x12,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2112 <unknown> + +msrr VTTBR_EL2, x20, x21 +// CHECK-INST: msrr VTTBR_EL2, x20, x21 +// CHECK-ENCODING: encoding: [0x14,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2114 <unknown> + +msrr VTTBR_EL2, x22, x23 +// CHECK-INST: msrr VTTBR_EL2, x22, x23 +// CHECK-ENCODING: encoding: [0x16,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2116 <unknown> + +msrr VTTBR_EL2, x24, x25 +// CHECK-INST: msrr VTTBR_EL2, x24, x25 +// CHECK-ENCODING: encoding: [0x18,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2118 <unknown> + +msrr VTTBR_EL2, x26, x27 +// CHECK-INST: msrr VTTBR_EL2, x26, x27 +// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c211a <unknown> diff --git a/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s b/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s new file mode 100644 index 000000000000..d49a3ee68b63 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9-msrr-diagnostics.s @@ -0,0 +1,30 @@ +// +the required for RCWSMASK_EL1, RCWMASK_EL1 +// +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2 +// +vh required for TTBR1_EL2 + +// RUN: not llvm-mc -triple=aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR + +msrr TTBR0_EL1, x0, x2 +// CHECK-ERROR: error: expected second odd register of a consecutive same-size even/odd register pair + +msrr TTBR0_EL1, x0 +// CHECK-ERROR: error: expected comma + +msrr TTBR0_EL1, x1, x2 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +msrr TTBR0_EL1, x31, x0 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +msrr TTBR0_EL1, xzr, x30 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +msrr TTBR0_EL1, xzr +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair + +msrr S3_0_c2_c0_1 +// CHECK-ERROR: error: too few operands for instruction + +msrr x0, x1, S3_0_c2_c0_1 +// CHECK-ERROR: error: expected first even register of a consecutive same-size even/odd register pair diff --git a/llvm/test/MC/AArch64/armv9-msrr.s b/llvm/test/MC/AArch64/armv9-msrr.s index 2be17a71e7d4..439e054779b0 100644 --- a/llvm/test/MC/AArch64/armv9-msrr.s +++ b/llvm/test/MC/AArch64/armv9-msrr.s @@ -1,100 +1,150 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | llvm-objdump -d --mattr=+d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | llvm-objdump -d --mattr=-d128,+the,+el2vmsa,+vh - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+the,+el2vmsa,+vh < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+the,+el2vmsa,+vh -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + // +the required for RCWSMASK_EL1, RCWMASK_EL1 // +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2 // +vh required for TTBR1_EL2 -// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding %s -o - 2> %t | FileCheck %s -// RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS - -// RUN: not llvm-mc -triple aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 - - msrr TTBR0_EL1, x0, x1 -// CHECK: msrr TTBR0_EL1, x0, x1 // encoding: [0x00,0x20,0x58,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr TTBR1_EL1, x0, x1 -// CHECK: msrr TTBR1_EL1, x0, x1 // encoding: [0x20,0x20,0x58,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr PAR_EL1, x0, x1 -// CHECK: msrr PAR_EL1, x0, x1 // encoding: [0x00,0x74,0x58,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr RCWSMASK_EL1, x0, x1 -// CHECK: msrr RCWSMASK_EL1, x0, x1 // encoding: [0x60,0xd0,0x58,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr RCWMASK_EL1, x0, x1 -// CHECK: msrr RCWMASK_EL1, x0, x1 // encoding: [0xc0,0xd0,0x58,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr TTBR0_EL2, x0, x1 -// CHECK: msrr TTBR0_EL2, x0, x1 // encoding: [0x00,0x20,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr TTBR1_EL2, x0, x1 -// CHECK: msrr TTBR1_EL2, x0, x1 // encoding: [0x20,0x20,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x0, x1 -// CHECK: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - msrr VTTBR_EL2, x0, x1 -// CHECK: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x2, x3 -// CHECK: msrr VTTBR_EL2, x2, x3 // encoding: [0x02,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x4, x5 -// CHECK: msrr VTTBR_EL2, x4, x5 // encoding: [0x04,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x6, x7 -// CHECK: msrr VTTBR_EL2, x6, x7 // encoding: [0x06,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x8, x9 -// CHECK: msrr VTTBR_EL2, x8, x9 // encoding: [0x08,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x10, x11 -// CHECK: msrr VTTBR_EL2, x10, x11 // encoding: [0x0a,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x12, x13 -// CHECK: msrr VTTBR_EL2, x12, x13 // encoding: [0x0c,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x14, x15 -// CHECK: msrr VTTBR_EL2, x14, x15 // encoding: [0x0e,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x16, x17 -// CHECK: msrr VTTBR_EL2, x16, x17 // encoding: [0x10,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x18, x19 -// CHECK: msrr VTTBR_EL2, x18, x19 // encoding: [0x12,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x20, x21 -// CHECK: msrr VTTBR_EL2, x20, x21 // encoding: [0x14,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x22, x23 -// CHECK: msrr VTTBR_EL2, x22, x23 // encoding: [0x16,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x24, x25 -// CHECK: msrr VTTBR_EL2, x24, x25 // encoding: [0x18,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - msrr VTTBR_EL2, x26, x27 -// CHECK: msrr VTTBR_EL2, x26, x27 // encoding: [0x1a,0x21,0x5c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - msrr TTBR0_EL1, x0, x2 -// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair - - msrr TTBR0_EL1, x0 -// ERRORS: error: expected comma - - msrr TTBR0_EL1, x1, x2 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - msrr TTBR0_EL1, x31, x0 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - msrr TTBR0_EL1, xzr, x30 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - msrr TTBR0_EL1, xzr -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - msrr S3_0_c2_c0_1 -// ERRORS: error: too few operands for instruction - - msrr x0, x1, S3_0_c2_c0_1 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair +msrr TTBR0_EL1, x0, x1 +// CHECK-INST: msrr TTBR0_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d5582000 <unknown> + +msrr TTBR1_EL1, x0, x1 +// CHECK-INST: msrr TTBR1_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d5582020 <unknown> + +msrr PAR_EL1, x0, x1 +// CHECK-INST: msrr PAR_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x74,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d5587400 <unknown> + +msrr RCWSMASK_EL1, x0, x1 +// CHECK-INST: msrr RCWSMASK_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0xd0,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d558d060 <unknown> + +msrr RCWMASK_EL1, x0, x1 +// CHECK-INST: msrr RCWMASK_EL1, x0, x1 +// CHECK-ENCODING: encoding: [0xc0,0xd0,0x58,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d558d0c0 <unknown> + +msrr TTBR0_EL2, x0, x1 +// CHECK-INST: msrr TTBR0_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2000 <unknown> + +msrr TTBR1_EL2, x0, x1 +// CHECK-INST: msrr TTBR1_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2020 <unknown> + +msrr VTTBR_EL2, x0, x1 +// CHECK-INST: msrr VTTBR_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2100 <unknown> + +msrr VTTBR_EL2, x0, x1 +// CHECK-INST: msrr VTTBR_EL2, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2100 <unknown> + +msrr VTTBR_EL2, x2, x3 +// CHECK-INST: msrr VTTBR_EL2, x2, x3 +// CHECK-ENCODING: encoding: [0x02,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2102 <unknown> + +msrr VTTBR_EL2, x4, x5 +// CHECK-INST: msrr VTTBR_EL2, x4, x5 +// CHECK-ENCODING: encoding: [0x04,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2104 <unknown> + +msrr VTTBR_EL2, x6, x7 +// CHECK-INST: msrr VTTBR_EL2, x6, x7 +// CHECK-ENCODING: encoding: [0x06,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2106 <unknown> + +msrr VTTBR_EL2, x8, x9 +// CHECK-INST: msrr VTTBR_EL2, x8, x9 +// CHECK-ENCODING: encoding: [0x08,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2108 <unknown> + +msrr VTTBR_EL2, x10, x11 +// CHECK-INST: msrr VTTBR_EL2, x10, x11 +// CHECK-ENCODING: encoding: [0x0a,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c210a <unknown> + +msrr VTTBR_EL2, x12, x13 +// CHECK-INST: msrr VTTBR_EL2, x12, x13 +// CHECK-ENCODING: encoding: [0x0c,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c210c <unknown> + +msrr VTTBR_EL2, x14, x15 +// CHECK-INST: msrr VTTBR_EL2, x14, x15 +// CHECK-ENCODING: encoding: [0x0e,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c210e <unknown> + +msrr VTTBR_EL2, x16, x17 +// CHECK-INST: msrr VTTBR_EL2, x16, x17 +// CHECK-ENCODING: encoding: [0x10,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2110 <unknown> + +msrr VTTBR_EL2, x18, x19 +// CHECK-INST: msrr VTTBR_EL2, x18, x19 +// CHECK-ENCODING: encoding: [0x12,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2112 <unknown> + +msrr VTTBR_EL2, x20, x21 +// CHECK-INST: msrr VTTBR_EL2, x20, x21 +// CHECK-ENCODING: encoding: [0x14,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2114 <unknown> + +msrr VTTBR_EL2, x22, x23 +// CHECK-INST: msrr VTTBR_EL2, x22, x23 +// CHECK-ENCODING: encoding: [0x16,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2116 <unknown> + +msrr VTTBR_EL2, x24, x25 +// CHECK-INST: msrr VTTBR_EL2, x24, x25 +// CHECK-ENCODING: encoding: [0x18,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c2118 <unknown> + +msrr VTTBR_EL2, x26, x27 +// CHECK-INST: msrr VTTBR_EL2, x26, x27 +// CHECK-ENCODING: encoding: [0x1a,0x21,0x5c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: d128 +// CHECK-UNKNOWN: d55c211a <unknown> diff --git a/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s b/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s new file mode 100644 index 000000000000..8b466c10b0aa --- /dev/null +++ b/llvm/test/MC/AArch64/armv9-sysp-diagnostics.s @@ -0,0 +1,35 @@ +// +tbl-rmi required for RIPA*/RVA* +// +xs required for *NXS + +// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+tlb-rmi,+xs -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERRORS + +// sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} +// registers with 128-bit formats (op0, op1, Cn, Cm, op2) +// For sysp, op0 is 0 + +sysp #0, c2, c0, #0, x0, x2 +// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair +sysp #0, c2, c0, #0, x0 +// ERRORS: error: expected comma +sysp #0, c2, c0, #0, x1, x2 +// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair +sysp #0, c2, c0, #0, x31, x0 +// ERRORS: error: xzr must be followed by xzr +sysp #0, c2, c0, #0, xzr, x30 +// ERRORS: error: xzr must be followed by xzr +sysp #0, c2, c0, #0, xzr +// ERRORS: error: expected comma +sysp #0, c2, c0, #0, xzr, +// ERRORS: error: expected register operand + + +tlbip RVAE3IS +// ERRORS: error: expected comma +tlbip RVAE3IS, +// ERRORS: error: expected register identifier +tlbip VAE3, +// ERRORS: error: expected register identifier +tlbip IPAS2E1, x4, x8 +// ERRORS: error: specified tlbip op requires a pair of registers +tlbip RVAE3, x11, x11 +// ERRORS: error: specified tlbip op requires a pair of registers diff --git a/llvm/test/MC/AArch64/armv9-sysp.s b/llvm/test/MC/AArch64/armv9-sysp.s deleted file mode 100644 index 908e880ad0aa..000000000000 --- a/llvm/test/MC/AArch64/armv9-sysp.s +++ /dev/null @@ -1,538 +0,0 @@ -// +tbl-rmi required for RIPA*/RVA* -// +xs required for *NXS - -// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+tlb-rmi,+xs -show-encoding %s -o - 2> %t | FileCheck %s -// RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS - -// RUN: not llvm-mc -triple aarch64 -mattr=+tlb-rmi,+xs -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 - -// sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} -// registers with 128-bit formats (op0, op1, Cn, Cm, op2) -// For sysp, op0 is 0 - - sysp #0, c2, c0, #0, x0, x1 // TTBR0_EL1 3 0 2 0 0 -// CHECK: sysp #0, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #1, x0, x1 // TTBR1_EL1 3 0 2 0 1 -// CHECK: sysp #0, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c7, c4, #0, x0, x1 // PAR_EL1 3 0 7 4 0 -// CHECK: sysp #0, c7, c4, #0, x0, x1 // encoding: [0x00,0x74,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c13, c0, #3, x0, x1 // RCWSMASK_EL1 3 0 13 0 3 -// CHECK: sysp #0, c13, c0, #3, x0, x1 // encoding: [0x60,0xd0,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c13, c0, #6, x0, x1 // RCWMASK_EL1 3 0 13 0 6 -// CHECK: sysp #0, c13, c0, #6, x0, x1 // encoding: [0xc0,0xd0,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #4, c2, c0, #0, x0, x1 // TTBR0_EL2 3 4 2 0 0 -// CHECK: sysp #4, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #4, c2, c0, #1, x0, x1 // TTBR1_EL2 3 4 2 0 1 -// CHECK: sysp #4, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #4, c2, c1, #0, x0, x1 // VTTBR_EL2 3 4 2 1 0 -// CHECK: sysp #4, c2, c1, #0, x0, x1 // encoding: [0x00,0x21,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - - sysp #0, c2, c0, #0, x0, x1 -// CHECK: sysp #0, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #1, x0, x1 -// CHECK: sysp #0, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c7, c4, #0, x0, x1 -// CHECK: sysp #0, c7, c4, #0, x0, x1 // encoding: [0x00,0x74,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c13, c0, #3, x0, x1 -// CHECK: sysp #0, c13, c0, #3, x0, x1 // encoding: [0x60,0xd0,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c13, c0, #6, x0, x1 -// CHECK: sysp #0, c13, c0, #6, x0, x1 // encoding: [0xc0,0xd0,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #4, c2, c0, #0, x0, x1 -// CHECK: sysp #4, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #4, c2, c0, #1, x0, x1 -// CHECK: sysp #4, c2, c0, #1, x0, x1 // encoding: [0x20,0x20,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #4, c2, c1, #0, x0, x1 -// CHECK: sysp #4, c2, c1, #0, x0, x1 // encoding: [0x00,0x21,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - sysp #0, c2, c0, #0, x0, x1 -// CHECK: sysp #0, c2, c0, #0, x0, x1 // encoding: [0x00,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x2, x3 -// CHECK: sysp #0, c2, c0, #0, x2, x3 // encoding: [0x02,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x4, x5 -// CHECK: sysp #0, c2, c0, #0, x4, x5 // encoding: [0x04,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x6, x7 -// CHECK: sysp #0, c2, c0, #0, x6, x7 // encoding: [0x06,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x8, x9 -// CHECK: sysp #0, c2, c0, #0, x8, x9 // encoding: [0x08,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x10, x11 -// CHECK: sysp #0, c2, c0, #0, x10, x11 // encoding: [0x0a,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x12, x13 -// CHECK: sysp #0, c2, c0, #0, x12, x13 // encoding: [0x0c,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x14, x15 -// CHECK: sysp #0, c2, c0, #0, x14, x15 // encoding: [0x0e,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x16, x17 -// CHECK: sysp #0, c2, c0, #0, x16, x17 // encoding: [0x10,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x18, x19 -// CHECK: sysp #0, c2, c0, #0, x18, x19 // encoding: [0x12,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x20, x21 -// CHECK: sysp #0, c2, c0, #0, x20, x21 // encoding: [0x14,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x22, x23 -// CHECK: sysp #0, c2, c0, #0, x22, x23 // encoding: [0x16,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x24, x25 -// CHECK: sysp #0, c2, c0, #0, x24, x25 // encoding: [0x18,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x26, x27 -// CHECK: sysp #0, c2, c0, #0, x26, x27 // encoding: [0x1a,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x28, x29 -// CHECK: sysp #0, c2, c0, #0, x28, x29 // encoding: [0x1c,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x30, x31 -// CHECK: sysp #0, c2, c0, #0, x30, xzr // encoding: [0x1e,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - sysp #0, c2, c0, #0, x31, x31 -// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, xzr, xzr -// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, x31, xzr -// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0, xzr, x31 -// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - sysp #0, c2, c0, #0 -// CHECK: sysp #0, c2, c0, #0 // encoding: [0x1f,0x20,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - - sysp #0, c2, c0, #0, x0, x2 -// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair - - sysp #0, c2, c0, #0, x0 -// ERRORS: error: expected comma - - sysp #0, c2, c0, #0, x1, x2 -// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair - - sysp #0, c2, c0, #0, x31, x0 -// ERRORS: error: xzr must be followed by xzr - - sysp #0, c2, c0, #0, xzr, x30 -// ERRORS: error: xzr must be followed by xzr - - sysp #0, c2, c0, #0, xzr -// ERRORS: error: expected comma - - sysp #0, c2, c0, #0, xzr, -// ERRORS: error: expected register operand - - - tlbip IPAS2E1, x4, x5 -// CHECK: tlbip ipas2e1, x4, x5 // encoding: [0x24,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2E1NXS, x4, x5 -// CHECK: tlbip ipas2e1nxs, x4, x5 // encoding: [0x24,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2E1IS, x4, x5 -// CHECK: tlbip ipas2e1is, x4, x5 // encoding: [0x24,0x80,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2E1ISNXS, x4, x5 -// CHECK: tlbip ipas2e1isnxs, x4, x5 // encoding: [0x24,0x90,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2E1OS, x4, x5 -// CHECK: tlbip ipas2e1os, x4, x5 // encoding: [0x04,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2E1OSNXS, x4, x5 -// CHECK: tlbip ipas2e1osnxs, x4, x5 // encoding: [0x04,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2LE1, x4, x5 -// CHECK: tlbip ipas2le1, x4, x5 // encoding: [0xa4,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2LE1NXS, x4, x5 -// CHECK: tlbip ipas2le1nxs, x4, x5 // encoding: [0xa4,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2LE1IS, x4, x5 -// CHECK: tlbip ipas2le1is, x4, x5 // encoding: [0xa4,0x80,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2LE1ISNXS, x4, x5 -// CHECK: tlbip ipas2le1isnxs, x4, x5 // encoding: [0xa4,0x90,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2LE1OS, x4, x5 -// CHECK: tlbip ipas2le1os, x4, x5 // encoding: [0x84,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip IPAS2LE1OSNXS, x4, x5 -// CHECK: tlbip ipas2le1osnxs, x4, x5 // encoding: [0x84,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - - tlbip VAE1, x8, x9 -// CHECK: tlbip vae1, x8, x9 // encoding: [0x28,0x87,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE1NXS, x8, x9 -// CHECK: tlbip vae1nxs, x8, x9 // encoding: [0x28,0x97,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE1IS, x8, x9 -// CHECK: tlbip vae1is, x8, x9 // encoding: [0x28,0x83,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE1ISNXS, x8, x9 -// CHECK: tlbip vae1isnxs, x8, x9 // encoding: [0x28,0x93,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE1OS, x8, x9 -// CHECK: tlbip vae1os, x8, x9 // encoding: [0x28,0x81,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE1OSNXS, x8, x9 -// CHECK: tlbip vae1osnxs, x8, x9 // encoding: [0x28,0x91,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE1, x8, x9 -// CHECK: tlbip vale1, x8, x9 // encoding: [0xa8,0x87,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE1NXS, x8, x9 -// CHECK: tlbip vale1nxs, x8, x9 // encoding: [0xa8,0x97,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE1IS, x8, x9 -// CHECK: tlbip vale1is, x8, x9 // encoding: [0xa8,0x83,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE1ISNXS, x8, x9 -// CHECK: tlbip vale1isnxs, x8, x9 // encoding: [0xa8,0x93,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE1OS, x8, x9 -// CHECK: tlbip vale1os, x8, x9 // encoding: [0xa8,0x81,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE1OSNXS, x8, x9 -// CHECK: tlbip vale1osnxs, x8, x9 // encoding: [0xa8,0x91,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAAE1, x8, x9 -// CHECK: tlbip vaae1, x8, x9 // encoding: [0x68,0x87,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAAE1NXS, x8, x9 -// CHECK: tlbip vaae1nxs, x8, x9 // encoding: [0x68,0x97,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAAE1IS, x8, x9 -// CHECK: tlbip vaae1is, x8, x9 // encoding: [0x68,0x83,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAAE1ISNXS, x8, x9 -// CHECK: tlbip vaae1isnxs, x8, x9 // encoding: [0x68,0x93,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAAE1OS, x8, x9 -// CHECK: tlbip vaae1os, x8, x9 // encoding: [0x68,0x81,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAAE1OSNXS, x8, x9 -// CHECK: tlbip vaae1osnxs, x8, x9 // encoding: [0x68,0x91,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAALE1, x8, x9 -// CHECK: tlbip vaale1, x8, x9 // encoding: [0xe8,0x87,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAALE1NXS, x8, x9 -// CHECK: tlbip vaale1nxs, x8, x9 // encoding: [0xe8,0x97,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAALE1IS, x8, x9 -// CHECK: tlbip vaale1is, x8, x9 // encoding: [0xe8,0x83,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAALE1ISNXS, x8, x9 -// CHECK: tlbip vaale1isnxs, x8, x9 // encoding: [0xe8,0x93,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAALE1OS, x8, x9 -// CHECK: tlbip vaale1os, x8, x9 // encoding: [0xe8,0x81,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAALE1OSNXS, x8, x9 -// CHECK: tlbip vaale1osnxs, x8, x9 // encoding: [0xe8,0x91,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - tlbip VAE2, x14, x15 -// CHECK: tlbip vae2, x14, x15 // encoding: [0x2e,0x87,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE2NXS, x14, x15 -// CHECK: tlbip vae2nxs, x14, x15 // encoding: [0x2e,0x97,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE2IS, x14, x15 -// CHECK: tlbip vae2is, x14, x15 // encoding: [0x2e,0x83,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE2ISNXS, x14, x15 -// CHECK: tlbip vae2isnxs, x14, x15 // encoding: [0x2e,0x93,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE2OS, x14, x15 -// CHECK: tlbip vae2os, x14, x15 // encoding: [0x2e,0x81,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE2OSNXS, x14, x15 -// CHECK: tlbip vae2osnxs, x14, x15 // encoding: [0x2e,0x91,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE2, x14, x15 -// CHECK: tlbip vale2, x14, x15 // encoding: [0xae,0x87,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE2NXS, x14, x15 -// CHECK: tlbip vale2nxs, x14, x15 // encoding: [0xae,0x97,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE2IS, x14, x15 -// CHECK: tlbip vale2is, x14, x15 // encoding: [0xae,0x83,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE2ISNXS, x14, x15 -// CHECK: tlbip vale2isnxs, x14, x15 // encoding: [0xae,0x93,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE2OS, x14, x15 -// CHECK: tlbip vale2os, x14, x15 // encoding: [0xae,0x81,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE2OSNXS, x14, x15 -// CHECK: tlbip vale2osnxs, x14, x15 // encoding: [0xae,0x91,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - tlbip VAE3, x24, x25 -// CHECK: tlbip vae3, x24, x25 // encoding: [0x38,0x87,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE3NXS, x24, x25 -// CHECK: tlbip vae3nxs, x24, x25 // encoding: [0x38,0x97,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE3IS, x24, x25 -// CHECK: tlbip vae3is, x24, x25 // encoding: [0x38,0x83,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE3ISNXS, x24, x25 -// CHECK: tlbip vae3isnxs, x24, x25 // encoding: [0x38,0x93,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE3OS, x24, x25 -// CHECK: tlbip vae3os, x24, x25 // encoding: [0x38,0x81,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VAE3OSNXS, x24, x25 -// CHECK: tlbip vae3osnxs, x24, x25 // encoding: [0x38,0x91,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE3, x24, x25 -// CHECK: tlbip vale3, x24, x25 // encoding: [0xb8,0x87,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE3NXS, x24, x25 -// CHECK: tlbip vale3nxs, x24, x25 // encoding: [0xb8,0x97,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE3IS, x24, x25 -// CHECK: tlbip vale3is, x24, x25 // encoding: [0xb8,0x83,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE3ISNXS, x24, x25 -// CHECK: tlbip vale3isnxs, x24, x25 // encoding: [0xb8,0x93,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE3OS, x24, x25 -// CHECK: tlbip vale3os, x24, x25 // encoding: [0xb8,0x81,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip VALE3OSNXS, x24, x25 -// CHECK: tlbip vale3osnxs, x24, x25 // encoding: [0xb8,0x91,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - - tlbip RVAE1, x18, x19 -// CHECK: tlbip rvae1, x18, x19 // encoding: [0x32,0x86,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE1NXS, x18, x19 -// CHECK: tlbip rvae1nxs, x18, x19 // encoding: [0x32,0x96,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE1IS, x18, x19 -// CHECK: tlbip rvae1is, x18, x19 // encoding: [0x32,0x82,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE1ISNXS, x18, x19 -// CHECK: tlbip rvae1isnxs, x18, x19 // encoding: [0x32,0x92,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE1OS, x18, x19 -// CHECK: tlbip rvae1os, x18, x19 // encoding: [0x32,0x85,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE1OSNXS, x18, x19 -// CHECK: tlbip rvae1osnxs, x18, x19 // encoding: [0x32,0x95,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAAE1, x18, x19 -// CHECK: tlbip rvaae1, x18, x19 // encoding: [0x72,0x86,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAAE1NXS, x18, x19 -// CHECK: tlbip rvaae1nxs, x18, x19 // encoding: [0x72,0x96,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAAE1IS, x18, x19 -// CHECK: tlbip rvaae1is, x18, x19 // encoding: [0x72,0x82,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAAE1ISNXS, x18, x19 -// CHECK: tlbip rvaae1isnxs, x18, x19 // encoding: [0x72,0x92,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAAE1OS, x18, x19 -// CHECK: tlbip rvaae1os, x18, x19 // encoding: [0x72,0x85,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAAE1OSNXS, x18, x19 -// CHECK: tlbip rvaae1osnxs, x18, x19 // encoding: [0x72,0x95,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE1, x18, x19 -// CHECK: tlbip rvale1, x18, x19 // encoding: [0xb2,0x86,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE1NXS, x18, x19 -// CHECK: tlbip rvale1nxs, x18, x19 // encoding: [0xb2,0x96,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE1IS, x18, x19 -// CHECK: tlbip rvale1is, x18, x19 // encoding: [0xb2,0x82,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE1ISNXS, x18, x19 -// CHECK: tlbip rvale1isnxs, x18, x19 // encoding: [0xb2,0x92,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE1OS, x18, x19 -// CHECK: tlbip rvale1os, x18, x19 // encoding: [0xb2,0x85,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE1OSNXS, x18, x19 -// CHECK: tlbip rvale1osnxs, x18, x19 // encoding: [0xb2,0x95,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAALE1, x18, x19 -// CHECK: tlbip rvaale1, x18, x19 // encoding: [0xf2,0x86,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAALE1NXS, x18, x19 -// CHECK: tlbip rvaale1nxs, x18, x19 // encoding: [0xf2,0x96,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAALE1IS, x18, x19 -// CHECK: tlbip rvaale1is, x18, x19 // encoding: [0xf2,0x82,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAALE1ISNXS, x18, x19 -// CHECK: tlbip rvaale1isnxs, x18, x19 // encoding: [0xf2,0x92,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAALE1OS, x18, x19 -// CHECK: tlbip rvaale1os, x18, x19 // encoding: [0xf2,0x85,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAALE1OSNXS, x18, x19 -// CHECK: tlbip rvaale1osnxs, x18, x19 // encoding: [0xf2,0x95,0x48,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - tlbip RVAE2, x28, x29 -// CHECK: tlbip rvae2, x28, x29 // encoding: [0x3c,0x86,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE2NXS, x28, x29 -// CHECK: tlbip rvae2nxs, x28, x29 // encoding: [0x3c,0x96,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE2IS, x28, x29 -// CHECK: tlbip rvae2is, x28, x29 // encoding: [0x3c,0x82,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE2ISNXS, x28, x29 -// CHECK: tlbip rvae2isnxs, x28, x29 // encoding: [0x3c,0x92,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE2OS, x28, x29 -// CHECK: tlbip rvae2os, x28, x29 // encoding: [0x3c,0x85,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE2OSNXS, x28, x29 -// CHECK: tlbip rvae2osnxs, x28, x29 // encoding: [0x3c,0x95,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE2, x28, x29 -// CHECK: tlbip rvale2, x28, x29 // encoding: [0xbc,0x86,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE2NXS, x28, x29 -// CHECK: tlbip rvale2nxs, x28, x29 // encoding: [0xbc,0x96,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE2IS, x28, x29 -// CHECK: tlbip rvale2is, x28, x29 // encoding: [0xbc,0x82,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE2ISNXS, x28, x29 -// CHECK: tlbip rvale2isnxs, x28, x29 // encoding: [0xbc,0x92,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE2OS, x28, x29 -// CHECK: tlbip rvale2os, x28, x29 // encoding: [0xbc,0x85,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE2OSNXS, x28, x29 -// CHECK: tlbip rvale2osnxs, x28, x29 // encoding: [0xbc,0x95,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - tlbip RVAE3, x10, x11 -// CHECK: tlbip rvae3, x10, x11 // encoding: [0x2a,0x86,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE3NXS, x10, x11 -// CHECK: tlbip rvae3nxs, x10, x11 // encoding: [0x2a,0x96,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE3IS, x10, x11 -// CHECK: tlbip rvae3is, x10, x11 // encoding: [0x2a,0x82,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE3ISNXS, x10, x11 -// CHECK: tlbip rvae3isnxs, x10, x11 // encoding: [0x2a,0x92,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE3OS, x10, x11 -// CHECK: tlbip rvae3os, x10, x11 // encoding: [0x2a,0x85,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE3OSNXS, x10, x11 -// CHECK: tlbip rvae3osnxs, x10, x11 // encoding: [0x2a,0x95,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE3, x10, x11 -// CHECK: tlbip rvale3, x10, x11 // encoding: [0xaa,0x86,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE3NXS, x10, x11 -// CHECK: tlbip rvale3nxs, x10, x11 // encoding: [0xaa,0x96,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE3IS, x10, x11 -// CHECK: tlbip rvale3is, x10, x11 // encoding: [0xaa,0x82,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE3ISNXS, x10, x11 -// CHECK: tlbip rvale3isnxs, x10, x11 // encoding: [0xaa,0x92,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE3OS, x10, x11 -// CHECK: tlbip rvale3os, x10, x11 // encoding: [0xaa,0x85,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVALE3OSNXS, x10, x11 -// CHECK: tlbip rvale3osnxs, x10, x11 // encoding: [0xaa,0x95,0x4e,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - - tlbip RIPAS2E1, x20, x21 -// CHECK: tlbip ripas2e1, x20, x21 // encoding: [0x54,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2E1NXS, x20, x21 -// CHECK: tlbip ripas2e1nxs, x20, x21 // encoding: [0x54,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2E1IS, x20, x21 -// CHECK: tlbip ripas2e1is, x20, x21 // encoding: [0x54,0x80,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2E1ISNXS, x20, x21 -// CHECK: tlbip ripas2e1isnxs, x20, x21 // encoding: [0x54,0x90,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2E1OS, x20, x21 -// CHECK: tlbip ripas2e1os, x20, x21 // encoding: [0x74,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2E1OSNXS, x20, x21 -// CHECK: tlbip ripas2e1osnxs, x20, x21 // encoding: [0x74,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2LE1, x20, x21 -// CHECK: tlbip ripas2le1, x20, x21 // encoding: [0xd4,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2LE1NXS, x20, x21 -// CHECK: tlbip ripas2le1nxs, x20, x21 // encoding: [0xd4,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2LE1IS, x20, x21 -// CHECK: tlbip ripas2le1is, x20, x21 // encoding: [0xd4,0x80,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2LE1ISNXS, x20, x21 -// CHECK: tlbip ripas2le1isnxs, x20, x21 // encoding: [0xd4,0x90,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2LE1OS, x20, x21 -// CHECK: tlbip ripas2le1os, x20, x21 // encoding: [0xf4,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2LE1OSNXS, x20, x21 -// CHECK: tlbip ripas2le1osnxs, x20, x21 // encoding: [0xf4,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - - tlbip RIPAS2LE1OS, xzr, xzr -// CHECK: tlbip ripas2le1os, xzr, xzr // encoding: [0xff,0x84,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RIPAS2LE1OSNXS, xzr, xzr -// CHECK: tlbip ripas2le1osnxs, xzr, xzr // encoding: [0xff,0x94,0x4c,0xd5] -// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 - tlbip RVAE3IS -// ERRORS: error: expected comma - tlbip RVAE3IS, -// ERRORS: error: expected register identifier - tlbip VAE3, -// ERRORS: error: expected register identifier - tlbip IPAS2E1, x4, x8 -// ERRORS: error: specified tlbip op requires a pair of registers - tlbip RVAE3, x11, x11 -// ERRORS: error: specified tlbip op requires a pair of registers diff --git a/llvm/test/MC/AArch64/armv9.2a-mec.s b/llvm/test/MC/AArch64/armv9.2a-mec.s index 42e4bf732086..1998b43d336e 100644 --- a/llvm/test/MC/AArch64/armv9.2a-mec.s +++ b/llvm/test/MC/AArch64/armv9.2a-mec.s @@ -1,55 +1,129 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+mec < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s - - mrs x0, MECIDR_EL2 -// CHECK: mrs x0, MECIDR_EL2 // encoding: [0xe0,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P0_EL2 -// CHECK: mrs x0, MECID_P0_EL2 // encoding: [0x00,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A0_EL2 -// CHECK: mrs x0, MECID_A0_EL2 // encoding: [0x20,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_P1_EL2 -// CHECK: mrs x0, MECID_P1_EL2 // encoding: [0x40,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_A1_EL2 -// CHECK: mrs x0, MECID_A1_EL2 // encoding: [0x60,0xa8,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_P_EL2 -// CHECK: mrs x0, VMECID_P_EL2 // encoding: [0x00,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, VMECID_A_EL2 -// CHECK: mrs x0, VMECID_A_EL2 // encoding: [0x20,0xa9,0x3c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - mrs x0, MECID_RL_A_EL3 -// CHECK: mrs x0, MECID_RL_A_EL3 // encoding: [0x20,0xaa,0x3e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:19: error: expected readable system register - msr MECID_P0_EL2, x0 -// CHECK: msr MECID_P0_EL2, x0 // encoding: [0x00,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A0_EL2, x0 -// CHECK: msr MECID_A0_EL2, x0 // encoding: [0x20,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_P1_EL2, x0 -// CHECK: msr MECID_P1_EL2, x0 // encoding: [0x40,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_A1_EL2, x0 -// CHECK: msr MECID_A1_EL2, x0 // encoding: [0x60,0xa8,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr VMECID_P_EL2, x0 -// CHECK: msr VMECID_P_EL2, x0 // encoding: [0x00,0xa9,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr VMECID_A_EL2, x0 -// CHECK: msr VMECID_A_EL2, x0 // encoding: [0x20,0xa9,0x1c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - msr MECID_RL_A_EL3, x0 -// CHECK: msr MECID_RL_A_EL3, x0 // encoding: [0x20,0xaa,0x1e,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate - - dc cigdpae, x0 -// CHECK: dc cigdpae, x0 // encoding: [0xe0,0x7e,0x0c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec - dc cipae, x0 -// CHECK: dc cipae, x0 // encoding: [0x00,0x7e,0x0c,0xd5] -// CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \ +// RUN: | llvm-objdump -d --mattr=+mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+mec < %s \ +// RUN: | llvm-objdump -d --mattr=-mec --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+mec < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+mec -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple aarch64 -disassemble < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-MEC %s + + +mrs x0, MECIDR_EL2 +// CHECK-INST: mrs x0, MECIDR_EL2 +// CHECK-ENCODING: encoding: [0xe0,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca8e0 mrs x0, S3_4_C10_C8_7 + +mrs x0, MECID_P0_EL2 +// CHECK-INST: mrs x0, MECID_P0_EL2 +// CHECK-ENCODING: encoding: [0x00,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca800 mrs x0, S3_4_C10_C8_0 + +mrs x0, MECID_A0_EL2 +// CHECK-INST: mrs x0, MECID_A0_EL2 +// CHECK-ENCODING: encoding: [0x20,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca820 mrs x0, S3_4_C10_C8_1 + +mrs x0, MECID_P1_EL2 +// CHECK-INST: mrs x0, MECID_P1_EL2 +// CHECK-ENCODING: encoding: [0x40,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca840 mrs x0, S3_4_C10_C8_2 + +mrs x0, MECID_A1_EL2 +// CHECK-INST: mrs x0, MECID_A1_EL2 +// CHECK-ENCODING: encoding: [0x60,0xa8,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca860 mrs x0, S3_4_C10_C8_3 + +mrs x0, VMECID_P_EL2 +// CHECK-INST: mrs x0, VMECID_P_EL2 +// CHECK-ENCODING: encoding: [0x00,0xa9,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca900 mrs x0, S3_4_C10_C9_0 + +mrs x0, VMECID_A_EL2 +// CHECK-INST: mrs x0, VMECID_A_EL2 +// CHECK-ENCODING: encoding: [0x20,0xa9,0x3c,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53ca920 mrs x0, S3_4_C10_C9_1 + +mrs x0, MECID_RL_A_EL3 +// CHECK-INST: mrs x0, MECID_RL_A_EL3 +// CHECK-ENCODING: encoding: [0x20,0xaa,0x3e,0xd5] +// CHECK-ERROR: error: expected readable system register +// CHECK-UNKNOWN: d53eaa20 mrs x0, S3_6_C10_C10_1 + +msr MECID_P0_EL2, x0 +// CHECK-INST: msr MECID_P0_EL2, x0 +// CHECK-ENCODING: encoding: [0x00,0xa8,0x1c,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51ca800 msr S3_4_C10_C8_0, x0 + +msr MECID_A0_EL2, x0 +// CHECK-INST: msr MECID_A0_EL2, x0 +// CHECK-ENCODING: encoding: [0x20,0xa8,0x1c,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51ca820 msr S3_4_C10_C8_1, x0 + +msr MECID_P1_EL2, x0 +// CHECK-INST: msr MECID_P1_EL2, x0 +// CHECK-ENCODING: encoding: [0x40,0xa8,0x1c,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51ca840 msr S3_4_C10_C8_2, x0 + +msr MECID_A1_EL2, x0 +// CHECK-INST: msr MECID_A1_EL2, x0 +// CHECK-ENCODING: encoding: [0x60,0xa8,0x1c,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51ca860 msr S3_4_C10_C8_3, x0 + +msr VMECID_P_EL2, x0 +// CHECK-INST: msr VMECID_P_EL2, x0 +// CHECK-ENCODING: encoding: [0x00,0xa9,0x1c,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51ca900 msr S3_4_C10_C9_0, x0 + +msr VMECID_A_EL2, x0 +// CHECK-INST: msr VMECID_A_EL2, x0 +// CHECK-ENCODING: encoding: [0x20,0xa9,0x1c,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51ca920 msr S3_4_C10_C9_1, x0 + +msr MECID_RL_A_EL3, x0 +// CHECK-INST: msr MECID_RL_A_EL3, x0 +// CHECK-ENCODING: encoding: [0x20,0xaa,0x1e,0xd5] +// CHECK-ERROR: error: expected writable system register or pstate +// CHECK-UNKNOWN: d51eaa20 msr S3_6_C10_C10_1, x0 + +dc cigdpae, x0 +// CHECK-INST: dc cigdpae, x0 +// CHECK-ENCODING: encoding: [0xe0,0x7e,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:4: error: DC CIGDPAE requires: mec +// CHECK-UNKNOWN: d50c7ee0 sys #4, c7, c14, #7, x0 +// CHECK-NO-MEC: sys #4, c7, c14, #7, x0 + +dc cipae, x0 +// CHECK-INST: dc cipae, x0 +// CHECK-ENCODING: encoding: [0x00,0x7e,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:4: error: DC CIPAE requires: mec +// CHECK-UNKNOWN: d50c7e00 sys #4, c7, c14, #0, x0 +// CHECK-NO-MEC: sys #4, c7, c14, #0, x0 + +sys #4, c7, c14, #7, x0 +// CHECK-INST: dc cigdpae, x0 +// CHECK-ENCODING: encoding: [0xe0,0x7e,0x0c,0xd5] +// CHECK-UNKNOWN: d50c7ee0 sys #4, c7, c14, #7, x0 + +sys #4, c7, c14, #0, x0 +// CHECK-INST: dc cipae, x0 +// CHECK-ENCODING: encoding: [0x00,0x7e,0x0c,0xd5] +// CHECK-UNKNOWN: d50c7e00 sys #4, c7, c14, #0, x0 diff --git a/llvm/test/MC/AArch64/armv9.4-lse128.s b/llvm/test/MC/AArch64/armv9.4-lse128.s deleted file mode 100644 index a639278ec826..000000000000 --- a/llvm/test/MC/AArch64/armv9.4-lse128.s +++ /dev/null @@ -1,98 +0,0 @@ -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr +lse128 %s 2>%t | FileCheck %s -// RUN: FileCheck %s --input-file=%t --check-prefix=ERROR-INVALID-OP -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck --check-prefix=ERROR-NO-LSE128 %s - -ldclrp x1, x2, [x11] -// CHECK: ldclrp x1, x2, [x11] // encoding: [0x61,0x11,0x22,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrp x21, x22, [sp] -// CHECK: ldclrp x21, x22, [sp] // encoding: [0xf5,0x13,0x36,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrpa x1, x2, [x11] -// CHECK: ldclrpa x1, x2, [x11] // encoding: [0x61,0x11,0xa2,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrpa x21, x22, [sp] -// CHECK: ldclrpa x21, x22, [sp] // encoding: [0xf5,0x13,0xb6,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrpal x1, x2, [x11] -// CHECK: ldclrpal x1, x2, [x11] // encoding: [0x61,0x11,0xe2,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrpal x21, x22, [sp] -// CHECK: ldclrpal x21, x22, [sp] // encoding: [0xf5,0x13,0xf6,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrpl x1, x2, [x11] -// CHECK: ldclrpl x1, x2, [x11] // encoding: [0x61,0x11,0x62,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrpl x21, x22, [sp] -// CHECK: ldclrpl x21, x22, [sp] // encoding: [0xf5,0x13,0x76,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldclrpl x22, xzr, [sp] -// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction -// ERROR-NO-LSE128: error: invalid operand for instruction -ldclrpl xzr, x22, [sp] -// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction -// ERROR-NO-LSE128: error: invalid operand for instruction - -ldsetp x1, x2, [x11] -// CHECK: ldsetp x1, x2, [x11] // encoding: [0x61,0x31,0x22,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetp x21, x22, [sp] -// CHECK: ldsetp x21, x22, [sp] // encoding: [0xf5,0x33,0x36,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetpa x1, x2, [x11] -// CHECK: ldsetpa x1, x2, [x11] // encoding: [0x61,0x31,0xa2,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetpa x21, x22, [sp] -// CHECK: ldsetpa x21, x22, [sp] // encoding: [0xf5,0x33,0xb6,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetpal x1, x2, [x11] -// CHECK: ldsetpal x1, x2, [x11] // encoding: [0x61,0x31,0xe2,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetpal x21, x22, [sp] -// CHECK: ldsetpal x21, x22, [sp] // encoding: [0xf5,0x33,0xf6,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetpl x1, x2, [x11] -// CHECK: ldsetpl x1, x2, [x11] // encoding: [0x61,0x31,0x62,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetpl x21, x22, [sp] -// CHECK: ldsetpl x21, x22, [sp] // encoding: [0xf5,0x33,0x76,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -ldsetpl x22, xzr, [sp] -// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction -// ERROR-NO-LSE128: error: invalid operand for instruction -ldsetpl xzr, x22, [sp] -// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction -// ERROR-NO-LSE128: error: invalid operand for instruction - - -swpp x1, x2, [x11] -// CHECK: swpp x1, x2, [x11] // encoding: [0x61,0x81,0x22,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swpp x21, x22, [sp] -// CHECK: swpp x21, x22, [sp] // encoding: [0xf5,0x83,0x36,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swppa x1, x2, [x11] -// CHECK: swppa x1, x2, [x11] // encoding: [0x61,0x81,0xa2,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swppa x21, x22, [sp] -// CHECK: swppa x21, x22, [sp] // encoding: [0xf5,0x83,0xb6,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swppal x1, x2, [x11] -// CHECK: swppal x1, x2, [x11] // encoding: [0x61,0x81,0xe2,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swppal x21, x22, [sp] -// CHECK: swppal x21, x22, [sp] // encoding: [0xf5,0x83,0xf6,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swppl x1, x2, [x11] -// CHECK: swppl x1, x2, [x11] // encoding: [0x61,0x81,0x62,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swppl x21, x22, [sp] -// CHECK: swppl x21, x22, [sp] // encoding: [0xf5,0x83,0x76,0x19] -// ERROR-NO-LSE128: [[@LINE-2]]:1: error: instruction requires: lse128 -swppl x22, xzr, [sp] -// ERROR-INVALID-OP: [[@LINE-1]]:15: error: invalid operand for instruction -// ERROR-NO-LSE128: error: invalid operand for instruction -swppl xzr, x22, [sp] -// ERROR-INVALID-OP: [[@LINE-1]]:10: error: invalid operand for instruction -// ERROR-NO-LSE128: error: invalid operand for instruction - diff --git a/llvm/test/MC/AArch64/armv9.4a-chk.s b/llvm/test/MC/AArch64/armv9.4a-chk.s index 95acee370dcb..14b0c375a7bc 100644 --- a/llvm/test/MC/AArch64/armv9.4a-chk.s +++ b/llvm/test/MC/AArch64/armv9.4a-chk.s @@ -1,21 +1,38 @@ -// RUN: llvm-mc -triple aarch64 -mattr=+chk -show-encoding %s | FileCheck %s -// RUN: llvm-mc -triple aarch64 -mattr=+v8.9a -show-encoding %s | FileCheck %s -// RUN: llvm-mc -triple aarch64 -mattr=+v9.4a -show-encoding %s | FileCheck %s -// RUN: llvm-mc -triple aarch64 -mattr=+v8a -show-encoding %s | FileCheck %s --check-prefix=NO-CHK +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v8.9a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+v9.4a < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+chk < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+chk < %s \ +// RUN: | llvm-objdump -d --mattr=+chk - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+chk < %s \ +// RUN: | llvm-objdump -d --mattr=-chk - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+chk < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+chk -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + // FEAT_CHK is mandatory from v8.0-a, but a clang user may not be using the LLVM // integrated assembler, so we cannot just print `chkfeat x16` in all // circumstances. Thankfully, we can always print `hint #40` when we cannot // print `chkfeat x16`. -// // So, in this case, we only print `chkfeat x16` from v8.9-a onwards, as an // assembler that understands v8.9-a will understand `chkfeat x16`, and those // that understand previous versions may not. chkfeat x16 -// CHECK: chkfeat x16 // encoding: [0x1f,0x25,0x03,0xd5] -// NO-CHK: hint #40 // encoding: [0x1f,0x25,0x03,0xd5] +// CHECK-INST: chkfeat x16 +// CHECK-ENCODING: encoding: [0x1f,0x25,0x03,0xd5] +// CHECK-ERROR: hint #40 +// CHECK-UNKNOWN: d503251f hint #40 hint #40 -// CHECK: chkfeat x16 // encoding: [0x1f,0x25,0x03,0xd5] -// NO-CHK: hint #40 // encoding: [0x1f,0x25,0x03,0xd5] +// CHECK-INST: chkfeat x16 +// CHECK-ENCODING: encoding: [0x1f,0x25,0x03,0xd5] +// CHECK-ERROR: hint #40 +// CHECK-UNKNOWN: d503251f hint #40 diff --git a/llvm/test/MC/AArch64/armv9.4a-ebep.s b/llvm/test/MC/AArch64/armv9.4a-ebep.s index 7e9f1115d975..2c7c7147333c 100644 --- a/llvm/test/MC/AArch64/armv9.4a-ebep.s +++ b/llvm/test/MC/AArch64/armv9.4a-ebep.s @@ -1,9 +1,41 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + mrs x2, PM +// CHECK-INST: mrs x2, PM +// CHECK-ENCODING: encoding: [0x22,0x43,0x38,0xd5] +// CHECK-UNKNOWN: d5384322 mrs x2, PM + +mrs x3, PM +// CHECK-INST: mrs x3, PM +// CHECK-ENCODING: encoding: [0x23,0x43,0x38,0xd5] +// CHECK-UNKNOWN: d5384323 mrs x3, PM + msr PM, x3 +// CHECK-INST: msr PM, x3 +// CHECK-ENCODING: encoding: [0x23,0x43,0x18,0xd5] +// CHECK-UNKNOWN: d5184323 msr PM, x3 + +msr PM, x6 +// CHECK-INST: msr PM, x6 +// CHECK-ENCODING: encoding: [0x26,0x43,0x18,0xd5] +// CHECK-UNKNOWN: d5184326 msr PM, x6 + +msr PM, #0 +// CHECK-INST: msr PM, #0 +// CHECK-ENCODING: encoding: [0x1f,0x42,0x01,0xd5] +// CHECK-UNKNOWN: d501421f msr PM, #0 + msr PM, #1 +// CHECK-INST: msr PM, #1 +// CHECK-ENCODING: encoding: [0x1f,0x43,0x01,0xd5] +// CHECK-UNKNOWN: d501431f msr PM, #1 -// CHECK: mrs x2, {{pm|PM}} // encoding: [0x22,0x43,0x38,0xd5] -// CHECK: msr {{pm|PM}}, x3 // encoding: [0x23,0x43,0x18,0xd5] -// CHECK: msr {{pm|PM}}, #1 // encoding: [0x1f,0x43,0x01,0xd5] diff --git a/llvm/test/MC/AArch64/armv9.4a-gcs.s b/llvm/test/MC/AArch64/armv9.4a-gcs.s index b4af9b5dcb10..f702c947543a 100644 --- a/llvm/test/MC/AArch64/armv9.4a-gcs.s +++ b/llvm/test/MC/AArch64/armv9.4a-gcs.s @@ -1,115 +1,204 @@ -// RUN: llvm-mc -triple aarch64 -mattr +gcs -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t | FileCheck %s --check-prefix=NO-GCS -// RUN: FileCheck --check-prefix=ERROR-NO-GCS %s < %t +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \ +// RUN: | llvm-objdump -d --mattr=+gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+gcs < %s \ +// RUN: | llvm-objdump -d --mattr=-gcs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+gcs < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+gcs -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + msr GCSCR_EL1, x0 +// CHECK-INST: msr GCSCR_EL1, x0 +// CHECK-ENCODING: encoding: [0x00,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182500 msr GCSCR_EL1, x0 + mrs x1, GCSCR_EL1 -// CHECK: msr GCSCR_EL1, x0 // encoding: [0x00,0x25,0x18,0xd5] -// CHECK: mrs x1, GCSCR_EL1 // encoding: [0x01,0x25,0x38,0xd5] +// CHECK-INST: mrs x1, GCSCR_EL1 +// CHECK-ENCODING: encoding: [0x01,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382501 mrs x1, GCSCR_EL1 msr GCSPR_EL1, x2 +// CHECK-INST: msr GCSPR_EL1, x2 +// CHECK-ENCODING: encoding: [0x22,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182522 msr GCSPR_EL1, x2 + mrs x3, GCSPR_EL1 -// CHECK: msr GCSPR_EL1, x2 // encoding: [0x22,0x25,0x18,0xd5] -// CHECK: mrs x3, GCSPR_EL1 // encoding: [0x23,0x25,0x38,0xd5] +// CHECK-INST: mrs x3, GCSPR_EL1 +// CHECK-ENCODING: encoding: [0x23,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382523 mrs x3, GCSPR_EL1 msr GCSCRE0_EL1, x4 +// CHECK-INST: msr GCSCRE0_EL1, x4 +// CHECK-ENCODING: encoding: [0x44,0x25,0x18,0xd5] +// CHECK-UNKNOWN: d5182544 msr GCSCRE0_EL1, x4 + mrs x5, GCSCRE0_EL1 -// CHECK: msr GCSCRE0_EL1, x4 // encoding: [0x44,0x25,0x18,0xd5] -// CHECK: mrs x5, GCSCRE0_EL1 // encoding: [0x45,0x25,0x38,0xd5] +// CHECK-INST: mrs x5, GCSCRE0_EL1 +// CHECK-ENCODING: encoding: [0x45,0x25,0x38,0xd5] +// CHECK-UNKNOWN: d5382545 mrs x5, GCSCRE0_EL1 msr GCSPR_EL0, x6 +// CHECK-INST: msr GCSPR_EL0, x6 +// CHECK-ENCODING: encoding: [0x26,0x25,0x1b,0xd5] +// CHECK-UNKNOWN: d51b2526 msr GCSPR_EL0, x6 + mrs x7, GCSPR_EL0 -// CHECK: msr GCSPR_EL0, x6 // encoding: [0x26,0x25,0x1b,0xd5] -// CHECK: mrs x7, GCSPR_EL0 // encoding: [0x27,0x25,0x3b,0xd5] +// CHECK-INST: mrs x7, GCSPR_EL0 +// CHECK-ENCODING: encoding: [0x27,0x25,0x3b,0xd5] +// CHECK-UNKNOWN: d53b2527 mrs x7, GCSPR_EL0 msr GCSCR_EL2, x10 +// CHECK-INST: msr GCSCR_EL2, x10 +// CHECK-ENCODING: encoding: [0x0a,0x25,0x1c,0xd5] +// CHECK-UNKNOWN: d51c250a msr GCSCR_EL2, x10 + mrs x11, GCSCR_EL2 -// CHECK: msr GCSCR_EL2, x10 // encoding: [0x0a,0x25,0x1c,0xd5] -// CHECK: mrs x11, GCSCR_EL2 // encoding: [0x0b,0x25,0x3c,0xd5] +// CHECK-INST: mrs x11, GCSCR_EL2 +// CHECK-ENCODING: encoding: [0x0b,0x25,0x3c,0xd5] +// CHECK-UNKNOWN: d53c250b mrs x11, GCSCR_EL2 msr GCSPR_EL2, x12 +// CHECK-INST: msr GCSPR_EL2, x12 +// CHECK-ENCODING: encoding: [0x2c,0x25,0x1c,0xd5] +// CHECK-UNKNOWN: d51c252c msr GCSPR_EL2, x12 + mrs x13, GCSPR_EL2 -// CHECK: msr GCSPR_EL2, x12 // encoding: [0x2c,0x25,0x1c,0xd5] -// CHECK: mrs x13, GCSPR_EL2 // encoding: [0x2d,0x25,0x3c,0xd5] +// CHECK-INST: mrs x13, GCSPR_EL2 +// CHECK-ENCODING: encoding: [0x2d,0x25,0x3c,0xd5] +// CHECK-UNKNOWN: d53c252d mrs x13, GCSPR_EL2 msr GCSCR_EL12, x14 +// CHECK-INST: msr GCSCR_EL12, x14 +// CHECK-ENCODING: encoding: [0x0e,0x25,0x1d,0xd5] +// CHECK-UNKNOWN: d51d250e msr GCSCR_EL12, x14 + mrs x15, GCSCR_EL12 -// CHECK: msr GCSCR_EL12, x14 // encoding: [0x0e,0x25,0x1d,0xd5] -// CHECK: mrs x15, GCSCR_EL12 // encoding: [0x0f,0x25,0x3d,0xd5] +// CHECK-INST: mrs x15, GCSCR_EL12 +// CHECK-ENCODING: encoding: [0x0f,0x25,0x3d,0xd5] +// CHECK-UNKNOWN: d53d250f mrs x15, GCSCR_EL12 msr GCSPR_EL12, x16 +// CHECK-INST: msr GCSPR_EL12, x16 +// CHECK-ENCODING: encoding: [0x30,0x25,0x1d,0xd5] +// CHECK-UNKNOWN: d51d2530 msr GCSPR_EL12, x16 + mrs x17, GCSPR_EL12 -// CHECK: msr GCSPR_EL12, x16 // encoding: [0x30,0x25,0x1d,0xd5] -// CHECK: mrs x17, GCSPR_EL12 // encoding: [0x31,0x25,0x3d,0xd5] +// CHECK-INST: mrs x17, GCSPR_EL12 +// CHECK-ENCODING: encoding: [0x31,0x25,0x3d,0xd5] +// CHECK-UNKNOWN: d53d2531 mrs x17, GCSPR_EL12 msr GCSCR_EL3, x18 +// CHECK-INST: msr GCSCR_EL3, x18 +// CHECK-ENCODING: encoding: [0x12,0x25,0x1e,0xd5] +// CHECK-UNKNOWN: d51e2512 msr GCSCR_EL3, x18 + mrs x19, GCSCR_EL3 -// CHECK: msr GCSCR_EL3, x18 // encoding: [0x12,0x25,0x1e,0xd5] -// CHECK: mrs x19, GCSCR_EL3 // encoding: [0x13,0x25,0x3e,0xd5] +// CHECK-INST: mrs x19, GCSCR_EL3 +// CHECK-ENCODING: encoding: [0x13,0x25,0x3e,0xd5] +// CHECK-UNKNOWN: d53e2513 mrs x19, GCSCR_EL3 msr GCSPR_EL3, x20 +// CHECK-INST: msr GCSPR_EL3, x20 +// CHECK-ENCODING: encoding: [0x34,0x25,0x1e,0xd5] +// CHECK-UNKNOWN: d51e2534 msr GCSPR_EL3, x20 + mrs x21, GCSPR_EL3 -// CHECK: msr GCSPR_EL3, x20 // encoding: [0x34,0x25,0x1e,0xd5] -// CHECK: mrs x21, GCSPR_EL3 // encoding: [0x35,0x25,0x3e,0xd5] +// CHECK-INST: mrs x21, GCSPR_EL3 +// CHECK-ENCODING: encoding: [0x35,0x25,0x3e,0xd5] +// CHECK-UNKNOWN: d53e2535 mrs x21, GCSPR_EL3 gcsss1 x21 -// CHECK: gcsss1 x21 // encoding: [0x55,0x77,0x0b,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcsss1 x21 +// CHECK-ENCODING: encoding: [0x55,0x77,0x0b,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d50b7755 sys #3, c7, c7, #2, x21 gcsss2 x22 -// CHECK: gcsss2 x22 // encoding: [0x76,0x77,0x2b,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcsss2 x22 +// CHECK-ENCODING: encoding: [0x76,0x77,0x2b,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d52b7776 sysl x22, #3, c7, c7, #3 gcspushm x25 -// CHECK: gcspushm x25 // encoding: [0x19,0x77,0x0b,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcspushm x25 +// CHECK-ENCODING: encoding: [0x19,0x77,0x0b,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d50b7719 sys #3, c7, c7, #0, x25 gcspopm -// CHECK: gcspopm // encoding: [0x3f,0x77,0x2b,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcspopm +// CHECK-ENCODING: encoding: [0x3f,0x77,0x2b,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d52b773f sysl xzr, #3, c7, c7, #1 gcspopm xzr -// CHECK: gcspopm // encoding: [0x3f,0x77,0x2b,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcspopm +// CHECK-ENCODING: encoding: [0x3f,0x77,0x2b,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d52b773f sysl xzr, #3, c7, c7, #1 gcspopm x25 -// CHECK: gcspopm x25 // encoding: [0x39,0x77,0x2b,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs - -gcsb dsync -// CHECK: gcsb dsync // encoding: [0x7f,0x22,0x03,0xd5] -// ERROR-NO-GCS-NOT: [[@LINE-2]]:1: error: instruction requires: gcs -// NO-GCS: hint #19 // encoding: [0x7f,0x22,0x03,0xd5] - -hint #19 -// CHECK: gcsb dsync // encoding: [0x7f,0x22,0x03,0xd5] -// ERROR-NO-GCS-NOT: [[@LINE-2]]:1: error: instruction requires: gcs -// NO-GCS: hint #19 // encoding: [0x7f,0x22,0x03,0xd5] +// CHECK-INST: gcspopm x25 +// CHECK-ENCODING: encoding: [0x39,0x77,0x2b,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d52b7739 sysl x25, #3, c7, c7, #1 gcsstr x26, [x27] -// CHECK: gcsstr x26, [x27] // encoding: [0x7a,0x0f,0x1f,0xd9] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcsstr x26, [x27] +// CHECK-ENCODING: encoding: [0x7a,0x0f,0x1f,0xd9] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d91f0f7a <unknown> gcsstr x26, [sp] -// CHECK: gcsstr x26, [sp] // encoding: [0xfa,0x0f,0x1f,0xd9] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcsstr x26, [sp] +// CHECK-ENCODING: encoding: [0xfa,0x0f,0x1f,0xd9] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d91f0ffa <unknown> gcssttr x26, [x27] -// CHECK: gcssttr x26, [x27] // encoding: [0x7a,0x1f,0x1f,0xd9] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcssttr x26, [x27] +// CHECK-ENCODING: encoding: [0x7a,0x1f,0x1f,0xd9] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d91f1f7a <unknown> gcssttr x26, [sp] -// CHECK: gcssttr x26, [sp] // encoding: [0xfa,0x1f,0x1f,0xd9] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcssttr x26, [sp] +// CHECK-ENCODING: encoding: [0xfa,0x1f,0x1f,0xd9] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d91f1ffa <unknown> gcspushx -// CHECK: gcspushx // encoding: [0x9f,0x77,0x08,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcspushx +// CHECK-ENCODING: encoding: [0x9f,0x77,0x08,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d508779f sys #0, c7, c7, #4 gcspopcx -// CHECK: gcspopcx // encoding: [0xbf,0x77,0x08,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcspopcx +// CHECK-ENCODING: encoding: [0xbf,0x77,0x08,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d50877bf sys #0, c7, c7, #5 gcspopx -// CHECK: gcspopx // encoding: [0xdf,0x77,0x08,0xd5] -// ERROR-NO-GCS: [[@LINE-2]]:1: error: instruction requires: gcs +// CHECK-INST: gcspopx +// CHECK-ENCODING: encoding: [0xdf,0x77,0x08,0xd5] +// CHECK-ERROR: error: instruction requires: gcs +// CHECK-UNKNOWN: d50877df sys #0, c7, c7, #6 + +gcsb dsync +// CHECK-INST: gcsb dsync +// CHECK-ENCODING: encoding: [0x7f,0x22,0x03,0xd5] +// CHECK-UNKNOWN: d503227f hint #19 +// CHECK-ERROR: hint #19 // encoding: [0x7f,0x22,0x03,0xd5] + +hint #19 +// CHECK-INST: gcsb dsync +// CHECK-ENCODING: encoding: [0x7f,0x22,0x03,0xd5] +// CHECK-UNKNOWN: d503227f hint #19 +// CHECK-ERROR: hint #19 // encoding: [0x7f,0x22,0x03,0xd5] diff --git a/llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s b/llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s new file mode 100644 index 000000000000..059b18f1e915 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.4a-lse128-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR + +ldclrpl x22, xzr, [sp] +// CHECK-ERROR: error: invalid operand for instruction + +ldclrpl xzr, x22, [sp] +// CHECK-ERROR: error: invalid operand for instruction + +ldsetpl x22, xzr, [sp] +// CHECK-ERROR: error: invalid operand for instruction + +ldsetpl xzr, x22, [sp] +// CHECK-ERROR: error: invalid operand for instruction + +swppl x22, xzr, [sp] +// CHECK-ERROR: error: invalid operand for instruction + +swppl xzr, x22, [sp] +// CHECK-ERROR: error: invalid operand for instruction diff --git a/llvm/test/MC/AArch64/armv9.4a-lse128.s b/llvm/test/MC/AArch64/armv9.4a-lse128.s new file mode 100644 index 000000000000..25dcb04c2ae6 --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.4a-lse128.s @@ -0,0 +1,159 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lse128 < %s \ +// RUN: | llvm-objdump -d --mattr=+lse128 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lse128 < %s \ +// RUN: | llvm-objdump -d --mattr=-lse128 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lse128 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+lse128 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + +ldclrp x1, x2, [x11] +// CHECK-INST: ldclrp x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x11,0x22,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19221161 <unknown> + +ldclrp x21, x22, [sp] +// CHECK-INST: ldclrp x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x13,0x36,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 193613f5 <unknown> + +ldclrpa x1, x2, [x11] +// CHECK-INST: ldclrpa x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x11,0xa2,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19a21161 <unknown> + +ldclrpa x21, x22, [sp] +// CHECK-INST: ldclrpa x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x13,0xb6,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19b613f5 <unknown> + +ldclrpal x1, x2, [x11] +// CHECK-INST: ldclrpal x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x11,0xe2,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19e21161 <unknown> + +ldclrpal x21, x22, [sp] +// CHECK-INST: ldclrpal x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x13,0xf6,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19f613f5 <unknown> + +ldclrpl x1, x2, [x11] +// CHECK-INST: ldclrpl x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x11,0x62,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19621161 <unknown> + +ldclrpl x21, x22, [sp] +// CHECK-INST: ldclrpl x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x13,0x76,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 197613f5 <unknown> + +ldsetp x1, x2, [x11] +// CHECK-INST: ldsetp x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x31,0x22,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19223161 <unknown> + +ldsetp x21, x22, [sp] +// CHECK-INST: ldsetp x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x33,0x36,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 193633f5 <unknown> + +ldsetpa x1, x2, [x11] +// CHECK-INST: ldsetpa x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x31,0xa2,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19a23161 <unknown> + +ldsetpa x21, x22, [sp] +// CHECK-INST: ldsetpa x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x33,0xb6,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19b633f5 <unknown> + +ldsetpal x1, x2, [x11] +// CHECK-INST: ldsetpal x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x31,0xe2,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19e23161 <unknown> + +ldsetpal x21, x22, [sp] +// CHECK-INST: ldsetpal x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x33,0xf6,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19f633f5 <unknown> + +ldsetpl x1, x2, [x11] +// CHECK-INST: ldsetpl x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x31,0x62,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19623161 <unknown> + +ldsetpl x21, x22, [sp] +// CHECK-INST: ldsetpl x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x33,0x76,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 197633f5 <unknown> + +swpp x1, x2, [x11] +// CHECK-INST: swpp x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x81,0x22,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19228161 <unknown> + +swpp x21, x22, [sp] +// CHECK-INST: swpp x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x83,0x36,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 193683f5 <unknown> + +swppa x1, x2, [x11] +// CHECK-INST: swppa x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x81,0xa2,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19a28161 <unknown> + +swppa x21, x22, [sp] +// CHECK-INST: swppa x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x83,0xb6,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19b683f5 <unknown> + +swppal x1, x2, [x11] +// CHECK-INST: swppal x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x81,0xe2,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19e28161 <unknown> + +swppal x21, x22, [sp] +// CHECK-INST: swppal x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x83,0xf6,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19f683f5 <unknown> + +swppl x1, x2, [x11] +// CHECK-INST: swppl x1, x2, [x11] +// CHECK-ENCODING: encoding: [0x61,0x81,0x62,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 19628161 <unknown> + +swppl x21, x22, [sp] +// CHECK-INST: swppl x21, x22, [sp] +// CHECK-ENCODING: encoding: [0xf5,0x83,0x76,0x19] +// CHECK-ERROR: :[[@LINE-3]]:1: error: instruction requires: lse128 +// CHECK-UNKNOWN: 197683f5 <unknown> diff --git a/llvm/test/MC/AArch64/armv9.5a-cpa.s b/llvm/test/MC/AArch64/armv9.5a-cpa.s index 1c338eccf6ca..d239224b502f 100644 --- a/llvm/test/MC/AArch64/armv9.5a-cpa.s +++ b/llvm/test/MC/AArch64/armv9.5a-cpa.s @@ -1,50 +1,87 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+cpa < %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-CPA %s +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+cpa < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+cpa < %s \ +// RUN: | llvm-objdump -d --mattr=+cpa - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+cpa < %s \ +// RUN: | llvm-objdump -d --mattr=-cpa - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+cpa < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+cpa -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + addpt x0, x1, x2 -// CHECK: addpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0x9a] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: addpt x0, x1, x2 +// CHECK-ENCODING: encoding: [0x20,0x20,0x02,0x9a] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: 9a022020 <unknown> addpt sp, sp, x2 -// CHECK: addpt sp, sp, x2 // encoding: [0xff,0x23,0x02,0x9a] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: addpt sp, sp, x2 +// CHECK-ENCODING: encoding: [0xff,0x23,0x02,0x9a] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: 9a0223ff <unknown> addpt x0, x1, x2, lsl #0 -// CHECK: addpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0x9a] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: addpt x0, x1, x2 +// CHECK-ENCODING: encoding: [0x20,0x20,0x02,0x9a] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: 9a022020 <unknown> addpt x0, x1, x2, lsl #7 -// CHECK: addpt x0, x1, x2, lsl #7 // encoding: [0x20,0x3c,0x02,0x9a] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: addpt x0, x1, x2, lsl #7 +// CHECK-ENCODING: encoding: [0x20,0x3c,0x02,0x9a] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: 9a023c20 <unknown> addpt sp, sp, x2, lsl #7 -// CHECK: addpt sp, sp, x2, lsl #7 // encoding: [0xff,0x3f,0x02,0x9a] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: addpt sp, sp, x2, lsl #7 +// CHECK-ENCODING: encoding: [0xff,0x3f,0x02,0x9a] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: 9a023fff <unknown> subpt x0, x1, x2 -// CHECK: subpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0xda] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: subpt x0, x1, x2 +// CHECK-ENCODING: encoding: [0x20,0x20,0x02,0xda] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: da022020 <unknown> subpt sp, sp, x2 -// CHECK: subpt sp, sp, x2 // encoding: [0xff,0x23,0x02,0xda] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: subpt sp, sp, x2 +// CHECK-ENCODING: encoding: [0xff,0x23,0x02,0xda] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: da0223ff <unknown> subpt x0, x1, x2, lsl #0 -// CHECK: subpt x0, x1, x2 // encoding: [0x20,0x20,0x02,0xda] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: subpt x0, x1, x2 +// CHECK-ENCODING: encoding: [0x20,0x20,0x02,0xda] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: da022020 <unknown> subpt x0, x1, x2, lsl #7 -// CHECK: subpt x0, x1, x2, lsl #7 // encoding: [0x20,0x3c,0x02,0xda] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: subpt x0, x1, x2, lsl #7 +// CHECK-ENCODING: encoding: [0x20,0x3c,0x02,0xda] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: da023c20 <unknown> subpt sp, sp, x2, lsl #7 -// CHECK: subpt sp, sp, x2, lsl #7 // encoding: [0xff,0x3f,0x02,0xda] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: subpt sp, sp, x2, lsl #7 +// CHECK-ENCODING: encoding: [0xff,0x3f,0x02,0xda] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: da023fff <unknown> maddpt x0, x1, x2, x3 -// CHECK: maddpt x0, x1, x2, x3 // encoding: [0x20,0x0c,0x62,0x9b] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: maddpt x0, x1, x2, x3 +// CHECK-ENCODING: encoding: [0x20,0x0c,0x62,0x9b] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: 9b620c20 <unknown> msubpt x0, x1, x2, x3 -// CHECK: msubpt x0, x1, x2, x3 // encoding: [0x20,0x8c,0x62,0x9b] -// ERROR-NO-CPA: error: instruction requires: cpa +// CHECK-INST: msubpt x0, x1, x2, x3 +// CHECK-ENCODING: encoding: [0x20,0x8c,0x62,0x9b] +// CHECK-ERROR: error: instruction requires: cpa +// CHECK-UNKNOWN: 9b628c20 <unknown> diff --git a/llvm/test/MC/AArch64/armv9.5a-e3dse.s b/llvm/test/MC/AArch64/armv9.5a-e3dse.s index b69d49ab4e9e..9d9798a32c8c 100644 --- a/llvm/test/MC/AArch64/armv9.5a-e3dse.s +++ b/llvm/test/MC/AArch64/armv9.5a-e3dse.s @@ -1,13 +1,31 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + mrs x0, VDISR_EL3 -// CHECK: mrs x0, VDISR_EL3 // encoding: [0x20,0xc1,0x3e,0xd5] +// CHECK-INST: mrs x0, VDISR_EL3 +// CHECK-ENCODING: encoding: [0x20,0xc1,0x3e,0xd5] +// CHECK-UNKNOWN: d53ec120 mrs x0, VDISR_EL3 msr VDISR_EL3, x0 -// CHECK: msr VDISR_EL3, x0 // encoding: [0x20,0xc1,0x1e,0xd5] +// CHECK-INST: msr VDISR_EL3, x0 +// CHECK-ENCODING: encoding: [0x20,0xc1,0x1e,0xd5] +// CHECK-UNKNOWN: d51ec120 msr VDISR_EL3, x0 mrs x0, VSESR_EL3 -// CHECK: mrs x0, VSESR_EL3 // encoding: [0x60,0x52,0x3e,0xd5] +// CHECK-INST: mrs x0, VSESR_EL3 +// CHECK-ENCODING: encoding: [0x60,0x52,0x3e,0xd5] +// CHECK-UNKNOWN: d53e5260 mrs x0, VSESR_EL3 msr VSESR_EL3, x0 -// CHECK: msr VSESR_EL3, x0 // encoding: [0x60,0x52,0x1e,0xd5] +// CHECK-INST: msr VSESR_EL3, x0 +// CHECK-ENCODING: encoding: [0x60,0x52,0x1e,0xd5] +// CHECK-UNKNOWN: d51e5260 msr VSESR_EL3, x0 diff --git a/llvm/test/MC/AArch64/armv9.5a-fgwte3.s b/llvm/test/MC/AArch64/armv9.5a-fgwte3.s index 2352bc7e1ca7..6546d517d208 100644 --- a/llvm/test/MC/AArch64/armv9.5a-fgwte3.s +++ b/llvm/test/MC/AArch64/armv9.5a-fgwte3.s @@ -1,6 +1,20 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + mrs x0, FGWTE3_EL3 -// CHECK: mrs x0, FGWTE3_EL3 // encoding: [0xa0,0x11,0x3e,0xd5] +// CHECK-INST: mrs x0, FGWTE3_EL3 +// CHECK-ENCODING: encoding: [0xa0,0x11,0x3e,0xd5] +// CHECK-UNKNOWN: d53e11a0 mrs x0, FGWTE3_EL3 + msr FGWTE3_EL3, x0 -// CHECK: msr FGWTE3_EL3, x0 // encoding: [0xa0,0x11,0x1e,0xd5] +// CHECK-INST: msr FGWTE3_EL3, x0 +// CHECK-ENCODING: encoding: [0xa0,0x11,0x1e,0xd5] +// CHECK-UNKNOWN: d51e11a0 msr FGWTE3_EL3, x0 diff --git a/llvm/test/MC/AArch64/armv9.5a-hacdbs.s b/llvm/test/MC/AArch64/armv9.5a-hacdbs.s index 8ccba29beb44..e1d1aaace574 100644 --- a/llvm/test/MC/AArch64/armv9.5a-hacdbs.s +++ b/llvm/test/MC/AArch64/armv9.5a-hacdbs.s @@ -1,12 +1,31 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + mrs x0, HACDBSBR_EL2 -// CHECK: mrs x0, HACDBSBR_EL2 // encoding: [0x80,0x23,0x3c,0xd5] +// CHECK-INST: mrs x0, HACDBSBR_EL2 +// CHECK-ENCODING: encoding: [0x80,0x23,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2380 mrs x0, HACDBSBR_EL2 + msr HACDBSBR_EL2, x0 -// CHECK: msr HACDBSBR_EL2, x0 // encoding: [0x80,0x23,0x1c,0xd5] +// CHECK-INST: msr HACDBSBR_EL2, x0 +// CHECK-ENCODING: encoding: [0x80,0x23,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2380 msr HACDBSBR_EL2, x0 mrs x0, HACDBSCONS_EL2 -// CHECK: mrs x0, HACDBSCONS_EL2 // encoding: [0xa0,0x23,0x3c,0xd5] +// CHECK-INST: mrs x0, HACDBSCONS_EL2 +// CHECK-ENCODING: encoding: [0xa0,0x23,0x3c,0xd5] +// CHECK-UNKNOWN: d53c23a0 mrs x0, HACDBSCONS_EL2 + msr HACDBSCONS_EL2, x0 -// CHECK: msr HACDBSCONS_EL2, x0 // encoding: [0xa0,0x23,0x1c,0xd5] +// CHECK-INST: msr HACDBSCONS_EL2, x0 +// CHECK-ENCODING: encoding: [0xa0,0x23,0x1c,0xd5] +// CHECK-UNKNOWN: d51c23a0 msr HACDBSCONS_EL2, x0 diff --git a/llvm/test/MC/AArch64/armv9.5a-hdbss.s b/llvm/test/MC/AArch64/armv9.5a-hdbss.s index c4505c9d70e7..3e18fe32aa62 100644 --- a/llvm/test/MC/AArch64/armv9.5a-hdbss.s +++ b/llvm/test/MC/AArch64/armv9.5a-hdbss.s @@ -1,12 +1,32 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + mrs x0, HDBSSBR_EL2 -// CHECK: mrs x0, HDBSSBR_EL2 // encoding: [0x40,0x23,0x3c,0xd5] +// CHECK-INST: mrs x0, HDBSSBR_EL2 +// CHECK-ENCODING: encoding: [0x40,0x23,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2340 mrs x0, HDBSSBR_EL2 + msr HDBSSBR_EL2, x0 -// CHECK: msr HDBSSBR_EL2, x0 // encoding: [0x40,0x23,0x1c,0xd5] +// CHECK-INST: msr HDBSSBR_EL2, x0 +// CHECK-ENCODING: encoding: [0x40,0x23,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2340 msr HDBSSBR_EL2, x0 mrs x0, HDBSSPROD_EL2 -// CHECK: mrs x0, HDBSSPROD_EL2 // encoding: [0x60,0x23,0x3c,0xd5] +// CHECK-INST: mrs x0, HDBSSPROD_EL2 +// CHECK-ENCODING: encoding: [0x60,0x23,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2360 mrs x0, HDBSSPROD_EL2 + msr HDBSSPROD_EL2, x0 -// CHECK: msr HDBSSPROD_EL2, x0 // encoding: [0x60,0x23,0x1c,0xd5] +// CHECK-INST: msr HDBSSPROD_EL2, x0 +// CHECK-ENCODING: encoding: [0x60,0x23,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2360 msr HDBSSPROD_EL2, x0 diff --git a/llvm/test/MC/AArch64/armv9.5a-spmu2.s b/llvm/test/MC/AArch64/armv9.5a-spmu2.s index b7febdb9d248..51770981ef9b 100644 --- a/llvm/test/MC/AArch64/armv9.5a-spmu2.s +++ b/llvm/test/MC/AArch64/armv9.5a-spmu2.s @@ -1,4 +1,16 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + msr SPMZR_EL0, x0 -// CHECK: msr SPMZR_EL0, x0 // encoding: [0x80,0x9c,0x13,0xd5] +// CHECK-INST: msr SPMZR_EL0, x0 +// CHECK-ENCODING: encoding: [0x80,0x9c,0x13,0xd5] +// CHECK-UNKNOWN: d5139c80 msr SPMZR_EL0, x0 diff --git a/llvm/test/MC/AArch64/armv9.5a-step2.s b/llvm/test/MC/AArch64/armv9.5a-step2.s index c5f226bda317..5d0768502785 100644 --- a/llvm/test/MC/AArch64/armv9.5a-step2.s +++ b/llvm/test/MC/AArch64/armv9.5a-step2.s @@ -1,7 +1,21 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + mrs x0, MDSTEPOP_EL1 -// CHECK: mrs x0, MDSTEPOP_EL1 // encoding: [0x40,0x05,0x30,0xd5] +// CHECK-INST: mrs x0, MDSTEPOP_EL1 +// CHECK-ENCODING: encoding: [0x40,0x05,0x30,0xd5] +// CHECK-UNKNOWN: d5300540 mrs x0, MDSTEPOP_EL1 msr MDSTEPOP_EL1, x0 -// CHECK: msr MDSTEPOP_EL1, x0 // encoding: [0x40,0x05,0x10,0xd5] +// CHECK-INST: msr MDSTEPOP_EL1, x0 +// CHECK-ENCODING: encoding: [0x40,0x05,0x10,0xd5] +// CHECK-UNKNOWN: d5100540 msr MDSTEPOP_EL1, x0 diff --git a/llvm/test/MC/AArch64/armv9.5a-tlbiw.s b/llvm/test/MC/AArch64/armv9.5a-tlbiw.s index 435ed06b33c8..efd410c1c2c5 100644 --- a/llvm/test/MC/AArch64/armv9.5a-tlbiw.s +++ b/llvm/test/MC/AArch64/armv9.5a-tlbiw.s @@ -1,27 +1,50 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+tlbiw -mattr=+xs < %s | FileCheck --check-prefix=CHECK-TLBIW --check-prefix=CHECK-XS %s -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+tlbiw < %s 2> %t | FileCheck --check-prefix=CHECK-TLBIW %s && FileCheck --check-prefix=ERROR-NO-XS-TLBIW %s < %t -// RUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-TLBIW --check-prefix=ERROR-NO-XS-TLBIW %s +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbiw,+xs < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbiw,+xs < %s \ +// RUN: | llvm-objdump -d --mattr=+tlbiw,+xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+tlbiw,+xs < %s \ +// RUN: | llvm-objdump -d --mattr=-tlbiw,-xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+tlbiw,+xs < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+tlbiw,+xs -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + tlbi VMALLWS2E1 -// CHECK-TLBIW: tlbi vmallws2e1 // encoding: [0x5f,0x86,0x0c,0xd5] -// ERROR-NO-TLBIW: [[@LINE-2]]:6: error: TLBI VMALLWS2E1 requires: tlbiw +// CHECK-INST: tlbi vmallws2e1 +// CHECK-ENCODING: encoding: [0x5f,0x86,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1 requires: tlbiw +// CHECK-UNKNOWN: d50c865f sys #4, c8, c6, #2 tlbi VMALLWS2E1IS -// CHECK-TLBIW: tlbi vmallws2e1is // encoding: [0x5f,0x82,0x0c,0xd5] -// ERROR-NO-TLBIW: [[@LINE-2]]:6: error: TLBI VMALLWS2E1IS requires: tlbiw +// CHECK-INST: tlbi vmallws2e1is +// CHECK-ENCODING: encoding: [0x5f,0x82,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1IS requires: tlbiw +// CHECK-UNKNOWN: d50c825f sys #4, c8, c2, #2 tlbi VMALLWS2E1OS -// CHECK-TLBIW: tlbi vmallws2e1os // encoding: [0x5f,0x85,0x0c,0xd5] -// ERROR-NO-TLBIW: [[@LINE-2]]:6: error: TLBI VMALLWS2E1OS requires: tlbiw +// CHECK-INST: tlbi vmallws2e1os +// CHECK-ENCODING: encoding: [0x5f,0x85,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1OS requires: tlbiw +// CHECK-UNKNOWN: d50c855f sys #4, c8, c5, #2 tlbi VMALLWS2E1nXS -// CHECK-XS: tlbi vmallws2e1nxs // encoding: [0x5f,0x96,0x0c,0xd5] -// ERROR-NO-XS-TLBIW: [[@LINE-2]]:6: error: TLBI VMALLWS2E1nXS requires: xs, tlbiw +// CHECK-INST: tlbi vmallws2e1nxs +// CHECK-ENCODING: encoding: [0x5f,0x96,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1nXS requires: xs, tlbiw +// CHECK-UNKNOWN: d50c965f sys #4, c9, c6, #2 tlbi VMALLWS2E1ISnXS -// CHECK-XS: tlbi vmallws2e1isnxs // encoding: [0x5f,0x92,0x0c,0xd5] -// ERROR-NO-XS-TLBIW: [[@LINE-2]]:6: error: TLBI VMALLWS2E1ISnXS requires: xs, tlbiw +// CHECK-INST: tlbi vmallws2e1isnxs +// CHECK-ENCODING: encoding: [0x5f,0x92,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1ISnXS requires: xs, tlbiw +// CHECK-UNKNOWN: d50c925f sys #4, c9, c2, #2 tlbi VMALLWS2E1OSnXS -// CHECK-XS: tlbi vmallws2e1osnxs // encoding: [0x5f,0x95,0x0c,0xd5] -// ERROR-NO-XS-TLBIW: [[@LINE-2]]:6: error: TLBI VMALLWS2E1OSnXS requires: xs, tlbiw +// CHECK-INST: tlbi vmallws2e1osnxs +// CHECK-ENCODING: encoding: [0x5f,0x95,0x0c,0xd5] +// CHECK-ERROR: :[[@LINE-3]]:6: error: TLBI VMALLWS2E1OSnXS requires: xs, tlbiw +// CHECK-UNKNOWN: d50c955f sys #4, c9, c5, #2 diff --git a/llvm/test/MC/AArch64/armv9.6a-lsui.s b/llvm/test/MC/AArch64/armv9.6a-lsui.s index dcd2693d0a02..63a188921ace 100644 --- a/llvm/test/MC/AArch64/armv9.6a-lsui.s +++ b/llvm/test/MC/AArch64/armv9.6a-lsui.s @@ -1,408 +1,714 @@ -// RUN: llvm-mc -triple aarch64 -mattr=+lsui -show-encoding %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN: | llvm-objdump -d --mattr=+lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+lsui < %s \ +// RUN: | llvm-objdump -d --mattr=-lsui --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+lsui < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+lsui -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + -_func: -// CHECK: _func: //------------------------------------------------------------------------------ // Unprivileged load/store operations //------------------------------------------------------------------------------ - ldtxr x9, [sp] -// CHECK: ldtxr x9, [sp] // encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x9, [sp, #0] -// CHECK: ldtxr x9, [sp] // encoding: [0xe9,0x7f,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11] -// CHECK: ldtxr x10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldtxr x10, [x11, #0] -// CHECK: ldtxr x10, [x11] // encoding: [0x6a,0x7d,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - ldatxr x9, [sp] -// CHECK: ldatxr x9, [sp] // encoding: [0xe9,0xff,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - ldatxr x10, [x11] -// CHECK: ldatxr x10, [x11] // encoding: [0x6a,0xfd,0x5f,0xc9] -// ERROR: error: instruction requires: lsui - - sttxr wzr, w4, [sp] -// CHECK: sttxr wzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr wzr, w4, [sp, #0] -// CHECK: sttxr wzr, w4, [sp] // encoding: [0xe4,0x7f,0x1f,0x89] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7] -// CHECK: sttxr w5, x6, [x7] // encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - sttxr w5, x6, [x7, #0] -// CHECK: sttxr w5, x6, [x7] // encoding: [0xe6,0x7c,0x05,0xc9] -// ERROR: error: instruction requires: lsui - - stltxr w2, w4, [sp] -// CHECK: stltxr w2, w4, [sp] // encoding: [0xe4,0xff,0x02,0x89] -// ERROR: error: instruction requires: lsui - stltxr w5, x6, [x7] -// CHECK: stltxr w5, x6, [x7] // encoding: [0xe6,0xfc,0x05,0xc9] -// ERROR: error: instruction requires: lsui +ldtxr x9, [sp] +// CHECK-INST: ldtxr x9, [sp] +// CHECK-ENCODING: encoding: [0xe9,0x7f,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7fe9 <unknown> + +ldtxr x9, [sp, #0] +// CHECK-INST: ldtxr x9, [sp] +// CHECK-ENCODING: encoding: [0xe9,0x7f,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7fe9 <unknown> + +ldtxr x10, [x11] +// CHECK-INST: ldtxr x10, [x11] +// CHECK-ENCODING: encoding: [0x6a,0x7d,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7d6a <unknown> + +ldtxr x10, [x11, #0] +// CHECK-INST: ldtxr x10, [x11] +// CHECK-ENCODING: encoding: [0x6a,0x7d,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95f7d6a <unknown> + +ldatxr x9, [sp] +// CHECK-INST: ldatxr x9, [sp] +// CHECK-ENCODING: encoding: [0xe9,0xff,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95fffe9 <unknown> + +ldatxr x10, [x11] +// CHECK-INST: ldatxr x10, [x11] +// CHECK-ENCODING: encoding: [0x6a,0xfd,0x5f,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c95ffd6a <unknown> + +sttxr wzr, w4, [sp] +// CHECK-INST: sttxr wzr, w4, [sp] +// CHECK-ENCODING: encoding: [0xe4,0x7f,0x1f,0x89] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 891f7fe4 <unknown> + +sttxr wzr, w4, [sp, #0] +// CHECK-INST: sttxr wzr, w4, [sp] +// CHECK-ENCODING: encoding: [0xe4,0x7f,0x1f,0x89] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 891f7fe4 <unknown> + +sttxr w5, x6, [x7] +// CHECK-INST: sttxr w5, x6, [x7] +// CHECK-ENCODING: encoding: [0xe6,0x7c,0x05,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9057ce6 <unknown> + +sttxr w5, x6, [x7, #0] +// CHECK-INST: sttxr w5, x6, [x7] +// CHECK-ENCODING: encoding: [0xe6,0x7c,0x05,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9057ce6 <unknown> + +stltxr w2, w4, [sp] +// CHECK-INST: stltxr w2, w4, [sp] +// CHECK-ENCODING: encoding: [0xe4,0xff,0x02,0x89] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 8902ffe4 <unknown> + +stltxr w5, x6, [x7] +// CHECK-INST: stltxr w5, x6, [x7] +// CHECK-ENCODING: encoding: [0xe6,0xfc,0x05,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c905fce6 <unknown> //------------------------------------------------------------------------------ // Unprivileged load/store register pair (offset) //------------------------------------------------------------------------------ - ldtp x21, x29, [x2, #504] -// CHECK: ldtp x21, x29, [x2, #504] // encoding: [0x55,0xf4,0x5f,0xe9] -// ERROR: instruction requires: lsui - ldtp x22, x23, [x3, #-512] -// CHECK: ldtp x22, x23, [x3, #-512] // encoding: [0x76,0x5c,0x60,0xe9] -// ERROR: instruction requires: lsui - ldtp x24, x25, [x4, #8] -// CHECK: ldtp x24, x25, [x4, #8] // encoding: [0x98,0xe4,0x40,0xe9] -// ERROR: instruction requires: lsui - - sttp x3, x5, [sp], #16 -// CHECK: sttp x3, x5, [sp], #16 // encoding: [0xe3,0x17,0x81,0xe8] -// ERROR: instruction requires: lsui - sttp x3, x5, [sp, #8]! -// CHECK: sttp x3, x5, [sp, #8]! // encoding: [0xe3,0x97,0x80,0xe9] -// ERROR: instruction requires: lsui - - sttp q3, q5, [sp] -// CHECK: sttp q3, q5, [sp] // encoding: [0xe3,0x17,0x00,0xed] -// ERROR: instruction requires: lsui - sttp q17, q19, [sp, #1008] -// CHECK: sttp q17, q19, [sp, #1008] // encoding: [0xf1,0xcf,0x1f,0xed] -// ERROR: instruction requires: lsui +ldtp x21, x29, [x2, #504] +// CHECK-INST: ldtp x21, x29, [x2, #504] +// CHECK-ENCODING: encoding: [0x55,0xf4,0x5f,0xe9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e95ff455 <unknown> + +ldtp x22, x23, [x3, #-512] +// CHECK-INST: ldtp x22, x23, [x3, #-512] +// CHECK-ENCODING: encoding: [0x76,0x5c,0x60,0xe9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e9605c76 <unknown> + +ldtp x24, x25, [x4, #8] +// CHECK-INST: ldtp x24, x25, [x4, #8] +// CHECK-ENCODING: encoding: [0x98,0xe4,0x40,0xe9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e940e498 <unknown> + +sttp x3, x5, [sp], #16 +// CHECK-INST: sttp x3, x5, [sp], #16 +// CHECK-ENCODING: encoding: [0xe3,0x17,0x81,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e88117e3 <unknown> + +sttp x3, x5, [sp, #8]! +// CHECK-INST: sttp x3, x5, [sp, #8]! +// CHECK-ENCODING: encoding: [0xe3,0x97,0x80,0xe9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e98097e3 <unknown> + +sttp q3, q5, [sp] +// CHECK-INST: sttp q3, q5, [sp] +// CHECK-ENCODING: encoding: [0xe3,0x17,0x00,0xed] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ed0017e3 <unknown> + +sttp q17, q19, [sp, #1008] +// CHECK-INST: sttp q17, q19, [sp, #1008] +// CHECK-ENCODING: encoding: [0xf1,0xcf,0x1f,0xed] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ed1fcff1 <unknown> //------------------------------------------------------------------------------ // Load/store register pair (post-indexed) //------------------------------------------------------------------------------ - ldtp x21, x29, [x2], #504 -// CHECK: ldtp x21, x29, [x2], #504 // encoding: [0x55,0xf4,0xdf,0xe8] -// ERROR: instruction requires: lsui - ldtp x22, x23, [x3], #-512 -// CHECK: ldtp x22, x23, [x3], #-512 // encoding: [0x76,0x5c,0xe0,0xe8] -// ERROR: instruction requires: lsui - ldtp x24, x25, [x4], #8 -// CHECK: ldtp x24, x25, [x4], #8 // encoding: [0x98,0xe4,0xc0,0xe8] -// ERROR: instruction requires: lsui - - sttp q3, q5, [sp], #0 -// CHECK: sttp q3, q5, [sp], #0 // encoding: [0xe3,0x17,0x80,0xec] -// ERROR: instruction requires: lsui - sttp q17, q19, [sp], #1008 -// CHECK: sttp q17, q19, [sp], #1008 // encoding: [0xf1,0xcf,0x9f,0xec] -// ERROR: instruction requires: lsui - ldtp q23, q29, [x1], #-1024 -// CHECK: ldtp q23, q29, [x1], #-1024 // encoding: [0x37,0x74,0xe0,0xec] -// ERROR: instruction requires: lsui +ldtp x21, x29, [x2], #504 +// CHECK-INST: ldtp x21, x29, [x2], #504 +// CHECK-ENCODING: encoding: [0x55,0xf4,0xdf,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e8dff455 <unknown> + +ldtp x22, x23, [x3], #-512 +// CHECK-INST: ldtp x22, x23, [x3], #-512 +// CHECK-ENCODING: encoding: [0x76,0x5c,0xe0,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e8e05c76 <unknown> + +ldtp x24, x25, [x4], #8 +// CHECK-INST: ldtp x24, x25, [x4], #8 +// CHECK-ENCODING: encoding: [0x98,0xe4,0xc0,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e8c0e498 <unknown> + +sttp q3, q5, [sp], #0 +// CHECK-INST: sttp q3, q5, [sp], #0 +// CHECK-ENCODING: encoding: [0xe3,0x17,0x80,0xec] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ec8017e3 <unknown> + +sttp q17, q19, [sp], #1008 +// CHECK-INST: sttp q17, q19, [sp], #1008 +// CHECK-ENCODING: encoding: [0xf1,0xcf,0x9f,0xec] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ec9fcff1 <unknown> + +ldtp q23, q29, [x1], #-1024 +// CHECK-INST: ldtp q23, q29, [x1], #-1024 +// CHECK-ENCODING: encoding: [0x37,0x74,0xe0,0xec] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ece07437 <unknown> //------------------------------------------------------------------------------ // Load/store register pair (pre-indexed) //------------------------------------------------------------------------------ - ldtp x21, x29, [x2, #504]! -// CHECK: ldtp x21, x29, [x2, #504]! // encoding: [0x55,0xf4,0xdf,0xe9] -// ERROR: instruction requires: lsui - ldtp x22, x23, [x3, #-512]! -// CHECK: ldtp x22, x23, [x3, #-512]! // encoding: [0x76,0x5c,0xe0,0xe9] -// ERROR: instruction requires: lsui - ldtp x24, x25, [x4, #8]! -// CHECK: ldtp x24, x25, [x4, #8]! // encoding: [0x98,0xe4,0xc0,0xe9] -// ERROR: instruction requires: lsui - - sttp q3, q5, [sp, #0]! -// CHECK: sttp q3, q5, [sp, #0]! // encoding: [0xe3,0x17,0x80,0xed] -// ERROR: instruction requires: lsui - sttp q17, q19, [sp, #1008]! -// CHECK: sttp q17, q19, [sp, #1008]! // encoding: [0xf1,0xcf,0x9f,0xed] -// ERROR: instruction requires: lsui - ldtp q23, q29, [x1, #-1024]! -// CHECK: ldtp q23, q29, [x1, #-1024]! // encoding: [0x37,0x74,0xe0,0xed] -// ERROR: instruction requires: lsui +ldtp x21, x29, [x2, #504]! +// CHECK-INST: ldtp x21, x29, [x2, #504]! +// CHECK-ENCODING: encoding: [0x55,0xf4,0xdf,0xe9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e9dff455 <unknown> + +ldtp x22, x23, [x3, #-512]! +// CHECK-INST: ldtp x22, x23, [x3, #-512]! +// CHECK-ENCODING: encoding: [0x76,0x5c,0xe0,0xe9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e9e05c76 <unknown> + +ldtp x24, x25, [x4, #8]! +// CHECK-INST: ldtp x24, x25, [x4, #8]! +// CHECK-ENCODING: encoding: [0x98,0xe4,0xc0,0xe9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e9c0e498 <unknown> + +sttp q3, q5, [sp, #0]! +// CHECK-INST: sttp q3, q5, [sp, #0]! +// CHECK-ENCODING: encoding: [0xe3,0x17,0x80,0xed] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ed8017e3 <unknown> + +sttp q17, q19, [sp, #1008]! +// CHECK-INST: sttp q17, q19, [sp, #1008]! +// CHECK-ENCODING: encoding: [0xf1,0xcf,0x9f,0xed] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ed9fcff1 <unknown> + +ldtp q23, q29, [x1, #-1024]! +// CHECK-INST: ldtp q23, q29, [x1, #-1024]! +// CHECK-ENCODING: encoding: [0x37,0x74,0xe0,0xed] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ede07437 <unknown> //------------------------------------------------------------------------------ // CAS(P)T instructions //------------------------------------------------------------------------------ //64 bits - cast x0, x1, [x2] -// CHECK: cast x0, x1, [x2] // encoding: [0x41,0x7c,0x80,0xc9] -// ERROR: instruction requires: lsui - cast x0, x1, [sp, #0] -// CHECK: cast x0, x1, [sp] // encoding: [0xe1,0x7f,0x80,0xc9] -// ERROR: instruction requires: lsui - casat x0, x1, [x2] -// CHECK: casat x0, x1, [x2] // encoding: [0x41,0x7c,0xc0,0xc9] -// ERROR: instruction requires: lsui - casat x0, x1, [sp, #0] -// CHECK: casat x0, x1, [sp] // encoding: [0xe1,0x7f,0xc0,0xc9] -// ERROR: instruction requires: lsui - casalt x0, x1, [x2] -// CHECK: casalt x0, x1, [x2] // encoding: [0x41,0xfc,0xc0,0xc9] -// ERROR: instruction requires: lsui - casalt x0, x1, [sp, #0] -// CHECK: casalt x0, x1, [sp] // encoding: [0xe1,0xff,0xc0,0xc9] -// ERROR: instruction requires: lsui - caslt x0, x1, [x2] -// CHECK: caslt x0, x1, [x2] // encoding: [0x41,0xfc,0x80,0xc9] -// ERROR: instruction requires: lsui - caslt x0, x1, [sp, #0] -// CHECK: caslt x0, x1, [sp] // encoding: [0xe1,0xff,0x80,0xc9] -// ERROR: instruction requires: lsui + cast x0, x1, [x2] +// CHECK-INST: cast x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x41,0x7c,0x80,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9807c41 <unknown> + + cast x0, x1, [sp, #0] +// CHECK-INST: cast x0, x1, [sp] +// CHECK-ENCODING: encoding: [0xe1,0x7f,0x80,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9807fe1 <unknown> + + casat x0, x1, [x2] +// CHECK-INST: casat x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x41,0x7c,0xc0,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9c07c41 <unknown> + + casat x0, x1, [sp, #0] +// CHECK-INST: casat x0, x1, [sp] +// CHECK-ENCODING: encoding: [0xe1,0x7f,0xc0,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9c07fe1 <unknown> + + casalt x0, x1, [x2] +// CHECK-INST: casalt x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x41,0xfc,0xc0,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9c0fc41 <unknown> + + casalt x0, x1, [sp, #0] +// CHECK-INST: casalt x0, x1, [sp] +// CHECK-ENCODING: encoding: [0xe1,0xff,0xc0,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c9c0ffe1 <unknown> + + caslt x0, x1, [x2] +// CHECK-INST: caslt x0, x1, [x2] +// CHECK-ENCODING: encoding: [0x41,0xfc,0x80,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c980fc41 <unknown> + + caslt x0, x1, [sp, #0] +// CHECK-INST: caslt x0, x1, [sp] +// CHECK-ENCODING: encoding: [0xe1,0xff,0x80,0xc9] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: c980ffe1 <unknown> //CASP instruction - caspt x0, x1, x2, x3, [x4] -// CHECK: caspt x0, x1, x2, x3, [x4] // encoding: [0x82,0x7c,0x80,0x49] -// ERROR: instruction requires: lsui - caspt x0, x1, x2, x3, [sp, #0] -// CHECK: caspt x0, x1, x2, x3, [sp] // encoding: [0xe2,0x7f,0x80,0x49] -// ERROR: instruction requires: lsui - caspat x0, x1, x2, x3, [x4] -// CHECK: caspat x0, x1, x2, x3, [x4] // encoding: [0x82,0x7c,0xc0,0x49] -// ERROR: instruction requires: lsui - caspat x0, x1, x2, x3, [sp, #0] -// CHECK: caspat x0, x1, x2, x3, [sp] // encoding: [0xe2,0x7f,0xc0,0x49] -// ERROR: instruction requires: lsui - casplt x0, x1, x2, x3, [x4] -// CHECK: casplt x0, x1, x2, x3, [x4] // encoding: [0x82,0xfc,0x80,0x49] -// ERROR: instruction requires: lsui - casplt x0, x1, x2, x3, [sp, #0] -// CHECK: casplt x0, x1, x2, x3, [sp] // encoding: [0xe2,0xff,0x80,0x49] -// ERROR: instruction requires: lsui - caspalt x0, x1, x2, x3, [x4] -// CHECK: caspalt x0, x1, x2, x3, [x4] // encoding: [0x82,0xfc,0xc0,0x49] -// ERROR: instruction requires: lsui - caspalt x0, x1, x2, x3, [sp, #0] -// CHECK: caspalt x0, x1, x2, x3, [sp] // encoding: [0xe2,0xff,0xc0,0x49] -// ERROR: instruction requires: lsui +caspt x0, x1, x2, x3, [x4] +// CHECK-INST: caspt x0, x1, x2, x3, [x4] +// CHECK-ENCODING: encoding: [0x82,0x7c,0x80,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 49807c82 <unknown> + +caspt x0, x1, x2, x3, [sp, #0] +// CHECK-INST: caspt x0, x1, x2, x3, [sp] +// CHECK-ENCODING: encoding: [0xe2,0x7f,0x80,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 49807fe2 <unknown> + +caspat x0, x1, x2, x3, [x4] +// CHECK-INST: caspat x0, x1, x2, x3, [x4] +// CHECK-ENCODING: encoding: [0x82,0x7c,0xc0,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 49c07c82 <unknown> + +caspat x0, x1, x2, x3, [sp, #0] +// CHECK-INST: caspat x0, x1, x2, x3, [sp] +// CHECK-ENCODING: encoding: [0xe2,0x7f,0xc0,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 49c07fe2 <unknown> + +casplt x0, x1, x2, x3, [x4] +// CHECK-INST: casplt x0, x1, x2, x3, [x4] +// CHECK-ENCODING: encoding: [0x82,0xfc,0x80,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 4980fc82 <unknown> + +casplt x0, x1, x2, x3, [sp, #0] +// CHECK-INST: casplt x0, x1, x2, x3, [sp] +// CHECK-ENCODING: encoding: [0xe2,0xff,0x80,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 4980ffe2 <unknown> + +caspalt x0, x1, x2, x3, [x4] +// CHECK-INST: caspalt x0, x1, x2, x3, [x4] +// CHECK-ENCODING: encoding: [0x82,0xfc,0xc0,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 49c0fc82 <unknown> + +caspalt x0, x1, x2, x3, [sp, #0] +// CHECK-INST: caspalt x0, x1, x2, x3, [sp] +// CHECK-ENCODING: encoding: [0xe2,0xff,0xc0,0x49] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 49c0ffe2 <unknown> //------------------------------------------------------------------------------ // SWP(A|L)T instructions //------------------------------------------------------------------------------ - swpt w7, wzr, [x5] -// CHECK: swpt w7, wzr, [x5] // encoding: [0xbf,0x84,0x27,0x19] -// ERROR: instruction requires: lsui - swpt x9, xzr, [sp] -// CHECK: swpt x9, xzr, [sp] // encoding: [0xff,0x87,0x29,0x59] -// ERROR: instruction requires: lsui - - swpta w7, wzr, [x5] -// CHECK: swpta w7, wzr, [x5] // encoding: [0xbf,0x84,0xa7,0x19] -// ERROR: instruction requires: lsui - swpta x9, xzr, [sp] -// CHECK: swpta x9, xzr, [sp] // encoding: [0xff,0x87,0xa9,0x59] -// ERROR: instruction requires: lsui - - swptl w7, wzr, [x5] -// CHECK: swptl w7, wzr, [x5] // encoding: [0xbf,0x84,0x67,0x19] -// ERROR: instruction requires: lsui - swptl x9, xzr, [sp] -// CHECK: swptl x9, xzr, [sp] // encoding: [0xff,0x87,0x69,0x59] -// ERROR: instruction requires: lsui - - swptal w7, wzr, [x5] -// CHECK: swptal w7, wzr, [x5] // encoding: [0xbf,0x84,0xe7,0x19] -// ERROR: instruction requires: lsui - swptal x9, xzr, [sp] -// CHECK: swptal x9, xzr, [sp] // encoding: [0xff,0x87,0xe9,0x59] -// ERROR: instruction requires: lsui +swpt w7, wzr, [x5] +// CHECK-INST: swpt w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x84,0x27,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 192784bf <unknown> + +swpt x9, xzr, [sp] +// CHECK-INST: swpt x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x87,0x29,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 592987ff <unknown> + +swpta w7, wzr, [x5] +// CHECK-INST: swpta w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x84,0xa7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19a784bf <unknown> + +swpta x9, xzr, [sp] +// CHECK-INST: swpta x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x87,0xa9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59a987ff <unknown> + +swptl w7, wzr, [x5] +// CHECK-INST: swptl w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x84,0x67,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 196784bf <unknown> + +swptl x9, xzr, [sp] +// CHECK-INST: swptl x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x87,0x69,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 596987ff <unknown> + +swptal w7, wzr, [x5] +// CHECK-INST: swptal w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x84,0xe7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19e784bf <unknown> + +swptal x9, xzr, [sp] +// CHECK-INST: swptal x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x87,0xe9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59e987ff <unknown> //------------------------------------------------------------------------------ // LD{ADD|CLR|SET)(A|L|AL)T instructions //------------------------------------------------------------------------------ - ldtadd w7, wzr, [x5] -// CHECK: sttadd w7, [x5] // encoding: [0xbf,0x04,0x27,0x19] -// ERROR: instruction requires: lsui - ldtadd x9, xzr, [sp] -// CHECK: sttadd x9, [sp] // encoding: [0xff,0x07,0x29,0x59] -// ERROR: instruction requires: lsui - - ldtadda w7, wzr, [x5] -// CHECK: ldtadda w7, wzr, [x5] // encoding: [0xbf,0x04,0xa7,0x19] -// ERROR: instruction requires: lsui - ldtadda x9, xzr, [sp] -// CHECK: ldtadda x9, xzr, [sp] // encoding: [0xff,0x07,0xa9,0x59] -// ERROR: instruction requires: lsui - - ldtaddl w7, wzr, [x5] -// CHECK: sttaddl w7, [x5] // encoding: [0xbf,0x04,0x67,0x19] -// ERROR: instruction requires: lsui - ldtaddl x9, xzr, [sp] -// CHECK: sttaddl x9, [sp] // encoding: [0xff,0x07,0x69,0x59] -// ERROR: instruction requires: lsui - - ldtaddal w7, wzr, [x5] -// CHECK: ldtaddal w7, wzr, [x5] // encoding: [0xbf,0x04,0xe7,0x19] -// ERROR: instruction requires: lsui - ldtaddal x9, xzr, [sp] -// CHECK: ldtaddal x9, xzr, [sp] // encoding: [0xff,0x07,0xe9,0x59] -// ERROR: instruction requires: lsui - - ldtclr w7, wzr, [x5] -// CHECK: sttclr w7, [x5] // encoding: [0xbf,0x14,0x27,0x19] -// ERROR: instruction requires: lsui - ldtclr x9, xzr, [sp] -// CHECK: sttclr x9, [sp] // encoding: [0xff,0x17,0x29,0x59] -// ERROR: instruction requires: lsui - - ldtclrl w7, wzr, [x5] -// CHECK: sttclrl w7, [x5] // encoding: [0xbf,0x14,0x67,0x19] -// ERROR: instruction requires: lsui - ldtclrl x9, xzr, [sp] -// CHECK: sttclrl x9, [sp] // encoding: [0xff,0x17,0x69,0x59] -// ERROR: instruction requires: lsui - - ldtclra w7, wzr, [x5] -// CHECK: ldtclra w7, wzr, [x5] // encoding: [0xbf,0x14,0xa7,0x19] -// ERROR: instruction requires: lsui - ldtclra x9, xzr, [sp] -// CHECK: ldtclra x9, xzr, [sp] // encoding: [0xff,0x17,0xa9,0x59] -// ERROR: instruction requires: lsui - - ldtclral w7, wzr, [x5] -// CHECK: ldtclral w7, wzr, [x5] // encoding: [0xbf,0x14,0xe7,0x19] -// ERROR: instruction requires: lsui - ldtclral x9, xzr, [sp] -// CHECK: ldtclral x9, xzr, [sp] // encoding: [0xff,0x17,0xe9,0x59] -// ERROR: instruction requires: lsui - - ldtset w7, wzr, [x5] -// CHECK: sttset w7, [x5] // encoding: [0xbf,0x34,0x27,0x19] -// ERROR: instruction requires: lsui - ldtset x9, xzr, [sp] -// CHECK: sttset x9, [sp] // encoding: [0xff,0x37,0x29,0x59] -// ERROR: instruction requires: lsui - - ldtsetl w7, wzr, [x5] -// CHECK: sttsetl w7, [x5] // encoding: [0xbf,0x34,0x67,0x19] -// ERROR: instruction requires: lsui - ldtsetl x9, xzr, [sp] -// CHECK: sttsetl x9, [sp] // encoding: [0xff,0x37,0x69,0x59] -// ERROR: instruction requires: lsui - - ldtseta w7, wzr, [x5] -// CHECK: ldtseta w7, wzr, [x5] // encoding: [0xbf,0x34,0xa7,0x19] -// ERROR: instruction requires: lsui - ldtseta x9, xzr, [sp] -// CHECK: ldtseta x9, xzr, [sp] // encoding: [0xff,0x37,0xa9,0x59] -// ERROR: instruction requires: lsui - - ldtsetal w7, wzr, [x5] -// CHECK: ldtsetal w7, wzr, [x5] // encoding: [0xbf,0x34,0xe7,0x19] -// ERROR: instruction requires: lsui - ldtsetal x9, xzr, [sp] -// CHECK: ldtsetal x9, xzr, [sp] // encoding: [0xff,0x37,0xe9,0x59] -// ERROR: instruction requires: lsui +ldtadd w7, wzr, [x5] +// CHECK-INST: sttadd w7, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x04,0x27,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 192704bf <unknown> + +ldtadd x9, xzr, [sp] +// CHECK-INST: sttadd x9, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0x29,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 592907ff <unknown> + +ldtadda w7, wzr, [x5] +// CHECK-INST: ldtadda w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x04,0xa7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19a704bf <unknown> + +ldtadda x9, xzr, [sp] +// CHECK-INST: ldtadda x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0xa9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59a907ff <unknown> + +ldtaddl w7, wzr, [x5] +// CHECK-INST: sttaddl w7, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x04,0x67,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 196704bf <unknown> + +ldtaddl x9, xzr, [sp] +// CHECK-INST: sttaddl x9, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0x69,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 596907ff <unknown> + +ldtaddal w7, wzr, [x5] +// CHECK-INST: ldtaddal w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x04,0xe7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19e704bf <unknown> + +ldtaddal x9, xzr, [sp] +// CHECK-INST: ldtaddal x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0xe9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59e907ff <unknown> + +ldtclr w7, wzr, [x5] +// CHECK-INST: sttclr w7, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x14,0x27,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 192714bf <unknown> + +ldtclr x9, xzr, [sp] +// CHECK-INST: sttclr x9, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0x29,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 592917ff <unknown> + +ldtclrl w7, wzr, [x5] +// CHECK-INST: sttclrl w7, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x14,0x67,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 196714bf <unknown> + +ldtclrl x9, xzr, [sp] +// CHECK-INST: sttclrl x9, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0x69,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 596917ff <unknown> + +ldtclra w7, wzr, [x5] +// CHECK-INST: ldtclra w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x14,0xa7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19a714bf <unknown> + +ldtclra x9, xzr, [sp] +// CHECK-INST: ldtclra x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0xa9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59a917ff <unknown> + +ldtclral w7, wzr, [x5] +// CHECK-INST: ldtclral w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x14,0xe7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19e714bf <unknown> + +ldtclral x9, xzr, [sp] +// CHECK-INST: ldtclral x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0xe9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59e917ff <unknown> + +ldtset w7, wzr, [x5] +// CHECK-INST: sttset w7, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x34,0x27,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 192734bf <unknown> + +ldtset x9, xzr, [sp] +// CHECK-INST: sttset x9, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0x29,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 592937ff <unknown> + +ldtsetl w7, wzr, [x5] +// CHECK-INST: sttsetl w7, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x34,0x67,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 196734bf <unknown> + +ldtsetl x9, xzr, [sp] +// CHECK-INST: sttsetl x9, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0x69,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 596937ff <unknown> + +ldtseta w7, wzr, [x5] +// CHECK-INST: ldtseta w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x34,0xa7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19a734bf <unknown> + +ldtseta x9, xzr, [sp] +// CHECK-INST: ldtseta x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0xa9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59a937ff <unknown> + +ldtsetal w7, wzr, [x5] +// CHECK-INST: ldtsetal w7, wzr, [x5] +// CHECK-ENCODING: encoding: [0xbf,0x34,0xe7,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 19e734bf <unknown> + +ldtsetal x9, xzr, [sp] +// CHECK-INST: ldtsetal x9, xzr, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0xe9,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 59e937ff <unknown> //------------------------------------------------------------------------------ // ST{ADD|CLR|SET)(A|L|AL)T instructions //------------------------------------------------------------------------------ - sttadd w0, [x2] -// CHECK: sttadd w0, [x2] // encoding: [0x5f,0x04,0x20,0x19] -// ERROR: instruction requires: lsui - sttadd w2, [sp] -// CHECK: sttadd w2, [sp] // encoding: [0xff,0x07,0x22,0x19] -// ERROR: instruction requires: lsui - sttadd x0, [x2] -// CHECK: sttadd x0, [x2] // encoding: [0x5f,0x04,0x20,0x59] -// ERROR: instruction requires: lsui - sttadd x2, [sp] -// CHECK: sttadd x2, [sp] // encoding: [0xff,0x07,0x22,0x59] -// ERROR: instruction requires: lsui - - sttaddl w0, [x2] -// CHECK: sttaddl w0, [x2] // encoding: [0x5f,0x04,0x60,0x19] -// ERROR: instruction requires: lsui - sttaddl w2, [sp] -// CHECK: sttaddl w2, [sp] // encoding: [0xff,0x07,0x62,0x19] -// ERROR: instruction requires: lsui - sttaddl x0, [x2] -// CHECK: sttaddl x0, [x2] // encoding: [0x5f,0x04,0x60,0x59] -// ERROR: instruction requires: lsui - sttaddl x2, [sp] -// CHECK: sttaddl x2, [sp] // encoding: [0xff,0x07,0x62,0x59] -// ERROR: instruction requires: lsui - - sttclr w0, [x2] -// CHECK: sttclr w0, [x2] // encoding: [0x5f,0x14,0x20,0x19] -// ERROR: instruction requires: lsui - sttclr w2, [sp] -// CHECK: sttclr w2, [sp] // encoding: [0xff,0x17,0x22,0x19] -// ERROR: instruction requires: lsui - sttclr x0, [x2] -// CHECK: sttclr x0, [x2] // encoding: [0x5f,0x14,0x20,0x59] -// ERROR: instruction requires: lsui - sttclr x2, [sp] -// CHECK: sttclr x2, [sp] // encoding: [0xff,0x17,0x22,0x59] -// ERROR: instruction requires: lsui - - sttclrl w0, [x2] -// CHECK: sttclrl w0, [x2] // encoding: [0x5f,0x14,0x60,0x19] -// ERROR: instruction requires: lsui - sttclrl w2, [sp] -// CHECK: sttclrl w2, [sp] // encoding: [0xff,0x17,0x62,0x19] -// ERROR: instruction requires: lsui - sttclrl x0, [x2] -// CHECK: sttclrl x0, [x2] // encoding: [0x5f,0x14,0x60,0x59] -// ERROR: instruction requires: lsui - sttclrl x2, [sp] -// CHECK: sttclrl x2, [sp] // encoding: [0xff,0x17,0x62,0x59] -// ERROR: instruction requires: lsui - - sttset w0, [x2] -// CHECK: sttset w0, [x2] // encoding: [0x5f,0x34,0x20,0x19] -// ERROR: instruction requires: lsui - sttset w2, [sp] -// CHECK: sttset w2, [sp] // encoding: [0xff,0x37,0x22,0x19] -// ERROR: instruction requires: lsui - sttset x0, [x2] -// CHECK: sttset x0, [x2] // encoding: [0x5f,0x34,0x20,0x59] -// ERROR: instruction requires: lsui - sttset x2, [sp] -// CHECK: sttset x2, [sp] // encoding: [0xff,0x37,0x22,0x59] -// ERROR: instruction requires: lsui - - sttsetl w0, [x2] -// CHECK: sttsetl w0, [x2] // encoding: [0x5f,0x34,0x60,0x19] -// ERROR: instruction requires: lsui - sttsetl w2, [sp] -// CHECK: sttsetl w2, [sp] // encoding: [0xff,0x37,0x62,0x19] -// ERROR: instruction requires: lsui - sttsetl x0, [x2] -// CHECK: sttsetl x0, [x2] // encoding: [0x5f,0x34,0x60,0x59] -// ERROR: instruction requires: lsui - sttsetl x2, [sp] -// CHECK: sttsetl x2, [sp] // encoding: [0xff,0x37,0x62,0x59] -// ERROR: instruction requires: lsui +sttadd w0, [x2] +// CHECK-INST: sttadd w0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x04,0x20,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 1920045f <unknown> + +sttadd w2, [sp] +// CHECK-INST: sttadd w2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0x22,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 192207ff <unknown> + +sttadd x0, [x2] +// CHECK-INST: sttadd x0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x04,0x20,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 5920045f <unknown> + +sttadd x2, [sp] +// CHECK-INST: sttadd x2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0x22,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 592207ff <unknown> + +sttaddl w0, [x2] +// CHECK-INST: sttaddl w0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x04,0x60,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 1960045f <unknown> + +sttaddl w2, [sp] +// CHECK-INST: sttaddl w2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0x62,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 196207ff <unknown> + +sttaddl x0, [x2] +// CHECK-INST: sttaddl x0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x04,0x60,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 5960045f <unknown> + +sttaddl x2, [sp] +// CHECK-INST: sttaddl x2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x07,0x62,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 596207ff <unknown> + +sttclr w0, [x2] +// CHECK-INST: sttclr w0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x14,0x20,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 1920145f <unknown> + +sttclr w2, [sp] +// CHECK-INST: sttclr w2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0x22,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 192217ff <unknown> + +sttclr x0, [x2] +// CHECK-INST: sttclr x0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x14,0x20,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 5920145f <unknown> + +sttclr x2, [sp] +// CHECK-INST: sttclr x2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0x22,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 592217ff <unknown> + +sttclrl w0, [x2] +// CHECK-INST: sttclrl w0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x14,0x60,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 1960145f <unknown> + +sttclrl w2, [sp] +// CHECK-INST: sttclrl w2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0x62,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 196217ff <unknown> + +sttclrl x0, [x2] +// CHECK-INST: sttclrl x0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x14,0x60,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 5960145f <unknown> + +sttclrl x2, [sp] +// CHECK-INST: sttclrl x2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x17,0x62,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 596217ff <unknown> + +sttset w0, [x2] +// CHECK-INST: sttset w0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x34,0x20,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 1920345f <unknown> + +sttset w2, [sp] +// CHECK-INST: sttset w2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0x22,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 192237ff <unknown> + +sttset x0, [x2] +// CHECK-INST: sttset x0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x34,0x20,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 5920345f <unknown> + +sttset x2, [sp] +// CHECK-INST: sttset x2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0x22,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 592237ff <unknown> + +sttsetl w0, [x2] +// CHECK-INST: sttsetl w0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x34,0x60,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 1960345f <unknown> + +sttsetl w2, [sp] +// CHECK-INST: sttsetl w2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0x62,0x19] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 196237ff <unknown> + +sttsetl x0, [x2] +// CHECK-INST: sttsetl x0, [x2] +// CHECK-ENCODING: encoding: [0x5f,0x34,0x60,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 5960345f <unknown> + +sttsetl x2, [sp] +// CHECK-INST: sttsetl x2, [sp] +// CHECK-ENCODING: encoding: [0xff,0x37,0x62,0x59] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: 596237ff <unknown> //------------------------------------------------------------------------------ // Load/store non-temporal register pair (offset) //------------------------------------------------------------------------------ - ldtnp x21, x29, [x2, #504] -// CHECK: ldtnp x21, x29, [x2, #504] // encoding: [0x55,0xf4,0x5f,0xe8] -// ERROR: instruction requires: lsui - ldtnp x22, x23, [x3, #-512] -// CHECK: ldtnp x22, x23, [x3, #-512] // encoding: [0x76,0x5c,0x60,0xe8] -// ERROR: instruction requires: lsui - ldtnp x24, x25, [x4, #8] -// CHECK: ldtnp x24, x25, [x4, #8] // encoding: [0x98,0xe4,0x40,0xe8] -// ERROR: instruction requires: lsui - ldtnp q23, q29, [x1, #-1024] -// CHECK: ldtnp q23, q29, [x1, #-1024] // encoding: [0x37,0x74,0x60,0xec] -// ERROR: instruction requires: lsui - - sttnp x3, x5, [sp] -// CHECK: sttnp x3, x5, [sp] // encoding: [0xe3,0x17,0x00,0xe8] -// ERROR: instruction requires: lsui - sttnp x17, x19, [sp, #64] -// CHECK: sttnp x17, x19, [sp, #64] // encoding: [0xf1,0x4f,0x04,0xe8] -// ERROR: instruction requires: lsui - sttnp q3, q5, [sp] -// CHECK: sttnp q3, q5, [sp] // encoding: [0xe3,0x17,0x00,0xec] -// ERROR: instruction requires: lsui - sttnp q17, q19, [sp, #1008] -// CHECK: sttnp q17, q19, [sp, #1008] // encoding: [0xf1,0xcf,0x1f,0xec] -// ERROR: instruction requires: lsui - +ldtnp x21, x29, [x2, #504] +// CHECK-INST: ldtnp x21, x29, [x2, #504] +// CHECK-ENCODING: encoding: [0x55,0xf4,0x5f,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e85ff455 <unknown> + +ldtnp x22, x23, [x3, #-512] +// CHECK-INST: ldtnp x22, x23, [x3, #-512] +// CHECK-ENCODING: encoding: [0x76,0x5c,0x60,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e8605c76 <unknown> + +ldtnp x24, x25, [x4, #8] +// CHECK-INST: ldtnp x24, x25, [x4, #8] +// CHECK-ENCODING: encoding: [0x98,0xe4,0x40,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e840e498 <unknown> + +ldtnp q23, q29, [x1, #-1024] +// CHECK-INST: ldtnp q23, q29, [x1, #-1024] +// CHECK-ENCODING: encoding: [0x37,0x74,0x60,0xec] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ec607437 <unknown> + +sttnp x3, x5, [sp] +// CHECK-INST: sttnp x3, x5, [sp] +// CHECK-ENCODING: encoding: [0xe3,0x17,0x00,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e80017e3 <unknown> + +sttnp x17, x19, [sp, #64] +// CHECK-INST: sttnp x17, x19, [sp, #64] +// CHECK-ENCODING: encoding: [0xf1,0x4f,0x04,0xe8] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: e8044ff1 <unknown> + +sttnp q3, q5, [sp] +// CHECK-INST: sttnp q3, q5, [sp] +// CHECK-ENCODING: encoding: [0xe3,0x17,0x00,0xec] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ec0017e3 <unknown> + +sttnp q17, q19, [sp, #1008] +// CHECK-INST: sttnp q17, q19, [sp, #1008] +// CHECK-ENCODING: encoding: [0xf1,0xcf,0x1f,0xec] +// CHECK-ERROR: error: instruction requires: lsui +// CHECK-UNKNOWN: ec1fcff1 <unknown> diff --git a/llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s b/llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s new file mode 100644 index 000000000000..a39eaef2a8df --- /dev/null +++ b/llvm/test/MC/AArch64/armv9.6a-mpam-diagnostics.s @@ -0,0 +1,5 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR + +msr MPAMBWIDR_EL1, x0 +// CHECK-ERROR: error: expected writable system register or pstate
\ No newline at end of file diff --git a/llvm/test/MC/AArch64/armv9.6a-mpam.s b/llvm/test/MC/AArch64/armv9.6a-mpam.s index c0696efd3cce..82603caed554 100644 --- a/llvm/test/MC/AArch64/armv9.6a-mpam.s +++ b/llvm/test/MC/AArch64/armv9.6a-mpam.s @@ -1,45 +1,94 @@ -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK -// RUN: FileCheck --check-prefix=CHECK-RO < %t %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + //------------------------------------------------------------------------------ // Armv9.6-A FEAT_MPAM Extensions //------------------------------------------------------------------------------ -msr MPAMBWIDR_EL1, x0 msr MPAMBW3_EL3, x0 +// CHECK-INST: msr MPAMBW3_EL3, x0 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x1e,0xd5] +// CHECK-UNKNOWN: d51ea580 msr MPAMBW3_EL3, x0 + msr MPAMBW2_EL2, x0 +// CHECK-INST: msr MPAMBW2_EL2, x0 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x1c,0xd5] +// CHECK-UNKNOWN: d51ca580 msr MPAMBW2_EL2, x0 + msr MPAMBW1_EL1, x0 +// CHECK-INST: msr MPAMBW1_EL1, x0 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x18,0xd5] +// CHECK-UNKNOWN: d518a580 msr MPAMBW1_EL1, x0 + msr MPAMBW1_EL12, x0 +// CHECK-INST: msr MPAMBW1_EL12, x0 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x1d,0xd5] +// CHECK-UNKNOWN: d51da580 msr MPAMBW1_EL12, x0 + msr MPAMBW0_EL1, x0 +// CHECK-INST: msr MPAMBW0_EL1, x0 +// CHECK-ENCODING: encoding: [0xa0,0xa5,0x18,0xd5] +// CHECK-UNKNOWN: d518a5a0 msr MPAMBW0_EL1, x0 + msr MPAMBWCAP_EL2, x0 +// CHECK-INST: msr MPAMBWCAP_EL2, x0 +// CHECK-ENCODING: encoding: [0xc0,0xa5,0x1c,0xd5] +// CHECK-UNKNOWN: d51ca5c0 msr MPAMBWCAP_EL2, x0 + msr MPAMBWSM_EL1, x0 +// CHECK-INST: msr MPAMBWSM_EL1, x0 +// CHECK-ENCODING: encoding: [0xe0,0xa5,0x18,0xd5] +// CHECK-UNKNOWN: d518a5e0 msr MPAMBWSM_EL1, x0 mrs x0, MPAMBWIDR_EL1 +// CHECK-INST: mrs x0, MPAMBWIDR_EL1 +// CHECK-ENCODING: encoding: [0xa0,0xa4,0x38,0xd5] +// CHECK-UNKNOWN: d538a4a0 mrs x0, MPAMBWIDR_EL1 + mrs x0, MPAMBW3_EL3 +// CHECK-INST: mrs x0, MPAMBW3_EL3 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x3e,0xd5] +// CHECK-UNKNOWN: d53ea580 mrs x0, MPAMBW3_EL3 + mrs x0, MPAMBW2_EL2 +// CHECK-INST: mrs x0, MPAMBW2_EL2 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x3c,0xd5] +// CHECK-UNKNOWN: d53ca580 mrs x0, MPAMBW2_EL2 + mrs x0, MPAMBW1_EL1 +// CHECK-INST: mrs x0, MPAMBW1_EL1 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x38,0xd5] +// CHECK-UNKNOWN: d538a580 mrs x0, MPAMBW1_EL1 + mrs x0, MPAMBW1_EL12 +// CHECK-INST: mrs x0, MPAMBW1_EL12 +// CHECK-ENCODING: encoding: [0x80,0xa5,0x3d,0xd5] +// CHECK-UNKNOWN: d53da580 mrs x0, MPAMBW1_EL12 + mrs x0, MPAMBW0_EL1 +// CHECK-INST: mrs x0, MPAMBW0_EL1 +// CHECK-ENCODING: encoding: [0xa0,0xa5,0x38,0xd5] +// CHECK-UNKNOWN: d538a5a0 mrs x0, MPAMBW0_EL1 + mrs x0, MPAMBWCAP_EL2 +// CHECK-INST: mrs x0, MPAMBWCAP_EL2 +// CHECK-ENCODING: encoding: [0xc0,0xa5,0x3c,0xd5] +// CHECK-UNKNOWN: d53ca5c0 mrs x0, MPAMBWCAP_EL2 + mrs x0, MPAMBWSM_EL1 +// CHECK-INST: mrs x0, MPAMBWSM_EL1 +// CHECK-ENCODING: encoding: [0xe0,0xa5,0x38,0xd5] +// CHECK-UNKNOWN: d538a5e0 mrs x0, MPAMBWSM_EL1 + -//CHECK: msr MPAMBW3_EL3, x0 // encoding: [0x80,0xa5,0x1e,0xd5] -//CHECK: msr MPAMBW2_EL2, x0 // encoding: [0x80,0xa5,0x1c,0xd5] -//CHECK: msr MPAMBW1_EL1, x0 // encoding: [0x80,0xa5,0x18,0xd5] -//CHECK: msr MPAMBW1_EL12, x0 // encoding: [0x80,0xa5,0x1d,0xd5] -//CHECK: msr MPAMBW0_EL1, x0 // encoding: [0xa0,0xa5,0x18,0xd5] -//CHECK: msr MPAMBWCAP_EL2, x0 // encoding: [0xc0,0xa5,0x1c,0xd5] -//CHECK: msr MPAMBWSM_EL1, x0 // encoding: [0xe0,0xa5,0x18,0xd5] - -//CHECK-RO: error: expected writable system register or pstate -//CHECK-RO: msr MPAMBWIDR_EL1, x0 -//CHECK-RO: ^ - -//CHECK: mrs x0, MPAMBWIDR_EL1 // encoding: [0xa0,0xa4,0x38,0xd5] -//CHECK: mrs x0, MPAMBW3_EL3 // encoding: [0x80,0xa5,0x3e,0xd5] -//CHECK: mrs x0, MPAMBW2_EL2 // encoding: [0x80,0xa5,0x3c,0xd5] -//CHECK: mrs x0, MPAMBW1_EL1 // encoding: [0x80,0xa5,0x38,0xd5] -//CHECK: mrs x0, MPAMBW1_EL12 // encoding: [0x80,0xa5,0x3d,0xd5] -//CHECK: mrs x0, MPAMBW0_EL1 // encoding: [0xa0,0xa5,0x38,0xd5] -//CHECK: mrs x0, MPAMBWCAP_EL2 // encoding: [0xc0,0xa5,0x3c,0xd5] -//CHECK: mrs x0, MPAMBWSM_EL1 // encoding: [0xe0,0xa5,0x38,0xd5] diff --git a/llvm/test/MC/AArch64/armv9.6a-occmo.s b/llvm/test/MC/AArch64/armv9.6a-occmo.s index d6548f98645a..9f2564200991 100644 --- a/llvm/test/MC/AArch64/armv9.6a-occmo.s +++ b/llvm/test/MC/AArch64/armv9.6a-occmo.s @@ -1,17 +1,39 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+occmo -mattr=+mte %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding %s -mattr=+mte 2>&1 | FileCheck --check-prefix=ERROR %s -.func: -// CHECK: .func: - dc civaoc, x12 -// CHECK: dc civaoc, x12 // encoding: [0x0c,0x7f,0x0b,0xd5] -// ERROR: error: DC CIVAOC requires: occmo - dc cigdvaoc, x0 -// CHECK: dc cigdvaoc, x0 // encoding: [0xe0,0x7f,0x0b,0xd5] -// ERROR: error: DC CIGDVAOC requires: mte, memtag, occmo - dc cvaoc, x13 -// CHECK: dc cvaoc, x13 // encoding: [0x0d,0x7b,0x0b,0xd5] -// ERROR: error: DC CVAOC requires: occmo - dc cgdvaoc, x1 -// CHECK: dc cgdvaoc, x1 // encoding: [0xe1,0x7b,0x0b,0xd5] -// ERROR: error: DC CGDVAOC requires: mte, memtag, occmo +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+occmo,+mte,+memtag < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+occmo,+mte,+memtag < %s \ +// RUN: | llvm-objdump -d --mattr=+occmo,+mte,+memtag --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+occmo,+mte,+memtag < %s \ +// RUN: | llvm-objdump -d --mattr=-occmo,-mte,-memtag --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+occmo,+mte,+memtag < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+occmo,+mte,+memtag -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +dc civaoc, x12 +// CHECK-INST: dc civaoc, x12 +// CHECK-ENCODING: encoding: [0x0c,0x7f,0x0b,0xd5] +// CHECK-ERROR: error: DC CIVAOC requires: occmo +// CHECK-UNKNOWN: d50b7f0c sys #3, c7, c15, #0, x12 + +dc cigdvaoc, x0 +// CHECK-INST: dc cigdvaoc, x0 +// CHECK-ENCODING: encoding: [0xe0,0x7f,0x0b,0xd5] +// CHECK-ERROR: error: DC CIGDVAOC requires: mte, memtag, occmo +// CHECK-UNKNOWN: d50b7fe0 sys #3, c7, c15, #7, x0 + +dc cvaoc, x13 +// CHECK-INST: dc cvaoc, x13 +// CHECK-ENCODING: encoding: [0x0d,0x7b,0x0b,0xd5] +// CHECK-ERROR: error: DC CVAOC requires: occmo +// CHECK-UNKNOWN: d50b7b0d sys #3, c7, c11, #0, x13 + +dc cgdvaoc, x1 +// CHECK-INST: dc cgdvaoc, x1 +// CHECK-ENCODING: encoding: [0xe1,0x7b,0x0b,0xd5] +// CHECK-ERROR: error: DC CGDVAOC requires: mte, memtag, occmo +// CHECK-UNKNOWN: d50b7be1 sys #3, c7, c11, #7, x1 diff --git a/llvm/test/MC/AArch64/armv9.6a-pcdphint.s b/llvm/test/MC/AArch64/armv9.6a-pcdphint.s index 6314e534318c..839417174050 100644 --- a/llvm/test/MC/AArch64/armv9.6a-pcdphint.s +++ b/llvm/test/MC/AArch64/armv9.6a-pcdphint.s @@ -1,13 +1,25 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+pcdphint %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding %s 2>&1 | FileCheck --check-prefix=ERROR %s - -.func: -// CHECK: .func: - stshh keep -// CHECK: stshh keep // encoding: [0x1f,0x96,0x01,0xd5] -// ERROR: error: instruction requires: pcdphint - stshh strm -// CHECK: stshh strm // encoding: [0x3f,0x96,0x01,0xd5] -// ERROR: error: instruction requires: pcdphint +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+pcdphint < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \ +// RUN: | llvm-objdump -d --mattr=+pcdphint - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \ +// RUN: | llvm-objdump -d --mattr=-pcdphint - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+pcdphint < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+pcdphint -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +stshh keep +// CHECK-INST: stshh keep +// CHECK-ENCODING: encoding: [0x1f,0x96,0x01,0xd5] +// CHECK-ERROR: error: instruction requires: pcdphint +// CHECK-UNKNOWN: d501961f msr S0_1_C9_C6_0, xzr +stshh strm +// CHECK-INST: stshh strm +// CHECK-ENCODING: encoding: [0x3f,0x96,0x01,0xd5] +// CHECK-ERROR: error: instruction requires: pcdphint +// CHECK-UNKNOWN: d501963f msr S0_1_C9_C6_1, xzr diff --git a/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s b/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s index 093101b6cd81..2a1943ac22a2 100644 --- a/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s +++ b/llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s @@ -1,19 +1,45 @@ -# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s -.func: +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + apas x0 +// CHECK-INST: apas x0 +// CHECK-ENCODING: encoding: [0x00,0x70,0x0e,0xd5] +// CHECK-UNKNOWN: d50e7000 apas x0 + apas x1 +// CHECK-INST: apas x1 +// CHECK-ENCODING: encoding: [0x01,0x70,0x0e,0xd5] +// CHECK-UNKNOWN: d50e7001 apas x1 + apas x2 +// CHECK-INST: apas x2 +// CHECK-ENCODING: encoding: [0x02,0x70,0x0e,0xd5] +// CHECK-UNKNOWN: d50e7002 apas x2 + apas x17 +// CHECK-INST: apas x17 +// CHECK-ENCODING: encoding: [0x11,0x70,0x0e,0xd5] +// CHECK-UNKNOWN: d50e7011 apas x17 + apas x30 +// CHECK-INST: apas x30 +// CHECK-ENCODING: encoding: [0x1e,0x70,0x0e,0xd5] +// CHECK-UNKNOWN: d50e701e apas x30 + mrs x3, GPCBW_EL3 - msr GPCBW_EL3, x4 +// CHECK-INST: mrs x3, GPCBW_EL3 +// CHECK-ENCODING: encoding: [0xa3,0x21,0x3e,0xd5] +// CHECK-UNKNOWN: d53e21a3 mrs x3, GPCBW_EL3 -# CHECK: .func: -# CHECK-NEXT: apas x0 // encoding: [0x00,0x70,0x0e,0xd5] -# CHECK-NEXT: apas x1 // encoding: [0x01,0x70,0x0e,0xd5] -# CHECK-NEXT: apas x2 // encoding: [0x02,0x70,0x0e,0xd5] -# CHECK-NEXT: apas x17 // encoding: [0x11,0x70,0x0e,0xd5] -# CHECK-NEXT: apas x30 // encoding: [0x1e,0x70,0x0e,0xd5] -# CHECK-NEXT: mrs x3, GPCBW_EL3 // encoding: [0xa3,0x21,0x3e,0xd5] -# CHECK-NEXT: msr GPCBW_EL3, x4 // encoding: [0xa4,0x21,0x1e,0xd5] + msr GPCBW_EL3, x4 +// CHECK-INST: msr GPCBW_EL3, x4 +// CHECK-ENCODING: encoding: [0xa4,0x21,0x1e,0xd5] +// CHECK-UNKNOWN: d51e21a4 msr GPCBW_EL3, x4 diff --git a/llvm/test/MC/AArch64/armv9.6a-srmask.s b/llvm/test/MC/AArch64/armv9.6a-srmask.s index 40f0e98494d4..fb91993bad13 100644 --- a/llvm/test/MC/AArch64/armv9.6a-srmask.s +++ b/llvm/test/MC/AArch64/armv9.6a-srmask.s @@ -1,102 +1,254 @@ -// RUN: llvm-mc -triple aarch64 -show-encoding %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + mrs x3, SCTLRMASK_EL1 -// CHECK: mrs x3, SCTLRMASK_EL1 // encoding: [0x03,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, SCTLRMASK_EL1 +// CHECK-ENCODING: encoding: [0x03,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d5381403 mrs x3, SCTLRMASK_EL1 + mrs x3, SCTLRMASK_EL2 -// CHECK: mrs x3, SCTLRMASK_EL2 // encoding: [0x03,0x14,0x3c,0xd5] +// CHECK-INST: mrs x3, SCTLRMASK_EL2 +// CHECK-ENCODING: encoding: [0x03,0x14,0x3c,0xd5] +// CHECK-UNKNOWN: d53c1403 mrs x3, SCTLRMASK_EL2 + mrs x3, SCTLRMASK_EL12 -// CHECK: mrs x3, SCTLRMASK_EL12 // encoding: [0x03,0x14,0x3d,0xd5] +// CHECK-INST: mrs x3, SCTLRMASK_EL12 +// CHECK-ENCODING: encoding: [0x03,0x14,0x3d,0xd5] +// CHECK-UNKNOWN: d53d1403 mrs x3, SCTLRMASK_EL12 + mrs x3, CPACRMASK_EL1 -// CHECK: mrs x3, CPACRMASK_EL1 // encoding: [0x43,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, CPACRMASK_EL1 +// CHECK-ENCODING: encoding: [0x43,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d5381443 mrs x3, CPACRMASK_EL1 + mrs x3, CPTRMASK_EL2 -// CHECK: mrs x3, CPTRMASK_EL2 // encoding: [0x43,0x14,0x3c,0xd5] +// CHECK-INST: mrs x3, CPTRMASK_EL2 +// CHECK-ENCODING: encoding: [0x43,0x14,0x3c,0xd5] +// CHECK-UNKNOWN: d53c1443 mrs x3, CPTRMASK_EL2 + mrs x3, CPACRMASK_EL12 -// CHECK: mrs x3, CPACRMASK_EL12 // encoding: [0x43,0x14,0x3d,0xd5] +// CHECK-INST: mrs x3, CPACRMASK_EL12 +// CHECK-ENCODING: encoding: [0x43,0x14,0x3d,0xd5] +// CHECK-UNKNOWN: d53d1443 mrs x3, CPACRMASK_EL12 + mrs x3, SCTLR2MASK_EL1 -// CHECK: mrs x3, SCTLR2MASK_EL1 // encoding: [0x63,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, SCTLR2MASK_EL1 +// CHECK-ENCODING: encoding: [0x63,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d5381463 mrs x3, SCTLR2MASK_EL1 + mrs x3, SCTLR2MASK_EL2 -// CHECK: mrs x3, SCTLR2MASK_EL2 // encoding: [0x63,0x14,0x3c,0xd5] +// CHECK-INST: mrs x3, SCTLR2MASK_EL2 +// CHECK-ENCODING: encoding: [0x63,0x14,0x3c,0xd5] +// CHECK-UNKNOWN: d53c1463 mrs x3, SCTLR2MASK_EL2 + mrs x3, SCTLR2MASK_EL12 -// CHECK: mrs x3, SCTLR2MASK_EL12 // encoding: [0x63,0x14,0x3d,0xd5] +// CHECK-INST: mrs x3, SCTLR2MASK_EL12 +// CHECK-ENCODING: encoding: [0x63,0x14,0x3d,0xd5] +// CHECK-UNKNOWN: d53d1463 mrs x3, SCTLR2MASK_EL12 + mrs x3, CPACRALIAS_EL1 -// CHECK: mrs x3, CPACRALIAS_EL1 // encoding: [0x83,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, CPACRALIAS_EL1 +// CHECK-ENCODING: encoding: [0x83,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d5381483 mrs x3, CPACRALIAS_EL1 + mrs x3, SCTLRALIAS_EL1 -// CHECK: mrs x3, SCTLRALIAS_EL1 // encoding: [0xc3,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, SCTLRALIAS_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d53814c3 mrs x3, SCTLRALIAS_EL1 + mrs x3, SCTLR2ALIAS_EL1 -// CHECK: mrs x3, SCTLR2ALIAS_EL1 // encoding: [0xe3,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, SCTLR2ALIAS_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d53814e3 mrs x3, SCTLR2ALIAS_EL1 + mrs x3, TCRMASK_EL1 -// CHECK: mrs x3, TCRMASK_EL1 // encoding: [0x43,0x27,0x38,0xd5] +// CHECK-INST: mrs x3, TCRMASK_EL1 +// CHECK-ENCODING: encoding: [0x43,0x27,0x38,0xd5] +// CHECK-UNKNOWN: d5382743 mrs x3, TCRMASK_EL1 + mrs x3, TCRMASK_EL2 -// CHECK: mrs x3, TCRMASK_EL2 // encoding: [0x43,0x27,0x3c,0xd5] +// CHECK-INST: mrs x3, TCRMASK_EL2 +// CHECK-ENCODING: encoding: [0x43,0x27,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2743 mrs x3, TCRMASK_EL2 + mrs x3, TCRMASK_EL12 -// CHECK: mrs x3, TCRMASK_EL12 // encoding: [0x43,0x27,0x3d,0xd5] +// CHECK-INST: mrs x3, TCRMASK_EL12 +// CHECK-ENCODING: encoding: [0x43,0x27,0x3d,0xd5] +// CHECK-UNKNOWN: d53d2743 mrs x3, TCRMASK_EL12 + mrs x3, TCR2MASK_EL1 -// CHECK: mrs x3, TCR2MASK_EL1 // encoding: [0x63,0x27,0x38,0xd5] +// CHECK-INST: mrs x3, TCR2MASK_EL1 +// CHECK-ENCODING: encoding: [0x63,0x27,0x38,0xd5] +// CHECK-UNKNOWN: d5382763 mrs x3, TCR2MASK_EL1 + mrs x3, TCR2MASK_EL2 -// CHECK: mrs x3, TCR2MASK_EL2 // encoding: [0x63,0x27,0x3c,0xd5] +// CHECK-INST: mrs x3, TCR2MASK_EL2 +// CHECK-ENCODING: encoding: [0x63,0x27,0x3c,0xd5] +// CHECK-UNKNOWN: d53c2763 mrs x3, TCR2MASK_EL2 + mrs x3, TCR2MASK_EL12 -// CHECK: mrs x3, TCR2MASK_EL12 // encoding: [0x63,0x27,0x3d,0xd5] +// CHECK-INST: mrs x3, TCR2MASK_EL12 +// CHECK-ENCODING: encoding: [0x63,0x27,0x3d,0xd5] +// CHECK-UNKNOWN: d53d2763 mrs x3, TCR2MASK_EL12 + mrs x3, TCRALIAS_EL1 -// CHECK: mrs x3, TCRALIAS_EL1 // encoding: [0xc3,0x27,0x38,0xd5] +// CHECK-INST: mrs x3, TCRALIAS_EL1 +// CHECK-ENCODING: encoding: [0xc3,0x27,0x38,0xd5] +// CHECK-UNKNOWN: d53827c3 mrs x3, TCRALIAS_EL1 + mrs x3, TCR2ALIAS_EL1 -// CHECK: mrs x3, TCR2ALIAS_EL1 // encoding: [0xe3,0x27,0x38,0xd5] +// CHECK-INST: mrs x3, TCR2ALIAS_EL1 +// CHECK-ENCODING: encoding: [0xe3,0x27,0x38,0xd5] +// CHECK-UNKNOWN: d53827e3 mrs x3, TCR2ALIAS_EL1 + mrs x3, ACTLRMASK_EL1 -// CHECK: mrs x3, ACTLRMASK_EL1 // encoding: [0x23,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, ACTLRMASK_EL1 +// CHECK-ENCODING: encoding: [0x23,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d5381423 mrs x3, ACTLRMASK_EL1 + mrs x3, ACTLRMASK_EL2 -// CHECK: mrs x3, ACTLRMASK_EL2 // encoding: [0x23,0x14,0x3c,0xd5] +// CHECK-INST: mrs x3, ACTLRMASK_EL2 +// CHECK-ENCODING: encoding: [0x23,0x14,0x3c,0xd5] +// CHECK-UNKNOWN: d53c1423 mrs x3, ACTLRMASK_EL2 + mrs x3, ACTLRMASK_EL12 -// CHECK: mrs x3, ACTLRMASK_EL12 // encoding: [0x23,0x14,0x3d,0xd5] +// CHECK-INST: mrs x3, ACTLRMASK_EL12 +// CHECK-ENCODING: encoding: [0x23,0x14,0x3d,0xd5] +// CHECK-UNKNOWN: d53d1423 mrs x3, ACTLRMASK_EL12 + mrs x3, ACTLRALIAS_EL1 -// CHECK: mrs x3, ACTLRALIAS_EL1 // encoding: [0xa3,0x14,0x38,0xd5] +// CHECK-INST: mrs x3, ACTLRALIAS_EL1 +// CHECK-ENCODING: encoding: [0xa3,0x14,0x38,0xd5] +// CHECK-UNKNOWN: d53814a3 mrs x3, ACTLRALIAS_EL1 msr SCTLRMASK_EL1, x3 -// CHECK: msr SCTLRMASK_EL1, x3 // encoding: [0x03,0x14,0x18,0xd5] +// CHECK-INST: msr SCTLRMASK_EL1, x3 +// CHECK-ENCODING: encoding: [0x03,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d5181403 msr SCTLRMASK_EL1, x3 + msr SCTLRMASK_EL2, x3 -// CHECK: msr SCTLRMASK_EL2, x3 // encoding: [0x03,0x14,0x1c,0xd5] +// CHECK-INST: msr SCTLRMASK_EL2, x3 +// CHECK-ENCODING: encoding: [0x03,0x14,0x1c,0xd5] +// CHECK-UNKNOWN: d51c1403 msr SCTLRMASK_EL2, x3 + msr SCTLRMASK_EL12, x3 -// CHECK: msr SCTLRMASK_EL12, x3 // encoding: [0x03,0x14,0x1d,0xd5] +// CHECK-INST: msr SCTLRMASK_EL12, x3 +// CHECK-ENCODING: encoding: [0x03,0x14,0x1d,0xd5] +// CHECK-UNKNOWN: d51d1403 msr SCTLRMASK_EL12, x3 + msr CPACRMASK_EL1, x3 -// CHECK: msr CPACRMASK_EL1, x3 // encoding: [0x43,0x14,0x18,0xd5] +// CHECK-INST: msr CPACRMASK_EL1, x3 +// CHECK-ENCODING: encoding: [0x43,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d5181443 msr CPACRMASK_EL1, x3 + msr CPTRMASK_EL2, x3 -// CHECK: msr CPTRMASK_EL2, x3 // encoding: [0x43,0x14,0x1c,0xd5] +// CHECK-INST: msr CPTRMASK_EL2, x3 +// CHECK-ENCODING: encoding: [0x43,0x14,0x1c,0xd5] +// CHECK-UNKNOWN: d51c1443 msr CPTRMASK_EL2, x3 + msr CPACRMASK_EL12, x3 -// CHECK: msr CPACRMASK_EL12, x3 // encoding: [0x43,0x14,0x1d,0xd5] +// CHECK-INST: msr CPACRMASK_EL12, x3 +// CHECK-ENCODING: encoding: [0x43,0x14,0x1d,0xd5] +// CHECK-UNKNOWN: d51d1443 msr CPACRMASK_EL12, x3 + msr SCTLR2MASK_EL1, x3 -// CHECK: msr SCTLR2MASK_EL1, x3 // encoding: [0x63,0x14,0x18,0xd5] +// CHECK-INST: msr SCTLR2MASK_EL1, x3 +// CHECK-ENCODING: encoding: [0x63,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d5181463 msr SCTLR2MASK_EL1, x3 + msr SCTLR2MASK_EL2, x3 -// CHECK: msr SCTLR2MASK_EL2, x3 // encoding: [0x63,0x14,0x1c,0xd5] +// CHECK-INST: msr SCTLR2MASK_EL2, x3 +// CHECK-ENCODING: encoding: [0x63,0x14,0x1c,0xd5] +// CHECK-UNKNOWN: d51c1463 msr SCTLR2MASK_EL2, x3 + msr SCTLR2MASK_EL12, x3 -// CHECK: msr SCTLR2MASK_EL12, x3 // encoding: [0x63,0x14,0x1d,0xd5] +// CHECK-INST: msr SCTLR2MASK_EL12, x3 +// CHECK-ENCODING: encoding: [0x63,0x14,0x1d,0xd5] +// CHECK-UNKNOWN: d51d1463 msr SCTLR2MASK_EL12, x3 + msr CPACRALIAS_EL1, x3 -// CHECK: msr CPACRALIAS_EL1, x3 // encoding: [0x83,0x14,0x18,0xd5] +// CHECK-INST: msr CPACRALIAS_EL1, x3 +// CHECK-ENCODING: encoding: [0x83,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d5181483 msr CPACRALIAS_EL1, x3 + msr SCTLRALIAS_EL1, x3 -// CHECK: msr SCTLRALIAS_EL1, x3 // encoding: [0xc3,0x14,0x18,0xd5] +// CHECK-INST: msr SCTLRALIAS_EL1, x3 +// CHECK-ENCODING: encoding: [0xc3,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d51814c3 msr SCTLRALIAS_EL1, x3 + msr SCTLR2ALIAS_EL1, x3 -// CHECK: msr SCTLR2ALIAS_EL1, x3 // encoding: [0xe3,0x14,0x18,0xd5] +// CHECK-INST: msr SCTLR2ALIAS_EL1, x3 +// CHECK-ENCODING: encoding: [0xe3,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d51814e3 msr SCTLR2ALIAS_EL1, x3 + msr TCRMASK_EL1, x3 -// CHECK: msr TCRMASK_EL1, x3 // encoding: [0x43,0x27,0x18,0xd5] +// CHECK-INST: msr TCRMASK_EL1, x3 +// CHECK-ENCODING: encoding: [0x43,0x27,0x18,0xd5] +// CHECK-UNKNOWN: d5182743 msr TCRMASK_EL1, x3 + msr TCRMASK_EL2, x3 -// CHECK: msr TCRMASK_EL2, x3 // encoding: [0x43,0x27,0x1c,0xd5] +// CHECK-INST: msr TCRMASK_EL2, x3 +// CHECK-ENCODING: encoding: [0x43,0x27,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2743 msr TCRMASK_EL2, x3 + msr TCRMASK_EL12, x3 -// CHECK: msr TCRMASK_EL12, x3 // encoding: [0x43,0x27,0x1d,0xd5] +// CHECK-INST: msr TCRMASK_EL12, x3 +// CHECK-ENCODING: encoding: [0x43,0x27,0x1d,0xd5] +// CHECK-UNKNOWN: d51d2743 msr TCRMASK_EL12, x3 + msr TCR2MASK_EL1, x3 -// CHECK: msr TCR2MASK_EL1, x3 // encoding: [0x63,0x27,0x18,0xd5] +// CHECK-INST: msr TCR2MASK_EL1, x3 +// CHECK-ENCODING: encoding: [0x63,0x27,0x18,0xd5] +// CHECK-UNKNOWN: d5182763 msr TCR2MASK_EL1, x3 + msr TCR2MASK_EL2, x3 -// CHECK: msr TCR2MASK_EL2, x3 // encoding: [0x63,0x27,0x1c,0xd5] +// CHECK-INST: msr TCR2MASK_EL2, x3 +// CHECK-ENCODING: encoding: [0x63,0x27,0x1c,0xd5] +// CHECK-UNKNOWN: d51c2763 msr TCR2MASK_EL2, x3 + msr TCR2MASK_EL12, x3 -// CHECK: msr TCR2MASK_EL12, x3 // encoding: [0x63,0x27,0x1d,0xd5] +// CHECK-INST: msr TCR2MASK_EL12, x3 +// CHECK-ENCODING: encoding: [0x63,0x27,0x1d,0xd5] +// CHECK-UNKNOWN: d51d2763 msr TCR2MASK_EL12, x3 + msr TCRALIAS_EL1, x3 -// CHECK: msr TCRALIAS_EL1, x3 // encoding: [0xc3,0x27,0x18,0xd5] +// CHECK-INST: msr TCRALIAS_EL1, x3 +// CHECK-ENCODING: encoding: [0xc3,0x27,0x18,0xd5] +// CHECK-UNKNOWN: d51827c3 msr TCRALIAS_EL1, x3 + msr TCR2ALIAS_EL1, x3 -// CHECK: msr TCR2ALIAS_EL1, x3 // encoding: [0xe3,0x27,0x18,0xd5] +// CHECK-INST: msr TCR2ALIAS_EL1, x3 +// CHECK-ENCODING: encoding: [0xe3,0x27,0x18,0xd5] +// CHECK-UNKNOWN: d51827e3 msr TCR2ALIAS_EL1, x3 + msr ACTLRMASK_EL1, x3 -// CHECK: msr ACTLRMASK_EL1, x3 // encoding: [0x23,0x14,0x18,0xd5] +// CHECK-INST: msr ACTLRMASK_EL1, x3 +// CHECK-ENCODING: encoding: [0x23,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d5181423 msr ACTLRMASK_EL1, x3 + msr ACTLRMASK_EL2, x3 -// CHECK: msr ACTLRMASK_EL2, x3 // encoding: [0x23,0x14,0x1c,0xd5] +// CHECK-INST: msr ACTLRMASK_EL2, x3 +// CHECK-ENCODING: encoding: [0x23,0x14,0x1c,0xd5] +// CHECK-UNKNOWN: d51c1423 msr ACTLRMASK_EL2, x3 + msr ACTLRMASK_EL12, x3 -// CHECK: msr ACTLRMASK_EL12, x3 // encoding: [0x23,0x14,0x1d,0xd5] +// CHECK-INST: msr ACTLRMASK_EL12, x3 +// CHECK-ENCODING: encoding: [0x23,0x14,0x1d,0xd5] +// CHECK-UNKNOWN: d51d1423 msr ACTLRMASK_EL12, x3 + msr ACTLRALIAS_EL1, x3 -// CHECK: msr ACTLRALIAS_EL1, x3 // encoding: [0xa3,0x14,0x18,0xd5] +// CHECK-INST: msr ACTLRALIAS_EL1, x3 +// CHECK-ENCODING: encoding: [0xa3,0x14,0x18,0xd5] +// CHECK-UNKNOWN: d51814a3 msr ACTLRALIAS_EL1, x3 diff --git a/llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s b/llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s index 2314c414d4d9..4ef6367c62ea 100644 --- a/llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s +++ b/llvm/test/MC/AArch64/armv9.6a-statistical-profiling.s @@ -1,19 +1,51 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s - - msr pmbmar_el1, x0 - msr pmbsr_el12, x0 - msr pmbsr_el2, x0 - msr pmbsr_el3, x0 -// CHECK: msr PMBMAR_EL1, x0 // encoding: [0xa0,0x9a,0x18,0xd5] -// CHECK: msr PMBSR_EL12, x0 // encoding: [0x60,0x9a,0x1d,0xd5] -// CHECK: msr PMBSR_EL2, x0 // encoding: [0x60,0x9a,0x1c,0xd5] -// CHECK: msr PMBSR_EL3, x0 // encoding: [0x60,0x9a,0x1e,0xd5] - - mrs x0, pmbmar_el1 - mrs x0, pmbsr_el12 - mrs x0, pmbsr_el2 - mrs x0, pmbsr_el3 -// CHECK: mrs x0, PMBMAR_EL1 // encoding: [0xa0,0x9a,0x38,0xd5] -// CHECK: mrs x0, PMBSR_EL12 // encoding: [0x60,0x9a,0x3d,0xd5] -// CHECK: mrs x0, PMBSR_EL2 // encoding: [0x60,0x9a,0x3c,0xd5] -// CHECK: mrs x0, PMBSR_EL3 // encoding: [0x60,0x9a,0x3e,0xd5] +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + +msr pmbmar_el1, x0 +// CHECK-INST: msr PMBMAR_EL1, x0 +// CHECK-ENCODING: encoding: [0xa0,0x9a,0x18,0xd5] +// CHECK-UNKNOWN: d5189aa0 msr PMBMAR_EL1, x0 + +msr pmbsr_el12, x0 +// CHECK-INST: msr PMBSR_EL12, x0 +// CHECK-ENCODING: encoding: [0x60,0x9a,0x1d,0xd5] +// CHECK-UNKNOWN: d51d9a60 msr PMBSR_EL12, x0 + +msr pmbsr_el2, x0 +// CHECK-INST: msr PMBSR_EL2, x0 +// CHECK-ENCODING: encoding: [0x60,0x9a,0x1c,0xd5] +// CHECK-UNKNOWN: d51c9a60 msr PMBSR_EL2, x0 + +msr pmbsr_el3, x0 +// CHECK-INST: msr PMBSR_EL3, x0 +// CHECK-ENCODING: encoding: [0x60,0x9a,0x1e,0xd5] +// CHECK-UNKNOWN: d51e9a60 msr PMBSR_EL3, x0 + +mrs x0, pmbmar_el1 +// CHECK-INST: mrs x0, PMBMAR_EL1 +// CHECK-ENCODING: encoding: [0xa0,0x9a,0x38,0xd5] +// CHECK-UNKNOWN: d5389aa0 mrs x0, PMBMAR_EL1 + +mrs x0, pmbsr_el12 +// CHECK-INST: mrs x0, PMBSR_EL12 +// CHECK-ENCODING: encoding: [0x60,0x9a,0x3d,0xd5] +// CHECK-UNKNOWN: d53d9a60 mrs x0, PMBSR_EL12 + +mrs x0, pmbsr_el2 +// CHECK-INST: mrs x0, PMBSR_EL2 +// CHECK-ENCODING: encoding: [0x60,0x9a,0x3c,0xd5] +// CHECK-UNKNOWN: d53c9a60 mrs x0, PMBSR_EL2 + +mrs x0, pmbsr_el3 +// CHECK-INST: mrs x0, PMBSR_EL3 +// CHECK-ENCODING: encoding: [0x60,0x9a,0x3e,0xd5] +// CHECK-UNKNOWN: d53e9a60 mrs x0, PMBSR_EL3 diff --git a/llvm/test/MC/AArch64/armv9.6a-trbe-exception.s b/llvm/test/MC/AArch64/armv9.6a-trbe-exception.s index a8ba7c442e4c..fb795aa8c64c 100644 --- a/llvm/test/MC/AArch64/armv9.6a-trbe-exception.s +++ b/llvm/test/MC/AArch64/armv9.6a-trbe-exception.s @@ -1,15 +1,41 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s - - msr trbsr_el12, x0 - msr trbsr_el2, x0 - msr trbsr_el3, x0 -// CHECK: msr TRBSR_EL12, x0 // encoding: [0x60,0x9b,0x1d,0xd5] -// CHECK: msr TRBSR_EL2, x0 // encoding: [0x60,0x9b,0x1c,0xd5] -// CHECK: msr TRBSR_EL3, x0 // encoding: [0x60,0x9b,0x1e,0xd5] - - mrs x0, trbsr_el12 - mrs x0, trbsr_el2 - mrs x0, trbsr_el3 -// CHECK: mrs x0, TRBSR_EL12 // encoding: [0x60,0x9b,0x3d,0xd5] -// CHECK: mrs x0, TRBSR_EL2 // encoding: [0x60,0x9b,0x3c,0xd5] -// CHECK: mrs x0, TRBSR_EL3 // encoding: [0x60,0x9b,0x3e,0xd5] +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + + +msr trbsr_el12, x0 +// CHECK-INST: msr TRBSR_EL12, x0 +// CHECK-ENCODING: encoding: [0x60,0x9b,0x1d,0xd5] +// CHECK-UNKNOWN: d51d9b60 msr TRBSR_EL12, x0 + +msr trbsr_el2, x0 +// CHECK-INST: msr TRBSR_EL2, x0 +// CHECK-ENCODING: encoding: [0x60,0x9b,0x1c,0xd5] +// CHECK-UNKNOWN: d51c9b60 msr TRBSR_EL2, x0 + +msr trbsr_el3, x0 +// CHECK-INST: msr TRBSR_EL3, x0 +// CHECK-ENCODING: encoding: [0x60,0x9b,0x1e,0xd5] +// CHECK-UNKNOWN: d51e9b60 msr TRBSR_EL3, x0 + +mrs x0, trbsr_el12 +// CHECK-INST: mrs x0, TRBSR_EL12 +// CHECK-ENCODING: encoding: [0x60,0x9b,0x3d,0xd5] +// CHECK-UNKNOWN: d53d9b60 mrs x0, TRBSR_EL12 + +mrs x0, trbsr_el2 +// CHECK-INST: mrs x0, TRBSR_EL2 +// CHECK-ENCODING: encoding: [0x60,0x9b,0x3c,0xd5] +// CHECK-UNKNOWN: d53c9b60 mrs x0, TRBSR_EL2 + +mrs x0, trbsr_el3 +// CHECK-INST: mrs x0, TRBSR_EL3 +// CHECK-ENCODING: encoding: [0x60,0x9b,0x3e,0xd5] +// CHECK-UNKNOWN: d53e9b60 mrs x0, TRBSR_EL3 diff --git a/llvm/test/MC/AArch64/armv9a-sysp.s b/llvm/test/MC/AArch64/armv9a-sysp.s new file mode 100644 index 000000000000..600657595e8a --- /dev/null +++ b/llvm/test/MC/AArch64/armv9a-sysp.s @@ -0,0 +1,978 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi,+xs < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+tlb-rmi,+xs < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi,+xs < %s \ +// RUN: | llvm-objdump -d --mattr=+d128,+tlb-rmi,+xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+d128,+tlb-rmi,+xs < %s \ +// RUN: | llvm-objdump -d --mattr=-d128,+tlb-rmi,+xs --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+d128,+tlb-rmi,+xs < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+d128,+tlb-rmi,+xs -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +// +tbl-rmi required for RIPA*/RVA* +// +xs required for *NXS + +// sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} +// registers with 128-bit formats (op0, op1, Cn, Cm, op2) +// For sysp, op0 is 0 + +sysp #0, c2, c0, #0, x0, x1// TTBR0_EL1 3 0 2 0 0 +// CHECK-INST: sysp #0, c2, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482000 <unknown> + +sysp #0, c2, c0, #1, x0, x1// TTBR1_EL1 3 0 2 0 1 +// CHECK-INST: sysp #0, c2, c0, #1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482020 <unknown> + +sysp #0, c7, c4, #0, x0, x1// PAR_EL1 3 0 7 4 0 +// CHECK-INST: sysp #0, c7, c4, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x74,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5487400 <unknown> + +sysp #0, c13, c0, #3, x0, x1 // RCWSMASK_EL1 3 0 13 0 3 +// CHECK-INST: sysp #0, c13, c0, #3, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0xd0,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548d060 <unknown> + +sysp #0, c13, c0, #6, x0, x1 // RCWMASK_EL1 3 0 13 0 6 +// CHECK-INST: sysp #0, c13, c0, #6, x0, x1 +// CHECK-ENCODING: encoding: [0xc0,0xd0,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548d0c0 <unknown> + +sysp #4, c2, c0, #0, x0, x1// TTBR0_EL2 3 4 2 0 0 +// CHECK-INST: sysp #4, c2, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c2000 <unknown> + +sysp #4, c2, c0, #1, x0, x1// TTBR1_EL2 3 4 2 0 1 +// CHECK-INST: sysp #4, c2, c0, #1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c2020 <unknown> + +sysp #4, c2, c1, #0, x0, x1// VTTBR_EL2 3 4 2 1 0 +// CHECK-INST: sysp #4, c2, c1, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x21,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c2100 <unknown> + + + +sysp #0, c2, c0, #0, x0, x1 +// CHECK-INST: sysp #0, c2, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482000 <unknown> + +sysp #0, c2, c0, #1, x0, x1 +// CHECK-INST: sysp #0, c2, c0, #1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482020 <unknown> + +sysp #0, c7, c4, #0, x0, x1 +// CHECK-INST: sysp #0, c7, c4, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x74,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5487400 <unknown> + +sysp #0, c13, c0, #3, x0, x1 +// CHECK-INST: sysp #0, c13, c0, #3, x0, x1 +// CHECK-ENCODING: encoding: [0x60,0xd0,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548d060 <unknown> + +sysp #0, c13, c0, #6, x0, x1 +// CHECK-INST: sysp #0, c13, c0, #6, x0, x1 +// CHECK-ENCODING: encoding: [0xc0,0xd0,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548d0c0 <unknown> + +sysp #4, c2, c0, #0, x0, x1 +// CHECK-INST: sysp #4, c2, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c2000 <unknown> + +sysp #4, c2, c0, #1, x0, x1 +// CHECK-INST: sysp #4, c2, c0, #1, x0, x1 +// CHECK-ENCODING: encoding: [0x20,0x20,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c2020 <unknown> + +sysp #4, c2, c1, #0, x0, x1 +// CHECK-INST: sysp #4, c2, c1, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x21,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c2100 <unknown> + +sysp #0, c2, c0, #0, x0, x1 +// CHECK-INST: sysp #0, c2, c0, #0, x0, x1 +// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482000 <unknown> + +sysp #0, c2, c0, #0, x2, x3 +// CHECK-INST: sysp #0, c2, c0, #0, x2, x3 +// CHECK-ENCODING: encoding: [0x02,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482002 <unknown> + +sysp #0, c2, c0, #0, x4, x5 +// CHECK-INST: sysp #0, c2, c0, #0, x4, x5 +// CHECK-ENCODING: encoding: [0x04,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482004 <unknown> + +sysp #0, c2, c0, #0, x6, x7 +// CHECK-INST: sysp #0, c2, c0, #0, x6, x7 +// CHECK-ENCODING: encoding: [0x06,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482006 <unknown> + +sysp #0, c2, c0, #0, x8, x9 +// CHECK-INST: sysp #0, c2, c0, #0, x8, x9 +// CHECK-ENCODING: encoding: [0x08,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482008 <unknown> + +sysp #0, c2, c0, #0, x10, x11 +// CHECK-INST: sysp #0, c2, c0, #0, x10, x11 +// CHECK-ENCODING: encoding: [0x0a,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548200a <unknown> + +sysp #0, c2, c0, #0, x12, x13 +// CHECK-INST: sysp #0, c2, c0, #0, x12, x13 +// CHECK-ENCODING: encoding: [0x0c,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548200c <unknown> + +sysp #0, c2, c0, #0, x14, x15 +// CHECK-INST: sysp #0, c2, c0, #0, x14, x15 +// CHECK-ENCODING: encoding: [0x0e,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548200e <unknown> + +sysp #0, c2, c0, #0, x16, x17 +// CHECK-INST: sysp #0, c2, c0, #0, x16, x17 +// CHECK-ENCODING: encoding: [0x10,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482010 <unknown> + +sysp #0, c2, c0, #0, x18, x19 +// CHECK-INST: sysp #0, c2, c0, #0, x18, x19 +// CHECK-ENCODING: encoding: [0x12,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482012 <unknown> + +sysp #0, c2, c0, #0, x20, x21 +// CHECK-INST: sysp #0, c2, c0, #0, x20, x21 +// CHECK-ENCODING: encoding: [0x14,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482014 <unknown> + +sysp #0, c2, c0, #0, x22, x23 +// CHECK-INST: sysp #0, c2, c0, #0, x22, x23 +// CHECK-ENCODING: encoding: [0x16,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482016 <unknown> + +sysp #0, c2, c0, #0, x24, x25 +// CHECK-INST: sysp #0, c2, c0, #0, x24, x25 +// CHECK-ENCODING: encoding: [0x18,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5482018 <unknown> + +sysp #0, c2, c0, #0, x26, x27 +// CHECK-INST: sysp #0, c2, c0, #0, x26, x27 +// CHECK-ENCODING: encoding: [0x1a,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201a <unknown> + +sysp #0, c2, c0, #0, x28, x29 +// CHECK-INST: sysp #0, c2, c0, #0, x28, x29 +// CHECK-ENCODING: encoding: [0x1c,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201c <unknown> + +sysp #0, c2, c0, #0, x30, x31 +// CHECK-INST: sysp #0, c2, c0, #0, x30, xzr +// CHECK-ENCODING: encoding: [0x1e,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201e <unknown> + + +sysp #0, c2, c0, #0, x31, x31 +// CHECK-INST: sysp #0, c2, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201f <unknown> + +sysp #0, c2, c0, #0, xzr, xzr +// CHECK-INST: sysp #0, c2, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201f <unknown> + +sysp #0, c2, c0, #0, x31, xzr +// CHECK-INST: sysp #0, c2, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201f <unknown> + +sysp #0, c2, c0, #0, xzr, x31 +// CHECK-INST: sysp #0, c2, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201f <unknown> + +sysp #0, c2, c0, #0 +// CHECK-INST: sysp #0, c2, c0, #0 +// CHECK-ENCODING: encoding: [0x1f,0x20,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d548201f <unknown> + +tlbip IPAS2E1, x4, x5 +// CHECK-INST: tlbip ipas2e1, x4, x5 +// CHECK-ENCODING: encoding: [0x24,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c8424 <unknown> + +tlbip IPAS2E1NXS, x4, x5 +// CHECK-INST: tlbip ipas2e1nxs, x4, x5 +// CHECK-ENCODING: encoding: [0x24,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c9424 <unknown> + +tlbip IPAS2E1IS, x4, x5 +// CHECK-INST: tlbip ipas2e1is, x4, x5 +// CHECK-ENCODING: encoding: [0x24,0x80,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c8024 <unknown> + +tlbip IPAS2E1ISNXS, x4, x5 +// CHECK-INST: tlbip ipas2e1isnxs, x4, x5 +// CHECK-ENCODING: encoding: [0x24,0x90,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c9024 <unknown> + +tlbip IPAS2E1OS, x4, x5 +// CHECK-INST: tlbip ipas2e1os, x4, x5 +// CHECK-ENCODING: encoding: [0x04,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c8404 <unknown> + +tlbip IPAS2E1OSNXS, x4, x5 +// CHECK-INST: tlbip ipas2e1osnxs, x4, x5 +// CHECK-ENCODING: encoding: [0x04,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c9404 <unknown> + +tlbip IPAS2LE1, x4, x5 +// CHECK-INST: tlbip ipas2le1, x4, x5 +// CHECK-ENCODING: encoding: [0xa4,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c84a4 <unknown> + +tlbip IPAS2LE1NXS, x4, x5 +// CHECK-INST: tlbip ipas2le1nxs, x4, x5 +// CHECK-ENCODING: encoding: [0xa4,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c94a4 <unknown> + +tlbip IPAS2LE1IS, x4, x5 +// CHECK-INST: tlbip ipas2le1is, x4, x5 +// CHECK-ENCODING: encoding: [0xa4,0x80,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c80a4 <unknown> + +tlbip IPAS2LE1ISNXS, x4, x5 +// CHECK-INST: tlbip ipas2le1isnxs, x4, x5 +// CHECK-ENCODING: encoding: [0xa4,0x90,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c90a4 <unknown> + +tlbip IPAS2LE1OS, x4, x5 +// CHECK-INST: tlbip ipas2le1os, x4, x5 +// CHECK-ENCODING: encoding: [0x84,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c8484 <unknown> + +tlbip IPAS2LE1OSNXS, x4, x5 +// CHECK-INST: tlbip ipas2le1osnxs, x4, x5 +// CHECK-ENCODING: encoding: [0x84,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c9484 <unknown> + +tlbip VAE1, x8, x9 +// CHECK-INST: tlbip vae1, x8, x9 +// CHECK-ENCODING: encoding: [0x28,0x87,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488728 <unknown> + +tlbip VAE1NXS, x8, x9 +// CHECK-INST: tlbip vae1nxs, x8, x9 +// CHECK-ENCODING: encoding: [0x28,0x97,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489728 <unknown> + +tlbip VAE1IS, x8, x9 +// CHECK-INST: tlbip vae1is, x8, x9 +// CHECK-ENCODING: encoding: [0x28,0x83,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488328 <unknown> + +tlbip VAE1ISNXS, x8, x9 +// CHECK-INST: tlbip vae1isnxs, x8, x9 +// CHECK-ENCODING: encoding: [0x28,0x93,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489328 <unknown> + +tlbip VAE1OS, x8, x9 +// CHECK-INST: tlbip vae1os, x8, x9 +// CHECK-ENCODING: encoding: [0x28,0x81,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488128 <unknown> + +tlbip VAE1OSNXS, x8, x9 +// CHECK-INST: tlbip vae1osnxs, x8, x9 +// CHECK-ENCODING: encoding: [0x28,0x91,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489128 <unknown> + +tlbip VALE1, x8, x9 +// CHECK-INST: tlbip vale1, x8, x9 +// CHECK-ENCODING: encoding: [0xa8,0x87,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54887a8 <unknown> + +tlbip VALE1NXS, x8, x9 +// CHECK-INST: tlbip vale1nxs, x8, x9 +// CHECK-ENCODING: encoding: [0xa8,0x97,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54897a8 <unknown> + +tlbip VALE1IS, x8, x9 +// CHECK-INST: tlbip vale1is, x8, x9 +// CHECK-ENCODING: encoding: [0xa8,0x83,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54883a8 <unknown> + +tlbip VALE1ISNXS, x8, x9 +// CHECK-INST: tlbip vale1isnxs, x8, x9 +// CHECK-ENCODING: encoding: [0xa8,0x93,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54893a8 <unknown> + +tlbip VALE1OS, x8, x9 +// CHECK-INST: tlbip vale1os, x8, x9 +// CHECK-ENCODING: encoding: [0xa8,0x81,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54881a8 <unknown> + +tlbip VALE1OSNXS, x8, x9 +// CHECK-INST: tlbip vale1osnxs, x8, x9 +// CHECK-ENCODING: encoding: [0xa8,0x91,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54891a8 <unknown> + +tlbip VAAE1, x8, x9 +// CHECK-INST: tlbip vaae1, x8, x9 +// CHECK-ENCODING: encoding: [0x68,0x87,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488768 <unknown> + +tlbip VAAE1NXS, x8, x9 +// CHECK-INST: tlbip vaae1nxs, x8, x9 +// CHECK-ENCODING: encoding: [0x68,0x97,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489768 <unknown> + +tlbip VAAE1IS, x8, x9 +// CHECK-INST: tlbip vaae1is, x8, x9 +// CHECK-ENCODING: encoding: [0x68,0x83,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488368 <unknown> + +tlbip VAAE1ISNXS, x8, x9 +// CHECK-INST: tlbip vaae1isnxs, x8, x9 +// CHECK-ENCODING: encoding: [0x68,0x93,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489368 <unknown> + +tlbip VAAE1OS, x8, x9 +// CHECK-INST: tlbip vaae1os, x8, x9 +// CHECK-ENCODING: encoding: [0x68,0x81,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488168 <unknown> + +tlbip VAAE1OSNXS, x8, x9 +// CHECK-INST: tlbip vaae1osnxs, x8, x9 +// CHECK-ENCODING: encoding: [0x68,0x91,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489168 <unknown> + +tlbip VAALE1, x8, x9 +// CHECK-INST: tlbip vaale1, x8, x9 +// CHECK-ENCODING: encoding: [0xe8,0x87,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54887e8 <unknown> + +tlbip VAALE1NXS, x8, x9 +// CHECK-INST: tlbip vaale1nxs, x8, x9 +// CHECK-ENCODING: encoding: [0xe8,0x97,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54897e8 <unknown> + +tlbip VAALE1IS, x8, x9 +// CHECK-INST: tlbip vaale1is, x8, x9 +// CHECK-ENCODING: encoding: [0xe8,0x83,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54883e8 <unknown> + +tlbip VAALE1ISNXS, x8, x9 +// CHECK-INST: tlbip vaale1isnxs, x8, x9 +// CHECK-ENCODING: encoding: [0xe8,0x93,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54893e8 <unknown> + +tlbip VAALE1OS, x8, x9 +// CHECK-INST: tlbip vaale1os, x8, x9 +// CHECK-ENCODING: encoding: [0xe8,0x81,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54881e8 <unknown> + +tlbip VAALE1OSNXS, x8, x9 +// CHECK-INST: tlbip vaale1osnxs, x8, x9 +// CHECK-ENCODING: encoding: [0xe8,0x91,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54891e8 <unknown> + +tlbip VAE2, x14, x15 +// CHECK-INST: tlbip vae2, x14, x15 +// CHECK-ENCODING: encoding: [0x2e,0x87,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c872e <unknown> + +tlbip VAE2NXS, x14, x15 +// CHECK-INST: tlbip vae2nxs, x14, x15 +// CHECK-ENCODING: encoding: [0x2e,0x97,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c972e <unknown> + +tlbip VAE2IS, x14, x15 +// CHECK-INST: tlbip vae2is, x14, x15 +// CHECK-ENCODING: encoding: [0x2e,0x83,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c832e <unknown> + +tlbip VAE2ISNXS, x14, x15 +// CHECK-INST: tlbip vae2isnxs, x14, x15 +// CHECK-ENCODING: encoding: [0x2e,0x93,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c932e <unknown> + +tlbip VAE2OS, x14, x15 +// CHECK-INST: tlbip vae2os, x14, x15 +// CHECK-ENCODING: encoding: [0x2e,0x81,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c812e <unknown> + +tlbip VAE2OSNXS, x14, x15 +// CHECK-INST: tlbip vae2osnxs, x14, x15 +// CHECK-ENCODING: encoding: [0x2e,0x91,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c912e <unknown> + +tlbip VALE2, x14, x15 +// CHECK-INST: tlbip vale2, x14, x15 +// CHECK-ENCODING: encoding: [0xae,0x87,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c87ae <unknown> + +tlbip VALE2NXS, x14, x15 +// CHECK-INST: tlbip vale2nxs, x14, x15 +// CHECK-ENCODING: encoding: [0xae,0x97,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c97ae <unknown> + +tlbip VALE2IS, x14, x15 +// CHECK-INST: tlbip vale2is, x14, x15 +// CHECK-ENCODING: encoding: [0xae,0x83,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c83ae <unknown> + +tlbip VALE2ISNXS, x14, x15 +// CHECK-INST: tlbip vale2isnxs, x14, x15 +// CHECK-ENCODING: encoding: [0xae,0x93,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c93ae <unknown> + +tlbip VALE2OS, x14, x15 +// CHECK-INST: tlbip vale2os, x14, x15 +// CHECK-ENCODING: encoding: [0xae,0x81,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c81ae <unknown> + +tlbip VALE2OSNXS, x14, x15 +// CHECK-INST: tlbip vale2osnxs, x14, x15 +// CHECK-ENCODING: encoding: [0xae,0x91,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c91ae <unknown> + +tlbip VAE3, x24, x25 +// CHECK-INST: tlbip vae3, x24, x25 +// CHECK-ENCODING: encoding: [0x38,0x87,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e8738 <unknown> + +tlbip VAE3NXS, x24, x25 +// CHECK-INST: tlbip vae3nxs, x24, x25 +// CHECK-ENCODING: encoding: [0x38,0x97,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e9738 <unknown> + +tlbip VAE3IS, x24, x25 +// CHECK-INST: tlbip vae3is, x24, x25 +// CHECK-ENCODING: encoding: [0x38,0x83,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e8338 <unknown> + +tlbip VAE3ISNXS, x24, x25 +// CHECK-INST: tlbip vae3isnxs, x24, x25 +// CHECK-ENCODING: encoding: [0x38,0x93,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e9338 <unknown> + +tlbip VAE3OS, x24, x25 +// CHECK-INST: tlbip vae3os, x24, x25 +// CHECK-ENCODING: encoding: [0x38,0x81,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e8138 <unknown> + +tlbip VAE3OSNXS, x24, x25 +// CHECK-INST: tlbip vae3osnxs, x24, x25 +// CHECK-ENCODING: encoding: [0x38,0x91,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e9138 <unknown> + +tlbip VALE3, x24, x25 +// CHECK-INST: tlbip vale3, x24, x25 +// CHECK-ENCODING: encoding: [0xb8,0x87,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e87b8 <unknown> + +tlbip VALE3NXS, x24, x25 +// CHECK-INST: tlbip vale3nxs, x24, x25 +// CHECK-ENCODING: encoding: [0xb8,0x97,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e97b8 <unknown> + +tlbip VALE3IS, x24, x25 +// CHECK-INST: tlbip vale3is, x24, x25 +// CHECK-ENCODING: encoding: [0xb8,0x83,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e83b8 <unknown> + +tlbip VALE3ISNXS, x24, x25 +// CHECK-INST: tlbip vale3isnxs, x24, x25 +// CHECK-ENCODING: encoding: [0xb8,0x93,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e93b8 <unknown> + +tlbip VALE3OS, x24, x25 +// CHECK-INST: tlbip vale3os, x24, x25 +// CHECK-ENCODING: encoding: [0xb8,0x81,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e81b8 <unknown> + +tlbip VALE3OSNXS, x24, x25 +// CHECK-INST: tlbip vale3osnxs, x24, x25 +// CHECK-ENCODING: encoding: [0xb8,0x91,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e91b8 <unknown> + +tlbip RVAE1, x18, x19 +// CHECK-INST: tlbip rvae1, x18, x19 +// CHECK-ENCODING: encoding: [0x32,0x86,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488632 <unknown> + +tlbip RVAE1NXS, x18, x19 +// CHECK-INST: tlbip rvae1nxs, x18, x19 +// CHECK-ENCODING: encoding: [0x32,0x96,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489632 <unknown> + +tlbip RVAE1IS, x18, x19 +// CHECK-INST: tlbip rvae1is, x18, x19 +// CHECK-ENCODING: encoding: [0x32,0x82,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488232 <unknown> + +tlbip RVAE1ISNXS, x18, x19 +// CHECK-INST: tlbip rvae1isnxs, x18, x19 +// CHECK-ENCODING: encoding: [0x32,0x92,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489232 <unknown> + +tlbip RVAE1OS, x18, x19 +// CHECK-INST: tlbip rvae1os, x18, x19 +// CHECK-ENCODING: encoding: [0x32,0x85,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488532 <unknown> + +tlbip RVAE1OSNXS, x18, x19 +// CHECK-INST: tlbip rvae1osnxs, x18, x19 +// CHECK-ENCODING: encoding: [0x32,0x95,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489532 <unknown> + +tlbip RVAAE1, x18, x19 +// CHECK-INST: tlbip rvaae1, x18, x19 +// CHECK-ENCODING: encoding: [0x72,0x86,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488672 <unknown> + +tlbip RVAAE1NXS, x18, x19 +// CHECK-INST: tlbip rvaae1nxs, x18, x19 +// CHECK-ENCODING: encoding: [0x72,0x96,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489672 <unknown> + +tlbip RVAAE1IS, x18, x19 +// CHECK-INST: tlbip rvaae1is, x18, x19 +// CHECK-ENCODING: encoding: [0x72,0x82,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488272 <unknown> + +tlbip RVAAE1ISNXS, x18, x19 +// CHECK-INST: tlbip rvaae1isnxs, x18, x19 +// CHECK-ENCODING: encoding: [0x72,0x92,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489272 <unknown> + +tlbip RVAAE1OS, x18, x19 +// CHECK-INST: tlbip rvaae1os, x18, x19 +// CHECK-ENCODING: encoding: [0x72,0x85,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5488572 <unknown> + +tlbip RVAAE1OSNXS, x18, x19 +// CHECK-INST: tlbip rvaae1osnxs, x18, x19 +// CHECK-ENCODING: encoding: [0x72,0x95,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d5489572 <unknown> + +tlbip RVALE1, x18, x19 +// CHECK-INST: tlbip rvale1, x18, x19 +// CHECK-ENCODING: encoding: [0xb2,0x86,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54886b2 <unknown> + +tlbip RVALE1NXS, x18, x19 +// CHECK-INST: tlbip rvale1nxs, x18, x19 +// CHECK-ENCODING: encoding: [0xb2,0x96,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54896b2 <unknown> + +tlbip RVALE1IS, x18, x19 +// CHECK-INST: tlbip rvale1is, x18, x19 +// CHECK-ENCODING: encoding: [0xb2,0x82,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54882b2 <unknown> + +tlbip RVALE1ISNXS, x18, x19 +// CHECK-INST: tlbip rvale1isnxs, x18, x19 +// CHECK-ENCODING: encoding: [0xb2,0x92,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54892b2 <unknown> + +tlbip RVALE1OS, x18, x19 +// CHECK-INST: tlbip rvale1os, x18, x19 +// CHECK-ENCODING: encoding: [0xb2,0x85,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54885b2 <unknown> + +tlbip RVALE1OSNXS, x18, x19 +// CHECK-INST: tlbip rvale1osnxs, x18, x19 +// CHECK-ENCODING: encoding: [0xb2,0x95,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54895b2 <unknown> + +tlbip RVAALE1, x18, x19 +// CHECK-INST: tlbip rvaale1, x18, x19 +// CHECK-ENCODING: encoding: [0xf2,0x86,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54886f2 <unknown> + +tlbip RVAALE1NXS, x18, x19 +// CHECK-INST: tlbip rvaale1nxs, x18, x19 +// CHECK-ENCODING: encoding: [0xf2,0x96,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54896f2 <unknown> + +tlbip RVAALE1IS, x18, x19 +// CHECK-INST: tlbip rvaale1is, x18, x19 +// CHECK-ENCODING: encoding: [0xf2,0x82,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54882f2 <unknown> + +tlbip RVAALE1ISNXS, x18, x19 +// CHECK-INST: tlbip rvaale1isnxs, x18, x19 +// CHECK-ENCODING: encoding: [0xf2,0x92,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54892f2 <unknown> + +tlbip RVAALE1OS, x18, x19 +// CHECK-INST: tlbip rvaale1os, x18, x19 +// CHECK-ENCODING: encoding: [0xf2,0x85,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54885f2 <unknown> + +tlbip RVAALE1OSNXS, x18, x19 +// CHECK-INST: tlbip rvaale1osnxs, x18, x19 +// CHECK-ENCODING: encoding: [0xf2,0x95,0x48,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54895f2 <unknown> + +tlbip RVAE2, x28, x29 +// CHECK-INST: tlbip rvae2, x28, x29 +// CHECK-ENCODING: encoding: [0x3c,0x86,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c863c <unknown> + +tlbip RVAE2NXS, x28, x29 +// CHECK-INST: tlbip rvae2nxs, x28, x29 +// CHECK-ENCODING: encoding: [0x3c,0x96,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c963c <unknown> + +tlbip RVAE2IS, x28, x29 +// CHECK-INST: tlbip rvae2is, x28, x29 +// CHECK-ENCODING: encoding: [0x3c,0x82,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c823c <unknown> + +tlbip RVAE2ISNXS, x28, x29 +// CHECK-INST: tlbip rvae2isnxs, x28, x29 +// CHECK-ENCODING: encoding: [0x3c,0x92,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c923c <unknown> + +tlbip RVAE2OS, x28, x29 +// CHECK-INST: tlbip rvae2os, x28, x29 +// CHECK-ENCODING: encoding: [0x3c,0x85,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c853c <unknown> + +tlbip RVAE2OSNXS, x28, x29 +// CHECK-INST: tlbip rvae2osnxs, x28, x29 +// CHECK-ENCODING: encoding: [0x3c,0x95,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c953c <unknown> + +tlbip RVALE2, x28, x29 +// CHECK-INST: tlbip rvale2, x28, x29 +// CHECK-ENCODING: encoding: [0xbc,0x86,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c86bc <unknown> + +tlbip RVALE2NXS, x28, x29 +// CHECK-INST: tlbip rvale2nxs, x28, x29 +// CHECK-ENCODING: encoding: [0xbc,0x96,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c96bc <unknown> + +tlbip RVALE2IS, x28, x29 +// CHECK-INST: tlbip rvale2is, x28, x29 +// CHECK-ENCODING: encoding: [0xbc,0x82,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c82bc <unknown> + +tlbip RVALE2ISNXS, x28, x29 +// CHECK-INST: tlbip rvale2isnxs, x28, x29 +// CHECK-ENCODING: encoding: [0xbc,0x92,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c92bc <unknown> + +tlbip RVALE2OS, x28, x29 +// CHECK-INST: tlbip rvale2os, x28, x29 +// CHECK-ENCODING: encoding: [0xbc,0x85,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c85bc <unknown> + +tlbip RVALE2OSNXS, x28, x29 +// CHECK-INST: tlbip rvale2osnxs, x28, x29 +// CHECK-ENCODING: encoding: [0xbc,0x95,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c95bc <unknown> + +tlbip RVAE3, x10, x11 +// CHECK-INST: tlbip rvae3, x10, x11 +// CHECK-ENCODING: encoding: [0x2a,0x86,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e862a <unknown> + +tlbip RVAE3NXS, x10, x11 +// CHECK-INST: tlbip rvae3nxs, x10, x11 +// CHECK-ENCODING: encoding: [0x2a,0x96,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e962a <unknown> + +tlbip RVAE3IS, x10, x11 +// CHECK-INST: tlbip rvae3is, x10, x11 +// CHECK-ENCODING: encoding: [0x2a,0x82,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e822a <unknown> + +tlbip RVAE3ISNXS, x10, x11 +// CHECK-INST: tlbip rvae3isnxs, x10, x11 +// CHECK-ENCODING: encoding: [0x2a,0x92,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e922a <unknown> + +tlbip RVAE3OS, x10, x11 +// CHECK-INST: tlbip rvae3os, x10, x11 +// CHECK-ENCODING: encoding: [0x2a,0x85,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e852a <unknown> + +tlbip RVAE3OSNXS, x10, x11 +// CHECK-INST: tlbip rvae3osnxs, x10, x11 +// CHECK-ENCODING: encoding: [0x2a,0x95,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e952a <unknown> + +tlbip RVALE3, x10, x11 +// CHECK-INST: tlbip rvale3, x10, x11 +// CHECK-ENCODING: encoding: [0xaa,0x86,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e86aa <unknown> + +tlbip RVALE3NXS, x10, x11 +// CHECK-INST: tlbip rvale3nxs, x10, x11 +// CHECK-ENCODING: encoding: [0xaa,0x96,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e96aa <unknown> + +tlbip RVALE3IS, x10, x11 +// CHECK-INST: tlbip rvale3is, x10, x11 +// CHECK-ENCODING: encoding: [0xaa,0x82,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e82aa <unknown> + +tlbip RVALE3ISNXS, x10, x11 +// CHECK-INST: tlbip rvale3isnxs, x10, x11 +// CHECK-ENCODING: encoding: [0xaa,0x92,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e92aa <unknown> + +tlbip RVALE3OS, x10, x11 +// CHECK-INST: tlbip rvale3os, x10, x11 +// CHECK-ENCODING: encoding: [0xaa,0x85,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e85aa <unknown> + +tlbip RVALE3OSNXS, x10, x11 +// CHECK-INST: tlbip rvale3osnxs, x10, x11 +// CHECK-ENCODING: encoding: [0xaa,0x95,0x4e,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54e95aa <unknown> + +tlbip RIPAS2E1, x20, x21 +// CHECK-INST: tlbip ripas2e1, x20, x21 +// CHECK-ENCODING: encoding: [0x54,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c8454 <unknown> + +tlbip RIPAS2E1NXS, x20, x21 +// CHECK-INST: tlbip ripas2e1nxs, x20, x21 +// CHECK-ENCODING: encoding: [0x54,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c9454 <unknown> + +tlbip RIPAS2E1IS, x20, x21 +// CHECK-INST: tlbip ripas2e1is, x20, x21 +// CHECK-ENCODING: encoding: [0x54,0x80,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c8054 <unknown> + +tlbip RIPAS2E1ISNXS, x20, x21 +// CHECK-INST: tlbip ripas2e1isnxs, x20, x21 +// CHECK-ENCODING: encoding: [0x54,0x90,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c9054 <unknown> + +tlbip RIPAS2E1OS, x20, x21 +// CHECK-INST: tlbip ripas2e1os, x20, x21 +// CHECK-ENCODING: encoding: [0x74,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c8474 <unknown> + +tlbip RIPAS2E1OSNXS, x20, x21 +// CHECK-INST: tlbip ripas2e1osnxs, x20, x21 +// CHECK-ENCODING: encoding: [0x74,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c9474 <unknown> + +tlbip RIPAS2LE1, x20, x21 +// CHECK-INST: tlbip ripas2le1, x20, x21 +// CHECK-ENCODING: encoding: [0xd4,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c84d4 <unknown> + +tlbip RIPAS2LE1NXS, x20, x21 +// CHECK-INST: tlbip ripas2le1nxs, x20, x21 +// CHECK-ENCODING: encoding: [0xd4,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c94d4 <unknown> + +tlbip RIPAS2LE1IS, x20, x21 +// CHECK-INST: tlbip ripas2le1is, x20, x21 +// CHECK-ENCODING: encoding: [0xd4,0x80,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c80d4 <unknown> + +tlbip RIPAS2LE1ISNXS, x20, x21 +// CHECK-INST: tlbip ripas2le1isnxs, x20, x21 +// CHECK-ENCODING: encoding: [0xd4,0x90,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c90d4 <unknown> + +tlbip RIPAS2LE1OS, x20, x21 +// CHECK-INST: tlbip ripas2le1os, x20, x21 +// CHECK-ENCODING: encoding: [0xf4,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c84f4 <unknown> + +tlbip RIPAS2LE1OSNXS, x20, x21 +// CHECK-INST: tlbip ripas2le1osnxs, x20, x21 +// CHECK-ENCODING: encoding: [0xf4,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c94f4 <unknown> + +tlbip RIPAS2LE1OS, xzr, xzr +// CHECK-INST: tlbip ripas2le1os, xzr, xzr +// CHECK-ENCODING: encoding: [0xff,0x84,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c84ff <unknown> + +tlbip RIPAS2LE1OSNXS, xzr, xzr +// CHECK-INST: tlbip ripas2le1osnxs, xzr, xzr +// CHECK-ENCODING: encoding: [0xff,0x94,0x4c,0xd5] +// CHECK-ERROR: error: instruction requires: d128 +// CHECK-UNKNOWN: d54c94ff <unknown> diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s index 100fc981c4f8..91b3fcb9f660 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s @@ -52,3 +52,7 @@ s_setreg_b32 hwreg(34), s1 s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1 // GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU // GFX1250: encoding: [0x22,0xf8,0x01,0xb9] + +s_setreg_b32 hwreg(HW_REG_IB_STS2), s1 +// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU +// GFX1250: encoding: [0x1c,0xf8,0x01,0xb9] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s index 234c2ed0de79..bfc3544ac1b1 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s @@ -48,3 +48,10 @@ s_monitor_sleep 32768 s_monitor_sleep 0 // GFX1250: s_monitor_sleep 0 ; encoding: [0x00,0x00,0x84,0xbf] // GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU + +s_sendmsg sendmsg(MSG_SAVEWAVE_HAS_TDM) +// GFX1250: s_sendmsg sendmsg(MSG_SAVEWAVE_HAS_TDM) ; encoding: [0x0a,0x00,0xb6,0xbf] +// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU + +s_barrier_wait -3 +// GFX1250: s_barrier_wait -3 ; encoding: [0xfd,0xff,0x94,0xbf] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_sopp_err.s b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp_err.s new file mode 100644 index 000000000000..d151c9ac2f80 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp_err.s @@ -0,0 +1,4 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX1250-ERR --implicit-check-not=error: -strict-whitespace %s + +s_setkill 0 +// GFX1250-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt deleted file mode 100644 index 5b8d8170145f..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt +++ /dev/null @@ -1,75 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+fgt -disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT - -[0x80,0x11,0x1c,0xd5] -[0xa0,0x11,0x1c,0xd5] -[0xc0,0x11,0x1c,0xd5] -[0x80,0x31,0x1c,0xd5] -[0xa0,0x31,0x1c,0xd5] -[0xc0,0x31,0x1c,0xd5] - -# CHECK: msr HFGRTR_EL2, x0 -# CHECK: msr HFGWTR_EL2, x0 -# CHECK: msr HFGITR_EL2, x0 -# CHECK: msr HDFGRTR_EL2, x0 -# CHECK: msr HDFGWTR_EL2, x0 -# CHECK: msr HAFGRTR_EL2, x0 -# NOFGT: msr S3_4_C1_C1_4, x0 -# NOFGT: msr S3_4_C1_C1_5, x0 -# NOFGT: msr S3_4_C1_C1_6, x0 -# NOFGT: msr S3_4_C3_C1_4, x0 -# NOFGT: msr S3_4_C3_C1_5, x0 -# NOFGT: msr S3_4_C3_C1_6, x0 - -[0x80,0x11,0x3c,0xd5] -[0xa0,0x11,0x3c,0xd5] -[0xc0,0x11,0x3c,0xd5] -[0x80,0x31,0x3c,0xd5] -[0xa0,0x31,0x3c,0xd5] -[0xc0,0x31,0x3c,0xd5] - -# CHECK: mrs x0, HFGRTR_EL2 -# CHECK: mrs x0, HFGWTR_EL2 -# CHECK: mrs x0, HFGITR_EL2 -# CHECK: mrs x0, HDFGRTR_EL2 -# CHECK: mrs x0, HDFGWTR_EL2 -# CHECK: mrs x0, HAFGRTR_EL2 -# NOFGT: mrs x0, S3_4_C1_C1_4 -# NOFGT: mrs x0, S3_4_C1_C1_5 -# NOFGT: mrs x0, S3_4_C1_C1_6 -# NOFGT: mrs x0, S3_4_C3_C1_4 -# NOFGT: mrs x0, S3_4_C3_C1_5 -# NOFGT: mrs x0, S3_4_C3_C1_6 - -[0x03,0x31,0x3c,0xd5] -[0x23,0x31,0x3c,0xd5] -[0x43,0x31,0x3c,0xd5] -[0x63,0x31,0x3c,0xd5] -[0xe3,0x31,0x3c,0xd5] -# CHECK: mrs x3, HDFGRTR2_EL2 -# CHECK: mrs x3, HDFGWTR2_EL2 -# CHECK: mrs x3, HFGRTR2_EL2 -# CHECK: mrs x3, HFGWTR2_EL2 -# CHECK: mrs x3, HFGITR2_EL2 -# NOFGT: mrs x3, S3_4_C3_C1_0 -# NOFGT: mrs x3, S3_4_C3_C1_1 -# NOFGT: mrs x3, S3_4_C3_C1_2 -# NOFGT: mrs x3, S3_4_C3_C1_3 -# NOFGT: mrs x3, S3_4_C3_C1_7 - - -[0x03,0x31,0x1c,0xd5] -[0x23,0x31,0x1c,0xd5] -[0x43,0x31,0x1c,0xd5] -[0x63,0x31,0x1c,0xd5] -[0xe3,0x31,0x1c,0xd5] -# CHECK: msr HDFGRTR2_EL2, x3 -# CHECK: msr HDFGWTR2_EL2, x3 -# CHECK: msr HFGRTR2_EL2, x3 -# CHECK: msr HFGWTR2_EL2, x3 -# CHECK: msr HFGITR2_EL2, x3 -# NOFGT: msr S3_4_C3_C1_0, x3 -# NOFGT: msr S3_4_C3_C1_1, x3 -# NOFGT: msr S3_4_C3_C1_2, x3 -# NOFGT: msr S3_4_C3_C1_3, x3 -# NOFGT: msr S3_4_C3_C1_7, x3 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt b/llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt deleted file mode 100644 index de7121c3b397..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.8a-mops.txt +++ /dev/null @@ -1,434 +0,0 @@ -# RUN: not llvm-mc -triple aarch64 -mattr=+mops,+mte -disassemble < %s 2> %t | FileCheck %s --check-prefixes=CHECK-MOPS,CHECK-MTE -# RUN: FileCheck %s --check-prefix=CHECK-INVALID < %t -# RUN: not llvm-mc -triple aarch64 -mattr=+v8.8a,+mte -disassemble < %s 2> %t | FileCheck %s --check-prefixes=CHECK-MOPS,CHECK-MTE -# RUN: FileCheck %s --check-prefix=CHECK-INVALID < %t -# RUN: not llvm-mc -triple aarch64 -mattr=+mops -disassemble < %s 2> %t | FileCheck %s --check-prefix=CHECK-MOPS -# RUN: FileCheck %s --check-prefixes=CHECK-INVALID,CHECK-NO-MTE < %t -# RUN: not llvm-mc -triple aarch64 -mattr=+v8.8a -disassemble < %s 2> %t | FileCheck %s --check-prefix=CHECK-MOPS -# RUN: FileCheck %s --check-prefixes=CHECK-INVALID,CHECK-NO-MTE < %t -# RUN: not llvm-mc -triple aarch64 -disassemble < %s 2> %t -# RUN: FileCheck %s --check-prefixes=CHECK-INVALID,CHECK-NO-MOPS,CHECK-NO-MTE < %t - - -[0x40,0x04,0x01,0x19] -[0x40,0x44,0x01,0x19] -[0x40,0x84,0x01,0x19] -[0x40,0xc4,0x01,0x19] -[0x40,0x14,0x01,0x19] -[0x40,0x54,0x01,0x19] -[0x40,0x94,0x01,0x19] -[0x40,0xd4,0x01,0x19] -[0x40,0x24,0x01,0x19] -[0x40,0x64,0x01,0x19] -[0x40,0xa4,0x01,0x19] -[0x40,0xe4,0x01,0x19] -[0x40,0x34,0x01,0x19] -[0x40,0x74,0x01,0x19] -[0x40,0xb4,0x01,0x19] -[0x40,0xf4,0x01,0x19] -# CHECK-MOPS: cpyfp [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfpwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfprn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfpn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfpwt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfpwtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfpwtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfpwtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfprt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfprtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfprtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfprtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfpt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfptwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfptrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfptn [x0]!, [x1]!, x2! -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x40,0x04,0x41,0x19] -[0x40,0x44,0x41,0x19] -[0x40,0x84,0x41,0x19] -[0x40,0xc4,0x41,0x19] -[0x40,0x14,0x41,0x19] -[0x40,0x54,0x41,0x19] -[0x40,0x94,0x41,0x19] -[0x40,0xd4,0x41,0x19] -[0x40,0x24,0x41,0x19] -[0x40,0x64,0x41,0x19] -[0x40,0xa4,0x41,0x19] -[0x40,0xe4,0x41,0x19] -[0x40,0x34,0x41,0x19] -[0x40,0x74,0x41,0x19] -[0x40,0xb4,0x41,0x19] -[0x40,0xf4,0x41,0x19] -# CHECK-MOPS: cpyfm [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmwt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmwtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmwtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmwtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmrt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmrtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmrtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmrtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfmtn [x0]!, [x1]!, x2! -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x40,0x04,0x81,0x19] -[0x40,0x44,0x81,0x19] -[0x40,0x84,0x81,0x19] -[0x40,0xc4,0x81,0x19] -[0x40,0x14,0x81,0x19] -[0x40,0x54,0x81,0x19] -[0x40,0x94,0x81,0x19] -[0x40,0xd4,0x81,0x19] -[0x40,0x24,0x81,0x19] -[0x40,0x64,0x81,0x19] -[0x40,0xa4,0x81,0x19] -[0x40,0xe4,0x81,0x19] -[0x40,0x34,0x81,0x19] -[0x40,0x74,0x81,0x19] -[0x40,0xb4,0x81,0x19] -[0x40,0xf4,0x81,0x19] -# CHECK-MOPS: cpyfe [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfewn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfern [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfen [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfewt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfewtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfewtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfewtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfert [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfertwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfertrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfertn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfet [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfetwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfetrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyfetn [x0]!, [x1]!, x2! -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x40,0x04,0x01,0x1d] -[0x40,0x44,0x01,0x1d] -[0x40,0x84,0x01,0x1d] -[0x40,0xc4,0x01,0x1d] -[0x40,0x14,0x01,0x1d] -[0x40,0x54,0x01,0x1d] -[0x40,0x94,0x01,0x1d] -[0x40,0xd4,0x01,0x1d] -[0x40,0x24,0x01,0x1d] -[0x40,0x64,0x01,0x1d] -[0x40,0xa4,0x01,0x1d] -[0x40,0xe4,0x01,0x1d] -[0x40,0x34,0x01,0x1d] -[0x40,0x74,0x01,0x1d] -[0x40,0xb4,0x01,0x1d] -[0x40,0xf4,0x01,0x1d] -# CHECK-MOPS: cpyp [x0]!, [x1]!, x2! -# CHECK-MOPS: cpypwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyprn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpypn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpypwt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpypwtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpypwtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpypwtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyprt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyprtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyprtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyprtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpypt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyptwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyptrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyptn [x0]!, [x1]!, x2! -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x40,0x04,0x41,0x1d] -[0x40,0x44,0x41,0x1d] -[0x40,0x84,0x41,0x1d] -[0x40,0xc4,0x41,0x1d] -[0x40,0x14,0x41,0x1d] -[0x40,0x54,0x41,0x1d] -[0x40,0x94,0x41,0x1d] -[0x40,0xd4,0x41,0x1d] -[0x40,0x24,0x41,0x1d] -[0x40,0x64,0x41,0x1d] -[0x40,0xa4,0x41,0x1d] -[0x40,0xe4,0x41,0x1d] -[0x40,0x34,0x41,0x1d] -[0x40,0x74,0x41,0x1d] -[0x40,0xb4,0x41,0x1d] -[0x40,0xf4,0x41,0x1d] -# CHECK-MOPS: cpym [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymwt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymwtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymwtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymwtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymrt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymrtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymrtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymrtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpymtn [x0]!, [x1]!, x2! -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x40,0x04,0x81,0x1d] -[0x40,0x44,0x81,0x1d] -[0x40,0x84,0x81,0x1d] -[0x40,0xc4,0x81,0x1d] -[0x40,0x14,0x81,0x1d] -[0x40,0x54,0x81,0x1d] -[0x40,0x94,0x81,0x1d] -[0x40,0xd4,0x81,0x1d] -[0x40,0x24,0x81,0x1d] -[0x40,0x64,0x81,0x1d] -[0x40,0xa4,0x81,0x1d] -[0x40,0xe4,0x81,0x1d] -[0x40,0x34,0x81,0x1d] -[0x40,0x74,0x81,0x1d] -[0x40,0xb4,0x81,0x1d] -[0x40,0xf4,0x81,0x1d] -# CHECK-MOPS: cpye [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyewn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyern [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyen [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyewt [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyewtwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyewtrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyewtn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyert [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyertwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyertrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyertn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyet [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyetwn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyetrn [x0]!, [x1]!, x2! -# CHECK-MOPS: cpyetn [x0]!, [x1]!, x2! -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x20,0x04,0xc2,0x19] -[0x20,0x14,0xc2,0x19] -[0x20,0x24,0xc2,0x19] -[0x20,0x34,0xc2,0x19] -# CHECK-MOPS: setp [x0]!, x1!, x2 -# CHECK-MOPS: setpt [x0]!, x1!, x2 -# CHECK-MOPS: setpn [x0]!, x1!, x2 -# CHECK-MOPS: setptn [x0]!, x1!, x2 -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x20,0x44,0xc2,0x19] -[0x20,0x54,0xc2,0x19] -[0x20,0x64,0xc2,0x19] -[0x20,0x74,0xc2,0x19] -# CHECK-MOPS: setm [x0]!, x1!, x2 -# CHECK-MOPS: setmt [x0]!, x1!, x2 -# CHECK-MOPS: setmn [x0]!, x1!, x2 -# CHECK-MOPS: setmtn [x0]!, x1!, x2 -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x20,0x84,0xc2,0x19] -[0x20,0x94,0xc2,0x19] -[0x20,0xa4,0xc2,0x19] -[0x20,0xb4,0xc2,0x19] -# CHECK-MOPS: sete [x0]!, x1!, x2 -# CHECK-MOPS: setet [x0]!, x1!, x2 -# CHECK-MOPS: seten [x0]!, x1!, x2 -# CHECK-MOPS: setetn [x0]!, x1!, x2 -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding -# CHECK-NO-MOPS: warning: invalid instruction encoding - -[0x20,0x04,0xc2,0x1d] -[0x20,0x14,0xc2,0x1d] -[0x20,0x24,0xc2,0x1d] -[0x20,0x34,0xc2,0x1d] -# CHECK-MTE: setgp [x0]!, x1!, x2 -# CHECK-MTE: setgpt [x0]!, x1!, x2 -# CHECK-MTE: setgpn [x0]!, x1!, x2 -# CHECK-MTE: setgptn [x0]!, x1!, x2 -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding - -[0x20,0x44,0xc2,0x1d] -[0x20,0x54,0xc2,0x1d] -[0x20,0x64,0xc2,0x1d] -[0x20,0x74,0xc2,0x1d] -# CHECK-MTE: setgm [x0]!, x1!, x2 -# CHECK-MTE: setgmt [x0]!, x1!, x2 -# CHECK-MTE: setgmn [x0]!, x1!, x2 -# CHECK-MTE: setgmtn [x0]!, x1!, x2 -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding - -[0x20,0x84,0xc2,0x1d] -[0x20,0x94,0xc2,0x1d] -[0x20,0xa4,0xc2,0x1d] -[0x20,0xb4,0xc2,0x1d] -# CHECK-MTE: setge [x0]!, x1!, x2 -# CHECK-MTE: setget [x0]!, x1!, x2 -# CHECK-MTE: setgen [x0]!, x1!, x2 -# CHECK-MTE: setgetn [x0]!, x1!, x2 -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding -# CHECK-NO-MTE: warning: invalid instruction encoding - - -# Register number 31 (SP or XZR) is not allowed in address positions. -# cpyfp -[0x5f,0x04,0x01,0x19] -[0x40,0x04,0x1f,0x19] -# cpyfm -[0x5f,0x04,0x41,0x19] -[0x40,0x04,0x5f,0x19] -# cpyfe -[0x5f,0x04,0x81,0x19] -[0x40,0x04,0x9f,0x19] -# cpyp -[0x5f,0x04,0x01,0x1d] -[0x40,0x04,0x1f,0x1d] -# cpym -[0x5f,0x04,0x41,0x1d] -[0x40,0x04,0x5f,0x1d] -# cpye -[0x5f,0x04,0x81,0x1d] -[0x40,0x04,0x9f,0x1d] -# setp -[0x5f,0x04,0xc2,0x19] -# setm -[0x5f,0x44,0xc2,0x19] -# sete -[0x5f,0x84,0xc2,0x19] -# setgp -[0x5f,0x04,0xc2,0x1d] -# setgm -[0x5f,0x44,0xc2,0x1d] -# setge -[0x5f,0x84,0xc2,0x1d] -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding -# CHECK-INVALID: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-ats1a.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-ats1a.txt deleted file mode 100644 index 03aca5e916db..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.9a-ats1a.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s - -[0x41,0x79,0x08,0xd5] -# CHECK: at s1e1a, x1 - -[0x41,0x79,0x0c,0xd5] -# CHECK: at s1e2a, x1 - -[0x41,0x79,0x0e,0xd5] -# CHECK: at s1e3a, x1 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-clrbhb.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-clrbhb.txt deleted file mode 100644 index f8c7e9fa1a15..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.9a-clrbhb.txt +++ /dev/null @@ -1,16 +0,0 @@ -# CLRBHB is optional for all v8a/v9a, mandatory for 8.9a/9.4a. -# Should disassemble to hint #22 if the feature is not present. -# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a,-clrbhb %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a,-clrbhb %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+clrbhb %s | FileCheck %s --check-prefix=CLRBHB -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a,+clrbhb %s | FileCheck %s --check-prefix=CLRBHB -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a %s | FileCheck %s --check-prefix=CLRBHB -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a,+clrbhb %s | FileCheck %s --check-prefix=CLRBHB -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a %s | FileCheck %s --check-prefix=CLRBHB - -[0xdf,0x22,0x03,0xd5] -# CLRBHB: clrbhb -# HINT_22: hint #22 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt deleted file mode 100644 index ff898fec0c92..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt +++ /dev/null @@ -1,730 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+ite -disassemble %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -mattr=+ite -disassemble %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v9.3a -mattr=+ite -disassemble %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -mattr=+ite -disassemble %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -mattr=+ite -disassemble %s | FileCheck %s - -# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE -# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE -# RUN: llvm-mc -triple=aarch64 -mattr=+v9.3a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE -# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE -# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE - -[0x83,0x00,0x30,0xd5] -# CHECK: mrs x3, DBGBVR0_EL1 -[0x81,0x00,0x10,0xd5] -# CHECK: msr DBGBVR0_EL1, x1 -[0x83,0x01,0x30,0xd5] -# CHECK: mrs x3, DBGBVR1_EL1 -[0x81,0x01,0x10,0xd5] -# CHECK: msr DBGBVR1_EL1, x1 -[0x83,0x02,0x30,0xd5] -# CHECK: mrs x3, DBGBVR2_EL1 -[0x81,0x02,0x10,0xd5] -# CHECK: msr DBGBVR2_EL1, x1 -[0x83,0x03,0x30,0xd5] -# CHECK: mrs x3, DBGBVR3_EL1 -[0x81,0x03,0x10,0xd5] -# CHECK: msr DBGBVR3_EL1, x1 -[0x83,0x04,0x30,0xd5] -# CHECK: mrs x3, DBGBVR4_EL1 -[0x81,0x04,0x10,0xd5] -# CHECK: msr DBGBVR4_EL1, x1 -[0x83,0x05,0x30,0xd5] -# CHECK: mrs x3, DBGBVR5_EL1 -[0x81,0x05,0x10,0xd5] -# CHECK: msr DBGBVR5_EL1, x1 -[0x83,0x06,0x30,0xd5] -# CHECK: mrs x3, DBGBVR6_EL1 -[0x81,0x06,0x10,0xd5] -# CHECK: msr DBGBVR6_EL1, x1 -[0x83,0x07,0x30,0xd5] -# CHECK: mrs x3, DBGBVR7_EL1 -[0x81,0x07,0x10,0xd5] -# CHECK: msr DBGBVR7_EL1, x1 -[0x83,0x08,0x30,0xd5] -# CHECK: mrs x3, DBGBVR8_EL1 -[0x81,0x08,0x10,0xd5] -# CHECK: msr DBGBVR8_EL1, x1 -[0x83,0x09,0x30,0xd5] -# CHECK: mrs x3, DBGBVR9_EL1 -[0x81,0x09,0x10,0xd5] -# CHECK: msr DBGBVR9_EL1, x1 -[0x83,0x0a,0x30,0xd5] -# CHECK: mrs x3, DBGBVR10_EL1 -[0x81,0x0a,0x10,0xd5] -# CHECK: msr DBGBVR10_EL1, x1 -[0x83,0x0b,0x30,0xd5] -# CHECK: mrs x3, DBGBVR11_EL1 -[0x81,0x0b,0x10,0xd5] -# CHECK: msr DBGBVR11_EL1, x1 -[0x83,0x0c,0x30,0xd5] -# CHECK: mrs x3, DBGBVR12_EL1 -[0x81,0x0c,0x10,0xd5] -# CHECK: msr DBGBVR12_EL1, x1 -[0x83,0x0d,0x30,0xd5] -# CHECK: mrs x3, DBGBVR13_EL1 -[0x81,0x0d,0x10,0xd5] -# CHECK: msr DBGBVR13_EL1, x1 -[0x83,0x0e,0x30,0xd5] -# CHECK: mrs x3, DBGBVR14_EL1 -[0x81,0x0e,0x10,0xd5] -# CHECK: msr DBGBVR14_EL1, x1 -[0x83,0x0f,0x30,0xd5] -# CHECK: mrs x3, DBGBVR15_EL1 -[0x81,0x0f,0x10,0xd5] -# CHECK: msr DBGBVR15_EL1, x1 - -[0xa3,0x00,0x30,0xd5] -# CHECK: mrs x3, DBGBCR0_EL1 -[0xa1,0x00,0x10,0xd5] -# CHECK: msr DBGBCR0_EL1, x1 -[0xa3,0x01,0x30,0xd5] -# CHECK: mrs x3, DBGBCR1_EL1 -[0xa1,0x01,0x10,0xd5] -# CHECK: msr DBGBCR1_EL1, x1 -[0xa3,0x02,0x30,0xd5] -# CHECK: mrs x3, DBGBCR2_EL1 -[0xa1,0x02,0x10,0xd5] -# CHECK: msr DBGBCR2_EL1, x1 -[0xa3,0x03,0x30,0xd5] -# CHECK: mrs x3, DBGBCR3_EL1 -[0xa1,0x03,0x10,0xd5] -# CHECK: msr DBGBCR3_EL1, x1 -[0xa3,0x04,0x30,0xd5] -# CHECK: mrs x3, DBGBCR4_EL1 -[0xa1,0x04,0x10,0xd5] -# CHECK: msr DBGBCR4_EL1, x1 -[0xa3,0x05,0x30,0xd5] -# CHECK: mrs x3, DBGBCR5_EL1 -[0xa1,0x05,0x10,0xd5] -# CHECK: msr DBGBCR5_EL1, x1 -[0xa3,0x06,0x30,0xd5] -# CHECK: mrs x3, DBGBCR6_EL1 -[0xa1,0x06,0x10,0xd5] -# CHECK: msr DBGBCR6_EL1, x1 -[0xa3,0x07,0x30,0xd5] -# CHECK: mrs x3, DBGBCR7_EL1 -[0xa1,0x07,0x10,0xd5] -# CHECK: msr DBGBCR7_EL1, x1 -[0xa3,0x08,0x30,0xd5] -# CHECK: mrs x3, DBGBCR8_EL1 -[0xa1,0x08,0x10,0xd5] -# CHECK: msr DBGBCR8_EL1, x1 -[0xa3,0x09,0x30,0xd5] -# CHECK: mrs x3, DBGBCR9_EL1 -[0xa1,0x09,0x10,0xd5] -# CHECK: msr DBGBCR9_EL1, x1 -[0xa3,0x0a,0x30,0xd5] -# CHECK: mrs x3, DBGBCR10_EL1 -[0xa1,0x0a,0x10,0xd5] -# CHECK: msr DBGBCR10_EL1, x1 -[0xa3,0x0b,0x30,0xd5] -# CHECK: mrs x3, DBGBCR11_EL1 -[0xa1,0x0b,0x10,0xd5] -# CHECK: msr DBGBCR11_EL1, x1 -[0xa3,0x0c,0x30,0xd5] -# CHECK: mrs x3, DBGBCR12_EL1 -[0xa1,0x0c,0x10,0xd5] -# CHECK: msr DBGBCR12_EL1, x1 -[0xa3,0x0d,0x30,0xd5] -# CHECK: mrs x3, DBGBCR13_EL1 -[0xa1,0x0d,0x10,0xd5] -# CHECK: msr DBGBCR13_EL1, x1 -[0xa3,0x0e,0x30,0xd5] -# CHECK: mrs x3, DBGBCR14_EL1 -[0xa1,0x0e,0x10,0xd5] -# CHECK: msr DBGBCR14_EL1, x1 -[0xa3,0x0f,0x30,0xd5] -# CHECK: mrs x3, DBGBCR15_EL1 -[0xa1,0x0f,0x10,0xd5] -# CHECK: msr DBGBCR15_EL1, x1 - -[0xc3,0x00,0x30,0xd5] -# CHECK: mrs x3, DBGWVR0_EL1 -[0xc1,0x00,0x10,0xd5] -# CHECK: msr DBGWVR0_EL1, x1 -[0xc3,0x01,0x30,0xd5] -# CHECK: mrs x3, DBGWVR1_EL1 -[0xc1,0x01,0x10,0xd5] -# CHECK: msr DBGWVR1_EL1, x1 -[0xc3,0x02,0x30,0xd5] -# CHECK: mrs x3, DBGWVR2_EL1 -[0xc1,0x02,0x10,0xd5] -# CHECK: msr DBGWVR2_EL1, x1 -[0xc3,0x03,0x30,0xd5] -# CHECK: mrs x3, DBGWVR3_EL1 -[0xc1,0x03,0x10,0xd5] -# CHECK: msr DBGWVR3_EL1, x1 -[0xc3,0x04,0x30,0xd5] -# CHECK: mrs x3, DBGWVR4_EL1 -[0xc1,0x04,0x10,0xd5] -# CHECK: msr DBGWVR4_EL1, x1 -[0xc3,0x05,0x30,0xd5] -# CHECK: mrs x3, DBGWVR5_EL1 -[0xc1,0x05,0x10,0xd5] -# CHECK: msr DBGWVR5_EL1, x1 -[0xc3,0x06,0x30,0xd5] -# CHECK: mrs x3, DBGWVR6_EL1 -[0xc1,0x06,0x10,0xd5] -# CHECK: msr DBGWVR6_EL1, x1 -[0xc3,0x07,0x30,0xd5] -# CHECK: mrs x3, DBGWVR7_EL1 -[0xc1,0x07,0x10,0xd5] -# CHECK: msr DBGWVR7_EL1, x1 -[0xc3,0x08,0x30,0xd5] -# CHECK: mrs x3, DBGWVR8_EL1 -[0xc1,0x08,0x10,0xd5] -# CHECK: msr DBGWVR8_EL1, x1 -[0xc3,0x09,0x30,0xd5] -# CHECK: mrs x3, DBGWVR9_EL1 -[0xc1,0x09,0x10,0xd5] -# CHECK: msr DBGWVR9_EL1, x1 -[0xc3,0x0a,0x30,0xd5] -# CHECK: mrs x3, DBGWVR10_EL1 -[0xc1,0x0a,0x10,0xd5] -# CHECK: msr DBGWVR10_EL1, x1 -[0xc3,0x0b,0x30,0xd5] -# CHECK: mrs x3, DBGWVR11_EL1 -[0xc1,0x0b,0x10,0xd5] -# CHECK: msr DBGWVR11_EL1, x1 -[0xc3,0x0c,0x30,0xd5] -# CHECK: mrs x3, DBGWVR12_EL1 -[0xc1,0x0c,0x10,0xd5] -# CHECK: msr DBGWVR12_EL1, x1 -[0xc3,0x0d,0x30,0xd5] -# CHECK: mrs x3, DBGWVR13_EL1 -[0xc1,0x0d,0x10,0xd5] -# CHECK: msr DBGWVR13_EL1, x1 -[0xc3,0x0e,0x30,0xd5] -# CHECK: mrs x3, DBGWVR14_EL1 -[0xc1,0x0e,0x10,0xd5] -# CHECK: msr DBGWVR14_EL1, x1 -[0xc3,0x0f,0x30,0xd5] -# CHECK: mrs x3, DBGWVR15_EL1 -[0xc1,0x0f,0x10,0xd5] -# CHECK: msr DBGWVR15_EL1, x1 - -[0xe3,0x00,0x30,0xd5] -# CHECK: mrs x3, DBGWCR0_EL1 -[0xe1,0x00,0x10,0xd5] -# CHECK: msr DBGWCR0_EL1, x1 -[0xe3,0x01,0x30,0xd5] -# CHECK: mrs x3, DBGWCR1_EL1 -[0xe1,0x01,0x10,0xd5] -# CHECK: msr DBGWCR1_EL1, x1 -[0xe3,0x02,0x30,0xd5] -# CHECK: mrs x3, DBGWCR2_EL1 -[0xe1,0x02,0x10,0xd5] -# CHECK: msr DBGWCR2_EL1, x1 -[0xe3,0x03,0x30,0xd5] -# CHECK: mrs x3, DBGWCR3_EL1 -[0xe1,0x03,0x10,0xd5] -# CHECK: msr DBGWCR3_EL1, x1 -[0xe3,0x04,0x30,0xd5] -# CHECK: mrs x3, DBGWCR4_EL1 -[0xe1,0x04,0x10,0xd5] -# CHECK: msr DBGWCR4_EL1, x1 -[0xe3,0x05,0x30,0xd5] -# CHECK: mrs x3, DBGWCR5_EL1 -[0xe1,0x05,0x10,0xd5] -# CHECK: msr DBGWCR5_EL1, x1 -[0xe3,0x06,0x30,0xd5] -# CHECK: mrs x3, DBGWCR6_EL1 -[0xe1,0x06,0x10,0xd5] -# CHECK: msr DBGWCR6_EL1, x1 -[0xe3,0x07,0x30,0xd5] -# CHECK: mrs x3, DBGWCR7_EL1 -[0xe1,0x07,0x10,0xd5] -# CHECK: msr DBGWCR7_EL1, x1 -[0xe3,0x08,0x30,0xd5] -# CHECK: mrs x3, DBGWCR8_EL1 -[0xe1,0x08,0x10,0xd5] -# CHECK: msr DBGWCR8_EL1, x1 -[0xe3,0x09,0x30,0xd5] -# CHECK: mrs x3, DBGWCR9_EL1 -[0xe1,0x09,0x10,0xd5] -# CHECK: msr DBGWCR9_EL1, x1 -[0xe3,0x0a,0x30,0xd5] -# CHECK: mrs x3, DBGWCR10_EL1 -[0xe1,0x0a,0x10,0xd5] -# CHECK: msr DBGWCR10_EL1, x1 -[0xe3,0x0b,0x30,0xd5] -# CHECK: mrs x3, DBGWCR11_EL1 -[0xe1,0x0b,0x10,0xd5] -# CHECK: msr DBGWCR11_EL1, x1 -[0xe3,0x0c,0x30,0xd5] -# CHECK: mrs x3, DBGWCR12_EL1 -[0xe1,0x0c,0x10,0xd5] -# CHECK: msr DBGWCR12_EL1, x1 -[0xe3,0x0d,0x30,0xd5] -# CHECK: mrs x3, DBGWCR13_EL1 -[0xe1,0x0d,0x10,0xd5] -# CHECK: msr DBGWCR13_EL1, x1 -[0xe3,0x0e,0x30,0xd5] -# CHECK: mrs x3, DBGWCR14_EL1 -[0xe1,0x0e,0x10,0xd5] -# CHECK: msr DBGWCR14_EL1, x1 -[0xe3,0x0f,0x30,0xd5] -# CHECK: mrs x3, DBGWCR15_EL1 -[0xe1,0x0f,0x10,0xd5] -# CHECK: msr DBGWCR15_EL1, x1 - -[0x43,0x04,0x30,0xd5] -# CHECK: mrs x3, MDSELR_EL1 -[0x41,0x04,0x10,0xd5] -# CHECK: msr MDSELR_EL1, x1 - -[0x83,0x9e,0x38,0xd5] -# CHECK: mrs x3, PMUACR_EL1 -[0x81,0x9e,0x18,0xd5] -# CHECK: msr PMUACR_EL1, x1 - -[0xe3,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMCCNTSVR_EL1 -[0x03,0xec,0x30,0xd5] -# CHECK: mrs x3, PMICNTSVR_EL1 -[0x63,0x9d,0x38,0xd5] -# CHECK: mrs x3, PMSSCR_EL1 -[0x61,0x9d,0x18,0xd5] -# CHECK: msr PMSSCR_EL1, x1 -[0x03,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR0_EL1 -[0x23,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR1_EL1 -[0x43,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR2_EL1 -[0x63,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR3_EL1 -[0x83,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR4_EL1 -[0xa3,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR5_EL1 -[0xc3,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR6_EL1 -[0xe3,0xe8,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR7_EL1 -[0x03,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR8_EL1 -[0x23,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR9_EL1 -[0x43,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR10_EL1 -[0x63,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR11_EL1 -[0x83,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR12_EL1 -[0xa3,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR13_EL1 -[0xc3,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR14_EL1 -[0xe3,0xe9,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR15_EL1 -[0x03,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR16_EL1 -[0x23,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR17_EL1 -[0x43,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR18_EL1 -[0x63,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR19_EL1 -[0x83,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR20_EL1 -[0xa3,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR21_EL1 -[0xc3,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR22_EL1 -[0xe3,0xea,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR23_EL1 -[0x03,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR24_EL1 -[0x23,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR25_EL1 -[0x43,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR26_EL1 -[0x63,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR27_EL1 -[0x83,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR28_EL1 -[0xa3,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR29_EL1 -[0xc3,0xeb,0x30,0xd5] -# CHECK: mrs x3, PMEVCNTSVR30_EL1 - -[0x03,0x94,0x3b,0xd5] -# CHECK: mrs x3, PMICNTR_EL0 -[0x03,0x94,0x1b,0xd5] -# CHECK: msr PMICNTR_EL0, x3 -[0x03,0x96,0x3b,0xd5] -# CHECK: mrs x3, PMICFILTR_EL0 -[0x03,0x96,0x1b,0xd5] -# CHECK: msr PMICFILTR_EL0, x3 - -[0x83,0x9d,0x1b,0xd5] -# CHECK: msr PMZR_EL0, x3 - -[0xa3,0x9e,0x38,0xd5] -# CHECK: mrs x3, PMECR_EL1 -[0xa1,0x9e,0x18,0xd5] -# CHECK: msr PMECR_EL1, x1 -[0xe3,0x9e,0x38,0xd5] -# CHECK: mrs x3, PMIAR_EL1 -[0xe1,0x9e,0x18,0xd5] -# CHECK: msr PMIAR_EL1, x1 - -[0x63,0x9d,0x30,0xd5] -# CHECK: mrs x3, SPMACCESSR_EL1 -[0x61,0x9d,0x10,0xd5] -# CHECK: msr SPMACCESSR_EL1, x1 -[0x63,0x9d,0x35,0xd5] -# CHECK: mrs x3, SPMACCESSR_EL12 -[0x61,0x9d,0x15,0xd5] -# CHECK: msr SPMACCESSR_EL12, x1 -[0x63,0x9d,0x34,0xd5] -# CHECK: mrs x3, SPMACCESSR_EL2 -[0x61,0x9d,0x14,0xd5] -# CHECK: msr SPMACCESSR_EL2, x1 -[0x63,0x9d,0x36,0xd5] -# CHECK: mrs x3, SPMACCESSR_EL3 -[0x61,0x9d,0x16,0xd5] -# CHECK: msr SPMACCESSR_EL3, x1 -[0x43,0x9c,0x33,0xd5] -# CHECK: mrs x3, SPMCNTENCLR_EL0 -[0x41,0x9c,0x13,0xd5] -# CHECK: msr SPMCNTENCLR_EL0, x1 -[0x23,0x9c,0x33,0xd5] -# CHECK: mrs x3, SPMCNTENSET_EL0 -[0x21,0x9c,0x13,0xd5] -# CHECK: msr SPMCNTENSET_EL0, x1 -[0x03,0x9c,0x33,0xd5] -# CHECK: mrs x3, SPMCR_EL0 -[0x01,0x9c,0x13,0xd5] -# CHECK: msr SPMCR_EL0, x1 -[0xc3,0x9d,0x30,0xd5] -# CHECK: mrs x3, SPMDEVAFF_EL1 -[0xa3,0x9d,0x30,0xd5] -# CHECK: mrs x3, SPMDEVARCH_EL1 - -[0x03,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR0_EL0 -[0x01,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR0_EL0, x1 -[0x23,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR1_EL0 -[0x21,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR1_EL0, x1 -[0x43,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR2_EL0 -[0x41,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR2_EL0, x1 -[0x63,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR3_EL0 -[0x61,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR3_EL0, x1 -[0x83,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR4_EL0 -[0x81,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR4_EL0, x1 -[0xa3,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR5_EL0 -[0xa1,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR5_EL0, x1 -[0xc3,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR6_EL0 -[0xc1,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR6_EL0, x1 -[0xe3,0xe0,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR7_EL0 -[0xe1,0xe0,0x13,0xd5] -# CHECK: msr SPMEVCNTR7_EL0, x1 -[0x03,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR8_EL0 -[0x01,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR8_EL0, x1 -[0x23,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR9_EL0 -[0x21,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR9_EL0, x1 -[0x43,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR10_EL0 -[0x41,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR10_EL0, x1 -[0x63,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR11_EL0 -[0x61,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR11_EL0, x1 -[0x83,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR12_EL0 -[0x81,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR12_EL0, x1 -[0xa3,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR13_EL0 -[0xa1,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR13_EL0, x1 -[0xc3,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR14_EL0 -[0xc1,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR14_EL0, x1 -[0xe3,0xe1,0x33,0xd5] -# CHECK: mrs x3, SPMEVCNTR15_EL0 -[0xe1,0xe1,0x13,0xd5] -# CHECK: msr SPMEVCNTR15_EL0, x1 - -[0x03,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R0_EL0 -[0x01,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R0_EL0, x1 -[0x23,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R1_EL0 -[0x21,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R1_EL0, x1 -[0x43,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R2_EL0 -[0x41,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R2_EL0, x1 -[0x63,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R3_EL0 -[0x61,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R3_EL0, x1 -[0x83,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R4_EL0 -[0x81,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R4_EL0, x1 -[0xa3,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R5_EL0 -[0xa1,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R5_EL0, x1 -[0xc3,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R6_EL0 -[0xc1,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R6_EL0, x1 -[0xe3,0xe6,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R7_EL0 -[0xe1,0xe6,0x13,0xd5] -# CHECK: msr SPMEVFILT2R7_EL0, x1 -[0x03,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R8_EL0 -[0x01,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R8_EL0, x1 -[0x23,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R9_EL0 -[0x21,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R9_EL0, x1 -[0x43,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R10_EL0 -[0x41,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R10_EL0, x1 -[0x63,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R11_EL0 -[0x61,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R11_EL0, x1 -[0x83,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R12_EL0 -[0x81,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R12_EL0, x1 -[0xa3,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R13_EL0 -[0xa1,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R13_EL0, x1 -[0xc3,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R14_EL0 -[0xc1,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R14_EL0, x1 -[0xe3,0xe7,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILT2R15_EL0 -[0xe1,0xe7,0x13,0xd5] -# CHECK: msr SPMEVFILT2R15_EL0, x1 - -[0x03,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR0_EL0 -[0x01,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR0_EL0, x1 -[0x23,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR1_EL0 -[0x21,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR1_EL0, x1 -[0x43,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR2_EL0 -[0x41,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR2_EL0, x1 -[0x63,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR3_EL0 -[0x61,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR3_EL0, x1 -[0x83,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR4_EL0 -[0x81,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR4_EL0, x1 -[0xa3,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR5_EL0 -[0xa1,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR5_EL0, x1 -[0xc3,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR6_EL0 -[0xc1,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR6_EL0, x1 -[0xe3,0xe4,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR7_EL0 -[0xe1,0xe4,0x13,0xd5] -# CHECK: msr SPMEVFILTR7_EL0, x1 -[0x03,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR8_EL0 -[0x01,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR8_EL0, x1 -[0x23,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR9_EL0 -[0x21,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR9_EL0, x1 -[0x43,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR10_EL0 -[0x41,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR10_EL0, x1 -[0x63,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR11_EL0 -[0x61,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR11_EL0, x1 -[0x83,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR12_EL0 -[0x81,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR12_EL0, x1 -[0xa3,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR13_EL0 -[0xa1,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR13_EL0, x1 -[0xc3,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR14_EL0 -[0xc1,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR14_EL0, x1 -[0xe3,0xe5,0x33,0xd5] -# CHECK: mrs x3, SPMEVFILTR15_EL0 -[0xe1,0xe5,0x13,0xd5] -# CHECK: msr SPMEVFILTR15_EL0, x1 - -[0x03,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER0_EL0 -[0x01,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER0_EL0, x1 -[0x23,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER1_EL0 -[0x21,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER1_EL0, x1 -[0x43,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER2_EL0 -[0x41,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER2_EL0, x1 -[0x63,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER3_EL0 -[0x61,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER3_EL0, x1 -[0x83,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER4_EL0 -[0x81,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER4_EL0, x1 -[0xa3,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER5_EL0 -[0xa1,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER5_EL0, x1 -[0xc3,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER6_EL0 -[0xc1,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER6_EL0, x1 -[0xe3,0xe2,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER7_EL0 -[0xe1,0xe2,0x13,0xd5] -# CHECK: msr SPMEVTYPER7_EL0, x1 -[0x03,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER8_EL0 -[0x01,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER8_EL0, x1 -[0x23,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER9_EL0 -[0x21,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER9_EL0, x1 -[0x43,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER10_EL0 -[0x41,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER10_EL0, x1 -[0x63,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER11_EL0 -[0x61,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER11_EL0, x1 -[0x83,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER12_EL0 -[0x81,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER12_EL0, x1 -[0xa3,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER13_EL0 -[0xa1,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER13_EL0, x1 -[0xc3,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER14_EL0 -[0xc1,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER14_EL0, x1 -[0xe3,0xe3,0x33,0xd5] -# CHECK: mrs x3, SPMEVTYPER15_EL0 -[0xe1,0xe3,0x13,0xd5] -# CHECK: msr SPMEVTYPER15_EL0, x1 - -[0x83,0x9d,0x30,0xd5] -# CHECK: mrs x3, SPMIIDR_EL1 -[0x43,0x9e,0x30,0xd5] -# CHECK: mrs x3, SPMINTENCLR_EL1 -[0x41,0x9e,0x10,0xd5] -# CHECK: msr SPMINTENCLR_EL1, x1 -[0x23,0x9e,0x30,0xd5] -# CHECK: mrs x3, SPMINTENSET_EL1 -[0x21,0x9e,0x10,0xd5] -# CHECK: msr SPMINTENSET_EL1, x1 -[0x63,0x9c,0x33,0xd5] -# CHECK: mrs x3, SPMOVSCLR_EL0 -[0x61,0x9c,0x13,0xd5] -# CHECK: msr SPMOVSCLR_EL0, x1 -[0x63,0x9e,0x33,0xd5] -# CHECK: mrs x3, SPMOVSSET_EL0 -[0x61,0x9e,0x13,0xd5] -# CHECK: msr SPMOVSSET_EL0, x1 -[0xa3,0x9c,0x33,0xd5] -# CHECK: mrs x3, SPMSELR_EL0 -[0xa1,0x9c,0x13,0xd5] -# CHECK: msr SPMSELR_EL0, x1 -[0x03,0x9d,0x30,0xd5] -# CHECK: mrs x3, SPMCGCR0_EL1 -[0x23,0x9d,0x30,0xd5] -# CHECK: mrs x3, SPMCGCR1_EL1 -[0xe3,0x9d,0x30,0xd5] -# CHECK: mrs x3, SPMCFGR_EL1 -[0xe3,0x9e,0x36,0xd5] -# CHECK: mrs x3, SPMROOTCR_EL3 -[0xe3,0x9e,0x16,0xd5] -# CHECK: msr SPMROOTCR_EL3, x3 -[0xe3,0x9e,0x37,0xd5] -# CHECK: mrs x3, SPMSCR_EL1 -[0xe3,0x9e,0x17,0xd5] -# CHECK: msr SPMSCR_EL1, x3 - -[0x63,0x12,0x38,0xd5] -# CHECK: mrs x3, TRCITECR_EL1 -# ERROR-NO-ITE: mrs x3, S3_0_C1_C2_3 -[0x61,0x12,0x18,0xd5] -# CHECK: msr TRCITECR_EL1, x1 -# ERROR-NO-ITE: msr S3_0_C1_C2_3, x1 -[0x63,0x12,0x3d,0xd5] -# CHECK: mrs x3, TRCITECR_EL12 -# ERROR-NO-ITE: mrs x3, S3_5_C1_C2_3 -[0x61,0x12,0x1d,0xd5] -# CHECK: msr TRCITECR_EL12, x1 -# ERROR-NO-ITE: msr S3_5_C1_C2_3, x1 -[0x63,0x12,0x3c,0xd5] -# CHECK: mrs x3, TRCITECR_EL2 -# ERROR-NO-ITE: mrs x3, S3_4_C1_C2_3 -[0x61,0x12,0x1c,0xd5] -# CHECK: msr TRCITECR_EL2, x1 -# ERROR-NO-ITE: msr S3_4_C1_C2_3, x1 -[0xe1,0x72,0x0b,0xd5] -# CHECK: trcit x1 -# ERROR-NO-ITE: sys #3, c7, c2, #7, x1 - -[0x83,0x9a,0x38,0xd5] -# CHECK: mrs x3, PMSDSFR_EL1 -[0x83,0x9a,0x18,0xd5] -# CHECK: msr PMSDSFR_EL1, x3 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt deleted file mode 100644 index 644e032cd79c..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt +++ /dev/null @@ -1,113 +0,0 @@ -# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+rcpc3 < %s | FileCheck %s -# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v8.9a -mattr=+rcpc3 < %s | FileCheck %s -# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v9.4a -mattr=+rcpc3 < %s | FileCheck %s - -# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s -# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s -# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s - -[0x18,0x0a,0x00,0x99] -# CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x18,0x0a,0x00,0x99] -# CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x39,0x0a,0x01,0xd9] -# CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x39,0x0a,0x01,0xd9] -# CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x5a,0x1a,0x02,0x99] -# CHECK: stilp w26, w2, [x18] // encoding: [0x5a,0x1a,0x02,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xfb,0x1b,0x03,0xd9] -# CHECK: stilp x27, x3, [sp] // encoding: [0xfb,0x1b,0x03,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x9c,0x0a,0x44,0x99] -# CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x9c,0x0a,0x44,0x99] -# CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xbd,0x0a,0x45,0xd9] -# CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xbd,0x0a,0x45,0xd9] -# CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xfe,0x1b,0x46,0x99] -# CHECK: ldiapp w30, w6, [sp] // encoding: [0xfe,0x1b,0x46,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xff,0x1a,0x47,0xd9] -# CHECK: ldiapp xzr, x7, [x23] // encoding: [0xff,0x1a,0x47,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0xe3,0x09,0x80,0x99] -# CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x09,0x80,0x99] -# CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x09,0x80,0xd9] -# CHECK: stlr x3, [x15, #-8]! // encoding: [0xe3,0x09,0x80,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x0b,0x80,0xd9] -# CHECK: stlr x3, [sp, #-8]! // encoding: [0xe3,0x0b,0x80,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x0b,0xc0,0x99] -# CHECK: ldapr w3, [sp], #4 // encoding: [0xe3,0x0b,0xc0,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x09,0xc0,0x99] -# CHECK: ldapr w3, [x15], #4 // encoding: [0xe3,0x09,0xc0,0x99] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x09,0xc0,0xd9] -# CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x09,0xc0,0xd9] -# CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0xe3,0xf9,0x1f,0x1d] -# CHECK: stlur b3, [x15, #-1] // encoding: [0xe3,0xf9,0x1f,0x1d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x29,0x00,0x5d] -# CHECK: stlur h3, [x15, #2] // encoding: [0xe3,0x29,0x00,0x5d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0xd9,0x1f,0x9d] -# CHECK: stlur s3, [x15, #-3] // encoding: [0xe3,0xd9,0x1f,0x9d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x4b,0x00,0xdd] -# CHECK: stlur d3, [sp, #4] // encoding: [0xe3,0x4b,0x00,0xdd] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0xb9,0x9f,0x1d] -# CHECK: stlur q3, [x15, #-5] // encoding: [0xe3,0xb9,0x9f,0x1d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x69,0x40,0x1d] -# CHECK: ldapur b3, [x15, #6] // encoding: [0xe3,0x69,0x40,0x1d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x99,0x5f,0x5d] -# CHECK: ldapur h3, [x15, #-7] // encoding: [0xe3,0x99,0x5f,0x5d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x89,0x40,0x9d] -# CHECK: ldapur s3, [x15, #8] // encoding: [0xe3,0x89,0x40,0x9d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x79,0x5f,0xdd] -# CHECK: ldapur d3, [x15, #-9] // encoding: [0xe3,0x79,0x5f,0xdd] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0xab,0xc0,0x1d] -# CHECK: ldapur q3, [sp, #10] // encoding: [0xe3,0xab,0xc0,0x1d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0xe3,0x85,0x01,0x0d] -# CHECK: stl1 { v3.d }[0], [x15] // encoding: [0xe3,0x85,0x01,0x0d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x87,0x01,0x4d] -# CHECK: stl1 { v3.d }[1], [sp] // encoding: [0xe3,0x87,0x01,0x4d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x87,0x41,0x0d] -# CHECK: ldap1 { v3.d }[0], [sp] // encoding: [0xe3,0x87,0x41,0x0d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe3,0x85,0x41,0x4d] -# CHECK: ldap1 { v3.d }[1], [x15] // encoding: [0xe3,0x85,0x41,0x4d] -# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-specres2.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-specres2.txt deleted file mode 100644 index a114cd349378..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.9a-specres2.txt +++ /dev/null @@ -1,16 +0,0 @@ -# FEAT_SPECRES2 is optional for all v8a/v9a, mandatory for 8.9a/9.4a. -# Should disassemble to hint #22 if the feature is not present. -# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a -mattr=-specres2 %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a -mattr=-specres2 %s | FileCheck %s --check-prefix=HINT_22 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+specres2 %s | FileCheck %s --check-prefix=FEAT_SPECRES2 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8a -mattr=+specres2 %s | FileCheck %s --check-prefix=FEAT_SPECRES2 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v8.9a %s | FileCheck %s --check-prefix=FEAT_SPECRES2 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.3a -mattr=+specres2 %s | FileCheck %s --check-prefix=FEAT_SPECRES2 -# RUN: llvm-mc -triple=aarch64 -disassemble -mattr=+v9.4a %s | FileCheck %s --check-prefix=FEAT_SPECRES2 - -[0xc0,0x73,0x0b,0xd5] -# FEAT_SPECRES2: cosp rctx, x0 -# HINT_22: sys #3, c7, c3, #6, x0 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt deleted file mode 100644 index f3b313a36487..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv8.9a-the.txt +++ /dev/null @@ -1,482 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+the -mattr=+d128 -disassemble %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -mattr=+the -mattr=+d128 -disassemble %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -mattr=+the -mattr=+d128 -disassemble %s | FileCheck %s -# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-THE -# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.9a -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-THE -# RUN: not llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-THE -# RUN: not llvm-mc -triple=aarch64 -mattr=+the -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 -# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.9a -mattr=+the -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 -# RUN: not llvm-mc -triple=aarch64 -mattr=+v9.4a -mattr=+the -disassemble %s 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 - -[0xc3,0xd0,0x38,0xd5] -# CHECK: mrs x3, RCWMASK_EL1 -[0xc1,0xd0,0x18,0xd5] -# CHECK: msr RCWMASK_EL1, x1 -[0x63,0xd0,0x38,0xd5] -# CHECK: mrs x3, RCWSMASK_EL1 -[0x61,0xd0,0x18,0xd5] -# CHECK: msr RCWSMASK_EL1, x1 - -[0x81,0x08,0x20,0x19] -# CHECK: rcwcas x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x08,0xa0,0x19] -# CHECK: rcwcasa x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x08,0xe0,0x19] -# CHECK: rcwcasal x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x08,0x60,0x19] -# CHECK: rcwcasl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0x23,0x19] -# CHECK: rcwcas x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0xa3,0x19] -# CHECK: rcwcasa x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0xe3,0x19] -# CHECK: rcwcasal x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0x63,0x19] -# CHECK: rcwcasl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x81,0x08,0x20,0x59] -# CHECK: rcwscas x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x08,0xa0,0x59] -# CHECK: rcwscasa x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x08,0xe0,0x59] -# CHECK: rcwscasal x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x08,0x60,0x59] -# CHECK: rcwscasl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0x23,0x59] -# CHECK: rcwscas x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0xa3,0x59] -# CHECK: rcwscasa x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0xe3,0x59] -# CHECK: rcwscasal x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x0b,0x63,0x59] -# CHECK: rcwscasl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x86,0x0c,0x20,0x19] -# CHECK: rcwcasp x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x86,0x0c,0xa0,0x19] -# CHECK: rcwcaspa x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x86,0x0c,0xe0,0x19] -# CHECK: rcwcaspal x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x86,0x0c,0x60,0x19] -# CHECK: rcwcaspl x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0x24,0x19] -# CHECK: rcwcasp x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0xa4,0x19] -# CHECK: rcwcaspa x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0xe4,0x19] -# CHECK: rcwcaspal x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0x64,0x19] -# CHECK: rcwcaspl x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding - -[0x86,0x0c,0x20,0x59] -# CHECK: rcwscasp x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x86,0x0c,0xa0,0x59] -# CHECK: rcwscaspa x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x86,0x0c,0xe0,0x59] -# CHECK: rcwscaspal x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x86,0x0c,0x60,0x59] -# CHECK: rcwscaspl x0, x1, x6, x7, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0x24,0x59] -# CHECK: rcwscasp x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0xa4,0x59] -# CHECK: rcwscaspa x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0xe4,0x59] -# CHECK: rcwscaspal x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe6,0x0f,0x64,0x59] -# CHECK: rcwscaspl x4, x5, x6, x7, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding - -[0x81,0x90,0x20,0x38] -# CHECK: rcwclr x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x90,0xa0,0x38] -# CHECK: rcwclra x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x90,0xe0,0x38] -# CHECK: rcwclral x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x90,0x60,0x38] -# CHECK: rcwclrl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x23,0x38] -# CHECK: rcwclr x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xa3,0x38] -# CHECK: rcwclra x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xe3,0x38] -# CHECK: rcwclral x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x63,0x38] -# CHECK: rcwclrl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x81,0x90,0x20,0x78] -# CHECK: rcwsclr x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x90,0xa0,0x78] -# CHECK: rcwsclra x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x90,0xe0,0x78] -# CHECK: rcwsclral x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0x90,0x60,0x78] -# CHECK: rcwsclrl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x23,0x78] -# CHECK: rcwsclr x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xa3,0x78] -# CHECK: rcwsclra x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xe3,0x78] -# CHECK: rcwsclral x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x63,0x78] -# CHECK: rcwsclrl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x81,0x90,0x20,0x19] -# CHECK: rcwclrp x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0x90,0xa0,0x19] -# CHECK: rcwclrpa x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0x90,0xe0,0x19] -# CHECK: rcwclrpal x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0x90,0x60,0x19] -# CHECK: rcwclrpl x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x23,0x19] -# CHECK: rcwclrp x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xa3,0x19] -# CHECK: rcwclrpa x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xe3,0x19] -# CHECK: rcwclrpal x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x63,0x19] -# CHECK: rcwclrpl x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding - -[0x81,0x90,0x20,0x59] -# CHECK: rcwsclrp x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0x90,0xa0,0x59] -# CHECK: rcwsclrpa x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0x90,0xe0,0x59] -# CHECK: rcwsclrpal x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0x90,0x60,0x59] -# CHECK: rcwsclrpl x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x23,0x59] -# CHECK: rcwsclrp x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xa3,0x59] -# CHECK: rcwsclrpa x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0xe3,0x59] -# CHECK: rcwsclrpal x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0x93,0x63,0x59] -# CHECK: rcwsclrpl x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding - -[0x81,0xb0,0x20,0x38] -# CHECK: rcwset x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xa0,0x38] -# CHECK: rcwseta x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xe0,0x38] -# CHECK: rcwsetal x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xb0,0x60,0x38] -# CHECK: rcwsetl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x23,0x38] -# CHECK: rcwset x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xa3,0x38] -# CHECK: rcwseta x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xe3,0x38] -# CHECK: rcwsetal x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x63,0x38] -# CHECK: rcwsetl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x81,0xb0,0x20,0x78] -# CHECK: rcwsset x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xa0,0x78] -# CHECK: rcwsseta x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xe0,0x78] -# CHECK: rcwssetal x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xb0,0x60,0x78] -# CHECK: rcwssetl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x23,0x78] -# CHECK: rcwsset x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xa3,0x78] -# CHECK: rcwsseta x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xe3,0x78] -# CHECK: rcwssetal x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x63,0x78] -# CHECK: rcwssetl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x81,0xb0,0x20,0x19] -# CHECK: rcwsetp x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xa0,0x19] -# CHECK: rcwsetpa x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xe0,0x19] -# CHECK: rcwsetpal x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xb0,0x60,0x19] -# CHECK: rcwsetpl x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x23,0x19] -# CHECK: rcwsetp x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xa3,0x19] -# CHECK: rcwsetpa x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xe3,0x19] -# CHECK: rcwsetpal x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x63,0x19] -# CHECK: rcwsetpl x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding - -[0x81,0xb0,0x20,0x59] -# CHECK: rcwssetp x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xa0,0x59] -# CHECK: rcwssetpa x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xb0,0xe0,0x59] -# CHECK: rcwssetpal x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xb0,0x60,0x59] -# CHECK: rcwssetpl x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x23,0x59] -# CHECK: rcwssetp x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xa3,0x59] -# CHECK: rcwssetpa x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0xe3,0x59] -# CHECK: rcwssetpal x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xb3,0x63,0x59] -# CHECK: rcwssetpl x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding - -[0x81,0xa0,0x20,0x38] -# CHECK: rcwswp x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xa0,0x38] -# CHECK: rcwswpa x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xe0,0x38] -# CHECK: rcwswpal x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xa0,0x60,0x38] -# CHECK: rcwswpl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x23,0x38] -# CHECK: rcwswp x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xa3,0x38] -# CHECK: rcwswpa x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xe3,0x38] -# CHECK: rcwswpal x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x63,0x38] -# CHECK: rcwswpl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x81,0xa0,0x20,0x78] -# CHECK: rcwsswp x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xa0,0x78] -# CHECK: rcwsswpa x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xe0,0x78] -# CHECK: rcwsswpal x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0x81,0xa0,0x60,0x78] -# CHECK: rcwsswpl x0, x1, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x23,0x78] -# CHECK: rcwsswp x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xa3,0x78] -# CHECK: rcwsswpa x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xe3,0x78] -# CHECK: rcwsswpal x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x63,0x78] -# CHECK: rcwsswpl x3, x5, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding - -[0x81,0xa0,0x20,0x19] -# CHECK: rcwswpp x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xa0,0x19] -# CHECK: rcwswppa x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xe0,0x19] -# CHECK: rcwswppal x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xa0,0x60,0x19] -# CHECK: rcwswppl x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x23,0x19] -# CHECK: rcwswpp x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xa3,0x19] -# CHECK: rcwswppa x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xe3,0x19] -# CHECK: rcwswppal x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x63,0x19] -# CHECK: rcwswppl x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding - -[0x81,0xa0,0x20,0x59] -# CHECK: rcwsswpp x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xa0,0x59] -# CHECK: rcwsswppa x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xa0,0xe0,0x59] -# CHECK: rcwsswppal x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0x81,0xa0,0x60,0x59] -# CHECK: rcwsswppl x1, x0, [x4] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x23,0x59] -# CHECK: rcwsswpp x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xa3,0x59] -# CHECK: rcwsswppa x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0xe3,0x59] -# CHECK: rcwsswppal x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding -[0xe5,0xa3,0x63,0x59] -# CHECK: rcwsswppl x5, x3, [sp] -# ERROR-NO-THE: [[@LINE-2]]:2: warning: invalid instruction encoding -# ERROR-NO-D128: [[@LINE-3]]:2: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt b/llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt deleted file mode 100644 index 2bbdef4d5518..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9-sysp.txt +++ /dev/null @@ -1,562 +0,0 @@ -# RUN: llvm-mc -triple aarch64 --disassemble -mattr=+d128,+tlb-rmi,+xs %s -o - 2> %t | FileCheck %s -# RUN: FileCheck %s --check-prefix=INVALID --input-file=%t - -# RUN: llvm-mc -triple aarch64 --disassemble %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 - -0x00 0x20 0x48 0xd5 -0x20 0x20 0x48 0xd5 -0x00 0x74 0x48 0xd5 -0x60 0xd0 0x48 0xd5 -0xc0 0xd0 0x48 0xd5 -0x00 0x20 0x4c 0xd5 -0x20 0x20 0x4c 0xd5 -0x00 0x21 0x4c 0xd5 -0x00 0x20 0x48 0xd5 -0x20 0x20 0x48 0xd5 -0x00 0x74 0x48 0xd5 -0x60 0xd0 0x48 0xd5 -0xc0 0xd0 0x48 0xd5 -0x00 0x20 0x4c 0xd5 -0x20 0x20 0x4c 0xd5 -0x00 0x21 0x4c 0xd5 -0x00 0x20 0x48 0xd5 -0x02 0x20 0x48 0xd5 -0x04 0x20 0x48 0xd5 -0x06 0x20 0x48 0xd5 -0x08 0x20 0x48 0xd5 -0x0a 0x20 0x48 0xd5 -0x0c 0x20 0x48 0xd5 -0x0e 0x20 0x48 0xd5 -0x10 0x20 0x48 0xd5 -0x12 0x20 0x48 0xd5 -0x14 0x20 0x48 0xd5 -0x16 0x20 0x48 0xd5 -0x18 0x20 0x48 0xd5 -0x1a 0x20 0x48 0xd5 -0x1c 0x20 0x48 0xd5 -0x1e 0x20 0x48 0xd5 -0x1f 0x20 0x48 0xd5 - -# CHECK: sysp #0, c2, c0, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #1, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c7, c4, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c13, c0, #3, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c13, c0, #6, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #4, c2, c0, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #4, c2, c0, #1, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #4, c2, c1, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #1, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c7, c4, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c13, c0, #3, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c13, c0, #6, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #4, c2, c0, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #4, c2, c0, #1, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #4, c2, c1, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x0, x1 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x2, x3 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x6, x7 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x12, x13 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x16, x17 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x22, x23 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x26, x27 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0, x30, xzr -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK-NEXT: sysp #0, c2, c0, #0 -# ERROR-NO-D128: warning: invalid instruction encoding - - - -0x01 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x1, x2 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x01 0x20 0x48 0xd5 - -0x03 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x3, x4 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x03 0x20 0x48 0xd5 - -0x05 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x5, x6 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x05 0x20 0x48 0xd5 - -0x07 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x7, x8 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x07 0x20 0x48 0xd5 - -0x09 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x9, x10 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x09 0x20 0x48 0xd5 - -0x0b 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x11, x12 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x0b 0x20 0x48 0xd5 - -0x0d 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x13, x14 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x0d 0x20 0x48 0xd5 - -0x0f 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x15, x16 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x0f 0x20 0x48 0xd5 - -0x11 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x17, x18 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x11 0x20 0x48 0xd5 - -0x13 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x19, x20 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x13 0x20 0x48 0xd5 - -0x15 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x21, x22 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x15 0x20 0x48 0xd5 - -0x17 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x23, x24 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x17 0x20 0x48 0xd5 - -0x19 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x25, x26 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x19 0x20 0x48 0xd5 - -0x1b 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x27, x28 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x1b 0x20 0x48 0xd5 - -0x1d 0x20 0x48 0xd5 # sysp #0, c2, c0, #0, x29, x30 -# INVALID: warning: invalid instruction encoding -# INVALID-NEXT: 0x1d 0x20 0x48 0xd5 - -0x24 0x80 0x4c 0xd5 -# CHECK: tlbip ipas2e1is, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0x24 0x90 0x4c 0xd5 -# CHECK: tlbip ipas2e1isnxs, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0x24 0x84 0x4c 0xd5 -# CHECK: tlbip ipas2e1, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0x24 0x94 0x4c 0xd5 -# CHECK: tlbip ipas2e1nxs, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0x04 0x84 0x4c 0xd5 -# CHECK: tlbip ipas2e1os, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0x04 0x94 0x4c 0xd5 -# CHECK: tlbip ipas2e1osnxs, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa4 0x84 0x4c 0xd5 -# CHECK: tlbip ipas2le1, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa4 0x94 0x4c 0xd5 -# CHECK: tlbip ipas2le1nxs, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa4 0x80 0x4c 0xd5 -# CHECK: tlbip ipas2le1is, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa4 0x90 0x4c 0xd5 -# CHECK: tlbip ipas2le1isnxs, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0x84 0x84 0x4c 0xd5 -# CHECK: tlbip ipas2le1os, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding -0x84 0x94 0x4c 0xd5 -# CHECK: tlbip ipas2le1osnxs, x4, x5 -# ERROR-NO-D128: warning: invalid instruction encoding - - -0x28 0x83 0x48 0xd5 -# CHECK: tlbip vae1is, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x28 0x93 0x48 0xd5 -# CHECK: tlbip vae1isnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x28 0x87 0x48 0xd5 -# CHECK: tlbip vae1, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x28 0x97 0x48 0xd5 -# CHECK: tlbip vae1nxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x28 0x83 0x48 0xd5 -# CHECK: tlbip vae1is, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x28 0x93 0x48 0xd5 -# CHECK: tlbip vae1isnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x28 0x81 0x48 0xd5 -# CHECK: tlbip vae1os, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x28 0x91 0x48 0xd5 -# CHECK: tlbip vae1osnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa8 0x87 0x48 0xd5 -# CHECK: tlbip vale1, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa8 0x97 0x48 0xd5 -# CHECK: tlbip vale1nxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa8 0x83 0x48 0xd5 -# CHECK: tlbip vale1is, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa8 0x93 0x48 0xd5 -# CHECK: tlbip vale1isnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa8 0x81 0x48 0xd5 -# CHECK: tlbip vale1os, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xa8 0x91 0x48 0xd5 -# CHECK: tlbip vale1osnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x68 0x87 0x48 0xd5 -# CHECK: tlbip vaae1, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x68 0x97 0x48 0xd5 -# CHECK: tlbip vaae1nxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x68 0x83 0x48 0xd5 -# CHECK: tlbip vaae1is, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x68 0x93 0x48 0xd5 -# CHECK: tlbip vaae1isnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x68 0x81 0x48 0xd5 -# CHECK: tlbip vaae1os, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0x68 0x91 0x48 0xd5 -# CHECK: tlbip vaae1osnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xe8 0x87 0x48 0xd5 -# CHECK: tlbip vaale1, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xe8 0x97 0x48 0xd5 -# CHECK: tlbip vaale1nxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xe8 0x83 0x48 0xd5 -# CHECK: tlbip vaale1is, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xe8 0x93 0x48 0xd5 -# CHECK: tlbip vaale1isnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xe8 0x81 0x48 0xd5 -# CHECK: tlbip vaale1os, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding -0xe8 0x91 0x48 0xd5 -# CHECK: tlbip vaale1osnxs, x8, x9 -# ERROR-NO-D128: warning: invalid instruction encoding - -0x2e 0x87 0x4c 0xd5 -# CHECK: tlbip vae2, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2e 0x97 0x4c 0xd5 -# CHECK: tlbip vae2nxs, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2e 0x83 0x4c 0xd5 -# CHECK: tlbip vae2is, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2e 0x93 0x4c 0xd5 -# CHECK: tlbip vae2isnxs, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2e 0x81 0x4c 0xd5 -# CHECK: tlbip vae2os, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2e 0x91 0x4c 0xd5 -# CHECK: tlbip vae2osnxs, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0xae 0x87 0x4c 0xd5 -# CHECK: tlbip vale2, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0xae 0x97 0x4c 0xd5 -# CHECK: tlbip vale2nxs, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0xae 0x83 0x4c 0xd5 -# CHECK: tlbip vale2is, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0xae 0x93 0x4c 0xd5 -# CHECK: tlbip vale2isnxs, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0xae 0x81 0x4c 0xd5 -# CHECK: tlbip vale2os, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding -0xae 0x91 0x4c 0xd5 -# CHECK: tlbip vale2osnxs, x14, x15 -# ERROR-NO-D128: warning: invalid instruction encoding - -0x38 0x87 0x4e 0xd5 -# CHECK: tlbip vae3, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0x38 0x97 0x4e 0xd5 -# CHECK: tlbip vae3nxs, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0x38 0x83 0x4e 0xd5 -# CHECK: tlbip vae3is, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0x38 0x93 0x4e 0xd5 -# CHECK: tlbip vae3isnxs, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0x38 0x81 0x4e 0xd5 -# CHECK: tlbip vae3os, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0x38 0x91 0x4e 0xd5 -# CHECK: tlbip vae3osnxs, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb8 0x87 0x4e 0xd5 -# CHECK: tlbip vale3, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb8 0x97 0x4e 0xd5 -# CHECK: tlbip vale3nxs, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb8 0x83 0x4e 0xd5 -# CHECK: tlbip vale3is, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb8 0x93 0x4e 0xd5 -# CHECK: tlbip vale3isnxs, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb8 0x81 0x4e 0xd5 -# CHECK: tlbip vale3os, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb8 0x91 0x4e 0xd5 -# CHECK: tlbip vale3osnxs, x24, x25 -# ERROR-NO-D128: warning: invalid instruction encoding - - -0x32 0x86 0x48 0xd5 -# CHECK: tlbip rvae1, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x32 0x96 0x48 0xd5 -# CHECK: tlbip rvae1nxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x32 0x86 0x48 0xd5 -# CHECK: tlbip rvae1, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x32 0x96 0x48 0xd5 -# CHECK: tlbip rvae1nxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x32 0x82 0x48 0xd5 -# CHECK: tlbip rvae1is, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x32 0x92 0x48 0xd5 -# CHECK: tlbip rvae1isnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x32 0x85 0x48 0xd5 -# CHECK: tlbip rvae1os, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x32 0x95 0x48 0xd5 -# CHECK: tlbip rvae1osnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x72 0x86 0x48 0xd5 -# CHECK: tlbip rvaae1, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x72 0x96 0x48 0xd5 -# CHECK: tlbip rvaae1nxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x72 0x82 0x48 0xd5 -# CHECK: tlbip rvaae1is, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x72 0x92 0x48 0xd5 -# CHECK: tlbip rvaae1isnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x72 0x85 0x48 0xd5 -# CHECK: tlbip rvaae1os, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0x72 0x95 0x48 0xd5 -# CHECK: tlbip rvaae1osnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb2 0x86 0x48 0xd5 -# CHECK: tlbip rvale1, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb2 0x96 0x48 0xd5 -# CHECK: tlbip rvale1nxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb2 0x82 0x48 0xd5 -# CHECK: tlbip rvale1is, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb2 0x92 0x48 0xd5 -# CHECK: tlbip rvale1isnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb2 0x85 0x48 0xd5 -# CHECK: tlbip rvale1os, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xb2 0x95 0x48 0xd5 -# CHECK: tlbip rvale1osnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf2 0x86 0x48 0xd5 -# CHECK: tlbip rvaale1, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf2 0x96 0x48 0xd5 -# CHECK: tlbip rvaale1nxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf2 0x82 0x48 0xd5 -# CHECK: tlbip rvaale1is, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf2 0x92 0x48 0xd5 -# CHECK: tlbip rvaale1isnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf2 0x85 0x48 0xd5 -# CHECK: tlbip rvaale1os, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf2 0x95 0x48 0xd5 -# CHECK: tlbip rvaale1osnxs, x18, x19 -# ERROR-NO-D128: warning: invalid instruction encoding - -0x3c 0x86 0x4c 0xd5 -# CHECK: tlbip rvae2, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0x3c 0x96 0x4c 0xd5 -# CHECK: tlbip rvae2nxs, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0x3c 0x82 0x4c 0xd5 -# CHECK: tlbip rvae2is, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0x3c 0x92 0x4c 0xd5 -# CHECK: tlbip rvae2isnxs, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0x3c 0x85 0x4c 0xd5 -# CHECK: tlbip rvae2os, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0x3c 0x95 0x4c 0xd5 -# CHECK: tlbip rvae2osnxs, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0xbc 0x86 0x4c 0xd5 -# CHECK: tlbip rvale2, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0xbc 0x96 0x4c 0xd5 -# CHECK: tlbip rvale2nxs, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0xbc 0x82 0x4c 0xd5 -# CHECK: tlbip rvale2is, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0xbc 0x92 0x4c 0xd5 -# CHECK: tlbip rvale2isnxs, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0xbc 0x85 0x4c 0xd5 -# CHECK: tlbip rvale2os, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding -0xbc 0x95 0x4c 0xd5 -# CHECK: tlbip rvale2osnxs, x28, x29 -# ERROR-NO-D128: warning: invalid instruction encoding - -0x2a 0x86 0x4e 0xd5 -# CHECK: tlbip rvae3, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2a 0x96 0x4e 0xd5 -# CHECK: tlbip rvae3nxs, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2a 0x82 0x4e 0xd5 -# CHECK: tlbip rvae3is, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2a 0x92 0x4e 0xd5 -# CHECK: tlbip rvae3isnxs, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2a 0x85 0x4e 0xd5 -# CHECK: tlbip rvae3os, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0x2a 0x95 0x4e 0xd5 -# CHECK: tlbip rvae3osnxs, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0xaa 0x86 0x4e 0xd5 -# CHECK: tlbip rvale3, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0xaa 0x96 0x4e 0xd5 -# CHECK: tlbip rvale3nxs, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0xaa 0x82 0x4e 0xd5 -# CHECK: tlbip rvale3is, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0xaa 0x92 0x4e 0xd5 -# CHECK: tlbip rvale3isnxs, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0xaa 0x85 0x4e 0xd5 -# CHECK: tlbip rvale3os, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding -0xaa 0x95 0x4e 0xd5 -# CHECK: tlbip rvale3osnxs, x10, x11 -# ERROR-NO-D128: warning: invalid instruction encoding - - -0x54 0x80 0x4c 0xd5 -# CHECK: tlbip ripas2e1is, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0x54 0x90 0x4c 0xd5 -# CHECK: tlbip ripas2e1isnxs, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0x54 0x84 0x4c 0xd5 -# CHECK: tlbip ripas2e1, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0x54 0x94 0x4c 0xd5 -# CHECK: tlbip ripas2e1nxs, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0x54 0x80 0x4c 0xd5 -# CHECK: tlbip ripas2e1is, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0x54 0x90 0x4c 0xd5 -# CHECK: tlbip ripas2e1isnxs, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0x74 0x84 0x4c 0xd5 -# CHECK: tlbip ripas2e1os, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0x74 0x94 0x4c 0xd5 -# CHECK: tlbip ripas2e1osnxs, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0xd4 0x84 0x4c 0xd5 -# CHECK: tlbip ripas2le1, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0xd4 0x94 0x4c 0xd5 -# CHECK: tlbip ripas2le1nxs, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0xd4 0x80 0x4c 0xd5 -# CHECK: tlbip ripas2le1is, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0xd4 0x90 0x4c 0xd5 -# CHECK: tlbip ripas2le1isnxs, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf4 0x84 0x4c 0xd5 -# CHECK: tlbip ripas2le1os, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -0xf4 0x94 0x4c 0xd5 -# CHECK: tlbip ripas2le1osnxs, x20, x21 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK: tlbip ripas2le1os, xzr, xzr -0xff 0x84 0x4c 0xd5 -# ERROR-NO-D128: warning: invalid instruction encoding -# CHECK: tlbip ripas2le1osnxs, xzr, xzr -0xff 0x94 0x4c 0xd5 -# ERROR-NO-D128: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt b/llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt deleted file mode 100644 index 4ab37a020073..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt +++ /dev/null @@ -1,147 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -mattr=+d128 --disassemble -show-encoding %s -o - | FileCheck %s --check-prefix=WITHOUT -# RUN: llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh --disassemble -show-encoding %s -o - | FileCheck %s --check-prefix=W_FEATS - -# RUN: llvm-mc -triple aarch64 --disassemble -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 - -0x00,0x20,0x78,0xd5 -0x20,0x20,0x78,0xd5 -0x00,0x74,0x78,0xd5 -0x60,0xd0,0x78,0xd5 -0xc0,0xd0,0x78,0xd5 -0x00,0x20,0x7c,0xd5 -0x20,0x20,0x7c,0xd5 -0x00,0x21,0x7c,0xd5 -0x00,0x21,0x7c,0xd5 -0x02,0x21,0x7c,0xd5 -0x04,0x21,0x7c,0xd5 -0x06,0x21,0x7c,0xd5 -0x08,0x21,0x7c,0xd5 -0x0a,0x21,0x7c,0xd5 -0x0c,0x21,0x7c,0xd5 -0x0e,0x21,0x7c,0xd5 -0x10,0x21,0x7c,0xd5 -0x12,0x21,0x7c,0xd5 -0x14,0x21,0x7c,0xd5 -0x16,0x21,0x7c,0xd5 -0x18,0x21,0x7c,0xd5 -0x1a,0x21,0x7c,0xd5 - -# WITHOUT: mrrs x0, x1, TTBR0_EL1 // encoding: [0x00,0x20,0x78,0xd5] -# WITHOUT: mrrs x0, x1, TTBR1_EL1 // encoding: [0x20,0x20,0x78,0xd5] -# WITHOUT: mrrs x0, x1, PAR_EL1 // encoding: [0x00,0x74,0x78,0xd5] -# WITHOUT: mrrs x0, x1, S3_0_C13_C0_3 // encoding: [0x60,0xd0,0x78,0xd5] -# WITHOUT: mrrs x0, x1, S3_0_C13_C0_6 // encoding: [0xc0,0xd0,0x78,0xd5] -# WITHOUT: mrrs x0, x1, S3_4_C2_C0_0 // encoding: [0x00,0x20,0x7c,0xd5] -# WITHOUT: mrrs x0, x1, S3_4_C2_C0_1 // encoding: [0x20,0x20,0x7c,0xd5] -# WITHOUT: mrrs x0, x1, S3_4_C2_C1_0 // encoding: [0x00,0x21,0x7c,0xd5] -# WITHOUT: mrrs x0, x1, S3_4_C2_C1_0 // encoding: [0x00,0x21,0x7c,0xd5] -# WITHOUT: mrrs x2, x3, S3_4_C2_C1_0 // encoding: [0x02,0x21,0x7c,0xd5] -# WITHOUT: mrrs x4, x5, S3_4_C2_C1_0 // encoding: [0x04,0x21,0x7c,0xd5] -# WITHOUT: mrrs x6, x7, S3_4_C2_C1_0 // encoding: [0x06,0x21,0x7c,0xd5] -# WITHOUT: mrrs x8, x9, S3_4_C2_C1_0 // encoding: [0x08,0x21,0x7c,0xd5] -# WITHOUT: mrrs x10, x11, S3_4_C2_C1_0 // encoding: [0x0a,0x21,0x7c,0xd5] -# WITHOUT: mrrs x12, x13, S3_4_C2_C1_0 // encoding: [0x0c,0x21,0x7c,0xd5] -# WITHOUT: mrrs x14, x15, S3_4_C2_C1_0 // encoding: [0x0e,0x21,0x7c,0xd5] -# WITHOUT: mrrs x16, x17, S3_4_C2_C1_0 // encoding: [0x10,0x21,0x7c,0xd5] -# WITHOUT: mrrs x18, x19, S3_4_C2_C1_0 // encoding: [0x12,0x21,0x7c,0xd5] -# WITHOUT: mrrs x20, x21, S3_4_C2_C1_0 // encoding: [0x14,0x21,0x7c,0xd5] -# WITHOUT: mrrs x22, x23, S3_4_C2_C1_0 // encoding: [0x16,0x21,0x7c,0xd5] -# WITHOUT: mrrs x24, x25, S3_4_C2_C1_0 // encoding: [0x18,0x21,0x7c,0xd5] -# WITHOUT: mrrs x26, x27, S3_4_C2_C1_0 // encoding: [0x1a,0x21,0x7c,0xd5] - -# W_FEATS: mrrs x0, x1, TTBR0_EL1 // encoding: [0x00,0x20,0x78,0xd5] -# W_FEATS: mrrs x0, x1, TTBR1_EL1 // encoding: [0x20,0x20,0x78,0xd5] -# W_FEATS: mrrs x0, x1, PAR_EL1 // encoding: [0x00,0x74,0x78,0xd5] -# W_FEATS: mrrs x0, x1, RCWSMASK_EL1 // encoding: [0x60,0xd0,0x78,0xd5] -# W_FEATS: mrrs x0, x1, RCWMASK_EL1 // encoding: [0xc0,0xd0,0x78,0xd5] -# W_FEATS: mrrs x0, x1, TTBR0_EL2 // encoding: [0x00,0x20,0x7c,0xd5] -# W_FEATS: mrrs x0, x1, TTBR1_EL2 // encoding: [0x20,0x20,0x7c,0xd5] -# W_FEATS: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5] -# W_FEATS: mrrs x0, x1, VTTBR_EL2 // encoding: [0x00,0x21,0x7c,0xd5] -# W_FEATS: mrrs x2, x3, VTTBR_EL2 // encoding: [0x02,0x21,0x7c,0xd5] -# W_FEATS: mrrs x4, x5, VTTBR_EL2 // encoding: [0x04,0x21,0x7c,0xd5] -# W_FEATS: mrrs x6, x7, VTTBR_EL2 // encoding: [0x06,0x21,0x7c,0xd5] -# W_FEATS: mrrs x8, x9, VTTBR_EL2 // encoding: [0x08,0x21,0x7c,0xd5] -# W_FEATS: mrrs x10, x11, VTTBR_EL2 // encoding: [0x0a,0x21,0x7c,0xd5] -# W_FEATS: mrrs x12, x13, VTTBR_EL2 // encoding: [0x0c,0x21,0x7c,0xd5] -# W_FEATS: mrrs x14, x15, VTTBR_EL2 // encoding: [0x0e,0x21,0x7c,0xd5] -# W_FEATS: mrrs x16, x17, VTTBR_EL2 // encoding: [0x10,0x21,0x7c,0xd5] -# W_FEATS: mrrs x18, x19, VTTBR_EL2 // encoding: [0x12,0x21,0x7c,0xd5] -# W_FEATS: mrrs x20, x21, VTTBR_EL2 // encoding: [0x14,0x21,0x7c,0xd5] -# W_FEATS: mrrs x22, x23, VTTBR_EL2 // encoding: [0x16,0x21,0x7c,0xd5] -# W_FEATS: mrrs x24, x25, VTTBR_EL2 // encoding: [0x18,0x21,0x7c,0xd5] -# W_FEATS: mrrs x26, x27, VTTBR_EL2 // encoding: [0x1a,0x21,0x7c,0xd5] - -# ERROR-NO-D128: warning: invalid instruction encoding - - -0x00,0x20,0x58,0xd5 -0x20,0x20,0x58,0xd5 -0x00,0x74,0x58,0xd5 -0x60,0xd0,0x58,0xd5 -0xc0,0xd0,0x58,0xd5 -0x00,0x20,0x5c,0xd5 -0x20,0x20,0x5c,0xd5 -0x00,0x21,0x5c,0xd5 -0x00,0x21,0x5c,0xd5 -0x02,0x21,0x5c,0xd5 -0x04,0x21,0x5c,0xd5 -0x06,0x21,0x5c,0xd5 -0x08,0x21,0x5c,0xd5 -0x0a,0x21,0x5c,0xd5 -0x0c,0x21,0x5c,0xd5 -0x0e,0x21,0x5c,0xd5 -0x10,0x21,0x5c,0xd5 -0x12,0x21,0x5c,0xd5 -0x14,0x21,0x5c,0xd5 -0x16,0x21,0x5c,0xd5 -0x18,0x21,0x5c,0xd5 -0x1a,0x21,0x5c,0xd5 - -# WITHOUT: msrr TTBR0_EL1, x0, x1 // encoding: [0x00,0x20,0x58,0xd5] -# WITHOUT: msrr TTBR1_EL1, x0, x1 // encoding: [0x20,0x20,0x58,0xd5] -# WITHOUT: msrr PAR_EL1, x0, x1 // encoding: [0x00,0x74,0x58,0xd5] -# WITHOUT: msrr S3_0_C13_C0_3, x0, x1 // encoding: [0x60,0xd0,0x58,0xd5] -# WITHOUT: msrr S3_0_C13_C0_6, x0, x1 // encoding: [0xc0,0xd0,0x58,0xd5] -# WITHOUT: msrr S3_4_C2_C0_0, x0, x1 // encoding: [0x00,0x20,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C0_1, x0, x1 // encoding: [0x20,0x20,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x2, x3 // encoding: [0x02,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x4, x5 // encoding: [0x04,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x6, x7 // encoding: [0x06,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x8, x9 // encoding: [0x08,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x10, x11 // encoding: [0x0a,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x12, x13 // encoding: [0x0c,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x14, x15 // encoding: [0x0e,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x16, x17 // encoding: [0x10,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x18, x19 // encoding: [0x12,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x20, x21 // encoding: [0x14,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x22, x23 // encoding: [0x16,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x24, x25 // encoding: [0x18,0x21,0x5c,0xd5] -# WITHOUT: msrr S3_4_C2_C1_0, x26, x27 // encoding: [0x1a,0x21,0x5c,0xd5] - -# W_FEATS: msrr TTBR0_EL1, x0, x1 // encoding: [0x00,0x20,0x58,0xd5] -# W_FEATS: msrr TTBR1_EL1, x0, x1 // encoding: [0x20,0x20,0x58,0xd5] -# W_FEATS: msrr PAR_EL1, x0, x1 // encoding: [0x00,0x74,0x58,0xd5] -# W_FEATS: msrr RCWSMASK_EL1, x0, x1 // encoding: [0x60,0xd0,0x58,0xd5] -# W_FEATS: msrr RCWMASK_EL1, x0, x1 // encoding: [0xc0,0xd0,0x58,0xd5] -# W_FEATS: msrr TTBR0_EL2, x0, x1 // encoding: [0x00,0x20,0x5c,0xd5] -# W_FEATS: msrr TTBR1_EL2, x0, x1 // encoding: [0x20,0x20,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x2, x3 // encoding: [0x02,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x4, x5 // encoding: [0x04,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x6, x7 // encoding: [0x06,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x8, x9 // encoding: [0x08,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x10, x11 // encoding: [0x0a,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x12, x13 // encoding: [0x0c,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x14, x15 // encoding: [0x0e,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x16, x17 // encoding: [0x10,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x18, x19 // encoding: [0x12,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x20, x21 // encoding: [0x14,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x22, x23 // encoding: [0x16,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x24, x25 // encoding: [0x18,0x21,0x5c,0xd5] -# W_FEATS: msrr VTTBR_EL2, x26, x27 // encoding: [0x1a,0x21,0x5c,0xd5] - -# ERROR-NO-D128: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.4a-chk.txt b/llvm/test/MC/Disassembler/AArch64/armv9.4a-chk.txt deleted file mode 100644 index 730f4440402e..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.4a-chk.txt +++ /dev/null @@ -1,8 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -disassemble %s 2> %t | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble %s 2> %t | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+chk -disassemble %s 2> %t | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -mattr=+v8a -disassemble %s 2> %t | FileCheck %s --check-prefix=NO-CHK - -[0x1f,0x25,0x03,0xd5] -// CHECK: chkfeat x16 -// NO-CHK: hint #40 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.4a-ebep.txt b/llvm/test/MC/Disassembler/AArch64/armv9.4a-ebep.txt deleted file mode 100644 index aa9c95fb2082..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.4a-ebep.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s - -[0x23,0x43,0x38,0xd5] -# CHECK: mrs x3, PM - -[0x26,0x43,0x18,0xd5] -# CHECK: msr PM, x6 - -[0x1f,0x42,0x01,0xd5] -# CHECK: msr PM, #0 - -[0x1f,0x43,0x01,0xd5] -# CHECK: msr PM, #1 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt b/llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt deleted file mode 100644 index 512f4027d976..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.4a-gcs.txt +++ /dev/null @@ -1,90 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -mattr +gcs -disassemble %s 2> %t | FileCheck %s - -[0x00,0x25,0x18,0xd5] -[0x01,0x25,0x38,0xd5] -// CHECK: msr GCSCR_EL1, x0 -// CHECK: mrs x1, GCSCR_EL1 - -[0x22,0x25,0x18,0xd5] -[0x23,0x25,0x38,0xd5] -// CHECK: msr GCSPR_EL1, x2 -// CHECK: mrs x3, GCSPR_EL1 - -[0x44,0x25,0x18,0xd5] -[0x45,0x25,0x38,0xd5] -// CHECK: msr GCSCRE0_EL1, x4 -// CHECK: mrs x5, GCSCRE0_EL1 - -[0x26,0x25,0x1b,0xd5] -[0x27,0x25,0x3b,0xd5] -// CHECK: msr GCSPR_EL0, x6 -// CHECK: mrs x7, GCSPR_EL0 - -[0x0a,0x25,0x1c,0xd5] -[0x0b,0x25,0x3c,0xd5] -// CHECK: msr GCSCR_EL2, x10 -// CHECK: mrs x11, GCSCR_EL2 - -[0x2c,0x25,0x1c,0xd5] -[0x2d,0x25,0x3c,0xd5] -// CHECK: msr GCSPR_EL2, x12 -// CHECK: mrs x13, GCSPR_EL2 - -[0x0e,0x25,0x1d,0xd5] -[0x0f,0x25,0x3d,0xd5] -// CHECK: msr GCSCR_EL12, x14 -// CHECK: mrs x15, GCSCR_EL12 - -[0x30,0x25,0x1d,0xd5] -[0x31,0x25,0x3d,0xd5] -// CHECK: msr GCSPR_EL12, x16 -// CHECK: mrs x17, GCSPR_EL12 - -[0x12,0x25,0x1e,0xd5] -[0x13,0x25,0x3e,0xd5] -// CHECK: msr GCSCR_EL3, x18 -// CHECK: mrs x19, GCSCR_EL3 - -[0x34,0x25,0x1e,0xd5] -[0x35,0x25,0x3e,0xd5] -// CHECK: msr GCSPR_EL3, x20 -// CHECK: mrs x21, GCSPR_EL3 - -[0x55,0x77,0x0b,0xd5] -// CHECK: gcsss1 x21 - -[0x76,0x77,0x2b,0xd5] -// CHECK: gcsss2 x22 - -[0x19,0x77,0x0b,0xd5] -// CHECK: gcspushm x25 - -[0x3f,0x77,0x2b,0xd5] -// CHECK: gcspopm - -[0x39,0x77,0x2b,0xd5] -// CHECK: gcspopm x25 - -[0x7f,0x22,0x03,0xd5] -// CHECK: gcsb dsync - -[0x7a,0x0f,0x1f,0xd9] -// CHECK: gcsstr x26, [x27] - -[0xfa,0x0f,0x1f,0xd9] -// CHECK: gcsstr x26, [sp] - -[0x7a,0x1f,0x1f,0xd9] -// CHECK: gcssttr x26, [x27] - -[0xfa,0x1f,0x1f,0xd9] -// CHECK: gcssttr x26, [sp] - -[0x9f,0x77,0x08,0xd5] -// CHECK: gcspushx - -[0xbf,0x77,0x08,0xd5] -// CHECK: gcspopcx - -[0xdf,0x77,0x08,0xd5] -// CHECK: gcspopx diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt b/llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt deleted file mode 100644 index d4dffa0b3a9b..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.4a-lse128.txt +++ /dev/null @@ -1,98 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+lse128 -disassemble %s | FileCheck %s -# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2>&1 | FileCheck --check-prefix=NO-LSE128 %s - -[0x61,0x11,0x22,0x19] -# CHECK: ldclrp x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x13,0x36,0x19] -# CHECK: ldclrp x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x11,0xa2,0x19] -# CHECK: ldclrpa x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x13,0xb6,0x19] -# CHECK: ldclrpa x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x11,0xe2,0x19] -# CHECK: ldclrpal x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x13,0xf6,0x19] -# CHECK: ldclrpal x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x11,0x62,0x19] -# CHECK: ldclrpl x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x13,0x76,0x19] -# CHECK: ldclrpl x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x31,0x22,0x19] -# CHECK: ldsetp x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x33,0x36,0x19] -# CHECK: ldsetp x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x31,0xa2,0x19] -# CHECK: ldsetpa x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x33,0xb6,0x19] -# CHECK: ldsetpa x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x31,0xe2,0x19] -# CHECK: ldsetpal x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x33,0xf6,0x19] -# CHECK: ldsetpal x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x31,0x62,0x19] -# CHECK: ldsetpl x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x33,0x76,0x19] -# CHECK: ldsetpl x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x81,0x22,0x19] -# CHECK: swpp x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x83,0x36,0x19] -# CHECK: swpp x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x81,0xa2,0x19] -# CHECK: swppa x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x83,0xb6,0x19] -# CHECK: swppa x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x81,0xe2,0x19] -# CHECK: swppal x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x83,0xf6,0x19] -# CHECK: swppal x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding - -[0x61,0x81,0x62,0x19] -# CHECK: swppl x1, x2, [x11] -# NO-LSE128: warning: invalid instruction encoding - -[0xf5,0x83,0x76,0x19] -# CHECK: swppl x21, x22, [sp] -# NO-LSE128: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt deleted file mode 100644 index bf61782f912a..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt +++ /dev/null @@ -1,42 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+cpa < %s | FileCheck %s -# RUN: not llvm-mc -triple aarch64 -disassemble < %s 2>&1 | FileCheck --check-prefix=NO-CPA %s - -[0x20,0x20,0x02,0x9a] -# CHECK: addpt x0, x1, x2 -# NO-CPA: warning: invalid instruction encoding - -[0xff,0x23,0x02,0x9a] -# CHECK: addpt sp, sp, x2 -# NO-CPA: warning: invalid instruction encoding - -[0x20,0x3c,0x02,0x9a] -# CHECK: addpt x0, x1, x2, lsl #7 -# NO-CPA: warning: invalid instruction encoding - -[0xff,0x3f,0x02,0x9a] -# CHECK: addpt sp, sp, x2, lsl #7 -# NO-CPA: warning: invalid instruction encoding - -[0x20,0x20,0x02,0xda] -# CHECK: subpt x0, x1, x2 -# NO-CPA: warning: invalid instruction encoding - -[0xff,0x23,0x02,0xda] -# CHECK: subpt sp, sp, x2 -# NO-CPA: warning: invalid instruction encoding - -[0x20,0x3c,0x02,0xda] -# CHECK: subpt x0, x1, x2, lsl #7 -# NO-CPA: warning: invalid instruction encoding - -[0xff,0x3f,0x02,0xda] -# CHECK: subpt sp, sp, x2, lsl #7 -# NO-CPA: warning: invalid instruction encoding - -[0x20,0x0c,0x62,0x9b] -# CHECK: maddpt x0, x1, x2, x3 -# NO-CPA: warning: invalid instruction encoding - -[0x20,0x8c,0x62,0x9b] -# CHECK: msubpt x0, x1, x2, x3 -# NO-CPA: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt deleted file mode 100644 index d2476dbf876d..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-e3dse.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0x20,0xc1,0x3e,0xd5] -# CHECK: mrs x0, VDISR_EL3 - -[0x20,0xc1,0x1e,0xd5] -# CHECK: msr VDISR_EL3, x0 - -[0x60,0x52,0x3e,0xd5] -# CHECK: mrs x0, VSESR_EL3 - -[0x60,0x52,0x1e,0xd5] -# CHECK: msr VSESR_EL3, x0 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-fgwte3.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-fgwte3.txt deleted file mode 100644 index f7e355a700af..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-fgwte3.txt +++ /dev/null @@ -1,7 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0xa0,0x11,0x3e,0xd5] -# CHECK: mrs x0, FGWTE3_EL3 - -[0xa0,0x11,0x1e,0xd5] -# CHECK: msr FGWTE3_EL3, x0 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-hacdbs.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-hacdbs.txt deleted file mode 100644 index d9be7e5ba443..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-hacdbs.txt +++ /dev/null @@ -1,14 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0x80,0x23,0x3c,0xd5] -# CHECK: mrs x0, HACDBSBR_EL2 - -[0x80,0x23,0x1c,0xd5] -# CHECK: msr HACDBSBR_EL2, x0 - -[0xa0,0x23,0x3c,0xd5] -# CHECK: mrs x0, HACDBSCONS_EL2 - -[0xa0,0x23,0x1c,0xd5] -# CHECK: msr HACDBSCONS_EL2, x0 - diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-hdbss.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-hdbss.txt deleted file mode 100644 index 999f322548f4..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-hdbss.txt +++ /dev/null @@ -1,14 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0x40,0x23,0x3c,0xd5] -# CHECK: mrs x0, HDBSSBR_EL2 - -[0x40,0x23,0x1c,0xd5] -# CHECK: msr HDBSSBR_EL2, x0 - -[0x60,0x23,0x3c,0xd5] -# CHECK: mrs x0, HDBSSPROD_EL2 - -[0x60,0x23,0x1c,0xd5] -# CHECK: msr HDBSSPROD_EL2, x0 - diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-spmu2.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-spmu2.txt deleted file mode 100644 index 9d4fa1b1a078..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-spmu2.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0x80,0x9c,0x13,0xd5] -# CHECK: msr SPMZR_EL0, x0 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-step2.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-step2.txt deleted file mode 100644 index 473c16d09601..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-step2.txt +++ /dev/null @@ -1,7 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0x40,0x05,0x30,0xd5] -# CHECK: mrs x0, MDSTEPOP_EL1 - -[0x40,0x05,0x10,0xd5] -# CHECK: msr MDSTEPOP_EL1, x0 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.5a-tlbiw.txt b/llvm/test/MC/Disassembler/AArch64/armv9.5a-tlbiw.txt deleted file mode 100644 index df5e894a929e..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.5a-tlbiw.txt +++ /dev/null @@ -1,27 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+tlbiw -mattr=+xs < %s | FileCheck --check-prefix=CHECK-TLBIW --check-prefix=CHECK-XS %s -# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+tlbiw < %s | FileCheck --check-prefix=CHECK-TLBIW --check-prefix=CHECK-NO-XS-TLBIW %s -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck --check-prefix=CHECK-NO-TLBIW --check-prefix=CHECK-NO-XS-TLBIW %s - -[0x5f,0x86,0x0c,0xd5] -# CHECK-TLBIW: tlbi vmallws2e1 -# CHECK-NO-TLBIW: sys #4, c8, c6, #2 - -[0x5f,0x82,0x0c,0xd5] -# CHECK-TLBIW: tlbi vmallws2e1is -# CHECK-NO-TLBIW: sys #4, c8, c2, #2 - -[0x5f,0x85,0x0c,0xd5] -# CHECK-TLBIW: tlbi vmallws2e1os -# CHECK-NO-TLBIW: sys #4, c8, c5, #2 - -[0x5f,0x96,0x0c,0xd5] -# CHECK-XS: tlbi vmallws2e1nxs -# CHECK-NO-XS-TLBIW: sys #4, c9, c6, #2 - -[0x5f,0x92,0x0c,0xd5] -# CHECK-XS: tlbi vmallws2e1isnxs -# CHECK-NO-XS-TLBIW: sys #4, c9, c2, #2 - -[0x5f,0x95,0x0c,0xd5] -# CHECK-XS: tlbi vmallws2e1osnxs -# CHECK-NO-XS-TLBIW: sys #4, c9, c5, #2 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt deleted file mode 100644 index dc53a0bfc30e..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt +++ /dev/null @@ -1,323 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mc -triple aarch64 -mattr=+lsui -disassemble %s | FileCheck %s - -# LDTXR and STTXR -[0xe9,0x7f,0x5f,0xc9] -[0xe9,0x7f,0x5f,0xc9] -[0x6a,0x7d,0x5f,0xc9] -[0x6a,0x7d,0x5f,0xc9] - -[0xe4,0x7f,0x1f,0x89] -[0xe4,0x7f,0x1f,0x89] -[0xe6,0x7c,0x05,0xc9] -[0xe6,0x7c,0x05,0xc9] - -# LDATXR and STLTXR -[0xe9,0xff,0x5f,0xc9] -[0x6a,0xfd,0x5f,0xc9] - -[0xe4,0xff,0x02,0x89] -[0xe6,0xfc,0x05,0xc9] - -# STTP and LDTP -[0x55,0xf4,0x5f,0xe9] -[0x76,0x5c,0x60,0xe9] -[0x98,0xe4,0x40,0xe9] - -[0xe3,0x17,0x81,0xe8] -[0xe3,0x97,0x80,0xe9] -[0xe3,0x17,0x00,0xed] -[0xf1,0xcf,0x1f,0xed] - -[0x55,0xf4,0xdf,0xe8] -[0x76,0x5c,0xe0,0xe8] -[0x98,0xe4,0xc0,0xe8] - -[0xe3,0x17,0x80,0xec] -[0xf1,0xcf,0x9f,0xec] -[0x37,0x74,0xe0,0xec] - -[0x55,0xf4,0xdf,0xe9] -[0x76,0x5c,0xe0,0xe9] -[0x98,0xe4,0xc0,0xe9] - -[0xe3,0x17,0x80,0xed] -[0xf1,0xcf,0x9f,0xed] -[0x37,0x74,0xe0,0xed] - -[0x55,0xf4,0x5f,0xe8] -[0x76,0x5c,0x60,0xe8] -[0x98,0xe4,0x40,0xe8] -[0x37,0x74,0x60,0xec] - -[0xe3,0x17,0x00,0xe8] -[0xf1,0x4f,0x04,0xe8] -[0xe3,0x17,0x00,0xec] -[0xf1,0xcf,0x1f,0xec] - -# SWPT{A|L} -[0xbf,0x84,0x27,0x19] -[0xff,0x87,0x29,0x59] - -[0xbf,0x84,0xa7,0x19] -[0xff,0x87,0xa9,0x59] - -[0xbf,0x84,0x67,0x19] -[0xff,0x87,0x69,0x59] - -[0xbf,0x84,0xe7,0x19] -[0xff,0x87,0xe9,0x59] - -# CAS{A|L}T -[0x41,0x7c,0x80,0xc9] -[0xe1,0x7f,0x80,0xc9] -[0x41,0x7c,0xc0,0xc9] -[0xe1,0x7f,0xc0,0xc9] -[0x41,0xfc,0xc0,0xc9] -[0xe1,0xff,0xc0,0xc9] -[0x41,0xfc,0x80,0xc9] -[0xe1,0xff,0x80,0xc9] - -# CASP{A|L}T -[0x82,0x7c,0x80,0x49] -[0xe2,0x7f,0x80,0x49] -[0x82,0x7c,0xc0,0x49] -[0xe2,0x7f,0xc0,0x49] -[0x82,0xfc,0x80,0x49] -[0xe2,0xff,0x80,0x49] -[0x82,0xfc,0xc0,0x49] -[0xe2,0xff,0xc0,0x49] - -#LDT{SET|ADD|CLR}{A|L} and STT{ADD|SET|CLR}{L} - -[0xbf,0x04,0x27,0x19] -[0xff,0x07,0x29,0x59] - -[0xbf,0x04,0xa7,0x19] -[0xff,0x07,0xa9,0x59] - -[0xbf,0x04,0x67,0x19] -[0xff,0x07,0x69,0x59] - -[0xbf,0x04,0xe7,0x19] -[0xff,0x07,0xe9,0x59] - -[0xbf,0x14,0x27,0x19] -[0xff,0x17,0x29,0x59] - -[0xbf,0x14,0x67,0x19] -[0xff,0x17,0x69,0x59] - -[0xbf,0x14,0xa7,0x19] -[0xff,0x17,0xa9,0x59] - -[0xbf,0x14,0xe7,0x19] -[0xff,0x17,0xe9,0x59] - -[0xbf,0x34,0x27,0x19] -[0xff,0x37,0x29,0x59] - -[0xbf,0x34,0x67,0x19] -[0xff,0x37,0x69,0x59] - -[0xbf,0x34,0xa7,0x19] -[0xff,0x37,0xa9,0x59] - -[0xbf,0x34,0xe7,0x19] -[0xff,0x37,0xe9,0x59] - -[0x5f,0x04,0x20,0x19] -[0xff,0x07,0x22,0x19] -[0x5f,0x04,0x20,0x59] -[0xff,0x07,0x22,0x59] - -[0x5f,0x04,0x20,0x19] -[0xff,0x07,0x22,0x19] -[0x5f,0x04,0x20,0x59] -[0xff,0x07,0x22,0x59] - -[0x5f,0x04,0x20,0x19] -[0xff,0x07,0x22,0x19] -[0x5f,0x04,0x20,0x59] -[0xff,0x07,0x22,0x59] - -[0x5f,0x04,0x20,0x19] -[0xff,0x07,0x22,0x19] -[0x5f,0x04,0x20,0x59] -[0xff,0x07,0x22,0x59] - -[0x5f,0x14,0x20,0x19] -[0xff,0x17,0x22,0x19] -[0x5f,0x14,0x20,0x59] -[0xff,0x17,0x22,0x59] - -[0x5f,0x14,0x20,0x19] -[0xff,0x17,0x22,0x19] -[0x5f,0x14,0x20,0x59] -[0xff,0x17,0x22,0x59] - -[0x5f,0x14,0x20,0x19] -[0xff,0x17,0x22,0x19] -[0x5f,0x14,0x20,0x59] -[0xff,0x17,0x22,0x59] - -[0x5f,0x14,0x20,0x19] -[0xff,0x17,0x22,0x59] -[0x5f,0x14,0x20,0x59] -[0xff,0x17,0x22,0x59] - -[0x5f,0x34,0x20,0x19] -[0xff,0x37,0x22,0x19] -[0x5f,0x34,0x20,0x59] -[0xff,0x37,0x22,0x59] - -[0x5f,0x34,0x20,0x19] -[0xff,0x37,0x22,0x19] -[0x5f,0x34,0x20,0x59] -[0xff,0x37,0x22,0x59] - -[0x5f,0x34,0x20,0x19] -[0xff,0x37,0x22,0x19] -[0x5f,0x34,0x20,0x59] -[0xff,0x37,0x22,0x59] - -[0x5f,0x34,0x20,0x19] -[0xff,0x37,0x22,0x59] -[0x5f,0x34,0x20,0x59] -[0xff,0x37,0x22,0x59] - -# CHECK: ldtxr x9, [sp] -# CHECK-NEXT: ldtxr x9, [sp] -# CHECK-NEXT: ldtxr x10, [x11] -# CHECK-NEXT: ldtxr x10, [x11] -# CHECK-NEXT: sttxr wzr, w4, [sp] -# CHECK-NEXT: sttxr wzr, w4, [sp] -# CHECK-NEXT: sttxr w5, x6, [x7] -# CHECK-NEXT: sttxr w5, x6, [x7] -# CHECK-NEXT: ldatxr x9, [sp] -# CHECK-NEXT: ldatxr x10, [x11] -# CHECK-NEXT: stltxr w2, w4, [sp] -# CHECK-NEXT: stltxr w5, x6, [x7] -# CHECK-NEXT: ldtp x21, x29, [x2, #504] -# CHECK-NEXT: ldtp x22, x23, [x3, #-512] -# CHECK-NEXT: ldtp x24, x25, [x4, #8] -# CHECK-NEXT: sttp x3, x5, [sp], #16 -# CHECK-NEXT: sttp x3, x5, [sp, #8]! -# CHECK-NEXT: sttp q3, q5, [sp] -# CHECK-NEXT: sttp q17, q19, [sp, #1008] -# CHECK-NEXT: ldtp x21, x29, [x2], #504 -# CHECK-NEXT: ldtp x22, x23, [x3], #-512 -# CHECK-NEXT: ldtp x24, x25, [x4], #8 -# CHECK-NEXT: sttp q3, q5, [sp], #0 -# CHECK-NEXT: sttp q17, q19, [sp], #1008 -# CHECK-NEXT: ldtp q23, q29, [x1], #-1024 -# CHECK-NEXT: ldtp x21, x29, [x2, #504]! -# CHECK-NEXT: ldtp x22, x23, [x3, #-512]! -# CHECK-NEXT: ldtp x24, x25, [x4, #8]! -# CHECK-NEXT: sttp q3, q5, [sp, #0]! -# CHECK-NEXT: sttp q17, q19, [sp, #1008]! -# CHECK-NEXT: ldtp q23, q29, [x1, #-1024]! -# CHECK-NEXT: ldtnp x21, x29, [x2, #504] -# CHECK-NEXT: ldtnp x22, x23, [x3, #-512] -# CHECK-NEXT: ldtnp x24, x25, [x4, #8] -# CHECK-NEXT: ldtnp q23, q29, [x1, #-1024] -# CHECK-NEXT: sttnp x3, x5, [sp] -# CHECK-NEXT: sttnp x17, x19, [sp, #64] -# CHECK-NEXT: sttnp q3, q5, [sp] -# CHECK-NEXT: sttnp q17, q19, [sp, #1008] -# CHECK-NEXT: swpt w7, wzr, [x5] -# CHECK-NEXT: swpt x9, xzr, [sp] -# CHECK-NEXT: swpta w7, wzr, [x5] -# CHECK-NEXT: swpta x9, xzr, [sp] -# CHECK-NEXT: swptl w7, wzr, [x5] -# CHECK-NEXT: swptl x9, xzr, [sp] -# CHECK-NEXT: swptal w7, wzr, [x5] -# CHECK-NEXT: swptal x9, xzr, [sp] -# CHECK-NEXT: cast x0, x1, [x2] -# CHECK-NEXT: cast x0, x1, [sp] -# CHECK-NEXT: casat x0, x1, [x2] -# CHECK-NEXT: casat x0, x1, [sp] -# CHECK-NEXT: casalt x0, x1, [x2] -# CHECK-NEXT: casalt x0, x1, [sp] -# CHECK-NEXT: caslt x0, x1, [x2] -# CHECK-NEXT: caslt x0, x1, [sp] -# CHECK-NEXT: caspt x0, x1, x2, x3, [x4] -# CHECK-NEXT: caspt x0, x1, x2, x3, [sp] -# CHECK-NEXT: caspat x0, x1, x2, x3, [x4] -# CHECK-NEXT: caspat x0, x1, x2, x3, [sp] -# CHECK-NEXT: casplt x0, x1, x2, x3, [x4] -# CHECK-NEXT: casplt x0, x1, x2, x3, [sp] -# CHECK-NEXT: caspalt x0, x1, x2, x3, [x4] -# CHECK-NEXT: caspalt x0, x1, x2, x3, [sp] -# CHECK-NEXT: sttadd w7, [x5] -# CHECK-NEXT: sttadd x9, [sp] -# CHECK-NEXT: ldtadda w7, wzr, [x5] -# CHECK-NEXT: ldtadda x9, xzr, [sp] -# CHECK-NEXT: sttaddl w7, [x5] -# CHECK-NEXT: sttaddl x9, [sp] -# CHECK-NEXT: ldtaddal w7, wzr, [x5] -# CHECK-NEXT: ldtaddal x9, xzr, [sp] -# CHECK-NEXT: sttclr w7, [x5] -# CHECK-NEXT: sttclr x9, [sp] -# CHECK-NEXT: sttclrl w7, [x5] -# CHECK-NEXT: sttclrl x9, [sp] -# CHECK-NEXT: ldtclra w7, wzr, [x5] -# CHECK-NEXT: ldtclra x9, xzr, [sp] -# CHECK-NEXT: ldtclral w7, wzr, [x5] -# CHECK-NEXT: ldtclral x9, xzr, [sp] -# CHECK-NEXT: sttset w7, [x5] -# CHECK-NEXT: sttset x9, [sp] -# CHECK-NEXT: sttsetl w7, [x5] -# CHECK-NEXT: sttsetl x9, [sp] -# CHECK-NEXT: ldtseta w7, wzr, [x5] -# CHECK-NEXT: ldtseta x9, xzr, [sp] -# CHECK-NEXT: ldtsetal w7, wzr, [x5] -# CHECK-NEXT: ldtsetal x9, xzr, [sp] -# CHECK-NEXT: sttadd w0, [x2] -# CHECK-NEXT: sttadd w2, [sp] -# CHECK-NEXT: sttadd x0, [x2] -# CHECK-NEXT: sttadd x2, [sp] -# CHECK-NEXT: sttadd w0, [x2] -# CHECK-NEXT: sttadd w2, [sp] -# CHECK-NEXT: sttadd x0, [x2] -# CHECK-NEXT: sttadd x2, [sp] -# CHECK-NEXT: sttadd w0, [x2] -# CHECK-NEXT: sttadd w2, [sp] -# CHECK-NEXT: sttadd x0, [x2] -# CHECK-NEXT: sttadd x2, [sp] -# CHECK-NEXT: sttadd w0, [x2] -# CHECK-NEXT: sttadd w2, [sp] -# CHECK-NEXT: sttadd x0, [x2] -# CHECK-NEXT: sttadd x2, [sp] -# CHECK-NEXT: sttclr w0, [x2] -# CHECK-NEXT: sttclr w2, [sp] -# CHECK-NEXT: sttclr x0, [x2] -# CHECK-NEXT: sttclr x2, [sp] -# CHECK-NEXT: sttclr w0, [x2] -# CHECK-NEXT: sttclr w2, [sp] -# CHECK-NEXT: sttclr x0, [x2] -# CHECK-NEXT: sttclr x2, [sp] -# CHECK-NEXT: sttclr w0, [x2] -# CHECK-NEXT: sttclr w2, [sp] -# CHECK-NEXT: sttclr x0, [x2] -# CHECK-NEXT: sttclr x2, [sp] -# CHECK-NEXT: sttclr w0, [x2] -# CHECK-NEXT: sttclr x2, [sp] -# CHECK-NEXT: sttclr x0, [x2] -# CHECK-NEXT: sttclr x2, [sp] -# CHECK-NEXT: sttset w0, [x2] -# CHECK-NEXT: sttset w2, [sp] -# CHECK-NEXT: sttset x0, [x2] -# CHECK-NEXT: sttset x2, [sp] -# CHECK-NEXT: sttset w0, [x2] -# CHECK-NEXT: sttset w2, [sp] -# CHECK-NEXT: sttset x0, [x2] -# CHECK-NEXT: sttset x2, [sp] -# CHECK-NEXT: sttset w0, [x2] -# CHECK-NEXT: sttset w2, [sp] -# CHECK-NEXT: sttset x0, [x2] -# CHECK-NEXT: sttset x2, [sp] -# CHECK-NEXT: sttset w0, [x2] -# CHECK-NEXT: sttset x2, [sp] -# CHECK-NEXT: sttset x0, [x2] -# CHECK-NEXT: sttset x2, [sp] diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt deleted file mode 100644 index b9ff0a4d209b..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt +++ /dev/null @@ -1,50 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -#------------------------------------------------------------------------------ -# Armv9.6-A FEAT_MPAM Extensions -#------------------------------------------------------------------------------ - -[0x80,0xa5,0x1e,0xd5] -# CHECK: msr MPAMBW3_EL3, x0 - -[0x80,0xa5,0x1c,0xd5] -# CHECK: msr MPAMBW2_EL2, x0 - -[0x80,0xa5,0x18,0xd5] -# CHECK: msr MPAMBW1_EL1, x0 - -[0x80,0xa5,0x1d,0xd5] -# CHECK: msr MPAMBW1_EL12, x0 - -[0xa0,0xa5,0x18,0xd5] -# CHECK: msr MPAMBW0_EL1, x0 - -[0xc0,0xa5,0x1c,0xd5] -# CHECK: msr MPAMBWCAP_EL2, x0 - -[0xe0,0xa5,0x18,0xd5] -# CHECK: msr MPAMBWSM_EL1, x0 - -[0xa0,0xa4,0x38,0xd5] -# CHECK: mrs x0, MPAMBWIDR_EL1 - -[0x80,0xa5,0x3e,0xd5] -# CHECK: mrs x0, MPAMBW3_EL3 - -[0x80,0xa5,0x3c,0xd5] -# CHECK: mrs x0, MPAMBW2_EL2 - -[0x80,0xa5,0x38,0xd5] -# CHECK: mrs x0, MPAMBW1_EL1 - -[0x80,0xa5,0x3d,0xd5] -# CHECK: mrs x0, MPAMBW1_EL12 - -[0xa0,0xa5,0x38,0xd5] -# CHECK: mrs x0, MPAMBW0_EL1 - -[0xc0,0xa5,0x3c,0xd5] -# CHECK: mrs x0, MPAMBWCAP_EL2 - -[0xe0,0xa5,0x38,0xd5] -# CHECK: mrs x0, MPAMBWSM_EL1 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt deleted file mode 100644 index 5c3b57a871b9..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt +++ /dev/null @@ -1,11 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+occmo -mattr=+mte -disassemble < %s | FileCheck %s -[0x0c,0x7f,0x0b,0xd5] -[0xe0,0x7f,0x0b,0xd5] -[0x0d,0x7b,0x0b,0xd5] -[0xe1,0x7b,0x0b,0xd5] - -# CHECK: dc civaoc, x12 -# CHECK-NEXT: dc cigdvaoc, x0 -# CHECK-NEXT: dc cvaoc, x13 -# CHECK-NEXT: dc cgdvaoc, x1 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt deleted file mode 100644 index 3855ce035a4c..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt +++ /dev/null @@ -1,8 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mc -triple aarch64 -disassemble -mattr=+pcdphint %s | FileCheck %s - -[0x1f,0x96,0x01,0xd5] -[0x3f,0x96,0x01,0xd5] - -# CHECK: stshh keep -# CHECK-NEXT: stshh strm diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt deleted file mode 100644 index 75129ac48566..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt +++ /dev/null @@ -1,18 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mc -triple aarch64 -disassemble %s | FileCheck %s - -[0x00,0x70,0x0e,0xd5] -[0x01,0x70,0x0e,0xd5] -[0x02,0x70,0x0e,0xd5] -[0x11,0x70,0x0e,0xd5] -[0x1e,0x70,0x0e,0xd5] -[0xa3,0x21,0x3e,0xd5] -[0xa4,0x21,0x1e,0xd5] - -# CHECK: apas x0 -# CHECK-NEXT: apas x1 -# CHECK-NEXT: apas x2 -# CHECK-NEXT: apas x17 -# CHECK-NEXT: apas x30 -# CHECK-NEXT: mrs x3, GPCBW_EL3 -# CHECK-NEXT: msr GPCBW_EL3, x4 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt deleted file mode 100644 index 30d0a6032188..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt +++ /dev/null @@ -1,101 +0,0 @@ -# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mc -triple aarch64 -disassemble < %s 2> %t | FileCheck %s - -[0x03,0x14,0x38,0xd5] -[0x03,0x14,0x3c,0xd5] -[0x03,0x14,0x3d,0xd5] -[0x43,0x14,0x38,0xd5] -[0x43,0x14,0x3c,0xd5] -[0x43,0x14,0x3d,0xd5] -[0x63,0x14,0x38,0xd5] -[0x63,0x14,0x3c,0xd5] -[0x63,0x14,0x3d,0xd5] -[0x83,0x14,0x38,0xd5] -[0xc3,0x14,0x38,0xd5] -[0xe3,0x14,0x38,0xd5] -[0x43,0x27,0x38,0xd5] -[0x43,0x27,0x3c,0xd5] -[0x43,0x27,0x3d,0xd5] -[0x63,0x27,0x38,0xd5] -[0x63,0x27,0x3c,0xd5] -[0x63,0x27,0x3d,0xd5] -[0xc3,0x27,0x38,0xd5] -[0xe3,0x27,0x38,0xd5] -[0x23,0x14,0x38,0xd5] -[0x23,0x14,0x3c,0xd5] -[0x23,0x14,0x3d,0xd5] -[0xa3,0x14,0x38,0xd5] - -[0x03,0x14,0x18,0xd5] -[0x03,0x14,0x1c,0xd5] -[0x03,0x14,0x1d,0xd5] -[0x43,0x14,0x18,0xd5] -[0x43,0x14,0x1c,0xd5] -[0x43,0x14,0x1d,0xd5] -[0x63,0x14,0x18,0xd5] -[0x63,0x14,0x1c,0xd5] -[0x63,0x14,0x1d,0xd5] -[0x83,0x14,0x18,0xd5] -[0xc3,0x14,0x18,0xd5] -[0xe3,0x14,0x18,0xd5] -[0x43,0x27,0x18,0xd5] -[0x43,0x27,0x1c,0xd5] -[0x43,0x27,0x1d,0xd5] -[0x63,0x27,0x18,0xd5] -[0x63,0x27,0x1c,0xd5] -[0x63,0x27,0x1d,0xd5] -[0xc3,0x27,0x18,0xd5] -[0xe3,0x27,0x18,0xd5] -[0x23,0x14,0x18,0xd5] -[0x23,0x14,0x1c,0xd5] -[0x23,0x14,0x1d,0xd5] -[0xa3,0x14,0x18,0xd5] - -# CHECK: mrs x3, SCTLRMASK_EL1 -# CHECK-NEXT: mrs x3, SCTLRMASK_EL2 -# CHECK-NEXT: mrs x3, SCTLRMASK_EL12 -# CHECK-NEXT: mrs x3, CPACRMASK_EL1 -# CHECK-NEXT: mrs x3, CPTRMASK_EL2 -# CHECK-NEXT: mrs x3, CPACRMASK_EL12 -# CHECK-NEXT: mrs x3, SCTLR2MASK_EL1 -# CHECK-NEXT: mrs x3, SCTLR2MASK_EL2 -# CHECK-NEXT: mrs x3, SCTLR2MASK_EL12 -# CHECK-NEXT: mrs x3, CPACRALIAS_EL1 -# CHECK-NEXT: mrs x3, SCTLRALIAS_EL1 -# CHECK-NEXT: mrs x3, SCTLR2ALIAS_EL1 -# CHECK-NEXT: mrs x3, TCRMASK_EL1 -# CHECK-NEXT: mrs x3, TCRMASK_EL2 -# CHECK-NEXT: mrs x3, TCRMASK_EL12 -# CHECK-NEXT: mrs x3, TCR2MASK_EL1 -# CHECK-NEXT: mrs x3, TCR2MASK_EL2 -# CHECK-NEXT: mrs x3, TCR2MASK_EL12 -# CHECK-NEXT: mrs x3, TCRALIAS_EL1 -# CHECK-NEXT: mrs x3, TCR2ALIAS_EL1 -# CHECK-NEXT: mrs x3, ACTLRMASK_EL1 -# CHECK-NEXT: mrs x3, ACTLRMASK_EL2 -# CHECK-NEXT: mrs x3, ACTLRMASK_EL12 -# CHECK-NEXT: mrs x3, ACTLRALIAS_EL1 -# CHECK-NEXT: msr SCTLRMASK_EL1, x3 -# CHECK-NEXT: msr SCTLRMASK_EL2, x3 -# CHECK-NEXT: msr SCTLRMASK_EL12, x3 -# CHECK-NEXT: msr CPACRMASK_EL1, x3 -# CHECK-NEXT: msr CPTRMASK_EL2, x3 -# CHECK-NEXT: msr CPACRMASK_EL12, x3 -# CHECK-NEXT: msr SCTLR2MASK_EL1, x3 -# CHECK-NEXT: msr SCTLR2MASK_EL2, x3 -# CHECK-NEXT: msr SCTLR2MASK_EL12, x3 -# CHECK-NEXT: msr CPACRALIAS_EL1, x3 -# CHECK-NEXT: msr SCTLRALIAS_EL1, x3 -# CHECK-NEXT: msr SCTLR2ALIAS_EL1, x3 -# CHECK-NEXT: msr TCRMASK_EL1, x3 -# CHECK-NEXT: msr TCRMASK_EL2, x3 -# CHECK-NEXT: msr TCRMASK_EL12, x3 -# CHECK-NEXT: msr TCR2MASK_EL1, x3 -# CHECK-NEXT: msr TCR2MASK_EL2, x3 -# CHECK-NEXT: msr TCR2MASK_EL12, x3 -# CHECK-NEXT: msr TCRALIAS_EL1, x3 -# CHECK-NEXT: msr TCR2ALIAS_EL1, x3 -# CHECK-NEXT: msr ACTLRMASK_EL1, x3 -# CHECK-NEXT: msr ACTLRMASK_EL2, x3 -# CHECK-NEXT: msr ACTLRMASK_EL12, x3 -# CHECK-NEXT: msr ACTLRALIAS_EL1, x3 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-statistical-profiling.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-statistical-profiling.txt deleted file mode 100644 index 446e2f0eb05c..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-statistical-profiling.txt +++ /dev/null @@ -1,15 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0x60,0x9a,0x1d,0xd5] -# CHECK: msr PMBSR_EL12, x0 -[0x60,0x9a,0x1c,0xd5] -# CHECK: msr PMBSR_EL2, x0 -[0x60,0x9a,0x1e,0xd5] -# CHECK: msr PMBSR_EL3, x0 - -[0x60,0x9a,0x3d,0xd5] -# CHECK: mrs x0, PMBSR_EL12 -[0x60,0x9a,0x3c,0xd5] -# CHECK: mrs x0, PMBSR_EL2 -[0x60,0x9a,0x3e,0xd5] -# CHECK: mrs x0, PMBSR_EL3 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-trbe-exception.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-trbe-exception.txt deleted file mode 100644 index 4b39e107538d..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-trbe-exception.txt +++ /dev/null @@ -1,15 +0,0 @@ -# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s - -[0x60,0x9b,0x1d,0xd5] -# CHECK: msr TRBSR_EL12, x0 -[0x60,0x9b,0x1c,0xd5] -# CHECK: msr TRBSR_EL2, x0 -[0x60,0x9b,0x1e,0xd5] -# CHECK: msr TRBSR_EL3, x0 - -[0x60,0x9b,0x3d,0xd5] -# CHECK: mrs x0, TRBSR_EL12 -[0x60,0x9b,0x3c,0xd5] -# CHECK: mrs x0, TRBSR_EL2 -[0x60,0x9b,0x3e,0xd5] -# CHECK: mrs x0, TRBSR_EL3 diff --git a/llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt b/llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt deleted file mode 100644 index c5d931d46ca6..000000000000 --- a/llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt +++ /dev/null @@ -1,54 +0,0 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+mec -disassemble %s | FileCheck %s -# RUN: llvm-mc -triple=aarch64 -disassemble %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-MEC - -[0xe0,0xa8,0x3c,0xd5] -# CHECK: mrs x0, MECIDR_EL2 -# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_7 -[0x00,0xa8,0x3c,0xd5] -# CHECK: mrs x0, MECID_P0_EL2 -# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_0 -[0x20,0xa8,0x3c,0xd5] -# CHECK: mrs x0, MECID_A0_EL2 -# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_1 -[0x40,0xa8,0x3c,0xd5] -# CHECK: mrs x0, MECID_P1_EL2 -# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_2 -[0x60,0xa8,0x3c,0xd5] -# CHECK: mrs x0, MECID_A1_EL2 -# CHECK-NO-MEC: mrs x0, S3_4_C10_C8_3 -[0x00,0xa9,0x3c,0xd5] -# CHECK: mrs x0, VMECID_P_EL2 -# CHECK-NO-MEC: mrs x0, S3_4_C10_C9_0 -[0x20,0xa9,0x3c,0xd5] -# CHECK: mrs x0, VMECID_A_EL2 -# CHECK-NO-MEC: mrs x0, S3_4_C10_C9_1 -[0x20,0xaa,0x3e,0xd5] -# CHECK: mrs x0, MECID_RL_A_EL3 -# CHECK-NO-MEC: mrs x0, S3_6_C10_C10_1 -[0x00,0xa8,0x1c,0xd5] -# CHECK: msr MECID_P0_EL2, x0 -# CHECK-NO-MEC: msr S3_4_C10_C8_0, x0 -[0x20,0xa8,0x1c,0xd5] -# CHECK: msr MECID_A0_EL2, x0 -# CHECK-NO-MEC: msr S3_4_C10_C8_1, x0 -[0x40,0xa8,0x1c,0xd5] -# CHECK: msr MECID_P1_EL2, x0 -# CHECK-NO-MEC: msr S3_4_C10_C8_2, x0 -[0x60,0xa8,0x1c,0xd5] -# CHECK: msr MECID_A1_EL2, x0 -# CHECK-NO-MEC: msr S3_4_C10_C8_3, x0 -[0x00,0xa9,0x1c,0xd5] -# CHECK: msr VMECID_P_EL2, x0 -# CHECK-NO-MEC: msr S3_4_C10_C9_0, x0 -[0x20,0xa9,0x1c,0xd5] -# CHECK: msr VMECID_A_EL2, x0 -# CHECK-NO-MEC: msr S3_4_C10_C9_1, x0 -[0x20,0xaa,0x1e,0xd5] -# CHECK: msr MECID_RL_A_EL3, x0 -# CHECK-NO-MEC: msr S3_6_C10_C10_1, x0 -[0xe0,0x7e,0x0c,0xd5] -# CHECK: dc cigdpae, x0 -# CHECK-NO-MEC: sys #4, c7, c14, #7, x0 -[0x00,0x7e,0x0c,0xd5] -# CHECK: dc cipae, x0 -# CHECK-NO-MEC: sys #4, c7, c14, #0, x0 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt index d72009bc017f..361c49b34480 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt @@ -32,3 +32,6 @@ # GFX1250: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1 ; encoding: [0x22,0xf8,0x01,0xb9] 0x22,0xf8,0x01,0xb9 + +# GFX1250: s_setreg_b32 hwreg(HW_REG_IB_STS2), s1 ; encoding: [0x1c,0xf8,0x01,0xb9] +0x1c,0xf8,0x01,0xb9 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt index e7026df3c0e2..af94fbc7824a 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt @@ -35,3 +35,9 @@ # GFX1250: s_monitor_sleep 1 ; encoding: [0x01,0x00,0x84,0xbf] 0x01,0x00,0x84,0xbf + +# GFX1250: s_sendmsg sendmsg(MSG_SAVEWAVE_HAS_TDM) ; encoding: [0x0a,0x00,0xb6,0xbf] +0x0a,0x00,0xb6,0xbf + +# GFX1250: s_barrier_wait 0xfffd ; encoding: [0xfd,0xff,0x94,0xbf] +0xfd,0xff,0x94,0xbf diff --git a/llvm/test/MC/RISCV/rv32p-invalid.s b/llvm/test/MC/RISCV/rv32p-invalid.s index da3c67b73d0a..2ecce5fec84c 100644 --- a/llvm/test/MC/RISCV/rv32p-invalid.s +++ b/llvm/test/MC/RISCV/rv32p-invalid.s @@ -1,19 +1,35 @@ # RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-p %s 2>&1 \ -# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +# RUN: | FileCheck %s # Imm overflow -pli.h a0, 0x400 -# CHECK-ERROR: immediate must be an integer in the range [-512, 511] -plui.h a1, 0x400 -# CHECK-ERROR: immediate must be an integer in the range [-512, 1023] -pli.b a0, 0x200 -# CHECK-ERROR: immediate must be an integer in the range [0, 255] - -pslli.b a6, a7, 100 -# CHECK-ERROR: immediate must be an integer in the range [0, 7] -pslli.h ra, sp, 100 -# CHECK-ERROR: immediate must be an integer in the range [0, 15] -psslai.h t0, t1, 100 -# CHECK-ERROR: immediate must be an integer in the range [0, 15] -sslai a4, a5, -1 -# CHECK-ERROR: immediate must be an integer in the range [0, 31] +pli.h a0, 0x400 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [-512, 511] +plui.h a1, 0x400 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-512, 1023] +pli.b a0, 0x200 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 255] + +pslli.b a6, a7, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7] +pslli.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +pslli.w ra, sp, 12 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set + +psslai.h t0, t1, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 15] +psslai.w t0, t1, 27 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +sslai a4, a5, -1 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] + +psrli.b a6, a7, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7] +psrli.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +psrli.w ra, sp, 31 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set + +pusati.h ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 15] +pusati.w ra, sp, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +usati ra, sp, 100 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] + +psrai.b a6, a7, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7] +psrai.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +psrai.w ra, sp, 10 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set + +psrari.h ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 15] +psrari.w ra, sp, 15 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +srari ra, sp, 100 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] + +psati.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +psati.w ra, sp, 24 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +sati ra, sp, 100 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s index ffff0f25642a..1d0fb6d95781 100644 --- a/llvm/test/MC/RISCV/rv32p-valid.s +++ b/llvm/test/MC/RISCV/rv32p-valid.s @@ -76,3 +76,33 @@ plui.h gp, 32 # CHECK-ASM-AND-OBJ: plui.h gp, -412 # CHECK-ASM: encoding: [0x9b,0x21,0x99,0xf0] plui.h gp, 612 +# CHECK-ASM-AND-OBJ: psrli.b a6, a7, 0 +# CHECK-ASM: encoding: [0x1b,0xc8,0x88,0x80] +psrli.b a6, a7, 0 +# CHECK-ASM-AND-OBJ: psrli.h ra, sp, 1 +# CHECK-ASM: encoding: [0x9b,0x40,0x11,0x81] +psrli.h ra, sp, 1 +# CHECK-ASM-AND-OBJ: pusati.h t2, t3, 4 +# CHECK-ASM: encoding: [0x9b,0x43,0x4e,0xa1] +pusati.h t2, t3, 4 +# CHECK-ASM-AND-OBJ: usati t3, t4, 5 +# CHECK-ASM: encoding: [0x1b,0xce,0x5e,0xa2] +usati t3, t4, 5 +# CHECK-ASM-AND-OBJ: psrai.b a6, a7, 0 +# CHECK-ASM: encoding: [0x1b,0xc8,0x88,0xc0] +psrai.b a6, a7, 0 +# CHECK-ASM-AND-OBJ: psrai.h ra, sp, 1 +# CHECK-ASM: encoding: [0x9b,0x40,0x11,0xc1] +psrai.h ra, sp, 1 +# CHECK-ASM-AND-OBJ: psrari.h t4, t5, 6 +# CHECK-ASM: encoding: [0x9b,0x4e,0x6f,0xd1] +psrari.h t4, t5, 6 +# CHECK-ASM-AND-OBJ: srari t5, t6, 7 +# CHECK-ASM: encoding: [0x1b,0xcf,0x7f,0xd2] +srari t5, t6, 7 +# CHECK-ASM-AND-OBJ: psati.h t6, s11, 8 +# CHECK-ASM: encoding: [0x9b,0xcf,0x8d,0xe1] +psati.h t6, s11, 8 +# CHECK-ASM-AND-OBJ: sati s11, s10, 9 +# CHECK-ASM: encoding: [0x9b,0x4d,0x9d,0xe2] +sati s11, s10, 9 diff --git a/llvm/test/MC/RISCV/rv64p-invalid.s b/llvm/test/MC/RISCV/rv64p-invalid.s index 572a099fba4d..ccccba2e9e54 100644 --- a/llvm/test/MC/RISCV/rv64p-invalid.s +++ b/llvm/test/MC/RISCV/rv64p-invalid.s @@ -1,21 +1,35 @@ # RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-p %s 2>&1 \ -# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR +# RUN: | FileCheck %s # Imm overflow -pli.h a0, 0x400 -# CHECK-ERROR: immediate must be an integer in the range [-512, 511] -plui.h a1, 0x400 -# CHECK-ERROR: immediate must be an integer in the range [-512, 1023] -pli.w a1, -0x201 -# CHECK-ERROR: immediate must be an integer in the range [-512, 511] - -pslli.b a6, a7, 100 -# CHECK-ERROR: immediate must be an integer in the range [0, 7] -pslli.h ra, sp, 100 -# CHECK-ERROR: immediate must be an integer in the range [0, 15] -pslli.w ra, sp, 100 -# CHECK-ERROR: immediate must be an integer in the range [0, 31] -psslai.h t0, t1, 100 -# CHECK-ERROR: immediate must be an integer in the range [0, 15] -psslai.w a4, a5, -1 -# CHECK-ERROR: error: immediate must be an integer in the range [0, 31] +pli.h a0, 0x400 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [-512, 511] +plui.h a1, 0x400 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-512, 1023] +pli.w a1, -0x201 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [-512, 511] + +pslli.b a6, a7, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7] +pslli.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +pslli.w ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] + +psslai.h t0, t1, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 15] +psslai.w a4, a5, -1 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31] +sslai ra, sp, 10 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set + +psrli.b a6, a7, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7] +psrli.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +psrli.w ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] + +pusati.h ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 15] +pusati.w ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31] +usati ra, sp, 100 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 63] + +psrai.b a6, a7, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7] +psrai.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +psrai.w ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] + +psrari.h ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 15] +psrari.w ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31] +srari ra, sp, 100 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 63] + +psati.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +psati.w ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] +sati ra, sp, 100 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 63] diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s index a0d6eadfb6c3..13cfd5e8023b 100644 --- a/llvm/test/MC/RISCV/rv64p-valid.s +++ b/llvm/test/MC/RISCV/rv64p-valid.s @@ -55,7 +55,7 @@ max t3, t4, t5 # CHECK-ASM-AND-OBJ: maxu a4, a5, a6 # CHECK-ASM: encoding: [0x33,0xf7,0x07,0x0b] maxu a4, a5, a6 -# CHECK-ASM-AND-OBJ: pslli.b a6, a7 +# CHECK-ASM-AND-OBJ: pslli.b a6, a7, 0 # CHECK-ASM: encoding: [0x1b,0xa8,0x88,0x80] pslli.b a6, a7, 0 # CHECK-ASM-AND-OBJ: pslli.h ra, sp, 1 @@ -106,3 +106,48 @@ plui.w a2, 1 # CHECK-ASM-AND-OBJ: plui.w a2, -1 # CHECK-ASM: encoding: [0x1b,0xa6,0xff,0xf3] plui.w a2, 1023 +# CHECK-ASM-AND-OBJ: psrli.b a6, a7 +# CHECK-ASM: encoding: [0x1b,0xc8,0x88,0x80] +psrli.b a6, a7, 0 +# CHECK-ASM-AND-OBJ: psrli.h ra, sp, 1 +# CHECK-ASM: encoding: [0x9b,0x40,0x11,0x81] +psrli.h ra, sp, 1 +# CHECK-ASM-AND-OBJ: psrli.w ra, sp, 2 +# CHECK-ASM: encoding: [0x9b,0x40,0x21,0x82] +psrli.w ra, sp, 2 +# CHECK-ASM-AND-OBJ: pusati.h t2, t3, 4 +# CHECK-ASM: encoding: [0x9b,0x43,0x4e,0xa1] +pusati.h t2, t3, 4 +# CHECK-ASM-AND-OBJ: pusati.w t2, t3, 5 +# CHECK-ASM: encoding: [0x9b,0x43,0x5e,0xa2] +pusati.w t2, t3, 5 +# CHECK-ASM-AND-OBJ: usati t3, t4, 5 +# CHECK-ASM: encoding: [0x1b,0xce,0x5e,0xa4] +usati t3, t4, 5 +# CHECK-ASM-AND-OBJ: psrai.b a6, a7, 0 +# CHECK-ASM: encoding: [0x1b,0xc8,0x88,0xc0] +psrai.b a6, a7, 0 +# CHECK-ASM-AND-OBJ: psrai.h ra, sp, 1 +# CHECK-ASM: encoding: [0x9b,0x40,0x11,0xc1] +psrai.h ra, sp, 1 +# CHECK-ASM-AND-OBJ: psrai.w ra, sp, 2 +# CHECK-ASM: encoding: [0x9b,0x40,0x21,0xc2] +psrai.w ra, sp, 2 +# CHECK-ASM-AND-OBJ: psrari.h t4, t5, 6 +# CHECK-ASM: encoding: [0x9b,0x4e,0x6f,0xd1] +psrari.h t4, t5, 6 +# CHECK-ASM-AND-OBJ: psrari.w t5, t6, 7 +# CHECK-ASM: encoding: [0x1b,0xcf,0x7f,0xd2] +psrari.w t5, t6, 7 +# CHECK-ASM-AND-OBJ: srari t6, s11, 63 +# CHECK-ASM: encoding: [0x9b,0xcf,0xfd,0xd7] +srari t6, s11, 63 +# CHECK-ASM-AND-OBJ: psati.h s11, s10, 9 +# CHECK-ASM: encoding: [0x9b,0x4d,0x9d,0xe1] +psati.h s11, s10, 9 +# CHECK-ASM-AND-OBJ: psati.w s10, s9, 10 +# CHECK-ASM: encoding: [0x1b,0xcd,0xac,0xe2] +psati.w s10, s9, 10 +# CHECK-ASM-AND-OBJ: sati s9, s8, 32 +# CHECK-ASM: encoding: [0x9b,0x4c,0x0c,0xe6] +sati s9, s8, 32 diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td index 7fe63b1298ae..ef918d47b9d8 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td @@ -20,18 +20,18 @@ def Test0 : GICombineRule< // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] dst -// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/0, /*TempTypeIdx*/uint8_t(-1), +// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/0, /*TempTypeIdx*/255, // CHECK-NEXT: // MIs[0] src -// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/1, /*TempTypeIdx*/uint8_t(-2), +// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/1, /*TempTypeIdx*/254, // CHECK-NEXT: // MIs[0] Operand 2 -// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), -// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/uint8_t(-2), +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, +// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/254, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/1, /*Val*/GIMT_Encode8(0), -// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/uint8_t(-1), +// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/255, // CHECK-NEXT: // Combiner Rule #0: Test0 // CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), -// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/uint8_t(-2), /*Imm*/GIMT_Encode8(42), +// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/254, /*Imm*/GIMT_Encode8(42), // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td index 92baab91c620..8907cfe811ab 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td @@ -181,7 +181,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // CHECK-NEXT: // MIs[1] z -// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/1, /*Op*/1, GIMT_Encode8(-42), +// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/1, /*Op*/1, GIMT_Encode8(18446744073709551574u), // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 43, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #5: InOutInstTest1 diff --git a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td index 4a516c6e0235..7a86b5b726a8 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td +++ b/llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td @@ -617,11 +617,11 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), // R02N-NEXT: // MIs[0] Operand 2 // R02N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // -// R02C-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-2) +// R02C-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 254, // R02C-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // R02C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORI), // R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] -// R02C-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), +// R02C-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255, // R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // R02C-NEXT: GIR_RootConstrainSelectedInstOperands, // R02C-NEXT: // GIR_Coverage, 2, @@ -648,7 +648,7 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-3) +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 253, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XOR), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] @@ -676,11 +676,11 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-4) +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 252, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORlike), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), +// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255, // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, @@ -705,11 +705,11 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-5), +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 251, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORManyDefaults), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), +// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/255, // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 @@ -735,7 +735,7 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1) // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-6) +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 250, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -6:{ *:[i32] }) => (XORIb:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORIb), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] @@ -766,7 +766,7 @@ def XORIb : I<(outs GPR32:$dst), (ins mb:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) // NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ORN), // NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] diff --git a/llvm/test/TableGen/GlobalISelEmitter/int64min.td b/llvm/test/TableGen/GlobalISelEmitter/int64min.td new file mode 100644 index 000000000000..ccdb749f2c14 --- /dev/null +++ b/llvm/test/TableGen/GlobalISelEmitter/int64min.td @@ -0,0 +1,30 @@ +// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../../include -I %p/../Common %s | FileCheck %s + +include "llvm/Target/Target.td" +include "GlobalISelEmitterCommon.td" + +def GPR : RegisterClass<"MyTarget", [i64], 64, (add R0)>; +def ANDI : I<(outs GPR:$dst), (ins GPR:$src1, i64imm:$src2), []>; + +// CHECK-LABEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(59), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: // MIs[0] rs1 +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: // MIs[0] Operand 2 +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, +// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(9223372036854775808u), +// CHECK-NEXT: // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] }) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -9223372036854775808:{ *:[i64] }) +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANDI), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs1 +// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(9223372036854775808u), +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 0, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +def : Pat<(and GPR:$rs1, 0x8000000000000000), + (ANDI GPR:$rs1, 0x8000000000000000)>; diff --git a/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td b/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td index feef07502eed..fcc5f7e0b601 100644 --- a/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td +++ b/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td @@ -41,7 +41,7 @@ def MSP430LibraryWithCondCC : SystemRuntimeLibrary<isMSP430, >; -// CHECK: void llvm::RTLIB::RuntimeLibcallsInfo::setTargetRuntimeLibcallSets(const llvm::Triple &TT, FloatABI::ABIType FloatABI) { +// CHECK: void llvm::RTLIB::RuntimeLibcallsInfo::setTargetRuntimeLibcallSets(const llvm::Triple &TT, FloatABI::ABIType FloatABI, EABI EABIVersion, StringRef ABIName) { // CHECK: if (TT.getArch() == Triple::avr && TT.isOSHurd()) { // CHECK-NEXT: const CallingConv::ID DefaultCC = isFoo() ? CallingConv::Fast : CallingConv::GHC; // CHECK-NEXT: for (CallingConv::ID &Entry : LibcallImplCallingConvs) { diff --git a/llvm/test/TableGen/RuntimeLibcallEmitter.td b/llvm/test/TableGen/RuntimeLibcallEmitter.td index 59ccd2341c54..a2d946f3aa84 100644 --- a/llvm/test/TableGen/RuntimeLibcallEmitter.td +++ b/llvm/test/TableGen/RuntimeLibcallEmitter.td @@ -150,7 +150,7 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-NEXT: }; -// CHECK: void llvm::RTLIB::RuntimeLibcallsInfo::setTargetRuntimeLibcallSets(const llvm::Triple &TT, FloatABI::ABIType FloatABI) { +// CHECK: void llvm::RTLIB::RuntimeLibcallsInfo::setTargetRuntimeLibcallSets(const llvm::Triple &TT, FloatABI::ABIType FloatABI, EABI EABIVersion, StringRef ABIName) { // CHECK-NEXT: struct LibcallImplPair { // CHECK-NEXT: RTLIB::Libcall Func; // CHECK-NEXT: RTLIB::LibcallImpl Impl; diff --git a/llvm/test/Transforms/Coroutines/coro-async.ll b/llvm/test/Transforms/Coroutines/coro-async.ll index e5d2e6c2c42c..331d6a60bed6 100644 --- a/llvm/test/Transforms/Coroutines/coro-async.ll +++ b/llvm/test/Transforms/Coroutines/coro-async.ll @@ -496,6 +496,35 @@ entry: ; CHECK: call void @use(ptr null) ; CHECK: ret +@simpleFuncTu = global <{i32, i32}> <{ + i32 trunc (i64 sub (i64 ptrtoint (ptr @simpleFunc to i64), + i64 ptrtoint (ptr @simpleFuncTu to i64)) to i32), i32 16 }> + +define swifttailcc void @simpleFunc(ptr swiftasync %0) presplitcoroutine { +entry: + %1 = alloca ptr, align 8 + %2 = call token @llvm.coro.id.async(i32 16, i32 16, i32 0, ptr @simpleFuncTu) + %3 = call ptr @llvm.coro.begin(token %2, ptr null) + store ptr %0, ptr %1, align 8 + %4 = load ptr, ptr %1, align 8 + %5 = getelementptr inbounds <{ ptr, ptr }>, ptr %4, i32 0, i32 1 + %6 = load ptr, ptr %5, align 8 + %7 = load ptr, ptr %1, align 8 + %8 = call i1 (ptr, i1, ...) @llvm.coro.end.async(ptr %3, i1 false, ptr @simpleFunc.0, ptr %6, ptr %7) + unreachable +} + +; CHECK-LABEL: define swifttailcc void @simpleFunc(ptr swiftasync %0) { +; CHECK-NOT: define +; CHECK: [[RESUME:%.*]] = load ptr +; CHECK: musttail call swifttailcc void [[RESUME]] + +define internal swifttailcc void @simpleFunc.0(ptr %0, ptr %1) alwaysinline { +entry: + musttail call swifttailcc void %0(ptr swiftasync %1) + ret void +} + declare { ptr, ptr, ptr, ptr } @llvm.coro.suspend.async.sl_p0i8p0i8p0i8p0i8s(i32, ptr, ptr, ...) declare ptr @llvm.coro.prepare.async(ptr) declare token @llvm.coro.id.async(i32, i32, i32, ptr) diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll index 1a41c1f3e104..cb428097f2ae 100644 --- a/llvm/test/Transforms/InstCombine/icmp-add.ll +++ b/llvm/test/Transforms/InstCombine/icmp-add.ll @@ -3300,3 +3300,149 @@ entry: %cmp = icmp ult i32 %add, 253 ret i1 %cmp } + +; PR 152851 + +define i1 @val_is_aligend_const_pow2(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_pow2( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: [[_0:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4095 + %num.masked = and i32 %num.biased, -4096 + %_0 = icmp eq i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_const_pow2_add_commute(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_pow2_add_commute( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: [[_0:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 4095, %num + %num.masked = and i32 %num.biased, -4096 + %_0 = icmp eq i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_const_pow2_and_commute(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_pow2_and_commute( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: [[_0:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4095 + %num.masked = and i32 -4096, %num.biased + %_0 = icmp eq i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_const_pow2_icm_commute(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_pow2_icm_commute( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: [[_0:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4095 + %num.masked = and i32 %num.biased, -4096 + %_0 = icmp eq i32 %num, %num.masked + ret i1 %_0 +} + +; Should not work for non-power-of-two cases +define i1 @val_is_aligend_const_non_pow2(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_non_pow2( +; CHECK-NEXT: [[NUM_BIASED:%.*]] = add i32 [[NUM:%.*]], 6 +; CHECK-NEXT: [[NUM_MASKED:%.*]] = and i32 [[NUM_BIASED]], -7 +; CHECK-NEXT: [[_0:%.*]] = icmp eq i32 [[NUM_MASKED]], [[NUM]] +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 6 + %num.masked = and i32 %num.biased, -7 + %_0 = icmp eq i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_const_pow2_multiuse(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_pow2_multiuse( +; CHECK-NEXT: [[NUM_BIASED:%.*]] = add i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: [[NUM_MASKED:%.*]] = and i32 [[NUM_BIASED]], -4096 +; CHECK-NEXT: call void @use(i32 [[NUM_MASKED]]) +; CHECK-NEXT: [[_0:%.*]] = icmp eq i32 [[NUM_MASKED]], [[NUM]] +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4095 + %num.masked = and i32 %num.biased, -4096 + call void @use(i32 %num.masked) + %_0 = icmp eq i32 %num.masked, %num + ret i1 %_0 +} + +; Applies since number of instructions do not change +define i1 @val_is_aligend_const_pow2_multiuse1(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_pow2_multiuse1( +; CHECK-NEXT: [[NUM_BIASED:%.*]] = add i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: call void @use(i32 [[NUM_BIASED]]) +; CHECK-NEXT: [[NUM_MASKED:%.*]] = and i32 [[NUM_BIASED]], -4096 +; CHECK-NEXT: [[_0:%.*]] = icmp eq i32 [[NUM_MASKED]], [[NUM]] +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4095 + call void @use(i32 %num.biased) + %num.masked = and i32 %num.biased, -4096 + %_0 = icmp eq i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_const_pow2_ne(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_pow2_ne( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: [[_0:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4095 + %num.masked = and i32 %num.biased, -4096 + %_0 = icmp ne i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_const_mismatch(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_mismatch( +; CHECK-NEXT: [[NUM_BIASED:%.*]] = add i32 [[NUM:%.*]], 4095 +; CHECK-NEXT: [[NUM_MASKED:%.*]] = and i32 [[NUM_BIASED]], -4095 +; CHECK-NEXT: [[_0:%.*]] = icmp ne i32 [[NUM_MASKED]], [[NUM]] +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4095 + %num.masked = and i32 %num.biased, -4095 + %_0 = icmp ne i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_const_mismatch1(i32 %num) { +; CHECK-LABEL: @val_is_aligend_const_mismatch1( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[NUM:%.*]], -4096 +; CHECK-NEXT: [[NUM_MASKED:%.*]] = add i32 [[TMP1]], 4096 +; CHECK-NEXT: [[_0:%.*]] = icmp ne i32 [[NUM_MASKED]], [[NUM]] +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4096 + %num.masked = and i32 %num.biased, -4096 + %_0 = icmp ne i32 %num.masked, %num + ret i1 %_0 +} + +define i1 @val_is_aligend_pred_mismatch(i32 %num) { +; CHECK-LABEL: @val_is_aligend_pred_mismatch( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[NUM:%.*]], -4096 +; CHECK-NEXT: [[NUM_MASKED:%.*]] = add i32 [[TMP1]], 4096 +; CHECK-NEXT: [[_0:%.*]] = icmp sge i32 [[NUM_MASKED]], [[NUM]] +; CHECK-NEXT: ret i1 [[_0]] +; + %num.biased = add i32 %num, 4096 + %num.masked = and i32 %num.biased, -4096 + %_0 = icmp sge i32 %num.masked, %num + ret i1 %_0 +} diff --git a/llvm/test/Transforms/LICM/hoist-binop.ll b/llvm/test/Transforms/LICM/hoist-binop.ll index 1b1347776fb9..724f45979f6b 100644 --- a/llvm/test/Transforms/LICM/hoist-binop.ll +++ b/llvm/test/Transforms/LICM/hoist-binop.ll @@ -22,6 +22,31 @@ loop: br label %loop } +; Don't hoist ADD if the op has more than one use. +define void @add_two_uses(i64 %c1, i64 %c2) { +; CHECK-LABEL: @add_two_uses( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = add i64 [[INDEX]], [[C1:%.*]] +; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) +; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[STEP_ADD]], [[C2:%.*]] +; CHECK-NEXT: call void @use(i64 [[INDEX_NEXT]]) +; CHECK-NEXT: br label [[LOOP]] +; +entry: + br label %loop + +loop: + %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] + %step.add = add i64 %index, %c1 + call void @use(i64 %step.add) + %index.next = add i64 %step.add, %c2 + call void @use(i64 %index.next) + br label %loop +} + ; Hoist MUL and remove old op if unused. define void @mul_one_use(i64 %c1, i64 %c2) { ; CHECK-LABEL: @mul_one_use( @@ -51,8 +76,6 @@ define void @add_nuw(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add nuw i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -62,7 +85,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nuw i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nuw i64 %step.add, %c2 br label %loop } @@ -76,8 +98,6 @@ define void @add_nuw_comm(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw i64 [[C1]], [[INDEX]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add nuw i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -87,7 +107,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nuw i64 %c1, %index - call void @use(i64 %step.add) %index.next = add nuw i64 %step.add, %c2 br label %loop } @@ -101,8 +120,6 @@ define void @add_nuw_comm2(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add nuw i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -112,7 +129,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nuw i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nuw i64 %c2, %step.add br label %loop } @@ -126,8 +142,6 @@ define void @add_nuw_comm3(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw i64 [[C1]], [[INDEX]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add nuw i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -137,7 +151,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nuw i64 %c1, %index - call void @use(i64 %step.add) %index.next = add nuw i64 %c2, %step.add br label %loop } @@ -152,8 +165,6 @@ define void @add_nuw_twobinops(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw i64 [[C1]], [[INDEX]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add nuw i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -163,135 +174,134 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nuw i64 %c1, %index - call void @use(i64 %step.add) %c2.plus.2 = add nuw i64 %c2, 2 %index.next = add nuw i64 %step.add, %c2.plus.2 br label %loop } ; Hoist MUL and drop NUW even if both ops have it. -define void @mul_nuw(i64 %c1, i64 %c2) { +define void @mul_nuw(<2 x i64> %c1, <2 x i64> %c2) { ; CHECK-LABEL: @mul_nuw( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul i64 [[C1:%.*]], [[C2:%.*]] +; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul <2 x i64> [[C1:%.*]], [[C2:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) -; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul i64 [[INDEX]], [[INVARIANT_OP]] +; CHECK-NEXT: [[INDEX:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw <2 x i64> [[INDEX]], [[C1]] +; CHECK-NEXT: call void @use(<2 x i64> [[STEP_ADD]]) +; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul <2 x i64> [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; entry: br label %loop loop: - %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] - %step.add = mul nuw i64 %index, %c1 - call void @use(i64 %step.add) - %index.next = mul nuw i64 %step.add, %c2 + %index = phi <2 x i64> [ zeroinitializer, %entry ], [ %index.next, %loop ] + %step.add = mul nuw <2 x i64> %index, %c1 + call void @use(<2 x i64> %step.add) + %index.next = mul nuw <2 x i64> %step.add, %c2 br label %loop } ; Hoist MUL and drop NUW even if both ops have it. ; Version where operands are commuted. -define void @mul_nuw_comm(i64 %c1, i64 %c2) { +define void @mul_nuw_comm(<2 x i64> %c1, <2 x i64> %c2) { ; CHECK-LABEL: @mul_nuw_comm( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul i64 [[C1:%.*]], [[C2:%.*]] +; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul <2 x i64> [[C1:%.*]], [[C2:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw i64 [[C1]], [[INDEX]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) -; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul i64 [[INDEX]], [[INVARIANT_OP]] +; CHECK-NEXT: [[INDEX:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw <2 x i64> [[C1]], [[INDEX]] +; CHECK-NEXT: call void @use(<2 x i64> [[STEP_ADD]]) +; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul <2 x i64> [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; entry: br label %loop loop: - %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] - %step.add = mul nuw i64 %c1, %index - call void @use(i64 %step.add) - %index.next = mul nuw i64 %step.add, %c2 + %index = phi <2 x i64> [ zeroinitializer, %entry ], [ %index.next, %loop ] + %step.add = mul nuw <2 x i64> %c1, %index + call void @use(<2 x i64> %step.add) + %index.next = mul nuw <2 x i64> %step.add, %c2 br label %loop } ; Hoist MUL and drop NUW even if both ops have it. ; Another version where operands are commuted. -define void @mul_nuw_comm2(i64 %c1, i64 %c2) { +define void @mul_nuw_comm2(<2 x i64> %c1, <2 x i64> %c2) { ; CHECK-LABEL: @mul_nuw_comm2( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul i64 [[C1:%.*]], [[C2:%.*]] +; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul <2 x i64> [[C1:%.*]], [[C2:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) -; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul i64 [[INDEX]], [[INVARIANT_OP]] +; CHECK-NEXT: [[INDEX:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw <2 x i64> [[INDEX]], [[C1]] +; CHECK-NEXT: call void @use(<2 x i64> [[STEP_ADD]]) +; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul <2 x i64> [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; entry: br label %loop loop: - %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] - %step.add = mul nuw i64 %index, %c1 - call void @use(i64 %step.add) - %index.next = mul nuw i64 %c2, %step.add + %index = phi <2 x i64> [ zeroinitializer, %entry ], [ %index.next, %loop ] + %step.add = mul nuw <2 x i64> %index, %c1 + call void @use(<2 x i64> %step.add) + %index.next = mul nuw <2 x i64> %c2, %step.add br label %loop } ; Hoist MUL and drop NUW even if both ops have it. ; Another version where operands are commuted. -define void @mul_nuw_comm3(i64 %c1, i64 %c2) { +define void @mul_nuw_comm3(<2 x i64> %c1, <2 x i64> %c2) { ; CHECK-LABEL: @mul_nuw_comm3( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul i64 [[C1:%.*]], [[C2:%.*]] +; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul <2 x i64> [[C1:%.*]], [[C2:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw i64 [[C1]], [[INDEX]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) -; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul i64 [[INDEX]], [[INVARIANT_OP]] +; CHECK-NEXT: [[INDEX:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw <2 x i64> [[C1]], [[INDEX]] +; CHECK-NEXT: call void @use(<2 x i64> [[STEP_ADD]]) +; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul <2 x i64> [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; entry: br label %loop loop: - %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] - %step.add = mul nuw i64 %c1, %index - call void @use(i64 %step.add) - %index.next = mul nuw i64 %c2, %step.add + %index = phi <2 x i64> [ zeroinitializer, %entry ], [ %index.next, %loop ] + %step.add = mul nuw <2 x i64> %c1, %index + call void @use(<2 x i64> %step.add) + %index.next = mul nuw <2 x i64> %c2, %step.add br label %loop } ; Hoist MUL and drop NUW even if both ops have it. ; A version where the LHS and RHS of the outer BinOp are BinOps. -define void @mul_nuw_twobinops(i64 %c1, i64 %c2) { +define void @mul_nuw_twobinops(<2 x i64> %c1, <2 x i64> %c2) { ; CHECK-LABEL: @mul_nuw_twobinops( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[C2_PLUS_2:%.*]] = add nuw i64 [[C2:%.*]], 2 -; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul i64 [[C1:%.*]], [[C2_PLUS_2]] +; CHECK-NEXT: [[C2_PLUS_2:%.*]] = add nuw <2 x i64> [[C2:%.*]], splat (i64 2) +; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul <2 x i64> [[C1:%.*]], [[C2_PLUS_2]] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw i64 [[C1]], [[INDEX]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) -; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul i64 [[INDEX]], [[INVARIANT_OP]] +; CHECK-NEXT: [[INDEX:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nuw <2 x i64> [[C1]], [[INDEX]] +; CHECK-NEXT: call void @use(<2 x i64> [[STEP_ADD]]) +; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul <2 x i64> [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; entry: br label %loop loop: - %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] - %step.add = mul nuw i64 %c1, %index - call void @use(i64 %step.add) - %c2.plus.2 = add nuw i64 %c2, 2 - %index.next = mul nuw i64 %step.add, %c2.plus.2 + %index = phi <2 x i64> [ zeroinitializer, %entry ], [ %index.next, %loop ] + %step.add = mul nuw <2 x i64> %c1, %index + call void @use(<2 x i64> %step.add) + %c2.plus.2 = add nuw <2 x i64> %c2, <i64 2, i64 2> + %index.next = mul nuw <2 x i64> %step.add, %c2.plus.2 br label %loop } @@ -303,8 +313,6 @@ define void @add_no_nuw(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -314,7 +322,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nuw i64 %step.add, %c2 br label %loop } @@ -327,8 +334,6 @@ define void @add_no_nsw(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -338,7 +343,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nsw i64 %step.add, %c2 br label %loop } @@ -351,8 +355,6 @@ define void @add_no_nsw_2(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nsw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -362,7 +364,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nsw i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nsw i64 %step.add, %c2 br label %loop } @@ -375,8 +376,6 @@ define void @add_nuw_nsw(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw nsw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add nuw nsw i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -386,7 +385,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nuw nsw i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nuw nsw i64 %step.add, %c2 br label %loop } @@ -398,8 +396,6 @@ define void @add_both_nsw_first_nuw(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nuw nsw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -409,7 +405,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nuw nsw i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nsw i64 %step.add, %c2 br label %loop } @@ -421,8 +416,6 @@ define void @add_both_nsw_second_nuw(i64 %c1, i64 %c2) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add nsw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT_REASS]] = add i64 [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -432,33 +425,32 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add nsw i64 %index, %c1 - call void @use(i64 %step.add) %index.next = add nuw nsw i64 %step.add, %c2 br label %loop } ; ; Hoist MUL and drop NSW even if both ops have it. -define void @mul_no_nsw_2(i64 %c1, i64 %c2) { +define void @mul_no_nsw_2(<2 x i64> %c1, <2 x i64> %c2) { ; CHECK-LABEL: @mul_no_nsw_2( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul i64 [[C1:%.*]], [[C2:%.*]] +; CHECK-NEXT: [[INVARIANT_OP:%.*]] = mul <2 x i64> [[C1:%.*]], [[C2:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nsw i64 [[INDEX]], [[C1]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) -; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul i64 [[INDEX]], [[INVARIANT_OP]] +; CHECK-NEXT: [[INDEX:%.*]] = phi <2 x i64> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_REASS:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = mul nsw <2 x i64> [[INDEX]], [[C1]] +; CHECK-NEXT: call void @use(<2 x i64> [[STEP_ADD]]) +; CHECK-NEXT: [[INDEX_NEXT_REASS]] = mul <2 x i64> [[INDEX]], [[INVARIANT_OP]] ; CHECK-NEXT: br label [[LOOP]] ; entry: br label %loop loop: - %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] - %step.add = mul nsw i64 %index, %c1 - call void @use(i64 %step.add) - %index.next = mul nsw i64 %step.add, %c2 + %index = phi <2 x i64> [ zeroinitializer, %entry ], [ %index.next, %loop ] + %step.add = mul nsw <2 x i64> %index, %c1 + call void @use(<2 x i64> %step.add) + %index.next = mul nsw <2 x i64> %step.add, %c2 br label %loop } @@ -470,7 +462,6 @@ define void @diff_ops(i64 %c1, i64 %c2) { ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[STEP_ADD:%.*]] = add i64 [[INDEX]], [[C1:%.*]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT]] = mul i64 [[STEP_ADD]], [[C2:%.*]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -480,7 +471,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = add i64 %index, %c1 - call void @use(i64 %step.add) %index.next = mul i64 %step.add, %c2 br label %loop } @@ -493,7 +483,6 @@ define void @noassoc_ops(i64 %c1, i64 %c2) { ; CHECK: loop: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[STEP_ADD:%.*]] = sub i64 [[INDEX]], [[C1:%.*]] -; CHECK-NEXT: call void @use(i64 [[STEP_ADD]]) ; CHECK-NEXT: [[INDEX_NEXT]] = sub i64 [[STEP_ADD]], [[C2:%.*]] ; CHECK-NEXT: br label [[LOOP]] ; @@ -503,7 +492,6 @@ entry: loop: %index = phi i64 [ 0, %entry ], [ %index.next, %loop ] %step.add = sub i64 %index, %c1 - call void @use(i64 %step.add) %index.next = sub i64 %step.add, %c2 br label %loop } diff --git a/llvm/test/Transforms/LICM/sink-foldable.ll b/llvm/test/Transforms/LICM/sink-foldable.ll index d1cf3de5301b..59dea58a6ade 100644 --- a/llvm/test/Transforms/LICM/sink-foldable.ll +++ b/llvm/test/Transforms/LICM/sink-foldable.ll @@ -97,7 +97,7 @@ define ptr @test2(i32 %j, ptr readonly %P, ptr readnone %Q) { ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds ptr, ptr [[ADD_PTR]], i64 [[IDX2_EXT]] ; CHECK-NEXT: [[L1:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt ptr [[L1]], [[Q]] -; CHECK-NEXT: [[ADD_REASS]] = add i32 [[I_ADDR]], 2 +; CHECK-NEXT: [[ADD_REASS]] = add nsw i32 [[ADD_I]], 1 ; CHECK-NEXT: br i1 [[CMP2]], label [[LOOPEXIT2:%.*]], label [[FOR_COND]] ; CHECK: loopexit0: ; CHECK-NEXT: [[P0:%.*]] = phi ptr [ null, [[FOR_COND]] ] diff --git a/llvm/test/Transforms/LICM/update-scev-after-hoist.ll b/llvm/test/Transforms/LICM/update-scev-after-hoist.ll index e303d04ce319..8f9045350813 100644 --- a/llvm/test/Transforms/LICM/update-scev-after-hoist.ll +++ b/llvm/test/Transforms/LICM/update-scev-after-hoist.ll @@ -4,7 +4,7 @@ define i16 @main() { ; SCEV-EXPR-LABEL: 'main' ; SCEV-EXPR-NEXT: Classifying expressions for: @main -; SCEV-EXPR-NEXT: %mul = phi i16 [ 1, %entry ], [ %mul.n.3.reass, %loop ] +; SCEV-EXPR-NEXT: %mul = phi i16 [ 1, %entry ], [ %mul.n.3, %loop ] ; SCEV-EXPR-NEXT: --> %mul U: [0,-15) S: [-32768,32753) Exits: 4096 LoopDispositions: { %loop: Variant } ; SCEV-EXPR-NEXT: %div = phi i16 [ 32767, %entry ], [ %div.n.3, %loop ] ; SCEV-EXPR-NEXT: --> %div U: [-2048,-32768) S: [-2048,-32768) Exits: 7 LoopDispositions: { %loop: Variant } @@ -16,7 +16,7 @@ define i16 @main() { ; SCEV-EXPR-NEXT: --> %div.n.1 U: [-8192,8192) S: [-8192,8192) Exits: 1 LoopDispositions: { %loop: Variant } ; SCEV-EXPR-NEXT: %div.n.2 = sdiv i16 %div.n.1, 2 ; SCEV-EXPR-NEXT: --> %div.n.2 U: [-4096,4096) S: [-4096,4096) Exits: 0 LoopDispositions: { %loop: Variant } -; SCEV-EXPR-NEXT: %mul.n.3.reass = mul i16 %mul, 16 +; SCEV-EXPR-NEXT: %mul.n.3 = mul i16 %mul.n.reass.reass, 2 ; SCEV-EXPR-NEXT: --> (16 * %mul) U: [0,-15) S: [-32768,32753) Exits: 0 LoopDispositions: { %loop: Variant } ; SCEV-EXPR-NEXT: %div.n.3 = sdiv i16 %div.n.2, 2 ; SCEV-EXPR-NEXT: --> %div.n.3 U: [-2048,2048) S: [-2048,2048) Exits: 0 LoopDispositions: { %loop: Variant } diff --git a/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll b/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll index 901f228c6b67..ee6da8f528dd 100644 --- a/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll +++ b/llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll @@ -1,87 +1,91 @@ -; RUN: opt -S -passes=loop-vectorize,instcombine -force-vector-interleave=1 -force-vector-width=4 -force-target-supports-scalable-vectors=true -scalable-vectorization=on < %s | FileCheck %s --check-prefix=CHECKUF1 -; RUN: opt -S -passes=loop-vectorize,instcombine -force-vector-interleave=2 -force-vector-width=4 -force-target-supports-scalable-vectors=true -scalable-vectorization=on < %s | FileCheck %s --check-prefix=CHECKUF2 +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph\:" --version 5 +; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -force-target-supports-scalable-vectors=true -scalable-vectorization=on < %s | FileCheck %s --check-prefix=CHECKUF1 +; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=4 -force-target-supports-scalable-vectors=true -scalable-vectorization=on < %s | FileCheck %s --check-prefix=CHECKUF2 -; CHECKUF1: for.body.preheader: -; CHECKUF1-DAG: %wide.trip.count = zext nneg i32 %N to i64 -; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() -; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl nuw i64 %[[VSCALE]], 2 -; CHECKUF1-DAG: %min.iters.check = icmp ugt i64 %[[VSCALEX4]], %wide.trip.count - -; CHECKUF1: vector.ph: -; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() -; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl nuw i64 %[[VSCALE]], 2 -; CHECKUF1-DAG: %n.mod.vf = urem i64 %wide.trip.count, %[[VSCALEX4]] -; CHECKUF1: %n.vec = sub nsw i64 %wide.trip.count, %n.mod.vf - -; CHECKUF1: vector.body: -; CHECKUF1: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] -; CHECKUF1: %[[IDXB:.*]] = getelementptr inbounds double, ptr %b, i64 %index -; CHECKUF1: %wide.load = load <vscale x 4 x double>, ptr %[[IDXB]], align 8 -; CHECKUF1: %[[FADD:.*]] = fadd <vscale x 4 x double> %wide.load, splat (double 1.000000e+00) -; CHECKUF1: %[[IDXA:.*]] = getelementptr inbounds double, ptr %a, i64 %index -; CHECKUF1: store <vscale x 4 x double> %[[FADD]], ptr %[[IDXA]], align 8 -; CHECKUF1: %index.next = add nuw i64 %index, %[[VSCALEX4]] -; CHECKUF1: %[[CMP:.*]] = icmp eq i64 %index.next, %n.vec -; CHECKUF1: br i1 %[[CMP]], label %middle.block, label %vector.body, !llvm.loop !0 - - -; For an interleave factor of 2, vscale is scaled by 8 instead of 4 (and thus shifted left by 3 instead of 2). +; For an interleave factor of 2, vscale is scaled by 8 instead of 4. ; There is also the increment for the next iteration, e.g. instead of indexing IDXB, it indexes at IDXB + vscale * 4. - -; CHECKUF2: for.body.preheader: -; CHECKUF2-DAG: %wide.trip.count = zext nneg i32 %N to i64 -; CHECKUF2-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() -; CHECKUF2-DAG: %[[VSCALEX8:.*]] = shl nuw i64 %[[VSCALE]], 3 -; CHECKUF2-DAG: %min.iters.check = icmp ugt i64 %[[VSCALEX8]], %wide.trip.count - -; CHECKUF2: vector.ph: -; CHECKUF2-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() -; CHECKUF2-DAG: %[[VSCALEX8:.*]] = shl nuw i64 %[[VSCALE]], 3 -; CHECKUF2-DAG: %n.mod.vf = urem i64 %wide.trip.count, %[[VSCALEX8]] -; CHECKUF2: %n.vec = sub nsw i64 %wide.trip.count, %n.mod.vf - -; CHECKUF2: vector.body: -; CHECKUF2: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] -; CHECKUF2: %[[IDXB:.*]] = getelementptr inbounds double, ptr %b, i64 %index -; CHECKUF2: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() -; CHECKUF2: %[[VSCALE2:.*]] = shl i64 %[[VSCALE]], 5 -; CHECKUF2: %[[IDXB_NEXT:.*]] = getelementptr inbounds i8, ptr %[[IDXB]], i64 %[[VSCALE2]] -; CHECKUF2: %wide.load = load <vscale x 4 x double>, ptr %[[IDXB]], align 8 -; CHECKUF2: %wide.load{{[0-9]+}} = load <vscale x 4 x double>, ptr %[[IDXB_NEXT]], align 8 -; CHECKUF2: %[[FADD:.*]] = fadd <vscale x 4 x double> %wide.load, splat (double 1.000000e+00) -; CHECKUF2: %[[FADD_NEXT:.*]] = fadd <vscale x 4 x double> %wide.load{{[0-9]+}}, splat (double 1.000000e+00) -; CHECKUF2: %[[IDXA:.*]] = getelementptr inbounds double, ptr %a, i64 %index -; CHECKUF2: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64() -; CHECKUF2: %[[VSCALE2:.*]] = shl i64 %[[VSCALE]], 5 -; CHECKUF2: %[[IDXA_NEXT:.*]] = getelementptr inbounds i8, ptr %[[IDXA]], i64 %[[VSCALE2]] -; CHECKUF2: store <vscale x 4 x double> %[[FADD]], ptr %[[IDXA]], align 8 -; CHECKUF2: store <vscale x 4 x double> %[[FADD_NEXT]], ptr %[[IDXA_NEXT]], align 8 -; CHECKUF2: %index.next = add nuw i64 %index, %[[VSCALEX8]] -; CHECKUF2: %[[CMP:.*]] = icmp eq i64 %index.next, %n.vec -; CHECKUF2: br i1 %[[CMP]], label %middle.block, label %vector.body, !llvm.loop !0 - -define void @loop(i32 %N, ptr nocapture %a, ptr nocapture readonly %b) { +define void @loop(i64 %N, ptr noalias %a, ptr noalias %b) { +; CHECKUF1-LABEL: define void @loop( +; CHECKUF1-SAME: i64 [[N:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) { +; CHECKUF1-NEXT: [[ENTRY:.*:]] +; CHECKUF1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; CHECKUF1-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 4 +; CHECKUF1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]] +; CHECKUF1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECKUF1: [[VECTOR_PH]]: +; CHECKUF1-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; CHECKUF1-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 4 +; CHECKUF1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP6]] +; CHECKUF1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] +; CHECKUF1-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECKUF1: [[VECTOR_BODY]]: +; CHECKUF1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECKUF1-NEXT: [[TMP7:%.*]] = getelementptr inbounds double, ptr [[B]], i64 [[INDEX]] +; CHECKUF1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x double>, ptr [[TMP7]], align 8 +; CHECKUF1-NEXT: [[TMP8:%.*]] = fadd <vscale x 4 x double> [[WIDE_LOAD]], splat (double 1.000000e+00) +; CHECKUF1-NEXT: [[TMP9:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[INDEX]] +; CHECKUF1-NEXT: store <vscale x 4 x double> [[TMP8]], ptr [[TMP9]], align 8 +; CHECKUF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP6]] +; CHECKUF1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECKUF1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECKUF1: [[MIDDLE_BLOCK]]: +; CHECKUF1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] +; CHECKUF1-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] +; CHECKUF1: [[SCALAR_PH]]: +; +; CHECKUF2-LABEL: define void @loop( +; CHECKUF2-SAME: i64 [[N:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]]) { +; CHECKUF2-NEXT: [[ENTRY:.*:]] +; CHECKUF2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; CHECKUF2-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 8 +; CHECKUF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]] +; CHECKUF2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECKUF2: [[VECTOR_PH]]: +; CHECKUF2-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; CHECKUF2-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 8 +; CHECKUF2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP6]] +; CHECKUF2-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] +; CHECKUF2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECKUF2: [[VECTOR_BODY]]: +; CHECKUF2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECKUF2-NEXT: [[TMP7:%.*]] = getelementptr inbounds double, ptr [[B]], i64 [[INDEX]] +; CHECKUF2-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64() +; CHECKUF2-NEXT: [[TMP16:%.*]] = mul nuw i64 [[TMP8]], 4 +; CHECKUF2-NEXT: [[TMP9:%.*]] = getelementptr inbounds double, ptr [[TMP7]], i64 [[TMP16]] +; CHECKUF2-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x double>, ptr [[TMP7]], align 8 +; CHECKUF2-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 4 x double>, ptr [[TMP9]], align 8 +; CHECKUF2-NEXT: [[TMP10:%.*]] = fadd <vscale x 4 x double> [[WIDE_LOAD]], splat (double 1.000000e+00) +; CHECKUF2-NEXT: [[TMP11:%.*]] = fadd <vscale x 4 x double> [[WIDE_LOAD3]], splat (double 1.000000e+00) +; CHECKUF2-NEXT: [[TMP12:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[INDEX]] +; CHECKUF2-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64() +; CHECKUF2-NEXT: [[TMP17:%.*]] = mul nuw i64 [[TMP13]], 4 +; CHECKUF2-NEXT: [[TMP14:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 [[TMP17]] +; CHECKUF2-NEXT: store <vscale x 4 x double> [[TMP10]], ptr [[TMP12]], align 8 +; CHECKUF2-NEXT: store <vscale x 4 x double> [[TMP11]], ptr [[TMP14]], align 8 +; CHECKUF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP6]] +; CHECKUF2-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECKUF2-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECKUF2: [[MIDDLE_BLOCK]]: +; CHECKUF2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] +; CHECKUF2-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]] +; CHECKUF2: [[SCALAR_PH]]: +; entry: - %cmp7 = icmp sgt i32 %N, 0 - br i1 %cmp7, label %for.body.preheader, label %for.cond.cleanup - -for.body.preheader: ; preds = %entry - %wide.trip.count = zext i32 %N to i64 - br label %for.body - -for.cond.cleanup: ; preds = %for.body, %entry - ret void + br label %loop -for.body: ; preds = %for.body.preheader, %for.body - %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ] - %arrayidx = getelementptr inbounds double, ptr %b, i64 %indvars.iv +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %arrayidx = getelementptr inbounds double, ptr %b, i64 %iv %0 = load double, ptr %arrayidx, align 8 %add = fadd double %0, 1.000000e+00 - %arrayidx2 = getelementptr inbounds double, ptr %a, i64 %indvars.iv + %arrayidx2 = getelementptr inbounds double, ptr %a, i64 %iv store double %add, ptr %arrayidx2, align 8 - %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 - %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count - br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !1 + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp eq i64 %iv.next, %N + br i1 %ec, label %exit, label %loop, !llvm.loop !1 + +exit: + ret void } !1 = distinct !{!1, !2} diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll new file mode 100644 index 000000000000..fa25af5f3467 --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll @@ -0,0 +1,130 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -O3 -S %s | FileCheck %s + +target triple = "arm64-apple-macosx15.0.0" + +define i64 @std_find_i16_constant_offset_with_assumptions(ptr %first.coerce, i16 noundef signext %s) nofree nosync { +; CHECK-LABEL: define i64 @std_find_i16_constant_offset_with_assumptions( +; CHECK-SAME: ptr [[FIRST_COERCE:%.*]], i16 noundef signext [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[FIRST_COERCE]], i64 2) ] +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "dereferenceable"(ptr [[FIRST_COERCE]], i64 256) ] +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[FIRST_COERCE]] to i64 +; CHECK-NEXT: [[COERCE_VAL_PI_I:%.*]] = add i64 [[TMP0]], 256 +; CHECK-NEXT: [[COERCE_VAL_IP:%.*]] = inttoptr i64 [[COERCE_VAL_PI_I]] to ptr +; CHECK-NEXT: [[CMP_NOT6_I_I:%.*]] = icmp eq ptr [[FIRST_COERCE]], [[COERCE_VAL_IP]] +; CHECK-NEXT: br i1 [[CMP_NOT6_I_I]], label %[[RETURN:.*]], label %[[LOOP_HEADER:.*]] +; CHECK: [[LOOP_HEADER]]: +; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ [[FIRST_COERCE]], %[[ENTRY]] ] +; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[PTR_IV]], align 2 +; CHECK-NEXT: [[CMP2_I_I:%.*]] = icmp eq i16 [[TMP1]], [[S]] +; CHECK-NEXT: br i1 [[CMP2_I_I]], label %[[RETURN_LOOPEXIT:.*]], label %[[LOOP_LATCH]] +; CHECK: [[LOOP_LATCH]]: +; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 2 +; CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[COERCE_VAL_IP]] +; CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label %[[RETURN_LOOPEXIT]], label %[[LOOP_HEADER]] +; CHECK: [[RETURN_LOOPEXIT]]: +; CHECK-NEXT: [[MERGE_PH:%.*]] = phi ptr [ [[COERCE_VAL_IP]], %[[LOOP_LATCH]] ], [ [[PTR_IV]], %[[LOOP_HEADER]] ] +; CHECK-NEXT: [[DOTPRE:%.*]] = ptrtoint ptr [[MERGE_PH]] to i64 +; CHECK-NEXT: br label %[[RETURN]] +; CHECK: [[RETURN]]: +; CHECK-NEXT: [[RES_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE]], %[[RETURN_LOOPEXIT]] ], [ [[TMP0]], %[[ENTRY]] ] +; CHECK-NEXT: ret i64 [[RES_PRE_PHI]] +; +entry: + %first = alloca { ptr }, align 8 + %s.addr = alloca i16, align 2 + store ptr %first.coerce, ptr %first, align 8 + store i16 %s, ptr %s.addr, align 2 + %0 = load ptr, ptr %first, align 8 + call void @llvm.assume(i1 true) [ "align"(ptr %0, i64 2) ] + call void @llvm.assume(i1 true) [ "dereferenceable"(ptr %0, i64 256) ] + %start.ptr = load ptr, ptr %first, align 8 + %1 = load i64, ptr %first, align 8 + %coerce.val.pi.i = add i64 %1, 256 + %coerce.val.ip = inttoptr i64 %coerce.val.pi.i to ptr + %cmp.not6.i.i = icmp eq ptr %start.ptr, %coerce.val.ip + br i1 %cmp.not6.i.i, label %return, label %loop.ph + +loop.ph: + %2 = load i16, ptr %s.addr, align 2 + br label %loop.header + +loop.header: + %ptr.iv = phi ptr [ %start.ptr, %loop.ph ], [ %ptr.iv.next, %loop.latch ] + %3 = load i16, ptr %ptr.iv, align 2 + %cmp2.i.i = icmp eq i16 %3, %2 + br i1 %cmp2.i.i, label %return, label %loop.latch + +loop.latch: + %ptr.iv.next = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 2 + %cmp.not.i.i = icmp eq ptr %ptr.iv.next, %coerce.val.ip + br i1 %cmp.not.i.i, label %return, label %loop.header + +return: + %merge = phi ptr [ %start.ptr, %entry ], [ %coerce.val.ip, %loop.latch ], [ %ptr.iv, %loop.header ] + %res = ptrtoint ptr %merge to i64 + ret i64 %res +} + +define i64 @std_find_i16_constant_offset_no_assumptions(ptr %first.coerce, i16 noundef signext %s) nofree nosync { +; CHECK-LABEL: define i64 @std_find_i16_constant_offset_no_assumptions( +; CHECK-SAME: ptr [[FIRST_COERCE:%.*]], i16 noundef signext [[S:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[FIRST_COERCE]] to i64 +; CHECK-NEXT: [[COERCE_VAL_PI_I:%.*]] = add i64 [[TMP0]], 256 +; CHECK-NEXT: [[COERCE_VAL_IP:%.*]] = inttoptr i64 [[COERCE_VAL_PI_I]] to ptr +; CHECK-NEXT: [[CMP_NOT6_I_I:%.*]] = icmp eq ptr [[FIRST_COERCE]], [[COERCE_VAL_IP]] +; CHECK-NEXT: br i1 [[CMP_NOT6_I_I]], label %[[RETURN:.*]], label %[[LOOP_HEADER:.*]] +; CHECK: [[LOOP_HEADER]]: +; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ [[FIRST_COERCE]], %[[ENTRY]] ] +; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[PTR_IV]], align 2 +; CHECK-NEXT: [[CMP2_I_I:%.*]] = icmp eq i16 [[TMP1]], [[S]] +; CHECK-NEXT: br i1 [[CMP2_I_I]], label %[[RETURN_LOOPEXIT:.*]], label %[[LOOP_LATCH]] +; CHECK: [[LOOP_LATCH]]: +; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds nuw i8, ptr [[PTR_IV]], i64 2 +; CHECK-NEXT: [[CMP_NOT_I_I:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[COERCE_VAL_IP]] +; CHECK-NEXT: br i1 [[CMP_NOT_I_I]], label %[[RETURN_LOOPEXIT]], label %[[LOOP_HEADER]] +; CHECK: [[RETURN_LOOPEXIT]]: +; CHECK-NEXT: [[MERGE_PH:%.*]] = phi ptr [ [[COERCE_VAL_IP]], %[[LOOP_LATCH]] ], [ [[PTR_IV]], %[[LOOP_HEADER]] ] +; CHECK-NEXT: [[DOTPRE:%.*]] = ptrtoint ptr [[MERGE_PH]] to i64 +; CHECK-NEXT: br label %[[RETURN]] +; CHECK: [[RETURN]]: +; CHECK-NEXT: [[RES_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE]], %[[RETURN_LOOPEXIT]] ], [ [[TMP0]], %[[ENTRY]] ] +; CHECK-NEXT: ret i64 [[RES_PRE_PHI]] +; +entry: + %first = alloca { ptr }, align 8 + %s.addr = alloca i16, align 2 + store ptr %first.coerce, ptr %first, align 8 + store i16 %s, ptr %s.addr, align 2 + %0 = load ptr, ptr %first, align 8 + %start.ptr = load ptr, ptr %first, align 8 + %1 = load i64, ptr %first, align 8 + %coerce.val.pi.i = add i64 %1, 256 + %coerce.val.ip = inttoptr i64 %coerce.val.pi.i to ptr + %cmp.not6.i.i = icmp eq ptr %start.ptr, %coerce.val.ip + br i1 %cmp.not6.i.i, label %return, label %loop.ph + +loop.ph: + %2 = load i16, ptr %s.addr, align 2 + br label %loop.header + +loop.header: + %ptr.iv = phi ptr [ %start.ptr, %loop.ph ], [ %ptr.iv.next, %loop.latch ] + %3 = load i16, ptr %ptr.iv, align 2 + %cmp2.i.i = icmp eq i16 %3, %2 + br i1 %cmp2.i.i, label %return, label %loop.latch + +loop.latch: + %ptr.iv.next = getelementptr inbounds nuw i8, ptr %ptr.iv, i64 2 + %cmp.not.i.i = icmp eq ptr %ptr.iv.next, %coerce.val.ip + br i1 %cmp.not.i.i, label %return, label %loop.header + +return: + %merge = phi ptr [ %start.ptr, %entry ], [ %coerce.val.ip, %loop.latch ], [ %ptr.iv, %loop.header ] + %res = ptrtoint ptr %merge to i64 + ret i64 %res +} + +declare void @llvm.assume(i1 noundef) diff --git a/llvm/test/Transforms/SLPVectorizer/X86/control-dependent-schedule.ll b/llvm/test/Transforms/SLPVectorizer/X86/control-dependent-schedule.ll new file mode 100644 index 000000000000..8602c256ad8c --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/control-dependent-schedule.ll @@ -0,0 +1,56 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +define i32 @test(i32 %0, i32 %1) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[K:%.*]] = alloca [4 x i32], align 16 +; CHECK-NEXT: [[ADD1:%.*]] = add i32 [[TMP0]], [[TMP1]] +; CHECK-NEXT: [[SUB2:%.*]] = add i32 [[ADD1]], -1 +; CHECK-NEXT: [[CALL:%.*]] = tail call i32 (ptr, ...) @printf(ptr null, i32 [[ADD1]]) +; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[TMP1]], -1 +; CHECK-NEXT: [[SUB3:%.*]] = add i32 [[ADD2]], [[CALL]] +; CHECK-NEXT: [[ADD4:%.*]] = add i32 [[SUB3]], [[TMP0]] +; CHECK-NEXT: store i32 [[ADD4]], ptr [[K]], align 16 +; CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr i8, ptr [[K]], i64 4 +; CHECK-NEXT: store i32 0, ptr [[ARRAYINIT_ELEMENT]], align 4 +; CHECK-NEXT: [[ARRAYINIT_ELEMENT5:%.*]] = getelementptr i8, ptr [[K]], i64 8 +; CHECK-NEXT: [[ADD7:%.*]] = add i32 [[ADD2]], [[SUB2]] +; CHECK-NEXT: [[SUB8:%.*]] = add i32 [[ADD7]], [[TMP0]] +; CHECK-NEXT: store i32 [[SUB8]], ptr [[ARRAYINIT_ELEMENT5]], align 8 +; CHECK-NEXT: [[ARRAYINIT_ELEMENT9:%.*]] = getelementptr i8, ptr [[K]], i64 12 +; CHECK-NEXT: [[ADD13:%.*]] = add i32 [[TMP1]], 1 +; CHECK-NEXT: [[ADD10:%.*]] = add i32 [[ADD13]], [[TMP0]] +; CHECK-NEXT: [[ADD11:%.*]] = add i32 [[ADD10]], [[ADD1]] +; CHECK-NEXT: [[ADD12:%.*]] = add i32 [[ADD11]], [[TMP0]] +; CHECK-NEXT: store i32 [[ADD12]], ptr [[ARRAYINIT_ELEMENT9]], align 4 +; CHECK-NEXT: [[CALL15:%.*]] = call i32 (ptr, ...) @printf(ptr null, ptr [[K]]) +; CHECK-NEXT: ret i32 [[CALL15]] +; +entry: + %k = alloca [4 x i32], align 16 + %add1 = add i32 %0, %1 + %sub2 = add i32 %add1, -1 + %call = tail call i32 (ptr, ...) @printf(ptr null, i32 %add1) + %add2 = add i32 %1, -1 + %sub3 = add i32 %add2, %call + %add4 = add i32 %sub3, %0 + store i32 %add4, ptr %k, align 16 + %arrayinit.element = getelementptr i8, ptr %k, i64 4 + store i32 0, ptr %arrayinit.element, align 4 + %arrayinit.element5 = getelementptr i8, ptr %k, i64 8 + %add7 = add i32 %add2, %sub2 + %sub8 = add i32 %add7, %0 + store i32 %sub8, ptr %arrayinit.element5, align 8 + %arrayinit.element9 = getelementptr i8, ptr %k, i64 12 + %add13 = add i32 %1, 1 + %add10 = add i32 %add13, %0 + %add11 = add i32 %add10, %add1 + %add12 = add i32 %add11, %0 + store i32 %add12, ptr %arrayinit.element9, align 4 + %call15 = call i32 (ptr, ...) @printf(ptr null, ptr %k) + ret i32 %call15 +} + +declare i32 @printf(ptr, ...) diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll new file mode 100644 index 000000000000..056f33e5ee36 --- /dev/null +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll @@ -0,0 +1,435 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; Test the xor with constant operand is decomposed in to gep. +; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep \ +; RUN: -S < %s | FileCheck %s +; Test the gvn pass eliminates the redundant xor instructions from decomposition. +; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep,gvn \ +; RUN: -S < %s | FileCheck --check-prefix=GVN %s + +; Check that disjoint constants are properly extracted and folded into GEP +; addressing modes and GVN to eliminate redundant computations +define amdgpu_kernel void @test1(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test1( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 8192 +; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 16384 +; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP11]] +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP12]], i32 24576 +; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 +; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 16 +; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 16 +; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]] +; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]] +; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test1( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192 +; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 16384 +; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 24576 +; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 +; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] +; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]] +; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]] +; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 32 + %4 = xor i32 %2, 4128 + %5 = xor i32 %2, 8224 + %6 = xor i32 %2, 12320 + %7 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %8 = getelementptr half, ptr addrspace(3) %1, i32 %4 + %9 = getelementptr half, ptr addrspace(3) %1, i32 %5 + %10 = getelementptr half, ptr addrspace(3) %1, i32 %6 + %11 = load <8 x half>, ptr addrspace(3) %7, align 16 + %12 = load <8 x half>, ptr addrspace(3) %8, align 16 + %13 = load <8 x half>, ptr addrspace(3) %9, align 16 + %14 = load <8 x half>, ptr addrspace(3) %10, align 16 + %15 = fadd <8 x half> %11, %12 + %16 = fadd <8 x half> %13, %14 + %17 = fadd <8 x half> %15, %16 + store <8 x half> %17, ptr addrspace(3) %1, align 16 + ret void +} + +; Check that disjoint constants are properly extracted and folded into GEP +; addressing modes and GVN to eliminate redundant computations +define amdgpu_kernel void @test2(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test2( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP5]], i32 24576 +; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP8]], i32 16384 +; CHECK-NEXT: [[TMP10:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP10]] +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP11]], i32 8192 +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP9]], align 16 +; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP12]], align 16 +; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 16 +; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]] +; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]] +; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test2( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 24576 +; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 16384 +; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192 +; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 +; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] +; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]] +; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]] +; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 12320 + %4 = xor i32 %2, 8224 + %5 = xor i32 %2, 4128 + %6 = xor i32 %2, 32 + %7 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %8 = getelementptr half, ptr addrspace(3) %1, i32 %4 + %9 = getelementptr half, ptr addrspace(3) %1, i32 %5 + %10 = getelementptr half, ptr addrspace(3) %1, i32 %6 + %11 = load <8 x half>, ptr addrspace(3) %7, align 16 + %12 = load <8 x half>, ptr addrspace(3) %8, align 16 + %13 = load <8 x half>, ptr addrspace(3) %9, align 16 + %14 = load <8 x half>, ptr addrspace(3) %10, align 16 + %15 = fadd <8 x half> %11, %12 + %16 = fadd <8 x half> %13, %14 + %17 = fadd <8 x half> %15, %16 + store <8 x half> %17, ptr addrspace(3) %1, align 16 + ret void +} + +; Verify that xor instructions with different non-disjoint constants are optimized +define amdgpu_kernel void @test3(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test3( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096 +; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 8192 +; CHECK-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 +; CHECK-NEXT: [[TMP12:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; CHECK-NEXT: [[TMP13:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 16 +; CHECK-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]] +; CHECK-NEXT: [[TMP15:%.*]] = fadd <8 x half> [[TMP13]], [[TMP14]] +; CHECK-NEXT: store <8 x half> [[TMP15]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test3( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288 +; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] +; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096 +; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192 +; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 +; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 +; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] +; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]] +; GVN-NEXT: store <8 x half> [[TMP13]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 32 + %4 = xor i32 %2, 2336 + %5 = xor i32 %2, 4128 + %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %7 = getelementptr half, ptr addrspace(3) %1, i32 %4 + %8 = getelementptr half, ptr addrspace(3) %1, i32 %5 + %9 = load <8 x half>, ptr addrspace(3) %6, align 16 + %10 = load <8 x half>, ptr addrspace(3) %7, align 16 + %11 = load <8 x half>, ptr addrspace(3) %8, align 16 + %12 = fadd <8 x half> %9, %10 + %13 = fadd <8 x half> %11, %12 + store <8 x half> %13, ptr addrspace(3) %1, align 16 + ret void +} + +; Verify that no optimization occurs when disjoint constants are absent +define amdgpu_kernel void @test4(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test4( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] +; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test4( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288 +; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] +; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] +; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 32 + %4 = xor i32 %2, 288 + %5 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %6 = getelementptr half, ptr addrspace(3) %1, i32 %4 + %7 = load <8 x half>, ptr addrspace(3) %5, align 16 + %8 = load <8 x half>, ptr addrspace(3) %6, align 16 + %9 = fadd <8 x half> %7, %8 + store <8 x half> %9, ptr addrspace(3) %1, align 16 + ret void +} + + +; Verify that XOR-BinOp-GEP usage chains are properly optimized +define amdgpu_kernel void @test5(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test5( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 256 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192 +; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 +; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 +; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] +; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test5( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], 256 +; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] +; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 8192 +; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 +; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] +; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 32 + %4 = xor i32 %2, 4128 + %5 = add i32 %4, 256 + %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %7 = getelementptr half, ptr addrspace(3) %1, i32 %5 + %8 = load <8 x half>, ptr addrspace(3) %6, align 16 + %9 = load <8 x half>, ptr addrspace(3) %7, align 16 + %10 = fadd <8 x half> %8, %9 + store <8 x half> %10, ptr addrspace(3) %1, align 16 + ret void +} + +; Verify that BinOp-XOR-GEP usage chains are properly optimized. +; In the below test, make sure we stop processing the chain at xor +; and not fold the constant from add instruction in to gep. The +; constant from add can be folded and the future work will cover +; these cases. +define amdgpu_kernel void @test6(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test6( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192 +; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 +; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] +; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test6( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 +; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32 +; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]] +; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192 +; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 +; GVN-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] +; GVN-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 32 + %4 = add i32 %2, 256 + %5 = xor i32 %4, 4128 + %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %7 = getelementptr half, ptr addrspace(3) %1, i32 %5 + %8 = load <8 x half>, ptr addrspace(3) %6, align 16 + %9 = load <8 x half>, ptr addrspace(3) %7, align 16 + %10 = fadd <8 x half> %8, %9 + store <8 x half> %10, ptr addrspace(3) %1, align 16 + ret void +} + +; Verify that BinOp-XOR-GEP usage chains with non disjoint xor works as +; intended. +define amdgpu_kernel void @test6a(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test6a( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 +; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] +; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; CHECK-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] +; CHECK-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test6a( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 +; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288 +; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] +; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 +; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] +; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 32 + %4 = add i32 %2, 256 + %5 = xor i32 %4, 288 + %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %7 = getelementptr half, ptr addrspace(3) %1, i32 %5 + %8 = load <8 x half>, ptr addrspace(3) %6, align 16 + %9 = load <8 x half>, ptr addrspace(3) %7, align 16 + %10 = fadd <8 x half> %8, %9 + store <8 x half> %10, ptr addrspace(3) %1, align 16 + ret void +} + +; Ensure disjoint constants exceeding addressing mode limits (e.g., 32768) are +; not extracted +define amdgpu_kernel void @test7(i1 %0, ptr addrspace(3) %1) { +; CHECK-LABEL: define amdgpu_kernel void @test7( +; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] +; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 +; CHECK-NEXT: ret void +; +; GVN-LABEL: define amdgpu_kernel void @test7( +; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { +; GVN-NEXT: [[ENTRY:.*:]] +; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 +; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 +; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800 +; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] +; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] +; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 +; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 +; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] +; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 +; GVN-NEXT: ret void +; +entry: + %2 = select i1 %0, i32 0, i32 288 + %3 = xor i32 %2, 32 + %4 = xor i32 %2, 32800 + %5 = getelementptr half, ptr addrspace(3) %1, i32 %3 + %6 = getelementptr half, ptr addrspace(3) %1, i32 %4 + %7 = load <8 x half>, ptr addrspace(3) %5, align 16 + %8 = load <8 x half>, ptr addrspace(3) %6, align 16 + %9 = fadd <8 x half> %7, %8 + store <8 x half> %9, ptr addrspace(3) %1, align 16 + ret void +} + |