diff options
Diffstat (limited to 'llvm/test/Transforms/InstCombine/icmp.ll')
| -rw-r--r-- | llvm/test/Transforms/InstCombine/icmp.ll | 2542 |
1 files changed, 1501 insertions, 1041 deletions
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll index a090f9c4d261..0faa7da482ef 100644 --- a/llvm/test/Transforms/InstCombine/icmp.ll +++ b/llvm/test/Transforms/InstCombine/icmp.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-p1:16:16:16-p2:32:32:32-p3:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" @@ -11,8 +11,9 @@ declare void @use_i32(i32) declare void @use_i64(i64) define i32 @test1(i32 %X) { -; CHECK-LABEL: @test1( -; CHECK-NEXT: [[X_LOBIT:%.*]] = lshr i32 [[X:%.*]], 31 +; CHECK-LABEL: define i32 @test1( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[X_LOBIT:%.*]] = lshr i32 [[X]], 31 ; CHECK-NEXT: ret i32 [[X_LOBIT]] ; %a = icmp slt i32 %X, 0 @@ -21,8 +22,9 @@ define i32 @test1(i32 %X) { } define <2 x i32> @test1vec(<2 x i32> %X) { -; CHECK-LABEL: @test1vec( -; CHECK-NEXT: [[X_LOBIT:%.*]] = lshr <2 x i32> [[X:%.*]], splat (i32 31) +; CHECK-LABEL: define <2 x i32> @test1vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[X_LOBIT:%.*]] = lshr <2 x i32> [[X]], splat (i32 31) ; CHECK-NEXT: ret <2 x i32> [[X_LOBIT]] ; %a = icmp slt <2 x i32> %X, zeroinitializer @@ -31,8 +33,9 @@ define <2 x i32> @test1vec(<2 x i32> %X) { } define i32 @test2(i32 %X) { -; CHECK-LABEL: @test2( -; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1 +; CHECK-LABEL: define i32 @test2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X]], -1 ; CHECK-NEXT: [[B:%.*]] = zext i1 [[A]] to i32 ; CHECK-NEXT: ret i32 [[B]] ; @@ -42,8 +45,9 @@ define i32 @test2(i32 %X) { } define <2 x i32> @test2vec(<2 x i32> %X) { -; CHECK-LABEL: @test2vec( -; CHECK-NEXT: [[A:%.*]] = icmp sgt <2 x i32> [[X:%.*]], splat (i32 -1) +; CHECK-LABEL: define <2 x i32> @test2vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = icmp sgt <2 x i32> [[X]], splat (i32 -1) ; CHECK-NEXT: [[B:%.*]] = zext <2 x i1> [[A]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[B]] ; @@ -53,8 +57,9 @@ define <2 x i32> @test2vec(<2 x i32> %X) { } define i32 @test3(i32 %X) { -; CHECK-LABEL: @test3( -; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X:%.*]], 31 +; CHECK-LABEL: define i32 @test3( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X]], 31 ; CHECK-NEXT: ret i32 [[X_LOBIT]] ; %a = icmp slt i32 %X, 0 @@ -63,8 +68,9 @@ define i32 @test3(i32 %X) { } define i32 @test4(i32 %X) { -; CHECK-LABEL: @test4( -; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1 +; CHECK-LABEL: define i32 @test4( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X]], -1 ; CHECK-NEXT: [[B:%.*]] = sext i1 [[A]] to i32 ; CHECK-NEXT: ret i32 [[B]] ; @@ -75,28 +81,31 @@ define i32 @test4(i32 %X) { ; PR4837 define <2 x i1> @test5_eq(<2 x i64> %x) { -; CHECK-LABEL: @test5_eq( +; CHECK-LABEL: define <2 x i1> @test5_eq( +; CHECK-SAME: <2 x i64> [[X:%.*]]) { ; CHECK-NEXT: ret <2 x i1> undef ; %V = icmp eq <2 x i64> %x, undef ret <2 x i1> %V } define <2 x i1> @test5_ne(<2 x i64> %x) { -; CHECK-LABEL: @test5_ne( +; CHECK-LABEL: define <2 x i1> @test5_ne( +; CHECK-SAME: <2 x i64> [[X:%.*]]) { ; CHECK-NEXT: ret <2 x i1> undef ; %V = icmp ne <2 x i64> %x, undef ret <2 x i1> %V } define <2 x i1> @test5_ugt(<2 x i64> %x) { -; CHECK-LABEL: @test5_ugt( +; CHECK-LABEL: define <2 x i1> @test5_ugt( +; CHECK-SAME: <2 x i64> [[X:%.*]]) { ; CHECK-NEXT: ret <2 x i1> zeroinitializer ; %V = icmp ugt <2 x i64> %x, undef ret <2 x i1> %V } define <2 x i1> @test5_zero() { -; CHECK-LABEL: @test5_zero( +; CHECK-LABEL: define <2 x i1> @test5_zero() { ; CHECK-NEXT: ret <2 x i1> undef ; %V = icmp eq <2 x i64> zeroinitializer, undef @@ -104,9 +113,10 @@ define <2 x i1> @test5_zero() { } define i32 @test6(i32 %a, i32 %b) { -; CHECK-LABEL: @test6( -; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i32 [[A:%.*]], 0 -; CHECK-NEXT: [[F:%.*]] = select i1 [[ISNEG]], i32 [[B:%.*]], i32 0 +; CHECK-LABEL: define i32 @test6( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i32 [[A]], 0 +; CHECK-NEXT: [[F:%.*]] = select i1 [[ISNEG]], i32 [[B]], i32 0 ; CHECK-NEXT: ret i32 [[F]] ; %c = icmp sle i32 %a, -1 @@ -118,8 +128,9 @@ define i32 @test6(i32 %a, i32 %b) { define i1 @test7(i32 %x) { -; CHECK-LABEL: @test7( -; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @test7( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: ret i1 [[B]] ; %a = add i32 %x, -1 @@ -128,8 +139,9 @@ define i1 @test7(i32 %x) { } define <2 x i1> @test7_vec(<2 x i32> %x) { -; CHECK-LABEL: @test7_vec( -; CHECK-NEXT: [[B:%.*]] = icmp ne <2 x i32> [[X:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @test7_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ne <2 x i32> [[X]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[B]] ; %a = add <2 x i32> %x, <i32 -1, i32 -1> @@ -138,7 +150,8 @@ define <2 x i1> @test7_vec(<2 x i32> %x) { } define i1 @test8(i32 %x) { -; CHECK-LABEL: @test8( +; CHECK-LABEL: define i1 @test8( +; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: ret i1 false ; %a = add i32 %x, -1 @@ -147,7 +160,8 @@ define i1 @test8(i32 %x) { } define <2 x i1> @test8_vec(<2 x i32> %x) { -; CHECK-LABEL: @test8_vec( +; CHECK-LABEL: define <2 x i1> @test8_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { ; CHECK-NEXT: ret <2 x i1> zeroinitializer ; %a = add <2 x i32> %x, <i32 -1, i32 -1> @@ -156,8 +170,9 @@ define <2 x i1> @test8_vec(<2 x i32> %x) { } define i1 @test9(i32 %x) { -; CHECK-LABEL: @test9( -; CHECK-NEXT: [[B:%.*]] = icmp ugt i32 [[X:%.*]], 1 +; CHECK-LABEL: define i1 @test9( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ugt i32 [[X]], 1 ; CHECK-NEXT: ret i1 [[B]] ; %a = add i32 %x, -2 @@ -166,8 +181,9 @@ define i1 @test9(i32 %x) { } define <2 x i1> @test9_vec(<2 x i32> %x) { -; CHECK-LABEL: @test9_vec( -; CHECK-NEXT: [[B:%.*]] = icmp ugt <2 x i32> [[X:%.*]], splat (i32 1) +; CHECK-LABEL: define <2 x i1> @test9_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ugt <2 x i32> [[X]], splat (i32 1) ; CHECK-NEXT: ret <2 x i1> [[B]] ; %a = add <2 x i32> %x, <i32 -2, i32 -2> @@ -176,8 +192,9 @@ define <2 x i1> @test9_vec(<2 x i32> %x) { } define i1 @test9b(i32 %x) { -; CHECK-LABEL: @test9b( -; CHECK-NEXT: [[B:%.*]] = icmp ult i32 [[X:%.*]], 2 +; CHECK-LABEL: define i1 @test9b( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ult i32 [[X]], 2 ; CHECK-NEXT: ret i1 [[B]] ; %a = add i32 %x, -2 @@ -186,8 +203,9 @@ define i1 @test9b(i32 %x) { } define <2 x i1> @test9b_vec(<2 x i32> %x) { -; CHECK-LABEL: @test9b_vec( -; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 2) +; CHECK-LABEL: define <2 x i1> @test9b_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[X]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[B]] ; %a = add <2 x i32> %x, <i32 -2, i32 -2> @@ -196,8 +214,9 @@ define <2 x i1> @test9b_vec(<2 x i32> %x) { } define i1 @test10(i32 %x) { -; CHECK-LABEL: @test10( -; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[X:%.*]], -2147483648 +; CHECK-LABEL: define i1 @test10( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ne i32 [[X]], -2147483648 ; CHECK-NEXT: ret i1 [[B]] ; %a = add i32 %x, -1 @@ -206,8 +225,9 @@ define i1 @test10(i32 %x) { } define <2 x i1> @test10_vec(<2 x i32> %x) { -; CHECK-LABEL: @test10_vec( -; CHECK-NEXT: [[B:%.*]] = icmp ne <2 x i32> [[X:%.*]], splat (i32 -2147483648) +; CHECK-LABEL: define <2 x i1> @test10_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ne <2 x i32> [[X]], splat (i32 -2147483648) ; CHECK-NEXT: ret <2 x i1> [[B]] ; %a = add <2 x i32> %x, <i32 -1, i32 -1> @@ -216,8 +236,9 @@ define <2 x i1> @test10_vec(<2 x i32> %x) { } define i1 @test10b(i32 %x) { -; CHECK-LABEL: @test10b( -; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[X:%.*]], -2147483648 +; CHECK-LABEL: define i1 @test10b( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[X]], -2147483648 ; CHECK-NEXT: ret i1 [[B]] ; %a = add i32 %x, -1 @@ -226,8 +247,9 @@ define i1 @test10b(i32 %x) { } define <2 x i1> @test10b_vec(<2 x i32> %x) { -; CHECK-LABEL: @test10b_vec( -; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i32> [[X:%.*]], splat (i32 -2147483648) +; CHECK-LABEL: define <2 x i1> @test10b_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp eq <2 x i32> [[X]], splat (i32 -2147483648) ; CHECK-NEXT: ret <2 x i1> [[B]] ; %a = add <2 x i32> %x, <i32 -1, i32 -1> @@ -236,7 +258,8 @@ define <2 x i1> @test10b_vec(<2 x i32> %x) { } define i1 @test11(i32 %x) { -; CHECK-LABEL: @test11( +; CHECK-LABEL: define i1 @test11( +; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: ret i1 true ; %a = add nsw i32 %x, 8 @@ -245,7 +268,8 @@ define i1 @test11(i32 %x) { } define <2 x i1> @test11_vec(<2 x i32> %x) { -; CHECK-LABEL: @test11_vec( +; CHECK-LABEL: define <2 x i1> @test11_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { ; CHECK-NEXT: ret <2 x i1> splat (i1 true) ; %a = add nsw <2 x i32> %x, <i32 8, i32 8> @@ -255,8 +279,9 @@ define <2 x i1> @test11_vec(<2 x i32> %x) { ; PR6195 define i1 @test12(i1 %A) { -; CHECK-LABEL: @test12( -; CHECK-NEXT: [[NOT_A:%.*]] = xor i1 [[A:%.*]], true +; CHECK-LABEL: define i1 @test12( +; CHECK-SAME: i1 [[A:%.*]]) { +; CHECK-NEXT: [[NOT_A:%.*]] = xor i1 [[A]], true ; CHECK-NEXT: ret i1 [[NOT_A]] ; %S = select i1 %A, i64 -4294967295, i64 8589934591 @@ -266,7 +291,8 @@ define i1 @test12(i1 %A) { ; PR6481 define i1 @test13(i8 %X) { -; CHECK-LABEL: @test13( +; CHECK-LABEL: define i1 @test13( +; CHECK-SAME: i8 [[X:%.*]]) { ; CHECK-NEXT: ret i1 false ; %cmp = icmp slt i8 undef, %X @@ -274,7 +300,8 @@ define i1 @test13(i8 %X) { } define i1 @test14(i8 %X) { -; CHECK-LABEL: @test14( +; CHECK-LABEL: define i1 @test14( +; CHECK-SAME: i8 [[X:%.*]]) { ; CHECK-NEXT: ret i1 false ; %cmp = icmp slt i8 undef, -128 @@ -282,7 +309,7 @@ define i1 @test14(i8 %X) { } define i1 @test15() { -; CHECK-LABEL: @test15( +; CHECK-LABEL: define i1 @test15() { ; CHECK-NEXT: ret i1 undef ; %cmp = icmp eq i8 undef, -128 @@ -290,7 +317,7 @@ define i1 @test15() { } define i1 @test16() { -; CHECK-LABEL: @test16( +; CHECK-LABEL: define i1 @test16() { ; CHECK-NEXT: ret i1 undef ; %cmp = icmp ne i8 undef, -128 @@ -298,8 +325,9 @@ define i1 @test16() { } define i1 @test17(i32 %x) { -; CHECK-LABEL: @test17( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test17( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], 3 ; CHECK-NEXT: ret i1 [[TMP1]] ; %shl = shl i32 1, %x @@ -309,8 +337,9 @@ define i1 @test17(i32 %x) { } define <2 x i1> @test17vec(<2 x i32> %x) { -; CHECK-LABEL: @test17vec( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32> [[X:%.*]], splat (i32 3) +; CHECK-LABEL: define <2 x i1> @test17vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: ret <2 x i1> [[TMP1]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %x @@ -320,8 +349,9 @@ define <2 x i1> @test17vec(<2 x i32> %x) { } define i1 @test17a(i32 %x) { -; CHECK-LABEL: @test17a( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], 2 +; CHECK-LABEL: define i1 @test17a( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %x @@ -331,8 +361,9 @@ define i1 @test17a(i32 %x) { } define <2 x i1> @test17a_vec(<2 x i32> %x) { -; CHECK-LABEL: @test17a_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X:%.*]], splat (i32 2) +; CHECK-LABEL: define <2 x i1> @test17a_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %x @@ -342,8 +373,9 @@ define <2 x i1> @test17a_vec(<2 x i32> %x) { } define i1 @test18_eq(i32 %x) { -; CHECK-LABEL: @test18_eq( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test18_eq( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], 3 ; CHECK-NEXT: ret i1 [[TMP1]] ; %sh = lshr i32 8, %x @@ -353,8 +385,9 @@ define i1 @test18_eq(i32 %x) { } define <2 x i1> @test18_eq_vec(<2 x i32> %x) { -; CHECK-LABEL: @test18_eq_vec( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32> [[X:%.*]], splat (i32 3) +; CHECK-LABEL: define <2 x i1> @test18_eq_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: ret <2 x i1> [[TMP1]] ; %sh = lshr <2 x i32> <i32 8, i32 8>, %x @@ -364,8 +397,9 @@ define <2 x i1> @test18_eq_vec(<2 x i32> %x) { } define i1 @test18_ne(i32 %x) { -; CHECK-LABEL: @test18_ne( -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test18_ne( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X]], 3 ; CHECK-NEXT: ret i1 [[TMP1]] ; %sh = lshr i32 8, %x @@ -375,8 +409,9 @@ define i1 @test18_ne(i32 %x) { } define <2 x i1> @test18_ne_vec(<2 x i32> %x) { -; CHECK-LABEL: @test18_ne_vec( -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], splat (i32 3) +; CHECK-LABEL: define <2 x i1> @test18_ne_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: ret <2 x i1> [[TMP1]] ; %sh = lshr <2 x i32> <i32 8, i32 8>, %x @@ -386,8 +421,9 @@ define <2 x i1> @test18_ne_vec(<2 x i32> %x) { } define i1 @test19(i32 %x) { -; CHECK-LABEL: @test19( -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test19( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X]], 3 ; CHECK-NEXT: ret i1 [[TMP1]] ; %shl = shl i32 1, %x @@ -397,8 +433,9 @@ define i1 @test19(i32 %x) { } define <2 x i1> @test19vec(<2 x i32> %x) { -; CHECK-LABEL: @test19vec( -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], splat (i32 3) +; CHECK-LABEL: define <2 x i1> @test19vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: ret <2 x i1> [[TMP1]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %x @@ -408,8 +445,9 @@ define <2 x i1> @test19vec(<2 x i32> %x) { } define <2 x i1> @cmp_and_signbit_vec(<2 x i3> %x) { -; CHECK-LABEL: @cmp_and_signbit_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i3> [[X:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @cmp_and_signbit_vec( +; CHECK-SAME: <2 x i3> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i3> [[X]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %and = and <2 x i3> %x, <i3 4, i3 4> @@ -418,8 +456,9 @@ define <2 x i1> @cmp_and_signbit_vec(<2 x i3> %x) { } define i1 @test20(i32 %x) { -; CHECK-LABEL: @test20( -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test20( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X]], 3 ; CHECK-NEXT: ret i1 [[TMP1]] ; %shl = shl i32 1, %x @@ -429,8 +468,9 @@ define i1 @test20(i32 %x) { } define <2 x i1> @test20vec(<2 x i32> %x) { -; CHECK-LABEL: @test20vec( -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X:%.*]], splat (i32 3) +; CHECK-LABEL: define <2 x i1> @test20vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: ret <2 x i1> [[TMP1]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %x @@ -440,8 +480,9 @@ define <2 x i1> @test20vec(<2 x i32> %x) { } define i1 @test20a(i32 %x) { -; CHECK-LABEL: @test20a( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test20a( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X]], 3 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %x @@ -451,8 +492,9 @@ define i1 @test20a(i32 %x) { } define <2 x i1> @test20a_vec(<2 x i32> %x) { -; CHECK-LABEL: @test20a_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 3) +; CHECK-LABEL: define <2 x i1> @test20a_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %x @@ -462,8 +504,9 @@ define <2 x i1> @test20a_vec(<2 x i32> %x) { } define i1 @test21(i8 %x, i8 %y) { -; CHECK-LABEL: @test21( -; CHECK-NEXT: [[B:%.*]] = icmp ugt i8 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test21( +; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ugt i8 [[X]], 3 ; CHECK-NEXT: ret i1 [[B]] ; %A = or i8 %x, 1 @@ -472,8 +515,9 @@ define i1 @test21(i8 %x, i8 %y) { } define i1 @test22(i8 %x, i8 %y) { -; CHECK-LABEL: @test22( -; CHECK-NEXT: [[B:%.*]] = icmp ult i8 [[X:%.*]], 4 +; CHECK-LABEL: define i1 @test22( +; CHECK-SAME: i8 [[X:%.*]], i8 [[Y:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ult i8 [[X]], 4 ; CHECK-NEXT: ret i1 [[B]] ; %A = or i8 %x, 1 @@ -483,8 +527,9 @@ define i1 @test22(i8 %x, i8 %y) { ; PR2740 define i1 @test23(i32 %x) { -; CHECK-LABEL: @test23( -; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[X:%.*]], 1328634634 +; CHECK-LABEL: define i1 @test23( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[I4:%.*]] = icmp sgt i32 [[X]], 1328634634 ; CHECK-NEXT: ret i1 [[I4]] ; %i3 = sdiv i32 %x, -1328634635 @@ -493,8 +538,9 @@ define i1 @test23(i32 %x) { } define <2 x i1> @test23vec(<2 x i32> %x) { -; CHECK-LABEL: @test23vec( -; CHECK-NEXT: [[I4:%.*]] = icmp sgt <2 x i32> [[X:%.*]], splat (i32 1328634634) +; CHECK-LABEL: define <2 x i1> @test23vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[I4:%.*]] = icmp sgt <2 x i32> [[X]], splat (i32 1328634634) ; CHECK-NEXT: ret <2 x i1> [[I4]] ; %i3 = sdiv <2 x i32> %x, <i32 -1328634635, i32 -1328634635> @@ -505,8 +551,9 @@ define <2 x i1> @test23vec(<2 x i32> %x) { ; Note: offs can be negative, LLVM used to make an incorrect assumption that ; unsigned overflow does not happen during offset computation define i1 @test24_neg_offs(ptr %p, i64 %offs) { -; CHECK-LABEL: @test24_neg_offs( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[OFFS:%.*]], -2 +; CHECK-LABEL: define i1 @test24_neg_offs( +; CHECK-SAME: ptr [[P:%.*]], i64 [[OFFS:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[OFFS]], -2 ; CHECK-NEXT: ret i1 [[CMP]] ; %p1 = getelementptr inbounds i32, ptr %p, i64 %offs @@ -519,8 +566,9 @@ define i1 @test24_neg_offs(ptr %p, i64 %offs) { ; X - Z > Y - Z -> X > Y if there is no overflow. define i1 @test27(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test27( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test27( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %lhs = sub nsw i32 %x, %z @@ -530,10 +578,11 @@ define i1 @test27(i32 %x, i32 %y, i32 %z) { } define i1 @test27_extra_uses(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test27_extra_uses( -; CHECK-NEXT: [[LHS:%.*]] = sub nsw i32 [[X:%.*]], [[Z:%.*]] +; CHECK-LABEL: define i1 @test27_extra_uses( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[LHS:%.*]] = sub nsw i32 [[X]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[LHS]]) -; CHECK-NEXT: [[RHS:%.*]] = sub nsw i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[RHS:%.*]] = sub nsw i32 [[Y]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[RHS]]) ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] @@ -548,8 +597,9 @@ define i1 @test27_extra_uses(i32 %x, i32 %y, i32 %z) { ; X - Z > Y - Z -> X > Y if there is no overflow. define i1 @test28(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test28( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test28( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %lhs = sub nuw i32 %x, %z @@ -559,10 +609,11 @@ define i1 @test28(i32 %x, i32 %y, i32 %z) { } define i1 @test28_extra_uses(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test28_extra_uses( -; CHECK-NEXT: [[LHS:%.*]] = sub nuw i32 [[X:%.*]], [[Z:%.*]] +; CHECK-LABEL: define i1 @test28_extra_uses( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[LHS:%.*]] = sub nuw i32 [[X]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[LHS]]) -; CHECK-NEXT: [[RHS:%.*]] = sub nuw i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[RHS:%.*]] = sub nuw i32 [[Y]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[RHS]]) ; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] @@ -578,9 +629,10 @@ define i1 @test28_extra_uses(i32 %x, i32 %y, i32 %z) { ; PR36969 - https://bugs.llvm.org/show_bug.cgi?id=36969 define i1 @ugt_sub(i32 %xsrc, i32 %y) { -; CHECK-LABEL: @ugt_sub( -; CHECK-NEXT: [[X:%.*]] = udiv i32 [[XSRC:%.*]], 42 -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[Y:%.*]], [[X]] +; CHECK-LABEL: define i1 @ugt_sub( +; CHECK-SAME: i32 [[XSRC:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = udiv i32 [[XSRC]], 42 +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[Y]], [[X]] ; CHECK-NEXT: ret i1 [[CMP]] ; %x = udiv i32 %xsrc, 42 ; thwart complexity-based canonicalization @@ -592,9 +644,10 @@ define i1 @ugt_sub(i32 %xsrc, i32 %y) { ; Swap operands and predicate. Try a vector type to verify that works too. define <2 x i1> @ult_sub(<2 x i8> %xsrc, <2 x i8> %y) { -; CHECK-LABEL: @ult_sub( -; CHECK-NEXT: [[X:%.*]] = udiv <2 x i8> [[XSRC:%.*]], <i8 42, i8 -42> -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X]], [[Y:%.*]] +; CHECK-LABEL: define <2 x i1> @ult_sub( +; CHECK-SAME: <2 x i8> [[XSRC:%.*]], <2 x i8> [[Y:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = udiv <2 x i8> [[XSRC]], <i8 42, i8 -42> +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[X]], [[Y]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %x = udiv <2 x i8> %xsrc, <i8 42, i8 -42> ; thwart complexity-based canonicalization @@ -605,8 +658,9 @@ define <2 x i1> @ult_sub(<2 x i8> %xsrc, <2 x i8> %y) { ; X - Y > X -> 0 > Y if there is no overflow. define i1 @test33(i32 %x, i32 %y) { -; CHECK-LABEL: @test33( -; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[Y:%.*]], 0 +; CHECK-LABEL: define i1 @test33( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[Y]], 0 ; CHECK-NEXT: ret i1 [[C]] ; %lhs = sub nsw i32 %x, %y @@ -616,7 +670,8 @@ define i1 @test33(i32 %x, i32 %y) { ; X - Y > X -> 0 > Y if there is no overflow. define i1 @test34(i32 %x, i32 %y) { -; CHECK-LABEL: @test34( +; CHECK-LABEL: define i1 @test34( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: ret i1 false ; %lhs = sub nuw i32 %x, %y @@ -626,8 +681,9 @@ define i1 @test34(i32 %x, i32 %y) { ; X > X - Y -> Y > 0 if there is no overflow. define i1 @test35(i32 %x, i32 %y) { -; CHECK-LABEL: @test35( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[Y:%.*]], 0 +; CHECK-LABEL: define i1 @test35( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[Y]], 0 ; CHECK-NEXT: ret i1 [[C]] ; %rhs = sub nsw i32 %x, %y @@ -637,8 +693,9 @@ define i1 @test35(i32 %x, i32 %y) { ; X > X - Y -> Y > 0 if there is no overflow. define i1 @test36(i32 %x, i32 %y) { -; CHECK-LABEL: @test36( -; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[Y:%.*]], 0 +; CHECK-LABEL: define i1 @test36( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[Y]], 0 ; CHECK-NEXT: ret i1 [[C]] ; %rhs = sub nuw i32 %x, %y @@ -648,8 +705,9 @@ define i1 @test36(i32 %x, i32 %y) { ; X - Y > X - Z -> Z > Y if there is no overflow. define i1 @test37(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test37( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test37( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[Z]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %lhs = sub nsw i32 %x, %y @@ -659,10 +717,11 @@ define i1 @test37(i32 %x, i32 %y, i32 %z) { } define i1 @test37_extra_uses(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test37_extra_uses( -; CHECK-NEXT: [[LHS:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test37_extra_uses( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[LHS:%.*]] = sub nsw i32 [[X]], [[Y]] ; CHECK-NEXT: call void @use_i32(i32 [[LHS]]) -; CHECK-NEXT: [[RHS:%.*]] = sub nsw i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[RHS:%.*]] = sub nsw i32 [[X]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[RHS]]) ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[Z]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] @@ -678,8 +737,9 @@ define i1 @test37_extra_uses(i32 %x, i32 %y, i32 %z) { ; TODO: Min/max pattern should not prevent the fold. define i32 @neg_max_s32(i32 %x, i32 %y) { -; CHECK-LABEL: @neg_max_s32( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 [[Y:%.*]]) +; CHECK-LABEL: define i32 @neg_max_s32( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X]], i32 [[Y]]) ; CHECK-NEXT: ret i32 [[TMP1]] ; %nx = sub nsw i32 0, %x @@ -691,8 +751,9 @@ define i32 @neg_max_s32(i32 %x, i32 %y) { } define <4 x i32> @neg_max_v4s32(<4 x i32> %x, <4 x i32> %y) { -; CHECK-LABEL: @neg_max_v4s32( -; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]) +; CHECK-LABEL: define <4 x i32> @neg_max_v4s32( +; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[X]], <4 x i32> [[Y]]) ; CHECK-NEXT: ret <4 x i32> [[TMP1]] ; %nx = sub nsw <4 x i32> zeroinitializer, %x @@ -705,8 +766,9 @@ define <4 x i32> @neg_max_v4s32(<4 x i32> %x, <4 x i32> %y) { ; X - Y > X - Z -> Z > Y if there is no overflow. define i1 @test38(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test38( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[Z:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test38( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[Z]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %lhs = sub nuw i32 %x, %y @@ -716,10 +778,11 @@ define i1 @test38(i32 %x, i32 %y, i32 %z) { } define i1 @test38_extra_uses(i32 %x, i32 %y, i32 %z) { -; CHECK-LABEL: @test38_extra_uses( -; CHECK-NEXT: [[LHS:%.*]] = sub nuw i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test38_extra_uses( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[LHS:%.*]] = sub nuw i32 [[X]], [[Y]] ; CHECK-NEXT: call void @use_i32(i32 [[LHS]]) -; CHECK-NEXT: [[RHS:%.*]] = sub nuw i32 [[X]], [[Z:%.*]] +; CHECK-NEXT: [[RHS:%.*]] = sub nuw i32 [[X]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[RHS]]) ; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[Z]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] @@ -733,8 +796,9 @@ define i1 @test38_extra_uses(i32 %x, i32 %y, i32 %z) { } define i1 @shr_exact(i132 %x) { -; CHECK-LABEL: @shr_exact( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i132 [[X:%.*]], 32 +; CHECK-LABEL: define i1 @shr_exact( +; CHECK-SAME: i132 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i132 [[X]], 32 ; CHECK-NEXT: ret i1 [[CMP]] ; %sh = ashr exact i132 %x, 4 @@ -743,8 +807,9 @@ define i1 @shr_exact(i132 %x) { } define <2 x i1> @shr_exact_vec(<2 x i132> %x) { -; CHECK-LABEL: @shr_exact_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i132> [[X:%.*]], splat (i132 32) +; CHECK-LABEL: define <2 x i1> @shr_exact_vec( +; CHECK-SAME: <2 x i132> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i132> [[X]], splat (i132 32) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %sh = lshr exact <2 x i132> %x, <i132 4, i132 4> @@ -754,7 +819,8 @@ define <2 x i1> @shr_exact_vec(<2 x i132> %x) { ; PR9343 #3 define i1 @test41(i32 %X, i32 %Y) { -; CHECK-LABEL: @test41( +; CHECK-LABEL: define i1 @test41( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: ret i1 true ; %A = urem i32 %X, %Y @@ -763,8 +829,9 @@ define i1 @test41(i32 %X, i32 %Y) { } define i1 @test42(i32 %X, i32 %Y) { -; CHECK-LABEL: @test42( -; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1 +; CHECK-LABEL: define i1 @test42( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y]], -1 ; CHECK-NEXT: ret i1 [[B]] ; %A = srem i32 %X, %Y @@ -773,8 +840,9 @@ define i1 @test42(i32 %X, i32 %Y) { } define i1 @test43(i32 %X, i32 %Y) { -; CHECK-LABEL: @test43( -; CHECK-NEXT: [[B:%.*]] = icmp slt i32 [[Y:%.*]], 0 +; CHECK-LABEL: define i1 @test43( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp slt i32 [[Y]], 0 ; CHECK-NEXT: ret i1 [[B]] ; %A = srem i32 %X, %Y @@ -783,8 +851,9 @@ define i1 @test43(i32 %X, i32 %Y) { } define i1 @test44(i32 %X, i32 %Y) { -; CHECK-LABEL: @test44( -; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1 +; CHECK-LABEL: define i1 @test44( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y]], -1 ; CHECK-NEXT: ret i1 [[B]] ; %A = srem i32 %X, %Y @@ -793,8 +862,9 @@ define i1 @test44(i32 %X, i32 %Y) { } define i1 @test45(i32 %X, i32 %Y) { -; CHECK-LABEL: @test45( -; CHECK-NEXT: [[B:%.*]] = icmp slt i32 [[Y:%.*]], 0 +; CHECK-LABEL: define i1 @test45( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp slt i32 [[Y]], 0 ; CHECK-NEXT: ret i1 [[B]] ; %A = srem i32 %X, %Y @@ -804,8 +874,9 @@ define i1 @test45(i32 %X, i32 %Y) { ; PR9343 #4 define i1 @test46(i32 %X, i32 %Y, i32 %Z) { -; CHECK-LABEL: @test46( -; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test46( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %A = ashr exact i32 %X, %Z @@ -815,10 +886,11 @@ define i1 @test46(i32 %X, i32 %Y, i32 %Z) { } define i1 @test46_multiuse1(i32 %X, i32 %Y, i32 %Z) { -; CHECK-LABEL: @test46_multiuse1( -; CHECK-NEXT: [[A:%.*]] = ashr exact i32 [[X:%.*]], [[Z:%.*]] +; CHECK-LABEL: define i1 @test46_multiuse1( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = ashr exact i32 [[X]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[A]]) -; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X]], [[Y:%.*]] +; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %A = ashr exact i32 %X, %Z @@ -829,10 +901,11 @@ define i1 @test46_multiuse1(i32 %X, i32 %Y, i32 %Z) { } define i1 @test46_multiuse2(i32 %X, i32 %Y, i32 %Z) { -; CHECK-LABEL: @test46_multiuse2( -; CHECK-NEXT: [[B:%.*]] = ashr exact i32 [[Y:%.*]], [[Z:%.*]] +; CHECK-LABEL: define i1 @test46_multiuse2( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = ashr exact i32 [[Y]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[B]]) -; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], [[Y]] +; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %A = ashr exact i32 %X, %Z @@ -843,10 +916,11 @@ define i1 @test46_multiuse2(i32 %X, i32 %Y, i32 %Z) { } define i1 @test46_multiuse3(i32 %X, i32 %Y, i32 %Z) { -; CHECK-LABEL: @test46_multiuse3( -; CHECK-NEXT: [[A:%.*]] = ashr exact i32 [[X:%.*]], [[Z:%.*]] +; CHECK-LABEL: define i1 @test46_multiuse3( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = ashr exact i32 [[X]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[A]]) -; CHECK-NEXT: [[B:%.*]] = ashr exact i32 [[Y:%.*]], [[Z]] +; CHECK-NEXT: [[B:%.*]] = ashr exact i32 [[Y]], [[Z]] ; CHECK-NEXT: call void @use_i32(i32 [[B]]) ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A]], [[B]] ; CHECK-NEXT: ret i1 [[C]] @@ -861,8 +935,9 @@ define i1 @test46_multiuse3(i32 %X, i32 %Y, i32 %Z) { ; PR9343 #5 define i1 @test47(i32 %X, i32 %Y, i32 %Z) { -; CHECK-LABEL: @test47( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test47( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %A = ashr exact i32 %X, %Z @@ -873,8 +948,9 @@ define i1 @test47(i32 %X, i32 %Y, i32 %Z) { ; PR9343 #8 define i1 @test48(i32 %X, i32 %Y, i32 %Z) { -; CHECK-LABEL: @test48( -; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test48( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %A = sdiv exact i32 %X, %Z @@ -886,9 +962,10 @@ define i1 @test48(i32 %X, i32 %Y, i32 %Z) { ; The above transform only works for equality predicates. define i1 @PR32949(i32 %X, i32 %Y, i32 %Z) { -; CHECK-LABEL: @PR32949( -; CHECK-NEXT: [[A:%.*]] = sdiv exact i32 [[X:%.*]], [[Z:%.*]] -; CHECK-NEXT: [[B:%.*]] = sdiv exact i32 [[Y:%.*]], [[Z]] +; CHECK-LABEL: define i1 @PR32949( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = sdiv exact i32 [[X]], [[Z]] +; CHECK-NEXT: [[B:%.*]] = sdiv exact i32 [[Y]], [[Z]] ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[A]], [[B]] ; CHECK-NEXT: ret i1 [[C]] ; @@ -899,8 +976,9 @@ define i1 @PR32949(i32 %X, i32 %Y, i32 %Z) { } define i1 @test_sdiv_pos_slt(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_slt( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_slt( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -910,8 +988,9 @@ define i1 @test_sdiv_pos_slt(i32 %x, i32 %y) { } define i1 @test_sdiv_pos_sle(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_sle( -; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_sle( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -921,8 +1000,9 @@ define i1 @test_sdiv_pos_sle(i32 %x, i32 %y) { } define i1 @test_sdiv_pos_sgt(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_sgt( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_sgt( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -932,8 +1012,9 @@ define i1 @test_sdiv_pos_sgt(i32 %x, i32 %y) { } define i1 @test_sdiv_pos_sge(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_sge( -; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_sge( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -943,8 +1024,9 @@ define i1 @test_sdiv_pos_sge(i32 %x, i32 %y) { } define i1 @test_sdiv_pos_ult(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_ult( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_ult( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -954,8 +1036,9 @@ define i1 @test_sdiv_pos_ult(i32 %x, i32 %y) { } define i1 @test_sdiv_pos_ule(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_ule( -; CHECK-NEXT: [[CMP:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_ule( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ule i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -965,8 +1048,9 @@ define i1 @test_sdiv_pos_ule(i32 %x, i32 %y) { } define i1 @test_sdiv_pos_ugt(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_ugt( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_ugt( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -976,8 +1060,9 @@ define i1 @test_sdiv_pos_ugt(i32 %x, i32 %y) { } define i1 @test_sdiv_pos_uge(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_pos_uge( -; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test_sdiv_pos_uge( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %divx = sdiv exact i32 %x, 40 @@ -987,9 +1072,10 @@ define i1 @test_sdiv_pos_uge(i32 %x, i32 %y) { } define i1 @test_sdiv_neg_slt(i32 %x, i32 %y) { -; CHECK-LABEL: @test_sdiv_neg_slt( -; CHECK-NEXT: [[DIVX:%.*]] = sdiv exact i32 [[X:%.*]], -40 -; CHECK-NEXT: [[DIVY:%.*]] = sdiv exact i32 [[Y:%.*]], -40 +; CHECK-LABEL: define i1 @test_sdiv_neg_slt( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[DIVX:%.*]] = sdiv exact i32 [[X]], -40 +; CHECK-NEXT: [[DIVY:%.*]] = sdiv exact i32 [[Y]], -40 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[DIVX]], [[DIVY]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1001,8 +1087,9 @@ define i1 @test_sdiv_neg_slt(i32 %x, i32 %y) { ; PR8469 define <2 x i1> @test49(<2 x i32> %i3) { -; CHECK-LABEL: @test49( -; CHECK-NEXT: entry: +; CHECK-LABEL: define <2 x i1> @test49( +; CHECK-SAME: <2 x i32> [[I3:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: ret <2 x i1> splat (i1 true) ; entry: @@ -1013,7 +1100,8 @@ entry: ; PR9343 #7 define i1 @test50(i16 %X, i32 %Y) { -; CHECK-LABEL: @test50( +; CHECK-LABEL: define i1 @test50( +; CHECK-SAME: i16 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: ret i1 true ; %A = zext i16 %X to i32 @@ -1023,9 +1111,10 @@ define i1 @test50(i16 %X, i32 %Y) { } define i1 @test51(i32 %X, i32 %Y) { -; CHECK-LABEL: @test51( -; CHECK-NEXT: [[A:%.*]] = and i32 [[X:%.*]], -2147483648 -; CHECK-NEXT: [[B:%.*]] = srem i32 [[A]], [[Y:%.*]] +; CHECK-LABEL: define i1 @test51( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = and i32 [[X]], -2147483648 +; CHECK-NEXT: [[B:%.*]] = srem i32 [[A]], [[Y]] ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[B]], -1 ; CHECK-NEXT: ret i1 [[C]] ; @@ -1036,8 +1125,9 @@ define i1 @test51(i32 %X, i32 %Y) { } define i1 @test52(i32 %x1) { -; CHECK-LABEL: @test52( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X1:%.*]], 16711935 +; CHECK-LABEL: define i1 @test52( +; CHECK-SAME: i32 [[X1:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X1]], 16711935 ; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[TMP1]], 4980863 ; CHECK-NEXT: ret i1 [[A]] ; @@ -1052,8 +1142,9 @@ define i1 @test52(i32 %x1) { } define i1 @test52_logical(i32 %x1) { -; CHECK-LABEL: @test52_logical( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X1:%.*]], 16711935 +; CHECK-LABEL: define i1 @test52_logical( +; CHECK-SAME: i32 [[X1:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X1]], 16711935 ; CHECK-NEXT: [[A:%.*]] = icmp eq i32 [[TMP1]], 4980863 ; CHECK-NEXT: ret i1 [[A]] ; @@ -1068,8 +1159,9 @@ define i1 @test52_logical(i32 %x1) { } define i1 @test52b(i128 %x1) { -; CHECK-LABEL: @test52b( -; CHECK-NEXT: [[TMP1:%.*]] = and i128 [[X1:%.*]], 16711935 +; CHECK-LABEL: define i1 @test52b( +; CHECK-SAME: i128 [[X1:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i128 [[X1]], 16711935 ; CHECK-NEXT: [[A:%.*]] = icmp eq i128 [[TMP1]], 4980863 ; CHECK-NEXT: ret i1 [[A]] ; @@ -1084,8 +1176,9 @@ define i1 @test52b(i128 %x1) { } define i1 @test52b_logical(i128 %x1) { -; CHECK-LABEL: @test52b_logical( -; CHECK-NEXT: [[TMP1:%.*]] = and i128 [[X1:%.*]], 16711935 +; CHECK-LABEL: define i1 @test52b_logical( +; CHECK-SAME: i128 [[X1:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i128 [[X1]], 16711935 ; CHECK-NEXT: [[A:%.*]] = icmp eq i128 [[TMP1]], 4980863 ; CHECK-NEXT: ret i1 [[A]] ; @@ -1101,9 +1194,10 @@ define i1 @test52b_logical(i128 %x1) { ; PR9838 define i1 @test53(i32 %a, i32 %b) { -; CHECK-LABEL: @test53( -; CHECK-NEXT: [[X:%.*]] = sdiv exact i32 [[A:%.*]], 30 -; CHECK-NEXT: [[Y:%.*]] = sdiv i32 [[B:%.*]], 30 +; CHECK-LABEL: define i1 @test53( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = sdiv exact i32 [[A]], 30 +; CHECK-NEXT: [[Y:%.*]] = sdiv i32 [[B]], 30 ; CHECK-NEXT: [[Z:%.*]] = icmp eq i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[Z]] ; @@ -1114,8 +1208,9 @@ define i1 @test53(i32 %a, i32 %b) { } define i1 @test54(i8 %a) { -; CHECK-LABEL: @test54( -; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[A:%.*]], -64 +; CHECK-LABEL: define i1 @test54( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[A]], -64 ; CHECK-NEXT: ret i1 [[RET]] ; %ext = zext i8 %a to i32 @@ -1125,8 +1220,9 @@ define i1 @test54(i8 %a) { } define i1 @test55(i32 %a) { -; CHECK-LABEL: @test55( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], -123 +; CHECK-LABEL: define i1 @test55( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], -123 ; CHECK-NEXT: ret i1 [[CMP]] ; %sub = sub i32 0, %a @@ -1135,8 +1231,9 @@ define i1 @test55(i32 %a) { } define <2 x i1> @test55vec(<2 x i32> %a) { -; CHECK-LABEL: @test55vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[A:%.*]], splat (i32 -123) +; CHECK-LABEL: define <2 x i1> @test55vec( +; CHECK-SAME: <2 x i32> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[A]], splat (i32 -123) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %sub = sub <2 x i32> zeroinitializer, %a @@ -1145,8 +1242,9 @@ define <2 x i1> @test55vec(<2 x i32> %a) { } define i1 @test56(i32 %a) { -; CHECK-LABEL: @test56( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], -113 +; CHECK-LABEL: define i1 @test56( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], -113 ; CHECK-NEXT: ret i1 [[CMP]] ; %sub = sub i32 10, %a @@ -1155,8 +1253,9 @@ define i1 @test56(i32 %a) { } define <2 x i1> @test56vec(<2 x i32> %a) { -; CHECK-LABEL: @test56vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[A:%.*]], splat (i32 -113) +; CHECK-LABEL: define <2 x i1> @test56vec( +; CHECK-SAME: <2 x i32> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[A]], splat (i32 -113) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %sub = sub <2 x i32> <i32 10, i32 10>, %a @@ -1166,8 +1265,9 @@ define <2 x i1> @test56vec(<2 x i32> %a) { ; PR10267 Don't make icmps more expensive when no other inst is subsumed. define i1 @test57(i32 %a) { -; CHECK-LABEL: @test57( -; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], -2 +; CHECK-LABEL: define i1 @test57( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: call void @use_i32(i32 [[AND]]) ; CHECK-NEXT: ret i1 [[CMP]] @@ -1180,8 +1280,9 @@ define i1 @test57(i32 %a) { ; rdar://problem/10482509 define zeroext i1 @cmpabs1(i64 %val) { -; CHECK-LABEL: @cmpabs1( -; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 [[VAL:%.*]], 0 +; CHECK-LABEL: define zeroext i1 @cmpabs1( +; CHECK-SAME: i64 [[VAL:%.*]]) { +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 [[VAL]], 0 ; CHECK-NEXT: ret i1 [[TOBOOL]] ; %sub = sub nsw i64 0, %val @@ -1192,8 +1293,9 @@ define zeroext i1 @cmpabs1(i64 %val) { } define zeroext i1 @cmpabs2(i64 %val) { -; CHECK-LABEL: @cmpabs2( -; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 [[VAL:%.*]], 0 +; CHECK-LABEL: define zeroext i1 @cmpabs2( +; CHECK-SAME: i64 [[VAL:%.*]]) { +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 [[VAL]], 0 ; CHECK-NEXT: ret i1 [[TOBOOL]] ; %sub = sub nsw i64 0, %val @@ -1204,8 +1306,9 @@ define zeroext i1 @cmpabs2(i64 %val) { } define i1 @abs_intrin_eq_zero(i8 %x) { -; CHECK-LABEL: @abs_intrin_eq_zero( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @abs_intrin_eq_zero( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %abs = call i8 @llvm.abs.i8(i8 %x, i1 false) @@ -1214,8 +1317,9 @@ define i1 @abs_intrin_eq_zero(i8 %x) { } define i1 @abs_intrin_ne_zero(i8 %x) { -; CHECK-LABEL: @abs_intrin_ne_zero( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @abs_intrin_ne_zero( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %abs = call i8 @llvm.abs.i8(i8 %x, i1 false) @@ -1224,7 +1328,7 @@ define i1 @abs_intrin_ne_zero(i8 %x) { } define void @test58() { -; CHECK-LABEL: @test58( +; CHECK-LABEL: define void @test58() { ; CHECK-NEXT: [[CALL:%.*]] = call i32 @test58_d(i64 36029346783166592) ; CHECK-NEXT: ret void ; @@ -1236,8 +1340,9 @@ declare i32 @test58_d(i64) ; Negative test: GEP inbounds may cross sign boundary. define i1 @test62(ptr %a) { -; CHECK-LABEL: @test62( -; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw i8, ptr [[A:%.*]], i64 1 +; CHECK-LABEL: define i1 @test62( +; CHECK-SAME: ptr [[A:%.*]]) { +; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 1 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr [[A]], i64 10 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt ptr [[ARRAYIDX1]], [[ARRAYIDX2]] ; CHECK-NEXT: ret i1 [[CMP]] @@ -1249,8 +1354,9 @@ define i1 @test62(ptr %a) { } define i1 @test62_as1(ptr addrspace(1) %a) { -; CHECK-LABEL: @test62_as1( -; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[A:%.*]], i16 1 +; CHECK-LABEL: define i1 @test62_as1( +; CHECK-SAME: ptr addrspace(1) [[A:%.*]]) { +; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[A]], i16 1 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[A]], i16 10 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt ptr addrspace(1) [[ARRAYIDX1]], [[ARRAYIDX2]] ; CHECK-NEXT: ret i1 [[CMP]] @@ -1262,9 +1368,10 @@ define i1 @test62_as1(ptr addrspace(1) %a) { } define i1 @low_mask_eq_zext(i8 %a, i32 %b) { -; CHECK-LABEL: @low_mask_eq_zext( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8 -; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A:%.*]], [[TMP1]] +; CHECK-LABEL: define i1 @low_mask_eq_zext( +; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] ; %z = zext i8 %a to i32 @@ -1274,9 +1381,10 @@ define i1 @low_mask_eq_zext(i8 %a, i32 %b) { } define i1 @low_mask_eq_zext_commute(i8 %a, i32 %b) { -; CHECK-LABEL: @low_mask_eq_zext_commute( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8 -; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A:%.*]], [[TMP1]] +; CHECK-LABEL: define i1 @low_mask_eq_zext_commute( +; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] ; %t = and i32 %b, 255 @@ -1288,9 +1396,10 @@ define i1 @low_mask_eq_zext_commute(i8 %a, i32 %b) { ; negative test define i1 @wrong_low_mask_eq_zext(i8 %a, i32 %b) { -; CHECK-LABEL: @wrong_low_mask_eq_zext( -; CHECK-NEXT: [[T:%.*]] = and i32 [[B:%.*]], 127 -; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A:%.*]] to i32 +; CHECK-LABEL: define i1 @wrong_low_mask_eq_zext( +; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[T:%.*]] = and i32 [[B]], 127 +; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A]] to i32 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[T]], [[Z]] ; CHECK-NEXT: ret i1 [[C]] ; @@ -1303,9 +1412,10 @@ define i1 @wrong_low_mask_eq_zext(i8 %a, i32 %b) { ; negative test define i1 @wrong_low_mask_eq_zext2(i8 %a, i32 %b) { -; CHECK-LABEL: @wrong_low_mask_eq_zext2( -; CHECK-NEXT: [[T:%.*]] = and i32 [[B:%.*]], 254 -; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A:%.*]] to i32 +; CHECK-LABEL: define i1 @wrong_low_mask_eq_zext2( +; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[T:%.*]] = and i32 [[B]], 254 +; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A]] to i32 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[T]], [[Z]] ; CHECK-NEXT: ret i1 [[C]] ; @@ -1316,11 +1426,12 @@ define i1 @wrong_low_mask_eq_zext2(i8 %a, i32 %b) { } define i1 @low_mask_eq_zext_use1(i8 %a, i32 %b) { -; CHECK-LABEL: @low_mask_eq_zext_use1( -; CHECK-NEXT: [[T:%.*]] = and i32 [[B:%.*]], 255 +; CHECK-LABEL: define i1 @low_mask_eq_zext_use1( +; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[T:%.*]] = and i32 [[B]], 255 ; CHECK-NEXT: call void @use_i32(i32 [[T]]) ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B]] to i8 -; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A:%.*]], [[TMP1]] +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] ; %t = and i32 %b, 255 @@ -1331,10 +1442,11 @@ define i1 @low_mask_eq_zext_use1(i8 %a, i32 %b) { } define i1 @low_mask_eq_zext_use2(i8 %a, i32 %b) { -; CHECK-LABEL: @low_mask_eq_zext_use2( -; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A:%.*]] to i32 +; CHECK-LABEL: define i1 @low_mask_eq_zext_use2( +; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A]] to i32 ; CHECK-NEXT: call void @use_i32(i32 [[Z]]) -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8 +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B]] to i8 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] ; @@ -1346,10 +1458,11 @@ define i1 @low_mask_eq_zext_use2(i8 %a, i32 %b) { } define i1 @low_mask_eq_zext_use3(i8 %a, i32 %b) { -; CHECK-LABEL: @low_mask_eq_zext_use3( -; CHECK-NEXT: [[T:%.*]] = and i32 [[B:%.*]], 255 +; CHECK-LABEL: define i1 @low_mask_eq_zext_use3( +; CHECK-SAME: i8 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[T:%.*]] = and i32 [[B]], 255 ; CHECK-NEXT: call void @use_i32(i32 [[T]]) -; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A:%.*]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext i8 [[A]] to i32 ; CHECK-NEXT: call void @use_i32(i32 [[Z]]) ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[T]], [[Z]] ; CHECK-NEXT: ret i1 [[C]] @@ -1363,9 +1476,10 @@ define i1 @low_mask_eq_zext_use3(i8 %a, i32 %b) { } define <2 x i1> @low_mask_eq_zext_vec_splat(<2 x i8> %a, <2 x i32> %b) { -; CHECK-LABEL: @low_mask_eq_zext_vec_splat( -; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[B:%.*]] to <2 x i8> -; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[A:%.*]], [[TMP1]] +; CHECK-LABEL: define <2 x i1> @low_mask_eq_zext_vec_splat( +; CHECK-SAME: <2 x i8> [[A:%.*]], <2 x i32> [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[B]] to <2 x i8> +; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[A]], [[TMP1]] ; CHECK-NEXT: ret <2 x i1> [[C]] ; %t = and <2 x i32> %b, <i32 255, i32 255> @@ -1375,7 +1489,8 @@ define <2 x i1> @low_mask_eq_zext_vec_splat(<2 x i8> %a, <2 x i32> %b) { } define i1 @test65(i64 %A, i64 %B) { -; CHECK-LABEL: @test65( +; CHECK-LABEL: define i1 @test65( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { ; CHECK-NEXT: ret i1 true ; %s1 = add i64 %A, %B @@ -1385,7 +1500,8 @@ define i1 @test65(i64 %A, i64 %B) { } define i1 @test66(i64 %A, i64 %B) { -; CHECK-LABEL: @test66( +; CHECK-LABEL: define i1 @test66( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { ; CHECK-NEXT: ret i1 true ; %s1 = add i64 %A, %B @@ -1395,8 +1511,9 @@ define i1 @test66(i64 %A, i64 %B) { } define i1 @test67(i32 %x) { -; CHECK-LABEL: @test67( -; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 96 +; CHECK-LABEL: define i1 @test67( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X]], 96 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1406,8 +1523,9 @@ define i1 @test67(i32 %x) { } define i1 @test67inverse(i32 %x) { -; CHECK-LABEL: @test67inverse( -; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 96 +; CHECK-LABEL: define i1 @test67inverse( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X]], 96 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1420,8 +1538,9 @@ define i1 @test67inverse(i32 %x) { ; This test only checks the last of those (icmp ugt -> icmp ne). define <2 x i1> @test67vec(<2 x i32> %x) { -; CHECK-LABEL: @test67vec( -; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 96) +; CHECK-LABEL: define <2 x i1> @test67vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X]], splat (i32 96) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[AND]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1431,8 +1550,9 @@ define <2 x i1> @test67vec(<2 x i32> %x) { } define <2 x i1> @test67vec2(<2 x i32> %x) { -; CHECK-LABEL: @test67vec2( -; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 96) +; CHECK-LABEL: define <2 x i1> @test67vec2( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X]], splat (i32 96) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[AND]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1442,8 +1562,9 @@ define <2 x i1> @test67vec2(<2 x i32> %x) { } define <2 x i1> @test67vecinverse(<2 x i32> %x) { -; CHECK-LABEL: @test67vecinverse( -; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 96) +; CHECK-LABEL: define <2 x i1> @test67vecinverse( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X]], splat (i32 96) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[AND]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1453,8 +1574,9 @@ define <2 x i1> @test67vecinverse(<2 x i32> %x) { } define i1 @test68(i32 %x) { -; CHECK-LABEL: @test68( -; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 127 +; CHECK-LABEL: define i1 @test68( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X]], 127 ; CHECK-NEXT: [[CMP:%.*]] = icmp samesign ugt i32 [[AND]], 30 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1465,8 +1587,9 @@ define i1 @test68(i32 %x) { ; PR15940 define i1 @test70(i32 %X) { -; CHECK-LABEL: @test70( -; CHECK-NEXT: [[A:%.*]] = srem i32 5, [[X:%.*]] +; CHECK-LABEL: define i1 @test70( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = srem i32 5, [[X]] ; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A]], 2 ; CHECK-NEXT: ret i1 [[C]] ; @@ -1477,8 +1600,9 @@ define i1 @test70(i32 %X) { } define <2 x i1> @test70vec(<2 x i32> %X) { -; CHECK-LABEL: @test70vec( -; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i32> [[X:%.*]], splat (i32 2) +; CHECK-LABEL: define <2 x i1> @test70vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i32> [[X]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[C]] ; %B = add <2 x i32> %X, <i32 2, i32 2> @@ -1487,8 +1611,9 @@ define <2 x i1> @test70vec(<2 x i32> %X) { } define i1 @icmp_sext16trunc(i32 %x) { -; CHECK-LABEL: @icmp_sext16trunc( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16 +; CHECK-LABEL: define i1 @icmp_sext16trunc( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X]] to i16 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[TMP1]], 36 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1499,8 +1624,9 @@ define i1 @icmp_sext16trunc(i32 %x) { } define i1 @icmp_sext8trunc(i32 %x) { -; CHECK-LABEL: @icmp_sext8trunc( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8 +; CHECK-LABEL: define i1 @icmp_sext8trunc( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X]] to i8 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 36 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1512,8 +1638,9 @@ define i1 @icmp_sext8trunc(i32 %x) { ; Vectors should fold the same way. define <2 x i1> @icmp_sext8trunc_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_sext8trunc_vec( -; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i8> +; CHECK-LABEL: define <2 x i1> @icmp_sext8trunc_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[X]] to <2 x i8> ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[TMP1]], splat (i8 36) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1524,8 +1651,9 @@ define <2 x i1> @icmp_sext8trunc_vec(<2 x i32> %x) { } define i1 @icmp_shl16(i32 %x) { -; CHECK-LABEL: @icmp_shl16( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16 +; CHECK-LABEL: define i1 @icmp_shl16( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X]] to i16 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[TMP1]], 36 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1537,8 +1665,9 @@ define i1 @icmp_shl16(i32 %x) { ; D25952: Don't create illegal types like i15 in InstCombine define i1 @icmp_shl17(i32 %x) { -; CHECK-LABEL: @icmp_shl17( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 17 +; CHECK-LABEL: define i1 @icmp_shl17( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X]], 17 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 2359296 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1548,8 +1677,9 @@ define i1 @icmp_shl17(i32 %x) { } define <2 x i1> @icmp_shl16_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_shl16_vec( -; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[X:%.*]] to <2 x i16> +; CHECK-LABEL: define <2 x i1> @icmp_shl16_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> [[X]] to <2 x i16> ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i16> [[TMP1]], splat (i16 36) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1559,8 +1689,9 @@ define <2 x i1> @icmp_shl16_vec(<2 x i32> %x) { } define i1 @icmp_shl24(i32 %x) { -; CHECK-LABEL: @icmp_shl24( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8 +; CHECK-LABEL: define i1 @icmp_shl24( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X]] to i8 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 36 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1570,8 +1701,9 @@ define i1 @icmp_shl24(i32 %x) { } define i1 @icmp_shl_eq(i32 %x) { -; CHECK-LABEL: @icmp_shl_eq( -; CHECK-NEXT: [[MUL_MASK:%.*]] = and i32 [[X:%.*]], 134217727 +; CHECK-LABEL: define i1 @icmp_shl_eq( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[MUL_MASK:%.*]] = and i32 [[X]], 134217727 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[MUL_MASK]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1581,8 +1713,9 @@ define i1 @icmp_shl_eq(i32 %x) { } define <2 x i1> @icmp_shl_eq_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_shl_eq_vec( -; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 134217727) +; CHECK-LABEL: define <2 x i1> @icmp_shl_eq_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> [[X]], splat (i32 134217727) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[MUL_MASK]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1592,8 +1725,9 @@ define <2 x i1> @icmp_shl_eq_vec(<2 x i32> %x) { } define i1 @icmp_shl_nsw_ne(i32 %x) { -; CHECK-LABEL: @icmp_shl_nsw_ne( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @icmp_shl_nsw_ne( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = shl nsw i32 %x, 7 @@ -1602,8 +1736,9 @@ define i1 @icmp_shl_nsw_ne(i32 %x) { } define <2 x i1> @icmp_shl_nsw_ne_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_shl_nsw_ne_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @icmp_shl_nsw_ne_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %mul = shl nsw <2 x i32> %x, <i32 7, i32 7> @@ -1612,8 +1747,9 @@ define <2 x i1> @icmp_shl_nsw_ne_vec(<2 x i32> %x) { } define i1 @icmp_shl_ne(i32 %x) { -; CHECK-LABEL: @icmp_shl_ne( -; CHECK-NEXT: [[MUL_MASK:%.*]] = and i32 [[X:%.*]], 33554431 +; CHECK-LABEL: define i1 @icmp_shl_ne( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[MUL_MASK:%.*]] = and i32 [[X]], 33554431 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[MUL_MASK]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1623,8 +1759,9 @@ define i1 @icmp_shl_ne(i32 %x) { } define <2 x i1> @icmp_shl_ne_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_shl_ne_vec( -; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 33554431) +; CHECK-LABEL: define <2 x i1> @icmp_shl_ne_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[MUL_MASK:%.*]] = and <2 x i32> [[X]], splat (i32 33554431) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[MUL_MASK]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1634,8 +1771,9 @@ define <2 x i1> @icmp_shl_ne_vec(<2 x i32> %x) { } define <2 x i1> @icmp_shl_nuw_ne_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_shl_nuw_ne_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X:%.*]], splat (i32 2) +; CHECK-LABEL: define <2 x i1> @icmp_shl_nuw_ne_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl nuw <2 x i32> %x, <i32 7, i32 7> @@ -1646,8 +1784,9 @@ define <2 x i1> @icmp_shl_nuw_ne_vec(<2 x i32> %x) { ; If the (mul x, C) preserved the sign and this is sign test, ; compare the LHS operand instead define i1 @icmp_mul_nsw(i32 %x) { -; CHECK-LABEL: @icmp_mul_nsw( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @icmp_mul_nsw( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul nsw i32 %x, 12 @@ -1656,8 +1795,9 @@ define i1 @icmp_mul_nsw(i32 %x) { } define i1 @icmp_mul_nsw1(i32 %x) { -; CHECK-LABEL: @icmp_mul_nsw1( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @icmp_mul_nsw1( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul nsw i32 %x, 12 @@ -1666,8 +1806,9 @@ define i1 @icmp_mul_nsw1(i32 %x) { } define i1 @icmp_mul_nsw_neg(i32 %x) { -; CHECK-LABEL: @icmp_mul_nsw_neg( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1 +; CHECK-LABEL: define i1 @icmp_mul_nsw_neg( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul nsw i32 %x, -12 @@ -1676,8 +1817,9 @@ define i1 @icmp_mul_nsw_neg(i32 %x) { } define i1 @icmp_mul_nsw_neg1(i32 %x) { -; CHECK-LABEL: @icmp_mul_nsw_neg1( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @icmp_mul_nsw_neg1( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul nsw i32 %x, -12 @@ -1686,8 +1828,9 @@ define i1 @icmp_mul_nsw_neg1(i32 %x) { } define <2 x i1> @icmp_mul_nsw_neg1_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_mul_nsw_neg1_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @icmp_mul_nsw_neg1_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %mul = mul nsw <2 x i32> %x, <i32 -12, i32 -12> @@ -1696,7 +1839,8 @@ define <2 x i1> @icmp_mul_nsw_neg1_vec(<2 x i32> %x) { } define i1 @icmp_mul_nsw_0(i32 %x) { -; CHECK-LABEL: @icmp_mul_nsw_0( +; CHECK-LABEL: define i1 @icmp_mul_nsw_0( +; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: ret i1 false ; %mul = mul nsw i32 %x, 0 @@ -1705,8 +1849,9 @@ define i1 @icmp_mul_nsw_0(i32 %x) { } define i1 @icmp_mul(i32 %x) { -; CHECK-LABEL: @icmp_mul( -; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], -12 +; CHECK-LABEL: define i1 @icmp_mul( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X]], -12 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[MUL]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1717,8 +1862,9 @@ define i1 @icmp_mul(i32 %x) { ; Checks for icmp (eq|ne) (mul x, C), 0 define i1 @icmp_mul_neq0(i32 %x) { -; CHECK-LABEL: @icmp_mul_neq0( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @icmp_mul_neq0( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul nsw i32 %x, -12 @@ -1727,8 +1873,9 @@ define i1 @icmp_mul_neq0(i32 %x) { } define <2 x i1> @icmp_mul_neq0_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_mul_neq0_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @icmp_mul_neq0_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %mul = mul nsw <2 x i32> %x, <i32 -12, i32 -12> @@ -1737,8 +1884,9 @@ define <2 x i1> @icmp_mul_neq0_vec(<2 x i32> %x) { } define i1 @icmp_mul_eq0(i32 %x) { -; CHECK-LABEL: @icmp_mul_eq0( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @icmp_mul_eq0( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul nsw i32 %x, 12 @@ -1747,7 +1895,8 @@ define i1 @icmp_mul_eq0(i32 %x) { } define i1 @icmp_mul0_eq0(i32 %x) { -; CHECK-LABEL: @icmp_mul0_eq0( +; CHECK-LABEL: define i1 @icmp_mul0_eq0( +; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: ret i1 true ; %mul = mul i32 %x, 0 @@ -1756,7 +1905,8 @@ define i1 @icmp_mul0_eq0(i32 %x) { } define i1 @icmp_mul0_ne0(i32 %x) { -; CHECK-LABEL: @icmp_mul0_ne0( +; CHECK-LABEL: define i1 @icmp_mul0_ne0( +; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: ret i1 false ; %mul = mul i32 %x, 0 @@ -1765,9 +1915,10 @@ define i1 @icmp_mul0_ne0(i32 %x) { } define i1 @icmp_add20_eq_add57(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_add20_eq_add57( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y:%.*]], 37 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define i1 @icmp_add20_eq_add57( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y]], 37 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], [[TMP1]] ; CHECK-NEXT: ret i1 [[CMP]] ; %1 = add i32 %x, 20 @@ -1777,9 +1928,10 @@ define i1 @icmp_add20_eq_add57(i32 %x, i32 %y) { } define <2 x i1> @icmp_add20_eq_add57_splat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_add20_eq_add57_splat( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y:%.*]], splat (i32 37) -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define <2 x i1> @icmp_add20_eq_add57_splat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y]], splat (i32 37) +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X]], [[TMP1]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add <2 x i32> %x, <i32 20, i32 20> @@ -1789,9 +1941,10 @@ define <2 x i1> @icmp_add20_eq_add57_splat(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_add20_eq_add57_poison(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_add20_eq_add57_poison( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y:%.*]], splat (i32 37) -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define <2 x i1> @icmp_add20_eq_add57_poison( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y]], splat (i32 37) +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X]], [[TMP1]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add <2 x i32> %x, <i32 20, i32 20> @@ -1801,9 +1954,10 @@ define <2 x i1> @icmp_add20_eq_add57_poison(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_add20_eq_add57_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_add20_eq_add57_vec_nonsplat( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y:%.*]], <i32 37, i32 39> -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define <2 x i1> @icmp_add20_eq_add57_vec_nonsplat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y]], <i32 37, i32 39> +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X]], [[TMP1]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add <2 x i32> %x, <i32 20, i32 19> @@ -1813,9 +1967,10 @@ define <2 x i1> @icmp_add20_eq_add57_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { } define i1 @icmp_sub57_ne_sub20(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_sub57_ne_sub20( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -37 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_sub57_ne_sub20( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -37 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %1 = add i32 %x, -57 @@ -1825,9 +1980,10 @@ define i1 @icmp_sub57_ne_sub20(i32 %x, i32 %y) { } define <2 x i1> @icmp_sub57_ne_sub20_splat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_sub57_ne_sub20_splat( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], splat (i32 -37) -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-LABEL: define <2 x i1> @icmp_sub57_ne_sub20_splat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X]], splat (i32 -37) +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], [[Y]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add <2 x i32> %x, <i32 -57, i32 -57> @@ -1837,9 +1993,10 @@ define <2 x i1> @icmp_sub57_ne_sub20_splat(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_sub57_ne_sub20_vec_poison(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_sub57_ne_sub20_vec_poison( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], splat (i32 -37) -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-LABEL: define <2 x i1> @icmp_sub57_ne_sub20_vec_poison( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X]], splat (i32 -37) +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], [[Y]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add <2 x i32> %x, <i32 -57, i32 poison> @@ -1849,9 +2006,10 @@ define <2 x i1> @icmp_sub57_ne_sub20_vec_poison(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_sub57_ne_sub20_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_sub57_ne_sub20_vec_nonsplat( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y:%.*]], splat (i32 37) -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define <2 x i1> @icmp_sub57_ne_sub20_vec_nonsplat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[Y]], splat (i32 37) +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[X]], [[TMP1]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add <2 x i32> %x, <i32 -57, i32 -58> @@ -1861,8 +2019,9 @@ define <2 x i1> @icmp_sub57_ne_sub20_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { } define i1 @icmp_sub1_sge(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_sub1_sge( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_sub1_sge( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %sub = add nsw i32 %x, -1 @@ -1871,8 +2030,9 @@ define i1 @icmp_sub1_sge(i32 %x, i32 %y) { } define i1 @icmp_add1_sgt(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_add1_sgt( -; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_add1_sgt( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %add = add nsw i32 %x, 1 @@ -1881,8 +2041,9 @@ define i1 @icmp_add1_sgt(i32 %x, i32 %y) { } define i1 @icmp_sub1_slt(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_sub1_slt( -; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_sub1_slt( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %sub = add nsw i32 %x, -1 @@ -1891,8 +2052,9 @@ define i1 @icmp_sub1_slt(i32 %x, i32 %y) { } define i1 @icmp_add1_sle(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_add1_sle( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_add1_sle( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %add = add nsw i32 %x, 1 @@ -1901,9 +2063,10 @@ define i1 @icmp_add1_sle(i32 %x, i32 %y) { } define i1 @icmp_slt_offset_with_common_divisor(i64 %x, i64 %y) { -; CHECK-LABEL: @icmp_slt_offset_with_common_divisor( -; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X:%.*]], 4 -; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_slt_offset_with_common_divisor( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X]], 4 +; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y]], 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp sle i64 [[SHLX]], [[SHLY]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1915,9 +2078,10 @@ define i1 @icmp_slt_offset_with_common_divisor(i64 %x, i64 %y) { } define i1 @icmp_slt_offset_with_smaller_common_divisor(i64 %x, i64 %y) { -; CHECK-LABEL: @icmp_slt_offset_with_smaller_common_divisor( -; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X:%.*]], 4 -; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_slt_offset_with_smaller_common_divisor( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X]], 4 +; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y]], 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp sle i64 [[SHLX]], [[SHLY]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1929,9 +2093,10 @@ define i1 @icmp_slt_offset_with_smaller_common_divisor(i64 %x, i64 %y) { } define i1 @icmp_sle_offset_with_common_divisor(i64 %x, i64 %y) { -; CHECK-LABEL: @icmp_sle_offset_with_common_divisor( -; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X:%.*]], 4 -; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_sle_offset_with_common_divisor( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X]], 4 +; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y]], 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[SHLX]], [[SHLY]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1943,9 +2108,10 @@ define i1 @icmp_sle_offset_with_common_divisor(i64 %x, i64 %y) { } define i1 @icmp_ule_offset_with_common_divisor(i64 %x, i64 %y) { -; CHECK-LABEL: @icmp_ule_offset_with_common_divisor( -; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X:%.*]], 4 -; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_ule_offset_with_common_divisor( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X]], 4 +; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y]], 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SHLX]], [[SHLY]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1958,9 +2124,10 @@ define i1 @icmp_ule_offset_with_common_divisor(i64 %x, i64 %y) { ; TODO: Handle non-power-of-2 divisors define i1 @icmp_ule_offset_with_common_non_pow2_divisor(i64 %x, i64 %y) { -; CHECK-LABEL: @icmp_ule_offset_with_common_non_pow2_divisor( -; CHECK-NEXT: [[MULX:%.*]] = mul nuw i64 [[X:%.*]], 7 -; CHECK-NEXT: [[MULY:%.*]] = mul nuw i64 [[Y:%.*]], 7 +; CHECK-LABEL: define i1 @icmp_ule_offset_with_common_non_pow2_divisor( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[MULX:%.*]] = mul nuw i64 [[X]], 7 +; CHECK-NEXT: [[MULY:%.*]] = mul nuw i64 [[Y]], 7 ; CHECK-NEXT: [[MULX_OFFSET:%.*]] = add nuw i64 [[MULX]], 7 ; CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[MULX_OFFSET]], [[MULY]] ; CHECK-NEXT: ret i1 [[CMP]] @@ -1973,9 +2140,10 @@ define i1 @icmp_ule_offset_with_common_non_pow2_divisor(i64 %x, i64 %y) { } define i1 @neg_icmp_slt_offset_without_common_divisor(i64 %x, i64 %y) { -; CHECK-LABEL: @neg_icmp_slt_offset_without_common_divisor( -; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X:%.*]], 4 -; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y:%.*]], 4 +; CHECK-LABEL: define i1 @neg_icmp_slt_offset_without_common_divisor( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X]], 4 +; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y]], 4 ; CHECK-NEXT: [[SHLX_OFFSET:%.*]] = add nsw i64 [[SHLX]], -32 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[SHLX_OFFSET]], [[SHLY]] ; CHECK-NEXT: ret i1 [[CMP]] @@ -1988,9 +2156,10 @@ define i1 @neg_icmp_slt_offset_without_common_divisor(i64 %x, i64 %y) { } define i1 @neg_icmp_slt_offset_with_wrong_sign(i64 %x, i64 %y) { -; CHECK-LABEL: @neg_icmp_slt_offset_with_wrong_sign( -; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X:%.*]], 4 -; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y:%.*]], 4 +; CHECK-LABEL: define i1 @neg_icmp_slt_offset_with_wrong_sign( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[SHLX:%.*]] = shl i64 [[X]], 4 +; CHECK-NEXT: [[SHLY:%.*]] = shl i64 [[Y]], 4 ; CHECK-NEXT: [[SHLX_OFFSET:%.*]] = add nsw i64 [[SHLX]], 16 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[SHLX_OFFSET]], [[SHLY]] ; CHECK-NEXT: ret i1 [[CMP]] @@ -2003,9 +2172,10 @@ define i1 @neg_icmp_slt_offset_with_wrong_sign(i64 %x, i64 %y) { } define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_add20_sge_add57( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[Y:%.*]], 37 -; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define i1 @icmp_add20_sge_add57( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[Y]], 37 +; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X]], [[TMP1]] ; CHECK-NEXT: ret i1 [[CMP]] ; %1 = add nsw i32 %x, 20 @@ -2015,9 +2185,10 @@ define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) { } define <2 x i1> @icmp_add20_sge_add57_splat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_add20_sge_add57_splat( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[Y:%.*]], splat (i32 37) -; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define <2 x i1> @icmp_add20_sge_add57_splat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[Y]], splat (i32 37) +; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[X]], [[TMP1]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add nsw <2 x i32> %x, <i32 20, i32 20> @@ -2027,9 +2198,10 @@ define <2 x i1> @icmp_add20_sge_add57_splat(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_add20_sge_add57_poison(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_add20_sge_add57_poison( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[Y:%.*]], splat (i32 37) -; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[X:%.*]], [[TMP1]] +; CHECK-LABEL: define <2 x i1> @icmp_add20_sge_add57_poison( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[Y]], splat (i32 37) +; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[X]], [[TMP1]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add nsw <2 x i32> %x, <i32 20, i32 20> @@ -2039,9 +2211,10 @@ define <2 x i1> @icmp_add20_sge_add57_poison(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_add20_sge_add57_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_add20_sge_add57_vec_nonsplat( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 20, i32 19> -; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 57, i32 58> +; CHECK-LABEL: define <2 x i1> @icmp_add20_sge_add57_vec_nonsplat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X]], <i32 20, i32 19> +; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[Y]], <i32 57, i32 58> ; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -2052,9 +2225,10 @@ define <2 x i1> @icmp_add20_sge_add57_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { } define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_sub57_sge_sub20( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[X:%.*]], -37 -; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[TMP1]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_sub57_sge_sub20( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[X]], -37 +; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[TMP1]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %1 = add nsw i32 %x, -57 @@ -2064,9 +2238,10 @@ define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) { } define <2 x i1> @icmp_sub57_sge_sub20_splat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_sub57_sge_sub20_splat( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], splat (i32 -37) -; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-LABEL: define <2 x i1> @icmp_sub57_sge_sub20_splat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X]], splat (i32 -37) +; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[Y]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add nsw <2 x i32> %x, <i32 -57, i32 -57> @@ -2076,9 +2251,10 @@ define <2 x i1> @icmp_sub57_sge_sub20_splat(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_sub57_sge_sub20_vec_poison(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_sub57_sge_sub20_vec_poison( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], splat (i32 -37) -; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[Y:%.*]] +; CHECK-LABEL: define <2 x i1> @icmp_sub57_sge_sub20_vec_poison( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X]], splat (i32 -37) +; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[Y]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %1 = add nsw <2 x i32> %x, <i32 -57, i32 poison> @@ -2088,9 +2264,10 @@ define <2 x i1> @icmp_sub57_sge_sub20_vec_poison(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_sub57_sge_sub20_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_sub57_sge_sub20_vec_nonsplat( -; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X:%.*]], <i32 -57, i32 -58> -; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[Y:%.*]], <i32 -20, i32 -21> +; CHECK-LABEL: define <2 x i1> @icmp_sub57_sge_sub20_vec_nonsplat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i32> [[X]], <i32 -57, i32 -58> +; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i32> [[Y]], <i32 -20, i32 -21> ; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -2101,9 +2278,10 @@ define <2 x i1> @icmp_sub57_sge_sub20_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { } define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) { -; CHECK-LABEL: @icmp_and_shl_neg_ne_0( -; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A:%.*]] +; CHECK-LABEL: define i1 @icmp_and_shl_neg_ne_0( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2115,9 +2293,10 @@ define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) { } define i1 @icmp_and_shl_neg_ne_0_shl2_no_flags(i32 %A, i32 %B) { -; CHECK-LABEL: @icmp_and_shl_neg_ne_0_shl2_no_flags( -; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[A:%.*]], -1 -; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, [[B:%.*]] +; CHECK-LABEL: define i1 @icmp_and_shl_neg_ne_0_shl2_no_flags( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[A]], -1 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, [[B]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[NEG]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: ret i1 [[CMP]] @@ -2130,9 +2309,10 @@ define i1 @icmp_and_shl_neg_ne_0_shl2_no_flags(i32 %A, i32 %B) { } define i1 @icmp_and_shl_neg_ne_0_shl2_nuw(i32 %A, i32 %B) { -; CHECK-LABEL: @icmp_and_shl_neg_ne_0_shl2_nuw( -; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 2, [[B:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A:%.*]] +; CHECK-LABEL: define i1 @icmp_and_shl_neg_ne_0_shl2_nuw( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 2, [[B]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2144,9 +2324,10 @@ define i1 @icmp_and_shl_neg_ne_0_shl2_nuw(i32 %A, i32 %B) { } define i1 @icmp_and_shl_neg_ne_0_shl2_nsw(i32 %A, i32 %B) { -; CHECK-LABEL: @icmp_and_shl_neg_ne_0_shl2_nsw( -; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 2, [[B:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A:%.*]] +; CHECK-LABEL: define i1 @icmp_and_shl_neg_ne_0_shl2_nsw( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 2, [[B]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2158,9 +2339,10 @@ define i1 @icmp_and_shl_neg_ne_0_shl2_nsw(i32 %A, i32 %B) { } define i1 @icmp_and_shl_neg_eq_0(i32 %A, i32 %B) { -; CHECK-LABEL: @icmp_and_shl_neg_eq_0( -; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A:%.*]] +; CHECK-LABEL: define i1 @icmp_and_shl_neg_eq_0( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2172,8 +2354,9 @@ define i1 @icmp_and_shl_neg_eq_0(i32 %A, i32 %B) { } define i1 @icmp_add_and_shr_ne_0(i32 %X) { -; CHECK-LABEL: @icmp_add_and_shr_ne_0( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240 +; CHECK-LABEL: define i1 @icmp_add_and_shr_ne_0( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], 240 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 224 ; CHECK-NEXT: ret i1 [[TOBOOL]] ; @@ -2185,8 +2368,9 @@ define i1 @icmp_add_and_shr_ne_0(i32 %X) { } define <2 x i1> @icmp_add_and_shr_ne_0_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_add_and_shr_ne_0_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 240) +; CHECK-LABEL: define <2 x i1> @icmp_add_and_shr_ne_0_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 240) ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <2 x i32> [[TMP1]], splat (i32 224) ; CHECK-NEXT: ret <2 x i1> [[TOBOOL]] ; @@ -2199,8 +2383,9 @@ define <2 x i1> @icmp_add_and_shr_ne_0_vec(<2 x i32> %X) { ; Variation of the above with an extra use of the shift define i1 @icmp_and_shr_multiuse(i32 %X) { -; CHECK-LABEL: @icmp_and_shr_multiuse( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240 +; CHECK-LABEL: define i1 @icmp_and_shr_multiuse( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], 240 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 224 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[X]], 496 ; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP2]], 432 @@ -2217,8 +2402,9 @@ define i1 @icmp_and_shr_multiuse(i32 %X) { } define i1 @icmp_and_shr_multiuse_logical(i32 %X) { -; CHECK-LABEL: @icmp_and_shr_multiuse_logical( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240 +; CHECK-LABEL: define i1 @icmp_and_shr_multiuse_logical( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], 240 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 224 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[X]], 496 ; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP2]], 432 @@ -2236,8 +2422,9 @@ define i1 @icmp_and_shr_multiuse_logical(i32 %X) { ; Variation of the above with an ashr define i1 @icmp_and_ashr_multiuse(i32 %X) { -; CHECK-LABEL: @icmp_and_ashr_multiuse( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240 +; CHECK-LABEL: define i1 @icmp_and_ashr_multiuse( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], 240 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 224 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[X]], 496 ; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP2]], 432 @@ -2254,8 +2441,9 @@ define i1 @icmp_and_ashr_multiuse(i32 %X) { } define i1 @icmp_and_ashr_multiuse_logical(i32 %X) { -; CHECK-LABEL: @icmp_and_ashr_multiuse_logical( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 240 +; CHECK-LABEL: define i1 @icmp_and_ashr_multiuse_logical( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], 240 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 224 ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[X]], 496 ; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp ne i32 [[TMP2]], 432 @@ -2272,8 +2460,9 @@ define i1 @icmp_and_ashr_multiuse_logical(i32 %X) { } define i1 @icmp_lshr_and_overshift(i8 %X) { -; CHECK-LABEL: @icmp_lshr_and_overshift( -; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ugt i8 [[X:%.*]], 31 +; CHECK-LABEL: define i1 @icmp_lshr_and_overshift( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ugt i8 [[X]], 31 ; CHECK-NEXT: ret i1 [[TOBOOL]] ; %shr = lshr i8 %X, 5 @@ -2284,8 +2473,9 @@ define i1 @icmp_lshr_and_overshift(i8 %X) { ; We shouldn't simplify this because the and uses bits that are shifted in. define i1 @icmp_ashr_and_overshift(i8 %X) { -; CHECK-LABEL: @icmp_ashr_and_overshift( -; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[X:%.*]], 5 +; CHECK-LABEL: define i1 @icmp_ashr_and_overshift( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[X]], 5 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[SHR]], 15 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[AND]], 0 ; CHECK-NEXT: ret i1 [[TOBOOL]] @@ -2297,8 +2487,9 @@ define i1 @icmp_ashr_and_overshift(i8 %X) { } define i1 @icmp_and_ashr_neg_and_legal(i8 %x) { -; CHECK-LABEL: @icmp_and_ashr_neg_and_legal( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 32 +; CHECK-LABEL: define i1 @icmp_and_ashr_neg_and_legal( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X]], 32 ; CHECK-NEXT: ret i1 [[CMP]] ; %ashr = ashr i8 %x, 4 @@ -2309,8 +2500,9 @@ define i1 @icmp_and_ashr_neg_and_legal(i8 %x) { ; Negative test. define i1 @icmp_and_ashr_mixed_and_shiftout(i8 %x) { -; CHECK-LABEL: @icmp_and_ashr_mixed_and_shiftout( -; CHECK-NEXT: [[ASHR:%.*]] = ashr i8 [[X:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_and_ashr_mixed_and_shiftout( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[ASHR:%.*]] = ashr i8 [[X]], 4 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[ASHR]], 31 ; CHECK-NEXT: [[CMP:%.*]] = icmp samesign ugt i8 [[AND]], 8 ; CHECK-NEXT: ret i1 [[CMP]] @@ -2322,8 +2514,9 @@ define i1 @icmp_and_ashr_mixed_and_shiftout(i8 %x) { } define i1 @icmp_and_ashr_neg_cmp_slt_legal(i8 %x) { -; CHECK-LABEL: @icmp_and_ashr_neg_cmp_slt_legal( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -32 +; CHECK-LABEL: define i1 @icmp_and_ashr_neg_cmp_slt_legal( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X]], -32 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], -64 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2335,8 +2528,9 @@ define i1 @icmp_and_ashr_neg_cmp_slt_legal(i8 %x) { ; Negative test. define i1 @icmp_and_ashr_neg_cmp_slt_shiftout(i8 %x) { -; CHECK-LABEL: @icmp_and_ashr_neg_cmp_slt_shiftout( -; CHECK-NEXT: [[ASHR:%.*]] = ashr i8 [[X:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_and_ashr_neg_cmp_slt_shiftout( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[ASHR:%.*]] = ashr i8 [[X]], 4 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[ASHR]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[AND]], -68 ; CHECK-NEXT: ret i1 [[CMP]] @@ -2348,8 +2542,9 @@ define i1 @icmp_and_ashr_neg_cmp_slt_shiftout(i8 %x) { } define i1 @icmp_and_ashr_neg_cmp_eq_legal(i8 %x) { -; CHECK-LABEL: @icmp_and_ashr_neg_cmp_eq_legal( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -32 +; CHECK-LABEL: define i1 @icmp_and_ashr_neg_cmp_eq_legal( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X]], -32 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], -64 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2360,7 +2555,8 @@ define i1 @icmp_and_ashr_neg_cmp_eq_legal(i8 %x) { } define i1 @icmp_and_ashr_neg_cmp_eq_shiftout(i8 %x) { -; CHECK-LABEL: @icmp_and_ashr_neg_cmp_eq_shiftout( +; CHECK-LABEL: define i1 @icmp_and_ashr_neg_cmp_eq_shiftout( +; CHECK-SAME: i8 [[X:%.*]]) { ; CHECK-NEXT: ret i1 false ; %ashr = ashr i8 %x, 4 @@ -2370,7 +2566,8 @@ define i1 @icmp_and_ashr_neg_cmp_eq_shiftout(i8 %x) { } define i1 @icmp_and_ashr_neg_cmp_ne_shiftout(i8 %x) { -; CHECK-LABEL: @icmp_and_ashr_neg_cmp_ne_shiftout( +; CHECK-LABEL: define i1 @icmp_and_ashr_neg_cmp_ne_shiftout( +; CHECK-SAME: i8 [[X:%.*]]) { ; CHECK-NEXT: ret i1 true ; %ashr = ashr i8 %x, 4 @@ -2380,8 +2577,9 @@ define i1 @icmp_and_ashr_neg_cmp_ne_shiftout(i8 %x) { } define i1 @icmp_shl_1_V_ult_32(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_ult_32( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[V:%.*]], 5 +; CHECK-LABEL: define i1 @icmp_shl_1_V_ult_32( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[V]], 5 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2390,8 +2588,9 @@ define i1 @icmp_shl_1_V_ult_32(i32 %V) { } define <2 x i1> @icmp_shl_1_V_ult_32_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_ult_32_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[V:%.*]], splat (i32 5) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_ult_32_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[V]], splat (i32 5) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2400,8 +2599,9 @@ define <2 x i1> @icmp_shl_1_V_ult_32_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_eq_32(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_eq_32( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V:%.*]], 5 +; CHECK-LABEL: define i1 @icmp_shl_1_V_eq_32( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V]], 5 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2410,8 +2610,9 @@ define i1 @icmp_shl_1_V_eq_32(i32 %V) { } define <2 x i1> @icmp_shl_1_V_eq_32_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_eq_32_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V:%.*]], splat (i32 5) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_eq_32_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V]], splat (i32 5) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2420,8 +2621,9 @@ define <2 x i1> @icmp_shl_1_V_eq_32_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_ult_30(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_ult_30( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[V:%.*]], 5 +; CHECK-LABEL: define i1 @icmp_shl_1_V_ult_30( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[V]], 5 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2430,8 +2632,9 @@ define i1 @icmp_shl_1_V_ult_30(i32 %V) { } define <2 x i1> @icmp_shl_1_V_ult_30_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_ult_30_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[V:%.*]], splat (i32 5) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_ult_30_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[V]], splat (i32 5) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2440,8 +2643,9 @@ define <2 x i1> @icmp_shl_1_V_ult_30_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_ugt_30(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_ugt_30( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[V:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_shl_1_V_ugt_30( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[V]], 4 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2450,8 +2654,9 @@ define i1 @icmp_shl_1_V_ugt_30(i32 %V) { } define <2 x i1> @icmp_shl_1_V_ugt_30_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_ugt_30_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[V:%.*]], splat (i32 4) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_ugt_30_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[V]], splat (i32 4) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2460,8 +2665,9 @@ define <2 x i1> @icmp_shl_1_V_ugt_30_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_ule_30(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_ule_30( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[V:%.*]], 5 +; CHECK-LABEL: define i1 @icmp_shl_1_V_ule_30( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[V]], 5 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2470,8 +2676,9 @@ define i1 @icmp_shl_1_V_ule_30(i32 %V) { } define <2 x i1> @icmp_shl_1_V_ule_30_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_ule_30_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[V:%.*]], splat (i32 5) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_ule_30_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[V]], splat (i32 5) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2480,8 +2687,9 @@ define <2 x i1> @icmp_shl_1_V_ule_30_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_uge_30(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_uge_30( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[V:%.*]], 4 +; CHECK-LABEL: define i1 @icmp_shl_1_V_uge_30( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[V]], 4 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2490,8 +2698,9 @@ define i1 @icmp_shl_1_V_uge_30(i32 %V) { } define <2 x i1> @icmp_shl_1_V_uge_30_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_uge_30_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[V:%.*]], splat (i32 4) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_uge_30_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[V]], splat (i32 4) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2500,8 +2709,9 @@ define <2 x i1> @icmp_shl_1_V_uge_30_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_uge_2147483648(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_uge_2147483648( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V:%.*]], 31 +; CHECK-LABEL: define i1 @icmp_shl_1_V_uge_2147483648( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V]], 31 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2510,8 +2720,9 @@ define i1 @icmp_shl_1_V_uge_2147483648(i32 %V) { } define <2 x i1> @icmp_shl_1_V_uge_2147483648_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_uge_2147483648_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V:%.*]], splat (i32 31) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_uge_2147483648_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V]], splat (i32 31) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2520,8 +2731,9 @@ define <2 x i1> @icmp_shl_1_V_uge_2147483648_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_ult_2147483648(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_ult_2147483648( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[V:%.*]], 31 +; CHECK-LABEL: define i1 @icmp_shl_1_V_ult_2147483648( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[V]], 31 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2530,8 +2742,9 @@ define i1 @icmp_shl_1_V_ult_2147483648(i32 %V) { } define <2 x i1> @icmp_shl_1_V_ult_2147483648_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_ult_2147483648_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[V:%.*]], splat (i32 31) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_ult_2147483648_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[V]], splat (i32 31) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2540,8 +2753,9 @@ define <2 x i1> @icmp_shl_1_V_ult_2147483648_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_sle_0(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_sle_0( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V:%.*]], 31 +; CHECK-LABEL: define i1 @icmp_shl_1_V_sle_0( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V]], 31 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2550,8 +2764,9 @@ define i1 @icmp_shl_1_V_sle_0(i32 %V) { } define <2 x i1> @icmp_shl_1_V_sle_0_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_sle_0_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V:%.*]], splat (i32 31) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_sle_0_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V]], splat (i32 31) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2560,8 +2775,9 @@ define <2 x i1> @icmp_shl_1_V_sle_0_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_sle_negative(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_sle_negative( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V:%.*]], 31 +; CHECK-LABEL: define i1 @icmp_shl_1_V_sle_negative( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[V]], 31 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2570,8 +2786,9 @@ define i1 @icmp_shl_1_V_sle_negative(i32 %V) { } define <2 x i1> @icmp_shl_1_V_sle_0_negative(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_sle_0_negative( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V:%.*]], splat (i32 31) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_sle_0_negative( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[V]], splat (i32 31) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2580,8 +2797,9 @@ define <2 x i1> @icmp_shl_1_V_sle_0_negative(<2 x i32> %V) { } define i1 @icmp_shl_1_V_sgt_0(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_sgt_0( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[V:%.*]], 31 +; CHECK-LABEL: define i1 @icmp_shl_1_V_sgt_0( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[V]], 31 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2590,8 +2808,9 @@ define i1 @icmp_shl_1_V_sgt_0(i32 %V) { } define <2 x i1> @icmp_shl_1_V_sgt_0_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_sgt_0_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[V:%.*]], splat (i32 31) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_sgt_0_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[V]], splat (i32 31) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2600,8 +2819,9 @@ define <2 x i1> @icmp_shl_1_V_sgt_0_vec(<2 x i32> %V) { } define i1 @icmp_shl_1_V_sgt_negative(i32 %V) { -; CHECK-LABEL: @icmp_shl_1_V_sgt_negative( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[V:%.*]], 31 +; CHECK-LABEL: define i1 @icmp_shl_1_V_sgt_negative( +; CHECK-SAME: i32 [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[V]], 31 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 1, %V @@ -2610,8 +2830,9 @@ define i1 @icmp_shl_1_V_sgt_negative(i32 %V) { } define <2 x i1> @icmp_shl_1_V_sgt_negative_vec(<2 x i32> %V) { -; CHECK-LABEL: @icmp_shl_1_V_sgt_negative_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[V:%.*]], splat (i32 31) +; CHECK-LABEL: define <2 x i1> @icmp_shl_1_V_sgt_negative_vec( +; CHECK-SAME: <2 x i32> [[V:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[V]], splat (i32 31) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 1, i32 1>, %V @@ -2620,9 +2841,10 @@ define <2 x i1> @icmp_shl_1_V_sgt_negative_vec(<2 x i32> %V) { } define i1 @or_icmp_eq_B_0_icmp_ult_A_B(i64 %a, i64 %b) { -; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B( -; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B:%.*]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define i1 @or_icmp_eq_B_0_icmp_ult_A_B( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[TMP1]], [[A]] ; CHECK-NEXT: ret i1 [[TMP2]] ; %1 = icmp eq i64 %b, 0 @@ -2632,9 +2854,10 @@ define i1 @or_icmp_eq_B_0_icmp_ult_A_B(i64 %a, i64 %b) { } define i1 @or_icmp_eq_B_0_icmp_ult_A_B_logical(i64 %a, i64 %b) { -; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B_logical( -; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[A:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B:%.*]], -1 +; CHECK-LABEL: define i1 @or_icmp_eq_B_0_icmp_ult_A_B_logical( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[A]] +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B]], -1 ; CHECK-NEXT: [[TMP3:%.*]] = icmp uge i64 [[TMP2]], [[TMP1]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2645,9 +2868,10 @@ define i1 @or_icmp_eq_B_0_icmp_ult_A_B_logical(i64 %a, i64 %b) { } define <2 x i1> @or_icmp_eq_B_0_icmp_ult_A_B_uniform(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B_uniform( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B:%.*]], splat (i64 -1) -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge <2 x i64> [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define <2 x i1> @or_icmp_eq_B_0_icmp_ult_A_B_uniform( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B]], splat (i64 -1) +; CHECK-NEXT: [[TMP2:%.*]] = icmp uge <2 x i64> [[TMP1]], [[A]] ; CHECK-NEXT: ret <2 x i1> [[TMP2]] ; %1 = icmp eq <2 x i64> %b, zeroinitializer @@ -2657,9 +2881,10 @@ define <2 x i1> @or_icmp_eq_B_0_icmp_ult_A_B_uniform(<2 x i64> %a, <2 x i64> %b) } define <2 x i1> @or_icmp_eq_B_0_icmp_ult_A_B_poison(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B_poison( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B:%.*]], splat (i64 -1) -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge <2 x i64> [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define <2 x i1> @or_icmp_eq_B_0_icmp_ult_A_B_poison( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B]], splat (i64 -1) +; CHECK-NEXT: [[TMP2:%.*]] = icmp uge <2 x i64> [[TMP1]], [[A]] ; CHECK-NEXT: ret <2 x i1> [[TMP2]] ; %1 = icmp eq <2 x i64> %b, <i64 0, i64 poison> @@ -2669,8 +2894,9 @@ define <2 x i1> @or_icmp_eq_B_0_icmp_ult_A_B_poison(<2 x i64> %a, <2 x i64> %b) } define i1 @or_icmp_ne_A_0_icmp_ne_B_0(i64 %a, i64 %b) { -; CHECK-LABEL: @or_icmp_ne_A_0_icmp_ne_B_0( -; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @or_icmp_ne_A_0_icmp_ne_B_0( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or i64 [[A]], [[B]] ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[TMP2]] ; @@ -2681,9 +2907,10 @@ define i1 @or_icmp_ne_A_0_icmp_ne_B_0(i64 %a, i64 %b) { } define i1 @or_icmp_ne_A_0_icmp_ne_B_0_logical(i64 %a, i64 %b) { -; CHECK-LABEL: @or_icmp_ne_A_0_icmp_ne_B_0_logical( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A:%.*]], 0 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B:%.*]], 0 +; CHECK-LABEL: define i1 @or_icmp_ne_A_0_icmp_ne_B_0_logical( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[A]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[B]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2694,8 +2921,9 @@ define i1 @or_icmp_ne_A_0_icmp_ne_B_0_logical(i64 %a, i64 %b) { } define <2 x i1> @or_icmp_ne_A_0_icmp_ne_B_0_uniform(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @or_icmp_ne_A_0_icmp_ne_B_0_uniform( -; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define <2 x i1> @or_icmp_ne_A_0_icmp_ne_B_0_uniform( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> [[A]], [[B]] ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[TMP2]] ; @@ -2706,8 +2934,9 @@ define <2 x i1> @or_icmp_ne_A_0_icmp_ne_B_0_uniform(<2 x i64> %a, <2 x i64> %b) } define <2 x i1> @or_icmp_ne_A_0_icmp_ne_B_0_poison(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @or_icmp_ne_A_0_icmp_ne_B_0_poison( -; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define <2 x i1> @or_icmp_ne_A_0_icmp_ne_B_0_poison( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i64> [[A]], [[B]] ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[TMP2]] ; @@ -2718,9 +2947,10 @@ define <2 x i1> @or_icmp_ne_A_0_icmp_ne_B_0_poison(<2 x i64> %a, <2 x i64> %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B( -; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B:%.*]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A]] ; CHECK-NEXT: ret i1 [[TMP2]] ; %1 = icmp ne i64 %b, 0 @@ -2730,9 +2960,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted1(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_commuted1( -; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B:%.*]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted1( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A]] ; CHECK-NEXT: ret i1 [[TMP2]] ; %1 = icmp uge i64 %a, %b @@ -2742,9 +2973,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted1(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted2(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_commuted2( -; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B:%.*]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted2( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A]] ; CHECK-NEXT: ret i1 [[TMP2]] ; %1 = icmp ne i64 %b, 0 @@ -2754,9 +2986,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted2(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted1_logical(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_commuted1_logical( -; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B:%.*]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted1_logical( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[B]], -1 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], [[A]] ; CHECK-NEXT: ret i1 [[TMP2]] ; %1 = icmp uge i64 %a, %b @@ -2766,9 +2999,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted1_logical(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted2_logical(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_commuted2_logical( -; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[A:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B:%.*]], -1 +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted2_logical( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[A]] +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B]], -1 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], [[TMP1]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2779,11 +3013,12 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_commuted2_logical(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use1(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_extra_use1( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B:%.*]], 0 +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use1( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B]], 0 ; CHECK-NEXT: call void @use_i1(i1 [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B]], -1 -; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], [[A:%.*]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], [[A]] ; CHECK-NEXT: ret i1 [[TMP3]] ; %1 = icmp ne i64 %b, 0 @@ -2794,8 +3029,9 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use1(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use2(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_extra_use2( -; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use2( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i64 [[A]], [[B]] ; CHECK-NEXT: call void @use_i1(i1 [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B]], -1 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], [[A]] @@ -2809,10 +3045,11 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use2(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use3(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_extra_use3( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B:%.*]], 0 +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use3( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B]], 0 ; CHECK-NEXT: call void @use_i1(i1 [[TMP1]]) -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A:%.*]], [[B]] +; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A]], [[B]] ; CHECK-NEXT: call void @use_i1(i1 [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret i1 [[TMP3]] @@ -2826,9 +3063,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_extra_use3(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred1(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred1( -; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[B:%.*]], 0 -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A:%.*]], [[B]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred1( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[B]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A]], [[B]] ; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2839,9 +3077,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred1(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred2(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred2( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B:%.*]], 0 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[A:%.*]], [[B]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred2( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i64 [[A]], [[B]] ; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2852,9 +3091,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_pred2(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op1(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op1( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B:%.*]], 1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A:%.*]], [[B]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op1( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A]], [[B]] ; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2865,9 +3105,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op1(i64 %a, i64 %b) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op2(i64 %a, i64 %b, i64 %c) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op2( -; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B:%.*]], 0 -; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A:%.*]], [[C:%.*]] +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op2( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = icmp uge i64 [[A]], [[C]] ; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2878,9 +3119,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_wrong_op2(i64 %a, i64 %b, i64 %c) { } define i1 @and_icmp_ne_B_0_icmp_uge_A_B_logical(i64 %a, i64 %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_logical( -; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[A:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B:%.*]], -1 +; CHECK-LABEL: define i1 @and_icmp_ne_B_0_icmp_uge_A_B_logical( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[A]] +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[B]], -1 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], [[TMP1]] ; CHECK-NEXT: ret i1 [[TMP3]] ; @@ -2891,9 +3133,10 @@ define i1 @and_icmp_ne_B_0_icmp_uge_A_B_logical(i64 %a, i64 %b) { } define <2 x i1> @and_icmp_ne_B_0_icmp_uge_A_B_uniform(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_uniform( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B:%.*]], splat (i64 -1) -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i64> [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define <2 x i1> @and_icmp_ne_B_0_icmp_uge_A_B_uniform( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B]], splat (i64 -1) +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i64> [[TMP1]], [[A]] ; CHECK-NEXT: ret <2 x i1> [[TMP2]] ; %1 = icmp ne <2 x i64> %b, zeroinitializer @@ -2903,9 +3146,10 @@ define <2 x i1> @and_icmp_ne_B_0_icmp_uge_A_B_uniform(<2 x i64> %a, <2 x i64> %b } define <2 x i1> @and_icmp_ne_B_0_icmp_uge_A_B_poison(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @and_icmp_ne_B_0_icmp_uge_A_B_poison( -; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B:%.*]], splat (i64 -1) -; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i64> [[TMP1]], [[A:%.*]] +; CHECK-LABEL: define <2 x i1> @and_icmp_ne_B_0_icmp_uge_A_B_poison( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i64> [[B]], splat (i64 -1) +; CHECK-NEXT: [[TMP2:%.*]] = icmp ult <2 x i64> [[TMP1]], [[A]] ; CHECK-NEXT: ret <2 x i1> [[TMP2]] ; %1 = icmp ne <2 x i64> %b, <i64 0, i64 poison> @@ -2915,8 +3159,9 @@ define <2 x i1> @and_icmp_ne_B_0_icmp_uge_A_B_poison(<2 x i64> %a, <2 x i64> %b) } define i1 @icmp_add_ult_2(i32 %X) { -; CHECK-LABEL: @icmp_add_ult_2( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2 +; CHECK-LABEL: define i1 @icmp_add_ult_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 14 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2926,8 +3171,9 @@ define i1 @icmp_add_ult_2(i32 %X) { } define <2 x i1> @icmp_add_X_-14_ult_2_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_add_X_-14_ult_2_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 -2) +; CHECK-LABEL: define <2 x i1> @icmp_add_X_-14_ult_2_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 -2) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], splat (i32 14) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -2937,8 +3183,9 @@ define <2 x i1> @icmp_add_X_-14_ult_2_vec(<2 x i32> %X) { } define i1 @icmp_sub_3_X_ult_2(i32 %X) { -; CHECK-LABEL: @icmp_sub_3_X_ult_2( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2 +; CHECK-LABEL: define i1 @icmp_sub_3_X_ult_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2948,8 +3195,9 @@ define i1 @icmp_sub_3_X_ult_2(i32 %X) { } define <2 x i1> @icmp_sub_3_X_ult_2_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_sub_3_X_ult_2_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 -2) +; CHECK-LABEL: define <2 x i1> @icmp_sub_3_X_ult_2_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 -2) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -2959,8 +3207,9 @@ define <2 x i1> @icmp_sub_3_X_ult_2_vec(<2 x i32> %X) { } define i1 @icmp_add_X_-14_uge_2(i32 %X) { -; CHECK-LABEL: @icmp_add_X_-14_uge_2( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2 +; CHECK-LABEL: define i1 @icmp_add_X_-14_uge_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], 14 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2970,8 +3219,9 @@ define i1 @icmp_add_X_-14_uge_2(i32 %X) { } define <2 x i1> @icmp_add_X_-14_uge_2_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_add_X_-14_uge_2_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 -2) +; CHECK-LABEL: define <2 x i1> @icmp_add_X_-14_uge_2_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 -2) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], splat (i32 14) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -2981,8 +3231,9 @@ define <2 x i1> @icmp_add_X_-14_uge_2_vec(<2 x i32> %X) { } define i1 @icmp_sub_3_X_uge_2(i32 %X) { -; CHECK-LABEL: @icmp_sub_3_X_uge_2( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2 +; CHECK-LABEL: define i1 @icmp_sub_3_X_uge_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -2992,8 +3243,9 @@ define i1 @icmp_sub_3_X_uge_2(i32 %X) { } define <2 x i1> @icmp_sub_3_X_uge_2_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_sub_3_X_uge_2_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 -2) +; CHECK-LABEL: define <2 x i1> @icmp_sub_3_X_uge_2_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 -2) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -3003,8 +3255,9 @@ define <2 x i1> @icmp_sub_3_X_uge_2_vec(<2 x i32> %X) { } define i1 @icmp_and_X_-16_eq-16(i32 %X) { -; CHECK-LABEL: @icmp_and_X_-16_eq-16( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -17 +; CHECK-LABEL: define i1 @icmp_and_X_-16_eq-16( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X]], -17 ; CHECK-NEXT: ret i1 [[CMP]] ; %and = and i32 %X, -16 @@ -3013,8 +3266,9 @@ define i1 @icmp_and_X_-16_eq-16(i32 %X) { } define <2 x i1> @icmp_and_X_-16_eq-16_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_and_X_-16_eq-16_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X:%.*]], splat (i32 -17) +; CHECK-LABEL: define <2 x i1> @icmp_and_X_-16_eq-16_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X]], splat (i32 -17) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %and = and <2 x i32> %X, <i32 -16, i32 -16> @@ -3023,8 +3277,9 @@ define <2 x i1> @icmp_and_X_-16_eq-16_vec(<2 x i32> %X) { } define i1 @icmp_and_X_-16_ne-16(i32 %X) { -; CHECK-LABEL: @icmp_and_X_-16_ne-16( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], -16 +; CHECK-LABEL: define i1 @icmp_and_X_-16_ne-16( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X]], -16 ; CHECK-NEXT: ret i1 [[CMP]] ; %and = and i32 %X, -16 @@ -3033,8 +3288,9 @@ define i1 @icmp_and_X_-16_ne-16(i32 %X) { } define <2 x i1> @icmp_and_X_-16_ne-16_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_and_X_-16_ne-16_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 -16) +; CHECK-LABEL: define <2 x i1> @icmp_and_X_-16_ne-16_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[X]], splat (i32 -16) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %and = and <2 x i32> %X, <i32 -16, i32 -16> @@ -3046,8 +3302,9 @@ define <2 x i1> @icmp_and_X_-16_ne-16_vec(<2 x i32> %X) { ; X | C == C --> X <=u C (when C+1 is PowerOf2). define i1 @or1_eq1(i32 %x) { -; CHECK-LABEL: @or1_eq1( -; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 2 +; CHECK-LABEL: define i1 @or1_eq1( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X]], 2 ; CHECK-NEXT: ret i1 [[T1]] ; %t0 = or i32 %x, 1 @@ -3056,8 +3313,9 @@ define i1 @or1_eq1(i32 %x) { } define <2 x i1> @or1_eq1_vec(<2 x i32> %x) { -; CHECK-LABEL: @or1_eq1_vec( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 2) +; CHECK-LABEL: define <2 x i1> @or1_eq1_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[T1]] ; %t0 = or <2 x i32> %x, splat (i32 1) @@ -3066,8 +3324,9 @@ define <2 x i1> @or1_eq1_vec(<2 x i32> %x) { } define <2 x i1> @or_eq_vec_nonsplat(<2 x i32> %x) { -; CHECK-LABEL: @or_eq_vec_nonsplat( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 -2, i32 -3> +; CHECK-LABEL: define <2 x i1> @or_eq_vec_nonsplat( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], <i32 -2, i32 -3> ; CHECK-NEXT: [[T1:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[T1]] ; @@ -3077,16 +3336,17 @@ define <2 x i1> @or_eq_vec_nonsplat(<2 x i32> %x) { } define void @or_eq_vec_multiple_nonsplat(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z, ptr %ptr0, ptr %ptr1, ptr %ptr2) { -; CHECK-LABEL: @or_eq_vec_multiple_nonsplat( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 -2, i32 -3> +; CHECK-LABEL: define void @or_eq_vec_multiple_nonsplat( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]], ptr [[PTR0:%.*]], ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], <i32 -2, i32 -3> ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i32> [[TMP1]], zeroinitializer -; CHECK-NEXT: store <2 x i1> [[CMP0]], ptr [[PTR0:%.*]], align 1 -; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[Y:%.*]], <i32 -2, i32 -3> +; CHECK-NEXT: store <2 x i1> [[CMP0]], ptr [[PTR0]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[Y]], <i32 -2, i32 -3> ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq <2 x i32> [[TMP2]], zeroinitializer -; CHECK-NEXT: store <2 x i1> [[CMP1]], ptr [[PTR1:%.*]], align 1 -; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[Z:%.*]], <i32 -2, i32 -3> +; CHECK-NEXT: store <2 x i1> [[CMP1]], ptr [[PTR1]], align 1 +; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[Z]], <i32 -2, i32 -3> ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq <2 x i32> [[TMP3]], zeroinitializer -; CHECK-NEXT: store <2 x i1> [[CMP2]], ptr [[PTR2:%.*]], align 1 +; CHECK-NEXT: store <2 x i1> [[CMP2]], ptr [[PTR2]], align 1 ; CHECK-NEXT: ret void ; %t0 = or <2 x i32> %x, <i32 1, i32 2> @@ -3105,13 +3365,14 @@ define void @or_eq_vec_multiple_nonsplat(<2 x i32> %x, <2 x i32> %y, <2 x i32> % ; Make sure use count of 1 doesn't matter define i1 @or1_eq1_multiple(i32 %x, i32 %y, i32 %z, ptr %ptr0, ptr %ptr1) { -; CHECK-LABEL: @or1_eq1_multiple( -; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[X:%.*]], 2 -; CHECK-NEXT: store i1 [[CMP1]], ptr [[PTR:%.*]], align 1 -; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[Y:%.*]], 2 -; CHECK-NEXT: store i1 [[CMP2]], ptr [[PTR1:%.*]], align 1 -; CHECK-NEXT: [[CMP3:%.*]] = icmp ult i32 [[Z:%.*]], 2 -; CHECK-NEXT: ret i1 [[CMP3]] +; CHECK-LABEL: define i1 @or1_eq1_multiple( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]], ptr [[PTR0:%.*]], ptr [[PTR1:%.*]]) { +; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i32 [[X]], 2 +; CHECK-NEXT: store i1 [[CMP0]], ptr [[PTR0]], align 1 +; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[Y]], 2 +; CHECK-NEXT: store i1 [[CMP1]], ptr [[PTR1]], align 1 +; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[Z]], 2 +; CHECK-NEXT: ret i1 [[CMP2]] ; %t0 = or i32 %x, 1 %cmp0 = icmp eq i32 %t0, 1 @@ -3127,12 +3388,13 @@ define i1 @or1_eq1_multiple(i32 %x, i32 %y, i32 %z, ptr %ptr0, ptr %ptr1) { } define <2 x i1> @or1_eq1_multiple_vec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z, ptr %ptr0, ptr %ptr1) { -; CHECK-LABEL: @or1_eq1_multiple_vec( -; CHECK-NEXT: [[CMP0:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 2) -; CHECK-NEXT: store <2 x i1> [[CMP0]], ptr [[PTR0:%.*]], align 1 -; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[Y:%.*]], splat (i32 2) -; CHECK-NEXT: store <2 x i1> [[CMP1]], ptr [[PTR1:%.*]], align 1 -; CHECK-NEXT: [[CMP2:%.*]] = icmp ult <2 x i32> [[Z:%.*]], splat (i32 2) +; CHECK-LABEL: define <2 x i1> @or1_eq1_multiple_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[Z:%.*]], ptr [[PTR0:%.*]], ptr [[PTR1:%.*]]) { +; CHECK-NEXT: [[CMP0:%.*]] = icmp ult <2 x i32> [[X]], splat (i32 2) +; CHECK-NEXT: store <2 x i1> [[CMP0]], ptr [[PTR0]], align 1 +; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[Y]], splat (i32 2) +; CHECK-NEXT: store <2 x i1> [[CMP1]], ptr [[PTR1]], align 1 +; CHECK-NEXT: [[CMP2:%.*]] = icmp ult <2 x i32> [[Z]], splat (i32 2) ; CHECK-NEXT: ret <2 x i1> [[CMP2]] ; %t0 = or <2 x i32> %x, splat (i32 1) @@ -3151,8 +3413,9 @@ define <2 x i1> @or1_eq1_multiple_vec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z, ; X | C == C --> X <=u C (when C+1 is PowerOf2). define <2 x i1> @or3_eq3_vec(<2 x i8> %x) { -; CHECK-LABEL: @or3_eq3_vec( -; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i8> [[X:%.*]], splat (i8 4) +; CHECK-LABEL: define <2 x i1> @or3_eq3_vec( +; CHECK-SAME: <2 x i8> [[X:%.*]]) { +; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i8> [[X]], splat (i8 4) ; CHECK-NEXT: ret <2 x i1> [[T1]] ; %t0 = or <2 x i8> %x, <i8 3, i8 3> @@ -3163,8 +3426,9 @@ define <2 x i1> @or3_eq3_vec(<2 x i8> %x) { ; X | C != C --> X >u C (when C+1 is PowerOf2). define i1 @or7_ne7(i32 %x) { -; CHECK-LABEL: @or7_ne7( -; CHECK-NEXT: [[T1:%.*]] = icmp ugt i32 [[X:%.*]], 7 +; CHECK-LABEL: define i1 @or7_ne7( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[T1:%.*]] = icmp ugt i32 [[X]], 7 ; CHECK-NEXT: ret i1 [[T1]] ; %t0 = or i32 %x, 7 @@ -3175,8 +3439,9 @@ define i1 @or7_ne7(i32 %x) { ; X | C != C --> X >u C (when C+1 is PowerOf2). define <2 x i1> @or63_ne63_vec(<2 x i8> %x) { -; CHECK-LABEL: @or63_ne63_vec( -; CHECK-NEXT: [[T1:%.*]] = icmp ugt <2 x i8> [[X:%.*]], splat (i8 63) +; CHECK-LABEL: define <2 x i1> @or63_ne63_vec( +; CHECK-SAME: <2 x i8> [[X:%.*]]) { +; CHECK-NEXT: [[T1:%.*]] = icmp ugt <2 x i8> [[X]], splat (i8 63) ; CHECK-NEXT: ret <2 x i1> [[T1]] ; %t0 = or <2 x i8> %x, <i8 63, i8 63> @@ -3188,8 +3453,9 @@ define <2 x i1> @or63_ne63_vec(<2 x i8> %x) { ; X | C == C --> (X & ~C) == 0 define i1 @orC_eqC(i32 %x) { -; CHECK-LABEL: @orC_eqC( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -43 +; CHECK-LABEL: define i1 @orC_eqC( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], -43 ; CHECK-NEXT: [[T1:%.*]] = icmp eq i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[T1]] ; @@ -3201,8 +3467,9 @@ define i1 @orC_eqC(i32 %x) { ; X | C == C --> (X & ~C) == 0 define <2 x i1> @orC_eqC_vec(<2 x i8> %x) { -; CHECK-LABEL: @orC_eqC_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], splat (i8 -44) +; CHECK-LABEL: define <2 x i1> @orC_eqC_vec( +; CHECK-SAME: <2 x i8> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X]], splat (i8 -44) ; CHECK-NEXT: [[T1:%.*]] = icmp eq <2 x i8> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[T1]] ; @@ -3214,8 +3481,9 @@ define <2 x i1> @orC_eqC_vec(<2 x i8> %x) { ; X | C != C --> (X & ~C) != 0 define i1 @orC_neC(i32 %x) { -; CHECK-LABEL: @orC_neC( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 41 +; CHECK-LABEL: define i1 @orC_neC( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], 41 ; CHECK-NEXT: [[T1:%.*]] = icmp ne i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[T1]] ; @@ -3227,8 +3495,9 @@ define i1 @orC_neC(i32 %x) { ; X | C != C --> (X & ~C) != 0 define <2 x i1> @orC_neC_vec(<2 x i8> %x) { -; CHECK-LABEL: @orC_neC_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], splat (i8 42) +; CHECK-LABEL: define <2 x i1> @orC_neC_vec( +; CHECK-SAME: <2 x i8> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X]], splat (i8 42) ; CHECK-NEXT: [[T1:%.*]] = icmp ne <2 x i8> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[T1]] ; @@ -3238,8 +3507,9 @@ define <2 x i1> @orC_neC_vec(<2 x i8> %x) { } define i1 @shrink_constant(i32 %X) { -; CHECK-LABEL: @shrink_constant( -; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], -12 +; CHECK-LABEL: define i1 @shrink_constant( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X]], -12 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[XOR]], 4 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -3249,8 +3519,9 @@ define i1 @shrink_constant(i32 %X) { } define <2 x i1> @shrink_constant_vec(<2 x i32> %X) { -; CHECK-LABEL: @shrink_constant_vec( -; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[X:%.*]], splat (i32 -12) +; CHECK-LABEL: define <2 x i1> @shrink_constant_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[X]], splat (i32 -12) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[XOR]], splat (i32 4) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -3261,8 +3532,9 @@ define <2 x i1> @shrink_constant_vec(<2 x i32> %X) { ; This test requires 3 different transforms to get to the result. define i1 @icmp_sub_-1_X_ult_4(i32 %X) { -; CHECK-LABEL: @icmp_sub_-1_X_ult_4( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X:%.*]], -5 +; CHECK-LABEL: define i1 @icmp_sub_-1_X_ult_4( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[X]], -5 ; CHECK-NEXT: ret i1 [[CMP]] ; %sub = sub i32 -1, %X @@ -3271,8 +3543,9 @@ define i1 @icmp_sub_-1_X_ult_4(i32 %X) { } define <2 x i1> @icmp_xor_neg4_X_ult_4_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_xor_neg4_X_ult_4_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X:%.*]], splat (i32 -5) +; CHECK-LABEL: define <2 x i1> @icmp_xor_neg4_X_ult_4_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X]], splat (i32 -5) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %xor = xor <2 x i32> %X, <i32 -4, i32 -4> @@ -3281,8 +3554,9 @@ define <2 x i1> @icmp_xor_neg4_X_ult_4_vec(<2 x i32> %X) { } define i1 @icmp_sub_-1_X_uge_4(i32 %X) { -; CHECK-LABEL: @icmp_sub_-1_X_uge_4( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], -4 +; CHECK-LABEL: define i1 @icmp_sub_-1_X_uge_4( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X]], -4 ; CHECK-NEXT: ret i1 [[CMP]] ; %sub = sub i32 -1, %X @@ -3291,8 +3565,9 @@ define i1 @icmp_sub_-1_X_uge_4(i32 %X) { } define <2 x i1> @icmp_xor_neg4_X_uge_4_vec(<2 x i32> %X) { -; CHECK-LABEL: @icmp_xor_neg4_X_uge_4_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[X:%.*]], splat (i32 -4) +; CHECK-LABEL: define <2 x i1> @icmp_xor_neg4_X_uge_4_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[X]], splat (i32 -4) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %xor = xor <2 x i32> %X, <i32 -4, i32 -4> @@ -3301,8 +3576,9 @@ define <2 x i1> @icmp_xor_neg4_X_uge_4_vec(<2 x i32> %X) { } define <2 x i1> @xor_ult(<2 x i8> %x) { -; CHECK-LABEL: @xor_ult( -; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i8> [[X:%.*]], splat (i8 3) +; CHECK-LABEL: define <2 x i1> @xor_ult( +; CHECK-SAME: <2 x i8> [[X:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i8> [[X]], splat (i8 3) ; CHECK-NEXT: ret <2 x i1> [[R]] ; %xor = xor <2 x i8> %x, <i8 -4, i8 -4> @@ -3311,9 +3587,10 @@ define <2 x i1> @xor_ult(<2 x i8> %x) { } define i1 @xor_ult_extra_use(i8 %x, ptr %p) { -; CHECK-LABEL: @xor_ult_extra_use( -; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[X:%.*]], -32 -; CHECK-NEXT: store i8 [[XOR]], ptr [[P:%.*]], align 1 +; CHECK-LABEL: define i1 @xor_ult_extra_use( +; CHECK-SAME: i8 [[X:%.*]], ptr [[P:%.*]]) { +; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[X]], -32 +; CHECK-NEXT: store i8 [[XOR]], ptr [[P]], align 1 ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], 31 ; CHECK-NEXT: ret i1 [[R]] ; @@ -3324,8 +3601,9 @@ define i1 @xor_ult_extra_use(i8 %x, ptr %p) { } define <2 x i1> @xor_ugt(<2 x i8> %x) { -; CHECK-LABEL: @xor_ugt( -; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i8> [[X:%.*]], splat (i8 7) +; CHECK-LABEL: define <2 x i1> @xor_ugt( +; CHECK-SAME: <2 x i8> [[X:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i8> [[X]], splat (i8 7) ; CHECK-NEXT: ret <2 x i1> [[R]] ; %xor = xor <2 x i8> %x, <i8 7, i8 7> @@ -3334,9 +3612,10 @@ define <2 x i1> @xor_ugt(<2 x i8> %x) { } define i1 @xor_ugt_extra_use(i8 %x, ptr %p) { -; CHECK-LABEL: @xor_ugt_extra_use( -; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[X:%.*]], 63 -; CHECK-NEXT: store i8 [[XOR]], ptr [[P:%.*]], align 1 +; CHECK-LABEL: define i1 @xor_ugt_extra_use( +; CHECK-SAME: i8 [[X:%.*]], ptr [[P:%.*]]) { +; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[X]], 63 +; CHECK-NEXT: store i8 [[XOR]], ptr [[P]], align 1 ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[X]], 63 ; CHECK-NEXT: ret i1 [[R]] ; @@ -3347,8 +3626,9 @@ define i1 @xor_ugt_extra_use(i8 %x, ptr %p) { } define i1 @icmp_lshr_lshr_eq(i32 %a, i32 %b) { -; CHECK-LABEL: @icmp_lshr_lshr_eq( -; CHECK-NEXT: [[Z_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @icmp_lshr_lshr_eq( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[Z_UNSHIFTED:%.*]] = xor i32 [[A]], [[B]] ; CHECK-NEXT: [[Z:%.*]] = icmp ult i32 [[Z_UNSHIFTED]], 1073741824 ; CHECK-NEXT: ret i1 [[Z]] ; @@ -3359,8 +3639,9 @@ define i1 @icmp_lshr_lshr_eq(i32 %a, i32 %b) { } define i1 @icmp_ashr_ashr_ne(i32 %a, i32 %b) { -; CHECK-LABEL: @icmp_ashr_ashr_ne( -; CHECK-NEXT: [[Z_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @icmp_ashr_ashr_ne( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[Z_UNSHIFTED:%.*]] = xor i32 [[A]], [[B]] ; CHECK-NEXT: [[Z:%.*]] = icmp ugt i32 [[Z_UNSHIFTED]], 255 ; CHECK-NEXT: ret i1 [[Z]] ; @@ -3371,8 +3652,9 @@ define i1 @icmp_ashr_ashr_ne(i32 %a, i32 %b) { } define i1 @icmp_neg_cst_slt(i32 %a) { -; CHECK-LABEL: @icmp_neg_cst_slt( -; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], 10 +; CHECK-LABEL: define i1 @icmp_neg_cst_slt( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A]], 10 ; CHECK-NEXT: ret i1 [[TMP1]] ; %1 = sub nsw i32 0, %a @@ -3381,10 +3663,11 @@ define i1 @icmp_neg_cst_slt(i32 %a) { } define i1 @icmp_and_or_lshr(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_and_or_lshr( -; CHECK-NEXT: [[SHF1:%.*]] = shl nuw i32 1, [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_and_or_lshr( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[SHF1:%.*]] = shl nuw i32 1, [[Y]] ; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHF1]], 1 -; CHECK-NEXT: [[AND3:%.*]] = and i32 [[X:%.*]], [[OR2]] +; CHECK-NEXT: [[AND3:%.*]] = and i32 [[X]], [[OR2]] ; CHECK-NEXT: [[RET:%.*]] = icmp ne i32 [[AND3]], 0 ; CHECK-NEXT: ret i1 [[RET]] ; @@ -3396,10 +3679,11 @@ define i1 @icmp_and_or_lshr(i32 %x, i32 %y) { } define i1 @icmp_and_or_lshr_samesign(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_and_or_lshr_samesign( -; CHECK-NEXT: [[SHF1:%.*]] = shl nuw i32 1, [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_and_or_lshr_samesign( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[SHF1:%.*]] = shl nuw i32 1, [[Y]] ; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHF1]], 1 -; CHECK-NEXT: [[AND3:%.*]] = and i32 [[X:%.*]], [[OR2]] +; CHECK-NEXT: [[AND3:%.*]] = and i32 [[X]], [[OR2]] ; CHECK-NEXT: [[RET:%.*]] = icmp ne i32 [[AND3]], 0 ; CHECK-NEXT: ret i1 [[RET]] ; @@ -3411,8 +3695,9 @@ define i1 @icmp_and_or_lshr_samesign(i32 %x, i32 %y) { } define <2 x i1> @icmp_and_or_lshr_vec(<2 x i32> %x, <2 x i32> %y) { -; CHECK-LABEL: @icmp_and_or_lshr_vec( -; CHECK-NEXT: [[SHF:%.*]] = lshr <2 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[SHF:%.*]] = lshr <2 x i32> [[X]], [[Y]] ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[SHF]], [[X]] ; CHECK-NEXT: [[RET:%.*]] = trunc <2 x i32> [[OR]] to <2 x i1> ; CHECK-NEXT: ret <2 x i1> [[RET]] @@ -3425,9 +3710,10 @@ define <2 x i1> @icmp_and_or_lshr_vec(<2 x i32> %x, <2 x i32> %y) { } define <2 x i1> @icmp_and_or_lshr_vec_commute(<2 x i32> %xp, <2 x i32> %y) { -; CHECK-LABEL: @icmp_and_or_lshr_vec_commute( -; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP:%.*]], splat (i32 42) -; CHECK-NEXT: [[SHF:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]] +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_vec_commute( +; CHECK-SAME: <2 x i32> [[XP:%.*]], <2 x i32> [[Y:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP]], splat (i32 42) +; CHECK-NEXT: [[SHF:%.*]] = lshr <2 x i32> [[X]], [[Y]] ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[X]], [[SHF]] ; CHECK-NEXT: [[RET:%.*]] = trunc <2 x i32> [[OR]] to <2 x i1> ; CHECK-NEXT: ret <2 x i1> [[RET]] @@ -3441,8 +3727,9 @@ define <2 x i1> @icmp_and_or_lshr_vec_commute(<2 x i32> %xp, <2 x i32> %y) { } define i1 @icmp_and_or_lshr_cst(i32 %x) { -; CHECK-LABEL: @icmp_and_or_lshr_cst( -; CHECK-NEXT: [[AND1:%.*]] = and i32 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @icmp_and_or_lshr_cst( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[AND1:%.*]] = and i32 [[X]], 3 ; CHECK-NEXT: [[RET:%.*]] = icmp ne i32 [[AND1]], 0 ; CHECK-NEXT: ret i1 [[RET]] ; @@ -3454,8 +3741,9 @@ define i1 @icmp_and_or_lshr_cst(i32 %x) { } define <2 x i1> @icmp_and_or_lshr_cst_vec(<2 x i32> %x) { -; CHECK-LABEL: @icmp_and_or_lshr_cst_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 3) +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_cst_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] ; @@ -3467,8 +3755,9 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec(<2 x i32> %x) { } define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform(<2 x i32> %x) { -; CHECK-LABEL: @icmp_and_or_lshr_cst_vec_nonuniform( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 3, i32 5> +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], <i32 3, i32 5> ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] ; @@ -3480,8 +3769,9 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform(<2 x i32> %x) { } define <2 x i1> @icmp_and_or_lshr_cst_vec_poison(<2 x i32> %x) { -; CHECK-LABEL: @icmp_and_or_lshr_cst_vec_poison( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 3, i32 poison> +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_cst_vec_poison( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], <i32 3, i32 poison> ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] ; @@ -3493,8 +3783,9 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec_poison(<2 x i32> %x) { } define <2 x i1> @icmp_and_or_lshr_cst_vec_commute(<2 x i32> %xp) { -; CHECK-LABEL: @icmp_and_or_lshr_cst_vec_commute( -; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP:%.*]], splat (i32 42) +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_cst_vec_commute( +; CHECK-SAME: <2 x i32> [[XP:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP]], splat (i32 42) ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 3) ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] @@ -3508,8 +3799,9 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec_commute(<2 x i32> %xp) { } define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform_commute(<2 x i32> %xp) { -; CHECK-LABEL: @icmp_and_or_lshr_cst_vec_nonuniform_commute( -; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP:%.*]], splat (i32 42) +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform_commute( +; CHECK-SAME: <2 x i32> [[XP:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP]], splat (i32 42) ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], <i32 3, i32 5> ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] @@ -3523,8 +3815,9 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec_nonuniform_commute(<2 x i32> %xp) { } define <2 x i1> @icmp_and_or_lshr_cst_vec_poison_commute(<2 x i32> %xp) { -; CHECK-LABEL: @icmp_and_or_lshr_cst_vec_poison_commute( -; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP:%.*]], splat (i32 42) +; CHECK-LABEL: define <2 x i1> @icmp_and_or_lshr_cst_vec_poison_commute( +; CHECK-SAME: <2 x i32> [[XP:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = srem <2 x i32> [[XP]], splat (i32 42) ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], <i32 3, i32 poison> ; CHECK-NEXT: [[RET:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RET]] @@ -3538,8 +3831,9 @@ define <2 x i1> @icmp_and_or_lshr_cst_vec_poison_commute(<2 x i32> %xp) { } define i1 @shl_ap1_zero_ap2_non_zero_2(i32 %a) { -; CHECK-LABEL: @shl_ap1_zero_ap2_non_zero_2( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[A:%.*]], 29 +; CHECK-LABEL: define i1 @shl_ap1_zero_ap2_non_zero_2( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[A]], 29 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 4, %a @@ -3548,8 +3842,9 @@ define i1 @shl_ap1_zero_ap2_non_zero_2(i32 %a) { } define <2 x i1> @shl_ap1_zero_ap2_non_zero_2_vec(<2 x i32> %a) { -; CHECK-LABEL: @shl_ap1_zero_ap2_non_zero_2_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[A:%.*]], splat (i32 29) +; CHECK-LABEL: define <2 x i1> @shl_ap1_zero_ap2_non_zero_2_vec( +; CHECK-SAME: <2 x i32> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[A]], splat (i32 29) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shl = shl <2 x i32> <i32 4, i32 4>, %a @@ -3558,8 +3853,9 @@ define <2 x i1> @shl_ap1_zero_ap2_non_zero_2_vec(<2 x i32> %a) { } define <2 x i1> @shl_ap1_zero_ap2_non_zero_2_vec_nonuniform(<2 x i32> %a) { -; CHECK-LABEL: @shl_ap1_zero_ap2_non_zero_2_vec_nonuniform( -; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> <i32 4, i32 5>, [[A:%.*]] +; CHECK-LABEL: define <2 x i1> @shl_ap1_zero_ap2_non_zero_2_vec_nonuniform( +; CHECK-SAME: <2 x i32> [[A:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> <i32 4, i32 5>, [[A]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[SHL]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -3569,8 +3865,9 @@ define <2 x i1> @shl_ap1_zero_ap2_non_zero_2_vec_nonuniform(<2 x i32> %a) { } define i1 @shl_ap1_zero_ap2_non_zero_4(i32 %a) { -; CHECK-LABEL: @shl_ap1_zero_ap2_non_zero_4( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[A:%.*]], 30 +; CHECK-LABEL: define i1 @shl_ap1_zero_ap2_non_zero_4( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[A]], 30 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 -2, %a @@ -3579,8 +3876,9 @@ define i1 @shl_ap1_zero_ap2_non_zero_4(i32 %a) { } define i1 @shl_ap1_non_zero_ap2_non_zero_both_positive(i32 %a) { -; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_both_positive( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @shl_ap1_non_zero_ap2_non_zero_both_positive( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 50, %a @@ -3589,8 +3887,9 @@ define i1 @shl_ap1_non_zero_ap2_non_zero_both_positive(i32 %a) { } define i1 @shl_ap1_non_zero_ap2_non_zero_both_negative(i32 %a) { -; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_both_negative( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @shl_ap1_non_zero_ap2_non_zero_both_negative( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 -50, %a @@ -3599,7 +3898,8 @@ define i1 @shl_ap1_non_zero_ap2_non_zero_both_negative(i32 %a) { } define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_1(i32 %a) { -; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_ap1_1( +; CHECK-LABEL: define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_1( +; CHECK-SAME: i32 [[A:%.*]]) { ; CHECK-NEXT: ret i1 false ; %shl = shl i32 50, %a @@ -3608,8 +3908,9 @@ define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_1(i32 %a) { } define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_2(i32 %a) { -; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_ap1_2( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 1 +; CHECK-LABEL: define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_2( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl i32 25, %a @@ -3618,7 +3919,8 @@ define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_2(i32 %a) { } define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_3(i32 %a) { -; CHECK-LABEL: @shl_ap1_non_zero_ap2_non_zero_ap1_3( +; CHECK-LABEL: define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_3( +; CHECK-SAME: i32 [[A:%.*]]) { ; CHECK-NEXT: ret i1 false ; %shl = shl i32 26, %a @@ -3627,8 +3929,9 @@ define i1 @shl_ap1_non_zero_ap2_non_zero_ap1_3(i32 %a) { } define i1 @icmp_sgt_zero_add_nsw(i32 %a) { -; CHECK-LABEL: @icmp_sgt_zero_add_nsw( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A:%.*]], -1 +; CHECK-LABEL: define i1 @icmp_sgt_zero_add_nsw( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; %add = add nsw i32 %a, 1 @@ -3637,8 +3940,9 @@ define i1 @icmp_sgt_zero_add_nsw(i32 %a) { } define i1 @icmp_sge_zero_add_nsw(i32 %a) { -; CHECK-LABEL: @icmp_sge_zero_add_nsw( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A:%.*]], -2 +; CHECK-LABEL: define i1 @icmp_sge_zero_add_nsw( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A]], -2 ; CHECK-NEXT: ret i1 [[CMP]] ; %add = add nsw i32 %a, 1 @@ -3647,8 +3951,9 @@ define i1 @icmp_sge_zero_add_nsw(i32 %a) { } define i1 @icmp_sle_zero_add_nsw(i32 %a) { -; CHECK-LABEL: @icmp_sle_zero_add_nsw( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @icmp_sle_zero_add_nsw( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %add = add nsw i32 %a, 1 @@ -3657,8 +3962,9 @@ define i1 @icmp_sle_zero_add_nsw(i32 %a) { } define zeroext i1 @icmp_cmpxchg_strong(ptr %sc, i32 %old_val, i32 %new_val) { -; CHECK-LABEL: @icmp_cmpxchg_strong( -; CHECK-NEXT: [[XCHG:%.*]] = cmpxchg ptr [[SC:%.*]], i32 [[OLD_VAL:%.*]], i32 [[NEW_VAL:%.*]] seq_cst seq_cst, align 4 +; CHECK-LABEL: define zeroext i1 @icmp_cmpxchg_strong( +; CHECK-SAME: ptr [[SC:%.*]], i32 [[OLD_VAL:%.*]], i32 [[NEW_VAL:%.*]]) { +; CHECK-NEXT: [[XCHG:%.*]] = cmpxchg ptr [[SC]], i32 [[OLD_VAL]], i32 [[NEW_VAL]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[ICMP:%.*]] = extractvalue { i32, i1 } [[XCHG]], 1 ; CHECK-NEXT: ret i1 [[ICMP]] ; @@ -3669,8 +3975,9 @@ define zeroext i1 @icmp_cmpxchg_strong(ptr %sc, i32 %old_val, i32 %new_val) { } define i1 @f1(i64 %a, i64 %b) { -; CHECK-LABEL: @f1( -; CHECK-NEXT: [[V:%.*]] = icmp sge i64 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @f1( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp sge i64 [[A]], [[B]] ; CHECK-NEXT: ret i1 [[V]] ; %t = sub nsw i64 %a, %b @@ -3679,8 +3986,9 @@ define i1 @f1(i64 %a, i64 %b) { } define <2 x i1> @f1_vec(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @f1_vec( -; CHECK-NEXT: [[V:%.*]] = icmp sge <2 x i64> [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define <2 x i1> @f1_vec( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp sge <2 x i64> [[A]], [[B]] ; CHECK-NEXT: ret <2 x i1> [[V]] ; %t = sub nsw <2 x i64> %a, %b @@ -3689,8 +3997,9 @@ define <2 x i1> @f1_vec(<2 x i64> %a, <2 x i64> %b) { } define i1 @f2(i64 %a, i64 %b) { -; CHECK-LABEL: @f2( -; CHECK-NEXT: [[V:%.*]] = icmp sgt i64 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @f2( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp sgt i64 [[A]], [[B]] ; CHECK-NEXT: ret i1 [[V]] ; %t = sub nsw i64 %a, %b @@ -3699,8 +4008,9 @@ define i1 @f2(i64 %a, i64 %b) { } define <2 x i1> @f2_vec(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @f2_vec( -; CHECK-NEXT: [[V:%.*]] = icmp sgt <2 x i64> [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define <2 x i1> @f2_vec( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp sgt <2 x i64> [[A]], [[B]] ; CHECK-NEXT: ret <2 x i1> [[V]] ; %t = sub nsw <2 x i64> %a, %b @@ -3709,8 +4019,9 @@ define <2 x i1> @f2_vec(<2 x i64> %a, <2 x i64> %b) { } define i1 @f3(i64 %a, i64 %b) { -; CHECK-LABEL: @f3( -; CHECK-NEXT: [[V:%.*]] = icmp slt i64 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @f3( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp slt i64 [[A]], [[B]] ; CHECK-NEXT: ret i1 [[V]] ; %t = sub nsw i64 %a, %b @@ -3719,8 +4030,9 @@ define i1 @f3(i64 %a, i64 %b) { } define <2 x i1> @f3_vec(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @f3_vec( -; CHECK-NEXT: [[V:%.*]] = icmp slt <2 x i64> [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define <2 x i1> @f3_vec( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp slt <2 x i64> [[A]], [[B]] ; CHECK-NEXT: ret <2 x i1> [[V]] ; %t = sub nsw <2 x i64> %a, %b @@ -3729,8 +4041,9 @@ define <2 x i1> @f3_vec(<2 x i64> %a, <2 x i64> %b) { } define i1 @f4(i64 %a, i64 %b) { -; CHECK-LABEL: @f4( -; CHECK-NEXT: [[V:%.*]] = icmp sle i64 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i1 @f4( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp sle i64 [[A]], [[B]] ; CHECK-NEXT: ret i1 [[V]] ; %t = sub nsw i64 %a, %b @@ -3739,8 +4052,9 @@ define i1 @f4(i64 %a, i64 %b) { } define <2 x i1> @f4_vec(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: @f4_vec( -; CHECK-NEXT: [[V:%.*]] = icmp sle <2 x i64> [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define <2 x i1> @f4_vec( +; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp sle <2 x i64> [[A]], [[B]] ; CHECK-NEXT: ret <2 x i1> [[V]] ; %t = sub nsw <2 x i64> %a, %b @@ -3749,9 +4063,10 @@ define <2 x i1> @f4_vec(<2 x i64> %a, <2 x i64> %b) { } define i32 @f5(i8 %a, i8 %b) { -; CHECK-LABEL: @f5( -; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32 -; CHECK-NEXT: [[CONV3:%.*]] = zext i8 [[B:%.*]] to i32 +; CHECK-LABEL: define i32 @f5( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A]] to i32 +; CHECK-NEXT: [[CONV3:%.*]] = zext i8 [[B]] to i32 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV3]] ; CHECK-NEXT: [[SUB7_SUB:%.*]] = call i32 @llvm.abs.i32(i32 [[SUB]], i1 true) ; CHECK-NEXT: ret i32 [[SUB7_SUB]] @@ -3766,8 +4081,9 @@ define i32 @f5(i8 %a, i8 %b) { } define i32 @f6(i32 %a, i32 %b) { -; CHECK-LABEL: @f6( -; CHECK-NEXT: [[CMP_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i32 @f6( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[CMP_UNSHIFTED:%.*]] = xor i32 [[A]], [[B]] ; CHECK-NEXT: [[CMP_MASK:%.*]] = and i32 [[CMP_UNSHIFTED]], 255 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CMP_MASK]], 0 ; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP]], i32 10000, i32 0 @@ -3783,8 +4099,9 @@ define i32 @f6(i32 %a, i32 %b) { } define i32 @f7(i32 %a, i32 %b) { -; CHECK-LABEL: @f7( -; CHECK-NEXT: [[CMP_NOT_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] +; CHECK-LABEL: define i32 @f7( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[CMP_NOT_UNSHIFTED:%.*]] = xor i32 [[A]], [[B]] ; CHECK-NEXT: [[CMP_NOT_MASK:%.*]] = and i32 [[CMP_NOT_UNSHIFTED]], 511 ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[CMP_NOT_MASK]], 0 ; CHECK-NEXT: [[S:%.*]] = select i1 [[CMP_NOT]], i32 0, i32 10000 @@ -3798,8 +4115,9 @@ define i32 @f7(i32 %a, i32 %b) { } define i1 @f8(i32 %val, i32 %lim) { -; CHECK-LABEL: @f8( -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[LIM:%.*]], 0 +; CHECK-LABEL: define i1 @f8( +; CHECK-SAME: i32 [[VAL:%.*]], i32 [[LIM:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[LIM]], 0 ; CHECK-NEXT: ret i1 [[R]] ; %lim.sub = add i32 %lim, -1 @@ -3809,8 +4127,9 @@ define i1 @f8(i32 %val, i32 %lim) { } define i1 @f9(i32 %val, i32 %lim) { -; CHECK-LABEL: @f9( -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[LIM:%.*]], 0 +; CHECK-LABEL: define i1 @f9( +; CHECK-SAME: i32 [[VAL:%.*]], i32 [[LIM:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[LIM]], 0 ; CHECK-NEXT: ret i1 [[R]] ; %lim.sub = sub i32 %lim, 1 @@ -3820,11 +4139,12 @@ define i1 @f9(i32 %val, i32 %lim) { } define i1 @f10(i16 %p) { -; CHECK-LABEL: @f10( +; CHECK-LABEL: define i1 @f10( +; CHECK-SAME: i16 [[P:%.*]]) { ; CHECK-NEXT: [[EXT1:%.*]] = zext i8 ptrtoint (ptr @f10 to i8) to i16 ; CHECK-NEXT: [[EXT2:%.*]] = zext i8 ptrtoint (ptr @f10 to i8) to i16 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw i16 [[EXT1]], [[EXT2]] -; CHECK-NEXT: [[CMP580:%.*]] = icmp ule i16 [[MUL]], [[P:%.*]] +; CHECK-NEXT: [[CMP580:%.*]] = icmp ule i16 [[MUL]], [[P]] ; CHECK-NEXT: ret i1 [[CMP580]] ; %ext1 = zext i8 ptrtoint (ptr @f10 to i8) to i16 @@ -3839,9 +4159,10 @@ define i1 @f10(i16 %p) { ; equivalent to one another. define i1 @cmp_sgt_rhs_dec(float %x, i32 %i) { -; CHECK-LABEL: @cmp_sgt_rhs_dec( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[I:%.*]], [[CONV]] +; CHECK-LABEL: define i1 @cmp_sgt_rhs_dec( +; CHECK-SAME: float [[X:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[I]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; %conv = fptosi float %x to i32 @@ -3851,9 +4172,10 @@ define i1 @cmp_sgt_rhs_dec(float %x, i32 %i) { } define i1 @cmp_sle_rhs_dec(float %x, i32 %i) { -; CHECK-LABEL: @cmp_sle_rhs_dec( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[I:%.*]], [[CONV]] +; CHECK-LABEL: define i1 @cmp_sle_rhs_dec( +; CHECK-SAME: float [[X:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[I]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; %conv = fptosi float %x to i32 @@ -3863,9 +4185,10 @@ define i1 @cmp_sle_rhs_dec(float %x, i32 %i) { } define i1 @cmp_sge_rhs_inc(float %x, i32 %i) { -; CHECK-LABEL: @cmp_sge_rhs_inc( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I:%.*]], [[CONV]] +; CHECK-LABEL: define i1 @cmp_sge_rhs_inc( +; CHECK-SAME: float [[X:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[I]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; %conv = fptosi float %x to i32 @@ -3875,9 +4198,10 @@ define i1 @cmp_sge_rhs_inc(float %x, i32 %i) { } define i1 @cmp_slt_rhs_inc(float %x, i32 %i) { -; CHECK-LABEL: @cmp_slt_rhs_inc( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[I:%.*]], [[CONV]] +; CHECK-LABEL: define i1 @cmp_slt_rhs_inc( +; CHECK-SAME: float [[X:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[I]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; %conv = fptosi float %x to i32 @@ -3887,9 +4211,10 @@ define i1 @cmp_slt_rhs_inc(float %x, i32 %i) { } define i1 @PR26407(i32 %x, i32 %y) { -; CHECK-LABEL: @PR26407( -; CHECK-NEXT: [[ADDX:%.*]] = add i32 [[X:%.*]], 2147483647 -; CHECK-NEXT: [[ADDY:%.*]] = add i32 [[Y:%.*]], 2147483647 +; CHECK-LABEL: define i1 @PR26407( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[ADDX:%.*]] = add i32 [[X]], 2147483647 +; CHECK-NEXT: [[ADDY:%.*]] = add i32 [[Y]], 2147483647 ; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[ADDX]], [[ADDY]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -3900,8 +4225,9 @@ define i1 @PR26407(i32 %x, i32 %y) { } define i1 @cmp_inverse_mask_bits_set_eq(i32 %x) { -; CHECK-LABEL: @cmp_inverse_mask_bits_set_eq( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -43 +; CHECK-LABEL: define i1 @cmp_inverse_mask_bits_set_eq( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], -43 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], -43 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -3911,8 +4237,9 @@ define i1 @cmp_inverse_mask_bits_set_eq(i32 %x) { } define <2 x i1> @cmp_inverse_mask_bits_set_eq_vec(<2 x i32> %x) { -; CHECK-LABEL: @cmp_inverse_mask_bits_set_eq_vec( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 -43) +; CHECK-LABEL: define <2 x i1> @cmp_inverse_mask_bits_set_eq_vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X]], splat (i32 -43) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], splat (i32 -43) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -3922,8 +4249,9 @@ define <2 x i1> @cmp_inverse_mask_bits_set_eq_vec(<2 x i32> %x) { } define i1 @cmp_inverse_mask_bits_set_ne(i32 %x) { -; CHECK-LABEL: @cmp_inverse_mask_bits_set_ne( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -43 +; CHECK-LABEL: define i1 @cmp_inverse_mask_bits_set_ne( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X]], -43 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], -43 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -3935,8 +4263,9 @@ define i1 @cmp_inverse_mask_bits_set_ne(i32 %x) { ; When canonicalizing to 'gt/lt', make sure the constant is correct. define i1 @PR27792(i128 %a) { -; CHECK-LABEL: @PR27792( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i128 [[A:%.*]], -1 +; CHECK-LABEL: define i1 @PR27792( +; CHECK-SAME: i128 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i128 [[A]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; %cmp = icmp sge i128 %a, 0 @@ -3944,8 +4273,9 @@ define i1 @PR27792(i128 %a) { } define i1 @PR27792_2(i128 %a) { -; CHECK-LABEL: @PR27792_2( -; CHECK-NEXT: [[B:%.*]] = icmp ne i128 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @PR27792_2( +; CHECK-SAME: i128 [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = icmp ne i128 [[A]], 0 ; CHECK-NEXT: ret i1 [[B]] ; %b = icmp uge i128 %a, 1 @@ -3953,8 +4283,9 @@ define i1 @PR27792_2(i128 %a) { } define i1 @ugtMaxSignedVal(i8 %a) { -; CHECK-LABEL: @ugtMaxSignedVal( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @ugtMaxSignedVal( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %cmp = icmp ugt i8 %a, 127 @@ -3962,8 +4293,9 @@ define i1 @ugtMaxSignedVal(i8 %a) { } define <2 x i1> @ugtMaxSignedValVec(<2 x i8> %a) { -; CHECK-LABEL: @ugtMaxSignedValVec( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @ugtMaxSignedValVec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %cmp = icmp ugt <2 x i8> %a, <i8 127, i8 127> @@ -3971,8 +4303,9 @@ define <2 x i1> @ugtMaxSignedValVec(<2 x i8> %a) { } define i1 @ugtKnownBits(i8 %a) { -; CHECK-LABEL: @ugtKnownBits( -; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 17 +; CHECK-LABEL: define i1 @ugtKnownBits( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = and i8 [[A]], 17 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[B]], 17 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -3982,8 +4315,9 @@ define i1 @ugtKnownBits(i8 %a) { } define <2 x i1> @ugtKnownBitsVec(<2 x i8> %a) { -; CHECK-LABEL: @ugtKnownBitsVec( -; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[A:%.*]], splat (i8 17) +; CHECK-LABEL: define <2 x i1> @ugtKnownBitsVec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[A]], splat (i8 17) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[B]], splat (i8 17) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -3993,9 +4327,10 @@ define <2 x i1> @ugtKnownBitsVec(<2 x i8> %a) { } define i1 @or_ptrtoint_mismatch(ptr %p, ptr %q) { -; CHECK-LABEL: @or_ptrtoint_mismatch( -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[P:%.*]], null -; CHECK-NEXT: [[TMP2:%.*]] = icmp eq ptr [[Q:%.*]], null +; CHECK-LABEL: define i1 @or_ptrtoint_mismatch( +; CHECK-SAME: ptr [[P:%.*]], ptr [[Q:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq ptr [[P]], null +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq ptr [[Q]], null ; CHECK-NEXT: [[B:%.*]] = and i1 [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret i1 [[B]] ; @@ -4008,8 +4343,9 @@ define i1 @or_ptrtoint_mismatch(ptr %p, ptr %q) { } define i1 @icmp_add1_ugt(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_add1_ugt( -; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_add1_ugt( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %add = add nuw i32 %x, 1 @@ -4018,8 +4354,9 @@ define i1 @icmp_add1_ugt(i32 %x, i32 %y) { } define i1 @icmp_add1_ule(i32 %x, i32 %y) { -; CHECK-LABEL: @icmp_add1_ule( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @icmp_add1_ule( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %add = add nuw i32 %x, 1 @@ -4028,9 +4365,10 @@ define i1 @icmp_add1_ule(i32 %x, i32 %y) { } define i1 @cmp_uge_rhs_inc(float %x, i32 %i) { -; CHECK-LABEL: @cmp_uge_rhs_inc( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[I:%.*]], [[CONV]] +; CHECK-LABEL: define i1 @cmp_uge_rhs_inc( +; CHECK-SAME: float [[X:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[I]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; %conv = fptosi float %x to i32 @@ -4040,9 +4378,10 @@ define i1 @cmp_uge_rhs_inc(float %x, i32 %i) { } define i1 @cmp_ult_rhs_inc(float %x, i32 %i) { -; CHECK-LABEL: @cmp_ult_rhs_inc( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[I:%.*]], [[CONV]] +; CHECK-LABEL: define i1 @cmp_ult_rhs_inc( +; CHECK-SAME: float [[X:%.*]], i32 [[I:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[I]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; %conv = fptosi float %x to i32 @@ -4052,9 +4391,10 @@ define i1 @cmp_ult_rhs_inc(float %x, i32 %i) { } define i1 @cmp_sge_lhs_inc(i32 %x, i32 %y) { -; CHECK-LABEL: @cmp_sge_lhs_inc( -; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[INC]], [[Y:%.*]] +; CHECK-LABEL: define i1 @cmp_sge_lhs_inc( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[X]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[INC]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %inc = add nsw i32 %x, 1 @@ -4063,9 +4403,10 @@ define i1 @cmp_sge_lhs_inc(i32 %x, i32 %y) { } define i1 @cmp_uge_lhs_inc(i32 %x, i32 %y) { -; CHECK-LABEL: @cmp_uge_lhs_inc( -; CHECK-NEXT: [[INC:%.*]] = add nuw i32 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[INC]], [[Y:%.*]] +; CHECK-LABEL: define i1 @cmp_uge_lhs_inc( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[INC:%.*]] = add nuw i32 [[X]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[INC]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %inc = add nuw i32 %x, 1 @@ -4074,9 +4415,10 @@ define i1 @cmp_uge_lhs_inc(i32 %x, i32 %y) { } define i1 @cmp_sgt_lhs_dec(i32 %x, i32 %y) { -; CHECK-LABEL: @cmp_sgt_lhs_dec( -; CHECK-NEXT: [[DEC:%.*]] = add nsw i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[DEC]], [[Y:%.*]] +; CHECK-LABEL: define i1 @cmp_sgt_lhs_dec( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[DEC:%.*]] = add nsw i32 [[X]], -1 +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[DEC]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %dec = sub nsw i32 %x, 1 @@ -4085,9 +4427,10 @@ define i1 @cmp_sgt_lhs_dec(i32 %x, i32 %y) { } define i1 @cmp_ugt_lhs_dec(i32 %x, i32 %y) { -; CHECK-LABEL: @cmp_ugt_lhs_dec( -; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[DEC]], [[Y:%.*]] +; CHECK-LABEL: define i1 @cmp_ugt_lhs_dec( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X]], -1 +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[DEC]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %dec = sub nuw i32 %x, 1 @@ -4096,9 +4439,10 @@ define i1 @cmp_ugt_lhs_dec(i32 %x, i32 %y) { } define i1 @cmp_sle_rhs_inc(float %x, i32 %y) { -; CHECK-LABEL: @cmp_sle_rhs_inc( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[Y:%.*]], 1 +; CHECK-LABEL: define i1 @cmp_sle_rhs_inc( +; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[Y]], 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[INC]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -4109,9 +4453,10 @@ define i1 @cmp_sle_rhs_inc(float %x, i32 %y) { } define i1 @cmp_ule_rhs_inc(float %x, i32 %y) { -; CHECK-LABEL: @cmp_ule_rhs_inc( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[INC:%.*]] = add nuw i32 [[Y:%.*]], 1 +; CHECK-LABEL: define i1 @cmp_ule_rhs_inc( +; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[INC:%.*]] = add nuw i32 [[Y]], 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[INC]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -4122,9 +4467,10 @@ define i1 @cmp_ule_rhs_inc(float %x, i32 %y) { } define i1 @cmp_slt_rhs_dec(float %x, i32 %y) { -; CHECK-LABEL: @cmp_slt_rhs_dec( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[DEC:%.*]] = add nsw i32 [[Y:%.*]], -1 +; CHECK-LABEL: define i1 @cmp_slt_rhs_dec( +; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[DEC:%.*]] = add nsw i32 [[Y]], -1 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[DEC]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -4135,9 +4481,10 @@ define i1 @cmp_slt_rhs_dec(float %x, i32 %y) { } define i1 @cmp_ult_rhs_dec(float %x, i32 %y) { -; CHECK-LABEL: @cmp_ult_rhs_dec( -; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X:%.*]] to i32 -; CHECK-NEXT: [[DEC:%.*]] = add i32 [[Y:%.*]], -1 +; CHECK-LABEL: define i1 @cmp_ult_rhs_dec( +; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CONV:%.*]] = fptosi float [[X]] to i32 +; CHECK-NEXT: [[DEC:%.*]] = add i32 [[Y]], -1 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[DEC]], [[CONV]] ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -4148,8 +4495,9 @@ define i1 @cmp_ult_rhs_dec(float %x, i32 %y) { } define i1 @eq_add_constants(i32 %x, i32 %y) { -; CHECK-LABEL: @eq_add_constants( -; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @eq_add_constants( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[C]] ; %A = add i32 %x, 5 @@ -4161,8 +4509,9 @@ define i1 @eq_add_constants(i32 %x, i32 %y) { declare i32 @llvm.bswap.i32(i32) define i1 @bswap_ne(i32 %x, i32 %y) { -; CHECK-LABEL: @bswap_ne( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @bswap_ne( +; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %swapx = call i32 @llvm.bswap.i32(i32 %x) @@ -4174,8 +4523,9 @@ define i1 @bswap_ne(i32 %x, i32 %y) { declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>) define <8 x i1> @bswap_vec_eq(<8 x i16> %x, <8 x i16> %y) { -; CHECK-LABEL: @bswap_vec_eq( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define <8 x i1> @bswap_vec_eq( +; CHECK-SAME: <8 x i16> [[X:%.*]], <8 x i16> [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <8 x i16> [[X]], [[Y]] ; CHECK-NEXT: ret <8 x i1> [[CMP]] ; %swapx = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %x) @@ -4187,8 +4537,9 @@ define <8 x i1> @bswap_vec_eq(<8 x i16> %x, <8 x i16> %y) { declare i64 @llvm.bitreverse.i64(i64) define i1 @bitreverse_eq(i64 %x, i64 %y) { -; CHECK-LABEL: @bitreverse_eq( -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define i1 @bitreverse_eq( +; CHECK-SAME: i64 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X]], [[Y]] ; CHECK-NEXT: ret i1 [[CMP]] ; %revx = call i64 @llvm.bitreverse.i64(i64 %x) @@ -4200,8 +4551,9 @@ define i1 @bitreverse_eq(i64 %x, i64 %y) { declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>) define <8 x i1> @bitreverse_vec_ne(<8 x i16> %x, <8 x i16> %y) { -; CHECK-LABEL: @bitreverse_vec_ne( -; CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i16> [[X:%.*]], [[Y:%.*]] +; CHECK-LABEL: define <8 x i1> @bitreverse_vec_ne( +; CHECK-SAME: <8 x i16> [[X:%.*]], <8 x i16> [[Y:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <8 x i16> [[X]], [[Y]] ; CHECK-NEXT: ret <8 x i1> [[CMP]] ; %revx = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %x) @@ -4213,9 +4565,10 @@ define <8 x i1> @bitreverse_vec_ne(<8 x i16> %x, <8 x i16> %y) { ; These perform a comparison of a value known to be between 4 and 5 with a value between 5 and 7. ; They should all simplify to equality compares. define i1 @knownbits1(i8 %a, i8 %b) { -; CHECK-LABEL: @knownbits1( -; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1 -; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2 +; CHECK-LABEL: define i1 @knownbits1( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and i8 [[A]], 1 +; CHECK-NEXT: [[B1:%.*]] = and i8 [[B]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A1]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] @@ -4229,9 +4582,10 @@ define i1 @knownbits1(i8 %a, i8 %b) { } define i1 @knownbits2(i8 %a, i8 %b) { -; CHECK-LABEL: @knownbits2( -; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1 -; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2 +; CHECK-LABEL: define i1 @knownbits2( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and i8 [[A]], 1 +; CHECK-NEXT: [[B1:%.*]] = and i8 [[B]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1 ; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A1]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] @@ -4245,9 +4599,10 @@ define i1 @knownbits2(i8 %a, i8 %b) { } define i1 @knownbits3(i8 %a, i8 %b) { -; CHECK-LABEL: @knownbits3( -; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], 1 -; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2 +; CHECK-LABEL: define i1 @knownbits3( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and i8 [[A]], 1 +; CHECK-NEXT: [[B1:%.*]] = and i8 [[B]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[TMP1]], [[A1]] ; CHECK-NEXT: ret i1 [[C]] @@ -4261,9 +4616,10 @@ define i1 @knownbits3(i8 %a, i8 %b) { } define <2 x i1> @knownbits4(<2 x i8> %a, <2 x i8> %b) { -; CHECK-LABEL: @knownbits4( -; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], splat (i8 1) -; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], splat (i8 2) +; CHECK-LABEL: define <2 x i1> @knownbits4( +; CHECK-SAME: <2 x i8> [[A:%.*]], <2 x i8> [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A]], splat (i8 1) +; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B]], splat (i8 2) ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint <2 x i8> [[B1]], splat (i8 1) ; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i8> [[TMP1]], [[A1]] ; CHECK-NEXT: ret <2 x i1> [[C]] @@ -4279,9 +4635,10 @@ define <2 x i1> @knownbits4(<2 x i8> %a, <2 x i8> %b) { ; These are the signed versions of the above. One value is less than or equal to 5, but maybe negative. ; The other is known to be a value 5-7. These should simplify to equality comparisons. define i1 @knownbits5(i8 %a, i8 %b) { -; CHECK-LABEL: @knownbits5( -; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127 -; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2 +; CHECK-LABEL: define i1 @knownbits5( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and i8 [[A]], -127 +; CHECK-NEXT: [[B1:%.*]] = and i8 [[B]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1 ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A1]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] @@ -4295,9 +4652,10 @@ define i1 @knownbits5(i8 %a, i8 %b) { } define i1 @knownbits6(i8 %a, i8 %b) { -; CHECK-LABEL: @knownbits6( -; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127 -; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2 +; CHECK-LABEL: define i1 @knownbits6( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and i8 [[A]], -127 +; CHECK-NEXT: [[B1:%.*]] = and i8 [[B]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1 ; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A1]], [[TMP1]] ; CHECK-NEXT: ret i1 [[C]] @@ -4311,9 +4669,10 @@ define i1 @knownbits6(i8 %a, i8 %b) { } define <2 x i1> @knownbits7(<2 x i8> %a, <2 x i8> %b) { -; CHECK-LABEL: @knownbits7( -; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A:%.*]], splat (i8 -127) -; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B:%.*]], splat (i8 2) +; CHECK-LABEL: define <2 x i1> @knownbits7( +; CHECK-SAME: <2 x i8> [[A:%.*]], <2 x i8> [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and <2 x i8> [[A]], splat (i8 -127) +; CHECK-NEXT: [[B1:%.*]] = and <2 x i8> [[B]], splat (i8 2) ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint <2 x i8> [[B1]], splat (i8 1) ; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i8> [[TMP1]], [[A1]] ; CHECK-NEXT: ret <2 x i1> [[C]] @@ -4327,9 +4686,10 @@ define <2 x i1> @knownbits7(<2 x i8> %a, <2 x i8> %b) { } define i1 @knownbits8(i8 %a, i8 %b) { -; CHECK-LABEL: @knownbits8( -; CHECK-NEXT: [[A1:%.*]] = and i8 [[A:%.*]], -127 -; CHECK-NEXT: [[B1:%.*]] = and i8 [[B:%.*]], 2 +; CHECK-LABEL: define i1 @knownbits8( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = and i8 [[A]], -127 +; CHECK-NEXT: [[B1:%.*]] = and i8 [[B]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i8 [[B1]], 1 ; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[TMP1]], [[A1]] ; CHECK-NEXT: ret i1 [[C]] @@ -4344,8 +4704,9 @@ define i1 @knownbits8(i8 %a, i8 %b) { ; Make sure InstCombine doesn't try too hard to simplify the icmp and break the abs idiom define i32 @abs_preserve(i32 %x) { -; CHECK-LABEL: @abs_preserve( -; CHECK-NEXT: [[A:%.*]] = shl nsw i32 [[X:%.*]], 1 +; CHECK-LABEL: define i32 @abs_preserve( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = shl nsw i32 [[X]], 1 ; CHECK-NEXT: [[ABS:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false) ; CHECK-NEXT: ret i32 [[ABS]] ; @@ -4360,8 +4721,9 @@ define i32 @abs_preserve(i32 %x) { declare void @llvm.assume(i1) define i1 @PR35794(ptr %a) { -; CHECK-LABEL: @PR35794( -; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq ptr [[A:%.*]], null +; CHECK-LABEL: define i1 @PR35794( +; CHECK-SAME: ptr [[A:%.*]]) { +; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq ptr [[A]], null ; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) ; CHECK-NEXT: ret i1 true ; @@ -4373,8 +4735,9 @@ define i1 @PR35794(ptr %a) { ; Don't crash by assuming the compared values are integers. define <2 x i1> @PR36583(<2 x ptr>) { -; CHECK-LABEL: @PR36583( -; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x ptr> [[TMP0:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @PR36583( +; CHECK-SAME: <2 x ptr> [[TMP0:%.*]]) { +; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x ptr> [[TMP0]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[RES]] ; %cast = ptrtoint <2 x ptr> %0 to <2 x i64> @@ -4384,8 +4747,9 @@ define <2 x i1> @PR36583(<2 x ptr>) { ; fold (icmp pred (sub (0, X)) C1) for vec type define <2 x i32> @Op1Negated_Vec(<2 x i32> %x) { -; CHECK-LABEL: @Op1Negated_Vec( -; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true) +; CHECK-LABEL: define <2 x i32> @Op1Negated_Vec( +; CHECK-SAME: <2 x i32> [[X:%.*]]) { +; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X]], i1 true) ; CHECK-NEXT: ret <2 x i32> [[COND]] ; %sub = sub nsw <2 x i32> zeroinitializer, %x @@ -4395,8 +4759,9 @@ define <2 x i32> @Op1Negated_Vec(<2 x i32> %x) { } define i1 @signbit_bitcast_fpext(float %x) { -; CHECK-LABEL: @signbit_bitcast_fpext( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[X:%.*]] to i32 +; CHECK-LABEL: define i1 @signbit_bitcast_fpext( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[R]] ; @@ -4407,8 +4772,9 @@ define i1 @signbit_bitcast_fpext(float %x) { } define <2 x i1> @signbit_bitcast_fpext_vec(<2 x half> %x) { -; CHECK-LABEL: @signbit_bitcast_fpext_vec( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[X:%.*]] to <2 x i16> +; CHECK-LABEL: define <2 x i1> @signbit_bitcast_fpext_vec( +; CHECK-SAME: <2 x half> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[X]] to <2 x i16> ; CHECK-NEXT: [[R:%.*]] = icmp slt <2 x i16> [[TMP1]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -4419,8 +4785,9 @@ define <2 x i1> @signbit_bitcast_fpext_vec(<2 x half> %x) { } define i1 @signbit_bitcast_fptrunc(float %x) { -; CHECK-LABEL: @signbit_bitcast_fptrunc( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[X:%.*]] to i32 +; CHECK-LABEL: define i1 @signbit_bitcast_fptrunc( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[TMP1]], -1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -4431,8 +4798,9 @@ define i1 @signbit_bitcast_fptrunc(float %x) { } define <2 x i1> @signbit_bitcast_fptrunc_vec(<2 x double> %x) { -; CHECK-LABEL: @signbit_bitcast_fptrunc_vec( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[X:%.*]] to <2 x i64> +; CHECK-LABEL: define <2 x i1> @signbit_bitcast_fptrunc_vec( +; CHECK-SAME: <2 x double> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[X]] to <2 x i64> ; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i64> [[TMP1]], splat (i64 -1) ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -4443,8 +4811,9 @@ define <2 x i1> @signbit_bitcast_fptrunc_vec(<2 x double> %x) { } define i1 @signbit_bitcast_fpext_wrong_cmp(float %x) { -; CHECK-LABEL: @signbit_bitcast_fpext_wrong_cmp( -; CHECK-NEXT: [[F:%.*]] = fpext float [[X:%.*]] to double +; CHECK-LABEL: define i1 @signbit_bitcast_fpext_wrong_cmp( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[F:%.*]] = fpext float [[X]] to double ; CHECK-NEXT: [[B:%.*]] = bitcast double [[F]] to i64 ; CHECK-NEXT: [[R:%.*]] = icmp slt i64 [[B]], 1 ; CHECK-NEXT: ret i1 [[R]] @@ -4456,8 +4825,9 @@ define i1 @signbit_bitcast_fpext_wrong_cmp(float %x) { } define <4 x i1> @signbit_bitcast_fpext_vec_wrong_bitcast(<2 x half> %x) { -; CHECK-LABEL: @signbit_bitcast_fpext_vec_wrong_bitcast( -; CHECK-NEXT: [[F:%.*]] = fpext <2 x half> [[X:%.*]] to <2 x float> +; CHECK-LABEL: define <4 x i1> @signbit_bitcast_fpext_vec_wrong_bitcast( +; CHECK-SAME: <2 x half> [[X:%.*]]) { +; CHECK-NEXT: [[F:%.*]] = fpext <2 x half> [[X]] to <2 x float> ; CHECK-NEXT: [[B:%.*]] = bitcast <2 x float> [[F]] to <4 x i16> ; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i16> [[B]], splat (i16 -1) ; CHECK-NEXT: ret <4 x i1> [[R]] @@ -4469,8 +4839,9 @@ define <4 x i1> @signbit_bitcast_fpext_vec_wrong_bitcast(<2 x half> %x) { } define i1 @signbit_bitcast_fpext_extra_use(float %x, ptr %p) { -; CHECK-LABEL: @signbit_bitcast_fpext_extra_use( -; CHECK-NEXT: [[F:%.*]] = fpext float [[X:%.*]] to double +; CHECK-LABEL: define i1 @signbit_bitcast_fpext_extra_use( +; CHECK-SAME: float [[X:%.*]], ptr [[P:%.*]]) { +; CHECK-NEXT: [[F:%.*]] = fpext float [[X]] to double ; CHECK-NEXT: [[B:%.*]] = bitcast double [[F]] to i64 ; CHECK-NEXT: call void @use_i64(i64 [[B]]) ; CHECK-NEXT: [[R:%.*]] = icmp slt i64 [[B]], 0 @@ -4484,8 +4855,9 @@ define i1 @signbit_bitcast_fpext_extra_use(float %x, ptr %p) { } define i1 @signbit_bitcast_fpext_ppc_fp128(float %x) { -; CHECK-LABEL: @signbit_bitcast_fpext_ppc_fp128( -; CHECK-NEXT: [[S2:%.*]] = fpext float [[X:%.*]] to ppc_fp128 +; CHECK-LABEL: define i1 @signbit_bitcast_fpext_ppc_fp128( +; CHECK-SAME: float [[X:%.*]]) { +; CHECK-NEXT: [[S2:%.*]] = fpext float [[X]] to ppc_fp128 ; CHECK-NEXT: [[S3:%.*]] = bitcast ppc_fp128 [[S2]] to i128 ; CHECK-NEXT: [[S4:%.*]] = icmp slt i128 [[S3]], 0 ; CHECK-NEXT: ret i1 [[S4]] @@ -4497,8 +4869,9 @@ define i1 @signbit_bitcast_fpext_ppc_fp128(float %x) { } define i1 @signbit_bitcast_fptrunc_ppc_fp128(ppc_fp128 %x) { -; CHECK-LABEL: @signbit_bitcast_fptrunc_ppc_fp128( -; CHECK-NEXT: [[S2:%.*]] = fptrunc ppc_fp128 [[X:%.*]] to float +; CHECK-LABEL: define i1 @signbit_bitcast_fptrunc_ppc_fp128( +; CHECK-SAME: ppc_fp128 [[X:%.*]]) { +; CHECK-NEXT: [[S2:%.*]] = fptrunc ppc_fp128 [[X]] to float ; CHECK-NEXT: [[S3:%.*]] = bitcast float [[S2]] to i32 ; CHECK-NEXT: [[S4:%.*]] = icmp slt i32 [[S3]], 0 ; CHECK-NEXT: ret i1 [[S4]] @@ -4512,9 +4885,10 @@ define i1 @signbit_bitcast_fptrunc_ppc_fp128(ppc_fp128 %x) { @x = external dso_local local_unnamed_addr global i32, align 4 @y = external dso_local local_unnamed_addr global i32, align 4 define i1 @pr47997(i32 %arg) { -; CHECK-LABEL: @pr47997( -; CHECK-NEXT: bb: -; CHECK-NEXT: [[I:%.*]] = add nsw i32 [[ARG:%.*]], -1 +; CHECK-LABEL: define i1 @pr47997( +; CHECK-SAME: i32 [[ARG:%.*]]) { +; CHECK-NEXT: [[BB:.*:]] +; CHECK-NEXT: [[I:%.*]] = add nsw i32 [[ARG]], -1 ; CHECK-NEXT: store i32 [[I]], ptr @x, align 4 ; CHECK-NEXT: [[I1:%.*]] = sub nsw i32 1, [[ARG]] ; CHECK-NEXT: store i32 [[I1]], ptr @y, align 4 @@ -4533,7 +4907,8 @@ bb: ; PR50944 define i1 @thread_cmp_over_select_with_poison_trueval(i1 %b) { -; CHECK-LABEL: @thread_cmp_over_select_with_poison_trueval( +; CHECK-LABEL: define i1 @thread_cmp_over_select_with_poison_trueval( +; CHECK-SAME: i1 [[B:%.*]]) { ; CHECK-NEXT: ret i1 false ; %s = select i1 %b, i32 poison, i32 0 @@ -4542,7 +4917,8 @@ define i1 @thread_cmp_over_select_with_poison_trueval(i1 %b) { } define i1 @thread_cmp_over_select_with_poison_falseval(i1 %b) { -; CHECK-LABEL: @thread_cmp_over_select_with_poison_falseval( +; CHECK-LABEL: define i1 @thread_cmp_over_select_with_poison_falseval( +; CHECK-SAME: i1 [[B:%.*]]) { ; CHECK-NEXT: ret i1 true ; %s = select i1 %b, i32 1, i32 poison @@ -4551,8 +4927,9 @@ define i1 @thread_cmp_over_select_with_poison_falseval(i1 %b) { } define i1 @signbit_true_logic(i8 %x) { -; CHECK-LABEL: @signbit_true_logic( -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[X:%.*]], 0 +; CHECK-LABEL: define i1 @signbit_true_logic( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[X]], 0 ; CHECK-NEXT: ret i1 [[R]] ; %dec = add i8 %x, -1 @@ -4563,8 +4940,9 @@ define i1 @signbit_true_logic(i8 %x) { } define <2 x i1> @signbit_false_logic(<2 x i5> %x) { -; CHECK-LABEL: @signbit_false_logic( -; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i5> [[X:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @signbit_false_logic( +; CHECK-SAME: <2 x i5> [[X:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i5> [[X]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[R]] ; %dec = add <2 x i5> %x, <i5 -1, i5 poison> @@ -4577,8 +4955,9 @@ define <2 x i1> @signbit_false_logic(<2 x i5> %x) { ; Confirm that complexity canonicalization works for commuted pattern. define i1 @signbit_true_logic_uses_commute(i64 %x) { -; CHECK-LABEL: @signbit_true_logic_uses_commute( -; CHECK-NEXT: [[DEC:%.*]] = add i64 [[X:%.*]], -1 +; CHECK-LABEL: define i1 @signbit_true_logic_uses_commute( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[DEC:%.*]] = add i64 [[X]], -1 ; CHECK-NEXT: call void @use_i64(i64 [[DEC]]) ; CHECK-NEXT: [[NOT:%.*]] = xor i64 [[X]], -1 ; CHECK-NEXT: call void @use_i64(i64 [[NOT]]) @@ -4598,8 +4977,9 @@ define i1 @signbit_true_logic_uses_commute(i64 %x) { } define i1 @redundant_sign_bit_count_ult_1_2(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_1_2( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 4 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ult_1_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 4 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], 8 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4610,8 +4990,9 @@ define i1 @redundant_sign_bit_count_ult_1_2(i32 %x) { } define i1 @redundant_sign_bit_count_ult_1_30(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_1_30( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1073741824 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ult_1_30( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 1073741824 ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[TMP1]], -1 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4622,8 +5003,9 @@ define i1 @redundant_sign_bit_count_ult_1_30(i32 %x) { } define i1 @redundant_sign_bit_count_ult_31_2(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_31_2( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 4 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ult_31_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 4 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], 8 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4634,8 +5016,9 @@ define i1 @redundant_sign_bit_count_ult_31_2(i32 %x) { } define i1 @redundant_sign_bit_count_ult_31_30(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1073741824 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ult_31_30( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 1073741824 ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[TMP1]], -1 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4646,8 +5029,9 @@ define i1 @redundant_sign_bit_count_ult_31_30(i32 %x) { } define i1 @redundant_sign_bit_count_ult_31_30_extra_use_ashr(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_extra_use_ashr( -; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ult_31_30_extra_use_ashr( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X]], 31 ; CHECK-NEXT: call void @use_i32(i32 [[Y]]) ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 1073741824 ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[TMP1]], -1 @@ -4661,8 +5045,9 @@ define i1 @redundant_sign_bit_count_ult_31_30_extra_use_ashr(i32 %x) { } define i1 @redundant_sign_bit_count_ult_31_30_extra_use_xor(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_extra_use_xor( -; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ult_31_30_extra_use_xor( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X]], 31 ; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[X]] ; CHECK-NEXT: call void @use_i32(i32 [[Z]]) ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824 @@ -4676,9 +5061,10 @@ define i1 @redundant_sign_bit_count_ult_31_30_extra_use_xor(i32 %x) { } define i1 @not_redundant_sign_bit_count_ult(i32 %w, i32 %x) { -; CHECK-LABEL: @not_redundant_sign_bit_count_ult( -; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[W:%.*]] +; CHECK-LABEL: define i1 @not_redundant_sign_bit_count_ult( +; CHECK-SAME: i32 [[W:%.*]], i32 [[X:%.*]]) { +; CHECK-NEXT: [[Y:%.*]] = ashr i32 [[X]], 31 +; CHECK-NEXT: [[Z:%.*]] = xor i32 [[Y]], [[W]] ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[Z]], 1073741824 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4689,8 +5075,9 @@ define i1 @not_redundant_sign_bit_count_ult(i32 %w, i32 %x) { } define i1 @wrong_shift_opcode_i8(i8 %x) { -; CHECK-LABEL: @wrong_shift_opcode_i8( -; CHECK-NEXT: [[Y:%.*]] = lshr i8 [[X:%.*]], 5 +; CHECK-LABEL: define i1 @wrong_shift_opcode_i8( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[Y:%.*]] = lshr i8 [[X]], 5 ; CHECK-NEXT: [[Z:%.*]] = xor i8 [[Y]], [[X]] ; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[Z]], 2 ; CHECK-NEXT: ret i1 [[C]] @@ -4702,8 +5089,9 @@ define i1 @wrong_shift_opcode_i8(i8 %x) { } define i1 @redundant_sign_bit_count_ult_31_30_commute(i32 %xsrc) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_commute( -; CHECK-NEXT: [[X:%.*]] = mul i32 [[XSRC:%.*]], 13 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ult_31_30_commute( +; CHECK-SAME: i32 [[XSRC:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = mul i32 [[XSRC]], 13 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 1073741824 ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[TMP1]], -1 ; CHECK-NEXT: ret i1 [[C]] @@ -4716,8 +5104,9 @@ define i1 @redundant_sign_bit_count_ult_31_30_commute(i32 %xsrc) { } define i1 @redundant_sign_bit_count_i8(i8 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_i8( -; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], 2 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_i8( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X]], 2 ; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[TMP1]], 4 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4728,8 +5117,9 @@ define i1 @redundant_sign_bit_count_i8(i8 %x) { } define <2 x i1> @redundant_sign_bit_count_ult_31_30_vector(<2 x i32> %xsrc) { -; CHECK-LABEL: @redundant_sign_bit_count_ult_31_30_vector( -; CHECK-NEXT: [[X:%.*]] = mul <2 x i32> [[XSRC:%.*]], splat (i32 13) +; CHECK-LABEL: define <2 x i1> @redundant_sign_bit_count_ult_31_30_vector( +; CHECK-SAME: <2 x i32> [[XSRC:%.*]]) { +; CHECK-NEXT: [[X:%.*]] = mul <2 x i32> [[XSRC]], splat (i32 13) ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X]], splat (i32 1073741824) ; CHECK-NEXT: [[C:%.*]] = icmp sgt <2 x i32> [[TMP1]], splat (i32 -1) ; CHECK-NEXT: ret <2 x i1> [[C]] @@ -4742,8 +5132,9 @@ define <2 x i1> @redundant_sign_bit_count_ult_31_30_vector(<2 x i32> %xsrc) { } define i1 @redundant_sign_bit_count_ugt_1_2(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ugt_1_2( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -4 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ugt_1_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -4 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -8 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4754,8 +5145,9 @@ define i1 @redundant_sign_bit_count_ugt_1_2(i32 %x) { } define i1 @redundant_sign_bit_count_ugt_1_30(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ugt_1_30( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1073741824 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ugt_1_30( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 1073741824 ; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4766,8 +5158,9 @@ define i1 @redundant_sign_bit_count_ugt_1_30(i32 %x) { } define i1 @redundant_sign_bit_count_ugt_31_2(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ugt_31_2( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -4 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ugt_31_2( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -4 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[TMP1]], -8 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4778,8 +5171,9 @@ define i1 @redundant_sign_bit_count_ugt_31_2(i32 %x) { } define i1 @redundant_sign_bit_count_ugt_31_30(i32 %x) { -; CHECK-LABEL: @redundant_sign_bit_count_ugt_31_30( -; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], 1073741824 +; CHECK-LABEL: define i1 @redundant_sign_bit_count_ugt_31_30( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], 1073741824 ; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[C]] ; @@ -4790,10 +5184,11 @@ define i1 @redundant_sign_bit_count_ugt_31_30(i32 %x) { } define i1 @zext_bool_and_eq0(i1 %x, i8 %y) { -; CHECK-LABEL: @zext_bool_and_eq0( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y:%.*]], 1 +; CHECK-LABEL: define i1 @zext_bool_and_eq0( +; CHECK-SAME: i1 [[X:%.*]], i8 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y]], 1 ; CHECK-NEXT: [[R1:%.*]] = icmp eq i8 [[TMP1]], 0 -; CHECK-NEXT: [[NOT_X:%.*]] = xor i1 [[X:%.*]], true +; CHECK-NEXT: [[NOT_X:%.*]] = xor i1 [[X]], true ; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_X]], i1 true, i1 [[R1]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -4804,10 +5199,11 @@ define i1 @zext_bool_and_eq0(i1 %x, i8 %y) { } define <2 x i1> @zext_bool_and_eq0_commute(<2 x i1> %x, <2 x i8> %p) { -; CHECK-LABEL: @zext_bool_and_eq0_commute( -; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[P:%.*]], splat (i8 1) +; CHECK-LABEL: define <2 x i1> @zext_bool_and_eq0_commute( +; CHECK-SAME: <2 x i1> [[X:%.*]], <2 x i8> [[P:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[P]], splat (i8 1) ; CHECK-NEXT: [[R1:%.*]] = icmp eq <2 x i8> [[TMP1]], zeroinitializer -; CHECK-NEXT: [[NOT_X:%.*]] = xor <2 x i1> [[X:%.*]], splat (i1 true) +; CHECK-NEXT: [[NOT_X:%.*]] = xor <2 x i1> [[X]], splat (i1 true) ; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[NOT_X]], <2 x i1> splat (i1 true), <2 x i1> [[R1]] ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -4819,10 +5215,11 @@ define <2 x i1> @zext_bool_and_eq0_commute(<2 x i1> %x, <2 x i8> %p) { } define i1 @zext_bool_and_ne0(i1 %x, i8 %y) { -; CHECK-LABEL: @zext_bool_and_ne0( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y:%.*]], 1 +; CHECK-LABEL: define i1 @zext_bool_and_ne0( +; CHECK-SAME: i1 [[X:%.*]], i8 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y]], 1 ; CHECK-NEXT: [[R1:%.*]] = icmp ne i8 [[TMP1]], 0 -; CHECK-NEXT: [[R:%.*]] = select i1 [[X:%.*]], i1 [[R1]], i1 false +; CHECK-NEXT: [[R:%.*]] = select i1 [[X]], i1 [[R1]], i1 false ; CHECK-NEXT: ret i1 [[R]] ; %zx = zext i1 %x to i8 @@ -4832,10 +5229,11 @@ define i1 @zext_bool_and_ne0(i1 %x, i8 %y) { } define i1 @zext_bool_and_ne1(i1 %x, i8 %y) { -; CHECK-LABEL: @zext_bool_and_ne1( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y:%.*]], 1 +; CHECK-LABEL: define i1 @zext_bool_and_ne1( +; CHECK-SAME: i1 [[X:%.*]], i8 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y]], 1 ; CHECK-NEXT: [[R1:%.*]] = icmp eq i8 [[TMP1]], 0 -; CHECK-NEXT: [[NOT_X:%.*]] = xor i1 [[X:%.*]], true +; CHECK-NEXT: [[NOT_X:%.*]] = xor i1 [[X]], true ; CHECK-NEXT: [[R:%.*]] = select i1 [[NOT_X]], i1 true, i1 [[R1]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -4846,9 +5244,10 @@ define i1 @zext_bool_and_ne1(i1 %x, i8 %y) { } define <2 x i1> @zext_bool_and_eq1(<2 x i1> %x, <2 x i8> %y) { -; CHECK-LABEL: @zext_bool_and_eq1( -; CHECK-NEXT: [[R1:%.*]] = trunc <2 x i8> [[Y:%.*]] to <2 x i1> -; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[X:%.*]], <2 x i1> [[R1]], <2 x i1> zeroinitializer +; CHECK-LABEL: define <2 x i1> @zext_bool_and_eq1( +; CHECK-SAME: <2 x i1> [[X:%.*]], <2 x i8> [[Y:%.*]]) { +; CHECK-NEXT: [[R1:%.*]] = trunc <2 x i8> [[Y]] to <2 x i1> +; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[X]], <2 x i1> [[R1]], <2 x i1> zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[R]] ; %zx = zext <2 x i1> %x to <2 x i8> @@ -4860,9 +5259,10 @@ define <2 x i1> @zext_bool_and_eq1(<2 x i1> %x, <2 x i8> %y) { ; negative test - wrong logic op define i1 @zext_bool_or_eq0(i1 %x, i8 %y) { -; CHECK-LABEL: @zext_bool_or_eq0( -; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i8 -; CHECK-NEXT: [[A:%.*]] = or i8 [[Y:%.*]], [[ZX]] +; CHECK-LABEL: define i1 @zext_bool_or_eq0( +; CHECK-SAME: i1 [[X:%.*]], i8 [[Y:%.*]]) { +; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X]] to i8 +; CHECK-NEXT: [[A:%.*]] = or i8 [[Y]], [[ZX]] ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[A]], 0 ; CHECK-NEXT: ret i1 [[R]] ; @@ -4875,10 +5275,11 @@ define i1 @zext_bool_or_eq0(i1 %x, i8 %y) { ; negative test - extra use define i1 @zext_bool_and_eq0_use(i1 %x, i64 %y) { -; CHECK-LABEL: @zext_bool_and_eq0_use( -; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X:%.*]] to i64 +; CHECK-LABEL: define i1 @zext_bool_and_eq0_use( +; CHECK-SAME: i1 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[ZX:%.*]] = zext i1 [[X]] to i64 ; CHECK-NEXT: call void @use_i64(i64 [[ZX]]) -; CHECK-NEXT: [[A:%.*]] = and i64 [[Y:%.*]], [[ZX]] +; CHECK-NEXT: [[A:%.*]] = and i64 [[Y]], [[ZX]] ; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[A]], 0 ; CHECK-NEXT: ret i1 [[R]] ; @@ -4892,9 +5293,10 @@ define i1 @zext_bool_and_eq0_use(i1 %x, i64 %y) { ; negative test - extra use define i1 @zext_bool_and_ne0_use(i1 %x, i64 %y) { -; CHECK-LABEL: @zext_bool_and_ne0_use( -; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y:%.*]], 1 -; CHECK-NEXT: [[A:%.*]] = select i1 [[X:%.*]], i64 [[TMP1]], i64 0 +; CHECK-LABEL: define i1 @zext_bool_and_ne0_use( +; CHECK-SAME: i1 [[X:%.*]], i64 [[Y:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y]], 1 +; CHECK-NEXT: [[A:%.*]] = select i1 [[X]], i64 [[TMP1]], i64 0 ; CHECK-NEXT: call void @use_i64(i64 [[A]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i64 [[A]], 0 ; CHECK-NEXT: ret i1 [[R]] @@ -4909,9 +5311,10 @@ define i1 @zext_bool_and_ne0_use(i1 %x, i64 %y) { ; negative test - must zext from i1 define i1 @zext_notbool_and_ne0(i2 %x, i8 %y) { -; CHECK-LABEL: @zext_notbool_and_ne0( -; CHECK-NEXT: [[ZX:%.*]] = zext i2 [[X:%.*]] to i8 -; CHECK-NEXT: [[A:%.*]] = and i8 [[Y:%.*]], [[ZX]] +; CHECK-LABEL: define i1 @zext_notbool_and_ne0( +; CHECK-SAME: i2 [[X:%.*]], i8 [[Y:%.*]]) { +; CHECK-NEXT: [[ZX:%.*]] = zext i2 [[X]] to i8 +; CHECK-NEXT: [[A:%.*]] = and i8 [[Y]], [[ZX]] ; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[A]], 0 ; CHECK-NEXT: ret i1 [[R]] ; @@ -4924,8 +5327,9 @@ define i1 @zext_notbool_and_ne0(i2 %x, i8 %y) { ; fold icmp(X | OrC, C) --> icmp(X, 0) define i1 @or_positive_sgt_zero(i8 %a) { -; CHECK-LABEL: @or_positive_sgt_zero( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A:%.*]], -1 +; CHECK-LABEL: define i1 @or_positive_sgt_zero( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -4934,8 +5338,9 @@ define i1 @or_positive_sgt_zero(i8 %a) { } define <2 x i1> @or_postive_sgt_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_sgt_zero_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A:%.*]], splat (i8 -1) +; CHECK-LABEL: define <2 x i1> @or_postive_sgt_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A]], splat (i8 -1) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -4945,7 +5350,8 @@ define <2 x i1> @or_postive_sgt_zero_vec(<2 x i8> %a) { } define <2 x i1> @or_poison_vec_sgt_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_poison_vec_sgt_zero_vec( +; CHECK-LABEL: define <2 x i1> @or_poison_vec_sgt_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { ; CHECK-NEXT: ret <2 x i1> poison ; @@ -4955,8 +5361,9 @@ define <2 x i1> @or_poison_vec_sgt_zero_vec(<2 x i8> %a) { } define i1 @or_positive_sge_zero(i8 %a) { -; CHECK-LABEL: @or_positive_sge_zero( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A:%.*]], -1 +; CHECK-LABEL: define i1 @or_positive_sge_zero( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -4965,8 +5372,9 @@ define i1 @or_positive_sge_zero(i8 %a) { } define <2 x i1> @or_postive_sge_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_sge_zero_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A:%.*]], splat (i8 -1) +; CHECK-LABEL: define <2 x i1> @or_postive_sge_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A]], splat (i8 -1) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -4976,7 +5384,8 @@ define <2 x i1> @or_postive_sge_zero_vec(<2 x i8> %a) { } define <2 x i1> @or_poison_vec_sge_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_poison_vec_sge_zero_vec( +; CHECK-LABEL: define <2 x i1> @or_poison_vec_sge_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { ; CHECK-NEXT: ret <2 x i1> poison ; @@ -4986,8 +5395,9 @@ define <2 x i1> @or_poison_vec_sge_zero_vec(<2 x i8> %a) { } define i1 @or_positive_sge_postive(i8 %a) { -; CHECK-LABEL: @or_positive_sge_postive( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A:%.*]], -1 +; CHECK-LABEL: define i1 @or_positive_sge_postive( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -4996,8 +5406,9 @@ define i1 @or_positive_sge_postive(i8 %a) { } define <2 x i1> @or_postive_sge_positive_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_sge_positive_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A:%.*]], splat (i8 -1) +; CHECK-LABEL: define <2 x i1> @or_postive_sge_positive_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A]], splat (i8 -1) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5007,7 +5418,8 @@ define <2 x i1> @or_postive_sge_positive_vec(<2 x i8> %a) { } define <2 x i1> @or_poison_vec_sge_positive_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_poison_vec_sge_positive_vec( +; CHECK-LABEL: define <2 x i1> @or_poison_vec_sge_positive_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { ; CHECK-NEXT: ret <2 x i1> poison ; @@ -5017,8 +5429,9 @@ define <2 x i1> @or_poison_vec_sge_positive_vec(<2 x i8> %a) { } define i1 @or_positive_sle_zero(i8 %a) { -; CHECK-LABEL: @or_positive_sle_zero( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @or_positive_sle_zero( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -5027,8 +5440,9 @@ define i1 @or_positive_sle_zero(i8 %a) { } define <2 x i1> @or_postive_sle_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_sle_zero_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @or_postive_sle_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5038,7 +5452,8 @@ define <2 x i1> @or_postive_sle_zero_vec(<2 x i8> %a) { } define <2 x i1> @or_poison_vec_sle_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_poison_vec_sle_zero_vec( +; CHECK-LABEL: define <2 x i1> @or_poison_vec_sle_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { ; CHECK-NEXT: ret <2 x i1> poison ; @@ -5048,8 +5463,9 @@ define <2 x i1> @or_poison_vec_sle_zero_vec(<2 x i8> %a) { } define i1 @or_positive_slt_zero(i8 %a) { -; CHECK-LABEL: @or_positive_slt_zero( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @or_positive_slt_zero( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -5058,8 +5474,9 @@ define i1 @or_positive_slt_zero(i8 %a) { } define <2 x i1> @or_postive_slt_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_slt_zero_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @or_postive_slt_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5069,7 +5486,8 @@ define <2 x i1> @or_postive_slt_zero_vec(<2 x i8> %a) { } define <2 x i1> @or_poison_vec_slt_zero_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_poison_vec_slt_zero_vec( +; CHECK-LABEL: define <2 x i1> @or_poison_vec_slt_zero_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { ; CHECK-NEXT: ret <2 x i1> poison ; @@ -5079,8 +5497,9 @@ define <2 x i1> @or_poison_vec_slt_zero_vec(<2 x i8> %a) { } define i1 @or_positive_slt_postive(i8 %a) { -; CHECK-LABEL: @or_positive_slt_postive( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @or_positive_slt_postive( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -5089,8 +5508,9 @@ define i1 @or_positive_slt_postive(i8 %a) { } define <2 x i1> @or_postive_slt_positive_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_slt_positive_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @or_postive_slt_positive_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5100,7 +5520,8 @@ define <2 x i1> @or_postive_slt_positive_vec(<2 x i8> %a) { } define <2 x i1> @or_poison_vec_slt_positive_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_poison_vec_slt_positive_vec( +; CHECK-LABEL: define <2 x i1> @or_poison_vec_slt_positive_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { ; CHECK-NEXT: ret <2 x i1> poison ; @@ -5112,8 +5533,9 @@ define <2 x i1> @or_poison_vec_slt_positive_vec(<2 x i8> %a) { ; negative tests for icmp(X | OrC, C) --> icmp(X, 0) define i1 @or_positive_sgt_neg(i8 %a) { -; CHECK-LABEL: @or_positive_sgt_neg( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A:%.*]], -1 +; CHECK-LABEL: define i1 @or_positive_sgt_neg( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -5122,8 +5544,9 @@ define i1 @or_positive_sgt_neg(i8 %a) { } define <2 x i1> @or_postive_sgt_neg_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_sgt_neg_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A:%.*]], splat (i8 -1) +; CHECK-LABEL: define <2 x i1> @or_postive_sgt_neg_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[A]], splat (i8 -1) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5133,8 +5556,9 @@ define <2 x i1> @or_postive_sgt_neg_vec(<2 x i8> %a) { } define i1 @mul_or_positive_sge_neg(i8 %a) { -; CHECK-LABEL: @mul_or_positive_sge_neg( -; CHECK-NEXT: [[B:%.*]] = or i8 [[A:%.*]], 24 +; CHECK-LABEL: define i1 @mul_or_positive_sge_neg( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or i8 [[A]], 24 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[B]], -2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5144,8 +5568,9 @@ define i1 @mul_or_positive_sge_neg(i8 %a) { } define <2 x i1> @or_postive_sge_neg_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_sge_neg_vec( -; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A:%.*]], splat (i8 24) +; CHECK-LABEL: define <2 x i1> @or_postive_sge_neg_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A]], splat (i8 24) ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[B]], splat (i8 -2) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5156,8 +5581,9 @@ define <2 x i1> @or_postive_sge_neg_vec(<2 x i8> %a) { } define i1 @mul_or_small_sge_large(i8 %a) { -; CHECK-LABEL: @mul_or_small_sge_large( -; CHECK-NEXT: [[B:%.*]] = or i8 [[A:%.*]], 24 +; CHECK-LABEL: define i1 @mul_or_small_sge_large( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or i8 [[A]], 24 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[B]], 24 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5167,8 +5593,9 @@ define i1 @mul_or_small_sge_large(i8 %a) { } define <2 x i1> @or_small_sge_large_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_small_sge_large_vec( -; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A:%.*]], splat (i8 24) +; CHECK-LABEL: define <2 x i1> @or_small_sge_large_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A]], splat (i8 24) ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i8> [[B]], splat (i8 24) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5179,8 +5606,9 @@ define <2 x i1> @or_small_sge_large_vec(<2 x i8> %a) { } define i1 @or_positive_sle_neg(i8 %a) { -; CHECK-LABEL: @or_positive_sle_neg( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A:%.*]], 0 +; CHECK-LABEL: define i1 @or_positive_sle_neg( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %b = or i8 %a, 24 @@ -5189,8 +5617,9 @@ define i1 @or_positive_sle_neg(i8 %a) { } define <2 x i1> @or_sle_neg_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_sle_neg_vec( -; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A:%.*]], zeroinitializer +; CHECK-LABEL: define <2 x i1> @or_sle_neg_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[A]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5200,8 +5629,9 @@ define <2 x i1> @or_sle_neg_vec(<2 x i8> %a) { } define i1 @or_positive_slt_neg(i8 %a) { -; CHECK-LABEL: @or_positive_slt_neg( -; CHECK-NEXT: [[B:%.*]] = or i8 [[A:%.*]], 24 +; CHECK-LABEL: define i1 @or_positive_slt_neg( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or i8 [[A]], 24 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[B]], -1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5211,8 +5641,9 @@ define i1 @or_positive_slt_neg(i8 %a) { } define <2 x i1> @or_postive_slt_neg_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_postive_slt_neg_vec( -; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A:%.*]], splat (i8 24) +; CHECK-LABEL: define <2 x i1> @or_postive_slt_neg_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A]], splat (i8 24) ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[B]], splat (i8 -1) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5223,8 +5654,9 @@ define <2 x i1> @or_postive_slt_neg_vec(<2 x i8> %a) { } define i1 @or_small_slt_large(i8 %a) { -; CHECK-LABEL: @or_small_slt_large( -; CHECK-NEXT: [[B:%.*]] = or i8 [[A:%.*]], 24 +; CHECK-LABEL: define i1 @or_small_slt_large( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or i8 [[A]], 24 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[B]], 25 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5234,8 +5666,9 @@ define i1 @or_small_slt_large(i8 %a) { } define <2 x i1> @or_small_slt_large_vec(<2 x i8> %a) { -; CHECK-LABEL: @or_small_slt_large_vec( -; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A:%.*]], splat (i8 24) +; CHECK-LABEL: define <2 x i1> @or_small_slt_large_vec( +; CHECK-SAME: <2 x i8> [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or <2 x i8> [[A]], splat (i8 24) ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[B]], splat (i8 25) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5246,8 +5679,9 @@ define <2 x i1> @or_small_slt_large_vec(<2 x i8> %a) { } define i1 @or_positive_sgt_zero_multi_use(i8 %a) { -; CHECK-LABEL: @or_positive_sgt_zero_multi_use( -; CHECK-NEXT: [[B:%.*]] = or i8 [[A:%.*]], 24 +; CHECK-LABEL: define i1 @or_positive_sgt_zero_multi_use( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[B:%.*]] = or i8 [[A]], 24 ; CHECK-NEXT: call void @use_i8(i8 [[B]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[A]], -1 ; CHECK-NEXT: ret i1 [[CMP]] @@ -5260,9 +5694,10 @@ define i1 @or_positive_sgt_zero_multi_use(i8 %a) { define i1 @disjoint_or_sgt_1(i8 %a, i8 %b) { -; CHECK-LABEL: @disjoint_or_sgt_1( -; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B:%.*]], 2 -; CHECK-NEXT: [[ICMP_:%.*]] = icmp sge i8 [[A:%.*]], [[B1]] +; CHECK-LABEL: define i1 @disjoint_or_sgt_1( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B]], 2 +; CHECK-NEXT: [[ICMP_:%.*]] = icmp sge i8 [[A]], [[B1]] ; CHECK-NEXT: ret i1 [[ICMP_]] ; %a1 = or disjoint i8 %a, 1 @@ -5272,9 +5707,10 @@ define i1 @disjoint_or_sgt_1(i8 %a, i8 %b) { } define i1 @disjoint_or_sgt_2(i8 %a, i8 %b) { -; CHECK-LABEL: @disjoint_or_sgt_2( -; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2 -; CHECK-NEXT: [[B1:%.*]] = add i8 [[B:%.*]], 1 +; CHECK-LABEL: define i1 @disjoint_or_sgt_2( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A]], 2 +; CHECK-NEXT: [[B1:%.*]] = add i8 [[B]], 1 ; CHECK-NEXT: [[ICMP_:%.*]] = icmp sgt i8 [[A1]], [[B1]] ; CHECK-NEXT: ret i1 [[ICMP_]] ; @@ -5285,9 +5721,10 @@ define i1 @disjoint_or_sgt_2(i8 %a, i8 %b) { } define i1 @disjoint_or_sgt_3(i8 %a, i8 %b) { -; CHECK-LABEL: @disjoint_or_sgt_3( -; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2 -; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B:%.*]], 1 +; CHECK-LABEL: define i1 @disjoint_or_sgt_3( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A]], 2 +; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B]], 1 ; CHECK-NEXT: [[ICMP_:%.*]] = icmp sgt i8 [[A1]], [[B1]] ; CHECK-NEXT: ret i1 [[ICMP_]] ; @@ -5298,9 +5735,10 @@ define i1 @disjoint_or_sgt_3(i8 %a, i8 %b) { } define i1 @disjoint_or_ugt_1(i8 %a, i8 %b) { -; CHECK-LABEL: @disjoint_or_ugt_1( -; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B:%.*]], 2 -; CHECK-NEXT: [[ICMP_:%.*]] = icmp uge i8 [[A:%.*]], [[B1]] +; CHECK-LABEL: define i1 @disjoint_or_ugt_1( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[B1:%.*]] = add nsw i8 [[B]], 2 +; CHECK-NEXT: [[ICMP_:%.*]] = icmp uge i8 [[A]], [[B1]] ; CHECK-NEXT: ret i1 [[ICMP_]] ; %a1 = or disjoint i8 %a, 1 @@ -5310,9 +5748,10 @@ define i1 @disjoint_or_ugt_1(i8 %a, i8 %b) { } define i1 @disjoint_or_ugt_2(i8 %a, i8 %b) { -; CHECK-LABEL: @disjoint_or_ugt_2( -; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2 -; CHECK-NEXT: [[B1:%.*]] = add i8 [[B:%.*]], 1 +; CHECK-LABEL: define i1 @disjoint_or_ugt_2( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A]], 2 +; CHECK-NEXT: [[B1:%.*]] = add i8 [[B]], 1 ; CHECK-NEXT: [[ICMP_:%.*]] = icmp ugt i8 [[A1]], [[B1]] ; CHECK-NEXT: ret i1 [[ICMP_]] ; @@ -5323,9 +5762,10 @@ define i1 @disjoint_or_ugt_2(i8 %a, i8 %b) { } define i1 @disjoint_or_ugt_3(i8 %a, i8 %b) { -; CHECK-LABEL: @disjoint_or_ugt_3( -; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A:%.*]], 2 -; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B:%.*]], 1 +; CHECK-LABEL: define i1 @disjoint_or_ugt_3( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[A1:%.*]] = or disjoint i8 [[A]], 2 +; CHECK-NEXT: [[B1:%.*]] = add nuw i8 [[B]], 1 ; CHECK-NEXT: [[ICMP_:%.*]] = icmp ugt i8 [[A1]], [[B1]] ; CHECK-NEXT: ret i1 [[ICMP_]] ; @@ -5336,10 +5776,11 @@ define i1 @disjoint_or_ugt_3(i8 %a, i8 %b) { } define i1 @deduce_nuw_flag_1(i8 %a, i8 %b) { -; CHECK-LABEL: @deduce_nuw_flag_1( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = add nuw i8 [[B:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A:%.*]] +; CHECK-LABEL: define i1 @deduce_nuw_flag_1( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP0:%.*]] = add nuw i8 [[B]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A]] ; CHECK-NEXT: ret i1 [[CMP]] ; entry: @@ -5350,10 +5791,11 @@ entry: } define i1 @deduce_nuw_flag_2(i8 %a, i8 %b) { -; CHECK-LABEL: @deduce_nuw_flag_2( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = add nuw i8 [[B:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[A:%.*]], [[TMP0]] +; CHECK-LABEL: define i1 @deduce_nuw_flag_2( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP0:%.*]] = add nuw i8 [[B]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[A]], [[TMP0]] ; CHECK-NEXT: ret i1 [[CMP]] ; entry: @@ -5364,10 +5806,11 @@ entry: } define i1 @dont_deduce_nuw_flag_1(i8 %a, i8 %b) { -; CHECK-LABEL: @dont_deduce_nuw_flag_1( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[B:%.*]], -1 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A:%.*]] +; CHECK-LABEL: define i1 @dont_deduce_nuw_flag_1( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[B]], -1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP0]], [[A]] ; CHECK-NEXT: ret i1 [[CMP]] ; entry: @@ -5378,10 +5821,11 @@ entry: } define i1 @dont_deduce_nuw_flag_2(i8 %a, i8 %b) { -; CHECK-LABEL: @dont_deduce_nuw_flag_2( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[B:%.*]], -1 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[A:%.*]], [[TMP0]] +; CHECK-LABEL: define i1 @dont_deduce_nuw_flag_2( +; CHECK-SAME: i8 [[A:%.*]], i8 [[B:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[B]], -1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[A]], [[TMP0]] ; CHECK-NEXT: ret i1 [[CMP]] ; entry: @@ -5392,11 +5836,11 @@ entry: } define i1 @icmp_freeze_sext(i16 %x, i16 %y) { -; CHECK-LABEL: @icmp_freeze_sext( -; CHECK-NEXT: [[CMP1:%.*]] = icmp uge i16 [[X:%.*]], [[Y:%.*]] -; CHECK-NEXT: [[CMP1_FR:%.*]] = freeze i1 [[CMP1]] -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i16 [[Y]], 0 -; CHECK-NEXT: [[CMP2:%.*]] = or i1 [[TMP1]], [[CMP1_FR]] +; CHECK-LABEL: define i1 @icmp_freeze_sext( +; CHECK-SAME: i16 [[X:%.*]], i16 [[Y:%.*]]) { +; CHECK-NEXT: [[Y_FR:%.*]] = freeze i16 [[Y]] +; CHECK-NEXT: [[X_FR:%.*]] = freeze i16 [[X]] +; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i16 [[X_FR]], [[Y_FR]] ; CHECK-NEXT: ret i1 [[CMP2]] ; %cmp1 = icmp uge i16 %x, %y @@ -5407,8 +5851,9 @@ define i1 @icmp_freeze_sext(i16 %x, i16 %y) { } define i1 @test_icmp_shl(i64 %x) { -; CHECK-LABEL: @test_icmp_shl( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32 +; CHECK-LABEL: define i1 @test_icmp_shl( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X]] to i32 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP1]], 3 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5418,8 +5863,9 @@ define i1 @test_icmp_shl(i64 %x) { } define i1 @test_icmp_shl_multiuse(i64 %x) { -; CHECK-LABEL: @test_icmp_shl_multiuse( -; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X:%.*]], 32 +; CHECK-LABEL: define i1 @test_icmp_shl_multiuse( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X]], 32 ; CHECK-NEXT: call void @use_i64(i64 [[SHL]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SHL]], 8589934593 ; CHECK-NEXT: ret i1 [[CMP]] @@ -5431,8 +5877,9 @@ define i1 @test_icmp_shl_multiuse(i64 %x) { } define i1 @test_icmp_shl_illegal_length(i64 %x) { -; CHECK-LABEL: @test_icmp_shl_illegal_length( -; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X:%.*]], 31 +; CHECK-LABEL: define i1 @test_icmp_shl_illegal_length( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X]], 31 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SHL]], 8589934593 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5442,8 +5889,9 @@ define i1 @test_icmp_shl_illegal_length(i64 %x) { } define i1 @test_icmp_shl_invalid_rhsc(i64 %x) { -; CHECK-LABEL: @test_icmp_shl_invalid_rhsc( -; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X:%.*]], 32 +; CHECK-LABEL: define i1 @test_icmp_shl_invalid_rhsc( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X]], 32 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SHL]], 8589934595 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5453,8 +5901,9 @@ define i1 @test_icmp_shl_invalid_rhsc(i64 %x) { } define i1 @test_icmp_shl_nuw(i64 %x) { -; CHECK-LABEL: @test_icmp_shl_nuw( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test_icmp_shl_nuw( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[X]], 3 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl nuw i64 %x, 32 @@ -5463,8 +5912,9 @@ define i1 @test_icmp_shl_nuw(i64 %x) { } define i1 @test_icmp_shl_nuw_i31(i31 %x) { -; CHECK-LABEL: @test_icmp_shl_nuw_i31( -; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i31 [[X:%.*]], 250 +; CHECK-LABEL: define i1 @test_icmp_shl_nuw_i31( +; CHECK-SAME: i31 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i31 [[X]], 250 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl nuw i31 %x, 23 @@ -5473,8 +5923,9 @@ define i1 @test_icmp_shl_nuw_i31(i31 %x) { } define i1 @test_icmp_shl_nsw(i64 %x) { -; CHECK-LABEL: @test_icmp_shl_nsw( -; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[X:%.*]], 3 +; CHECK-LABEL: define i1 @test_icmp_shl_nsw( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[X]], 3 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl nsw i64 %x, 32 @@ -5483,8 +5934,9 @@ define i1 @test_icmp_shl_nsw(i64 %x) { } define i1 @test_icmp_shl_nsw_i31(i31 %x) { -; CHECK-LABEL: @test_icmp_shl_nsw_i31( -; CHECK-NEXT: [[TMP1:%.*]] = trunc nsw i31 [[X:%.*]] to i8 +; CHECK-LABEL: define i1 @test_icmp_shl_nsw_i31( +; CHECK-SAME: i31 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc nsw i31 [[X]] to i8 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[TMP1]], -6 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5494,8 +5946,9 @@ define i1 @test_icmp_shl_nsw_i31(i31 %x) { } define <2 x i1> @test_icmp_shl_vec(<2 x i64> %x) { -; CHECK-LABEL: @test_icmp_shl_vec( -; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[X:%.*]] to <2 x i32> +; CHECK-LABEL: define <2 x i1> @test_icmp_shl_vec( +; CHECK-SAME: <2 x i64> [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i64> [[X]] to <2 x i32> ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[TMP1]], splat (i32 3) ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -5505,7 +5958,8 @@ define <2 x i1> @test_icmp_shl_vec(<2 x i64> %x) { } define i1 @test_icmp_shl_eq(i64 %x) { -; CHECK-LABEL: @test_icmp_shl_eq( +; CHECK-LABEL: define i1 @test_icmp_shl_eq( +; CHECK-SAME: i64 [[X:%.*]]) { ; CHECK-NEXT: ret i1 false ; %shl = shl i64 %x, 32 @@ -5514,8 +5968,9 @@ define i1 @test_icmp_shl_eq(i64 %x) { } define i1 @test_icmp_shl_sgt(i64 %x) { -; CHECK-LABEL: @test_icmp_shl_sgt( -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32 +; CHECK-LABEL: define i1 @test_icmp_shl_sgt( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X]] to i32 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5525,8 +5980,9 @@ define i1 @test_icmp_shl_sgt(i64 %x) { } define i1 @pr94897(i32 range(i32 -2147483648, 0) %x) { -; CHECK-LABEL: @pr94897( -; CHECK-NEXT: [[CMP:%.*]] = icmp samesign ugt i32 [[X:%.*]], -3 +; CHECK-LABEL: define i1 @pr94897( +; CHECK-SAME: i32 range(i32 -2147483648, 0) [[X:%.*]]) { +; CHECK-NEXT: [[CMP:%.*]] = icmp samesign ugt i32 [[X]], -3 ; CHECK-NEXT: ret i1 [[CMP]] ; %shl = shl nsw i32 %x, 24 @@ -5535,11 +5991,12 @@ define i1 @pr94897(i32 range(i32 -2147483648, 0) %x) { } define i1 @icmp_and_inv_pow2_ne_0(i32 %A, i32 %B) { -; CHECK-LABEL: @icmp_and_inv_pow2_ne_0( -; CHECK-NEXT: [[POPCNT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[A:%.*]]) +; CHECK-LABEL: define i1 @icmp_and_inv_pow2_ne_0( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[POPCNT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[A]]) ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[POPCNT]], 1 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]]) -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A]], [[B:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A]], [[B]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -5554,11 +6011,12 @@ define i1 @icmp_and_inv_pow2_ne_0(i32 %A, i32 %B) { } define i1 @icmp_and_inv_pow2_or_zero_ne_0(i32 %A, i32 %B) { -; CHECK-LABEL: @icmp_and_inv_pow2_or_zero_ne_0( -; CHECK-NEXT: [[POPCNT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[A:%.*]]) +; CHECK-LABEL: define i1 @icmp_and_inv_pow2_or_zero_ne_0( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[POPCNT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[A]]) ; CHECK-NEXT: [[COND:%.*]] = icmp samesign ult i32 [[POPCNT]], 2 ; CHECK-NEXT: call void @llvm.assume(i1 [[COND]]) -; CHECK-NEXT: [[INV:%.*]] = xor i32 [[B:%.*]], -1 +; CHECK-NEXT: [[INV:%.*]] = xor i32 [[B]], -1 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[A]], [[INV]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: ret i1 [[CMP]] @@ -5574,9 +6032,10 @@ define i1 @icmp_and_inv_pow2_or_zero_ne_0(i32 %A, i32 %B) { } define i1 @icmp_samesign_logical_and(i32 %In) { -; CHECK-LABEL: @icmp_samesign_logical_and( -; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[IN:%.*]], 1 -; CHECK-NEXT: ret i1 [[C2]] +; CHECK-LABEL: define i1 @icmp_samesign_logical_and( +; CHECK-SAME: i32 [[IN:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp eq i32 [[IN]], 1 +; CHECK-NEXT: ret i1 [[V]] ; %c1 = icmp samesign sgt i32 %In, -1 %c2 = icmp samesign eq i32 %In, 1 @@ -5585,8 +6044,9 @@ define i1 @icmp_samesign_logical_and(i32 %In) { } define i1 @icmp_samesign_logical_or(i32 %In) { -; CHECK-LABEL: @icmp_samesign_logical_or( -; CHECK-NEXT: [[V:%.*]] = icmp ne i32 [[IN:%.*]], 1 +; CHECK-LABEL: define i1 @icmp_samesign_logical_or( +; CHECK-SAME: i32 [[IN:%.*]]) { +; CHECK-NEXT: [[V:%.*]] = icmp ne i32 [[IN]], 1 ; CHECK-NEXT: ret i1 [[V]] ; %c1 = icmp samesign slt i32 %In, 0 |