diff options
Diffstat (limited to 'llvm/test/Transforms/AtomicExpand')
4 files changed, 255 insertions, 92 deletions
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll new file mode 100644 index 000000000000..2731f2118a26 --- /dev/null +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll @@ -0,0 +1,235 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -passes=atomic-expand %s | FileCheck -check-prefixes=GFX1200 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -passes=atomic-expand %s | FileCheck -check-prefixes=GFX1250 %s + +define void @system_atomic_store_unordered_float(ptr addrspace(5) %addr, float %val) { +; GFX1200-LABEL: define void @system_atomic_store_unordered_float( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], float [[VAL:%.*]]) #[[ATTR0:[0-9]+]] { +; GFX1200-NEXT: store float [[VAL]], ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret void +; +; GFX1250-LABEL: define void @system_atomic_store_unordered_float( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], float [[VAL:%.*]]) #[[ATTR0:[0-9]+]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: store atomic float [[VAL]], ptr [[SCRATCH_ASCAST]] unordered, align 4 +; GFX1250-NEXT: ret void +; + store atomic float %val, ptr addrspace(5) %addr unordered, align 4 + ret void +} + +define void @system_atomic_store_unordered_i32(ptr addrspace(5) %addr, i32 %val) { +; GFX1200-LABEL: define void @system_atomic_store_unordered_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: store i32 [[VAL]], ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret void +; +; GFX1250-LABEL: define void @system_atomic_store_unordered_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: store atomic i32 [[VAL]], ptr [[SCRATCH_ASCAST]] unordered, align 4 +; GFX1250-NEXT: ret void +; + store atomic i32 %val, ptr addrspace(5) %addr unordered, align 4 + ret void +} + +define void @system_atomic_store_release_i32(ptr addrspace(5) %addr, i32 %val) { +; GFX1200-LABEL: define void @system_atomic_store_release_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: store i32 [[VAL]], ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret void +; +; GFX1250-LABEL: define void @system_atomic_store_release_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: store atomic i32 [[VAL]], ptr [[SCRATCH_ASCAST]] release, align 4 +; GFX1250-NEXT: ret void +; + store atomic i32 %val, ptr addrspace(5) %addr release, align 4 + ret void +} + +define void @workgroup_atomic_store_release_i32(ptr addrspace(5) %addr, i32 %val) { +; GFX1200-LABEL: define void @workgroup_atomic_store_release_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: store i32 [[VAL]], ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret void +; +; GFX1250-LABEL: define void @workgroup_atomic_store_release_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: store atomic i32 [[VAL]], ptr [[SCRATCH_ASCAST]] syncscope("workgroup") release, align 4 +; GFX1250-NEXT: ret void +; + store atomic i32 %val, ptr addrspace(5) %addr syncscope("workgroup") release, align 4 + ret void +} + +define float @system_atomic_load_unordered_float(ptr addrspace(5) %addr) { +; GFX1200-LABEL: define float @system_atomic_load_unordered_float( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[VAL:%.*]] = load float, ptr addrspace(5) [[ADDR]], align 4, !invariant.load [[META0:![0-9]+]], !nontemporal [[META1:![0-9]+]] +; GFX1200-NEXT: ret float [[VAL]] +; +; GFX1250-LABEL: define float @system_atomic_load_unordered_float( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = load atomic float, ptr [[SCRATCH_ASCAST]] unordered, align 4, !invariant.load [[META0:![0-9]+]], !nontemporal [[META1:![0-9]+]] +; GFX1250-NEXT: ret float [[VAL]] +; + %val = load atomic float, ptr addrspace(5) %addr unordered, align 4, !invariant.load !1, !nontemporal !0 + ret float %val +} + +define i32 @system_atomic_load_unordered_i32(ptr addrspace(5) %addr) { +; GFX1200-LABEL: define i32 @system_atomic_load_unordered_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret i32 [[VAL]] +; +; GFX1250-LABEL: define i32 @system_atomic_load_unordered_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = load atomic i32, ptr [[SCRATCH_ASCAST]] unordered, align 4 +; GFX1250-NEXT: ret i32 [[VAL]] +; + %val = load atomic i32, ptr addrspace(5) %addr unordered, align 4 + ret i32 %val +} + +define i32 @system_atomic_load_acquire_i32(ptr addrspace(5) %addr) { +; GFX1200-LABEL: define i32 @system_atomic_load_acquire_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret i32 [[VAL]] +; +; GFX1250-LABEL: define i32 @system_atomic_load_acquire_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = load atomic i32, ptr [[SCRATCH_ASCAST]] acquire, align 4 +; GFX1250-NEXT: ret i32 [[VAL]] +; + %val = load atomic i32, ptr addrspace(5) %addr acquire, align 4 + ret i32 %val +} + +define i32 @workgroup_atomic_load_acquire_i32(ptr addrspace(5) %addr) { +; GFX1200-LABEL: define i32 @workgroup_atomic_load_acquire_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret i32 [[VAL]] +; +; GFX1250-LABEL: define i32 @workgroup_atomic_load_acquire_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = load atomic i32, ptr [[SCRATCH_ASCAST]] syncscope("workgroup") acquire, align 4 +; GFX1250-NEXT: ret i32 [[VAL]] +; + %val = load atomic i32, ptr addrspace(5) %addr syncscope("workgroup") acquire, align 4 + ret i32 %val +} + +define i32 @system_atomic_cmpxchg_acq_rel_acquire_i32(ptr addrspace(5) %addr, i32 %old, i32 %in) { +; GFX1200-LABEL: define i32 @system_atomic_cmpxchg_acq_rel_acquire_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[OLD:%.*]], i32 [[IN:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], [[OLD]] +; GFX1200-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[IN]], i32 [[TMP1]] +; GFX1200-NEXT: store i32 [[TMP3]], ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: [[TMP4:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP1]], 0 +; GFX1200-NEXT: [[TMP5:%.*]] = insertvalue { i32, i1 } [[TMP4]], i1 [[TMP2]], 1 +; GFX1200-NEXT: [[RES:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 +; GFX1200-NEXT: ret i32 [[RES]] +; +; GFX1250-LABEL: define i32 @system_atomic_cmpxchg_acq_rel_acquire_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[OLD:%.*]], i32 [[IN:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = cmpxchg volatile ptr [[SCRATCH_ASCAST]], i32 [[OLD]], i32 [[IN]] acq_rel acquire, align 4, !nontemporal [[META1]] +; GFX1250-NEXT: [[RES:%.*]] = extractvalue { i32, i1 } [[VAL]], 0 +; GFX1250-NEXT: ret i32 [[RES]] +; + %val = cmpxchg volatile ptr addrspace(5) %addr, i32 %old, i32 %in acq_rel acquire, !nontemporal !0 + %res = extractvalue { i32, i1 } %val, 0 + ret i32 %res +} + +define i32 @system_atomicrmw_xchg_acq_rel_i32(ptr addrspace(5) %addr, i32 %in) { +; GFX1200-LABEL: define i32 @system_atomicrmw_xchg_acq_rel_i32( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[IN:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: store i32 [[IN]], ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret i32 [[TMP1]] +; +; GFX1250-LABEL: define i32 @system_atomicrmw_xchg_acq_rel_i32( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], i32 [[IN:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = atomicrmw volatile xchg ptr [[SCRATCH_ASCAST]], i32 [[IN]] acq_rel, align 4 +; GFX1250-NEXT: ret i32 [[VAL]] +; + %val = atomicrmw volatile xchg ptr addrspace(5) %addr, i32 %in acq_rel + ret i32 %val +} + +define i16 @system_atomicrmw_xchg_acq_rel_i16(ptr addrspace(5) %addr, i16 %in) { +; GFX1200-LABEL: define i16 @system_atomicrmw_xchg_acq_rel_i16( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], i16 [[IN:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[TMP1:%.*]] = load i16, ptr addrspace(5) [[ADDR]], align 2 +; GFX1200-NEXT: store i16 [[IN]], ptr addrspace(5) [[ADDR]], align 2 +; GFX1200-NEXT: ret i16 [[TMP1]] +; +; GFX1250-LABEL: define i16 @system_atomicrmw_xchg_acq_rel_i16( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], i16 [[IN:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = atomicrmw volatile xchg ptr [[SCRATCH_ASCAST]], i16 [[IN]] acq_rel, align 2 +; GFX1250-NEXT: ret i16 [[VAL]] +; + %val = atomicrmw volatile xchg ptr addrspace(5) %addr, i16 %in acq_rel + ret i16 %val +} + +define half @system_atomicrmw_fmax_acq_rel_half(ptr addrspace(5) %addr, half %in) { +; GFX1200-LABEL: define half @system_atomicrmw_fmax_acq_rel_half( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], half [[IN:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[TMP1:%.*]] = load half, ptr addrspace(5) [[ADDR]], align 2 +; GFX1200-NEXT: [[TMP2:%.*]] = call half @llvm.maxnum.f16(half [[TMP1]], half [[IN]]) +; GFX1200-NEXT: store half [[TMP2]], ptr addrspace(5) [[ADDR]], align 2 +; GFX1200-NEXT: ret half [[TMP1]] +; +; GFX1250-LABEL: define half @system_atomicrmw_fmax_acq_rel_half( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], half [[IN:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = atomicrmw volatile fmax ptr [[SCRATCH_ASCAST]], half [[IN]] acq_rel, align 2 +; GFX1250-NEXT: ret half [[VAL]] +; + %val = atomicrmw volatile fmax ptr addrspace(5) %addr, half %in acq_rel + ret half %val +} + +define float @system_atomicrmw_fminimum_acq_rel_float(ptr addrspace(5) %addr, float %in) { +; GFX1200-LABEL: define float @system_atomicrmw_fminimum_acq_rel_float( +; GFX1200-SAME: ptr addrspace(5) [[ADDR:%.*]], float [[IN:%.*]]) #[[ATTR0]] { +; GFX1200-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: [[TMP2:%.*]] = call float @llvm.minimum.f32(float [[TMP1]], float [[IN]]) +; GFX1200-NEXT: store float [[TMP2]], ptr addrspace(5) [[ADDR]], align 4 +; GFX1200-NEXT: ret float [[TMP1]] +; +; GFX1250-LABEL: define float @system_atomicrmw_fminimum_acq_rel_float( +; GFX1250-SAME: ptr addrspace(5) [[ADDR:%.*]], float [[IN:%.*]]) #[[ATTR0]] { +; GFX1250-NEXT: [[SCRATCH_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR]] to ptr +; GFX1250-NEXT: [[VAL:%.*]] = atomicrmw volatile fminimum ptr [[SCRATCH_ASCAST]], float [[IN]] acq_rel, align 4, !nontemporal [[META1]] +; GFX1250-NEXT: ret float [[VAL]] +; + %val = atomicrmw volatile fminimum ptr addrspace(5) %addr, float %in acq_rel, !nontemporal !0 + ret float %val +} + +!0 = !{} +!1 = !{i32 1} +;. +; GFX1200: [[META0]] = !{i32 1} +; GFX1200: [[META1]] = !{} +;. +; GFX1250: [[META0]] = !{i32 1} +; GFX1250: [[META1]] = !{} +;. diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll index 2e72d26ed456..585b4c753824 100644 --- a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll +++ b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -passes=atomic-expand -codegen-opt-level=1 %s | FileCheck %s define i8 @test_atomic_xchg_i8(ptr %ptr, i8 %xchgend) { @@ -221,49 +222,40 @@ define i8 @test_atomic_umin_i8(ptr %ptr, i8 %uminend) { define i8 @test_cmpxchg_i8_seqcst_seqcst(ptr %ptr, i8 %desired, i8 %newval) { ; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst ; CHECK: br label %[[START:.*]] - ; CHECK: [[START]]: ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - ; CHECK: [[FENCED_STORE]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[LOADED_LOOP:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD]] - ; CHECK: [[RELEASED_LOAD]]: ; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i8 ; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i8 [[OLDVAL_LOOP]], %desired -; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] - +; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB:cmpxchg\.nostore]] ; CHECK: [[SUCCESS_BB]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i8 [ [[OLDVAL]], %[[START]] ], [ [[OLDVAL_LOOP]], %[[RELEASED_LOAD]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK: [[LOADED_FAILURE:%.*]] = phi i8 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED:%.*]] = phi i8 [ [[LOADED_LOOP]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i8 [[LOADED]] - %pairold = cmpxchg ptr %ptr, i8 %desired, i8 %newval seq_cst seq_cst %old = extractvalue { i8, i1 } %pairold, 0 ret i8 %old @@ -272,49 +264,40 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(ptr %ptr, i8 %desired, i8 %newval) { define i16 @test_cmpxchg_i16_seqcst_monotonic(ptr %ptr, i16 %desired, i16 %newval) { ; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - ; CHECK: [[FENCED_STORE]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[LOADED_LOOP:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 -; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:.*]] - +; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:cmpxchg\.releasedload]] ; CHECK: [[RELEASED_LOAD]]: ; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i16 ; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i16 [[OLDVAL_LOOP]], %desired -; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] - +; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB:cmpxchg\.nostore]] ; CHECK: [[SUCCESS_BB]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i16 [ [[OLDVAL]], %[[START]] ], [ [[OLDVAL_LOOP]], %[[RELEASED_LOAD]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i16 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] ; CHECK-NOT: dmb ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED:%.*]] = phi i16 [ [[LOADED_LOOP]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i16 [[LOADED]] - %pairold = cmpxchg ptr %ptr, i16 %desired, i16 %newval seq_cst monotonic %old = extractvalue { i16, i1 } %pairold, 0 ret i16 %old @@ -324,40 +307,32 @@ define i32 @test_cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %desired, i32 %newval ; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire ; CHECK-NOT: dmb ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %ptr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired -; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - +; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:cmpxchg\.nostore]] ; CHECK: [[FENCED_STORE]]: ; CHECK-NEXT: br label %[[TRY_STORE:.*]] - ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 %newval, ptr elementtype(i32) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] - ; CHECK: [[SUCCESS_BB]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i32 [ [[OLDVAL]], %[[LOOP]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK: [[LOADED_FAILURE:%.*]] = phi i32 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED_EXIT:%.*]] = phi i32 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pairold = cmpxchg ptr %ptr, i32 %desired, i32 %newval acquire acquire %old = extractvalue { i32, i1 } %pairold, 0 ret i32 %old @@ -367,7 +342,6 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %ne ; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic ; CHECK-NOT: dmb ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr) ; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 @@ -377,11 +351,9 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %ne ; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 ; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired -; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - +; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:cmpxchg\.nostore]] ; CHECK: [[FENCED_STORE]]: ; CHECK-NEXT: br label %[[TRY_STORE:.*]] - ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i64 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32 @@ -390,26 +362,21 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %ne ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] - ; CHECK: [[SUCCESS_BB]]: ; CHECK-NOT: dmb ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK-NEXT: [[LOADED_NO_STORE:%.*]] = phi i64 [ [[OLDVAL]], %[[LOOP]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i64 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] ; CHECK-NOT: dmb ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED_EXIT:%.*]] = phi i64 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i64 [[LOADED_EXIT]] - %pairold = cmpxchg ptr %ptr, i64 %desired, i64 %newval monotonic monotonic %old = extractvalue { i64, i1 } %pairold, 0 ret i64 %old @@ -419,40 +386,32 @@ define i32 @test_cmpxchg_minsize(ptr %addr, i32 %desired, i32 %new) minsize { ; CHECK-LABEL: @test_cmpxchg_minsize ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[START:.*]] - ; CHECK: [[START]]: ; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired -; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - +; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:cmpxchg\.nostore]] ; CHECK: [[FENCED_STORE]]: ; CHECK-NEXT: br label %[[TRY_STORE:.*]] - ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] ; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr) ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[START]] - ; CHECK: [[SUCCESS_BB]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[END:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK: [[LOADED_NO_STORE:%.*]] = phi i32 [ [[LOADED]], %[[START]] ] ; CHECK: call void @llvm.arm.clrex() ; CHECK: br label %[[FAILURE_BB]] - ; CHECK: [[FAILURE_BB]]: ; CHECK: [[LOADED_FAILURE:%.*]] = phi i32 [ [[LOADED_NO_STORE]], %[[NO_STORE_BB]] ] ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[END]] - ; CHECK: [[END]]: ; CHECK: [[LOADED_EXIT:%.*]] = phi i32 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pair = cmpxchg ptr %addr, i32 %desired, i32 %new seq_cst seq_cst %oldval = extractvalue { i32, i1 } %pair, 0 ret i32 %oldval diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll index 10073e23f5d4..98539ffcde32 100644 --- a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll +++ b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -o - -mtriple=armv8-linux-gnueabihf -passes=atomic-expand %s -codegen-opt-level=1 | FileCheck %s define i8 @test_atomic_xchg_i8(ptr %ptr, i8 %xchgend) { @@ -84,42 +85,34 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(ptr %ptr, i8 %desired, i8 %newval) { ; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired -; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - +; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:cmpxchg.nostore]] ; CHECK: [[FENCED_STORE]]: ; CHECK-NEXT: br label %[[TRY_STORE:.*]] - ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] - ; CHECK: [[SUCCESS_BB]]: ; CHECK-NOT: fence_cst ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK-NEXT: [[LOADED_NOSTORE:%.*]] = phi i8 [ [[OLDVAL]], %[[LOOP]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i8 [ [[LOADED_NOSTORE]], %[[NO_STORE_BB]] ] ; CHECK-NOT: fence_cst ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED_EXIT:%.*]] = phi i8 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i8 [[LOADED_EXIT]] - %pairold = cmpxchg ptr %ptr, i8 %desired, i8 %newval seq_cst seq_cst %old = extractvalue { i8, i1 } %pairold, 0 ret i8 %old @@ -129,43 +122,35 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(ptr %ptr, i16 %desired, i16 %newva ; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired -; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - +; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:cmpxchg.nostore]] ; CHECK: [[FENCED_STORE]]: ; CHECK-NEXT: br label %[[TRY_STORE:.*]] - ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] - ; CHECK: [[SUCCESS_BB]]: ; CHECK-NOT: fence ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; The PHI is not required. ; CHECK-NEXT: [[LOADED_NOSTORE:%.*]] = phi i16 [ [[OLDVAL]], %[[LOOP]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i16 [ [[LOADED_NOSTORE]], %[[NO_STORE_BB]] ] ; CHECK-NOT: fence ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED_EXIT:%.*]] = phi i16 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i16 [[LOADED_EXIT]] - %pairold = cmpxchg ptr %ptr, i16 %desired, i16 %newval seq_cst monotonic %old = extractvalue { i16, i1 } %pairold, 0 ret i16 %old @@ -175,40 +160,32 @@ define i32 @test_cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %desired, i32 %newval ; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %ptr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired -; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - +; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:cmpxchg.nostore]] ; CHECK: [[FENCED_STORE]]: ; CHECK-NEXT: br label %[[TRY_STORE:.*]] - ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 %newval, ptr elementtype(i32) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] - ; CHECK: [[SUCCESS_BB]]: ; CHECK-NOT: fence_cst ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK-NEXT: [[LOADED_NOSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[LOOP]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i32 [ [[LOADED_NOSTORE]], %[[NO_STORE_BB]] ] ; CHECK-NOT: fence_cst ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED_EXIT:%.*]] = phi i32 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pairold = cmpxchg ptr %ptr, i32 %desired, i32 %newval acquire acquire %old = extractvalue { i32, i1 } %pairold, 0 ret i32 %old @@ -218,7 +195,6 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %ne ; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] - ; CHECK: [[LOOP]]: ; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr) ; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 @@ -228,11 +204,9 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %ne ; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32 ; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]] ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired -; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] - +; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:cmpxchg.nostore]] ; CHECK: [[FENCED_STORE]]: ; CHECK-NEXT: br label %[[TRY_STORE:.*]] - ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i64 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32 @@ -241,26 +215,21 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %ne ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] - ; CHECK: [[SUCCESS_BB]]: ; CHECK-NOT: fence_cst ; CHECK: br label %[[DONE:.*]] - ; CHECK: [[NO_STORE_BB]]: ; CHECK-NEXT: [[LOADED_NOSTORE:%.*]] = phi i64 [ [[OLDVAL]], %[[LOOP]] ] ; CHECK-NEXT: call void @llvm.arm.clrex() ; CHECK-NEXT: br label %[[FAILURE_BB:.*]] - ; CHECK: [[FAILURE_BB]]: ; CHECK-NEXT: [[LOADED_FAILURE:%.*]] = phi i64 [ [[LOADED_NOSTORE]], %[[NO_STORE_BB]] ] ; CHECK-NOT: fence_cst ; CHECK: br label %[[DONE]] - ; CHECK: [[DONE]]: ; CHECK: [[LOADED_EXIT:%.*]] = phi i64 [ [[LOADED_TRYSTORE]], %[[SUCCESS_BB]] ], [ [[LOADED_FAILURE]], %[[FAILURE_BB]] ] ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i64 [[LOADED_EXIT]] - %pairold = cmpxchg ptr %ptr, i64 %desired, i64 %newval monotonic monotonic %old = extractvalue { i64, i1 } %pairold, 0 ret i64 %old diff --git a/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll b/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll index 8195a5b6145e..aff4196815e2 100644 --- a/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll +++ b/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll @@ -9,7 +9,7 @@ define i32 @test_cmpxchg_seq_cst(ptr %addr, i32 %desired, i32 %new) { ; CHECK: [[CMPXCHG_START]]: ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SHOULD_STORE:%.*]] = icmp eq i32 [[TMP1]], [[DESIRED]] -; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:.*]] +; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:cmpxchg.nostore]] ; CHECK: [[CMPXCHG_FENCEDSTORE]]: ; CHECK-NEXT: call void @llvm.arm.dmb(i32 10) ; CHECK-NEXT: br label %[[CMPXCHG_TRYSTORE:.*]] @@ -17,7 +17,7 @@ define i32 @test_cmpxchg_seq_cst(ptr %addr, i32 %desired, i32 %new) { ; CHECK-NEXT: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[TMP1]], %[[CMPXCHG_FENCEDSTORE]] ] ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEW]], ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i32 [[TMP2]], 0 -; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:.*]] +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:cmpxchg.failure]] ; CHECK: [[CMPXCHG_RELEASEDLOAD:.*:]] ; CHECK-NEXT: unreachable ; CHECK: [[CMPXCHG_SUCCESS]]: @@ -48,7 +48,7 @@ define i1 @test_cmpxchg_weak_fail(ptr %addr, i32 %desired, i32 %new) { ; CHECK: [[CMPXCHG_START]]: ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SHOULD_STORE:%.*]] = icmp eq i32 [[TMP1]], [[DESIRED]] -; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:.*]] +; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:cmpxchg.nostore]] ; CHECK: [[CMPXCHG_FENCEDSTORE]]: ; CHECK-NEXT: call void @llvm.arm.dmb(i32 10) ; CHECK-NEXT: br label %[[CMPXCHG_TRYSTORE:.*]] @@ -56,7 +56,7 @@ define i1 @test_cmpxchg_weak_fail(ptr %addr, i32 %desired, i32 %new) { ; CHECK-NEXT: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[TMP1]], %[[CMPXCHG_FENCEDSTORE]] ] ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEW]], ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i32 [[TMP2]], 0 -; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:.*]] +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:cmpxchg.failure]] ; CHECK: [[CMPXCHG_RELEASEDLOAD:.*:]] ; CHECK-NEXT: unreachable ; CHECK: [[CMPXCHG_SUCCESS]]: @@ -86,14 +86,14 @@ define i32 @test_cmpxchg_monotonic(ptr %addr, i32 %desired, i32 %new) { ; CHECK: [[CMPXCHG_START]]: ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SHOULD_STORE:%.*]] = icmp eq i32 [[TMP1]], [[DESIRED]] -; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:.*]] +; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:cmpxchg.nostore]] ; CHECK: [[CMPXCHG_FENCEDSTORE]]: ; CHECK-NEXT: br label %[[CMPXCHG_TRYSTORE:.*]] ; CHECK: [[CMPXCHG_TRYSTORE]]: ; CHECK-NEXT: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[TMP1]], %[[CMPXCHG_FENCEDSTORE]] ] ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEW]], ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i32 [[TMP2]], 0 -; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:.*]] +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:cmpxchg.failure]] ; CHECK: [[CMPXCHG_RELEASEDLOAD:.*:]] ; CHECK-NEXT: unreachable ; CHECK: [[CMPXCHG_SUCCESS]]: @@ -122,7 +122,7 @@ define i32 @test_cmpxchg_seq_cst_minsize(ptr %addr, i32 %desired, i32 %new) mins ; CHECK: [[CMPXCHG_START]]: ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SHOULD_STORE:%.*]] = icmp eq i32 [[TMP1]], [[DESIRED]] -; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:.*]] +; CHECK-NEXT: br i1 [[SHOULD_STORE]], label %[[CMPXCHG_FENCEDSTORE:.*]], label %[[CMPXCHG_NOSTORE:cmpxchg.nostore]] ; CHECK: [[CMPXCHG_FENCEDSTORE]]: ; CHECK-NEXT: call void @llvm.arm.dmb(i32 10) ; CHECK-NEXT: br label %[[CMPXCHG_TRYSTORE:.*]] @@ -130,7 +130,7 @@ define i32 @test_cmpxchg_seq_cst_minsize(ptr %addr, i32 %desired, i32 %new) mins ; CHECK-NEXT: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[TMP1]], %[[CMPXCHG_FENCEDSTORE]] ] ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEW]], ptr elementtype(i32) [[ADDR]]) ; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i32 [[TMP2]], 0 -; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:.*]] +; CHECK-NEXT: br i1 [[SUCCESS]], label %[[CMPXCHG_SUCCESS:.*]], label %[[CMPXCHG_FAILURE:cmpxchg.failure]] ; CHECK: [[CMPXCHG_RELEASEDLOAD:.*:]] ; CHECK-NEXT: unreachable ; CHECK: [[CMPXCHG_SUCCESS]]: |