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Diffstat (limited to 'llvm/test/MC/AMDGPU/gfx90a_err.s')
-rw-r--r--llvm/test/MC/AMDGPU/gfx90a_err.s10
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/MC/AMDGPU/gfx90a_err.s b/llvm/test/MC/AMDGPU/gfx90a_err.s
index a05c7fb1cc1c..ff0dfb371bbb 100644
--- a/llvm/test/MC/AMDGPU/gfx90a_err.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_err.s
@@ -154,10 +154,10 @@ v_ceil_f64_dpp v[0:1], v[2:3] row_share:1 row_mask:0xf bank_mask:0xf
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
flat_atomic_add v2, v[2:3], a2 glc
-// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: data and dst should be all VGPR or AGPR
+// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
flat_atomic_add a2, v[2:3], v2 glc
-// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: data and dst should be all VGPR or AGPR
+// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
tbuffer_store_format_xyzw v[0:3], off, s[4:7], dfmt:15, nfmt:2, s1 tfe
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
@@ -166,13 +166,13 @@ buffer_store_dwordx4 v[0:3], off, s[12:15], s4 offset:4095 glc tfe
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
ds_write2_b64 v1, a[4:5], v[2:3] offset1:255
-// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: data and dst should be all VGPR or AGPR
+// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
ds_write2_b64 v1, v[4:5], a[2:3] offset1:255
-// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: data and dst should be all VGPR or AGPR
+// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
ds_wrxchg2st64_rtn_b32 v[6:7], v1, a2, a3 offset0:127
-// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register class: data and dst should be all VGPR or AGPR
+// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
image_load v[0:4], v2, s[0:7] dmask:0xf unorm tfe
// GFX90A: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction