diff options
Diffstat (limited to 'llvm/test/CodeGen')
43 files changed, 1506 insertions, 3730 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll index e3228162be22..7e6f500181ec 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll @@ -9,7 +9,7 @@ declare hidden void @external_void_func_v16i32_v16i32_v4i32(<16 x i32>, <16 x i32>, <4 x i32>) #0 declare hidden void @external_void_func_byval(ptr addrspace(5) byval([16 x i32])) #0 -define amdgpu_kernel void @kernel_caller_stack() { +define amdgpu_kernel void @kernel_caller_stack() #2 { ; MUBUF-LABEL: kernel_caller_stack: ; MUBUF: ; %bb.0: ; MUBUF-NEXT: s_add_u32 flat_scratch_lo, s12, s17 @@ -57,7 +57,7 @@ define amdgpu_kernel void @kernel_caller_stack() { ret void } -define amdgpu_kernel void @kernel_caller_byval() { +define amdgpu_kernel void @kernel_caller_byval() #2 { ; MUBUF-LABEL: kernel_caller_byval: ; MUBUF: ; %bb.0: ; MUBUF-NEXT: s_add_u32 flat_scratch_lo, s12, s17 @@ -213,7 +213,7 @@ define amdgpu_kernel void @kernel_caller_byval() { ret void } -define void @func_caller_stack() { +define void @func_caller_stack() #2 { ; MUBUF-LABEL: func_caller_stack: ; MUBUF: ; %bb.0: ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -222,11 +222,11 @@ define void @func_caller_stack() { ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] -; MUBUF-NEXT: v_writelane_b32 v40, s4, 2 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: v_mov_b32_e32 v0, 9 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; MUBUF-NEXT: v_mov_b32_e32 v0, 10 +; MUBUF-NEXT: v_writelane_b32 v40, s4, 2 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; MUBUF-NEXT: v_mov_b32_e32 v0, 11 ; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 @@ -257,8 +257,8 @@ define void @func_caller_stack() { ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] -; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 ; FLATSCR-NEXT: s_add_u32 s0, s32, 4 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 9 ; FLATSCR-NEXT: scratch_store_dword off, v0, s0 @@ -291,7 +291,7 @@ define void @func_caller_stack() { ret void } -define void @func_caller_byval(ptr addrspace(5) %argptr) { +define void @func_caller_byval(ptr addrspace(5) %argptr) #2 { ; MUBUF-LABEL: func_caller_byval: ; MUBUF: ; %bb.0: ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -300,10 +300,10 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) { ; MUBUF-NEXT: s_or_saveexec_b64 s[6:7], -1 ; MUBUF-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; MUBUF-NEXT: s_mov_b64 exec, s[6:7] -; MUBUF-NEXT: v_writelane_b32 v40, s4, 2 ; MUBUF-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v2, v0, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 +; MUBUF-NEXT: v_writelane_b32 v40, s4, 2 ; MUBUF-NEXT: v_writelane_b32 v40, s30, 0 ; MUBUF-NEXT: s_getpc_b64 s[4:5] ; MUBUF-NEXT: s_add_u32 s4, s4, external_void_func_byval@rel32@lo+4 @@ -382,9 +382,9 @@ define void @func_caller_byval(ptr addrspace(5) %argptr) { ; FLATSCR-NEXT: s_or_saveexec_b64 s[2:3], -1 ; FLATSCR-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; FLATSCR-NEXT: s_mov_b64 exec, s[2:3] -; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 ; FLATSCR-NEXT: scratch_load_dwordx2 v[1:2], v0, off ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 +; FLATSCR-NEXT: v_writelane_b32 v40, s0, 2 ; FLATSCR-NEXT: v_writelane_b32 v40, s30, 0 ; FLATSCR-NEXT: s_getpc_b64 s[0:1] ; FLATSCR-NEXT: s_add_u32 s0, s0, external_void_func_byval@rel32@lo+4 @@ -432,3 +432,4 @@ declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } attributes #1 = { argmemonly nofree nounwind willreturn writeonly } +attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll index b17324a38ada..2e8f8f67bc5e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll @@ -5,7 +5,7 @@ @gv = external addrspace(4) constant i32 -define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align4(i32 %n) { +define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align4(i32 %n) #0 { ; GFX9-LABEL: kernel_dynamic_stackalloc_sgpr_align4: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s5, s[8:9], 0x0 @@ -63,7 +63,7 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align4(i32 %n) { ret void } -define void @func_dynamic_stackalloc_sgpr_align4() { +define void @func_dynamic_stackalloc_sgpr_align4() #0 { ; GFX9-LABEL: func_dynamic_stackalloc_sgpr_align4: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -146,7 +146,7 @@ define void @func_dynamic_stackalloc_sgpr_align4() { ret void } -define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align16(i32 %n) { +define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align16(i32 %n) #0 { ; GFX9-LABEL: kernel_dynamic_stackalloc_sgpr_align16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s5, s[8:9], 0x0 @@ -204,7 +204,7 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align16(i32 %n) { ret void } -define void @func_dynamic_stackalloc_sgpr_align16() { +define void @func_dynamic_stackalloc_sgpr_align16() #0 { ; GFX9-LABEL: func_dynamic_stackalloc_sgpr_align16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -287,7 +287,7 @@ define void @func_dynamic_stackalloc_sgpr_align16() { ret void } -define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align32(i32 %n) { +define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align32(i32 %n) #0 { ; GFX9-LABEL: kernel_dynamic_stackalloc_sgpr_align32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dword s4, s[8:9], 0x0 @@ -348,7 +348,7 @@ define amdgpu_kernel void @kernel_dynamic_stackalloc_sgpr_align32(i32 %n) { ret void } -define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { +define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) #0 { ; GFX9-LABEL: func_dynamic_stackalloc_sgpr_align32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -363,6 +363,7 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX9-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: s_mov_b32 s33, s6 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX9-NEXT: s_add_u32 s5, s32, 0x7ff @@ -376,7 +377,6 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX9-NEXT: s_add_u32 s32, s5, s4 ; GFX9-NEXT: s_mov_b32 s32, s34 ; GFX9-NEXT: s_mov_b32 s34, s7 -; GFX9-NEXT: s_mov_b32 s33, s6 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -394,6 +394,7 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX10-NEXT: s_addc_u32 s5, s5, gv@gotpcrel32@hi+12 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_add_u32 s5, s32, 0x3ff @@ -407,7 +408,6 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX10-NEXT: s_add_u32 s32, s5, s4 ; GFX10-NEXT: s_mov_b32 s32, s34 ; GFX10-NEXT: s_mov_b32 s34, s7 -; GFX10-NEXT: s_mov_b32 s33, s6 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: func_dynamic_stackalloc_sgpr_align32: @@ -424,6 +424,7 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX11-NEXT: s_addc_u32 s1, s1, gv@gotpcrel32@hi+12 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_mov_b32 s33, s2 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_add_u32 s1, s32, 0x3ff @@ -438,10 +439,11 @@ define void @func_dynamic_stackalloc_sgpr_align32(ptr addrspace(1) %out) { ; GFX11-NEXT: s_add_u32 s32, s1, s0 ; GFX11-NEXT: s_mov_b32 s32, s34 ; GFX11-NEXT: s_mov_b32 s34, s3 -; GFX11-NEXT: s_mov_b32 s33, s2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %n = load i32, ptr addrspace(4) @gv %alloca = alloca i32, i32 %n, align 32, addrspace(5) store i32 0, ptr addrspace(5) %alloca ret void } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll index c100d653c1cd..72766f47030c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll @@ -4,7 +4,7 @@ ; Test the localizer did something and we don't materialize all ; constants in SGPRs in the entry block. -define amdgpu_kernel void @localize_constants(i1 %cond) { +define amdgpu_kernel void @localize_constants(i1 %cond) #0 { ; GFX9-LABEL: localize_constants: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_load_dword s1, s[8:9], 0x0 @@ -91,7 +91,7 @@ bb2: @gv2 = addrspace(1) global i32 poison, align 4 @gv3 = addrspace(1) global i32 poison, align 4 -define amdgpu_kernel void @localize_globals(i1 %cond) { +define amdgpu_kernel void @localize_globals(i1 %cond) #0 { ; GFX9-LABEL: localize_globals: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_load_dword s1, s[8:9], 0x0 @@ -162,7 +162,7 @@ bb2: @static.gv2 = internal addrspace(1) global i32 poison, align 4 @static.gv3 = internal addrspace(1) global i32 poison, align 4 -define void @localize_internal_globals(i1 %cond) { +define void @localize_internal_globals(i1 %cond) #0 { ; GFX9-LABEL: localize_internal_globals: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -226,7 +226,7 @@ bb2: } ; This would crash from using the wrong insert point -define void @sink_null_insert_pt(ptr addrspace(4) %arg0) { +define void @sink_null_insert_pt(ptr addrspace(4) %arg0) #0 { ; GFX9-LABEL: sink_null_insert_pt: ; GFX9: ; %bb.0: ; %entry ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -235,11 +235,11 @@ define void @sink_null_insert_pt(ptr addrspace(4) %arg0) { ; GFX9-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-NEXT: v_writelane_b32 v40, s16, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dword v0, v[0:1], off glc ; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_writelane_b32 v40, s16, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 @@ -262,3 +262,5 @@ bb1: call void null() ret void } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll index 9839af011ecd..8bef60523e9a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll @@ -10,7 +10,7 @@ ; FIXME: FunctionLoweringInfo unhelpfully doesn't preserve an ; alignment less than the stack alignment. -define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) { +define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) #1 { ; GCN-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_load_dword s4, s[8:9], 0x8 @@ -82,7 +82,7 @@ bb.2: ; ASSUME1024: .amdhsa_private_segment_fixed_size 1040 ; ASSUME1024: ; ScratchSize: 1040 -define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) { +define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) #1 { ; GCN-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_load_dword s4, s[8:9], 0x8 @@ -146,13 +146,13 @@ bb.1: ; ASSUME1024: ; ScratchSize: 1088 -define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) { +define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) #1 { ; GCN-LABEL: func_non_entry_block_static_alloca_align4: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s7, s33 -; GCN-NEXT: s_mov_b32 s33, s32 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 +; GCN-NEXT: s_mov_b32 s33, s32 ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_cbranch_execz .LBB2_3 @@ -210,16 +210,16 @@ bb.2: ret void } -define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) { +define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) #1 { ; GCN-LABEL: func_non_entry_block_static_alloca_align64: ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s7, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xfc0 ; GCN-NEXT: s_mov_b32 s8, s34 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffff000 ; GCN-NEXT: s_mov_b32 s34, s32 -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_addk_i32 s32, 0x2000 ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_cbranch_execz .LBB3_2 @@ -272,6 +272,7 @@ bb.1: declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone speculatable } +attributes #1 = { nounwind } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; ASSUME1024: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir index 6e5f8aceaf16..8cdb0f215396 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir @@ -4,7 +4,7 @@ --- | define amdgpu_kernel void @agpr_spill_copy() #0 { ret void } - attributes #0 = { "amdgpu-waves-per-eu"="8,8" } + attributes #0 = { "amdgpu-waves-per-eu"="8,8" nounwind } --- name: agpr_spill_copy tracksRegLiveness: true @@ -18,54 +18,6 @@ body: | ; GFX942-LABEL: name: agpr_spill_copy ; GFX942: liveins: $agpr30, $agpr31 ; GFX942-NEXT: {{ $}} - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 - ; GFX942-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 ; GFX942-NEXT: renamable $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27 = IMPLICIT_DEF ; GFX942-NEXT: renamable $agpr28_agpr29 = IMPLICIT_DEF ; GFX942-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll index eb6482401f76..149b0cb4e052 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll @@ -4,7 +4,7 @@ declare amdgpu_gfx_whole_wave i32 @good_callee(i1 %active, i32 %x, i32 %y, i32 inreg %c) -define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr) { +define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr) #0 { ; DAGISEL-LABEL: basic_test: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -22,9 +22,9 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr) ; DAGISEL-NEXT: s_clause 0x1 ; DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; DAGISEL-NEXT: scratch_store_b32 off, v41, s33 -; DAGISEL-NEXT: v_writelane_b32 v42, s30, 0 ; DAGISEL-NEXT: v_dual_mov_b32 v41, v2 :: v_dual_mov_b32 v40, v1 ; DAGISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 +; DAGISEL-NEXT: v_writelane_b32 v42, s30, 0 ; DAGISEL-NEXT: s_mov_b32 s1, good_callee@abs32@hi ; DAGISEL-NEXT: s_mov_b32 s0, good_callee@abs32@lo ; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16 @@ -65,9 +65,9 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr) ; GISEL-NEXT: s_clause 0x1 ; GISEL-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GISEL-NEXT: scratch_store_b32 off, v41, s33 -; GISEL-NEXT: v_writelane_b32 v42, s30, 0 ; GISEL-NEXT: v_dual_mov_b32 v40, v1 :: v_dual_mov_b32 v41, v2 ; GISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 +; GISEL-NEXT: v_writelane_b32 v42, s30, 0 ; GISEL-NEXT: s_mov_b32 s0, good_callee@abs32@lo ; GISEL-NEXT: s_mov_b32 s1, good_callee@abs32@hi ; GISEL-NEXT: s_add_co_i32 s32, s32, 16 @@ -96,7 +96,7 @@ define amdgpu_gfx void @basic_test(i32 %x, i32 inreg %c, ptr addrspace(1) %ptr) ret void } -define amdgpu_gfx i32 @tail_call_from_gfx(i32 %x, i32 inreg %c) { +define amdgpu_gfx i32 @tail_call_from_gfx(i32 %x, i32 inreg %c) #0 { ; DAGISEL-LABEL: tail_call_from_gfx: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -127,7 +127,7 @@ define amdgpu_gfx i32 @tail_call_from_gfx(i32 %x, i32 inreg %c) { ret i32 %ret } -define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x, i32 inreg %c) { +define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x, i32 inreg %c) #0 { ; DAGISEL-LABEL: tail_call_from_whole_wave: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -138,291 +138,152 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x, ; DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; DAGISEL-NEXT: s_clause 0x1f ; DAGISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; DAGISEL-NEXT: s_clause 0xf ; DAGISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 -; DAGISEL-NEXT: ; meta instruction ; DAGISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; DAGISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 @@ -592,291 +453,152 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x, ; GISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v0, s32 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 ; GISEL-NEXT: s_clause 0x1f ; GISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 ; GISEL-NEXT: s_clause 0xf ; GISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 -; GISEL-NEXT: ; meta instruction ; GISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 ; GISEL-NEXT: s_mov_b32 exec_lo, -1 ; GISEL-NEXT: v_add_nc_u32_e32 v1, 13, v0 @@ -1042,7 +764,7 @@ define amdgpu_gfx_whole_wave i32 @tail_call_from_whole_wave(i1 %active, i32 %x, declare amdgpu_gfx_whole_wave void @void_callee(i1 %active, i32 %x) -define amdgpu_gfx void @ret_void(i32 %x) { +define amdgpu_gfx void @ret_void(i32 %x) #0 { ; DAGISEL-LABEL: ret_void: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -1057,10 +779,10 @@ define amdgpu_gfx void @ret_void(i32 %x) { ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_mov_b32 exec_lo, s1 ; DAGISEL-NEXT: v_writelane_b32 v40, s0, 2 -; DAGISEL-NEXT: v_writelane_b32 v40, s30, 0 ; DAGISEL-NEXT: s_mov_b32 s1, void_callee@abs32@hi ; DAGISEL-NEXT: s_mov_b32 s0, void_callee@abs32@lo ; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16 +; DAGISEL-NEXT: v_writelane_b32 v40, s30, 0 ; DAGISEL-NEXT: v_writelane_b32 v40, s31, 1 ; DAGISEL-NEXT: s_wait_alu 0xfffe ; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -1092,10 +814,10 @@ define amdgpu_gfx void @ret_void(i32 %x) { ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_mov_b32 exec_lo, s1 ; GISEL-NEXT: v_writelane_b32 v40, s0, 2 -; GISEL-NEXT: v_writelane_b32 v40, s30, 0 ; GISEL-NEXT: s_mov_b32 s0, void_callee@abs32@lo ; GISEL-NEXT: s_mov_b32 s1, void_callee@abs32@hi ; GISEL-NEXT: s_add_co_i32 s32, s32, 16 +; GISEL-NEXT: v_writelane_b32 v40, s30, 0 ; GISEL-NEXT: v_writelane_b32 v40, s31, 1 ; GISEL-NEXT: s_wait_alu 0xfffe ; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -1116,3 +838,4 @@ define amdgpu_gfx void @ret_void(i32 %x) { ret void } +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll index d821801677d7..c794168c4007 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll @@ -8,7 +8,7 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s -define <32 x float> @bitcast_v32i32_to_v32f32(<32 x i32> %a, i32 %b) { +define <32 x float> @bitcast_v32i32_to_v32f32(<32 x i32> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v32f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -227,7 +227,7 @@ end: ret <32 x float> %phi } -define inreg <32 x float> @bitcast_v32i32_to_v32f32_scalar(<32 x i32> inreg %a, i32 inreg %b) { +define inreg <32 x float> @bitcast_v32i32_to_v32f32_scalar(<32 x i32> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v32f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -547,7 +547,7 @@ end: ret <32 x float> %phi } -define <32 x i32> @bitcast_v32f32_to_v32i32(<32 x float> %a, i32 %b) { +define <32 x i32> @bitcast_v32f32_to_v32i32(<32 x float> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v32i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -750,7 +750,7 @@ end: ret <32 x i32> %phi } -define inreg <32 x i32> @bitcast_v32f32_to_v32i32_scalar(<32 x float> inreg %a, i32 inreg %b) { +define inreg <32 x i32> @bitcast_v32f32_to_v32i32_scalar(<32 x float> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v32i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1054,7 +1054,7 @@ end: ret <32 x i32> %phi } -define <16 x i64> @bitcast_v32i32_to_v16i64(<32 x i32> %a, i32 %b) { +define <16 x i64> @bitcast_v32i32_to_v16i64(<32 x i32> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v16i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1273,7 +1273,7 @@ end: ret <16 x i64> %phi } -define inreg <16 x i64> @bitcast_v32i32_to_v16i64_scalar(<32 x i32> inreg %a, i32 inreg %b) { +define inreg <16 x i64> @bitcast_v32i32_to_v16i64_scalar(<32 x i32> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v16i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1593,7 +1593,7 @@ end: ret <16 x i64> %phi } -define <32 x i32> @bitcast_v16i64_to_v32i32(<16 x i64> %a, i32 %b) { +define <32 x i32> @bitcast_v16i64_to_v32i32(<16 x i64> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v32i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1820,7 +1820,7 @@ end: ret <32 x i32> %phi } -define inreg <32 x i32> @bitcast_v16i64_to_v32i32_scalar(<16 x i64> inreg %a, i32 inreg %b) { +define inreg <32 x i32> @bitcast_v16i64_to_v32i32_scalar(<16 x i64> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v32i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2148,7 +2148,7 @@ end: ret <32 x i32> %phi } -define <16 x double> @bitcast_v32i32_to_v16f64(<32 x i32> %a, i32 %b) { +define <16 x double> @bitcast_v32i32_to_v16f64(<32 x i32> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v16f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2367,7 +2367,7 @@ end: ret <16 x double> %phi } -define inreg <16 x double> @bitcast_v32i32_to_v16f64_scalar(<32 x i32> inreg %a, i32 inreg %b) { +define inreg <16 x double> @bitcast_v32i32_to_v16f64_scalar(<32 x i32> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v16f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2687,7 +2687,7 @@ end: ret <16 x double> %phi } -define <32 x i32> @bitcast_v16f64_to_v32i32(<16 x double> %a, i32 %b) { +define <32 x i32> @bitcast_v16f64_to_v32i32(<16 x double> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v32i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2842,7 +2842,7 @@ end: ret <32 x i32> %phi } -define inreg <32 x i32> @bitcast_v16f64_to_v32i32_scalar(<16 x double> inreg %a, i32 inreg %b) { +define inreg <32 x i32> @bitcast_v16f64_to_v32i32_scalar(<16 x double> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v32i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -3101,7 +3101,7 @@ end: ret <32 x i32> %phi } -define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) { +define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -7456,7 +7456,7 @@ end: ret <128 x i8> %phi } -define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i32 inreg %b) { +define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v128i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -10668,11 +10668,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v16, s32 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v17, s32 offset:4 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v16, s30, 0 @@ -11627,7 +11624,7 @@ end: ret <128 x i8> %phi } -define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) { +define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v32i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -17411,7 +17408,7 @@ end: ret <32 x i32> %phi } -define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i32 inreg %b) { +define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v32i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -22581,7 +22578,7 @@ end: ret <32 x i32> %phi } -define <64 x bfloat> @bitcast_v32i32_to_v64bf16(<32 x i32> %a, i32 %b) { +define <64 x bfloat> @bitcast_v32i32_to_v64bf16(<32 x i32> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v64bf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -23482,7 +23479,7 @@ end: ret <64 x bfloat> %phi } -define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a, i32 inreg %b) { +define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v64bf16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -24331,7 +24328,7 @@ end: ret <64 x bfloat> %phi } -define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) { +define <32 x i32> @bitcast_v64bf16_to_v32i32(<64 x bfloat> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v32i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -27305,7 +27302,7 @@ end: ret <32 x i32> %phi } -define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a, i32 inreg %b) { +define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v32i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -31035,7 +31032,7 @@ end: ret <32 x i32> %phi } -define <64 x half> @bitcast_v32i32_to_v64f16(<32 x i32> %a, i32 %b) { +define <64 x half> @bitcast_v32i32_to_v64f16(<32 x i32> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v64f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -31997,7 +31994,7 @@ end: ret <64 x half> %phi } -define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i32 inreg %b) { +define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -32841,7 +32838,7 @@ end: ret <64 x half> %phi } -define <32 x i32> @bitcast_v64f16_to_v32i32(<64 x half> %a, i32 %b) { +define <32 x i32> @bitcast_v64f16_to_v32i32(<64 x half> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v32i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -33855,7 +33852,7 @@ end: ret <32 x i32> %phi } -define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i32 inreg %b) { +define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v32i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -34999,7 +34996,7 @@ end: ret <32 x i32> %phi } -define <64 x i16> @bitcast_v32i32_to_v64i16(<32 x i32> %a, i32 %b) { +define <64 x i16> @bitcast_v32i32_to_v64i16(<32 x i32> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v64i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -35559,7 +35556,7 @@ end: ret <64 x i16> %phi } -define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i32 inreg %b) { +define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32i32_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -36230,7 +36227,7 @@ end: ret <64 x i16> %phi } -define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) { +define <32 x i32> @bitcast_v64i16_to_v32i32(<64 x i16> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v32i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -37037,7 +37034,7 @@ end: ret <32 x i32> %phi } -define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i32 inreg %b) { +define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v32i32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -38049,7 +38046,7 @@ end: ret <32 x i32> %phi } -define <16 x i64> @bitcast_v32f32_to_v16i64(<32 x float> %a, i32 %b) { +define <16 x i64> @bitcast_v32f32_to_v16i64(<32 x float> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v16i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -38252,7 +38249,7 @@ end: ret <16 x i64> %phi } -define inreg <16 x i64> @bitcast_v32f32_to_v16i64_scalar(<32 x float> inreg %a, i32 inreg %b) { +define inreg <16 x i64> @bitcast_v32f32_to_v16i64_scalar(<32 x float> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v16i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -38556,7 +38553,7 @@ end: ret <16 x i64> %phi } -define <32 x float> @bitcast_v16i64_to_v32f32(<16 x i64> %a, i32 %b) { +define <32 x float> @bitcast_v16i64_to_v32f32(<16 x i64> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v32f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -38783,7 +38780,7 @@ end: ret <32 x float> %phi } -define inreg <32 x float> @bitcast_v16i64_to_v32f32_scalar(<16 x i64> inreg %a, i32 inreg %b) { +define inreg <32 x float> @bitcast_v16i64_to_v32f32_scalar(<16 x i64> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v32f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -39111,7 +39108,7 @@ end: ret <32 x float> %phi } -define <16 x double> @bitcast_v32f32_to_v16f64(<32 x float> %a, i32 %b) { +define <16 x double> @bitcast_v32f32_to_v16f64(<32 x float> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v16f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -39314,7 +39311,7 @@ end: ret <16 x double> %phi } -define inreg <16 x double> @bitcast_v32f32_to_v16f64_scalar(<32 x float> inreg %a, i32 inreg %b) { +define inreg <16 x double> @bitcast_v32f32_to_v16f64_scalar(<32 x float> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v16f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -39618,7 +39615,7 @@ end: ret <16 x double> %phi } -define <32 x float> @bitcast_v16f64_to_v32f32(<16 x double> %a, i32 %b) { +define <32 x float> @bitcast_v16f64_to_v32f32(<16 x double> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v32f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -39773,7 +39770,7 @@ end: ret <32 x float> %phi } -define inreg <32 x float> @bitcast_v16f64_to_v32f32_scalar(<16 x double> inreg %a, i32 inreg %b) { +define inreg <32 x float> @bitcast_v16f64_to_v32f32_scalar(<16 x double> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v32f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -40032,7 +40029,7 @@ end: ret <32 x float> %phi } -define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) { +define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -44353,7 +44350,7 @@ end: ret <128 x i8> %phi } -define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, i32 inreg %b) { +define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v128i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -48651,11 +48648,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:76 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v75, s30, 0 @@ -49694,7 +49688,7 @@ end: ret <128 x i8> %phi } -define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) { +define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v32f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -55478,7 +55472,7 @@ end: ret <32 x float> %phi } -define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a, i32 inreg %b) { +define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v32f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -60648,7 +60642,7 @@ end: ret <32 x float> %phi } -define <64 x bfloat> @bitcast_v32f32_to_v64bf16(<32 x float> %a, i32 %b) { +define <64 x bfloat> @bitcast_v32f32_to_v64bf16(<32 x float> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v64bf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -61533,7 +61527,7 @@ end: ret <64 x bfloat> %phi } -define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg %a, i32 inreg %b) { +define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v64bf16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -62444,7 +62438,7 @@ end: ret <64 x bfloat> %phi } -define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) { +define <32 x float> @bitcast_v64bf16_to_v32f32(<64 x bfloat> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v32f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -65418,7 +65412,7 @@ end: ret <32 x float> %phi } -define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg %a, i32 inreg %b) { +define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v32f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -69148,7 +69142,7 @@ end: ret <32 x float> %phi } -define <64 x half> @bitcast_v32f32_to_v64f16(<32 x float> %a, i32 %b) { +define <64 x half> @bitcast_v32f32_to_v64f16(<32 x float> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v64f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -70094,7 +70088,7 @@ end: ret <64 x half> %phi } -define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a, i32 inreg %b) { +define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -70925,7 +70919,7 @@ end: ret <64 x half> %phi } -define <32 x float> @bitcast_v64f16_to_v32f32(<64 x half> %a, i32 %b) { +define <32 x float> @bitcast_v64f16_to_v32f32(<64 x half> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v32f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -71939,7 +71933,7 @@ end: ret <32 x float> %phi } -define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a, i32 inreg %b) { +define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v32f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -73083,7 +73077,7 @@ end: ret <32 x float> %phi } -define <64 x i16> @bitcast_v32f32_to_v64i16(<32 x float> %a, i32 %b) { +define <64 x i16> @bitcast_v32f32_to_v64i16(<32 x float> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v64i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -73627,7 +73621,7 @@ end: ret <64 x i16> %phi } -define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a, i32 inreg %b) { +define inreg <64 x i16> @bitcast_v32f32_to_v64i16_scalar(<32 x float> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v32f32_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -74268,7 +74262,7 @@ end: ret <64 x i16> %phi } -define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) { +define <32 x float> @bitcast_v64i16_to_v32f32(<64 x i16> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v32f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -75075,7 +75069,7 @@ end: ret <32 x float> %phi } -define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, i32 inreg %b) { +define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v32f32_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -76087,7 +76081,7 @@ end: ret <32 x float> %phi } -define <16 x double> @bitcast_v16i64_to_v16f64(<16 x i64> %a, i32 %b) { +define <16 x double> @bitcast_v16i64_to_v16f64(<16 x i64> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v16f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -76314,7 +76308,7 @@ end: ret <16 x double> %phi } -define inreg <16 x double> @bitcast_v16i64_to_v16f64_scalar(<16 x i64> inreg %a, i32 inreg %b) { +define inreg <16 x double> @bitcast_v16i64_to_v16f64_scalar(<16 x i64> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v16f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -76642,7 +76636,7 @@ end: ret <16 x double> %phi } -define <16 x i64> @bitcast_v16f64_to_v16i64(<16 x double> %a, i32 %b) { +define <16 x i64> @bitcast_v16f64_to_v16i64(<16 x double> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v16i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -76797,7 +76791,7 @@ end: ret <16 x i64> %phi } -define inreg <16 x i64> @bitcast_v16f64_to_v16i64_scalar(<16 x double> inreg %a, i32 inreg %b) { +define inreg <16 x i64> @bitcast_v16f64_to_v16i64_scalar(<16 x double> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v16i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -77056,7 +77050,7 @@ end: ret <16 x i64> %phi } -define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) { +define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -81427,7 +81421,7 @@ end: ret <128 x i8> %phi } -define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i32 inreg %b) { +define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v128i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -84639,11 +84633,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v16, s32 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v17, s32 offset:4 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v16, s30, 0 @@ -85600,7 +85591,7 @@ end: ret <128 x i8> %phi } -define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) { +define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v16i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -91384,7 +91375,7 @@ end: ret <16 x i64> %phi } -define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i32 inreg %b) { +define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v16i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -96554,7 +96545,7 @@ end: ret <16 x i64> %phi } -define <64 x bfloat> @bitcast_v16i64_to_v64bf16(<16 x i64> %a, i32 %b) { +define <64 x bfloat> @bitcast_v16i64_to_v64bf16(<16 x i64> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v64bf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -97464,7 +97455,7 @@ end: ret <64 x bfloat> %phi } -define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a, i32 inreg %b) { +define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v64bf16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -98292,7 +98283,7 @@ end: ret <64 x bfloat> %phi } -define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) { +define <16 x i64> @bitcast_v64bf16_to_v16i64(<64 x bfloat> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v16i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -101266,7 +101257,7 @@ end: ret <16 x i64> %phi } -define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a, i32 inreg %b) { +define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v16i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -104996,7 +104987,7 @@ end: ret <16 x i64> %phi } -define <64 x half> @bitcast_v16i64_to_v64f16(<16 x i64> %a, i32 %b) { +define <64 x half> @bitcast_v16i64_to_v64f16(<16 x i64> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v64f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -105963,7 +105954,7 @@ end: ret <64 x half> %phi } -define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i32 inreg %b) { +define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -106815,7 +106806,7 @@ end: ret <64 x half> %phi } -define <16 x i64> @bitcast_v64f16_to_v16i64(<64 x half> %a, i32 %b) { +define <16 x i64> @bitcast_v64f16_to_v16i64(<64 x half> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v16i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -107829,7 +107820,7 @@ end: ret <16 x i64> %phi } -define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i32 inreg %b) { +define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v16i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -108973,7 +108964,7 @@ end: ret <16 x i64> %phi } -define <64 x i16> @bitcast_v16i64_to_v64i16(<16 x i64> %a, i32 %b) { +define <64 x i16> @bitcast_v16i64_to_v64i16(<16 x i64> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v64i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -109539,7 +109530,7 @@ end: ret <64 x i16> %phi } -define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i32 inreg %b) { +define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16i64_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -110218,7 +110209,7 @@ end: ret <64 x i16> %phi } -define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) { +define <16 x i64> @bitcast_v64i16_to_v16i64(<64 x i16> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v16i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -111025,7 +111016,7 @@ end: ret <16 x i64> %phi } -define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i32 inreg %b) { +define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v16i64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -112037,7 +112028,7 @@ end: ret <16 x i64> %phi } -define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) { +define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -116321,7 +116312,7 @@ end: ret <128 x i8> %phi } -define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, i32 inreg %b) { +define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v128i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -120610,11 +120601,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:92 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v76, s30, 0 @@ -121642,7 +121630,7 @@ end: ret <128 x i8> %phi } -define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) { +define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v16f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -127426,7 +127414,7 @@ end: ret <16 x double> %phi } -define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a, i32 inreg %b) { +define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v16f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -132596,7 +132584,7 @@ end: ret <16 x double> %phi } -define <64 x bfloat> @bitcast_v16f64_to_v64bf16(<16 x double> %a, i32 %b) { +define <64 x bfloat> @bitcast_v16f64_to_v64bf16(<16 x double> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v64bf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -133414,7 +133402,7 @@ end: ret <64 x bfloat> %phi } -define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg %a, i32 inreg %b) { +define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v64bf16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -134282,7 +134270,7 @@ end: ret <64 x bfloat> %phi } -define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) { +define <16 x double> @bitcast_v64bf16_to_v16f64(<64 x bfloat> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v16f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -137256,7 +137244,7 @@ end: ret <16 x double> %phi } -define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg %a, i32 inreg %b) { +define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v16f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -140986,7 +140974,7 @@ end: ret <16 x double> %phi } -define <64 x half> @bitcast_v16f64_to_v64f16(<16 x double> %a, i32 %b) { +define <64 x half> @bitcast_v16f64_to_v64f16(<16 x double> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v64f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -141863,7 +141851,7 @@ end: ret <64 x half> %phi } -define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a, i32 inreg %b) { +define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -142685,7 +142673,7 @@ end: ret <64 x half> %phi } -define <16 x double> @bitcast_v64f16_to_v16f64(<64 x half> %a, i32 %b) { +define <16 x double> @bitcast_v64f16_to_v16f64(<64 x half> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v16f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -143699,7 +143687,7 @@ end: ret <16 x double> %phi } -define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a, i32 inreg %b) { +define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v16f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -144843,7 +144831,7 @@ end: ret <16 x double> %phi } -define <64 x i16> @bitcast_v16f64_to_v64i16(<16 x double> %a, i32 %b) { +define <64 x i16> @bitcast_v16f64_to_v64i16(<16 x double> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v64i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -145339,7 +145327,7 @@ end: ret <64 x i16> %phi } -define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a, i32 inreg %b) { +define inreg <64 x i16> @bitcast_v16f64_to_v64i16_scalar(<16 x double> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v16f64_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -145932,7 +145920,7 @@ end: ret <64 x i16> %phi } -define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) { +define <16 x double> @bitcast_v64i16_to_v16f64(<64 x i16> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v16f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -146739,7 +146727,7 @@ end: ret <16 x double> %phi } -define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, i32 inreg %b) { +define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v16f64_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -147751,7 +147739,7 @@ end: ret <16 x double> %phi } -define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) { +define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v64bf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -154021,7 +154009,7 @@ end: ret <64 x bfloat> %phi } -define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a, i32 inreg %b) { +define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v64bf16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -159482,7 +159470,7 @@ end: ret <64 x bfloat> %phi } -define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { +define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -167045,7 +167033,7 @@ end: ret <128 x i8> %phi } -define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a, i32 inreg %b) { +define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v128i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -172208,11 +172196,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-TRUE16-NEXT: s_clause 0x3 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 -; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:4 -; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:8 -; GFX11-TRUE16-NEXT: ; meta instruction ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:12 ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 @@ -173774,11 +173759,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-FAKE16-NEXT: s_clause 0x3 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 -; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:4 -; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:8 -; GFX11-FAKE16-NEXT: ; meta instruction ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:12 ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 @@ -175357,7 +175339,7 @@ end: ret <128 x i8> %phi } -define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) { +define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v64f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -181744,7 +181726,7 @@ end: ret <64 x half> %phi } -define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i32 inreg %b) { +define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -187109,7 +187091,7 @@ end: ret <64 x half> %phi } -define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) { +define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -192351,7 +192333,7 @@ end: ret <128 x i8> %phi } -define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i32 inreg %b) { +define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v128i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -196735,11 +196717,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:76 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v75, s30, 0 @@ -197777,7 +197756,7 @@ end: ret <128 x i8> %phi } -define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) { +define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v64i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -204099,7 +204078,7 @@ end: ret <64 x i16> %phi } -define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i32 inreg %b) { +define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v128i8_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -209535,7 +209514,7 @@ end: ret <64 x i16> %phi } -define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) { +define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v128i8: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -214936,7 +214915,7 @@ end: ret <128 x i8> %phi } -define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i32 inreg %b) { +define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v128i8_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -219091,11 +219070,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:76 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 -; GFX11-NEXT: ; meta instruction ; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v75, s30, 0 @@ -220133,7 +220109,7 @@ end: ret <128 x i8> %phi } -define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) { +define <64 x half> @bitcast_v64bf16_to_v64f16(<64 x bfloat> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v64f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -223790,7 +223766,7 @@ end: ret <64 x half> %phi } -define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %a, i32 inreg %b) { +define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -227703,7 +227679,7 @@ end: ret <64 x half> %phi } -define <64 x bfloat> @bitcast_v64f16_to_v64bf16(<64 x half> %a, i32 %b) { +define <64 x bfloat> @bitcast_v64f16_to_v64bf16(<64 x half> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v64bf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -229240,7 +229216,7 @@ end: ret <64 x bfloat> %phi } -define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %a, i32 inreg %b) { +define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v64bf16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -230687,7 +230663,7 @@ end: ret <64 x bfloat> %phi } -define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) { +define <64 x i16> @bitcast_v64bf16_to_v64i16(<64 x bfloat> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v64i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -234098,7 +234074,7 @@ end: ret <64 x i16> %phi } -define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a, i32 inreg %b) { +define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64bf16_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -237770,7 +237746,7 @@ end: ret <64 x i16> %phi } -define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) { +define <64 x bfloat> @bitcast_v64i16_to_v64bf16(<64 x i16> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v64bf16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -238856,7 +238832,7 @@ end: ret <64 x bfloat> %phi } -define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a, i32 inreg %b) { +define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v64bf16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -240151,7 +240127,7 @@ end: ret <64 x bfloat> %phi } -define <64 x i16> @bitcast_v64f16_to_v64i16(<64 x half> %a, i32 %b) { +define <64 x i16> @bitcast_v64f16_to_v64i16(<64 x half> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v64i16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -241091,7 +241067,7 @@ end: ret <64 x i16> %phi } -define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i32 inreg %b) { +define inreg <64 x i16> @bitcast_v64f16_to_v64i16_scalar(<64 x half> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64f16_to_v64i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -242177,7 +242153,7 @@ end: ret <64 x i16> %phi } -define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) { +define <64 x half> @bitcast_v64i16_to_v64f16(<64 x i16> %a, i32 %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v64f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -243501,7 +243477,7 @@ end: ret <64 x half> %phi } -define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i32 inreg %b) { +define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i32 inreg %b) #0 { ; SI-LABEL: bitcast_v64i16_to_v64f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -244785,3 +244761,5 @@ end: %phi = phi <64 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ] ret <64 x half> %phi } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll index 7f6bb85827d3..49231b83a3bb 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll @@ -6,7 +6,7 @@ declare amdgpu_gfx void @use(...) -define amdgpu_cs_chain void @amdgpu_cs_chain_no_stack({ptr, i32, <4 x i32>} inreg %a, {ptr, i32, <4 x i32>} %b) { +define amdgpu_cs_chain void @amdgpu_cs_chain_no_stack({ptr, i32, <4 x i32>} inreg %a, {ptr, i32, <4 x i32>} %b) #0 { ; GISEL-GFX11-LABEL: amdgpu_cs_chain_no_stack: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -29,25 +29,23 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_no_stack({ptr, i32, <4 x i32>} inre ret void } -define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr, <4 x i32> %vgpr) { +define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr, <4 x i32> %vgpr) #0 { ; GISEL-GFX11-LABEL: amdgpu_cs_chain_simple_call: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-GFX11-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v6, v10 :: v_dual_mov_b32 v7, v11 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GISEL-GFX11-NEXT: s_mov_b32 s4, use@abs32@lo ; GISEL-GFX11-NEXT: s_mov_b32 s5, use@abs32@hi -; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-GFX11-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GISEL-GFX11-NEXT: s_endpgm ; ; GISEL-GFX10-LABEL: amdgpu_cs_chain_simple_call: ; GISEL-GFX10: ; %bb.0: ; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v4, v8 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v5, v9 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v6, v10 @@ -60,27 +58,26 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr, ; GISEL-GFX10-NEXT: s_mov_b32 s4, use@abs32@lo ; GISEL-GFX10-NEXT: s_mov_b32 s5, use@abs32@hi ; GISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] +; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GISEL-GFX10-NEXT: s_endpgm ; ; DAGISEL-GFX11-LABEL: amdgpu_cs_chain_simple_call: ; DAGISEL-GFX11: ; %bb.0: ; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v7, v11 :: v_dual_mov_b32 v6, v10 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v5, v9 :: v_dual_mov_b32 v4, v8 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; DAGISEL-GFX11-NEXT: s_mov_b32 s5, use@abs32@hi ; DAGISEL-GFX11-NEXT: s_mov_b32 s4, use@abs32@lo -; DAGISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[4:5] ; DAGISEL-GFX11-NEXT: s_endpgm ; ; DAGISEL-GFX10-LABEL: amdgpu_cs_chain_simple_call: ; DAGISEL-GFX10: ; %bb.0: ; DAGISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v7, v11 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v6, v10 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v5, v9 @@ -93,18 +90,19 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_simple_call(<4 x i32> inreg %sgpr, ; DAGISEL-GFX10-NEXT: s_mov_b32 s5, use@abs32@hi ; DAGISEL-GFX10-NEXT: s_mov_b32 s4, use@abs32@lo ; DAGISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] +; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; DAGISEL-GFX10-NEXT: s_endpgm call amdgpu_gfx void @use(<4 x i32> %sgpr, <4 x i32> %vgpr) ret void } -define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 x i32> %vgprs) { +define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 x i32> %vgprs) #0 { ; GISEL-GFX11-LABEL: amdgpu_cs_chain_spill: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-GFX11-NEXT: s_mov_b32 s32, 0 -; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GISEL-GFX11-NEXT: v_dual_mov_b32 v32, v8 :: v_dual_mov_b32 v33, v9 ; GISEL-GFX11-NEXT: s_add_u32 s24, s32, 4 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v16, s32 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v17, s24 @@ -125,7 +123,6 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v24, s24 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v25, s25 ; GISEL-GFX11-NEXT: s_add_u32 s24, s32, 40 -; GISEL-GFX11-NEXT: v_dual_mov_b32 v32, v8 :: v_dual_mov_b32 v33, v9 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v34, v10 :: v_dual_mov_b32 v35, v11 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v36, v12 :: v_dual_mov_b32 v37, v13 ; GISEL-GFX11-NEXT: v_dual_mov_b32 v38, v14 :: v_dual_mov_b32 v39, v15 @@ -165,7 +162,6 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; GISEL-GFX10-LABEL: amdgpu_cs_chain_spill: ; GISEL-GFX10: ; %bb.0: ; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v32, v8 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v33, v9 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v34, v10 @@ -174,6 +170,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v37, v13 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v38, v14 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v39, v15 +; GISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; GISEL-GFX10-NEXT: buffer_store_dword v16, off, s[48:51], s32 ; GISEL-GFX10-NEXT: buffer_store_dword v17, off, s[48:51], s32 offset:4 ; GISEL-GFX10-NEXT: buffer_store_dword v18, off, s[48:51], s32 offset:8 @@ -233,7 +230,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX11: ; %bb.0: ; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 0 -; DAGISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v32, v15 :: v_dual_mov_b32 v33, v14 ; DAGISEL-GFX11-NEXT: s_add_i32 s24, s32, 60 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v16, s32 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v31, s24 @@ -254,7 +251,6 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v24, s24 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v23, s25 ; DAGISEL-GFX11-NEXT: s_add_i32 s24, s32, 24 -; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v32, v15 :: v_dual_mov_b32 v33, v14 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v34, v13 :: v_dual_mov_b32 v35, v12 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v36, v11 :: v_dual_mov_b32 v37, v10 ; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v38, v9 :: v_dual_mov_b32 v39, v8 @@ -294,7 +290,6 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX10-LABEL: amdgpu_cs_chain_spill: ; DAGISEL-GFX10: ; %bb.0: ; DAGISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v32, v15 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v33, v14 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v34, v13 @@ -303,6 +298,7 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v37, v10 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v38, v9 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v39, v8 +; DAGISEL-GFX10-NEXT: s_mov_b32 s32, 0 ; DAGISEL-GFX10-NEXT: buffer_store_dword v16, off, s[48:51], s32 ; DAGISEL-GFX10-NEXT: buffer_store_dword v17, off, s[48:51], s32 offset:4 ; DAGISEL-GFX10-NEXT: buffer_store_dword v18, off, s[48:51], s32 offset:8 @@ -361,14 +357,14 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_spill(<24 x i32> inreg %sgprs, <24 ret void } -define amdgpu_cs_chain void @alloca_and_call() { +define amdgpu_cs_chain void @alloca_and_call() #0 { ; GISEL-GFX11-LABEL: alloca_and_call: ; GISEL-GFX11: ; %bb.0: ; %.entry ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 42 ; GISEL-GFX11-NEXT: s_mov_b32 s0, use@abs32@lo ; GISEL-GFX11-NEXT: s_mov_b32 s1, use@abs32@hi +; GISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; GISEL-GFX11-NEXT: scratch_store_b32 off, v0, off ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -377,7 +373,6 @@ define amdgpu_cs_chain void @alloca_and_call() { ; GISEL-GFX10-LABEL: alloca_and_call: ; GISEL-GFX10: ; %bb.0: ; %.entry ; GISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49] ; GISEL-GFX10-NEXT: s_mov_b32 s4, use@abs32@lo @@ -385,16 +380,17 @@ define amdgpu_cs_chain void @alloca_and_call() { ; GISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] ; GISEL-GFX10-NEXT: buffer_store_dword v0, off, s[48:51], 0 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; GISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GISEL-GFX10-NEXT: s_endpgm ; ; DAGISEL-GFX11-LABEL: alloca_and_call: ; DAGISEL-GFX11: ; %bb.0: ; %.entry ; DAGISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v0, 42 ; DAGISEL-GFX11-NEXT: s_mov_b32 s1, use@abs32@hi ; DAGISEL-GFX11-NEXT: s_mov_b32 s0, use@abs32@lo +; DAGISEL-GFX11-NEXT: s_mov_b32 s32, 16 ; DAGISEL-GFX11-NEXT: scratch_store_b32 off, v0, off ; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 ; DAGISEL-GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -403,7 +399,6 @@ define amdgpu_cs_chain void @alloca_and_call() { ; DAGISEL-GFX10-LABEL: alloca_and_call: ; DAGISEL-GFX10: ; %bb.0: ; %.entry ; DAGISEL-GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; DAGISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v0, 42 ; DAGISEL-GFX10-NEXT: s_mov_b64 s[0:1], s[48:49] ; DAGISEL-GFX10-NEXT: s_mov_b32 s5, use@abs32@hi @@ -411,6 +406,7 @@ define amdgpu_cs_chain void @alloca_and_call() { ; DAGISEL-GFX10-NEXT: s_mov_b64 s[2:3], s[50:51] ; DAGISEL-GFX10-NEXT: buffer_store_dword v0, off, s[48:51], 0 ; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; DAGISEL-GFX10-NEXT: s_movk_i32 s32, 0x200 ; DAGISEL-GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; DAGISEL-GFX10-NEXT: s_endpgm .entry: @@ -420,7 +416,7 @@ define amdgpu_cs_chain void @alloca_and_call() { ret void } -define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) { +define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) #0 { ; GISEL-GFX11-LABEL: cs_to_chain: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v10, v2 @@ -506,7 +502,7 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) { } ; Chain call with SGPR arguments that we cannot prove are uniform. -define amdgpu_cs void @cs_to_chain_nonuniform(<3 x i32> %a, <3 x i32> %b) { +define amdgpu_cs void @cs_to_chain_nonuniform(<3 x i32> %a, <3 x i32> %b) #0 { ; GISEL-GFX11-LABEL: cs_to_chain_nonuniform: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: v_readfirstlane_b32 s0, v0 @@ -578,7 +574,7 @@ define amdgpu_cs void @cs_to_chain_nonuniform(<3 x i32> %a, <3 x i32> %b) { unreachable } -define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %a, <3 x i32> %b) { +define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %a, <3 x i32> %b) #0 { ; GISEL-GFX11-LABEL: chain_to_chain: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -643,7 +639,7 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %a, <3 x i32> %b) { unreachable } -define amdgpu_cs_chain void @chain_to_chain_wwm(<3 x i32> inreg %a, <3 x i32> %b) { +define amdgpu_cs_chain void @chain_to_chain_wwm(<3 x i32> inreg %a, <3 x i32> %b) #0 { ; GISEL-GFX11-LABEL: chain_to_chain_wwm: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -725,7 +721,7 @@ define amdgpu_cs_chain void @chain_to_chain_wwm(<3 x i32> inreg %a, <3 x i32> %b unreachable } -define amdgpu_cs_chain void @chain_to_chain_use_all_v0_v7(<3 x i32> inreg %a, <3 x i32> %b) { +define amdgpu_cs_chain void @chain_to_chain_use_all_v0_v7(<3 x i32> inreg %a, <3 x i32> %b) #0 { ; GISEL-GFX11-LABEL: chain_to_chain_use_all_v0_v7: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -790,7 +786,7 @@ define amdgpu_cs_chain void @chain_to_chain_use_all_v0_v7(<3 x i32> inreg %a, <3 unreachable } -define amdgpu_cs_chain void @chain_to_chain_fewer_args(<3 x i32> inreg %a, <3 x i32> %b) { +define amdgpu_cs_chain void @chain_to_chain_fewer_args(<3 x i32> inreg %a, <3 x i32> %b) #0 { ; GISEL-GFX11-LABEL: chain_to_chain_fewer_args: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -857,7 +853,7 @@ define amdgpu_cs_chain void @chain_to_chain_fewer_args(<3 x i32> inreg %a, <3 x unreachable } -define amdgpu_cs_chain void @chain_to_chain_more_args(<3 x i32> inreg %a, <3 x i32> %b) { +define amdgpu_cs_chain void @chain_to_chain_more_args(<3 x i32> inreg %a, <3 x i32> %b) #0 { ; GISEL-GFX11-LABEL: chain_to_chain_more_args: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -930,7 +926,7 @@ define amdgpu_cs_chain void @chain_to_chain_more_args(<3 x i32> inreg %a, <3 x i unreachable } -define amdgpu_cs_chain void @amdgpu_cs_chain_dont_realign_stack(i32 %idx) { +define amdgpu_cs_chain void @amdgpu_cs_chain_dont_realign_stack(i32 %idx) #0 { ; GISEL-GFX11-LABEL: amdgpu_cs_chain_dont_realign_stack: ; GISEL-GFX11: ; %bb.0: ; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1006,3 +1002,5 @@ declare amdgpu_cs_chain void @chain_callee(<3 x i32> inreg, <3 x i32>) declare amdgpu_cs_chain void @chain_callee_4(<4 x i32> inreg, <4 x i32>) declare i32 @llvm.amdgcn.set.inactive(i32, i32) declare i32 @llvm.amdgcn.wwm(i32) + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll index 06150e4277e9..e552ef48a855 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll @@ -8,7 +8,7 @@ declare amdgpu_gfx void @foo() -define amdgpu_cs_chain void @test_alloca() { +define amdgpu_cs_chain void @test_alloca() #0 { ; GFX12-LABEL: test_alloca: ; GFX12: ; %bb.0: ; %.entry ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -43,7 +43,7 @@ SW_C: ; preds = %.entry ret void } -define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) { +define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) #0 { ; GFX12-LABEL: test_alloca_var_uniform: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -84,7 +84,7 @@ define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) { ret void } -define amdgpu_cs_chain void @test_alloca_var(i32 %count) { +define amdgpu_cs_chain void @test_alloca_var(i32 %count) #0 { ; GFX12-LABEL: test_alloca_var: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -145,7 +145,7 @@ define amdgpu_cs_chain void @test_alloca_var(i32 %count) { ret void } -define amdgpu_cs_chain void @test_alloca_and_call() { +define amdgpu_cs_chain void @test_alloca_and_call() #0 { ; GFX12-LABEL: test_alloca_and_call: ; GFX12: ; %bb.0: ; %.entry ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -197,7 +197,7 @@ SW_C: ; preds = %.entry ret void } -define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count) { +define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count) #0 { ; GFX12-LABEL: test_alloca_and_call_var_uniform: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -254,7 +254,7 @@ define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count) ret void } -define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) { +define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) #0 { ; GFX12-LABEL: test_alloca_and_call_var: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -331,7 +331,7 @@ define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) { ret void } -define amdgpu_cs_chain void @test_call_and_alloca() { +define amdgpu_cs_chain void @test_call_and_alloca() #0 { ; GFX12-LABEL: test_call_and_alloca: ; GFX12: ; %bb.0: ; %.entry ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -382,7 +382,7 @@ SW_C: ; preds = %.entry ret void } -define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count) { +define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count) #0 { ; GFX12-LABEL: test_call_and_alloca_var_uniform: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -439,7 +439,7 @@ define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count) ret void } -define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) { +define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) #0 { ; GFX12-LABEL: test_call_and_alloca_var: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -517,3 +517,5 @@ define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) { store i32 0, ptr addrspace(5) %v, align 4 ret void } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll index 1e04fc1da938..d1cede64ce71 100644 --- a/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/call-args-inreg.ll @@ -69,11 +69,11 @@ define void @test_call_external_void_func_i8_inreg(i8 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i8_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i8_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -129,11 +129,11 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i16_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -189,11 +189,11 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i32_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -250,11 +250,11 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_i64_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_i64_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -311,11 +311,11 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2i32_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -373,11 +373,11 @@ define void @test_call_external_void_func_v3i32_inreg(<3 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s16 ; GFX11-NEXT: v_writelane_b32 v40, s3, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v3i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v3i32_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -436,11 +436,11 @@ define void @test_call_external_void_func_v4i32_inreg(<4 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s17 ; GFX11-NEXT: v_writelane_b32 v40, s16, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v4i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v4i32_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -503,11 +503,11 @@ define void @test_call_external_void_func_v8i32_inreg(<8 x i32> inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s21 ; GFX11-NEXT: v_writelane_b32 v40, s20, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[20:21] ; GFX11-NEXT: s_add_u32 s20, s20, external_void_func_v8i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s21, s21, external_void_func_v8i32_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[20:21] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -563,11 +563,11 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f16_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -623,11 +623,11 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_bf16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_bf16_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -683,11 +683,11 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f32_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -744,11 +744,11 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_f64_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_f64_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -804,11 +804,11 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2f16_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -865,11 +865,11 @@ define void @test_call_external_void_func_v2bf16_inreg(<2 x bfloat> inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2bf16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2bf16_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -926,11 +926,11 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v3f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v3f16_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -987,11 +987,11 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v4f16_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v4f16_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1048,11 +1048,11 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p0_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p0_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1109,11 +1109,11 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p1_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p1_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1169,11 +1169,11 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s2 ; GFX11-NEXT: v_writelane_b32 v40, s1, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_p3_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_p3_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1232,11 +1232,11 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s17 ; GFX11-NEXT: v_writelane_b32 v40, s16, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, external_void_func_v2p1_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, external_void_func_v2p1_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1293,11 +1293,11 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s3 ; GFX11-NEXT: v_writelane_b32 v40, s2, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_v2p5_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_v2p5_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1357,11 +1357,11 @@ define void @test_call_external_void_func_i64_inreg_i32_inreg_i64_inreg(i64 inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s18 ; GFX11-NEXT: v_writelane_b32 v40, s17, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[18:19] ; GFX11-NEXT: s_add_u32 s18, s18, external_void_func_i64_inreg_i32_inreg_i64_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s19, s19, external_void_func_i64_inreg_i32_inreg_i64_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1429,11 +1429,11 @@ define void @test_call_external_void_func_a15i32_inreg([13 x i32] inreg %arg0) # ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s26 ; GFX11-NEXT: v_writelane_b32 v40, s25, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[26:27] ; GFX11-NEXT: s_add_u32 s26, s26, external_void_func_a15i32_inreg@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s27, s27, external_void_func_a15i32_inreg@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[26:27] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1504,11 +1504,11 @@ define void @test_call_external_void_func_a15i32_inreg_i32_inreg([13 x i32] inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s18 ; GFX11-NEXT: v_writelane_b32 v40, s17, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[18:19] ; GFX11-NEXT: s_add_u32 s18, s18, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@lo+4 ; GFX11-NEXT: s_addc_u32 s19, s19, external_void_func_a15i32_inreg_i32_inreg__noimplicit@rel32@hi+12 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[18:19] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll index 2f2d2005ea2a..8e12e7e03947 100644 --- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll @@ -5852,7 +5852,6 @@ define void @stack_12xv3i32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: s_addk_i32 s32, 0x400 ; VI-NEXT: v_mov_b32_e32 v0, 11 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -5861,6 +5860,7 @@ define void @stack_12xv3i32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 13 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; VI-NEXT: v_mov_b32_e32 v0, 14 +; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; VI-NEXT: v_mov_b32_e32 v0, 15 ; VI-NEXT: v_writelane_b32 v40, s30, 0 @@ -5920,7 +5920,6 @@ define void @stack_12xv3i32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: s_addk_i32 s32, 0x400 ; CI-NEXT: v_mov_b32_e32 v0, 11 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -5929,6 +5928,7 @@ define void @stack_12xv3i32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 13 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; CI-NEXT: v_mov_b32_e32 v0, 14 +; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; CI-NEXT: v_mov_b32_e32 v0, 15 ; CI-NEXT: v_writelane_b32 v40, s30, 0 @@ -5988,7 +5988,6 @@ define void @stack_12xv3i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_mov_b32_e32 v0, 11 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -5997,6 +5996,7 @@ define void @stack_12xv3i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -6106,7 +6106,6 @@ define void @stack_12xv3i32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: s_addk_i32 s32, 0x400 ; HSA-NEXT: v_mov_b32_e32 v0, 11 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6115,6 +6114,7 @@ define void @stack_12xv3i32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 13 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; HSA-NEXT: v_mov_b32_e32 v0, 14 +; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; HSA-NEXT: v_mov_b32_e32 v0, 15 ; HSA-NEXT: v_writelane_b32 v40, s30, 0 @@ -6191,7 +6191,6 @@ define void @stack_12xv3f32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: s_addk_i32 s32, 0x400 ; VI-NEXT: v_mov_b32_e32 v0, 0x41300000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6200,6 +6199,7 @@ define void @stack_12xv3f32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; VI-NEXT: v_mov_b32_e32 v0, 0x41600000 +; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; VI-NEXT: v_mov_b32_e32 v0, 0x41700000 ; VI-NEXT: v_writelane_b32 v40, s30, 0 @@ -6259,7 +6259,6 @@ define void @stack_12xv3f32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: s_addk_i32 s32, 0x400 ; CI-NEXT: v_mov_b32_e32 v0, 0x41300000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6268,6 +6267,7 @@ define void @stack_12xv3f32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; CI-NEXT: v_mov_b32_e32 v0, 0x41600000 +; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; CI-NEXT: v_mov_b32_e32 v0, 0x41700000 ; CI-NEXT: v_writelane_b32 v40, s30, 0 @@ -6327,7 +6327,6 @@ define void @stack_12xv3f32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41300000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6336,6 +6335,7 @@ define void @stack_12xv3f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000 +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -6449,7 +6449,6 @@ define void @stack_12xv3f32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: s_addk_i32 s32, 0x400 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41300000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6458,6 +6457,7 @@ define void @stack_12xv3f32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 0x41500000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41600000 +; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41700000 ; HSA-NEXT: v_writelane_b32 v40, s30, 0 @@ -6534,7 +6534,6 @@ define void @stack_8xv5i32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: s_addk_i32 s32, 0x400 ; VI-NEXT: v_mov_b32_e32 v0, 7 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6551,6 +6550,7 @@ define void @stack_8xv5i32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 13 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; VI-NEXT: v_mov_b32_e32 v0, 14 +; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; VI-NEXT: v_mov_b32_e32 v0, 15 ; VI-NEXT: v_writelane_b32 v40, s30, 0 @@ -6610,7 +6610,6 @@ define void @stack_8xv5i32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: s_addk_i32 s32, 0x400 ; CI-NEXT: v_mov_b32_e32 v0, 7 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6627,6 +6626,7 @@ define void @stack_8xv5i32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 13 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; CI-NEXT: v_mov_b32_e32 v0, 14 +; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; CI-NEXT: v_mov_b32_e32 v0, 15 ; CI-NEXT: v_writelane_b32 v40, s30, 0 @@ -6686,7 +6686,6 @@ define void @stack_8xv5i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_mov_b32_e32 v0, 7 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6703,6 +6702,7 @@ define void @stack_8xv5i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -6817,7 +6817,6 @@ define void @stack_8xv5i32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: s_addk_i32 s32, 0x400 ; HSA-NEXT: v_mov_b32_e32 v0, 7 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6834,6 +6833,7 @@ define void @stack_8xv5i32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 13 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; HSA-NEXT: v_mov_b32_e32 v0, 14 +; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; HSA-NEXT: v_mov_b32_e32 v0, 15 ; HSA-NEXT: v_writelane_b32 v40, s30, 0 @@ -6906,7 +6906,6 @@ define void @stack_8xv5f32() #0 { ; VI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[8:9] -; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: s_addk_i32 s32, 0x400 ; VI-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6923,6 +6922,7 @@ define void @stack_8xv5f32() #0 { ; VI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; VI-NEXT: v_mov_b32_e32 v0, 0x41600000 +; VI-NEXT: v_writelane_b32 v40, s4, 2 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; VI-NEXT: v_mov_b32_e32 v0, 0x41700000 ; VI-NEXT: v_writelane_b32 v40, s30, 0 @@ -6982,7 +6982,6 @@ define void @stack_8xv5f32() #0 { ; CI-NEXT: s_or_saveexec_b64 s[8:9], -1 ; CI-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CI-NEXT: s_mov_b64 exec, s[8:9] -; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: s_addk_i32 s32, 0x400 ; CI-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -6999,6 +6998,7 @@ define void @stack_8xv5f32() #0 { ; CI-NEXT: v_mov_b32_e32 v0, 0x41500000 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; CI-NEXT: v_mov_b32_e32 v0, 0x41600000 +; CI-NEXT: v_writelane_b32 v40, s4, 2 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; CI-NEXT: v_mov_b32_e32 v0, 0x41700000 ; CI-NEXT: v_writelane_b32 v40, s30, 0 @@ -7058,7 +7058,6 @@ define void @stack_8xv5f32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[8:9], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[8:9] -; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -7075,6 +7074,7 @@ define void @stack_8xv5f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000 +; GFX9-NEXT: v_writelane_b32 v40, s4, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -7192,7 +7192,6 @@ define void @stack_8xv5f32() #0 { ; HSA-NEXT: s_or_saveexec_b64 s[8:9], -1 ; HSA-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; HSA-NEXT: s_mov_b64 exec, s[8:9] -; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: s_addk_i32 s32, 0x400 ; HSA-NEXT: v_mov_b32_e32 v0, 0x40e00000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -7209,6 +7208,7 @@ define void @stack_8xv5f32() #0 { ; HSA-NEXT: v_mov_b32_e32 v0, 0x41500000 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41600000 +; HSA-NEXT: v_writelane_b32 v40, s4, 2 ; HSA-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; HSA-NEXT: v_mov_b32_e32 v0, 0x41700000 ; HSA-NEXT: v_writelane_b32 v40, s30, 0 diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll index fcc032b51fe5..fccee3da6d77 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll @@ -420,8 +420,8 @@ define void @func_indirect_use_workitem_id_x() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x@gotpcrel32@hi+12 @@ -453,8 +453,8 @@ define void @func_indirect_use_workitem_id_y() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_y@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_y@gotpcrel32@hi+12 @@ -486,8 +486,8 @@ define void @func_indirect_use_workitem_id_z() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_z@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_z@gotpcrel32@hi+12 @@ -939,8 +939,8 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 { ; GFX7-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[6:7] -; GFX7-NEXT: v_writelane_b32 v40, s4, 2 ; GFX7-NEXT: s_addk_i32 s32, 0x400 +; GFX7-NEXT: v_writelane_b32 v40, s4, 2 ; GFX7-NEXT: s_getpc_b64 s[4:5] ; GFX7-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 ; GFX7-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 @@ -1003,8 +1003,8 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 { ; GFX90A-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX90A-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[6:7] -; GFX90A-NEXT: v_writelane_b32 v40, s4, 2 ; GFX90A-NEXT: s_addk_i32 s32, 0x400 +; GFX90A-NEXT: v_writelane_b32 v40, s4, 2 ; GFX90A-NEXT: s_getpc_b64 s[4:5] ; GFX90A-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 ; GFX90A-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 @@ -1081,9 +1081,9 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x( ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 @@ -1396,7 +1396,6 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7 ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 @@ -1404,6 +1403,7 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { ; GCN-NEXT: v_mov_b32_e32 v0, 0x140 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval@gotpcrel32@hi+12 diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll index 2854bdca76d0..bb2f06bfe83f 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll @@ -265,8 +265,8 @@ define void @func_indirect_use_workitem_id_x() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_x@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_x@gotpcrel32@hi+12 @@ -298,8 +298,8 @@ define void @func_indirect_use_workitem_id_y() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_y@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_y@gotpcrel32@hi+12 @@ -331,8 +331,8 @@ define void @func_indirect_use_workitem_id_z() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, use_workitem_id_z@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, use_workitem_id_z@gotpcrel32@hi+12 @@ -651,8 +651,8 @@ define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 @@ -729,9 +729,9 @@ define void @too_many_args_call_too_many_args_use_workitem_id_x( ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s33 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x@gotpcrel32@hi+12 @@ -970,7 +970,6 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: v_mov_b32_e32 v0, 0x3e7 ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s33 @@ -978,6 +977,7 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { ; GCN-NEXT: v_mov_b32_e32 v0, 0x140 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s33 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, too_many_args_use_workitem_id_x_byval@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, too_many_args_use_workitem_id_x_byval@gotpcrel32@hi+12 diff --git a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll index c05eef51c276..bcccf50e3805 100644 --- a/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll +++ b/llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll @@ -287,10 +287,10 @@ define amdgpu_gfx void @amdgpu_gfx() #0 { ; CHECK-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15 -; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi ; CHECK-TRUE16-NEXT: s_mov_b32 s0, callee@abs32@lo ; CHECK-TRUE16-NEXT: s_add_co_i32 s32, s32, 16 +; CHECK-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0 ; CHECK-TRUE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS ; CHECK-TRUE16-NEXT: s_wait_storecnt 0x0 @@ -327,10 +327,10 @@ define amdgpu_gfx void @amdgpu_gfx() #0 { ; CHECK-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15 -; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi ; CHECK-FAKE16-NEXT: s_mov_b32 s0, callee@abs32@lo ; CHECK-FAKE16-NEXT: s_add_co_i32 s32, s32, 16 +; CHECK-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0 ; CHECK-FAKE16-NEXT: scratch_store_b8 off, v0, s33 scope:SCOPE_SYS ; CHECK-FAKE16-NEXT: s_wait_storecnt 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll index ed767aeaf112..b89b57a3ae29 100644 --- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll @@ -4,7 +4,7 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s ; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-GISEL %s -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_load_dword s4, s[8:9], 0x0 @@ -84,7 +84,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) { ret void } -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_over_aligned(i32 %n) { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_over_aligned(i32 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform_over_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_load_dword s4, s[8:9], 0x0 @@ -169,7 +169,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_over_aligned(i ret void } -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_under_aligned(i32 %n) { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_under_aligned(i32 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform_under_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_load_dword s4, s[8:9], 0x0 @@ -249,7 +249,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_under_aligned( ret void } -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent() { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent() #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 @@ -364,7 +364,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent() { ret void } -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_over_aligned() { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_over_aligned() #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent_over_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 @@ -484,7 +484,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_over_aligned ret void } -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_under_aligned() { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_under_aligned() #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent_under_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 @@ -596,7 +596,7 @@ define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_under_aligne ret void } -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %n, i32 %m) { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %n, i32 %m) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_multiple_allocas: ; GFX9-SDAG: ; %bb.0: ; %entry ; GFX9-SDAG-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 @@ -833,7 +833,7 @@ bb.1: ret void } -define amdgpu_kernel void @test_dynamic_stackalloc_kernel_control_flow(i32 %n, i32 %m) { +define amdgpu_kernel void @test_dynamic_stackalloc_kernel_control_flow(i32 %n, i32 %m) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_control_flow: ; GFX9-SDAG: ; %bb.0: ; %entry ; GFX9-SDAG-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 @@ -1045,16 +1045,16 @@ bb.2: ret void } -define void @test_dynamic_stackalloc_device_uniform(i32 %n) { +define void @test_dynamic_stackalloc_device_uniform(i32 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1078,12 +1078,12 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1107,14 +1107,13 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 ; GFX11-SDAG-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1137,14 +1136,13 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 ; GFX11-GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1169,19 +1167,19 @@ define void @test_dynamic_stackalloc_device_uniform(i32 %n) { ret void } -define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { +define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-SDAG-NEXT: s_mov_b32 s10, s34 -; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 -; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 -; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-SDAG-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1207,15 +1205,15 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-GISEL-NEXT: s_mov_b32 s10, s34 -; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 -; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 -; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1241,20 +1239,19 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-SDAG-NEXT: s_mov_b32 s5, s34 -; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 -; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x100 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-SDAG-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 ; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 ; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 @@ -1264,33 +1261,31 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0xfff ; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 10 ; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xfffff000 -; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 ; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc ; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 ; GFX11-SDAG-NEXT: s_mov_b32 s32, s34 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s5 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-GISEL-NEXT: s_mov_b32 s5, s34 -; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 -; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x100 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 ; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 ; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 @@ -1301,29 +1296,28 @@ define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { ; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 10 ; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 ; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 ; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 ; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc ; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-GISEL-NEXT: s_mov_b32 s32, s34 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s5 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, i32 %n, align 128, addrspace(5) store volatile i32 10, ptr addrspace(5) %alloca ret void } -define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { +define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1347,12 +1341,12 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1376,14 +1370,13 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 ; GFX11-SDAG-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1406,14 +1399,13 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 ; GFX11-GISEL-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1438,17 +1430,17 @@ define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { ret void } -define void @test_dynamic_stackalloc_device_divergent() { +define void @test_dynamic_stackalloc_device_divergent() #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1472,13 +1464,13 @@ define void @test_dynamic_stackalloc_device_divergent() { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1502,14 +1494,14 @@ define void @test_dynamic_stackalloc_device_divergent() { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX11-SDAG-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 @@ -1533,14 +1525,14 @@ define void @test_dynamic_stackalloc_device_divergent() { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -1567,14 +1559,13 @@ define void @test_dynamic_stackalloc_device_divergent() { ret void } -define void @test_dynamic_stackalloc_device_divergent_over_aligned() { +define void @test_dynamic_stackalloc_device_divergent_over_aligned() #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_mov_b32 s10, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-SDAG-NEXT: s_mov_b32 s11, s34 -; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 @@ -1584,6 +1575,7 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s7, 0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GFX9-SDAG-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s8, s[4:5] ; GFX9-SDAG-NEXT: v_readlane_b32 s9, v0, s8 @@ -1606,16 +1598,16 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0x1fc0 ; GFX9-GISEL-NEXT: s_mov_b32 s10, s34 -; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 -; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 -; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x4000 ; GFX9-GISEL-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1641,20 +1633,19 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-SDAG-NEXT: s_mov_b32 s5, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-SDAG-NEXT: s_mov_b32 s6, s34 -; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x100 ; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo ; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0xfff ; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 -; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 -; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000 +; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 ; GFX11-SDAG-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s3, s2 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1666,29 +1657,28 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX11-SDAG-NEXT: ; %bb.2: ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0 ; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x1bc +; GFX11-SDAG-NEXT: s_mov_b32 s33, s5 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 ; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s0 dlc ; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-SDAG-NEXT: s_mov_b32 s32, s34 ; GFX11-SDAG-NEXT: s_mov_b32 s34, s6 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s5 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 0x7f ; GFX11-GISEL-NEXT: s_mov_b32 s5, s34 -; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 -; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x100 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -1703,13 +1693,12 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x1bc ; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 ; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 ; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 ; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc ; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-GISEL-NEXT: s_mov_b32 s32, s34 ; GFX11-GISEL-NEXT: s_mov_b32 s34, s5 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca i32, i32 %idx, align 128, addrspace(5) @@ -1717,17 +1706,17 @@ define void @test_dynamic_stackalloc_device_divergent_over_aligned() { ret void } -define void @test_dynamic_stackalloc_device_divergent_under_aligned() { +define void @test_dynamic_stackalloc_device_divergent_under_aligned() #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1751,13 +1740,13 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -1781,14 +1770,14 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 ; GFX11-SDAG-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 @@ -1812,14 +1801,14 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -1846,17 +1835,17 @@ define void @test_dynamic_stackalloc_device_divergent_under_aligned() { ret void } -define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { +define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_multiple_allocas: ; GFX9-SDAG: ; %bb.0: ; %entry ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_mov_b32 s13, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-SDAG-NEXT: s_mov_b32 s14, s34 -; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 -; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x3000 ; GFX9-SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-SDAG-NEXT: s_cbranch_execz .LBB14_6 @@ -1936,10 +1925,10 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { ; GFX9-GISEL-NEXT: s_mov_b32 s13, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-GISEL-NEXT: s_mov_b32 s14, s34 -; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 -; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x3000 ; GFX9-GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-GISEL-NEXT: s_cbranch_execz .LBB14_6 @@ -2018,10 +2007,10 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { ; GFX11-SDAG-NEXT: s_mov_b32 s7, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 63 ; GFX11-SDAG-NEXT: s_mov_b32 s8, s34 -; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 -; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0xc0 ; GFX11-SDAG-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11-SDAG-NEXT: s_cbranch_execz .LBB14_6 @@ -2103,10 +2092,10 @@ define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { ; GFX11-GISEL-NEXT: s_mov_b32 s7, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 63 ; GFX11-GISEL-NEXT: s_mov_b32 s8, s34 -; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 -; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xc0 ; GFX11-GISEL-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11-GISEL-NEXT: s_cbranch_execz .LBB14_6 @@ -2196,17 +2185,17 @@ bb.1: ret void } -define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { +define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_control_flow: ; GFX9-SDAG: ; %bb.0: ; %entry ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_mov_b32 s11, s33 ; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-SDAG-NEXT: s_mov_b32 s12, s34 -; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 -; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 ; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x2000 ; GFX9-SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-SDAG-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -2269,10 +2258,10 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { ; GFX9-GISEL-NEXT: s_mov_b32 s11, s33 ; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0xfc0 ; GFX9-GISEL-NEXT: s_mov_b32 s12, s34 -; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 -; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 ; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x2000 ; GFX9-GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GFX9-GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -2335,10 +2324,10 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { ; GFX11-SDAG-NEXT: s_mov_b32 s5, s33 ; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 63 ; GFX11-SDAG-NEXT: s_mov_b32 s6, s34 -; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 -; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 ; GFX11-SDAG-NEXT: s_mov_b32 s0, exec_lo +; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-SDAG-NEXT: s_mov_b32 s34, s32 ; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x80 ; GFX11-SDAG-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GFX11-SDAG-NEXT: s_xor_b32 s0, exec_lo, s0 @@ -2404,10 +2393,10 @@ define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { ; GFX11-GISEL-NEXT: s_mov_b32 s5, s33 ; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 63 ; GFX11-GISEL-NEXT: s_mov_b32 s6, s34 -; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 -; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX11-GISEL-NEXT: s_mov_b32 s1, 0 ; GFX11-GISEL-NEXT: s_mov_b32 s0, exec_lo +; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-GISEL-NEXT: s_mov_b32 s34, s32 ; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x80 ; GFX11-GISEL-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GFX11-GISEL-NEXT: s_xor_b32 s0, exec_lo, s0 @@ -2483,17 +2472,17 @@ bb.2: ret void } -define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 %n) { +define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff0, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2517,13 +2506,13 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2547,15 +2536,15 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_mov_b16_e32 v1.h, 0 ; GFX11-SDAG-NEXT: v_mov_b16_e32 v1.l, v0.l +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v1, 2, 15 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff0, v0 ; GFX11-SDAG-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 @@ -2579,14 +2568,14 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX11-GISEL-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 @@ -2612,16 +2601,16 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 ret void } -define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 %n) { +define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 %n) #0 { ; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 -; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 ; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec ; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 ; GFX9-SDAG-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2645,12 +2634,12 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 ; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 -; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 ; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 ; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec ; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 ; GFX9-GISEL-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] @@ -2674,14 +2663,13 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 ; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 -; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 ; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo ; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 ; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 ; GFX11-SDAG-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -2704,14 +2692,13 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 ; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 -; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 ; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo ; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 -; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 ; GFX11-GISEL-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 ; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 ; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -2735,3 +2722,5 @@ define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 store volatile i32 666, ptr addrspace(5) %alloca ret void } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll index 381b1741517b..0f535c3a3bdb 100644 --- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll @@ -1649,7 +1649,7 @@ define void @too_many_args_use_workitem_id_x_inreg( i32 inreg %arg0, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 inreg %arg7, i32 inreg %arg8, i32 inreg %arg9, i32 inreg %arg10, i32 inreg %arg11, i32 inreg %arg12, i32 inreg %arg13, i32 inreg %arg14, i32 inreg %arg15, i32 inreg %arg16, i32 inreg %arg17, i32 inreg %arg18, i32 inreg %arg19, i32 inreg %arg20, i32 inreg %arg21, i32 inreg %arg22, i32 inreg %arg23, - i32 inreg %arg24, i32 inreg %arg25, i32 inreg %arg26, i32 inreg %arg27, i32 inreg %arg28, i32 inreg %arg29, i32 inreg %arg30, i32 inreg %arg31) { + i32 inreg %arg24, i32 inreg %arg25, i32 inreg %arg26, i32 inreg %arg27, i32 inreg %arg28, i32 inreg %arg29, i32 inreg %arg30, i32 inreg %arg31) #0 { ;%val = call i32 @llvm.amdgcn.workitem.id.x() ;store volatile i32 %val, ptr addrspace(1) poison @@ -1727,12 +1727,12 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr ; GFX9-NEXT: s_or_saveexec_b64 s[20:21], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[20:21] -; GFX9-NEXT: v_writelane_b32 v40, s19, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: s_getpc_b64 s[20:21] ; GFX9-NEXT: s_add_u32 s20, s20, caller_void_func_i32_v2float_inreg@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s21, s21, caller_void_func_i32_v2float_inreg@gotpcrel32@hi+12 ; GFX9-NEXT: s_load_dwordx2 s[20:21], s[20:21], 0x0 +; GFX9-NEXT: v_writelane_b32 v40, s19, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s2, s18 ; GFX9-NEXT: s_mov_b32 s1, s17 @@ -1759,13 +1759,13 @@ define void @caller_void_func_i32_v2float_inreg(i32 inreg %arg0, <2 x float> inr ; GFX11-NEXT: s_or_saveexec_b32 s16, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s16 -; GFX11-NEXT: v_writelane_b32 v40, s3, 2 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_getpc_b64 s[16:17] ; GFX11-NEXT: s_add_u32 s16, s16, caller_void_func_i32_v2float_inreg@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s17, s17, caller_void_func_i32_v2float_inreg@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s3, 2 ; GFX11-NEXT: s_load_b64 s[16:17], s[16:17], 0x0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] @@ -1955,7 +1955,7 @@ define void @void_func_v16bf16_inreg(<16 x bfloat> inreg %arg0) #0 { ret void } -define void @void_func_2_i32_inreg(i32 inreg %arg0, i32 inreg %arg1, ptr addrspace(1) %ptr) { +define void @void_func_2_i32_inreg(i32 inreg %arg0, i32 inreg %arg1, ptr addrspace(1) %ptr) #0 { ; GFX9-LABEL: void_func_2_i32_inreg: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1981,7 +1981,7 @@ define void @void_func_2_i32_inreg(i32 inreg %arg0, i32 inreg %arg1, ptr addrspa ret void } -define void @void_func_2_i64_inreg(i64 inreg %arg0, i64 inreg %arg1, ptr addrspace(1) %ptr) { +define void @void_func_2_i64_inreg(i64 inreg %arg0, i64 inreg %arg1, ptr addrspace(1) %ptr) #0 { ; GFX9-LABEL: void_func_2_i64_inreg: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2010,7 +2010,7 @@ define void @void_func_2_i64_inreg(i64 inreg %arg0, i64 inreg %arg1, ptr addrspa ret void } -define void @void_func_i64_inreg_i32_inreg_i64_inreg(i64 inreg %arg0, i32 inreg %arg1, i64 inreg %arg2, ptr addrspace(1) %ptr) { +define void @void_func_i64_inreg_i32_inreg_i64_inreg(i64 inreg %arg0, i32 inreg %arg1, i64 inreg %arg2, ptr addrspace(1) %ptr) #0 { ; GFX9-LABEL: void_func_i64_inreg_i32_inreg_i64_inreg: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2046,7 +2046,7 @@ define void @void_func_i64_inreg_i32_inreg_i64_inreg(i64 inreg %arg0, i32 inreg ret void } -define void @void_func_5_i32_inreg(i32 inreg %arg0, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, ptr addrspace(1) %ptr) { +define void @void_func_5_i32_inreg(i32 inreg %arg0, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, ptr addrspace(1) %ptr) #0 { ; GFX9-LABEL: void_func_5_i32_inreg: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2092,7 +2092,7 @@ define void @void_func_5_i32_inreg(i32 inreg %arg0, i32 inreg %arg1, i32 inreg % ret void } -define void @void_func_a5i32_inreg([5 x i32] inreg %arg0, ptr addrspace(1) %ptr) { +define void @void_func_a5i32_inreg([5 x i32] inreg %arg0, ptr addrspace(1) %ptr) #0 { ; GFX9-LABEL: void_func_a5i32_inreg: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2123,7 +2123,7 @@ define void @void_func_a5i32_inreg([5 x i32] inreg %arg0, ptr addrspace(1) %ptr) ; Force all implicit inputs to be required declare void @extern() -define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %ptr) { +define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %ptr) #0 { ; GFX9-LABEL: void_func_a13i32_inreg: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2132,7 +2132,6 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX9-NEXT: s_or_saveexec_b64 s[40:41], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[40:41] -; GFX9-NEXT: v_writelane_b32 v40, s29, 2 ; GFX9-NEXT: v_mov_b32_e32 v2, s28 ; GFX9-NEXT: global_store_dword v[0:1], v2, off offset:48 ; GFX9-NEXT: v_mov_b32_e32 v5, s27 @@ -2141,13 +2140,13 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX9-NEXT: v_mov_b32_e32 v2, s24 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:32 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: v_writelane_b32 v40, s29, 2 ; GFX9-NEXT: v_mov_b32_e32 v5, s23 ; GFX9-NEXT: v_mov_b32_e32 v4, s22 ; GFX9-NEXT: v_mov_b32_e32 v3, s21 ; GFX9-NEXT: v_mov_b32_e32 v2, s20 ; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:16 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, s17 ; GFX9-NEXT: v_mov_b32_e32 v2, s16 ; GFX9-NEXT: s_getpc_b64 s[16:17] @@ -2156,6 +2155,7 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX9-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 ; GFX9-NEXT: v_mov_b32_e32 v5, s19 ; GFX9-NEXT: v_mov_b32_e32 v4, s18 +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: global_store_dwordx4 v[0:1], v[2:5], off ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[16:17] @@ -2178,7 +2178,6 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX11-NEXT: s_or_saveexec_b32 s26, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s26 -; GFX11-NEXT: v_writelane_b32 v40, s25, 2 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v3, s21 ; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v9, s19 @@ -2188,18 +2187,20 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ; GFX11-NEXT: v_dual_mov_b32 v8, s18 :: v_dual_mov_b32 v7, s17 ; GFX11-NEXT: v_dual_mov_b32 v6, s16 :: v_dual_mov_b32 v13, s3 ; GFX11-NEXT: s_load_b64 s[16:17], s[20:21], 0x0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s25, 2 ; GFX11-NEXT: v_dual_mov_b32 v14, s24 :: v_dual_mov_b32 v5, s23 ; GFX11-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v10, s0 -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: global_store_b32 v[0:1], v14, off offset:48 ; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off offset:32 ; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16 ; GFX11-NEXT: global_store_b128 v[0:1], v[10:13], off +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[16:17] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -2215,28 +2216,28 @@ define void @void_func_a13i32_inreg([13 x i32] inreg %arg0, ptr addrspace(1) %p ret void } -; define void @void_func_a14i32_inreg([14 x i32] inreg %arg0, ptr addrspace(1) %ptr) { +; define void @void_func_a14i32_inreg([14 x i32] inreg %arg0, ptr addrspace(1) %ptr) #0 { ; store [14 x i32] %arg0, ptr addrspace(1) %ptr ; call void @extern() ; ret void ; } ; FIXME: -; define void @void_func_a15i32_inreg([15 x i32] inreg %arg0, ptr addrspace(1) %ptr) { +; define void @void_func_a15i32_inreg([15 x i32] inreg %arg0, ptr addrspace(1) %ptr) #0 { ; store [15 x i32] %arg0, ptr addrspace(1) %ptr ; call void @extern() ; ret void ; } ; FIXME: -; define void @void_func_a16i32_inreg([16 x i32] inreg %arg0, ptr addrspace(1) %ptr) { +; define void @void_func_a16i32_inreg([16 x i32] inreg %arg0, ptr addrspace(1) %ptr) #0 { ; store [16 x i32] %arg0, ptr addrspace(1) %ptr ; call void @extern() ; ret void ; } ; FIXME: Should still fail -define void @void_func_a16i32_inreg__noimplicit([16 x i32] inreg %arg0, ptr addrspace(1) %ptr) { +define void @void_func_a16i32_inreg__noimplicit([16 x i32] inreg %arg0, ptr addrspace(1) %ptr) #0 { ; GFX9-LABEL: void_func_a16i32_inreg__noimplicit: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll index 3ca36a97981f..234eaa8af7ed 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll @@ -162,13 +162,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 @@ -191,14 +191,15 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 1 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -220,13 +221,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 @@ -252,9 +253,9 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc ; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_signext@abs32@hi @@ -283,13 +284,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_signext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_signext@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 @@ -314,13 +315,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_signext@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_signext@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 @@ -345,13 +346,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_signext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_signext@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 @@ -381,9 +382,9 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc ; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i1_zeroext@abs32@hi @@ -412,13 +413,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_zeroext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_zeroext@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 @@ -443,13 +444,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 @@ -474,13 +475,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_zeroext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_zeroext@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 @@ -539,11 +540,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -567,11 +568,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -595,11 +596,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -624,11 +625,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -655,9 +656,9 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_sbyte v0, v[0:1], off glc ; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_signext@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_signext@abs32@lo @@ -684,13 +685,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_sbyte v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_signext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_signext@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -713,13 +714,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: global_load_d16_i8 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -742,13 +743,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: global_load_i8 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_signext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_signext@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -772,13 +773,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_sbyte v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_signext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_signext@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -806,9 +807,9 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc ; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext@abs32@lo @@ -835,13 +836,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_zeroext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_zeroext@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -864,13 +865,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -893,13 +894,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: global_load_u8 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -923,13 +924,13 @@ define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_zeroext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_zeroext@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -986,11 +987,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -1014,11 +1015,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7b ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1042,11 +1043,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1071,11 +1072,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -1102,9 +1103,9 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc ; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_signext@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_signext@abs32@lo @@ -1131,13 +1132,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_signext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_signext@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -1160,13 +1161,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1189,13 +1190,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_signext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_signext@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1219,13 +1220,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_signext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_signext@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -1253,9 +1254,9 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc ; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext@abs32@lo @@ -1282,13 +1283,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_zeroext@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_zeroext@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -1311,13 +1312,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1340,13 +1341,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1370,13 +1371,13 @@ define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off glc dlc ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_zeroext@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_zeroext@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -1433,11 +1434,11 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -1461,11 +1462,11 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 42 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1490,11 +1491,11 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -1551,11 +1552,11 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -1580,10 +1581,10 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 0x7b :: v_dual_mov_b32 v1, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -1609,11 +1610,11 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -1641,10 +1642,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i64@abs32@lo @@ -1671,14 +1672,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -1701,14 +1702,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1732,14 +1733,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -1799,11 +1800,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 @@ -1830,9 +1831,9 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 @@ -1860,11 +1861,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 @@ -1894,10 +1895,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i64@abs32@lo @@ -1926,14 +1927,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i64@abs32@hi ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i64@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -1958,14 +1959,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 2 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 1 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i64@abs32@lo ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1989,14 +1990,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i64@abs32@hi ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i64@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -2028,10 +2029,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i64@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i64@abs32@lo @@ -2062,14 +2063,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-NEXT: v_mov_b32_e32 v6, 3 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v7, 4 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i64@abs32@lo @@ -2096,13 +2097,13 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, 2 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 1 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_dual_mov_b32 v6, 3 :: v_dual_mov_b32 v7, 4 ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i64@abs32@hi +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i64@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 @@ -2128,14 +2129,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 3 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v7, 4 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i64@abs32@lo @@ -2197,11 +2198,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x4400 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -2225,11 +2226,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4400 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_f16@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_f16@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -2253,11 +2254,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4400 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_f16@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_f16@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -2282,11 +2283,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x4400 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -2342,11 +2343,11 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -2370,11 +2371,11 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -2399,11 +2400,11 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 4.0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -2460,11 +2461,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -2489,10 +2490,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -2518,11 +2519,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -2581,11 +2582,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32@abs32@hi +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -2611,10 +2612,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32@abs32@hi +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 @@ -2641,11 +2642,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32@abs32@hi +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -2707,11 +2708,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-NEXT: v_mov_b32_e32 v3, -1.0 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0.5 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5f32@abs32@lo @@ -2739,9 +2740,9 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_dual_mov_b32 v2, 4.0 :: v_dual_mov_b32 v3, -1.0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v4, 0.5 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32@abs32@lo @@ -2770,11 +2771,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, -1.0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0.5 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32@abs32@lo @@ -2835,11 +2836,11 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x40100000 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -2864,10 +2865,10 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x40100000 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -2893,11 +2894,11 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x40100000 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -2957,11 +2958,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0x40100000 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 @@ -2988,9 +2989,9 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 @@ -3018,11 +3019,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x40100000 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 @@ -3086,11 +3087,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0x40100000 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0x40200000 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64@abs32@hi @@ -3119,9 +3120,9 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 2.0 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x40100000 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0x40200000 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64@abs32@lo @@ -3150,11 +3151,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 0x40100000 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0x40200000 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64@abs32@hi @@ -3186,10 +3187,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_ushort v0, v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v1, 8 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i8@abs32@hi @@ -3219,15 +3220,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i8@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: v_mov_b32_e32 v1, 8 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 @@ -3252,14 +3253,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v2i8@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v2i8@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 @@ -3285,14 +3286,14 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v2i8@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v2i8@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 @@ -3319,15 +3320,15 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 @@ -3357,10 +3358,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8@abs32@lo @@ -3390,14 +3391,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -3423,14 +3424,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i8@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -3456,14 +3457,14 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -3494,10 +3495,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i8@abs32@lo @@ -3528,14 +3529,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i8@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[0:1], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -3562,14 +3563,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i8@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b32 v0, v[0:1], off +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -3596,14 +3597,14 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -3635,10 +3636,10 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx2 v[5:6], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i8@abs32@lo @@ -3671,14 +3672,14 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i8@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[5:6], v[0:1], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] @@ -3707,14 +3708,14 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i8@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b64 v[5:6], v[0:1], off +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] @@ -3743,14 +3744,14 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[0:1], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] @@ -3784,10 +3785,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i8@abs32@lo @@ -3823,14 +3824,14 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i8@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v0 @@ -3862,14 +3863,14 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i8@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i8@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v8, 8, v0 @@ -3900,14 +3901,14 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v8, 8, v0 @@ -3944,14 +3945,14 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 16 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dwordx4 v[16:19], v[4:5], off +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i8@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i8@abs32@lo ; GFX9-NEXT: s_addk_i32 s32, 0x400 @@ -4015,17 +4016,17 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 16 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i8@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i8@abs32@lo ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[16:19], v[4:5], off +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(1) @@ -4087,15 +4088,15 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16 ; GFX11-NEXT: v_mov_b32_e32 v5, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i8@abs32@hi ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i8@abs32@lo ; GFX11-NEXT: global_load_b128 v[16:19], v[4:5], off +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(1) @@ -4154,17 +4155,17 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 16 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i8@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i8@abs32@lo ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[4:5], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1) @@ -4232,12 +4233,12 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_ubyte v0, v[40:41], off +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_i8_ret@abs32@lo @@ -4268,16 +4269,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_ret@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_ubyte v0, v[40:41], off +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: global_store_byte v[40:41], v0, off @@ -4304,17 +4305,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v[40:41], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-TRUE16-NEXT: global_store_b8 v[40:41], v0, off @@ -4340,17 +4341,17 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_i8_ret@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_u8 v0, v[40:41], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-FAKE16-NEXT: global_store_b8 v[40:41], v0, off @@ -4377,16 +4378,16 @@ define amdgpu_gfx void @test_call_external_void_func_i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v[40:41], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: global_store_byte v[40:41], v0, off @@ -4420,12 +4421,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_ushort v0, v[40:41], off +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v1, 8 ; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret@abs32@hi @@ -4461,16 +4462,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i8_ret@abs32@lo ; GFX10-NEXT: global_load_ushort v0, v[40:41], off +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) @@ -4502,17 +4503,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[40:41], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 @@ -4546,17 +4547,17 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[40:41], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v0 @@ -4590,16 +4591,16 @@ define amdgpu_gfx void @test_call_external_void_func_v2i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: global_load_ushort v0, v[40:41], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) @@ -4638,12 +4639,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dword v0, v[40:41], off +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo @@ -4682,16 +4683,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[40:41], off +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -4726,17 +4727,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -4773,17 +4774,17 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -4821,16 +4822,16 @@ define amdgpu_gfx void @test_call_external_void_func_v3i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -4872,12 +4873,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dword v0, v[40:41], off +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret@abs32@lo @@ -4917,16 +4918,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i8_ret@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v0, v[40:41], off +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -4962,17 +4963,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b32 v0, v[40:41], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -5010,17 +5011,17 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b32 v0, v[40:41], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -5063,16 +5064,16 @@ define amdgpu_gfx void @test_call_external_void_func_v4i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[40:41], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v1, 8, v0 @@ -5115,12 +5116,12 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dwordx2 v[5:6], v[40:41], off +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret@abs32@lo @@ -5165,16 +5166,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i8_ret@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[5:6], v[40:41], off +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] @@ -5215,17 +5216,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b64 v[5:6], v[40:41], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] @@ -5268,17 +5269,17 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b64 v[5:6], v[40:41], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] @@ -5326,16 +5327,16 @@ define amdgpu_gfx void @test_call_external_void_func_v5i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[5:6], v[40:41], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6] @@ -5383,12 +5384,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, 0 ; GFX9-NEXT: v_mov_b32_e32 v41, 0 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[40:41], off +; GFX9-NEXT: v_writelane_b32 v42, s34, 2 ; GFX9-NEXT: v_writelane_b32 v42, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret@abs32@lo @@ -5438,16 +5439,16 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i8_ret@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[40:41], off +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_lshrrev_b32_e32 v8, 8, v0 @@ -5493,17 +5494,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v[40:41], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0 @@ -5551,17 +5552,17 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v[40:41], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v0 @@ -5616,16 +5617,16 @@ define amdgpu_gfx void @test_call_external_void_func_v8i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[40:41], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: v_lshrrev_b32_e32 v8, 8, v0 @@ -5678,7 +5679,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v44, s34, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill @@ -5689,6 +5689,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX9-NEXT: v_mov_b32_e32 v43, 0 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[40:41], off ; GFX9-NEXT: global_load_dwordx4 v[16:19], v[42:43], off +; GFX9-NEXT: v_writelane_b32 v44, s34, 2 ; GFX9-NEXT: v_writelane_b32 v44, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo @@ -5800,7 +5801,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v44, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill @@ -5809,12 +5809,13 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-NEXT: v_mov_b32_e32 v42, 16 ; GFX10-NEXT: v_mov_b32_e32 v41, 0 ; GFX10-NEXT: v_mov_b32_e32 v43, 0 -; GFX10-NEXT: v_writelane_b32 v44, s30, 0 +; GFX10-NEXT: v_writelane_b32 v44, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i8_ret@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i8_ret@abs32@lo ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[40:41], off ; GFX10-NEXT: global_load_dwordx4 v[16:19], v[42:43], off +; GFX10-NEXT: v_writelane_b32 v44, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x400 ; GFX10-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(1) @@ -5923,7 +5924,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-TRUE16-NEXT: s_clause 0x3 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s33 offset:12 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s33 offset:8 @@ -5932,11 +5932,12 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v43, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s30, 0 +; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v[40:41], off ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo ; GFX11-TRUE16-NEXT: global_load_b128 v[16:19], v[42:43], off +; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s30, 0 ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 32 ; GFX11-TRUE16-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) @@ -6050,7 +6051,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-FAKE16-NEXT: s_clause 0x3 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s33 offset:12 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s33 offset:8 @@ -6059,11 +6059,12 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, 0 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v41, 0 :: v_dual_mov_b32 v42, 16 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v43, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s30, 0 +; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX11-FAKE16-NEXT: global_load_b128 v[0:3], v[40:41], off ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo ; GFX11-FAKE16-NEXT: global_load_b128 v[16:19], v[42:43], off +; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s30, 0 ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 32 ; GFX11-FAKE16-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1) @@ -6202,7 +6203,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:12 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v42, s33 offset:4 ; 4-byte Folded Spill @@ -6211,12 +6211,13 @@ define amdgpu_gfx void @test_call_external_void_func_v32i8_ret() #0 { ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v42, 16 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v43, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i8_ret@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i8_ret@abs32@lo ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[40:41], off ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[16:19], v[42:43], off +; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 32 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(1) @@ -6333,8 +6334,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i16@abs32@lo @@ -6361,12 +6362,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_dword v0, v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -6389,12 +6390,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_b32 v0, v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -6418,12 +6419,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -6451,8 +6452,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo @@ -6479,12 +6480,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -6507,12 +6508,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -6536,12 +6537,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -6569,8 +6570,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo @@ -6597,12 +6598,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -6625,12 +6626,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -6654,12 +6655,12 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -6717,11 +6718,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-NEXT: v_mov_b32_e32 v1, 3 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -6746,10 +6747,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 0x20001 :: v_dual_mov_b32 v1, 3 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -6775,11 +6776,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 3 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -6837,11 +6838,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x40003c00 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x4400 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -6866,11 +6867,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x40003c00 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x4400 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -6896,11 +6897,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x40003c00 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x4400 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -6928,8 +6929,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo @@ -6956,12 +6957,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -6984,12 +6985,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -7013,12 +7014,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -7076,11 +7077,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x40003 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -7105,11 +7106,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX11-NEXT: v_mov_b32_e32 v1, 0x40003 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -7135,11 +7136,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0x20001 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 0x40003 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -7167,8 +7168,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2f16@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2f16@abs32@lo @@ -7195,12 +7196,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_dword v0, v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -7223,12 +7224,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_b32 v0, v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -7252,12 +7253,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_dword v0, v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -7285,8 +7286,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo @@ -7313,12 +7314,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -7341,12 +7342,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -7370,12 +7371,12 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_dwordx2 v[0:1], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -7433,11 +7434,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -7462,10 +7463,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -7491,11 +7492,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -7554,11 +7555,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32@abs32@hi +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -7584,10 +7585,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4 ; GFX11-NEXT: v_mov_b32_e32 v2, 5 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32@abs32@hi +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 @@ -7614,11 +7615,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32@abs32@hi +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -7679,11 +7680,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-NEXT: v_mov_b32_e32 v3, 6 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 @@ -7710,9 +7711,9 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4 ; GFX11-NEXT: v_dual_mov_b32 v2, 5 :: v_dual_mov_b32 v3, 6 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 @@ -7740,11 +7741,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 5 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 6 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 @@ -7774,8 +7775,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo @@ -7802,12 +7803,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -7830,12 +7831,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -7859,12 +7860,12 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32() #0 { ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v[0:1], off -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -7924,11 +7925,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 @@ -7955,9 +7956,9 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 @@ -7985,11 +7986,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 @@ -8052,11 +8053,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32@abs32@lo @@ -8084,9 +8085,9 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v4, 5 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32@abs32@lo @@ -8115,11 +8116,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32@abs32@lo @@ -8155,12 +8156,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v8i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v8i32@abs32@lo +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 @@ -8185,13 +8186,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v8, s[34:35] ; GFX10-NEXT: global_load_dwordx4 v[4:7], v8, s[34:35] offset:16 -; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -8219,12 +8219,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v4, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: global_load_b128 v[0:3], v4, s[0:1] ; GFX11-NEXT: global_load_b128 v[4:7], v4, s[0:1] offset:16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 @@ -8253,13 +8253,12 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v8, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v8, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v8, s[0:1] offset:16 -; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32@abs32@lo ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -8326,11 +8325,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-NEXT: v_mov_b32_e32 v5, 6 ; GFX10-NEXT: v_mov_b32_e32 v6, 7 @@ -8361,9 +8360,9 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v4, 5 :: v_dual_mov_b32 v5, 6 ; GFX11-NEXT: v_dual_mov_b32 v6, 7 :: v_dual_mov_b32 v7, 8 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32@abs32@hi @@ -8393,11 +8392,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v3, 4 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v4, 5 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v5, 6 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v6, 7 @@ -8436,7 +8435,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v16, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v16, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16 @@ -8444,6 +8442,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX9-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v16i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v16i32@abs32@lo +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 @@ -8468,7 +8467,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v16, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x3 @@ -8476,7 +8474,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX10-NEXT: global_load_dwordx4 v[4:7], v16, s[34:35] offset:16 ; GFX10-NEXT: global_load_dwordx4 v[8:11], v16, s[34:35] offset:32 ; GFX10-NEXT: global_load_dwordx4 v[12:15], v16, s[34:35] offset:48 -; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16i32@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -8504,7 +8502,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v12, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x3 @@ -8512,6 +8509,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX11-NEXT: global_load_b128 v[4:7], v12, s[0:1] offset:16 ; GFX11-NEXT: global_load_b128 v[8:11], v12, s[0:1] offset:32 ; GFX11-NEXT: global_load_b128 v[12:15], v12, s[0:1] offset:48 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16i32@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 @@ -8540,7 +8538,6 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v16, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x3 @@ -8548,7 +8545,7 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32() #0 { ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[4:7], v16, s[0:1] offset:16 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[8:11], v16, s[0:1] offset:32 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[12:15], v16, s[0:1] offset:48 -; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16i32@abs32@lo ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -8584,7 +8581,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v28, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v28, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v28, s[34:35] offset:16 @@ -8597,6 +8593,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX9-NEXT: global_load_dwordx4 v[28:31], v28, s[34:35] offset:112 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32@abs32@lo +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 @@ -8621,7 +8618,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x7 @@ -8633,7 +8629,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80 ; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96 ; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112 -; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -8661,7 +8657,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v28, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_clause 0x7 @@ -8673,6 +8668,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80 ; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96 ; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 @@ -8701,7 +8697,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x7 @@ -8713,7 +8708,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32() #0 { ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112 -; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32@abs32@lo ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -8749,7 +8744,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX9-NEXT: v_mov_b32_e32 v28, 0 ; GFX9-NEXT: global_load_dword v32, v[0:1], off ; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_dwordx4 v[0:3], v28, s[34:35] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v28, s[34:35] offset:16 @@ -8760,6 +8754,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX9-NEXT: global_load_dwordx4 v[24:27], v28, s[34:35] offset:96 ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: global_load_dwordx4 v[28:31], v28, s[34:35] offset:112 +; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32@abs32@lo ; GFX9-NEXT: v_writelane_b32 v40, s31, 1 @@ -8789,7 +8784,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: global_load_dword v33, v[0:1], off ; GFX10-NEXT: s_waitcnt lgkmcnt(0) @@ -8802,7 +8796,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-NEXT: global_load_dwordx4 v[20:23], v32, s[34:35] offset:80 ; GFX10-NEXT: global_load_dwordx4 v[24:27], v32, s[34:35] offset:96 ; GFX10-NEXT: global_load_dwordx4 v[28:31], v32, s[34:35] offset:112 -; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v32i32_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v32i32_i32@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -8832,7 +8826,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v28, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: global_load_b32 v32, v[0:1], off ; GFX11-NEXT: s_waitcnt lgkmcnt(0) @@ -8845,6 +8838,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX11-NEXT: global_load_b128 v[20:23], v28, s[0:1] offset:80 ; GFX11-NEXT: global_load_b128 v[24:27], v28, s[0:1] offset:96 ; GFX11-NEXT: global_load_b128 v[28:31], v28, s[0:1] offset:112 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32@abs32@lo ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 @@ -8874,7 +8868,6 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v32, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: global_load_dword v33, v[0:1], off ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) @@ -8887,7 +8880,7 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32(i32) #0 { ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[20:23], v32, s[0:1] offset:80 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[24:27], v32, s[0:1] offset:96 ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[28:31], v32, s[0:1] offset:112 -; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v32i32_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v32i32_i32@abs32@lo ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -8960,14 +8953,14 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou ; GFX10-NEXT: v_writelane_b32 v42, s34, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v40, v0 ; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: s_mov_b32 s35, external_i32_func_i32@abs32@hi +; GFX10-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-NEXT: s_mov_b32 s34, external_i32_func_i32@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v41, v1 +; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: global_store_dword v[40:41], v0, off ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 @@ -8998,9 +8991,9 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:4 ; GFX11-NEXT: scratch_store_b32 off, v41, s33 -; GFX11-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v41, v1 :: v_dual_mov_b32 v40, v0 ; GFX11-NEXT: v_mov_b32_e32 v0, 42 +; GFX11-NEXT: v_writelane_b32 v42, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_i32_func_i32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_i32_func_i32@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 @@ -9034,14 +9027,14 @@ define amdgpu_gfx void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %ou ; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:4 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v41, s33 ; 4-byte Folded Spill -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v40, v0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_i32_func_i32@abs32@hi +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_i32_func_i32@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v41, v1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: global_store_dword v[40:41], v0, off ; GFX10-SCRATCH-NEXT: s_waitcnt_vscnt null, 0x0 @@ -9078,12 +9071,12 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_addk_i32 s32, 0x400 -; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_ubyte v0, v2, s[34:35] ; GFX9-NEXT: global_load_dword v1, v2, s[34:35] offset:4 ; GFX9-NEXT: s_mov_b32 s35, external_void_func_struct_i8_i32@abs32@hi ; GFX9-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32@abs32@lo +; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX9-NEXT: v_readlane_b32 s31, v40, 1 ; GFX9-NEXT: v_readlane_b32 s30, v40, 0 @@ -9108,13 +9101,12 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_ubyte v0, v2, s[34:35] ; GFX10-NEXT: global_load_dword v1, v2, s[34:35] offset:4 -; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_struct_i8_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_struct_i8_i32@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 @@ -9142,8 +9134,8 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: s_add_i32 s32, s32, 16 +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v1, s[0:1] @@ -9175,12 +9167,12 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: s_add_i32 s32, s32, 16 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: global_load_u8 v0, v1, s[0:1] ; GFX11-FAKE16-NEXT: global_load_b32 v1, v1, s[0:1] offset:4 +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 @@ -9209,13 +9201,12 @@ define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v2, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: s_clause 0x1 ; GFX10-SCRATCH-NEXT: global_load_ubyte v0, v2, s[0:1] ; GFX10-SCRATCH-NEXT: global_load_dword v1, v2, s[0:1] offset:4 -; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_struct_i8_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_struct_i8_i32@abs32@lo ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 @@ -9246,8 +9237,8 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 3 +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX9-NEXT: v_mov_b32_e32 v0, 8 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -9281,9 +9272,9 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_byval_struct_i8_i32@abs32@lo +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 @@ -9313,9 +9304,9 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 3 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX11-TRUE16-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo +; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b8 off, v0, s33 ; GFX11-TRUE16-NEXT: scratch_store_b32 off, v1, s33 offset:4 @@ -9345,9 +9336,9 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX11-FAKE16-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo +; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: scratch_store_b8 off, v0, s33 ; GFX11-FAKE16-NEXT: scratch_store_b32 off, v1, s33 offset:4 @@ -9379,9 +9370,9 @@ define amdgpu_gfx void @test_call_external_void_func_byval_struct_i8_i32() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_byval_struct_i8_i32@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_byval_struct_i8_i32@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s33 ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v1, s33 offset:4 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, s33 @@ -9417,10 +9408,10 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: v_mov_b32_e32 v0, 3 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX9-NEXT: v_mov_b32_e32 v0, 8 +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -9458,19 +9449,19 @@ define amdgpu_gfx void @test_call_external_void_func_sret_struct_i8_i32_byval_st ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 3 ; GFX10-NEXT: v_mov_b32_e32 v1, 8 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_sret_struct_i8_i32_byval_struct_i8_i32@abs32@lo ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s33 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_lshrrev_b32_e64 v1, 5, s33 ; GFX10-NEXT: s_addk_i32 s32, 0x400 -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_add_nc_u32_e32 v0, 8, v0 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8 @@ -9694,8 +9685,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: global_load_dwordx4 v[0:3], v0, s[34:35] @@ -9745,8 +9736,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] @@ -9793,8 +9784,8 @@ define amdgpu_gfx void @test_call_external_void_func_v16i8() #0 { ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-SCRATCH-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1] @@ -10121,13 +10112,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i1_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i1_inreg@abs32@lo -; GFX10-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 +; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-NEXT: v_readlane_b32 s30, v40, 0 @@ -10150,14 +10141,15 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 1 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i1_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i1_inreg@abs32@lo -; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: scratch_store_b8 off, v0, s32 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_readlane_b32 s31, v40, 1 ; GFX11-NEXT: v_readlane_b32 s30, v40, 0 ; GFX11-NEXT: s_mov_b32 s32, s33 @@ -10179,13 +10171,13 @@ define amdgpu_gfx void @test_call_external_void_func_i1_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_mov_b32_e32 v0, 1 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i1_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i1_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: scratch_store_byte off, v0, s32 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 ; GFX10-SCRATCH-NEXT: v_readlane_b32 s30, v40, 0 @@ -10242,11 +10234,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i8_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i8_inreg@abs32@lo -; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -10272,11 +10264,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i8_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i8_inreg@abs32@lo -; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -10303,11 +10295,11 @@ define amdgpu_gfx void @test_call_external_void_func_i8_imm_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i8_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i8_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -10367,11 +10359,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i16_inreg@abs32@lo -; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -10397,11 +10389,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i16_inreg@abs32@lo -; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -10428,11 +10420,11 @@ define amdgpu_gfx void @test_call_external_void_func_i16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -10492,11 +10484,11 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 42 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 42 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -10522,11 +10514,11 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 42 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 42 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -10553,11 +10545,11 @@ define amdgpu_gfx void @test_call_external_void_func_i32_imm_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 42 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 42 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -10620,11 +10612,11 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_i64_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_i64_inreg@abs32@lo -; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_movk_i32 s4, 0x7b ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -10653,11 +10645,11 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_i64_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_i64_inreg@abs32@lo -; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_movk_i32 s4, 0x7b ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -10687,11 +10679,11 @@ define amdgpu_gfx void @test_call_external_void_func_i64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_i64_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_i64_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x7b ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 @@ -10761,9 +10753,9 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b64 s[34:35], 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -10798,9 +10790,9 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -10836,9 +10828,9 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -10917,11 +10909,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i64_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i64_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -10956,11 +10948,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -10996,11 +10988,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i64_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i64_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -11082,9 +11074,9 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 8 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b64 s[34:35], 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -11125,9 +11117,9 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 8 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -11169,9 +11161,9 @@ define amdgpu_gfx void @test_call_external_void_func_v3i64_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -11268,9 +11260,9 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 10 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b64 s[34:35], 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -11317,9 +11309,9 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 10 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -11367,9 +11359,9 @@ define amdgpu_gfx void @test_call_external_void_func_v4i64_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b64 s[0:1], 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -11452,11 +11444,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f16_inreg@abs32@lo -; GFX10-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -11482,11 +11474,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_f16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_f16_inreg@abs32@lo -; GFX11-NEXT: s_movk_i32 s4, 0x4400 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_movk_i32 s4, 0x4400 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -11513,11 +11505,11 @@ define amdgpu_gfx void @test_call_external_void_func_f16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_movk_i32 s4, 0x4400 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -11577,11 +11569,11 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 4.0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 4.0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -11607,11 +11599,11 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_f32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_f32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 4.0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 4.0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -11638,11 +11630,11 @@ define amdgpu_gfx void @test_call_external_void_func_f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 4.0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 4.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -11705,11 +11697,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -11738,11 +11730,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -11772,11 +11764,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 @@ -11845,11 +11837,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 5 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -11881,11 +11873,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 5 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -11918,11 +11910,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -12000,11 +11992,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 7 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5f32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5f32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1.0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -12042,11 +12034,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 7 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1.0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -12085,11 +12077,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5f32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5f32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5f32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -12164,11 +12156,11 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_f64_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_f64_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 0x40100000 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -12197,11 +12189,11 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_f64_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_f64_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 0x40100000 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -12231,11 +12223,11 @@ define amdgpu_gfx void @test_call_external_void_func_f64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_f64_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_f64_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40100000 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 @@ -12307,11 +12299,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f64_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f64_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -12346,11 +12338,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -12386,11 +12378,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f64_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f64_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -12474,11 +12466,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 8 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f64_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f64_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2.0 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -12519,11 +12511,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 8 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2.0 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -12565,11 +12557,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f64_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 8 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f64_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f64_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2.0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -12644,11 +12636,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i16_inreg@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -12674,11 +12666,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i16_inreg@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -12705,11 +12697,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -12772,8 +12764,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg@abs32@hi @@ -12804,8 +12796,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi @@ -12837,8 +12829,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi @@ -12906,8 +12898,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg@abs32@hi @@ -12938,8 +12930,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi @@ -12971,8 +12963,8 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi @@ -13041,11 +13033,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i16_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 3 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -13074,11 +13066,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 0x20001 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 0x20001 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 3 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -13108,11 +13100,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 @@ -13178,11 +13170,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3f16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3f16_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_movk_i32 s5, 0x4400 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -13211,11 +13203,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_movk_i32 s5, 0x4400 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -13245,11 +13237,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3f16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3f16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3f16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x40003c00 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_movk_i32 s5, 0x4400 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 @@ -13314,8 +13306,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg@abs32@hi @@ -13346,8 +13338,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi @@ -13379,8 +13371,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi @@ -13449,11 +13441,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i16_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 0x40003 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -13482,11 +13474,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 0x20001 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 0x20001 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 0x40003 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -13516,11 +13508,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i16_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 0x20001 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 0x40003 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 @@ -13583,11 +13575,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_load_dword s4, s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2f16_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2f16_inreg@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] @@ -13613,11 +13605,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2f16_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2f16_inreg@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -13644,11 +13636,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2f16_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 3 +; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_load_dword s4, s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2f16_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2f16_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -13711,8 +13703,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[34:35], 0x0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg@abs32@hi @@ -13743,8 +13735,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi @@ -13776,8 +13768,8 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi @@ -13846,11 +13838,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2i32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -13879,11 +13871,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -13913,11 +13905,11 @@ define amdgpu_gfx void @test_call_external_void_func_v2i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 4 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 2 @@ -13986,11 +13978,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 5 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 3 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 3 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 4 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -14022,11 +14014,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 5 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 3 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 3 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 4 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -14059,11 +14051,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_imm_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 5 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -14138,11 +14130,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3i32_i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3i32_i32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 3 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 3 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 4 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -14177,11 +14169,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 3 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 3 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 4 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -14217,11 +14209,11 @@ define amdgpu_gfx void @test_call_external_void_func_v3i32_i32_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3i32_i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3i32_i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 3 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 4 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -14296,8 +14288,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -14332,8 +14324,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -14369,8 +14361,8 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -14449,11 +14441,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 6 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4i32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -14488,11 +14480,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 6 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -14528,11 +14520,11 @@ define amdgpu_gfx void @test_call_external_void_func_v4i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 6 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -14613,11 +14605,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 7 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v5i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v5i32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -14655,11 +14647,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 7 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -14698,11 +14690,11 @@ define amdgpu_gfx void @test_call_external_void_func_v5i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 7 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v5i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v5i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -14790,9 +14782,9 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 10 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -14836,9 +14828,9 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 10 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -14883,9 +14875,9 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -14986,11 +14978,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 10 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8i32_inreg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8i32_inreg@abs32@lo -; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, 1 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, 2 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 @@ -15037,11 +15029,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 10 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo -; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 +; GFX11-NEXT: s_mov_b32 s4, 1 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, 2 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 @@ -15089,11 +15081,11 @@ define amdgpu_gfx void @test_call_external_void_func_v8i32_imm_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 10 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8i32_inreg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8i32_inreg@abs32@lo -; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-SCRATCH-NEXT: s_mov_b32 s4, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: s_mov_b32 s5, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 @@ -15206,9 +15198,9 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 18 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -15268,9 +15260,9 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 18 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -15331,9 +15323,9 @@ define amdgpu_gfx void @test_call_external_void_func_v16i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 18 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -15505,9 +15497,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 28 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -15612,11 +15604,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 28 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_add_i32 s2, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -15715,10 +15707,10 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_inreg() #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_add_i32 s2, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -15936,9 +15928,9 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 28 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[34:35], 0x0 ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-NEXT: v_writelane_b32 v40, s7, 3 @@ -16048,11 +16040,11 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 28 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_add_i32 s3, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: v_writelane_b32 v40, s6, 2 ; GFX11-NEXT: v_writelane_b32 v40, s7, 3 @@ -16155,10 +16147,10 @@ define amdgpu_gfx void @test_call_external_void_func_v32i32_i32_inreg(i32) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 28 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_add_i32 s3, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s6, 2 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s7, 3 @@ -16271,9 +16263,9 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s33 ; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4 +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: s_mov_b32 s35, stack_passed_f64_arg@abs32@hi @@ -16304,11 +16296,10 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s33 offset:4 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: s_mov_b32 s35, stack_passed_f64_arg@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, stack_passed_f64_arg@abs32@lo @@ -16316,6 +16307,7 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:4 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -16338,12 +16330,12 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:8 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: scratch_load_b64 v[32:33], off, s33 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v40, s0, 2 ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: s_mov_b32 s1, stack_passed_f64_arg@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, stack_passed_f64_arg@abs32@lo +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32 @@ -16368,12 +16360,12 @@ define amdgpu_gfx void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, d ; GFX10-SCRATCH-NEXT: scratch_store_dword off, v40, s33 offset:8 ; 4-byte Folded Spill ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: scratch_load_dwordx2 v[32:33], off, s33 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, stack_passed_f64_arg@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, stack_passed_f64_arg@abs32@lo +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GFX10-SCRATCH-NEXT: scratch_store_dwordx2 off, v[32:33], s32 @@ -16403,13 +16395,13 @@ define amdgpu_gfx void @stack_12xv3i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_mov_b32_e32 v0, 12 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -16665,7 +16657,6 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_mov_b32_e32 v0, 8 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -16680,6 +16671,7 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; GFX9-NEXT: v_mov_b32_e32 v0, 14 +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -16740,18 +16732,18 @@ define amdgpu_gfx void @stack_8xv5i32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 8 ; GFX10-NEXT: v_mov_b32_e32 v1, 9 ; GFX10-NEXT: v_mov_b32_e32 v2, 10 ; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_mov_b32_e32 v3, 14 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: v_mov_b32_e32 v0, 11 ; GFX10-NEXT: v_mov_b32_e32 v1, 12 ; GFX10-NEXT: v_mov_b32_e32 v2, 13 +; GFX10-NEXT: v_mov_b32_e32 v3, 14 ; GFX10-NEXT: v_mov_b32_e32 v4, 15 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 @@ -16949,7 +16941,6 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX9-NEXT: s_or_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: s_addk_i32 s32, 0x400 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41000000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 @@ -16964,6 +16955,7 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41500000 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41600000 +; GFX9-NEXT: v_writelane_b32 v40, s34, 2 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x41700000 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0 @@ -17024,18 +17016,18 @@ define amdgpu_gfx void @stack_8xv5f32() #0 { ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 -; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x41000000 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x41100000 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x41200000 ; GFX10-NEXT: s_addk_i32 s32, 0x200 -; GFX10-NEXT: v_mov_b32_e32 v3, 0x41600000 +; GFX10-NEXT: v_writelane_b32 v40, s34, 2 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; GFX10-NEXT: v_mov_b32_e32 v0, 0x41300000 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x41400000 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x41500000 +; GFX10-NEXT: v_mov_b32_e32 v3, 0x41600000 ; GFX10-NEXT: v_mov_b32_e32 v4, 0x41700000 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:12 @@ -17266,10 +17258,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -17293,10 +17285,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -17321,10 +17313,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16(i16 %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -17380,10 +17372,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -17407,10 +17399,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -17435,10 +17427,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16(i16 %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -17494,10 +17486,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -17521,10 +17513,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -17549,10 +17541,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16(i32 %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -17608,10 +17600,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -17635,10 +17627,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -17663,10 +17655,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16(<3 x i16> %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -17722,10 +17714,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -17749,10 +17741,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -17777,10 +17769,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16(<4 x i16> %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -17836,10 +17828,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -17863,10 +17855,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -17891,10 +17883,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16(<8 x i16> %arg) #0 { ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -17950,10 +17942,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -17977,10 +17969,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18005,10 +17997,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16(<16 x i16> %arg) #0 ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -18064,10 +18056,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -18091,10 +18083,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18119,10 +18111,10 @@ define amdgpu_gfx void @test_call_external_void_func_bf16_inreg(i16 inreg %arg) ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -18178,10 +18170,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v1bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v1bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -18205,10 +18197,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18233,10 +18225,10 @@ define amdgpu_gfx void @test_call_external_void_func_v1bf16_inreg(i16 inreg %arg ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v1bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v1bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -18292,10 +18284,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v2bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v2bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -18319,10 +18311,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18347,10 +18339,10 @@ define amdgpu_gfx void @test_call_external_void_func_v2bf16_inreg(i32 inreg %arg ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v2bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v2bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -18406,10 +18398,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v3bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v3bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -18433,10 +18425,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18461,10 +18453,10 @@ define amdgpu_gfx void @test_call_external_void_func_v3bf16_inreg(<3 x i16> inre ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v3bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v3bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -18520,10 +18512,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v4bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v4bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -18547,10 +18539,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18575,10 +18567,10 @@ define amdgpu_gfx void @test_call_external_void_func_v4bf16_inreg(<4 x i16> inre ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v4bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v4bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -18634,10 +18626,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v8bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v8bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -18661,10 +18653,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18689,10 +18681,10 @@ define amdgpu_gfx void @test_call_external_void_func_v8bf16_inreg(<8 x i16> inre ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v8bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v8bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 @@ -18748,10 +18740,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_v16bf16@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_v16bf16@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -18775,10 +18767,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -18803,10 +18795,10 @@ define amdgpu_gfx void @test_call_external_void_func_v16bf16_inreg(<16 x i16> in ; GFX10-SCRATCH-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-SCRATCH-NEXT: s_mov_b32 exec_lo, s1 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s0, 2 -; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: s_mov_b32 s1, external_void_func_v16bf16@abs32@hi ; GFX10-SCRATCH-NEXT: s_mov_b32 s0, external_void_func_v16bf16@abs32@lo ; GFX10-SCRATCH-NEXT: s_add_i32 s32, s32, 16 +; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-SCRATCH-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-SCRATCH-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX10-SCRATCH-NEXT: v_readlane_b32 s31, v40, 1 diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll index 77c34b69820c..124de7e00f02 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll @@ -49,9 +49,9 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 4 +; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s4, external_void_func_void@abs32@lo -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s5, 1 ; GFX10-NEXT: s_mov_b32 s5, external_void_func_void@abs32@hi ; GFX10-NEXT: v_writelane_b32 v40, s30, 2 @@ -83,9 +83,9 @@ define amdgpu_gfx void @test_call_external_void_func_void_clobber_s30_s31_call_e ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 4 +; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s4, external_void_func_void@abs32@lo -; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: v_writelane_b32 v40, s5, 1 ; GFX11-NEXT: s_mov_b32 s5, external_void_func_void@abs32@hi ; GFX11-NEXT: v_writelane_b32 v40, s30, 2 @@ -246,10 +246,10 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: ;;#ASMSTART @@ -283,10 +283,10 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: ;;#ASMSTART @@ -362,16 +362,16 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v41, s34, 2 -; GFX10-NEXT: v_writelane_b32 v41, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX10-NEXT: v_writelane_b32 v41, s31, 1 +; GFX10-NEXT: v_writelane_b32 v41, s30, 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def v31 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_mov_b32_e32 v40, v31 +; GFX10-NEXT: v_writelane_b32 v41, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_mov_b32_e32 v31, v40 ; GFX10-NEXT: ;;#ASMSTART @@ -399,18 +399,18 @@ define amdgpu_gfx void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v41, s0, 2 -; GFX11-NEXT: v_writelane_b32 v41, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill -; GFX11-NEXT: v_writelane_b32 v41, s31, 1 +; GFX11-NEXT: v_writelane_b32 v41, s30, 0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def v31 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: v_mov_b32_e32 v40, v31 +; GFX11-NEXT: v_writelane_b32 v41, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_mov_b32_e32 v31, v40 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v31 @@ -480,15 +480,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s33 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s4, s33 +; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_mov_b32 s33, s4 @@ -517,15 +517,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s33(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s33 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s4, s33 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_mov_b32 s33, s4 @@ -597,15 +597,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s34 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: s_mov_b32 s4, s34 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi +; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 +; GFX10-NEXT: s_mov_b32 s4, s34 ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: v_writelane_b32 v40, s30, 1 -; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: s_mov_b32 s34, s4 @@ -634,15 +634,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_s34(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s34 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s4, s34 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_mov_b32 s34, s4 @@ -712,15 +712,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1) ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v41, s34, 2 -; GFX10-NEXT: v_writelane_b32 v41, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX10-NEXT: v_writelane_b32 v41, s31, 1 +; GFX10-NEXT: v_writelane_b32 v41, s30, 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def v40 ; GFX10-NEXT: ;;#ASMEND +; GFX10-NEXT: v_writelane_b32 v41, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; use v40 @@ -747,15 +747,15 @@ define amdgpu_gfx void @test_call_void_func_void_preserves_v40(ptr addrspace(1) ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v41, s0, 2 -; GFX11-NEXT: v_writelane_b32 v41, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill -; GFX11-NEXT: v_writelane_b32 v41, s31, 1 +; GFX11-NEXT: v_writelane_b32 v41, s30, 0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def v40 ; GFX11-NEXT: ;;#ASMEND +; GFX11-NEXT: v_writelane_b32 v41, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; use v40 @@ -870,10 +870,10 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s33@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s33@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -897,10 +897,10 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s33() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s33@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s33@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -955,10 +955,10 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 2 -; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: s_mov_b32 s35, void_func_void_clobber_s34@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, void_func_void_clobber_s34@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 +; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: v_readlane_b32 s31, v40, 1 @@ -982,10 +982,10 @@ define amdgpu_gfx void @test_call_void_func_void_clobber_s34() #0 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 2 -; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: s_mov_b32 s1, void_func_void_clobber_s34@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, void_func_void_clobber_s34@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 ; GFX11-NEXT: v_writelane_b32 v40, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -1049,15 +1049,15 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v40, s34, 3 -; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s40 ; GFX10-NEXT: ;;#ASMEND -; GFX10-NEXT: v_writelane_b32 v40, s30, 1 +; GFX10-NEXT: v_writelane_b32 v40, s4, 0 ; GFX10-NEXT: s_mov_b32 s4, s40 +; GFX10-NEXT: v_writelane_b32 v40, s30, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: ;;#ASMSTART @@ -1085,15 +1085,15 @@ define amdgpu_gfx void @callee_saved_sgpr_kernel() #1 { ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v40, s0, 3 -; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s40 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: v_writelane_b32 v40, s30, 1 +; GFX11-NEXT: v_writelane_b32 v40, s4, 0 ; GFX11-NEXT: s_mov_b32 s4, s40 +; GFX11-NEXT: v_writelane_b32 v40, s30, 1 ; GFX11-NEXT: v_writelane_b32 v40, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: ;;#ASMSTART @@ -1172,12 +1172,11 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s35 ; GFX10-NEXT: v_writelane_b32 v41, s34, 3 -; GFX10-NEXT: v_writelane_b32 v41, s4, 0 ; GFX10-NEXT: s_mov_b32 s35, external_void_func_void@abs32@hi ; GFX10-NEXT: s_mov_b32 s34, external_void_func_void@abs32@lo ; GFX10-NEXT: s_addk_i32 s32, 0x200 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX10-NEXT: v_writelane_b32 v41, s30, 1 +; GFX10-NEXT: v_writelane_b32 v41, s4, 0 ; GFX10-NEXT: ;;#ASMSTART ; GFX10-NEXT: ; def s40 ; GFX10-NEXT: ;;#ASMEND @@ -1186,6 +1185,7 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX10-NEXT: ; def v32 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_mov_b32_e32 v40, v32 +; GFX10-NEXT: v_writelane_b32 v41, s30, 1 ; GFX10-NEXT: v_writelane_b32 v41, s31, 2 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[34:35] ; GFX10-NEXT: ;;#ASMSTART @@ -1217,12 +1217,11 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:4 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 ; GFX11-NEXT: v_writelane_b32 v41, s0, 3 -; GFX11-NEXT: v_writelane_b32 v41, s4, 0 ; GFX11-NEXT: s_mov_b32 s1, external_void_func_void@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, external_void_func_void@abs32@lo ; GFX11-NEXT: s_add_i32 s32, s32, 16 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill -; GFX11-NEXT: v_writelane_b32 v41, s30, 1 +; GFX11-NEXT: v_writelane_b32 v41, s4, 0 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; def s40 ; GFX11-NEXT: ;;#ASMEND @@ -1231,6 +1230,7 @@ define amdgpu_gfx void @callee_saved_sgpr_vgpr_kernel() #1 { ; GFX11-NEXT: ; def v32 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: v_mov_b32_e32 v40, v32 +; GFX11-NEXT: v_writelane_b32 v41, s30, 1 ; GFX11-NEXT: v_writelane_b32 v41, s31, 2 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX11-NEXT: ;;#ASMSTART diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll index 3110bbae6101..b750d28ffa7d 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll @@ -2142,12 +2142,12 @@ define amdgpu_gfx void @call_512xi32() #0 { ; GFX9-NEXT: s_xor_saveexec_b64 s[36:37], -1 ; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:2048 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[36:37] -; GFX9-NEXT: s_mov_b32 s38, s34 -; GFX9-NEXT: s_mov_b32 s34, s32 ; GFX9-NEXT: v_writelane_b32 v2, s30, 0 ; GFX9-NEXT: s_mov_b32 s37, return_512xi32@abs32@hi ; GFX9-NEXT: s_mov_b32 s36, return_512xi32@abs32@lo ; GFX9-NEXT: v_lshrrev_b32_e64 v0, 6, s33 +; GFX9-NEXT: s_mov_b32 s38, s34 +; GFX9-NEXT: s_mov_b32 s34, s32 ; GFX9-NEXT: s_add_i32 s32, s32, 0x60000 ; GFX9-NEXT: v_writelane_b32 v2, s31, 1 ; GFX9-NEXT: s_swappc_b64 s[30:31], s[36:37] @@ -2172,12 +2172,12 @@ define amdgpu_gfx void @call_512xi32() #0 { ; GFX10-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:2048 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s36 -; GFX10-NEXT: s_mov_b32 s38, s34 -; GFX10-NEXT: s_mov_b32 s34, s32 ; GFX10-NEXT: v_writelane_b32 v2, s30, 0 ; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 ; GFX10-NEXT: s_mov_b32 s37, return_512xi32@abs32@hi ; GFX10-NEXT: s_mov_b32 s36, return_512xi32@abs32@lo +; GFX10-NEXT: s_mov_b32 s38, s34 +; GFX10-NEXT: s_mov_b32 s34, s32 ; GFX10-NEXT: s_add_i32 s32, s32, 0x30000 ; GFX10-NEXT: v_writelane_b32 v2, s31, 1 ; GFX10-NEXT: s_swappc_b64 s[30:31], s[36:37] @@ -2203,12 +2203,12 @@ define amdgpu_gfx void @call_512xi32() #0 { ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v5, s33 offset:2048 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: s_mov_b32 s36, s34 -; GFX11-NEXT: s_mov_b32 s34, s32 ; GFX11-NEXT: v_writelane_b32 v5, s30, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, s33 ; GFX11-NEXT: s_mov_b32 s1, return_512xi32@abs32@hi ; GFX11-NEXT: s_mov_b32 s0, return_512xi32@abs32@lo +; GFX11-NEXT: s_mov_b32 s36, s34 +; GFX11-NEXT: s_mov_b32 s34, s32 ; GFX11-NEXT: s_addk_i32 s32, 0x1800 ; GFX11-NEXT: v_writelane_b32 v5, s31, 1 ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -2910,9 +2910,9 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:1568 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s36 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: s_mov_b32 s38, s34 ; GFX10-NEXT: s_mov_b32 s34, s32 -; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: s_add_i32 s32, s32, 0x14000 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill @@ -2929,8 +2929,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill -; GFX10-NEXT: v_writelane_b32 v63, s30, 0 -; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:8 @@ -2973,11 +2971,13 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; GFX10-NEXT: v_lshrrev_b32_e64 v0, 5, s33 +; GFX10-NEXT: v_writelane_b32 v63, s30, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0 +; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x200, v0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-NEXT: v_add_nc_u32_e32 v0, 0x200, v0 ; GFX10-NEXT: v_mov_b32_e32 v6, 0 ; GFX10-NEXT: v_mov_b32_e32 v7, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, 0 @@ -3189,8 +3189,6 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: scratch_store_b32 off, v60, s33 offset:1600 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-NEXT: s_mov_b32 s36, s34 -; GFX11-NEXT: s_mov_b32 s34, s32 ; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX11-NEXT: v_mov_b32_e32 v4, 0 ; GFX11-NEXT: s_mov_b32 s1, s0 @@ -3198,6 +3196,8 @@ define amdgpu_gfx void @call_72xi32() #1 { ; GFX11-NEXT: s_mov_b32 s3, s0 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: s_mov_b32 s36, s34 +; GFX11-NEXT: s_mov_b32 s34, s32 ; GFX11-NEXT: s_addk_i32 s32, 0xa00 ; GFX11-NEXT: s_clause 0xb ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:44 diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll index 5a344c8ee37f..df784a6e00cf 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll @@ -3,243 +3,32 @@ declare fastcc void @bar() -define fastcc i32 @foo() { +define fastcc i32 @foo() #0 { ; CHECK-LABEL: name: foo ; CHECK: bb.0 (%ir-block.0): ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr30, $sgpr31, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr28 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr29 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr30 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr31 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr32 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr33 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr34 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr35 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr36 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr37 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr38 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr39 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr144 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr145 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr146 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr147 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr148 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr149 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr150 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr151 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr160 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr161 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr162 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr163 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr164 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr165 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr166 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr167 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr176 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr177 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr178 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr179 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr180 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr181 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr182 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr183 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr192 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr193 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr194 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr195 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr196 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr197 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr198 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr199 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr208 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr209 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr210 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr211 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr212 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr213 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr214 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr215 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr224 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr225 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr226 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr227 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr228 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr229 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr230 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr231 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 ; CHECK-NEXT: S_WAITCNT 0 ; CHECK-NEXT: $sgpr16 = S_MOV_B32 $sgpr33 ; CHECK-NEXT: $sgpr33 = S_MOV_B32 $sgpr32 ; CHECK-NEXT: $sgpr17 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr40, 0 ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr17 - ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr16, 2, undef $vgpr40 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION llvm_vector_registers $sgpr33, $vgpr40, 2, 32 - ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $sgpr33 ; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc + ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr16, 2, undef $vgpr40 ; CHECK-NEXT: BUNDLE implicit-def $sgpr16_sgpr17, implicit-def $sgpr16, implicit-def $scc, implicit-def $sgpr17 { ; CHECK-NEXT: $sgpr16_sgpr17 = S_GETPC_B64 ; CHECK-NEXT: $sgpr16 = S_ADD_U32 internal $sgpr16, target-flags(amdgpu-gotprel32-lo) @bar + 4, implicit-def $scc ; CHECK-NEXT: $sgpr17 = S_ADDC_U32 internal $sgpr17, target-flags(amdgpu-gotprel32-hi) @bar + 12, implicit-def $scc, implicit internal $scc ; CHECK-NEXT: } - ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40 - ; CHECK-NEXT: renamable $sgpr16_sgpr17 = S_LOAD_DWORDX2_IMM killed renamable $sgpr16_sgpr17, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4) - ; CHECK-NEXT: S_WAITCNT 49279 ; CHECK-NEXT: S_WAITCNT_VSCNT undef $sgpr_null, 0 ; CHECK-NEXT: BUFFER_GL1_INV implicit $exec ; CHECK-NEXT: BUFFER_GL0_INV implicit $exec + ; CHECK-NEXT: renamable $sgpr16_sgpr17 = S_LOAD_DWORDX2_IMM killed renamable $sgpr16_sgpr17, 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4) + ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr30, 0, $vgpr40 ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr31, 1, $vgpr40 + ; CHECK-NEXT: S_WAITCNT 49279 ; CHECK-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, @bar, csr_amdgpu, implicit killed $sgpr4_sgpr5, implicit killed $sgpr6_sgpr7, implicit killed $sgpr8_sgpr9, implicit killed $sgpr10_sgpr11, implicit killed $sgpr12, implicit killed $sgpr13, implicit killed $sgpr14, implicit killed $sgpr15, implicit killed $vgpr31, implicit $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $vcc_lo = S_MOV_B32 $exec_lo ; CHECK-NEXT: {{ $}} @@ -257,7 +46,6 @@ define fastcc i32 @foo() { ; CHECK-NEXT: $sgpr5 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr5 - ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_register $sgpr32 ; CHECK-NEXT: $sgpr33 = S_MOV_B32 killed $sgpr4 ; CHECK-NEXT: S_WAITCNT 16240 ; CHECK-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit undef $vgpr0 @@ -268,3 +56,5 @@ define fastcc i32 @foo() { 1: br label %1 } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll index db80f5479d36..bd655a88704f 100644 --- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll +++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll @@ -16,7 +16,7 @@ ; so eliminateFrameIndex would not adjust the access to use the ; correct FP offset. -define amdgpu_kernel void @local_stack_offset_uses_sp(ptr addrspace(1) %out) { +define amdgpu_kernel void @local_stack_offset_uses_sp(ptr addrspace(1) %out) #1 { ; MUBUF-LABEL: local_stack_offset_uses_sp: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_add_u32 s0, s0, s17 @@ -103,21 +103,21 @@ entry: ret void } -define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { +define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) #1 { ; MUBUF-LABEL: func_local_stack_offset_uses_sp: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_mov_b32 s5, s33 ; MUBUF-NEXT: s_add_i32 s33, s32, 0x7ffc0 -; MUBUF-NEXT: s_mov_b32 s6, s34 ; MUBUF-NEXT: s_and_b32 s33, s33, 0xfff80000 -; MUBUF-NEXT: s_mov_b32 s34, s32 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x3000, v3 +; MUBUF-NEXT: s_mov_b32 s6, s34 ; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3 ; MUBUF-NEXT: v_mov_b32_e32 v3, 0 ; MUBUF-NEXT: v_mov_b32_e32 v4, 0x2000 ; MUBUF-NEXT: s_mov_b32 s4, 0 +; MUBUF-NEXT: s_mov_b32 s34, s32 ; MUBUF-NEXT: s_add_i32 s32, s32, 0x200000 ; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], s33 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) @@ -145,11 +145,11 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_mov_b32 s32, s34 ; MUBUF-NEXT: s_mov_b32 s34, s6 +; MUBUF-NEXT: s_mov_b32 s33, s5 ; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v4, v6 ; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v7, vcc ; MUBUF-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: s_mov_b32 s33, s5 ; MUBUF-NEXT: s_setpc_b64 s[30:31] ; ; FLATSCR-LABEL: func_local_stack_offset_uses_sp: @@ -157,8 +157,8 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s2, s33 ; FLATSCR-NEXT: s_add_i32 s33, s32, 0x1fff -; FLATSCR-NEXT: s_mov_b32 s3, s34 ; FLATSCR-NEXT: s_and_b32 s33, s33, 0xffffe000 +; FLATSCR-NEXT: s_mov_b32 s3, s34 ; FLATSCR-NEXT: s_mov_b32 s34, s32 ; FLATSCR-NEXT: s_add_i32 s32, s32, 0x8000 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 @@ -186,11 +186,11 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s32, s34 ; FLATSCR-NEXT: s_mov_b32 s34, s3 +; FLATSCR-NEXT: s_mov_b32 s33, s2 ; FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc ; FLATSCR-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; FLATSCR-NEXT: s_waitcnt vmcnt(0) -; FLATSCR-NEXT: s_mov_b32 s33, s2 ; FLATSCR-NEXT: s_setpc_b64 s[30:31] entry: %pin.low = alloca i32, align 8192, addrspace(5) @@ -206,7 +206,7 @@ entry: ret void } -define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out) { +define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out) #1 { ; MUBUF-LABEL: local_stack_offset_uses_sp_flat: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_add_u32 s0, s0, s17 @@ -347,3 +347,4 @@ entry: declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg) #0 attributes #0 = { argmemonly nounwind willreturn writeonly } +attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/nested-calls.ll b/llvm/test/CodeGen/AMDGPU/nested-calls.ll index 94e997cf49dd..ccaf0ac5377e 100644 --- a/llvm/test/CodeGen/AMDGPU/nested-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/nested-calls.ll @@ -18,8 +18,8 @@ define void @test_func_call_external_void_func_i32_imm() #0 { ; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] -; GCN-NEXT: v_writelane_b32 v40, s16, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s16, 2 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, external_void_func_i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, external_void_func_i32@gotpcrel32@hi+12 @@ -52,8 +52,8 @@ define void @test_func_call_external_void_func_i32_imm_stack_use() #0 { ; GCN-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:64 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] -; GCN-NEXT: v_writelane_b32 v40, s16, 2 ; GCN-NEXT: s_addk_i32 s32, 0x1400 +; GCN-NEXT: v_writelane_b32 v40, s16, 2 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, external_void_func_i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, external_void_func_i32@gotpcrel32@hi+12 diff --git a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll index 7155c8e08547..6b6c60ebe2a9 100644 --- a/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll +++ b/llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll @@ -267,7 +267,7 @@ entry: ; Function Attrs: convergent nounwind declare void @_ZL13sleep_foreverv() #0 -attributes #0 = { nounwind "frame-pointer"="all" } +attributes #0 = { "frame-pointer"="all" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!1638, !1639, !1640, !1641} diff --git a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll index bac460949d57..7d5c58f3aa16 100644 --- a/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll +++ b/llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll @@ -118,7 +118,7 @@ bb.2: ; ASSUME1024: .amdhsa_private_segment_fixed_size 1040 ; ASSUME1024: ; ScratchSize: 1040 -define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) { +define amdgpu_kernel void @kernel_non_entry_block_static_alloca_uniformly_reached_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) #2 { ; MUBUF-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x8 @@ -214,13 +214,13 @@ bb.1: ; ASSUME1024: ; ScratchSize: 1088 -define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) { +define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i32 %arg.cond0, i32 %arg.cond1, i32 %in) #2 { ; MUBUF-LABEL: func_non_entry_block_static_alloca_align4: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_mov_b32 s7, s33 -; MUBUF-NEXT: s_mov_b32 s33, s32 ; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 +; MUBUF-NEXT: s_mov_b32 s33, s32 ; MUBUF-NEXT: s_addk_i32 s32, 0x400 ; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc ; MUBUF-NEXT: s_cbranch_execz .LBB2_3 @@ -254,8 +254,8 @@ define void @func_non_entry_block_static_alloca_align4(ptr addrspace(1) %out, i3 ; FLATSCR: ; %bb.0: ; %entry ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s3, s33 -; FLATSCR-NEXT: s_mov_b32 s33, s32 ; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 +; FLATSCR-NEXT: s_mov_b32 s33, s32 ; FLATSCR-NEXT: s_add_i32 s32, s32, 16 ; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc ; FLATSCR-NEXT: s_cbranch_execz .LBB2_3 @@ -310,16 +310,16 @@ bb.2: ret void } -define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) { +define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i32 %arg.cond, i32 %in) #2 { ; MUBUF-LABEL: func_non_entry_block_static_alloca_align64: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_mov_b32 s7, s33 ; MUBUF-NEXT: s_add_i32 s33, s32, 0xfc0 ; MUBUF-NEXT: s_mov_b32 s8, s34 +; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: s_and_b32 s33, s33, 0xfffff000 ; MUBUF-NEXT: s_mov_b32 s34, s32 -; MUBUF-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; MUBUF-NEXT: s_addk_i32 s32, 0x2000 ; MUBUF-NEXT: s_and_saveexec_b64 s[4:5], vcc ; MUBUF-NEXT: s_cbranch_execz .LBB3_2 @@ -354,9 +354,9 @@ define void @func_non_entry_block_static_alloca_align64(ptr addrspace(1) %out, i ; FLATSCR-NEXT: s_mov_b32 s3, s33 ; FLATSCR-NEXT: s_add_i32 s33, s32, 63 ; FLATSCR-NEXT: s_mov_b32 s4, s34 +; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: s_andn2_b32 s33, s33, 63 ; FLATSCR-NEXT: s_mov_b32 s34, s32 -; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: s_addk_i32 s32, 0x80 ; FLATSCR-NEXT: s_and_saveexec_b64 s[0:1], vcc ; FLATSCR-NEXT: s_cbranch_execz .LBB3_2 @@ -407,6 +407,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +attributes #2 = { nounwind } !llvm.module.flags = !{!0} !0 = !{i32 1, !"amdhsa_code_object_version", i32 CODE_OBJECT_VERSION} diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir index c61241c65b32..4db196d4dd96 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir @@ -5,13 +5,15 @@ declare amdgpu_cs_chain void @callee() declare amdgpu_gfx void @gfx_callee() - define amdgpu_cs_chain_preserve void @preserve_active_lanes_above_args() {ret void} - define amdgpu_cs_chain_preserve void @preserve_all_lanes_wwm_above_args() {ret void} - define amdgpu_cs_chain_preserve void @dont_preserve_args() {ret void} - define amdgpu_cs_chain_preserve void @preserve_inactive_lanes_wwm_args() {ret void} - define amdgpu_cs_chain_preserve void @dont_preserve_if_no_chain_calls() {ret void} - define amdgpu_cs_chain_preserve void @dont_preserve_v0_v7() {ret void} - define amdgpu_cs_chain_preserve void @dont_preserve_sgpr() {ret void} + define amdgpu_cs_chain_preserve void @preserve_active_lanes_above_args() #0 {ret void} + define amdgpu_cs_chain_preserve void @preserve_all_lanes_wwm_above_args() #0 {ret void} + define amdgpu_cs_chain_preserve void @dont_preserve_args() #0 {ret void} + define amdgpu_cs_chain_preserve void @preserve_inactive_lanes_wwm_args() #0 {ret void} + define amdgpu_cs_chain_preserve void @dont_preserve_if_no_chain_calls() #0 {ret void} + define amdgpu_cs_chain_preserve void @dont_preserve_v0_v7() #0 {ret void} + define amdgpu_cs_chain_preserve void @dont_preserve_sgpr() #0 {ret void} + + attributes #0 = { nounwind } ... --- @@ -36,114 +38,6 @@ body: | ; GCN-LABEL: name: preserve_active_lanes_above_args ; GCN: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: SCRATCH_STORE_DWORD_ST killed $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: renamable $vgpr10 = V_MOV_B32_e32 10, implicit $exec ; GCN-NEXT: $vgpr8 = COPY killed renamable $vgpr10 @@ -177,125 +71,8 @@ body: | ; GCN-LABEL: name: preserve_all_lanes_wwm_above_args ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr10, 0 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr10 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr10 @@ -337,122 +114,6 @@ body: | ; GCN-LABEL: name: dont_preserve_args ; GCN: liveins: $sgpr0, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: renamable $vgpr8 = V_MOV_B32_e32 10, implicit $exec ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc @@ -484,125 +145,8 @@ body: | ; GCN-LABEL: name: preserve_inactive_lanes_wwm_args ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr9, 0 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr8 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr8 @@ -644,17 +188,6 @@ body: | ; GCN-LABEL: name: dont_preserve_if_no_chain_calls ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr8 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr8 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 @@ -691,116 +224,6 @@ body: | ; GCN-LABEL: name: dont_preserve_v0_v7 ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr8 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr0 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 ; GCN-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0 @@ -839,114 +262,6 @@ body: | ; GCN-LABEL: name: dont_preserve_sgpr ; GCN: liveins: $sgpr0 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $sgpr1 = S_ADD_I32 killed renamable $sgpr0, renamable $sgpr0, implicit-def dead $scc ; GCN-NEXT: $sgpr0 = COPY killed renamable $sgpr1 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir index b4f441237350..d0c673e1cdbd 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir @@ -7,12 +7,14 @@ declare amdgpu_cs_chain void @callee() declare amdgpu_gfx void @gfx_callee() - define amdgpu_cs_chain void @preserve_inactive_wwm() {ret void} - define amdgpu_cs_chain void @dont_preserve_wwm_if_no_chain_calls() {ret void} - define amdgpu_cs_chain void @dont_preserve_wwm_if_init_whole_wave() {ret void} - define amdgpu_cs_chain void @dont_preserve_non_wwm() {ret void} - define amdgpu_cs_chain void @dont_preserve_v0_v7() {ret void} - define amdgpu_cs_chain void @dont_preserve_sgpr() {ret void} + define amdgpu_cs_chain void @preserve_inactive_wwm() #0 {ret void} + define amdgpu_cs_chain void @dont_preserve_wwm_if_no_chain_calls() #0 {ret void} + define amdgpu_cs_chain void @dont_preserve_wwm_if_init_whole_wave() #0 {ret void} + define amdgpu_cs_chain void @dont_preserve_non_wwm() #0 {ret void} + define amdgpu_cs_chain void @dont_preserve_v0_v7() #0 {ret void} + define amdgpu_cs_chain void @dont_preserve_sgpr() #0 {ret void} + + attributes #0 = { nounwind } ... --- @@ -37,127 +39,9 @@ body: | ; GCN-LABEL: name: preserve_inactive_wwm ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $sgpr1 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr8, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr8, 0 ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr9, 128 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) @@ -191,18 +75,6 @@ body: | ; GCN-LABEL: name: dont_preserve_wwm_if_no_chain_calls ; GCN: liveins: $sgpr35, $vgpr8 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 ; GCN-NEXT: $vgpr8 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr8 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 ; GCN-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr8, 0 @@ -236,114 +108,6 @@ body: | ; GCN-LABEL: name: dont_preserve_wwm_if_init_whole_wave ; GCN: liveins: $sgpr0, $sgpr35 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) ; GCN-NEXT: SI_CS_CHAIN_TC_W32 killed renamable $sgpr4_sgpr5, @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr1 @@ -369,116 +133,6 @@ body: | ; GCN-LABEL: name: dont_preserve_non_wwm ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr8, $vgpr16 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $vgpr16 = V_MOV_B32_e32 16, implicit $exec ; GCN-NEXT: renamable $vgpr8 = V_MOV_B32_e32 8, implicit $exec ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc @@ -510,118 +164,6 @@ body: | ; GCN-LABEL: name: dont_preserve_v0_v7 ; GCN: liveins: $sgpr0, $sgpr35, $vgpr0, $vgpr7, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr0 ; GCN-NEXT: $sgpr35 = S_MOV_B32 5 ; GCN-NEXT: $sgpr35 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0 @@ -660,114 +202,6 @@ body: | ; GCN-LABEL: name: dont_preserve_sgpr ; GCN: liveins: $sgpr0 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr6 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr7 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr8 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr9 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr10 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr11 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr12 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr13 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr14 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr15 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr16 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr17 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr18 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr19 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr20 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr21 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr23 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr24 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr25 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr26 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr27 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr28 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr29 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr30 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr31 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr64 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr65 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr66 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr67 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr68 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr69 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr70 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr71 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr72 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr73 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr74 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr75 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr76 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr77 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr78 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr79 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr80 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr81 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr82 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr83 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr84 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr85 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr86 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr87 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr88 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr89 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr90 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr91 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr92 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr93 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr94 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr95 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr96 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr97 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr98 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr99 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr100 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr101 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr102 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr103 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr104 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr105 ; GCN-NEXT: renamable $sgpr1 = S_ADD_I32 killed renamable $sgpr0, renamable $sgpr0, implicit-def dead $scc ; GCN-NEXT: $sgpr0 = COPY killed renamable $sgpr1 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir index 55914bacb0dc..c9208bfa15c6 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir @@ -59,10 +59,6 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v2_partial_agpr ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 @@ -73,10 +69,6 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v2_partial_agpr ; FLATSCR-V2A: liveins: $agpr0 ; FLATSCR-V2A-NEXT: {{ $}} - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) @@ -104,11 +96,6 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v3_partial_agpr ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -121,11 +108,6 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v3_partial_agpr ; FLATSCR-V2A: liveins: $agpr0 ; FLATSCR-V2A-NEXT: {{ $}} - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s64) into %stack.0, align 4, addrspace 5) @@ -153,12 +135,6 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v4_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -173,12 +149,6 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v4_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-V2A-NEXT: {{ $}} - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -210,13 +180,6 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v5_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -233,13 +196,6 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v5_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2 ; FLATSCR-V2A-NEXT: {{ $}} - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 @@ -271,14 +227,6 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v6_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec @@ -297,14 +245,6 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v6_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-V2A-NEXT: {{ $}} - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 @@ -340,16 +280,6 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v8_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; MUBUF-V2A-NEXT: {{ $}} - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -372,16 +302,6 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v8_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; FLATSCR-V2A-NEXT: {{ $}} - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr7, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 @@ -415,24 +335,6 @@ body: | ; MUBUF-V2A-LABEL: name: test_spill_v16_partial_agpr ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_def_aspace_cfa $sgpr32, 0, 6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 - ; MUBUF-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) @@ -471,24 +373,6 @@ body: | ; FLATSCR-V2A-LABEL: name: test_spill_v16_partial_agpr ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-V2A-NEXT: {{ $}} - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 - ; FLATSCR-V2A-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir index 023bcc563cdc..a418e5c631b8 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir @@ -1,16 +1,18 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,+wavefrontsize32,-wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=W32 -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,-wavefrontsize32,+wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=W64 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,+wavefrontsize32,-wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W32 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+block-vgpr-csr,-wavefrontsize32,+wavefrontsize64 -start-before=si-lower-sgpr-spills -stop-after=prologepilog -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK,W64 --- | - define void @one_block() { ret void } - define void @one_block_csr_only() { ret void } - define void @multiple_blocks() { ret void } - define void @reg_tuples() { ret void } - define void @locals() { ret void } - define void @other_regs() { ret void } - define amdgpu_kernel void @entry_func() { ret void } - define void @multiple_basic_blocks() { ret void } + define void @one_block() #0 { ret void } + define void @one_block_csr_only() #0 { ret void } + define void @multiple_blocks() #0 { ret void } + define void @reg_tuples() #0 { ret void } + define void @locals() #0 { ret void } + define void @other_regs() #0 { ret void } + define amdgpu_kernel void @entry_func() #0 { ret void } + define void @multiple_basic_blocks() #0 { ret void } + + attributes #0 = { nounwind } ... # Block load/store v42 and v45. The mask should be 0x9. @@ -23,61 +25,15 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; W32-LABEL: name: one_block - ; W32: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W32-NEXT: $m0 = S_MOV_B32 9 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 - ; W32-NEXT: $m0 = S_MOV_B32 9 - ; W32-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 - ; - ; W64-LABEL: name: one_block - ; W64: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W64-NEXT: $m0 = S_MOV_B32 9 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 - ; W64-NEXT: $m0 = S_MOV_B32 9 - ; W64-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; CHECK-LABEL: name: one_block + ; CHECK: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $m0 = S_MOV_B32 9 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 + ; CHECK-NEXT: $m0 = S_MOV_B32 9 + ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -93,61 +49,15 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; W32-LABEL: name: one_block_csr_only - ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 - ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W32-NEXT: $m0 = S_MOV_B32 16711935 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 - ; W32-NEXT: $m0 = S_MOV_B32 16711935 - ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 - ; - ; W64-LABEL: name: one_block_csr_only - ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 - ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W64-NEXT: $m0 = S_MOV_B32 16711935 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 - ; W64-NEXT: $m0 = S_MOV_B32 16711935 - ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; CHECK-LABEL: name: one_block_csr_only + ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $m0 = S_MOV_B32 16711935 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 + ; CHECK-NEXT: $m0 = S_MOV_B32 16711935 + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -167,125 +77,23 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; W32-LABEL: name: multiple_blocks - ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 - ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 - ; W32-NEXT: $m0 = S_MOV_B32 3 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W32-NEXT: $m0 = S_MOV_B32 65 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) - ; W32-NEXT: $m0 = S_MOV_B32 1 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) - ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 - ; W32-NEXT: $m0 = S_MOV_B32 1 - ; W32-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5) - ; W32-NEXT: $m0 = S_MOV_B32 65 - ; W32-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5) - ; W32-NEXT: $m0 = S_MOV_B32 3 - ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 - ; - ; W64-LABEL: name: multiple_blocks - ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 - ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr112 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr113 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr114 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr115 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr116 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr117 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr118 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr119 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr128 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr129 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr130 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr131 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr132 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr133 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr134 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr135 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr240 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr241 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr242 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr243 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr244 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr245 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr246 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr247 - ; W64-NEXT: $m0 = S_MOV_B32 3 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W64-NEXT: $m0 = S_MOV_B32 65 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) - ; W64-NEXT: $m0 = S_MOV_B32 1 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) - ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 - ; W64-NEXT: $m0 = S_MOV_B32 1 - ; W64-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5) - ; W64-NEXT: $m0 = S_MOV_B32 65 - ; W64-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5) - ; W64-NEXT: $m0 = S_MOV_B32 3 - ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; CHECK-LABEL: name: multiple_blocks + ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $m0 = S_MOV_B32 3 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: $m0 = S_MOV_B32 65 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: $m0 = S_MOV_B32 1 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 + ; CHECK-NEXT: $m0 = S_MOV_B32 1 + ; CHECK-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: $m0 = S_MOV_B32 65 + ; CHECK-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: $m0 = S_MOV_B32 3 + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -303,101 +111,19 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; W32-LABEL: name: reg_tuples - ; W32: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 - ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 - ; W32-NEXT: $m0 = S_MOV_B32 7 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W32-NEXT: $m0 = S_MOV_B32 3 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) - ; W32-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 - ; W32-NEXT: $m0 = S_MOV_B32 3 - ; W32-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5) - ; W32-NEXT: $m0 = S_MOV_B32 7 - ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 - ; - ; W64-LABEL: name: reg_tuples - ; W64: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 - ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr80 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr81 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr82 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr83 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr84 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr85 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr86 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr87 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr96 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr97 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr98 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr99 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr100 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr101 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr102 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr103 - ; W64-NEXT: $m0 = S_MOV_B32 7 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W64-NEXT: $m0 = S_MOV_B32 3 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) - ; W64-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 - ; W64-NEXT: $m0 = S_MOV_B32 3 - ; W64-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5) - ; W64-NEXT: $m0 = S_MOV_B32 7 - ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; CHECK-LABEL: name: reg_tuples + ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $m0 = S_MOV_B32 7 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: $m0 = S_MOV_B32 3 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 + ; CHECK-NEXT: $m0 = S_MOV_B32 3 + ; CHECK-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: $m0 = S_MOV_B32 7 + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -421,65 +147,17 @@ stack: body: | bb.0: liveins: $sgpr30_sgpr31, $vgpr48 - ; W32-LABEL: name: locals - ; W32: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 - ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W32-NEXT: $m0 = S_MOV_B32 1 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) - ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; W32-NEXT: S_NOP 0, implicit-def $vgpr40 - ; W32-NEXT: $m0 = S_MOV_B32 1 - ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5) - ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 - ; - ; W64-LABEL: name: locals - ; W64: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 - ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W64-NEXT: $m0 = S_MOV_B32 1 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) - ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; W64-NEXT: S_NOP 0, implicit-def $vgpr40 - ; W64-NEXT: $m0 = S_MOV_B32 1 - ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5) - ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; CHECK-LABEL: name: locals + ; CHECK: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $m0 = S_MOV_B32 1 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40 + ; CHECK-NEXT: $m0 = S_MOV_B32 1 + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) S_NOP 0, implicit-def $vgpr40 @@ -506,32 +184,10 @@ body: | ; W32-LABEL: name: other_regs ; W32: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 ; W32-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; W32-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr41, 512 ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; W32-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr42, 640 ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) - ; W32-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr44, 768 ; W32-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 ; W32-NEXT: $m0 = S_MOV_B32 9 ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5) @@ -551,32 +207,10 @@ body: | ; W64-LABEL: name: other_regs ; W64: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr22 ; W64-NEXT: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; W64-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr41, 1024 ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; W64-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr42, 1280 ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) - ; W64-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr44, 1536 ; W64-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1 ; W64-NEXT: $m0 = S_MOV_B32 9 ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5) @@ -608,27 +242,11 @@ machineFunctionInfo: body: | bb.0: liveins: $sgpr30_sgpr31 - ; W32-LABEL: name: entry_func - ; W32: liveins: $sgpr30_sgpr31 - ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr42 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr45 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 - ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 - ; - ; W64-LABEL: name: entry_func - ; W64: liveins: $sgpr30_sgpr31 - ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr42 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr45 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 - ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; CHECK-LABEL: name: entry_func + ; CHECK: liveins: $sgpr30_sgpr31 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 + ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45, implicit-def $vgpr51 S_SETPC_B64_return $sgpr30_sgpr31 ... @@ -639,89 +257,29 @@ tracksRegLiveness: true machineFunctionInfo: stackPtrOffsetReg: $sgpr32 body: | - ; W32-LABEL: name: multiple_basic_blocks - ; W32: bb.0: - ; W32-NEXT: successors: %bb.1(0x80000000) - ; W32-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; W32-NEXT: {{ $}} - ; W32-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; W32-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W32-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W32-NEXT: $m0 = S_MOV_B32 11 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 - ; W32-NEXT: S_BRANCH %bb.1 - ; W32-NEXT: {{ $}} - ; W32-NEXT: bb.1: - ; W32-NEXT: successors: %bb.2(0x80000000) - ; W32-NEXT: liveins: $vgpr44, $sgpr30_sgpr31 - ; W32-NEXT: {{ $}} - ; W32-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44 - ; W32-NEXT: S_BRANCH %bb.2 - ; W32-NEXT: {{ $}} - ; W32-NEXT: bb.2: - ; W32-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; W32-NEXT: {{ $}} - ; W32-NEXT: $m0 = S_MOV_B32 11 - ; W32-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 - ; - ; W64-LABEL: name: multiple_basic_blocks - ; W64: bb.0: - ; W64-NEXT: successors: %bb.1(0x80000000) - ; W64-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; W64-NEXT: {{ $}} - ; W64-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 - ; W64-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr48 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr49 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr50 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr51 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr52 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr53 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr54 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr55 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr64 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr65 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr66 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr67 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr68 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr69 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr70 - ; W64-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr71 - ; W64-NEXT: $m0 = S_MOV_B32 11 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 - ; W64-NEXT: S_BRANCH %bb.1 - ; W64-NEXT: {{ $}} - ; W64-NEXT: bb.1: - ; W64-NEXT: successors: %bb.2(0x80000000) - ; W64-NEXT: liveins: $vgpr44, $sgpr30_sgpr31 - ; W64-NEXT: {{ $}} - ; W64-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44 - ; W64-NEXT: S_BRANCH %bb.2 - ; W64-NEXT: {{ $}} - ; W64-NEXT: bb.2: - ; W64-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 - ; W64-NEXT: {{ $}} - ; W64-NEXT: $m0 = S_MOV_B32 11 - ; W64-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) - ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 + ; CHECK-LABEL: name: multiple_basic_blocks + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $m0 = S_MOV_B32 11 + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 + ; CHECK-NEXT: S_BRANCH %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $vgpr44, $sgpr30_sgpr31 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr43, implicit $vgpr44 + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $m0 = S_MOV_B32 11 + ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 bb.0: liveins: $sgpr30_sgpr31, $vgpr44 S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 diff --git a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll index 29e34a0454d1..21f33efbfbdf 100644 --- a/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll +++ b/llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll @@ -17,9 +17,6 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { ; GFX906-NEXT: s_mov_b64 exec, -1 ; GFX906-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:148 ; 4-byte Folded Spill ; GFX906-NEXT: s_mov_b64 exec, s[18:19] -; GFX906-NEXT: v_writelane_b32 v41, s16, 4 -; GFX906-NEXT: v_writelane_b32 v41, s34, 2 -; GFX906-NEXT: v_writelane_b32 v41, s35, 3 ; GFX906-NEXT: s_mov_b32 s21, s15 ; GFX906-NEXT: ; implicit-def: $vgpr39 : SGPR spill to VGPR lane ; GFX906-NEXT: s_mov_b32 s22, s14 @@ -33,8 +30,11 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { ; GFX906-NEXT: v_writelane_b32 v39, s26, 4 ; GFX906-NEXT: v_writelane_b32 v39, s27, 5 ; GFX906-NEXT: v_writelane_b32 v39, s8, 6 +; GFX906-NEXT: v_writelane_b32 v41, s16, 4 ; GFX906-NEXT: v_writelane_b32 v39, s9, 7 +; GFX906-NEXT: v_writelane_b32 v41, s34, 2 ; GFX906-NEXT: v_writelane_b32 v39, s6, 8 +; GFX906-NEXT: v_writelane_b32 v41, s35, 3 ; GFX906-NEXT: v_writelane_b32 v39, s7, 9 ; GFX906-NEXT: v_writelane_b32 v41, s30, 0 ; GFX906-NEXT: v_writelane_b32 v39, s4, 10 @@ -823,5 +823,5 @@ define void @preserve_wwm_copy_dstreg(ptr %parg0, ptr %parg1, ptr %parg2) #0 { declare void @foo() -attributes #0 = { "amdgpu-num-vgpr"="42" "amdgpu-num-sgpr"="40"} +attributes #0 = { nounwind "amdgpu-num-vgpr"="42" "amdgpu-num-sgpr"="40"} diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir index 9e61fa0e681c..925984b15367 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir @@ -30,65 +30,15 @@ body: | ; GCN-NEXT: successors: %bb.1(0x80000000) ; GCN-NEXT: liveins: $vcc_hi, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $sgpr102, $sgpr103, $vgpr0 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr1 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr2 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr3 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr32 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr34 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr35 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr36 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr37 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr38 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr39 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr40 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr41 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr42 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr43 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr44 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr45 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr46 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr47 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr48 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr49 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr50 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr51 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr52 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr53 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr54 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr55 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr56 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr57 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr58 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr59 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr60 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr61 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr62 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION undefined $sgpr63 ; GCN-NEXT: $vcc_hi = frame-setup COPY $sgpr33 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION register $sgpr33, <badreg> ; GCN-NEXT: $sgpr33 = frame-setup COPY $sgpr32 ; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr1, 0 ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr2, 128 ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr3, 256 ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr4, 384 ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr5, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) - ; GCN-NEXT: frame-setup CFI_INSTRUCTION offset $vgpr5, 512 ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 - ; GCN-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x41, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 ; GCN-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2 ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr2 @@ -256,7 +206,6 @@ body: | ; GCN-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) ; GCN-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 - ; GCN-NEXT: frame-destroy CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 ; GCN-NEXT: $sgpr33 = frame-destroy COPY $vcc_hi ; GCN-NEXT: S_ENDPGM 0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll index 3c3a2f11fc96..00214ef36e1f 100644 --- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll +++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll @@ -231,8 +231,8 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, pt ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s33 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 ; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: s_getpc_b64 s[4:5] @@ -382,8 +382,8 @@ define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 { ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v40, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_i32_a32i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_i32_a32i32@gotpcrel32@hi+12 @@ -450,8 +450,8 @@ define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i3 ; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[6:7] -; GCN-NEXT: v_writelane_b32 v42, s4, 2 ; GCN-NEXT: s_addk_i32 s32, 0x400 +; GCN-NEXT: v_writelane_b32 v42, s4, 2 ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: s_add_u32 s4, s4, i32_fastcc_i32_i32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s5, s5, i32_fastcc_i32_i32@gotpcrel32@hi+12 diff --git a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir index bb87b6e52da8..cd9a4d07b870 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir @@ -30,6 +30,66 @@ body: | ; GFX950-LABEL: name: full_copy ; GFX950: liveins: $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27, $agpr28, $agpr29 ; GFX950-NEXT: {{ $}} + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 ; GFX950-NEXT: renamable $agpr0_agpr1 = IMPLICIT_DEF ; GFX950-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF ; GFX950-NEXT: renamable $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27 = IMPLICIT_DEF @@ -136,6 +196,66 @@ body: | ; GFX950-LABEL: name: partial_copy ; GFX950: liveins: $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25, $agpr26, $agpr27 ; GFX950-NEXT: {{ $}} + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; GFX950-NEXT: renamable $agpr0_agpr1 = IMPLICIT_DEF ; GFX950-NEXT: renamable $agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; GFX950-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF @@ -241,6 +361,68 @@ body: | ; GFX950-LABEL: name: full_spill ; GFX950: liveins: $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15, $agpr16, $agpr17, $agpr18, $agpr19, $agpr20, $agpr21, $agpr22, $agpr23, $agpr24, $agpr25 ; GFX950-NEXT: {{ $}} + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x36, 0x24, 0x36, 0xe9, 0x02 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr0 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr1 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr2 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr3 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr4 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr5 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr6 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr7 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr8 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr9 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr10 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr11 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr12 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr13 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr14 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr15 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr16 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr17 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr18 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr19 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr20 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr21 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr22 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr23 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr24 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr25 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr26 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr27 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr28 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr29 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr30 + ; GFX950-NEXT: frame-setup CFI_INSTRUCTION undefined $agpr31 ; GFX950-NEXT: renamable $agpr0_agpr1 = IMPLICIT_DEF ; GFX950-NEXT: renamable $agpr26_agpr27 = IMPLICIT_DEF ; GFX950-NEXT: renamable $agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir index 9da556326326..d87bc0a2c930 100644 --- a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir +++ b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir @@ -40,6 +40,9 @@ body: | ; SRAMECC-EXPANDED: bb.0: ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 @@ -112,6 +115,9 @@ body: | ; SRAMECC-EXPANDED: bb.0: ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 @@ -184,6 +190,9 @@ body: | ; SRAMECC-EXPANDED: bb.0: ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 diff --git a/llvm/test/CodeGen/AMDGPU/spillv16.mir b/llvm/test/CodeGen/AMDGPU/spillv16.mir index 5f1c3b4679b7..ce8645599094 100644 --- a/llvm/test/CodeGen/AMDGPU/spillv16.mir +++ b/llvm/test/CodeGen/AMDGPU/spillv16.mir @@ -55,6 +55,9 @@ body: | ; SRAMECC-EXPANDED: bb.0: ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x09, 0x90, 0x40, 0x94, 0x04, 0x35, 0x24, 0x36, 0xe9, 0x02 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION llvm_register_pair $pc_reg, $sgpr30, 32, $sgpr31, 32 + ; SRAMECC-EXPANDED-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr0 ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, addrspace 5) ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll index cf827945fb5f..52d9a30ffb8b 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll @@ -45,8 +45,6 @@ define void @needs_align16_stack_align4(i32 %idx) #2 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0x3c0 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffffc00 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v2 @@ -59,6 +57,8 @@ define void @needs_align16_stack_align4(i32 %idx) #2 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_or_b32_e32 v1, 8, v0 ; GCN-NEXT: v_mov_b32_e32 v2, 3 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0x2800 ; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) @@ -84,8 +84,6 @@ define void @needs_align32(i32 %idx) #0 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0x7c0 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffff800 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v2 @@ -98,6 +96,8 @@ define void @needs_align32(i32 %idx) #0 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_or_b32_e32 v1, 8, v0 ; GCN-NEXT: v_mov_b32_e32 v2, 3 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0x3000 ; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) @@ -122,10 +122,10 @@ define void @force_realign4(i32 %idx) #1 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xc0 ; GCN-NEXT: s_and_b32 s33, s33, 0xffffff00 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0xd00 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_mov_b32_e32 v1, 3 @@ -174,7 +174,7 @@ define amdgpu_kernel void @kernel_call_align16_from_8() #0 { } ; The call sequence should keep the stack on call aligned to 4 -define amdgpu_kernel void @kernel_call_align16_from_5() { +define amdgpu_kernel void @kernel_call_align16_from_5() #6 { ; GCN-LABEL: kernel_call_align16_from_5: ; GCN: ; %bb.0: ; GCN-NEXT: s_add_i32 s12, s12, s17 @@ -207,7 +207,7 @@ define amdgpu_kernel void @kernel_call_align16_from_5() { ret void } -define amdgpu_kernel void @kernel_call_align4_from_5() { +define amdgpu_kernel void @kernel_call_align4_from_5() #6 { ; GCN-LABEL: kernel_call_align4_from_5: ; GCN: ; %bb.0: ; GCN-NEXT: s_add_i32 s12, s12, s17 @@ -291,9 +291,9 @@ define void @func_call_align1024_bp_gets_vgpr_spill(<32 x i32> %a, i32 %b) #0 { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:1028 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 2 +; GCN-NEXT: v_mov_b32_e32 v32, 0 ; GCN-NEXT: v_writelane_b32 v40, s34, 3 ; GCN-NEXT: s_mov_b32 s34, s32 -; GCN-NEXT: v_mov_b32_e32 v32, 0 ; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:1024 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s34 @@ -342,8 +342,8 @@ define i32 @needs_align1024_stack_args_used_inside_loop(ptr addrspace(5) nocaptu ; GCN-NEXT: s_mov_b32 s11, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xffc0 ; GCN-NEXT: s_mov_b32 s14, s34 -; GCN-NEXT: s_and_b32 s33, s33, 0xffff0000 ; GCN-NEXT: s_mov_b32 s34, s32 +; GCN-NEXT: s_and_b32 s33, s33, 0xffff0000 ; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s34 ; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: s_mov_b32 s10, 0 @@ -412,12 +412,12 @@ define void @no_free_scratch_sgpr_for_bp_copy(<32 x i32> %a, i32 %b) #0 { ; GCN-LABEL: no_free_scratch_sgpr_for_bp_copy: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s40, s33 -; GCN-NEXT: s_add_i32 s33, s32, 0x1fc0 -; GCN-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GCN-NEXT: s_mov_b32 s41, s34 ; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 +; GCN-NEXT: s_mov_b32 s40, s33 +; GCN-NEXT: s_add_i32 s33, s32, 0x1fc0 +; GCN-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GCN-NEXT: s_addk_i32 s32, 0x6000 ; GCN-NEXT: s_mov_b32 s32, s34 ; GCN-NEXT: s_mov_b32 s34, s41 @@ -691,3 +691,4 @@ attributes #2 = { noinline nounwind alignstack=4 } attributes #3 = { noinline nounwind "no-realign-stack" } attributes #4 = { noinline nounwind "frame-pointer"="all"} attributes #5 = { noinline nounwind "amdgpu-waves-per-eu"="6,6" } +attributes #6 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll index 6be2c490e3ea..5c83491e7289 100644 --- a/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll +++ b/llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll @@ -184,8 +184,8 @@ define void @outgoing_f16_arg(ptr %ptr) #0 { ; GFX7-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] -; GFX7-NEXT: v_writelane_b32 v40, s16, 2 ; GFX7-NEXT: flat_load_ushort v0, v[0:1] +; GFX7-NEXT: v_writelane_b32 v40, s16, 2 ; GFX7-NEXT: v_writelane_b32 v40, s30, 0 ; GFX7-NEXT: s_mov_b32 s17, f16_user@abs32@hi ; GFX7-NEXT: s_mov_b32 s16, f16_user@abs32@lo @@ -218,8 +218,8 @@ define void @outgoing_v2f16_arg(ptr %ptr) #0 { ; GFX7-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX7-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX7-NEXT: s_mov_b64 exec, s[18:19] -; GFX7-NEXT: v_writelane_b32 v40, s16, 2 ; GFX7-NEXT: flat_load_dword v1, v[0:1] +; GFX7-NEXT: v_writelane_b32 v40, s16, 2 ; GFX7-NEXT: v_writelane_b32 v40, s30, 0 ; GFX7-NEXT: s_mov_b32 s17, v2f16_user@abs32@hi ; GFX7-NEXT: s_mov_b32 s16, v2f16_user@abs32@lo @@ -555,4 +555,4 @@ declare <2 x half> @llvm.experimental.constrained.fptrunc.v2f16.v2f32(<2 x float declare <3 x half> @llvm.experimental.constrained.fptrunc.v3f16.v3f32(<3 x float>, metadata, metadata) #0 declare <4 x half> @llvm.experimental.constrained.fptrunc.v4f16.v4f32(<4 x float>, metadata, metadata) #0 -attributes #0 = { strictfp } +attributes #0 = { strictfp nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll index eecc9f22db41..5c6fcd4f977e 100644 --- a/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll +++ b/llvm/test/CodeGen/AMDGPU/swdev504645-global-fold.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s -define void @test_load_zext() { +define void @test_load_zext() #0 { ; CHECK-LABEL: test_load_zext: ; CHECK: ; %bb.0: ; %.entry ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -10,8 +10,8 @@ define void @test_load_zext() { ; CHECK-NEXT: s_or_saveexec_b64 s[2:3], -1 ; CHECK-NEXT: scratch_store_dword off, v40, s33 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[2:3] -; CHECK-NEXT: v_writelane_b32 v40, s0, 2 ; CHECK-NEXT: s_add_i32 s32, s32, 16 +; CHECK-NEXT: v_writelane_b32 v40, s0, 2 ; CHECK-NEXT: s_getpc_b64 s[0:1] ; CHECK-NEXT: s_add_u32 s0, s0, has_spgr_args@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s1, s1, has_spgr_args@gotpcrel32@hi+12 @@ -41,4 +41,6 @@ declare void @has_spgr_args(i32 inreg) declare i32 @llvm.amdgcn.reloc.constant(metadata) #0 +attributes #0 = { nounwind } + !0 = !{!"DescriptorBuffer", i32 4, i32 8, i32 0, i32 0} diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll index 153ea2957dd7..d76b2e5f2358 100644 --- a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll +++ b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.error.ll @@ -8,7 +8,7 @@ declare hidden void @void_func_i32_inreg(i32 inreg) ; ERR: error: <unknown>:0:0: in function tail_call_i32_inreg_divergent void (i32): illegal VGPR to SGPR copy ; ERR: error: <unknown>:0:0: in function indirect_tail_call_i32_inreg_divergent void (i32): illegal VGPR to SGPR copy -define void @tail_call_i32_inreg_divergent(i32 %vgpr) { +define void @tail_call_i32_inreg_divergent(i32 %vgpr) #0 { ; CHECK-LABEL: tail_call_i32_inreg_divergent: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -42,7 +42,7 @@ define void @tail_call_i32_inreg_divergent(i32 %vgpr) { @constant = external hidden addrspace(4) constant ptr -define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) { +define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) #0 { ; CHECK-LABEL: indirect_tail_call_i32_inreg_divergent: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -51,8 +51,8 @@ define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) { ; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1 ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] -; CHECK-NEXT: v_writelane_b32 v40, s16, 2 ; CHECK-NEXT: s_addk_i32 s32, 0x400 +; CHECK-NEXT: v_writelane_b32 v40, s16, 2 ; CHECK-NEXT: s_getpc_b64 s[16:17] ; CHECK-NEXT: s_add_u32 s16, s16, constant@rel32@lo+4 ; CHECK-NEXT: s_addc_u32 s17, s17, constant@rel32@hi+12 @@ -76,3 +76,5 @@ define void @indirect_tail_call_i32_inreg_divergent(i32 %vgpr) { tail call void %fptr(i32 inreg %vgpr) ret void } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll index dbfb054c7d16..07f9d64fe71f 100644 --- a/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll +++ b/llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll @@ -4,7 +4,7 @@ declare void @wobble() -define internal fastcc void @widget() { +define internal fastcc void @widget() #0 { ; GFX90A-LABEL: widget: ; GFX90A: ; %bb.0: ; %bb ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -13,8 +13,8 @@ define internal fastcc void @widget() { ; GFX90A-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX90A-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX90A-NEXT: s_mov_b64 exec, s[18:19] -; GFX90A-NEXT: v_writelane_b32 v40, s16, 2 ; GFX90A-NEXT: s_addk_i32 s32, 0x400 +; GFX90A-NEXT: v_writelane_b32 v40, s16, 2 ; GFX90A-NEXT: s_getpc_b64 s[16:17] ; GFX90A-NEXT: s_add_u32 s16, s16, wobble@gotpcrel32@lo+4 ; GFX90A-NEXT: s_addc_u32 s17, s17, wobble@gotpcrel32@hi+12 @@ -28,7 +28,7 @@ bb: unreachable } -define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i32 %tmp5.i.i, i32 %tmp427.i, i1 %tmp438.i, double %tmp27.i, i1 %tmp48.i) { +define amdgpu_kernel void @kernel(ptr addrspace(1) %arg1.global, i1 %tmp3.i.i, i32 %tmp5.i.i, i32 %tmp427.i, i1 %tmp438.i, double %tmp27.i, i1 %tmp48.i) #0 { ; GLOBALNESS1-LABEL: kernel: ; GLOBALNESS1: ; %bb.0: ; %bb ; GLOBALNESS1-NEXT: s_mov_b64 s[36:37], s[6:7] @@ -765,3 +765,4 @@ bb73.i: ; preds = %bb70.i br label %bb5.backedge } +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll index f137f429ebe2..e78d62561238 100644 --- a/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll +++ b/llvm/test/CodeGen/AMDGPU/unfold-masked-merge-scalar-variablemask.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck --check-prefix=GCN %s -define i32 @s_out32(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out32(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -19,7 +19,7 @@ define i32 @s_out32(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { ret i32 %r } -define i64 @s_out64(i64 inreg %x, i64 inreg %y, i64 inreg %mask) { +define i64 @s_out64(i64 inreg %x, i64 inreg %y, i64 inreg %mask) #0 { ; GCN-LABEL: s_out64: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -37,7 +37,7 @@ define i64 @s_out64(i64 inreg %x, i64 inreg %y, i64 inreg %mask) { ret i64 %r } -define i32 @s_in32(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in32(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in32: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -54,7 +54,7 @@ define i32 @s_in32(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { ret i32 %r } -define i64 @s_in64(i64 inreg %x, i64 inreg %y, i64 inreg %mask) { +define i64 @s_in64(i64 inreg %x, i64 inreg %y, i64 inreg %mask) #0 { ; GCN-LABEL: s_in64: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -73,7 +73,7 @@ define i64 @s_in64(i64 inreg %x, i64 inreg %y, i64 inreg %mask) { ; ============================================================================ ; ; Commutativity tests. ; ============================================================================ ; -define i32 @s_in_commutativity_0_0_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_commutativity_0_0_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_commutativity_0_0_1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -90,7 +90,7 @@ define i32 @s_in_commutativity_0_0_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask ret i32 %r } -define i32 @s_in_commutativity_0_1_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_commutativity_0_1_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_commutativity_0_1_0: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -107,7 +107,7 @@ define i32 @s_in_commutativity_0_1_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask ret i32 %r } -define i32 @in_commutativity_0_1_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @in_commutativity_0_1_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: in_commutativity_0_1_1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -124,7 +124,7 @@ define i32 @in_commutativity_0_1_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) ret i32 %r } -define i32 @s_in_commutativity_1_0_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_commutativity_1_0_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_commutativity_1_0_0: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -141,7 +141,7 @@ define i32 @s_in_commutativity_1_0_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask ret i32 %r } -define i32 @s_in_commutativity_1_0_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_commutativity_1_0_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_commutativity_1_0_1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -158,7 +158,7 @@ define i32 @s_in_commutativity_1_0_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask ret i32 %r } -define i32 @s_in_commutativity_1_1_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_commutativity_1_1_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_commutativity_1_1_0: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -175,7 +175,7 @@ define i32 @s_in_commutativity_1_1_0(i32 inreg %x, i32 inreg %y, i32 inreg %mask ret i32 %r } -define i32 @s_in_commutativity_1_1_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_commutativity_1_1_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_commutativity_1_1_1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -194,7 +194,7 @@ define i32 @s_in_commutativity_1_1_1(i32 inreg %x, i32 inreg %y, i32 inreg %mask ; ============================================================================ ; ; Y is an 'and' too. ; ============================================================================ ; -define i32 @s_in_complex_y0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %mask) { +define i32 @s_in_complex_y0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_complex_y0: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -213,7 +213,7 @@ define i32 @s_in_complex_y0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 ret i32 %r } -define i32 @s_in_complex_y1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %mask) { +define i32 @s_in_complex_y1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_complex_y1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -234,7 +234,7 @@ define i32 @s_in_complex_y1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 ; ============================================================================ ; ; M is an 'xor' too. ; ============================================================================ ; -define i32 @s_in_complex_m0(i32 inreg %x, i32 inreg %y, i32 inreg %m_a, i32 inreg %m_b) { +define i32 @s_in_complex_m0(i32 inreg %x, i32 inreg %y, i32 inreg %m_a, i32 inreg %m_b) #0 { ; GCN-LABEL: s_in_complex_m0: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -253,7 +253,7 @@ define i32 @s_in_complex_m0(i32 inreg %x, i32 inreg %y, i32 inreg %m_a, i32 inre ret i32 %r } -define i32 @s_in_complex_m1(i32 inreg %x, i32 inreg %y, i32 inreg %m_a, i32 inreg %m_b) { +define i32 @s_in_complex_m1(i32 inreg %x, i32 inreg %y, i32 inreg %m_a, i32 inreg %m_b) #0 { ; GCN-LABEL: s_in_complex_m1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -274,7 +274,7 @@ define i32 @s_in_complex_m1(i32 inreg %x, i32 inreg %y, i32 inreg %m_a, i32 inre ; ============================================================================ ; ; Both Y and M are complex. ; ============================================================================ ; -define i32 @s_in_complex_y0_m0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) { +define i32 @s_in_complex_y0_m0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) #0 { ; GCN-LABEL: s_in_complex_y0_m0: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -295,7 +295,7 @@ define i32 @s_in_complex_y0_m0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, ret i32 %r } -define i32 @s_in_complex_y1_m0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) { +define i32 @s_in_complex_y1_m0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) #0 { ; GCN-LABEL: s_in_complex_y1_m0: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -316,7 +316,7 @@ define i32 @s_in_complex_y1_m0(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, ret i32 %r } -define i32 @s_in_complex_y0_m1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) { +define i32 @s_in_complex_y0_m1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) #0 { ; GCN-LABEL: s_in_complex_y0_m1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -337,7 +337,7 @@ define i32 @s_in_complex_y0_m1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, ret i32 %r } -define i32 @s_in_complex_y1_m1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) { +define i32 @s_in_complex_y1_m1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, i32 inreg %m_a, i32 inreg %m_b) #0 { ; GCN-LABEL: s_in_complex_y1_m1: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -360,7 +360,7 @@ define i32 @s_in_complex_y1_m1(i32 inreg %x, i32 inreg %y_hi, i32 inreg %y_low, ; ============================================================================ ; ; Various cases with %x and/or %y being a constant ; ============================================================================ ; -define i32 @s_out_constant_varx_mone(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_varx_mone(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_varx_mone: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -376,7 +376,7 @@ define i32 @s_out_constant_varx_mone(i32 inreg %x, i32 inreg %y, i32 inreg %mask ret i32 %r } -define i32 @s_in_constant_varx_mone(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_constant_varx_mone(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_constant_varx_mone: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -392,7 +392,7 @@ define i32 @s_in_constant_varx_mone(i32 inreg %x, i32 inreg %y, i32 inreg %mask) } ; This is not a canonical form. Testing for completeness only. -define i32 @s_out_constant_varx_mone_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_varx_mone_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_varx_mone_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -408,7 +408,7 @@ define i32 @s_out_constant_varx_mone_invmask(i32 inreg %x, i32 inreg %y, i32 inr } ; This is not a canonical form. Testing for completeness only. -define i32 @s_in_constant_varx_mone_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_constant_varx_mone_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_constant_varx_mone_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -425,7 +425,7 @@ define i32 @s_in_constant_varx_mone_invmask(i32 inreg %x, i32 inreg %y, i32 inre ret i32 %r } -define i32 @s_out_constant_varx_42(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_varx_42(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_varx_42: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -443,7 +443,7 @@ define i32 @s_out_constant_varx_42(i32 inreg %x, i32 inreg %y, i32 inreg %mask) ret i32 %r } -define i32 @in_constant_varx_42(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @in_constant_varx_42(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: in_constant_varx_42: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -461,7 +461,7 @@ define i32 @in_constant_varx_42(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { } ; This is not a canonical form. Testing for completeness only. -define i32 @s_out_constant_varx_42_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_varx_42_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_varx_42_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -480,7 +480,7 @@ define i32 @s_out_constant_varx_42_invmask(i32 inreg %x, i32 inreg %y, i32 inreg } ; This is not a canonical form. Testing for completeness only. -define i32 @s_in_constant_varx_42_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_constant_varx_42_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_constant_varx_42_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -498,7 +498,7 @@ define i32 @s_in_constant_varx_42_invmask(i32 inreg %x, i32 inreg %y, i32 inreg ret i32 %r } -define i32 @s_out_constant_mone_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_mone_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_mone_vary: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -513,7 +513,7 @@ define i32 @s_out_constant_mone_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask ret i32 %r } -define i32 @s_in_constant_mone_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_constant_mone_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_constant_mone_vary: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -528,7 +528,7 @@ define i32 @s_in_constant_mone_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) } ; This is not a canonical form. Testing for completeness only. -define i32 @s_out_constant_mone_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_mone_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_mone_vary_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -545,7 +545,7 @@ define i32 @s_out_constant_mone_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inr } ; This is not a canonical form. Testing for completeness only. -define i32 @s_in_constant_mone_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_constant_mone_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_constant_mone_vary_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -560,7 +560,7 @@ define i32 @s_in_constant_mone_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inre ret i32 %r } -define i32 @s_out_constant_42_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_42_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_42_vary: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -578,7 +578,7 @@ define i32 @s_out_constant_42_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) ret i32 %r } -define i32 @s_in_constant_42_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_constant_42_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_constant_42_vary: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -596,7 +596,7 @@ define i32 @s_in_constant_42_vary(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { } ; This is not a canonical form. Testing for completeness only. -define i32 @s_out_constant_42_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_out_constant_42_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_out_constant_42_vary_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -615,7 +615,7 @@ define i32 @s_out_constant_42_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg } ; This is not a canonical form. Testing for completeness only. -define i32 @s_in_constant_42_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_in_constant_42_vary_invmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_in_constant_42_vary_invmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -648,12 +648,12 @@ define i32 @s_in_multiuse_A(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg ; GCN-NEXT: s_mov_b32 exec_lo, s16 ; GCN-NEXT: v_writelane_b32 v40, s2, 4 ; GCN-NEXT: s_add_i32 s32, s32, 16 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, use32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, use32@gotpcrel32@hi+12 ; GCN-NEXT: s_xor_b32 s0, s0, s1 ; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0 +; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: v_writelane_b32 v40, s34, 2 ; GCN-NEXT: s_mov_b32 s34, s1 @@ -693,16 +693,16 @@ define i32 @s_in_multiuse_B(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg ; GCN-NEXT: s_or_saveexec_b32 s16, -1 ; GCN-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b32 exec_lo, s16 -; GCN-NEXT: v_writelane_b32 v40, s2, 4 ; GCN-NEXT: s_add_i32 s32, s32, 16 ; GCN-NEXT: s_getpc_b64 s[16:17] ; GCN-NEXT: s_add_u32 s16, s16, use32@gotpcrel32@lo+4 ; GCN-NEXT: s_addc_u32 s17, s17, use32@gotpcrel32@hi+12 -; GCN-NEXT: v_writelane_b32 v40, s30, 0 +; GCN-NEXT: v_writelane_b32 v40, s2, 4 ; GCN-NEXT: s_load_b64 s[16:17], s[16:17], 0x0 ; GCN-NEXT: s_xor_b32 s0, s0, s1 ; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_writelane_b32 v40, s30, 0 ; GCN-NEXT: v_writelane_b32 v40, s31, 1 ; GCN-NEXT: v_writelane_b32 v40, s34, 2 ; GCN-NEXT: s_mov_b32 s34, s1 @@ -732,7 +732,7 @@ define i32 @s_in_multiuse_B(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg } ; Various bad variants -define i32 @s_n0_badmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask, i32 inreg %mask2) { +define i32 @s_n0_badmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask, i32 inreg %mask2) #0 { ; GCN-LABEL: s_n0_badmask: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -749,7 +749,7 @@ define i32 @s_n0_badmask(i32 inreg %x, i32 inreg %y, i32 inreg %mask, i32 inreg ret i32 %r } -define i32 @s_n0_badxor(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { +define i32 @s_n0_badxor(i32 inreg %x, i32 inreg %y, i32 inreg %mask) #0 { ; GCN-LABEL: s_n0_badxor: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -767,7 +767,7 @@ define i32 @s_n0_badxor(i32 inreg %x, i32 inreg %y, i32 inreg %mask) { ret i32 %r } -define i32 @s_n1_thirdvar(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg %mask) { +define i32 @s_n1_thirdvar(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg %mask) #0 { ; GCN-LABEL: s_n1_thirdvar: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -783,3 +783,5 @@ define i32 @s_n1_thirdvar(i32 inreg %x, i32 inreg %y, i32 inreg %z, i32 inreg %m %r = xor i32 %n1, %z ret i32 %r } + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll index 5beb2237466a..9ce8859c410f 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll +++ b/llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll @@ -5,7 +5,7 @@ declare void @extern_func() #2 -define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) { +define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) #3 { ; The vgpr tuple8 operand in image_gather4_c_b_cl instruction needs not be ; preserved across the call and should get 8 scratch registers. ; GFX9-LABEL: non_preserved_vgpr_tuple8: @@ -16,7 +16,6 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[6:7] -; GFX9-NEXT: v_writelane_b32 v44, s4, 2 ; GFX9-NEXT: v_mov_b32_e32 v36, v16 ; GFX9-NEXT: v_mov_b32_e32 v35, v15 ; GFX9-NEXT: v_mov_b32_e32 v34, v14 @@ -36,6 +35,7 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: ;;#ASMEND ; GFX9-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1 ; GFX9-NEXT: s_addk_i32 s32, 0x800 +; GFX9-NEXT: v_writelane_b32 v44, s4, 2 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 @@ -72,7 +72,6 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s5 -; GFX10-NEXT: v_writelane_b32 v44, s4, 2 ; GFX10-NEXT: v_mov_b32_e32 v36, v16 ; GFX10-NEXT: v_mov_b32_e32 v35, v15 ; GFX10-NEXT: v_mov_b32_e32 v34, v14 @@ -92,12 +91,12 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX10-NEXT: s_addk_i32 s32, 0x400 -; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: v_writelane_b32 v44, s4, 2 ; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v44, s30, 0 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GFX10-NEXT: v_writelane_b32 v44, s30, 0 ; GFX10-NEXT: v_writelane_b32 v44, s31, 1 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] @@ -130,7 +129,6 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v44, s33 offset:16 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-NEXT: v_dual_mov_b32 v36, v16 :: v_dual_mov_b32 v35, v15 ; GFX11-NEXT: v_dual_mov_b32 v34, v14 :: v_dual_mov_b32 v33, v13 ; GFX11-NEXT: v_mov_b32_e32 v32, v12 @@ -149,11 +147,12 @@ define <4 x float> @non_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: image_gather4_c_b_cl v[40:43], v[32:36], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX11-NEXT: s_add_i32 s32, s32, 32 +; GFX11-NEXT: v_writelane_b32 v44, s0, 2 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, extern_func@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, extern_func@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v44, s30, 0 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: v_writelane_b32 v44, s30, 0 ; GFX11-NEXT: v_writelane_b32 v44, s31, 1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1] @@ -194,7 +193,7 @@ main_body: ret <4 x float> %v } -define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) { +define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) #3 { ; The vgpr tuple8 operand in image_gather4_c_b_cl instruction needs to be preserved ; across the call and should get allcoated to 8 CSRs. ; Only the lower 5 sub-registers of the tuple are preserved. @@ -207,7 +206,6 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[6:7] -; GFX9-NEXT: v_writelane_b32 v45, s4, 2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill @@ -220,6 +218,7 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX9-NEXT: v_mov_b32_e32 v40, v12 ; GFX9-NEXT: image_gather4_c_b_cl v[0:3], v[40:44], s[4:11], s[4:7] dmask:0x1 ; GFX9-NEXT: s_addk_i32 s32, 0x800 +; GFX9-NEXT: v_writelane_b32 v45, s4, 2 ; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX9-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 @@ -257,7 +256,6 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill ; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_mov_b32 exec_lo, s5 -; GFX10-NEXT: v_writelane_b32 v45, s4, 2 ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill @@ -265,18 +263,18 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX10-NEXT: buffer_store_dword v44, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX10-NEXT: image_gather4_c_b_cl v[0:3], v[12:16], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX10-NEXT: s_addk_i32 s32, 0x400 -; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: v_writelane_b32 v45, s4, 2 ; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4 ; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+12 -; GFX10-NEXT: v_writelane_b32 v45, s30, 0 -; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v40, v16 +; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-NEXT: v_mov_b32_e32 v41, v15 +; GFX10-NEXT: v_writelane_b32 v45, s30, 0 ; GFX10-NEXT: v_mov_b32_e32 v42, v14 -; GFX10-NEXT: v_writelane_b32 v45, s31, 1 ; GFX10-NEXT: v_mov_b32_e32 v43, v13 ; GFX10-NEXT: v_mov_b32_e32 v44, v12 +; GFX10-NEXT: v_writelane_b32 v45, s31, 1 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX10-NEXT: s_waitcnt lgkmcnt(0) @@ -308,7 +306,6 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: s_or_saveexec_b32 s1, -1 ; GFX11-NEXT: scratch_store_b32 off, v45, s33 offset:20 ; 4-byte Folded Spill ; GFX11-NEXT: s_mov_b32 exec_lo, s1 -; GFX11-NEXT: v_writelane_b32 v45, s0, 2 ; GFX11-NEXT: s_clause 0x4 ; GFX11-NEXT: scratch_store_b32 off, v40, s33 offset:16 ; GFX11-NEXT: scratch_store_b32 off, v41, s33 offset:12 @@ -317,15 +314,16 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp, ; GFX11-NEXT: scratch_store_b32 off, v44, s33 ; GFX11-NEXT: image_gather4_c_b_cl v[0:3], v[12:16], s[0:7], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX11-NEXT: s_add_i32 s32, s32, 32 +; GFX11-NEXT: v_writelane_b32 v45, s0, 2 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: s_add_u32 s0, s0, extern_func@gotpcrel32@lo+4 ; GFX11-NEXT: s_addc_u32 s1, s1, extern_func@gotpcrel32@hi+12 -; GFX11-NEXT: v_writelane_b32 v45, s30, 0 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_dual_mov_b32 v40, v16 :: v_dual_mov_b32 v41, v15 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: v_writelane_b32 v45, s30, 0 ; GFX11-NEXT: v_dual_mov_b32 v42, v14 :: v_dual_mov_b32 v43, v13 -; GFX11-NEXT: v_writelane_b32 v45, s31, 1 ; GFX11-NEXT: v_mov_b32_e32 v44, v12 +; GFX11-NEXT: v_writelane_b32 v45, s31, 1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off ; GFX11-NEXT: s_waitcnt lgkmcnt(0) @@ -367,3 +365,4 @@ declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.2d.v4f32.f32.f32(i32 immar attributes #0 = { nounwind writeonly } attributes #1 = { nounwind readonly } attributes #2 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } +attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index fe3a6c59f172..1805add14e47 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -5,7 +5,7 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -amdgpu-early-ifcvt=1 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032,GFX10DEFWAVE %s -define amdgpu_kernel void @test_vopc_i32(ptr addrspace(1) %arg) { +define amdgpu_kernel void @test_vopc_i32(ptr addrspace(1) %arg) #1 { ; GFX1032-LABEL: test_vopc_i32: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 @@ -38,7 +38,7 @@ define amdgpu_kernel void @test_vopc_i32(ptr addrspace(1) %arg) { ret void } -define amdgpu_kernel void @test_vopc_f32(ptr addrspace(1) %arg) { +define amdgpu_kernel void @test_vopc_f32(ptr addrspace(1) %arg) #1 { ; GFX1032-LABEL: test_vopc_f32: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 @@ -71,7 +71,7 @@ define amdgpu_kernel void @test_vopc_f32(ptr addrspace(1) %arg) { ret void } -define amdgpu_ps void @test_vopc_vcmp(float %x) { +define amdgpu_ps void @test_vopc_vcmp(float %x) #1 { ; GFX1032-LABEL: test_vopc_vcmp: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: v_cmp_nle_f32_e32 vcc_lo, 0, v0 @@ -98,7 +98,7 @@ define amdgpu_ps void @test_vopc_vcmp(float %x) { ret void } -define amdgpu_kernel void @test_vopc_2xf16(ptr addrspace(1) %arg) { +define amdgpu_kernel void @test_vopc_2xf16(ptr addrspace(1) %arg) #1 { ; GFX1032-LABEL: test_vopc_2xf16: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 @@ -197,7 +197,7 @@ define amdgpu_kernel void @test_vcmp_vcnd_f16(ptr addrspace(1) %out, half %x) #0 ret void } -define amdgpu_kernel void @test_vop3_cmp_f32_sop_and(ptr addrspace(1) %arg) { +define amdgpu_kernel void @test_vop3_cmp_f32_sop_and(ptr addrspace(1) %arg) #1 { ; GFX1032-LABEL: test_vop3_cmp_f32_sop_and: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 @@ -236,7 +236,7 @@ define amdgpu_kernel void @test_vop3_cmp_f32_sop_and(ptr addrspace(1) %arg) { ret void } -define amdgpu_kernel void @test_vop3_cmp_i32_sop_xor(ptr addrspace(1) %arg) { +define amdgpu_kernel void @test_vop3_cmp_i32_sop_xor(ptr addrspace(1) %arg) #1 { ; GFX1032-LABEL: test_vop3_cmp_i32_sop_xor: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 @@ -275,7 +275,7 @@ define amdgpu_kernel void @test_vop3_cmp_i32_sop_xor(ptr addrspace(1) %arg) { ret void } -define amdgpu_kernel void @test_vop3_cmp_u32_sop_or(ptr addrspace(1) %arg) { +define amdgpu_kernel void @test_vop3_cmp_u32_sop_or(ptr addrspace(1) %arg) #1 { ; GFX1032-LABEL: test_vop3_cmp_u32_sop_or: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 @@ -1409,7 +1409,7 @@ define amdgpu_kernel void @test_br_cc_f16( ; GFX1064-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a, - ptr addrspace(1) %b) { + ptr addrspace(1) %b) #1 { entry: %a.val = load half, ptr addrspace(1) %a %b.val = load half, ptr addrspace(1) %b @@ -1865,7 +1865,7 @@ break: ret <4 x float> %c.iv } -define amdgpu_ps float @test_wwm1(i32 inreg %idx0, i32 inreg %idx1, float %src0, float %src1) { +define amdgpu_ps float @test_wwm1(i32 inreg %idx0, i32 inreg %idx1, float %src0, float %src1) #1 { ; GFX1032-LABEL: test_wwm1: ; GFX1032: ; %bb.0: ; %main_body ; GFX1032-NEXT: s_or_saveexec_b32 s0, -1 @@ -1891,7 +1891,7 @@ main_body: ret float %out.0 } -define amdgpu_ps float @test_wwm2(i32 inreg %idx) { +define amdgpu_ps float @test_wwm2(i32 inreg %idx) #1 { ; GFX1032-LABEL: test_wwm2: ; GFX1032: ; %bb.0: ; %main_body ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 @@ -1952,7 +1952,7 @@ endif: ret float %out.2 } -define amdgpu_ps float @test_strict_wwm1(i32 inreg %idx0, i32 inreg %idx1, float %src0, float %src1) { +define amdgpu_ps float @test_strict_wwm1(i32 inreg %idx0, i32 inreg %idx1, float %src0, float %src1) #1 { ; GFX1032-LABEL: test_strict_wwm1: ; GFX1032: ; %bb.0: ; %main_body ; GFX1032-NEXT: s_or_saveexec_b32 s0, -1 @@ -1978,7 +1978,7 @@ main_body: ret float %out.0 } -define amdgpu_ps float @test_strict_wwm2(i32 inreg %idx) { +define amdgpu_ps float @test_strict_wwm2(i32 inreg %idx) #1 { ; GFX1032-LABEL: test_strict_wwm2: ; GFX1032: ; %bb.0: ; %main_body ; GFX1032-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 @@ -2119,7 +2119,7 @@ main_body: ret float %out.2 } -define amdgpu_kernel void @test_intr_fcmp_i64(ptr addrspace(1) %out, float %src, float %a) { +define amdgpu_kernel void @test_intr_fcmp_i64(ptr addrspace(1) %out, float %src, float %a) #1 { ; GFX1032-LABEL: test_intr_fcmp_i64: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 @@ -2146,7 +2146,7 @@ define amdgpu_kernel void @test_intr_fcmp_i64(ptr addrspace(1) %out, float %src, ret void } -define amdgpu_kernel void @test_intr_icmp_i64(ptr addrspace(1) %out, i32 %src) { +define amdgpu_kernel void @test_intr_icmp_i64(ptr addrspace(1) %out, i32 %src) #1 { ; GFX1032-LABEL: test_intr_icmp_i64: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_clause 0x1 @@ -2176,7 +2176,7 @@ define amdgpu_kernel void @test_intr_icmp_i64(ptr addrspace(1) %out, i32 %src) { ret void } -define amdgpu_kernel void @test_intr_fcmp_i32(ptr addrspace(1) %out, float %src, float %a) { +define amdgpu_kernel void @test_intr_fcmp_i32(ptr addrspace(1) %out, float %src, float %a) #1 { ; GFX1032-LABEL: test_intr_fcmp_i32: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 @@ -2202,7 +2202,7 @@ define amdgpu_kernel void @test_intr_fcmp_i32(ptr addrspace(1) %out, float %src, ret void } -define amdgpu_kernel void @test_intr_icmp_i32(ptr addrspace(1) %out, i32 %src) { +define amdgpu_kernel void @test_intr_icmp_i32(ptr addrspace(1) %out, i32 %src) #1 { ; GFX1032-LABEL: test_intr_icmp_i32: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: s_clause 0x1 @@ -2231,7 +2231,7 @@ define amdgpu_kernel void @test_intr_icmp_i32(ptr addrspace(1) %out, i32 %src) { ret void } -define amdgpu_ps void @test_wqm_vote(float %a) { +define amdgpu_ps void @test_wqm_vote(float %a) #1 { ; GFX1032-LABEL: test_wqm_vote: ; GFX1032: ; %bb.0: ; GFX1032-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0 @@ -2452,7 +2452,7 @@ main_body: ret float %s.10 } -define amdgpu_kernel void @icmp64(i32 %n, i32 %s) { +define amdgpu_kernel void @icmp64(i32 %n, i32 %s) #1 { ; GFX1032-LABEL: icmp64: ; GFX1032: ; %bb.0: ; %entry ; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28 @@ -2547,7 +2547,7 @@ if.end2: ; preds = %if.end ret void } -define amdgpu_kernel void @fcmp64(float %n, float %s) { +define amdgpu_kernel void @fcmp64(float %n, float %s) #1 { ; GFX1032-LABEL: fcmp64: ; GFX1032: ; %bb.0: ; %entry ; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28 @@ -2759,7 +2759,7 @@ if.end2: ; preds = %if.end ret void } -define amdgpu_kernel void @icmp32(i32 %n, i32 %s) { +define amdgpu_kernel void @icmp32(i32 %n, i32 %s) #1 { ; GFX1032-LABEL: icmp32: ; GFX1032: ; %bb.0: ; %entry ; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28 @@ -2853,7 +2853,7 @@ if.end2: ; preds = %if.end ret void } -define amdgpu_kernel void @fcmp32(float %n, float %s) { +define amdgpu_kernel void @fcmp32(float %n, float %s) #1 { ; GFX1032-LABEL: fcmp32: ; GFX1032: ; %bb.0: ; %entry ; GFX1032-NEXT: s_load_dword s0, s[4:5], 0x28 @@ -3076,13 +3076,13 @@ define void @callee_no_stack_with_call() #1 { ; GFX1032-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX1032-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1032-NEXT: s_mov_b32 exec_lo, s17 -; GFX1032-NEXT: v_writelane_b32 v40, s16, 2 ; GFX1032-NEXT: s_addk_i32 s32, 0x200 +; GFX1032-NEXT: v_writelane_b32 v40, s16, 2 ; GFX1032-NEXT: s_getpc_b64 s[16:17] ; GFX1032-NEXT: s_add_u32 s16, s16, external_void_func_void@gotpcrel32@lo+4 ; GFX1032-NEXT: s_addc_u32 s17, s17, external_void_func_void@gotpcrel32@hi+12 -; GFX1032-NEXT: v_writelane_b32 v40, s30, 0 ; GFX1032-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 +; GFX1032-NEXT: v_writelane_b32 v40, s30, 0 ; GFX1032-NEXT: v_writelane_b32 v40, s31, 1 ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) ; GFX1032-NEXT: s_swappc_b64 s[30:31], s[16:17] @@ -3107,13 +3107,13 @@ define void @callee_no_stack_with_call() #1 { ; GFX1064-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill ; GFX1064-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1064-NEXT: s_mov_b64 exec, s[18:19] -; GFX1064-NEXT: v_writelane_b32 v40, s16, 2 ; GFX1064-NEXT: s_addk_i32 s32, 0x400 +; GFX1064-NEXT: v_writelane_b32 v40, s16, 2 ; GFX1064-NEXT: s_getpc_b64 s[16:17] ; GFX1064-NEXT: s_add_u32 s16, s16, external_void_func_void@gotpcrel32@lo+4 ; GFX1064-NEXT: s_addc_u32 s17, s17, external_void_func_void@gotpcrel32@hi+12 -; GFX1064-NEXT: v_writelane_b32 v40, s30, 0 ; GFX1064-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0 +; GFX1064-NEXT: v_writelane_b32 v40, s30, 0 ; GFX1064-NEXT: v_writelane_b32 v40, s31, 1 ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) ; GFX1064-NEXT: s_swappc_b64 s[30:31], s[16:17] diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll index 75817105e74f..d1d591d19a58 100644 --- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll @@ -9,7 +9,7 @@ ; The EXEC mask should be set to -1 for the duration of the function ; and restored to its original value in the epilogue. ; We will also need to restore the inactive lanes for any allocated VGPRs. -define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { +define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) #0 { ; DAGISEL-LABEL: basic_test: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -136,7 +136,7 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { } ; Make sure we don't crash if there's only one use for %active. -define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 %b) { +define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 %b) #0 { ; DAGISEL-LABEL: single_use_of_active: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -260,7 +260,7 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % } ; Make sure we don't crash if %active is not used at all. -define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) { +define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) #0 { ; DAGISEL-LABEL: unused_active: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -353,7 +353,7 @@ define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) { ; For any used VGPRs (including those used for SGPR spills), we need to restore the inactive lanes. ; For CSR VGPRs, we need to restore all lanes. -define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { +define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) #0 { ; DAGISEL-LABEL: csr: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -558,7 +558,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { } ; Save and restore all lanes of v40. -define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) { +define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) #0 { ; DAGISEL-LABEL: csr_vgpr_only: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -650,7 +650,7 @@ define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) { ret void } -define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) { +define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) #0 { ; DAGISEL-LABEL: sgpr_spill_only: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -767,7 +767,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) { ret void } -define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) { +define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) #0 { ; DAGISEL-LABEL: realign_stack: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -897,7 +897,7 @@ define amdgpu_gfx_whole_wave void @realign_stack(i1 %active, i32 %x) { ret void } -define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { +define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) #0 { ; DAGISEL-LABEL: multiple_blocks: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -1058,7 +1058,7 @@ if.end: ret i32 %e } -define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { +define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) #0 { ; DAGISEL-LABEL: ret_64: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -1216,7 +1216,7 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ret i64 %ret } -define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i32> inreg %v4i32, float inreg %float, ptr addrspace(5) inreg %ptr, ptr addrspace(5) inreg %ptr2) { +define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i32> inreg %v4i32, float inreg %float, ptr addrspace(5) inreg %ptr, ptr addrspace(5) inreg %ptr2) #0 { ; DAGISEL-LABEL: inreg_args: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -1418,7 +1418,7 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i declare amdgpu_gfx <2 x half> @gfx_callee(<2 x half> %x, <2 x half> %y) -define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 x half> %x, <2 x half> %y) { +define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 x half> %x, <2 x half> %y) #0 { ; DAGISEL-LABEL: call_gfx_from_whole_wave: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -4667,7 +4667,7 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ret <2 x half> %ret } -define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %active, <2 x half> %x, <2 x half> %y) { +define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %active, <2 x half> %x, <2 x half> %y) #0 { ; This should not be turned into a tail call. ; DAGISEL-LABEL: tail_call_gfx_from_whole_wave: ; DAGISEL: ; %bb.0: @@ -7815,7 +7815,7 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ declare amdgpu_gfx_whole_wave float @callee(i1 %active, <8 x float> %x) -define amdgpu_cs void @call_from_entry(<8 x float> %x, ptr %p) { +define amdgpu_cs void @call_from_entry(<8 x float> %x, ptr %p) #0 { ; DAGISEL-LABEL: call_from_entry: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_mov_b32 s1, callee@abs32@hi @@ -7871,7 +7871,7 @@ define amdgpu_cs void @call_from_entry(<8 x float> %x, ptr %p) { ret void } -define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> %x, ptr %p) { +define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> %x, ptr %p) #0 { ; DAGISEL-LABEL: call_from_whole_wave: ; DAGISEL: ; %bb.0: ; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -11148,3 +11148,5 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> store float %ret, ptr %p ret void } + +attributes #0 = { nounwind } |