diff options
Diffstat (limited to 'llvm/test/CodeGen')
345 files changed, 30538 insertions, 12727 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir index 86fa12aa064a..4afa0d4378fe 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir @@ -436,6 +436,36 @@ body: | $w0 = COPY %ext(s32) ... --- +# select cond, 0, 64 --> (zext (!Cond)) << log2(Pow2) +name: select_cond_0_64_to_shift +body: | + bb.1: + liveins: $x0, $x1, $x2 + ; CHECK-LABEL: name: select_cond_0_64_to_shift + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %c:_(s1) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR %c, [[C]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[XOR]](s1) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 6 + ; CHECK-NEXT: %sel:_(s8) = G_SHL [[ZEXT]], [[C1]](s8) + ; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %sel(s8) + ; CHECK-NEXT: $w0 = COPY %ext(s32) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %c:_(s1) = G_TRUNC %0 + %t:_(s1) = G_TRUNC %1 + %f:_(s1) = G_TRUNC %2 + %two:_(s8) = G_CONSTANT i8 0 + %one:_(s8) = G_CONSTANT i8 64 + %sel:_(s8) = G_SELECT %c, %two, %one + %ext:_(s32) = G_ANYEXT %sel + $w0 = COPY %ext(s32) +... +--- # select cond, -1, 0 --> sext Cond name: select_cond_minus_1_0_to_sext_cond body: | diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir index e3a633c9e035..4d461c971d33 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir @@ -48,3 +48,73 @@ body: | G_BR %bb.2 ... +--- +name: boolean_vector_to_scalar +tracksRegLiveness: true +body: | + bb.1: + ; CHECK-LABEL: name: boolean_vector_to_scalar + ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s8>) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C]](s64) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C3]](s64) + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C4]](s64) + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C5]](s64) + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]] + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64) + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C6]](s64) + ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C1]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64) + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]] + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 + ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C7]](s64) + ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C1]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]] + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6 + ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C8]](s64) + ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C1]] + ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64) + ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]] + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<8 x s8>), [[C9]](s64) + ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C1]] + ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64) + ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32) + ; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[FRAME_INDEX]](p0) :: (store (s8) into %stack.0) + ; CHECK-NEXT: %bc:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s8) from %stack.0) + ; CHECK-NEXT: %ext:_(s32) = G_ANYEXT %bc(s8) + ; CHECK-NEXT: $w0 = COPY %ext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + %vec:_(<8 x s1>) = G_IMPLICIT_DEF + %bc:_(s8) = G_BITCAST %vec(<8 x s1>) + %ext:_(s32) = G_ANYEXT %bc(s8) + $w0 = COPY %ext(s32) + RET_ReallyLR implicit $w0 +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-1x.ll b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-1x.ll new file mode 100644 index 000000000000..b52957767de4 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-1x.ll @@ -0,0 +1,43 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple aarch64 -O0 -global-isel -o - %s | FileCheck %s + +define <1 x i1> @shuffle_extract_4(<8 x i1> %a, <8 x i1> %b) { +; CHECK-LABEL: shuffle_extract_4: +; CHECK: // %bb.0: +; CHECK-NEXT: ushll v0.8h, v0.8b, #0 +; CHECK-NEXT: umov w8, v0.h[4] +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %extractvec60 = shufflevector <8 x i1> %a, <8 x i1> %b, <1 x i32> <i32 4> + ret <1 x i1> %extractvec60 +} + +define <1 x i1> @shuffle_extract_12(<8 x i1> %a, <8 x i1> %b) { +; CHECK-LABEL: shuffle_extract_12: +; CHECK: // %bb.0: +; CHECK-NEXT: ushll v0.8h, v1.8b, #0 +; CHECK-NEXT: umov w8, v0.h[4] +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %extractvec60 = shufflevector <8 x i1> %a, <8 x i1> %b, <1 x i32> <i32 12> + ret <1 x i1> %extractvec60 +} + +define <1 x i1> @shuffle_extract_p(<8 x i1> %a, <8 x i1> %b) { +; CHECK-LABEL: shuffle_extract_p: +; CHECK: // %bb.0: +; CHECK-NEXT: // implicit-def: $w8 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %extractvec60 = shufflevector <8 x i1> %a, <8 x i1> %b, <1 x i32> <i32 poison> + ret <1 x i1> %extractvec60 +} + +define <1 x i32> @shufflevector_v1i32(<1 x i32> %a, <1 x i32> %b) { +; CHECK-LABEL: shufflevector_v1i32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret + %c = shufflevector <1 x i32> %a, <1 x i32> %b, <1 x i32> <i32 1> + ret <1 x i32> %c +} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir index 2464026aa125..af03a2180698 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir @@ -618,3 +618,32 @@ body: | RET_ReallyLR implicit $q0 ... +--- +name: shuffle_v8i1_v1i8 +alignment: 4 +tracksRegLiveness: true +body: | + bb.1: + liveins: $d0, $d1 + ; CHECK-LABEL: name: shuffle_v8i1_v1i8 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>) + ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[ANYEXT]](<8 x s16>), [[C]](s64) + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s16) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]] + ; CHECK-NEXT: $w0 = COPY [[AND]](s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + %2:_(<8 x s8>) = COPY $d0 + %0:_(<8 x s1>) = G_TRUNC %2:_(<8 x s8>) + %3:_(<8 x s8>) = COPY $d1 + %1:_(<8 x s1>) = G_TRUNC %3:_(<8 x s8>) + %4:_(s1) = G_SHUFFLE_VECTOR %0:_(<8 x s1>), %1:_, shufflemask(12) + %5:_(s8) = G_ZEXT %4:_(s1) + %6:_(s32) = G_ANYEXT %5:_(s8) + $w0 = COPY %6:_(s32) + RET_ReallyLR implicit $w0 +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir new file mode 100644 index 000000000000..1df6297e3638 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-store-vector-bools.mir @@ -0,0 +1,86 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s +--- +name: store_8xs1 +tracksRegLiveness: true +body: | + bb.1: + liveins: $q0, $q1, $x0 + ; CHECK-LABEL: name: store_8xs1 + ; CHECK: liveins: $q0, $q1, $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 + ; CHECK-NEXT: %ptr:_(p0) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY]](<4 x s32>), [[BUILD_VECTOR]] + ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY1]](<4 x s32>), [[BUILD_VECTOR1]] + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>) + ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C1]](s64) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC]](s8) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[EVEC1:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C3]](s64) + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC1]](s8) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[EVEC2:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C4]](s64) + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC2]](s8) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C4]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[EVEC3:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C5]](s64) + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC3]](s8) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]] + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64) + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; CHECK-NEXT: [[EVEC4:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C6]](s64) + ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC4]](s8) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C2]] + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C6]](s64) + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]] + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5 + ; CHECK-NEXT: [[EVEC5:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C7]](s64) + ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC5]](s8) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C2]] + ; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C7]](s64) + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]] + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6 + ; CHECK-NEXT: [[EVEC6:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C8]](s64) + ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC6]](s8) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C2]] + ; CHECK-NEXT: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s64) + ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]] + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[EVEC7:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[TRUNC2]](<8 x s8>), [[C9]](s64) + ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[EVEC7]](s8) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C2]] + ; CHECK-NEXT: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s64) + ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]] + ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR7]](s32) + ; CHECK-NEXT: G_STORE [[TRUNC3]](s8), %ptr(p0) :: (store (s8)) + ; CHECK-NEXT: RET_ReallyLR + %1:_(<4 x s32>) = COPY $q0 + %2:_(<4 x s32>) = COPY $q1 + %ptr:_(p0) = COPY $x0 + %0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>) + %4:_(s32) = G_CONSTANT i32 0 + %3:_(<8 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32), %4(s32) + %5:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s32>), %3 + G_STORE %5(<8 x s1>), %ptr(p0) :: (store (<8 x s1>)) + RET_ReallyLR +... diff --git a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll index ee9fff7ceebc..f0c9dccb21d8 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll @@ -440,11 +440,10 @@ define <8 x i16> @shufsext_v8i8_v8i16(<8 x i8> %src, <8 x i8> %b) { ; ; CHECK-GI-LABEL: shufsext_v8i8_v8i16: ; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI14_0 -; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #0 +; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0 ; CHECK-GI-NEXT: sshll v1.8h, v1.8b, #0 -; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI14_0] -; CHECK-GI-NEXT: tbl v0.16b, { v2.16b, v3.16b }, v0.16b +; CHECK-GI-NEXT: rev64 v0.8h, v0.8h +; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h ; CHECK-GI-NEXT: ret entry: @@ -493,11 +492,10 @@ define <8 x i16> @shufzext_v8i8_v8i16(<8 x i8> %src, <8 x i8> %b) { ; ; CHECK-GI-LABEL: shufzext_v8i8_v8i16: ; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI16_0 -; CHECK-GI-NEXT: ushll v2.8h, v0.8b, #0 +; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0 -; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI16_0] -; CHECK-GI-NEXT: tbl v0.16b, { v2.16b, v3.16b }, v0.16b +; CHECK-GI-NEXT: rev64 v0.8h, v0.8h +; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h ; CHECK-GI-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll index 1aa28f5c2733..9a1203f18243 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll @@ -156,11 +156,10 @@ define i32 @fptosi_bf(bfloat %a) nounwind ssp { ; CHECK-LABEL: fptosi_bf: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: fmov s1, s0 -; CHECK-NEXT: // implicit-def: $s0 +; CHECK-NEXT: // implicit-def: $d0 ; CHECK-NEXT: fmov s0, s1 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret entry: @@ -173,11 +172,10 @@ define i32 @fptoui_sbf(bfloat %a) nounwind ssp { ; CHECK-LABEL: fptoui_sbf: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: fmov s1, s0 -; CHECK-NEXT: // implicit-def: $s0 +; CHECK-NEXT: // implicit-def: $d0 ; CHECK-NEXT: fmov s0, s1 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: fcvtzu w0, s0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll index ed9c1b037d0c..fb40dfcbe101 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll @@ -182,17 +182,14 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fadd s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -202,36 +199,34 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fadd s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2: @@ -281,17 +276,14 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fadd s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -301,36 +293,34 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fadd s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4: diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll index 888b795876f7..818dcf3a0b48 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll @@ -184,17 +184,14 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fmaxnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -204,36 +201,34 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fmaxnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2: @@ -283,17 +278,14 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fmaxnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -303,36 +295,34 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fmaxnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4: @@ -653,31 +643,23 @@ define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; NOLSE-LABEL: test_atomicrmw_fmax_v2bf16_seq_cst_align4: ; NOLSE: // %bb.0: ; NOLSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NOLSE-NEXT: mov h1, v0.h[1] -; NOLSE-NEXT: fmov w10, s0 +; NOLSE-NEXT: dup v1.4h, v0.h[1] ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fmov w9, s1 -; NOLSE-NEXT: fmov s1, w10 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s0, w9 +; NOLSE-NEXT: shll v0.4s, v0.4h, #16 +; NOLSE-NEXT: shll v1.4s, v1.4h, #16 ; NOLSE-NEXT: .LBB7_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxr w9, [x0] ; NOLSE-NEXT: fmov s2, w9 -; NOLSE-NEXT: mov h3, v2.h[1] -; NOLSE-NEXT: fmov w11, s2 -; NOLSE-NEXT: lsl w11, w11, #16 -; NOLSE-NEXT: fmov w10, s3 -; NOLSE-NEXT: fmov s3, w11 -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fmaxnm s3, s3, s1 -; NOLSE-NEXT: fmov s2, w10 +; NOLSE-NEXT: dup v3.4h, v2.h[1] +; NOLSE-NEXT: shll v2.4s, v2.4h, #16 ; NOLSE-NEXT: fmaxnm s2, s2, s0 -; NOLSE-NEXT: fmov w11, s3 +; NOLSE-NEXT: shll v3.4s, v3.4h, #16 +; NOLSE-NEXT: fmaxnm s3, s3, s1 +; NOLSE-NEXT: fmov w11, s2 ; NOLSE-NEXT: ubfx w13, w11, #16, #1 ; NOLSE-NEXT: add w11, w11, w8 -; NOLSE-NEXT: fmov w10, s2 +; NOLSE-NEXT: fmov w10, s3 ; NOLSE-NEXT: add w11, w13, w11 ; NOLSE-NEXT: lsr w11, w11, #16 ; NOLSE-NEXT: ubfx w12, w10, #16, #1 @@ -697,25 +679,17 @@ define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; LSE-LABEL: test_atomicrmw_fmax_v2bf16_seq_cst_align4: ; LSE: // %bb.0: ; LSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; LSE-NEXT: mov h1, v0.h[1] -; LSE-NEXT: fmov w10, s0 +; LSE-NEXT: dup v1.4h, v0.h[1] +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr s0, [x0] -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s1 -; LSE-NEXT: fmov s2, w10 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 +; LSE-NEXT: shll v1.4s, v1.4h, #16 ; LSE-NEXT: .LBB7_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: mov h3, v0.h[1] -; LSE-NEXT: fmov w10, s0 -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s3 -; LSE-NEXT: fmov s4, w10 -; LSE-NEXT: lsl w9, w9, #16 +; LSE-NEXT: dup v3.4h, v0.h[1] +; LSE-NEXT: shll v4.4s, v0.4h, #16 ; LSE-NEXT: fmaxnm s4, s4, s2 -; LSE-NEXT: fmov s3, w9 +; LSE-NEXT: shll v3.4s, v3.4h, #16 ; LSE-NEXT: fmaxnm s3, s3, s1 ; LSE-NEXT: fmov w10, s4 ; LSE-NEXT: ubfx w12, w10, #16, #1 diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll index a3665c6e4286..b969241e8bf9 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll @@ -184,17 +184,14 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fminnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -204,36 +201,34 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fminnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2: @@ -283,17 +278,14 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fminnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -303,36 +295,34 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fminnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4: @@ -653,31 +643,23 @@ define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; NOLSE-LABEL: test_atomicrmw_fmin_v2bf16_seq_cst_align4: ; NOLSE: // %bb.0: ; NOLSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NOLSE-NEXT: mov h1, v0.h[1] -; NOLSE-NEXT: fmov w10, s0 +; NOLSE-NEXT: dup v1.4h, v0.h[1] ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fmov w9, s1 -; NOLSE-NEXT: fmov s1, w10 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s0, w9 +; NOLSE-NEXT: shll v0.4s, v0.4h, #16 +; NOLSE-NEXT: shll v1.4s, v1.4h, #16 ; NOLSE-NEXT: .LBB7_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxr w9, [x0] ; NOLSE-NEXT: fmov s2, w9 -; NOLSE-NEXT: mov h3, v2.h[1] -; NOLSE-NEXT: fmov w11, s2 -; NOLSE-NEXT: lsl w11, w11, #16 -; NOLSE-NEXT: fmov w10, s3 -; NOLSE-NEXT: fmov s3, w11 -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fminnm s3, s3, s1 -; NOLSE-NEXT: fmov s2, w10 +; NOLSE-NEXT: dup v3.4h, v2.h[1] +; NOLSE-NEXT: shll v2.4s, v2.4h, #16 ; NOLSE-NEXT: fminnm s2, s2, s0 -; NOLSE-NEXT: fmov w11, s3 +; NOLSE-NEXT: shll v3.4s, v3.4h, #16 +; NOLSE-NEXT: fminnm s3, s3, s1 +; NOLSE-NEXT: fmov w11, s2 ; NOLSE-NEXT: ubfx w13, w11, #16, #1 ; NOLSE-NEXT: add w11, w11, w8 -; NOLSE-NEXT: fmov w10, s2 +; NOLSE-NEXT: fmov w10, s3 ; NOLSE-NEXT: add w11, w13, w11 ; NOLSE-NEXT: lsr w11, w11, #16 ; NOLSE-NEXT: ubfx w12, w10, #16, #1 @@ -697,25 +679,17 @@ define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; LSE-LABEL: test_atomicrmw_fmin_v2bf16_seq_cst_align4: ; LSE: // %bb.0: ; LSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; LSE-NEXT: mov h1, v0.h[1] -; LSE-NEXT: fmov w10, s0 +; LSE-NEXT: dup v1.4h, v0.h[1] +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr s0, [x0] -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s1 -; LSE-NEXT: fmov s2, w10 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 +; LSE-NEXT: shll v1.4s, v1.4h, #16 ; LSE-NEXT: .LBB7_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: mov h3, v0.h[1] -; LSE-NEXT: fmov w10, s0 -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s3 -; LSE-NEXT: fmov s4, w10 -; LSE-NEXT: lsl w9, w9, #16 +; LSE-NEXT: dup v3.4h, v0.h[1] +; LSE-NEXT: shll v4.4s, v0.4h, #16 ; LSE-NEXT: fminnm s4, s4, s2 -; LSE-NEXT: fmov s3, w9 +; LSE-NEXT: shll v3.4s, v3.4h, #16 ; LSE-NEXT: fminnm s3, s3, s1 ; LSE-NEXT: fmov w10, s4 ; LSE-NEXT: ubfx w12, w10, #16, #1 diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll index 7725ce0e7318..e603337e7a56 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll @@ -182,17 +182,14 @@ define half @test_atomicrmw_fsub_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fsub s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -202,36 +199,34 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fsub s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2: @@ -281,17 +276,14 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fsub s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -301,36 +293,34 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fsub s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4: diff --git a/llvm/test/CodeGen/AArch64/bf16-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-instructions.ll index 33997614598c..bc06453e9c01 100644 --- a/llvm/test/CodeGen/AArch64/bf16-instructions.ll +++ b/llvm/test/CodeGen/AArch64/bf16-instructions.ll @@ -5,16 +5,12 @@ define bfloat @test_fadd(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fadd: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fadd s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -26,15 +22,11 @@ define bfloat @test_fadd(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fadd: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fadd s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fadd bfloat %a, %b @@ -44,16 +36,12 @@ define bfloat @test_fadd(bfloat %a, bfloat %b) #0 { define bfloat @test_fsub(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fsub: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fsub s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fsub s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -65,15 +53,11 @@ define bfloat @test_fsub(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fsub: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fsub s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fsub s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fsub bfloat %a, %b @@ -83,16 +67,12 @@ define bfloat @test_fsub(bfloat %a, bfloat %b) #0 { define bfloat @test_fmul(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fmul: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fmul s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmul s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -104,15 +84,11 @@ define bfloat @test_fmul(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fmul: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmul s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmul s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fmul bfloat %a, %b @@ -122,27 +98,21 @@ define bfloat @test_fmul(bfloat %a, bfloat %b) #0 { define bfloat @test_fmadd(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-CVT-LABEL: test_fmadd: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w10, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmul s0, s1, s0 +; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmul s0, s0, s1 +; CHECK-CVT-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 ; CHECK-CVT-NEXT: add w8, w8, w10 ; CHECK-CVT-NEXT: add w8, w9, w8 -; CHECK-CVT-NEXT: fmov w9, s2 ; CHECK-CVT-NEXT: lsr w8, w8, #16 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 ; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 @@ -155,23 +125,15 @@ define bfloat @test_fmadd(bfloat %a, bfloat %b, bfloat %c) #0 { ; ; CHECK-BF16-LABEL: test_fmadd: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmov w9, s2 -; CHECK-BF16-NEXT: fmul s0, s1, s0 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmul s0, s0, s1 +; CHECK-BF16-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-BF16-NEXT: bfcvt h0, s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -183,16 +145,12 @@ define bfloat @test_fmadd(bfloat %a, bfloat %b, bfloat %c) #0 { define bfloat @test_fdiv(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fdiv: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fdiv s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fdiv s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -204,15 +162,11 @@ define bfloat @test_fdiv(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fdiv: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fdiv s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fdiv s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fdiv bfloat %a, %b @@ -223,14 +177,12 @@ define bfloat @test_frem(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_frem: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-CVT-NEXT: bl fmodf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -246,14 +198,12 @@ define bfloat @test_frem(bfloat %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_frem: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-BF16-NEXT: bl fmodf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -334,17 +284,13 @@ define bfloat @test_select(bfloat %a, bfloat %b, i1 zeroext %c) #0 { define bfloat @test_select_cc(bfloat %a, bfloat %b, bfloat %c, bfloat %d) #0 { ; CHECK-LABEL: test_select_cc: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h3 killed $h3 def $s3 -; CHECK-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: // kill: def $h3 killed $h3 def $d3 +; CHECK-NEXT: // kill: def $h2 killed $h2 def $d2 ; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 ; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: fcmp s2, s3 ; CHECK-NEXT: fcsel s0, s0, s1, ne ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0 ; CHECK-NEXT: ret @@ -356,15 +302,11 @@ define bfloat @test_select_cc(bfloat %a, bfloat %b, bfloat %c, bfloat %d) #0 { define float @test_select_cc_f32_f16(float %a, float %b, bfloat %c, bfloat %d) #0 { ; CHECK-LABEL: test_select_cc_f32_f16: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h3 killed $h3 def $s3 -; CHECK-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s2 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: // kill: def $h3 killed $h3 def $d3 +; CHECK-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: fcmp s2, s3 ; CHECK-NEXT: fcsel s0, s0, s1, ne ; CHECK-NEXT: ret %cc = fcmp une bfloat %c, %d @@ -389,15 +331,11 @@ define bfloat @test_select_cc_f16_f32(bfloat %a, bfloat %b, float %c, float %d) define i1 @test_fcmp_une(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_une: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret %r = fcmp une bfloat %a, %b @@ -407,15 +345,11 @@ define i1 @test_fcmp_une(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ueq(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ueq: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w8, eq ; CHECK-NEXT: csinc w0, w8, wzr, vc ; CHECK-NEXT: ret @@ -426,15 +360,11 @@ define i1 @test_fcmp_ueq(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ugt(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ugt: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: ret %r = fcmp ugt bfloat %a, %b @@ -444,15 +374,11 @@ define i1 @test_fcmp_ugt(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_uge(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_uge: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, pl ; CHECK-NEXT: ret %r = fcmp uge bfloat %a, %b @@ -462,15 +388,11 @@ define i1 @test_fcmp_uge(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ult(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ult: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, lt ; CHECK-NEXT: ret %r = fcmp ult bfloat %a, %b @@ -480,15 +402,11 @@ define i1 @test_fcmp_ult(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ule(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ule: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, le ; CHECK-NEXT: ret %r = fcmp ule bfloat %a, %b @@ -498,15 +416,11 @@ define i1 @test_fcmp_ule(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_uno(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_uno: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, vs ; CHECK-NEXT: ret %r = fcmp uno bfloat %a, %b @@ -516,15 +430,11 @@ define i1 @test_fcmp_uno(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_one(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_one: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w8, mi ; CHECK-NEXT: csinc w0, w8, wzr, le ; CHECK-NEXT: ret @@ -535,15 +445,11 @@ define i1 @test_fcmp_one(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_oeq(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_oeq: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %r = fcmp oeq bfloat %a, %b @@ -553,15 +459,11 @@ define i1 @test_fcmp_oeq(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ogt(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ogt: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret %r = fcmp ogt bfloat %a, %b @@ -571,15 +473,11 @@ define i1 @test_fcmp_ogt(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_oge(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_oge: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, ge ; CHECK-NEXT: ret %r = fcmp oge bfloat %a, %b @@ -589,15 +487,11 @@ define i1 @test_fcmp_oge(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_olt(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_olt: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, mi ; CHECK-NEXT: ret %r = fcmp olt bfloat %a, %b @@ -607,15 +501,11 @@ define i1 @test_fcmp_olt(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ole(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ole: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, ls ; CHECK-NEXT: ret %r = fcmp ole bfloat %a, %b @@ -625,15 +515,11 @@ define i1 @test_fcmp_ole(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ord(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ord: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, vc ; CHECK-NEXT: ret %r = fcmp ord bfloat %a, %b @@ -643,13 +529,11 @@ define i1 @test_fcmp_ord(bfloat %a, bfloat %b) #0 { define void @test_fccmp(bfloat %in, ptr %out) { ; CHECK-LABEL: test_fccmp: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: movi v1.2s, #69, lsl #24 -; CHECK-NEXT: movi v3.2s, #72, lsl #24 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s2, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v2.4s, v0.4h, #16 ; CHECK-NEXT: adrp x8, .LCPI29_0 +; CHECK-NEXT: movi v3.2s, #72, lsl #24 ; CHECK-NEXT: fcmp s2, s1 ; CHECK-NEXT: ldr h1, [x8, :lo12:.LCPI29_0] ; CHECK-NEXT: fccmp s2, s3, #4, mi @@ -667,15 +551,11 @@ define void @test_fccmp(bfloat %in, ptr %out) { define void @test_br_cc(bfloat %a, bfloat %b, ptr %p1, ptr %p2) #0 { ; CHECK-LABEL: test_br_cc: ; CHECK: // %bb.0: // %common.ret -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: csel x8, x0, x1, pl ; CHECK-NEXT: str wzr, [x8] ; CHECK-NEXT: ret @@ -725,10 +605,8 @@ declare i1 @test_dummy(ptr %p1) #0 define i32 @test_fptosi_i32(bfloat %a) #0 { ; CHECK-LABEL: test_fptosi_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret %r = fptosi bfloat %a to i32 @@ -738,10 +616,8 @@ define i32 @test_fptosi_i32(bfloat %a) #0 { define i64 @test_fptosi_i64(bfloat %a) #0 { ; CHECK-LABEL: test_fptosi_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs x0, s0 ; CHECK-NEXT: ret %r = fptosi bfloat %a to i64 @@ -751,10 +627,8 @@ define i64 @test_fptosi_i64(bfloat %a) #0 { define i32 @test_fptoui_i32(bfloat %a) #0 { ; CHECK-LABEL: test_fptoui_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu w0, s0 ; CHECK-NEXT: ret %r = fptoui bfloat %a to i32 @@ -764,10 +638,8 @@ define i32 @test_fptoui_i32(bfloat %a) #0 { define i64 @test_fptoui_i64(bfloat %a) #0 { ; CHECK-LABEL: test_fptoui_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu x0, s0 ; CHECK-NEXT: ret %r = fptoui bfloat %a to i64 @@ -927,7 +799,8 @@ define bfloat @test_uitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: ucvtf d1, w0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fcvtxn s1, d1 ; CHECK-CVT-NEXT: fmov w9, s1 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -935,12 +808,7 @@ define bfloat @test_uitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT-NEXT: add w9, w10, w9 ; CHECK-CVT-NEXT: lsr w9, w9, #16 ; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmov w9, s0 -; CHECK-CVT-NEXT: fmov w10, s1 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s1, w10 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -954,15 +822,11 @@ define bfloat @test_uitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_uitofp_i32_fadd: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: ucvtf d1, w0 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fcvtxn s1, d1 -; CHECK-BF16-NEXT: fmov s0, w8 ; CHECK-BF16-NEXT: bfcvt h1, s1 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -976,7 +840,8 @@ define bfloat @test_sitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: scvtf d1, w0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fcvtxn s1, d1 ; CHECK-CVT-NEXT: fmov w9, s1 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -984,12 +849,7 @@ define bfloat @test_sitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT-NEXT: add w9, w10, w9 ; CHECK-CVT-NEXT: lsr w9, w9, #16 ; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmov w9, s0 -; CHECK-CVT-NEXT: fmov w10, s1 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s1, w10 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -1003,15 +863,11 @@ define bfloat @test_sitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_sitofp_i32_fadd: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: scvtf d1, w0 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fcvtxn s1, d1 -; CHECK-BF16-NEXT: fmov s0, w8 ; CHECK-BF16-NEXT: bfcvt h1, s1 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -1070,10 +926,9 @@ define bfloat @test_fptrunc_double(double %a) #0 { define float @test_fpext_float(bfloat %a) #0 { ; CHECK-LABEL: test_fpext_float: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: ret %r = fpext bfloat %a to float ret float %r @@ -1082,10 +937,8 @@ define float @test_fpext_float(bfloat %a) #0 { define double @test_fpext_double(bfloat %a) #0 { ; CHECK-LABEL: test_fpext_double: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvt d0, s0 ; CHECK-NEXT: ret %r = fpext bfloat %a to double @@ -1148,11 +1001,9 @@ declare bfloat @llvm.fmuladd.f16(bfloat %a, bfloat %b, bfloat %c) #0 define bfloat @test_sqrt(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_sqrt: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fsqrt s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -1165,10 +1016,8 @@ define bfloat @test_sqrt(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_sqrt: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fsqrt s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -1180,10 +1029,9 @@ define bfloat @test_powi(bfloat %a, i32 %b) #0 { ; CHECK-CVT-LABEL: test_powi: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl __powisf2 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1199,10 +1047,9 @@ define bfloat @test_powi(bfloat %a, i32 %b) #0 { ; CHECK-BF16-LABEL: test_powi: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl __powisf2 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1216,10 +1063,9 @@ define bfloat @test_sin(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_sin: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl sinf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1235,10 +1081,9 @@ define bfloat @test_sin(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_sin: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl sinf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1251,10 +1096,9 @@ define bfloat @test_cos(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_cos: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl cosf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1270,10 +1114,9 @@ define bfloat @test_cos(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_cos: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl cosf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1286,10 +1129,9 @@ define bfloat @test_tan(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_tan: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl tanf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1305,10 +1147,9 @@ define bfloat @test_tan(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_tan: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl tanf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1321,10 +1162,9 @@ define bfloat @test_acos(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_acos: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl acosf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1340,10 +1180,9 @@ define bfloat @test_acos(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_acos: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl acosf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1356,10 +1195,9 @@ define bfloat @test_asin(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_asin: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl asinf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1375,10 +1213,9 @@ define bfloat @test_asin(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_asin: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl asinf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1391,10 +1228,9 @@ define bfloat @test_atan(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_atan: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl atanf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1410,10 +1246,9 @@ define bfloat @test_atan(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_atan: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl atanf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1426,14 +1261,12 @@ define bfloat @test_atan2(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_atan2: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-CVT-NEXT: bl atan2f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1449,14 +1282,12 @@ define bfloat @test_atan2(bfloat %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_atan2: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-BF16-NEXT: bl atan2f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1469,10 +1300,9 @@ define bfloat @test_cosh(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_cosh: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl coshf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1488,10 +1318,9 @@ define bfloat @test_cosh(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_cosh: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl coshf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1504,10 +1333,9 @@ define bfloat @test_sinh(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_sinh: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl sinhf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1523,10 +1351,9 @@ define bfloat @test_sinh(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_sinh: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl sinhf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1539,10 +1366,9 @@ define bfloat @test_tanh(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_tanh: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl tanhf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1558,10 +1384,9 @@ define bfloat @test_tanh(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_tanh: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl tanhf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1574,14 +1399,12 @@ define bfloat @test_pow(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_pow: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-CVT-NEXT: bl powf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1597,14 +1420,12 @@ define bfloat @test_pow(bfloat %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_pow: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-BF16-NEXT: bl powf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1617,10 +1438,9 @@ define bfloat @test_exp(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_exp: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl expf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1636,10 +1456,9 @@ define bfloat @test_exp(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_exp: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl expf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1652,10 +1471,9 @@ define bfloat @test_exp2(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_exp2: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl exp2f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1671,10 +1489,9 @@ define bfloat @test_exp2(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_exp2: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl exp2f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1687,10 +1504,9 @@ define bfloat @test_log(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_log: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl logf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1706,10 +1522,9 @@ define bfloat @test_log(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_log: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl logf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1722,10 +1537,9 @@ define bfloat @test_log10(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_log10: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl log10f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1741,10 +1555,9 @@ define bfloat @test_log10(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_log10: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl log10f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1757,10 +1570,9 @@ define bfloat @test_log2(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_log2: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl log2f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1776,10 +1588,9 @@ define bfloat @test_log2(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_log2: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl log2f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1791,20 +1602,14 @@ define bfloat @test_log2(bfloat %a) #0 { define bfloat @test_fma(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-CVT-LABEL: test_fma: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s2 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmov s2, w10 +; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w10, #32767 // =0x7fff -; CHECK-CVT-NEXT: fmadd s0, s2, s1, s0 +; CHECK-CVT-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmadd s0, s0, s1, s2 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 ; CHECK-CVT-NEXT: add w8, w8, w10 @@ -1816,19 +1621,13 @@ define bfloat @test_fma(bfloat %a, bfloat %b, bfloat %c) #0 { ; ; CHECK-BF16-LABEL: test_fma: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s2 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: fmov w10, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: lsl w10, w10, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmov s2, w10 -; CHECK-BF16-NEXT: fmadd s0, s2, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmadd s0, s0, s1, s2 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.fma.f16(bfloat %a, bfloat %b, bfloat %c) @@ -1851,16 +1650,12 @@ define bfloat @test_fabs(bfloat %a) #0 { define bfloat @test_minnum(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_minnum: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fminnm s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fminnm s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -1872,15 +1667,11 @@ define bfloat @test_minnum(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_minnum: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fminnm s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fminnm s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.minnum.f16(bfloat %a, bfloat %b) @@ -1890,16 +1681,12 @@ define bfloat @test_minnum(bfloat %a, bfloat %b) #0 { define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_maxnum: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fmaxnm s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmaxnm s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -1911,15 +1698,11 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_maxnum: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmaxnm s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmaxnm s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.maxnum.f16(bfloat %a, bfloat %b) @@ -1929,16 +1712,12 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 { define bfloat @test_copysign(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_copysign: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 ; CHECK-CVT-NEXT: fmov s0, w8 @@ -1947,16 +1726,12 @@ define bfloat @test_copysign(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_copysign: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.copysign.f16(bfloat %a, bfloat %b) @@ -1966,12 +1741,10 @@ define bfloat @test_copysign(bfloat %a, bfloat %b) #0 { define bfloat @test_copysign_f32(bfloat %a, float %b) #0 { ; CHECK-CVT-LABEL: test_copysign_f32: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 ; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 def $q1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 @@ -1981,12 +1754,10 @@ define bfloat @test_copysign_f32(bfloat %a, float %b) #0 { ; ; CHECK-BF16-LABEL: test_copysign_f32: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 ; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 def $q1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -1998,12 +1769,10 @@ define bfloat @test_copysign_f32(bfloat %a, float %b) #0 { define bfloat @test_copysign_f64(bfloat %a, double %b) #0 { ; CHECK-CVT-LABEL: test_copysign_f64: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: fcvt s1, d1 ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 @@ -2013,12 +1782,10 @@ define bfloat @test_copysign_f64(bfloat %a, double %b) #0 { ; ; CHECK-BF16-LABEL: test_copysign_f64: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-BF16-NEXT: fcvt s1, d1 ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2032,34 +1799,33 @@ define bfloat @test_copysign_f64(bfloat %a, double %b) #0 { define float @test_copysign_extended(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_copysign_extended: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: movi v2.4s, #16 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: ushll v0.4s, v0.4h, #0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 -; CHECK-CVT-NEXT: lsl w8, w8, #16 ; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: ret ; ; CHECK-BF16-LABEL: test_copysign_extended: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: movi v2.4s, #16 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: ushll v0.4s, v0.4h, #0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b +; CHECK-BF16-NEXT: bfcvt h0, s0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.copysign.f16(bfloat %a, bfloat %b) @@ -2070,11 +1836,9 @@ define float @test_copysign_extended(bfloat %a, bfloat %b) #0 { define bfloat @test_floor(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_floor: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintm s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2087,10 +1851,8 @@ define bfloat @test_floor(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_floor: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintm s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2101,11 +1863,9 @@ define bfloat @test_floor(bfloat %a) #0 { define bfloat @test_ceil(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_ceil: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintp s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2118,10 +1878,8 @@ define bfloat @test_ceil(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_ceil: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintp s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2132,11 +1890,9 @@ define bfloat @test_ceil(bfloat %a) #0 { define bfloat @test_trunc(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_trunc: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintz s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2149,10 +1905,8 @@ define bfloat @test_trunc(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_trunc: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintz s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2163,11 +1917,9 @@ define bfloat @test_trunc(bfloat %a) #0 { define bfloat @test_rint(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_rint: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintx s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2180,10 +1932,8 @@ define bfloat @test_rint(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_rint: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintx s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2194,11 +1944,9 @@ define bfloat @test_rint(bfloat %a) #0 { define bfloat @test_nearbyint(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_nearbyint: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frinti s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2211,10 +1959,8 @@ define bfloat @test_nearbyint(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_nearbyint: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frinti s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2225,11 +1971,9 @@ define bfloat @test_nearbyint(bfloat %a) #0 { define bfloat @test_round(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_round: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frinta s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2242,10 +1986,8 @@ define bfloat @test_round(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_round: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frinta s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2256,11 +1998,9 @@ define bfloat @test_round(bfloat %a) #0 { define bfloat @test_roundeven(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_roundeven: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintn s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2273,10 +2013,8 @@ define bfloat @test_roundeven(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_roundeven: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintn s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2287,27 +2025,21 @@ define bfloat @test_roundeven(bfloat %a) #0 { define bfloat @test_fmuladd(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-CVT-LABEL: test_fmuladd: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w10, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmul s0, s1, s0 +; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmul s0, s0, s1 +; CHECK-CVT-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 ; CHECK-CVT-NEXT: add w8, w8, w10 ; CHECK-CVT-NEXT: add w8, w9, w8 -; CHECK-CVT-NEXT: fmov w9, s2 ; CHECK-CVT-NEXT: lsr w8, w8, #16 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 ; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 @@ -2320,23 +2052,15 @@ define bfloat @test_fmuladd(bfloat %a, bfloat %b, bfloat %c) #0 { ; ; CHECK-BF16-LABEL: test_fmuladd: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmov w9, s2 -; CHECK-BF16-NEXT: fmul s0, s1, s0 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmul s0, s0, s1 +; CHECK-BF16-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-BF16-NEXT: bfcvt h0, s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret diff --git a/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll index c03e2e532132..a609e33be935 100644 --- a/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll +++ b/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll @@ -272,9 +272,8 @@ define <8 x bfloat> @d_to_h(<8 x double> %a) { define <8 x float> @h_to_s(<8 x bfloat> %a) { ; CHECK-LABEL: h_to_s: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: ret %1 = fpext <8 x bfloat> %a to <8 x float> ret <8 x float> %1 @@ -283,13 +282,12 @@ define <8 x float> @h_to_s(<8 x bfloat> %a) { define <8 x double> @h_to_d(<8 x bfloat> %a) { ; CHECK-LABEL: h_to_d: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: shll v2.4s, v0.4h, #16 -; CHECK-NEXT: fcvtl v0.2d, v2.2s -; CHECK-NEXT: shll v4.4s, v1.4h, #16 -; CHECK-NEXT: fcvtl2 v1.2d, v2.4s -; CHECK-NEXT: fcvtl2 v3.2d, v4.4s -; CHECK-NEXT: fcvtl v2.2d, v4.2s +; CHECK-NEXT: shll v1.4s, v0.4h, #16 +; CHECK-NEXT: shll2 v2.4s, v0.8h, #16 +; CHECK-NEXT: fcvtl v0.2d, v1.2s +; CHECK-NEXT: fcvtl2 v3.2d, v2.4s +; CHECK-NEXT: fcvtl2 v1.2d, v1.4s +; CHECK-NEXT: fcvtl v2.2d, v2.2s ; CHECK-NEXT: ret %1 = fpext <8 x bfloat> %a to <8 x double> ret <8 x double> %1 @@ -788,11 +786,10 @@ define void @test_insert_at_zero(bfloat %a, ptr %b) #0 { define <8 x i8> @fptosi_i8(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptosi_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzs v1.4s, v1.4s +; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: xtn v0.8b, v0.8h ; CHECK-NEXT: ret @@ -803,11 +800,10 @@ define <8 x i8> @fptosi_i8(<8 x bfloat> %a) #0 { define <8 x i16> @fptosi_i16(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptosi_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzs v1.4s, v1.4s +; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: ret %1 = fptosi<8 x bfloat> %a to <8 x i16> @@ -817,11 +813,10 @@ define <8 x i16> @fptosi_i16(<8 x bfloat> %a) #0 { define <8 x i8> @fptoui_i8(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptoui_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzu v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzu v1.4s, v1.4s +; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: xtn v0.8b, v0.8h ; CHECK-NEXT: ret @@ -832,11 +827,10 @@ define <8 x i8> @fptoui_i8(<8 x bfloat> %a) #0 { define <8 x i16> @fptoui_i16(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptoui_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzu v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzu v1.4s, v1.4s +; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: ret %1 = fptoui<8 x bfloat> %a to <8 x i16> @@ -846,90 +840,58 @@ define <8 x i16> @fptoui_i16(<8 x bfloat> %a) #0 { define <8 x i1> @test_fcmp_une(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_une: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, ne -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, ne -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, ne +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, ne -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, ne ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -941,96 +903,64 @@ define <8 x i1> @test_fcmp_une(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ueq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ueq: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: lsl w9, w11, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s7, w9 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: csetm w10, eq -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csinv w10, w10, wzr, vc -; CHECK-NEXT: fcmp s7, s6 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w11, s4 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h4, v0.h[4] -; CHECK-NEXT: mov h7, v1.h[5] +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 +; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: csinv w8, w8, wzr, vc +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] ; CHECK-NEXT: csetm w9, eq ; CHECK-NEXT: csinv w9, w9, wzr, vc -; CHECK-NEXT: fcmp s3, s2 -; CHECK-NEXT: mov h3, v1.h[4] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 ; CHECK-NEXT: fmov s2, w9 -; CHECK-NEXT: lsl w11, w11, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s5, w11 -; CHECK-NEXT: fmov s6, w8 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, eq -; CHECK-NEXT: mov v2.h[1], w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csinv w8, w8, wzr, vc -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov s6, w10 ; CHECK-NEXT: csetm w8, eq -; CHECK-NEXT: fmov w9, s7 -; CHECK-NEXT: fmov w10, s5 ; CHECK-NEXT: csinv w8, w8, wzr, vc -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: fmov s6, w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csinv w8, w8, wzr, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: lsl w8, w9, #16 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: csetm w10, eq -; CHECK-NEXT: csinv w10, w10, wzr, vc -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csinv w8, w8, wzr, vc -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: csinv w8, w8, wzr, vc +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csinv w8, w8, wzr, vc @@ -1044,90 +974,58 @@ define <8 x i1> @test_fcmp_ueq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ugt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ugt: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, hi -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, hi -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, hi +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, hi -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, hi ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1139,90 +1037,58 @@ define <8 x i1> @test_fcmp_ugt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_uge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_uge: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, pl -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, pl -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, pl +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, pl -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, pl ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1234,90 +1100,58 @@ define <8 x i1> @test_fcmp_uge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ult(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ult: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, lt -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, lt -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, lt +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, lt -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, lt ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1329,90 +1163,58 @@ define <8 x i1> @test_fcmp_ult(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ule(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ule: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, le -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, le -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, le +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, le -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, le ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1424,90 +1226,58 @@ define <8 x i1> @test_fcmp_ule(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_uno(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_uno: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, vs -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, vs -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, vs +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, vs -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, vs ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1519,96 +1289,64 @@ define <8 x i1> @test_fcmp_uno(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_one(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_one: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: lsl w9, w11, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s7, w9 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: csetm w10, mi -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csinv w10, w10, wzr, le -; CHECK-NEXT: fcmp s7, s6 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w11, s4 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h4, v0.h[4] -; CHECK-NEXT: mov h7, v1.h[5] +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 +; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: csinv w8, w8, wzr, le +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] ; CHECK-NEXT: csetm w9, mi ; CHECK-NEXT: csinv w9, w9, wzr, le -; CHECK-NEXT: fcmp s3, s2 -; CHECK-NEXT: mov h3, v1.h[4] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 ; CHECK-NEXT: fmov s2, w9 -; CHECK-NEXT: lsl w11, w11, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s5, w11 -; CHECK-NEXT: fmov s6, w8 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, mi -; CHECK-NEXT: mov v2.h[1], w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csinv w8, w8, wzr, le -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov s6, w10 ; CHECK-NEXT: csetm w8, mi -; CHECK-NEXT: fmov w9, s7 -; CHECK-NEXT: fmov w10, s5 ; CHECK-NEXT: csinv w8, w8, wzr, le -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: fmov s6, w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: csinv w8, w8, wzr, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: lsl w8, w9, #16 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: csetm w10, mi -; CHECK-NEXT: csinv w10, w10, wzr, le -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: csinv w8, w8, wzr, le -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: csinv w8, w8, wzr, le +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: csinv w8, w8, wzr, le @@ -1622,90 +1360,58 @@ define <8 x i1> @test_fcmp_one(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_oeq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_oeq: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, eq -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, eq -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, eq +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, eq -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1717,90 +1423,58 @@ define <8 x i1> @test_fcmp_oeq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ogt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ogt: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, gt -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, gt -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, gt +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, gt -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, gt ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1812,90 +1486,58 @@ define <8 x i1> @test_fcmp_ogt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_oge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_oge: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, ge -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, ge -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, ge +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, ge -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, ge ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1907,90 +1549,58 @@ define <8 x i1> @test_fcmp_oge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_olt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_olt: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, mi -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, mi -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, mi +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, mi -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -2002,90 +1612,58 @@ define <8 x i1> @test_fcmp_olt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ole(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ole: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, ls -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, ls -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, ls +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, ls -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, ls ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -2097,90 +1675,58 @@ define <8 x i1> @test_fcmp_ole(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ord(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ord: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, vc -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, vc -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, vc +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, vc -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, vc ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-cdot.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-cdot.ll new file mode 100644 index 000000000000..11cf4c31936d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-cdot.ll @@ -0,0 +1,1136 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S --passes=complex-deinterleaving %s --mattr=+sve2 -o - | FileCheck %s --check-prefix=CHECK-SVE2 +; RUN: opt -S --passes=complex-deinterleaving %s --mattr=+sve -o - | FileCheck %s --check-prefix=CHECK-SVE +; RUN: opt -S --passes=complex-deinterleaving %s -o - | FileCheck %s --check-prefix=CHECK-NOSVE + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64-none-unknown-elf" + +define i32 @cdotp_i8_rot0(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { +; CHECK-SVE2-LABEL: define i32 @cdotp_i8_rot0( +; CHECK-SVE2-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 8 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 16) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 16) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 4) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP5]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[TMP2]], i32 0) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP6]], <vscale x 16 x i8> [[TMP3]], <vscale x 16 x i8> [[TMP4]], i32 0) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP8]], i64 4) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i32 [[TMP0]] +; +; CHECK-SVE-LABEL: define i32 @cdotp_i8_rot0( +; CHECK-SVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i32 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i32 @cdotp_i8_rot0( +; CHECK-NOSVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i32 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %a) + %b.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %b) + %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 16 x i8> %a.real to <vscale x 16 x i32> + %a.imag.ext = sext <vscale x 16 x i8> %a.imag to <vscale x 16 x i32> + %b.real.ext = sext <vscale x 16 x i8> %b.real to <vscale x 16 x i32> + %b.imag.ext = sext <vscale x 16 x i8> %b.imag to <vscale x 16 x i32> + %real.mul = mul <vscale x 16 x i32> %b.real.ext, %a.real.ext + %real.mul.reduced = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %vec.phi, <vscale x 16 x i32> %real.mul) + %imag.mul = mul <vscale x 16 x i32> %b.imag.ext, %a.imag.ext + %imag.mul.neg = sub <vscale x 16 x i32> zeroinitializer, %imag.mul + %partial.reduce.sub = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %real.mul.reduced, <vscale x 16 x i32> %imag.mul.neg) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %partial.reduce.sub) + ret i32 %0 +} + +define i32 @cdotp_i8_rot90(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { +; CHECK-SVE2-LABEL: define i32 @cdotp_i8_rot90( +; CHECK-SVE2-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 8 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 16) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 16) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 4) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP5]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[TMP2]], i32 90) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP6]], <vscale x 16 x i8> [[TMP3]], <vscale x 16 x i8> [[TMP4]], i32 90) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP8]], i64 4) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i32 [[TMP0]] +; +; CHECK-SVE-LABEL: define i32 @cdotp_i8_rot90( +; CHECK-SVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i32 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i32 @cdotp_i8_rot90( +; CHECK-NOSVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i32 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %a) + %b.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %b) + %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 16 x i8> %a.real to <vscale x 16 x i32> + %a.imag.ext = sext <vscale x 16 x i8> %a.imag to <vscale x 16 x i32> + %b.real.ext = sext <vscale x 16 x i8> %b.real to <vscale x 16 x i32> + %b.imag.ext = sext <vscale x 16 x i8> %b.imag to <vscale x 16 x i32> + %real.mul = mul <vscale x 16 x i32> %b.real.ext, %a.imag.ext + %real.mul.reduced = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %vec.phi, <vscale x 16 x i32> %real.mul) + %imag.mul = mul <vscale x 16 x i32> %b.imag.ext, %a.real.ext + %partial.reduce.sub = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %real.mul.reduced, <vscale x 16 x i32> %imag.mul) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %partial.reduce.sub) + ret i32 %0 +} + +define i32 @cdotp_i8_rot180(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { +; CHECK-SVE2-LABEL: define i32 @cdotp_i8_rot180( +; CHECK-SVE2-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 8 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 16) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 16) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 4) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP5]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[TMP2]], i32 180) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP6]], <vscale x 16 x i8> [[TMP3]], <vscale x 16 x i8> [[TMP4]], i32 180) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP8]], i64 4) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i32 [[TMP0]] +; +; CHECK-SVE-LABEL: define i32 @cdotp_i8_rot180( +; CHECK-SVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i32 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i32 @cdotp_i8_rot180( +; CHECK-NOSVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i32 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %a) + %b.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %b) + %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 16 x i8> %a.real to <vscale x 16 x i32> + %a.imag.ext = sext <vscale x 16 x i8> %a.imag to <vscale x 16 x i32> + %b.real.ext = sext <vscale x 16 x i8> %b.real to <vscale x 16 x i32> + %b.imag.ext = sext <vscale x 16 x i8> %b.imag to <vscale x 16 x i32> + %real.mul = mul <vscale x 16 x i32> %b.real.ext, %a.real.ext + %real.mul.reduced = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %vec.phi, <vscale x 16 x i32> %real.mul) + %imag.mul = mul <vscale x 16 x i32> %b.imag.ext, %a.imag.ext + %partial.reduce.sub = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %real.mul.reduced, <vscale x 16 x i32> %imag.mul) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %partial.reduce.sub) + ret i32 %0 +} + +define i32 @cdotp_i8_rot270(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { +; CHECK-SVE2-LABEL: define i32 @cdotp_i8_rot270( +; CHECK-SVE2-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 8 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[A]], i64 16) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv32i8(<vscale x 32 x i8> [[B]], i64 16) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> [[TMP11]], i64 4) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP5]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[TMP2]], i32 270) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.cdot.nxv4i32(<vscale x 4 x i32> [[TMP6]], <vscale x 16 x i8> [[TMP3]], <vscale x 16 x i8> [[TMP4]], i32 270) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> poison, <vscale x 4 x i32> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP9]], <vscale x 4 x i32> [[TMP8]], i64 4) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i32 [[TMP0]] +; +; CHECK-SVE-LABEL: define i32 @cdotp_i8_rot270( +; CHECK-SVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[REAL_MUL]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL_NEG]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i32 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i32 @cdotp_i8_rot270( +; CHECK-NOSVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[REAL_MUL]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL_NEG]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i32 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %a) + %b.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %b) + %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 16 x i8> %a.real to <vscale x 16 x i32> + %a.imag.ext = sext <vscale x 16 x i8> %a.imag to <vscale x 16 x i32> + %b.real.ext = sext <vscale x 16 x i8> %b.real to <vscale x 16 x i32> + %b.imag.ext = sext <vscale x 16 x i8> %b.imag to <vscale x 16 x i32> + %real.mul = mul <vscale x 16 x i32> %b.real.ext, %a.imag.ext + %real.mul.neg = sub <vscale x 16 x i32> zeroinitializer, %real.mul + %real.mul.reduced = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %vec.phi, <vscale x 16 x i32> %real.mul.neg) + %imag.mul = mul <vscale x 16 x i32> %b.imag.ext, %a.real.ext + %partial.reduce.sub = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %real.mul.reduced, <vscale x 16 x i32> %imag.mul) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %partial.reduce.sub) + ret i32 %0 +} + +define i64 @cdotp_i16_rot0(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) { +; CHECK-SVE2-LABEL: define i64 @cdotp_i16_rot0( +; CHECK-SVE2-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 4 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 8) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 8) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 2) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP5]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[TMP2]], i32 0) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP6]], <vscale x 8 x i16> [[TMP3]], <vscale x 8 x i16> [[TMP4]], i32 0) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP8]], i64 2) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i64 [[TMP0]] +; +; CHECK-SVE-LABEL: define i64 @cdotp_i16_rot0( +; CHECK-SVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 8 x i64> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL_NEG]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i64 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i64 @cdotp_i16_rot0( +; CHECK-NOSVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 8 x i64> zeroinitializer, [[IMAG_MUL]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL_NEG]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i64 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 2 x i64> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %a) + %b.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %b) + %a.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 8 x i16> %a.real to <vscale x 8 x i64> + %a.imag.ext = sext <vscale x 8 x i16> %a.imag to <vscale x 8 x i64> + %b.real.ext = sext <vscale x 8 x i16> %b.real to <vscale x 8 x i64> + %b.imag.ext = sext <vscale x 8 x i16> %b.imag to <vscale x 8 x i64> + %real.mul = mul <vscale x 8 x i64> %b.real.ext, %a.real.ext + %real.mul.reduced = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %vec.phi, <vscale x 8 x i64> %real.mul) + %imag.mul = mul <vscale x 8 x i64> %b.imag.ext, %a.imag.ext + %imag.mul.neg = sub <vscale x 8 x i64> zeroinitializer, %imag.mul + %partial.reduce.sub = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %real.mul.reduced, <vscale x 8 x i64> %imag.mul.neg) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %partial.reduce.sub) + ret i64 %0 +} + +define i64 @cdotp_i16_rot90(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) { +; CHECK-SVE2-LABEL: define i64 @cdotp_i16_rot90( +; CHECK-SVE2-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 4 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 8) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 8) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 2) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP5]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[TMP2]], i32 90) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP6]], <vscale x 8 x i16> [[TMP3]], <vscale x 8 x i16> [[TMP4]], i32 90) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP8]], i64 2) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i64 [[TMP0]] +; +; CHECK-SVE-LABEL: define i64 @cdotp_i16_rot90( +; CHECK-SVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i64 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i64 @cdotp_i16_rot90( +; CHECK-NOSVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i64 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 2 x i64> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %a) + %b.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %b) + %a.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 8 x i16> %a.real to <vscale x 8 x i64> + %a.imag.ext = sext <vscale x 8 x i16> %a.imag to <vscale x 8 x i64> + %b.real.ext = sext <vscale x 8 x i16> %b.real to <vscale x 8 x i64> + %b.imag.ext = sext <vscale x 8 x i16> %b.imag to <vscale x 8 x i64> + %real.mul = mul <vscale x 8 x i64> %b.real.ext, %a.imag.ext + %real.mul.reduced = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %vec.phi, <vscale x 8 x i64> %real.mul) + %imag.mul = mul <vscale x 8 x i64> %b.imag.ext, %a.real.ext + %partial.reduce.sub = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %real.mul.reduced, <vscale x 8 x i64> %imag.mul) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %partial.reduce.sub) + ret i64 %0 +} + +define i64 @cdotp_i16_rot180(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) { +; CHECK-SVE2-LABEL: define i64 @cdotp_i16_rot180( +; CHECK-SVE2-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 4 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 8) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 8) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 2) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP5]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[TMP2]], i32 180) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP6]], <vscale x 8 x i16> [[TMP3]], <vscale x 8 x i16> [[TMP4]], i32 180) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP8]], i64 2) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i64 [[TMP0]] +; +; CHECK-SVE-LABEL: define i64 @cdotp_i16_rot180( +; CHECK-SVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i64 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i64 @cdotp_i16_rot180( +; CHECK-NOSVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i64 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 2 x i64> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %a) + %b.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %b) + %a.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 8 x i16> %a.real to <vscale x 8 x i64> + %a.imag.ext = sext <vscale x 8 x i16> %a.imag to <vscale x 8 x i64> + %b.real.ext = sext <vscale x 8 x i16> %b.real to <vscale x 8 x i64> + %b.imag.ext = sext <vscale x 8 x i16> %b.imag to <vscale x 8 x i64> + %real.mul = mul <vscale x 8 x i64> %b.real.ext, %a.real.ext + %real.mul.reduced = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %vec.phi, <vscale x 8 x i64> %real.mul) + %imag.mul = mul <vscale x 8 x i64> %b.imag.ext, %a.imag.ext + %partial.reduce.sub = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %real.mul.reduced, <vscale x 8 x i64> %imag.mul) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %partial.reduce.sub) + ret i64 %0 +} + +define i64 @cdotp_i16_rot270(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) { +; CHECK-SVE2-LABEL: define i64 @cdotp_i16_rot270( +; CHECK-SVE2-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[TMP11:%.*]] = phi <vscale x 4 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 0) +; CHECK-SVE2-NEXT: [[TMP2:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 0) +; CHECK-SVE2-NEXT: [[TMP3:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[A]], i64 8) +; CHECK-SVE2-NEXT: [[TMP4:%.*]] = call <vscale x 8 x i16> @llvm.vector.extract.nxv8i16.nxv16i16(<vscale x 16 x i16> [[B]], i64 8) +; CHECK-SVE2-NEXT: [[TMP5:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 0) +; CHECK-SVE2-NEXT: [[TMP6:%.*]] = call <vscale x 2 x i64> @llvm.vector.extract.nxv2i64.nxv4i64(<vscale x 4 x i64> [[TMP11]], i64 2) +; CHECK-SVE2-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP5]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[TMP2]], i32 270) +; CHECK-SVE2-NEXT: [[TMP8:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.cdot.nxv2i64(<vscale x 2 x i64> [[TMP6]], <vscale x 8 x i16> [[TMP3]], <vscale x 8 x i16> [[TMP4]], i32 270) +; CHECK-SVE2-NEXT: [[TMP9:%.*]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> poison, <vscale x 2 x i64> [[TMP7]], i64 0) +; CHECK-SVE2-NEXT: [[TMP10]] = call <vscale x 4 x i64> @llvm.vector.insert.nxv4i64.nxv2i64(<vscale x 4 x i64> [[TMP9]], <vscale x 2 x i64> [[TMP8]], i64 2) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> [[TMP10]]) +; CHECK-SVE2-NEXT: ret i64 [[TMP0]] +; +; CHECK-SVE-LABEL: define i64 @cdotp_i16_rot270( +; CHECK-SVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_NEG:%.*]] = sub <vscale x 8 x i64> zeroinitializer, [[REAL_MUL]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL_NEG]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP11:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i64 [[TMP11]] +; +; CHECK-NOSVE-LABEL: define i64 @cdotp_i16_rot270( +; CHECK-NOSVE-SAME: <vscale x 16 x i16> [[A:%.*]], <vscale x 16 x i16> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x i64> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[A_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[A_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 8 x i16> [[B_REAL]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 8 x i16> [[B_IMAG]] to <vscale x 8 x i64> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 8 x i64> [[B_REAL_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_NEG:%.*]] = sub <vscale x 8 x i64> zeroinitializer, [[REAL_MUL]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[VEC_PHI]], <vscale x 8 x i64> [[REAL_MUL_NEG]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 8 x i64> [[B_IMAG_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> [[REAL_MUL_REDUCED]], <vscale x 8 x i64> [[IMAG_MUL]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i64 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 2 x i64> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %a) + %b.deinterleaved = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.vector.deinterleave2.v16i16(<vscale x 16 x i16> %b) + %a.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 8 x i16> %a.real to <vscale x 8 x i64> + %a.imag.ext = sext <vscale x 8 x i16> %a.imag to <vscale x 8 x i64> + %b.real.ext = sext <vscale x 8 x i16> %b.real to <vscale x 8 x i64> + %b.imag.ext = sext <vscale x 8 x i16> %b.imag to <vscale x 8 x i64> + %real.mul = mul <vscale x 8 x i64> %b.real.ext, %a.imag.ext + %real.mul.neg = sub <vscale x 8 x i64> zeroinitializer, %real.mul + %real.mul.reduced = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %vec.phi, <vscale x 8 x i64> %real.mul.neg) + %imag.mul = mul <vscale x 8 x i64> %b.imag.ext, %a.real.ext + %partial.reduce.sub = call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %real.mul.reduced, <vscale x 8 x i64> %imag.mul) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %partial.reduce.sub) + ret i64 %0 +} + + +define i32 @not_cdotp(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { +; CHECK-SVE2-LABEL: define i32 @not_cdotp( +; CHECK-SVE2-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE2-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE2-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE2-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE2-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE2-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE2-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE2-NEXT: [[REAL_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[REAL_MUL]] +; CHECK-SVE2-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL_NEG]]) +; CHECK-SVE2-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE2-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE2-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE2-NEXT: ret i32 [[TMP0]] +; +; CHECK-SVE-LABEL: define i32 @not_cdotp( +; CHECK-SVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[REAL_MUL]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL_NEG]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i32 [[TMP0]] +; +; CHECK-NOSVE-LABEL: define i32 @not_cdotp( +; CHECK-NOSVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[REAL_MUL]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL_NEG]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i32 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %a) + %b.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %b) + %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 16 x i8> %a.real to <vscale x 16 x i32> + %a.imag.ext = sext <vscale x 16 x i8> %a.imag to <vscale x 16 x i32> + %b.real.ext = sext <vscale x 16 x i8> %b.real to <vscale x 16 x i32> + %b.imag.ext = sext <vscale x 16 x i8> %b.imag to <vscale x 16 x i32> + %real.mul = mul <vscale x 16 x i32> %b.real.ext, %a.real.ext + %real.mul.neg = sub <vscale x 16 x i32> zeroinitializer, %real.mul + %real.mul.reduced = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %vec.phi, <vscale x 16 x i32> %real.mul.neg) + %imag.mul = mul <vscale x 16 x i32> %b.imag.ext, %a.imag.ext + %imag.mul.neg = sub <vscale x 16 x i32> zeroinitializer, %imag.mul + %partial.reduce.sub = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %real.mul.reduced, <vscale x 16 x i32> %imag.mul.neg) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %partial.reduce.sub) + ret i32 %0 +} + +define i16 @invalid_type(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { +; CHECK-SVE2-LABEL: define i16 @invalid_type( +; CHECK-SVE2-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x i16> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE2-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE2-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE2-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE2-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE2-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE2-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE2-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE2-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-SVE2-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE2-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE2-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.add.nxv8i16(<vscale x 8 x i16> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE2-NEXT: ret i16 [[TMP0]] +; +; CHECK-SVE-LABEL: define i16 @invalid_type( +; CHECK-SVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x i16> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.add.nxv8i16(<vscale x 8 x i16> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i16 [[TMP0]] +; +; CHECK-NOSVE-LABEL: define i16 @invalid_type( +; CHECK-NOSVE-SAME: <vscale x 32 x i8> [[A:%.*]], <vscale x 32 x i8> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x i16> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[A_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[A_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <vscale x 16 x i8> [[B_REAL]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <vscale x 16 x i8> [[B_IMAG]] to <vscale x 16 x i32> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <vscale x 16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> [[VEC_PHI]], <vscale x 16 x i32> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <vscale x 16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <vscale x 16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> [[REAL_MUL_REDUCED]], <vscale x 16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i16 @llvm.vector.reduce.add.nxv8i16(<vscale x 8 x i16> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i16 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <vscale x 8 x i16> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %a) + %b.deinterleaved = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.vector.deinterleave2.v32i8(<vscale x 32 x i8> %b) + %a.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 0 + %a.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %a.deinterleaved, 1 + %b.real = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 0 + %b.imag = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %b.deinterleaved, 1 + %a.real.ext = sext <vscale x 16 x i8> %a.real to <vscale x 16 x i32> + %a.imag.ext = sext <vscale x 16 x i8> %a.imag to <vscale x 16 x i32> + %b.real.ext = sext <vscale x 16 x i8> %b.real to <vscale x 16 x i32> + %b.imag.ext = sext <vscale x 16 x i8> %b.imag to <vscale x 16 x i32> + %real.mul = mul <vscale x 16 x i32> %b.real.ext, %a.real.ext + %real.mul.reduced = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> %vec.phi, <vscale x 16 x i32> %real.mul) + %imag.mul = mul <vscale x 16 x i32> %b.imag.ext, %a.imag.ext + %imag.mul.neg = sub <vscale x 16 x i32> zeroinitializer, %imag.mul + %partial.reduce.sub = call <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16> %real.mul.reduced, <vscale x 16 x i32> %imag.mul.neg) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i16 @llvm.vector.reduce.add.nxv8i16(<vscale x 8 x i16> %partial.reduce.sub) + ret i16 %0 +} + +define i32 @not_cdotp_i8_rot0_fixed_length(<32 x i8> %a, <32 x i8> %b) { +; CHECK-SVE2-LABEL: define i32 @not_cdotp_i8_rot0_fixed_length( +; CHECK-SVE2-SAME: <32 x i8> [[A:%.*]], <32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE2-NEXT: [[ENTRY:.*]]: +; CHECK-SVE2-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE2: [[VECTOR_BODY]]: +; CHECK-SVE2-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE2-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> [[A]]) +; CHECK-SVE2-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> [[B]]) +; CHECK-SVE2-NEXT: [[A_REAL:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE2-NEXT: [[A_IMAG:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE2-NEXT: [[B_REAL:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE2-NEXT: [[B_IMAG:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE2-NEXT: [[A_REAL_EXT:%.*]] = sext <16 x i8> [[A_REAL]] to <16 x i32> +; CHECK-SVE2-NEXT: [[A_IMAG_EXT:%.*]] = sext <16 x i8> [[A_IMAG]] to <16 x i32> +; CHECK-SVE2-NEXT: [[B_REAL_EXT:%.*]] = sext <16 x i8> [[B_REAL]] to <16 x i32> +; CHECK-SVE2-NEXT: [[B_IMAG_EXT:%.*]] = sext <16 x i8> [[B_IMAG]] to <16 x i32> +; CHECK-SVE2-NEXT: [[REAL_MUL:%.*]] = mul <16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE2-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI]], <16 x i32> [[REAL_MUL]]) +; CHECK-SVE2-NEXT: [[IMAG_MUL:%.*]] = mul <16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE2-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE2-NEXT: [[PARTIAL_REDUCE_SUB]] = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[REAL_MUL_REDUCED]], <16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-SVE2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE2: [[MIDDLE_BLOCK]]: +; CHECK-SVE2-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE2-NEXT: ret i32 [[TMP0]] +; +; CHECK-SVE-LABEL: define i32 @not_cdotp_i8_rot0_fixed_length( +; CHECK-SVE-SAME: <32 x i8> [[A:%.*]], <32 x i8> [[B:%.*]]) #[[ATTR0]] { +; CHECK-SVE-NEXT: [[ENTRY:.*]]: +; CHECK-SVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-SVE: [[VECTOR_BODY]]: +; CHECK-SVE-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-SVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> [[A]]) +; CHECK-SVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> [[B]]) +; CHECK-SVE-NEXT: [[A_REAL:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[B_REAL:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-SVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-SVE-NEXT: [[A_REAL_EXT:%.*]] = sext <16 x i8> [[A_REAL]] to <16 x i32> +; CHECK-SVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <16 x i8> [[A_IMAG]] to <16 x i32> +; CHECK-SVE-NEXT: [[B_REAL_EXT:%.*]] = sext <16 x i8> [[B_REAL]] to <16 x i32> +; CHECK-SVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <16 x i8> [[B_IMAG]] to <16 x i32> +; CHECK-SVE-NEXT: [[REAL_MUL:%.*]] = mul <16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-SVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI]], <16 x i32> [[REAL_MUL]]) +; CHECK-SVE-NEXT: [[IMAG_MUL:%.*]] = mul <16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-SVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-SVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[REAL_MUL_REDUCED]], <16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-SVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-SVE: [[MIDDLE_BLOCK]]: +; CHECK-SVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-SVE-NEXT: ret i32 [[TMP0]] +; +; CHECK-NOSVE-LABEL: define i32 @not_cdotp_i8_rot0_fixed_length( +; CHECK-NOSVE-SAME: <32 x i8> [[A:%.*]], <32 x i8> [[B:%.*]]) { +; CHECK-NOSVE-NEXT: [[ENTRY:.*]]: +; CHECK-NOSVE-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK-NOSVE: [[VECTOR_BODY]]: +; CHECK-NOSVE-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[ENTRY]] ], [ [[PARTIAL_REDUCE_SUB:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NOSVE-NEXT: [[A_DEINTERLEAVED:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> [[A]]) +; CHECK-NOSVE-NEXT: [[B_DEINTERLEAVED:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> [[B]]) +; CHECK-NOSVE-NEXT: [[A_REAL:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[A_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[A_IMAG:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[A_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[B_REAL:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[B_DEINTERLEAVED]], 0 +; CHECK-NOSVE-NEXT: [[B_IMAG:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[B_DEINTERLEAVED]], 1 +; CHECK-NOSVE-NEXT: [[A_REAL_EXT:%.*]] = sext <16 x i8> [[A_REAL]] to <16 x i32> +; CHECK-NOSVE-NEXT: [[A_IMAG_EXT:%.*]] = sext <16 x i8> [[A_IMAG]] to <16 x i32> +; CHECK-NOSVE-NEXT: [[B_REAL_EXT:%.*]] = sext <16 x i8> [[B_REAL]] to <16 x i32> +; CHECK-NOSVE-NEXT: [[B_IMAG_EXT:%.*]] = sext <16 x i8> [[B_IMAG]] to <16 x i32> +; CHECK-NOSVE-NEXT: [[REAL_MUL:%.*]] = mul <16 x i32> [[B_REAL_EXT]], [[A_REAL_EXT]] +; CHECK-NOSVE-NEXT: [[REAL_MUL_REDUCED:%.*]] = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[VEC_PHI]], <16 x i32> [[REAL_MUL]]) +; CHECK-NOSVE-NEXT: [[IMAG_MUL:%.*]] = mul <16 x i32> [[B_IMAG_EXT]], [[A_IMAG_EXT]] +; CHECK-NOSVE-NEXT: [[IMAG_MUL_NEG:%.*]] = sub <16 x i32> zeroinitializer, [[IMAG_MUL]] +; CHECK-NOSVE-NEXT: [[PARTIAL_REDUCE_SUB]] = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> [[REAL_MUL_REDUCED]], <16 x i32> [[IMAG_MUL_NEG]]) +; CHECK-NOSVE-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]] +; CHECK-NOSVE: [[MIDDLE_BLOCK]]: +; CHECK-NOSVE-NEXT: [[TMP0:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[PARTIAL_REDUCE_SUB]]) +; CHECK-NOSVE-NEXT: ret i32 [[TMP0]] +; +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %partial.reduce.sub, %vector.body ] + %a.deinterleaved = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %a) + %b.deinterleaved = call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %b) + %a.real = extractvalue { <16 x i8>, <16 x i8> } %a.deinterleaved, 0 + %a.imag = extractvalue { <16 x i8>, <16 x i8> } %a.deinterleaved, 1 + %b.real = extractvalue { <16 x i8>, <16 x i8> } %b.deinterleaved, 0 + %b.imag = extractvalue { <16 x i8>, <16 x i8> } %b.deinterleaved, 1 + %a.real.ext = sext <16 x i8> %a.real to <16 x i32> + %a.imag.ext = sext <16 x i8> %a.imag to <16 x i32> + %b.real.ext = sext <16 x i8> %b.real to <16 x i32> + %b.imag.ext = sext <16 x i8> %b.imag to <16 x i32> + %real.mul = mul <16 x i32> %b.real.ext, %a.real.ext + %real.mul.reduced = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %vec.phi, <16 x i32> %real.mul) + %imag.mul = mul <16 x i32> %b.imag.ext, %a.imag.ext + %imag.mul.neg = sub <16 x i32> zeroinitializer, %imag.mul + %partial.reduce.sub = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %real.mul.reduced, <16 x i32> %imag.mul.neg) + br i1 true, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %0 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %partial.reduce.sub) + ret i32 %0 +} + +declare <vscale x 8 x i16> @llvm.experimental.vector.partial.reduce.add.nxv8i16.nxv16i32(<vscale x 8 x i16>, <vscale x 16 x i32>) +declare <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32>, <vscale x 16 x i32>) +declare <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i32(<vscale x 2 x i64>, <vscale x 16 x i32>) + +declare <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32>, <16 x i32>) +declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) + +declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>) +declare i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64>) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll index 68cb29f8f5c8..7542e9c4b8f5 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-crash.ll @@ -29,3 +29,92 @@ bb193: ; preds = %bb173 store volatile i32 0, ptr null, align 4 unreachable } + +; Check that the deinterleaving pass doesn't try to transform isolated patterns without a relevant deinterleaving pattern +define i32 @check_deinterleaving_has_deinterleave(ptr %a) { +; CHECK-LABEL: check_deinterleaving_has_deinterleave: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: movi v1.4s, #1 +; CHECK-NEXT: add x8, x0, #16 +; CHECK-NEXT: movi v3.2d, #0000000000000000 +; CHECK-NEXT: movi v2.2d, #0000000000000000 +; CHECK-NEXT: mov w9, #32 // =0x20 +; CHECK-NEXT: movi v4.2d, #0000000000000000 +; CHECK-NEXT: movi v5.2d, #0000000000000000 +; CHECK-NEXT: movi v7.2d, #0000000000000000 +; CHECK-NEXT: movi v6.2d, #0000000000000000 +; CHECK-NEXT: movi v16.2d, #0000000000000000 +; CHECK-NEXT: .LBB1_1: // %vector.body +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ldp q17, q18, [x8, #-16] +; CHECK-NEXT: subs x9, x9, #32 +; CHECK-NEXT: add x8, x8, #32 +; CHECK-NEXT: cmeq v17.16b, v17.16b, #0 +; CHECK-NEXT: cmeq v18.16b, v18.16b, #0 +; CHECK-NEXT: ushll2 v19.8h, v17.16b, #0 +; CHECK-NEXT: ushll v17.8h, v17.8b, #0 +; CHECK-NEXT: ushll2 v20.8h, v18.16b, #0 +; CHECK-NEXT: ushll v18.8h, v18.8b, #0 +; CHECK-NEXT: ushll v21.4s, v19.4h, #0 +; CHECK-NEXT: ushll2 v19.4s, v19.8h, #0 +; CHECK-NEXT: ushll v22.4s, v17.4h, #0 +; CHECK-NEXT: ushll2 v17.4s, v17.8h, #0 +; CHECK-NEXT: ushll2 v23.4s, v20.8h, #0 +; CHECK-NEXT: ushll v24.4s, v18.4h, #0 +; CHECK-NEXT: ushll2 v18.4s, v18.8h, #0 +; CHECK-NEXT: ushll v20.4s, v20.4h, #0 +; CHECK-NEXT: and v21.16b, v21.16b, v1.16b +; CHECK-NEXT: and v19.16b, v19.16b, v1.16b +; CHECK-NEXT: and v22.16b, v22.16b, v1.16b +; CHECK-NEXT: and v17.16b, v17.16b, v1.16b +; CHECK-NEXT: and v23.16b, v23.16b, v1.16b +; CHECK-NEXT: and v24.16b, v24.16b, v1.16b +; CHECK-NEXT: and v18.16b, v18.16b, v1.16b +; CHECK-NEXT: and v20.16b, v20.16b, v1.16b +; CHECK-NEXT: add v4.4s, v4.4s, v19.4s +; CHECK-NEXT: add v2.4s, v2.4s, v21.4s +; CHECK-NEXT: add v0.4s, v0.4s, v22.4s +; CHECK-NEXT: add v3.4s, v3.4s, v17.4s +; CHECK-NEXT: add v16.4s, v16.4s, v23.4s +; CHECK-NEXT: add v5.4s, v5.4s, v24.4s +; CHECK-NEXT: add v6.4s, v6.4s, v20.4s +; CHECK-NEXT: add v7.4s, v7.4s, v18.4s +; CHECK-NEXT: b.ne .LBB1_1 +; CHECK-NEXT: // %bb.2: // %middle.block +; CHECK-NEXT: add v1.4s, v7.4s, v3.4s +; CHECK-NEXT: add v3.4s, v16.4s, v4.4s +; CHECK-NEXT: add v0.4s, v5.4s, v0.4s +; CHECK-NEXT: add v2.4s, v6.4s, v2.4s +; CHECK-NEXT: add v1.4s, v1.4s, v3.4s +; CHECK-NEXT: add v0.4s, v0.4s, v2.4s +; CHECK-NEXT: add v0.4s, v0.4s, v1.4s +; CHECK-NEXT: addv s0, v0.4s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %vec.phi = phi <16 x i32> [ zeroinitializer, %entry ], [ %9, %vector.body ] + %vec.phi50 = phi <16 x i32> [ zeroinitializer, %entry ], [ %10, %vector.body ] + %next.gep = getelementptr i8, ptr %a, i64 %index + %4 = getelementptr i8, ptr %next.gep, i64 16 + %wide.load = load <16 x i8>, ptr %next.gep, align 1 + %wide.load51 = load <16 x i8>, ptr %4, align 1 + %5 = icmp eq <16 x i8> %wide.load, zeroinitializer + %6 = icmp eq <16 x i8> %wide.load51, zeroinitializer + %7 = zext <16 x i1> %5 to <16 x i32> + %8 = zext <16 x i1> %6 to <16 x i32> + %9 = add <16 x i32> %vec.phi, %7 + %10 = add <16 x i32> %vec.phi50, %8 + %index.next = add nuw i64 %index, 32 + %11 = icmp eq i64 %index.next, 32 + br i1 %11, label %middle.block, label %vector.body + +middle.block: + %bin.rdx = add <16 x i32> %10, %9 + %12 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %bin.rdx) + ret i32 %12 +} diff --git a/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll b/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll new file mode 100644 index 000000000000..7c628cf1683d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/csel-subs-swapped.ll @@ -0,0 +1,322 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s + +define i32 @eq_i32(i32 %x) { +; CHECK-LABEL: eq_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: csel w0, w0, w8, eq +; CHECK-NEXT: ret + %cmp = icmp eq i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @ne_i32(i32 %x) { +; CHECK-LABEL: ne_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: csel w0, w0, w8, ne +; CHECK-NEXT: ret + %cmp = icmp ne i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @sgt_i32(i32 %x) { +; CHECK-LABEL: sgt_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: csel w0, w0, w8, gt +; CHECK-NEXT: ret + %cmp = icmp sgt i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @sge_i32(i32 %x) { +; CHECK-LABEL: sge_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: mov w9, #-2097153 // =0xffdfffff +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: cmp w0, w9 +; CHECK-NEXT: csel w0, w0, w8, gt +; CHECK-NEXT: ret + %cmp = icmp sge i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @slt_i32(i32 %x) { +; CHECK-LABEL: slt_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: csel w0, w0, w8, lt +; CHECK-NEXT: ret + %cmp = icmp slt i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @sle_i32(i32 %x) { +; CHECK-LABEL: sle_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: cmp w0, w9 +; CHECK-NEXT: csel w0, w0, w8, lt +; CHECK-NEXT: ret + %cmp = icmp sle i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @ugt_i32(i32 %x) { +; CHECK-LABEL: ugt_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: csel w0, w0, w8, hi +; CHECK-NEXT: ret + %cmp = icmp ugt i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @uge_i32(i32 %x) { +; CHECK-LABEL: uge_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: lsr w9, w0, #21 +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: cmp w9, #2046 +; CHECK-NEXT: csel w0, w0, w8, hi +; CHECK-NEXT: ret + %cmp = icmp uge i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @ult_i32(i32 %x) { +; CHECK-LABEL: ult_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: csel w0, w0, w8, lo +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + +define i32 @ule_i32(i32 %x) { +; CHECK-LABEL: ule_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000 +; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001 +; CHECK-NEXT: sub w8, w8, w0 +; CHECK-NEXT: cmp w0, w9 +; CHECK-NEXT: csel w0, w0, w8, lo +; CHECK-NEXT: ret + %cmp = icmp ule i32 %x, -2097152 + %sub = sub i32 -2097152, %x + %retval.0 = select i1 %cmp, i32 %x, i32 %sub + ret i32 %retval.0 +} + + +define i64 @eq_i64(i64 %x) { +; CHECK-LABEL: eq_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #100 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, eq +; CHECK-NEXT: ret + %cmp = icmp eq i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @ne_i64(i64 %x) { +; CHECK-LABEL: ne_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #100 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, ne +; CHECK-NEXT: ret + %cmp = icmp ne i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @sgt_i64(i64 %x) { +; CHECK-LABEL: sgt_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #100 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, gt +; CHECK-NEXT: ret + %cmp = icmp sgt i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @sge_i64(i64 %x) { +; CHECK-LABEL: sge_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #99 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, gt +; CHECK-NEXT: ret + %cmp = icmp sge i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @slt_i64(i64 %x) { +; CHECK-LABEL: slt_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #100 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, lt +; CHECK-NEXT: ret + %cmp = icmp slt i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @sle_i64(i64 %x) { +; CHECK-LABEL: sle_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #101 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, lt +; CHECK-NEXT: ret + %cmp = icmp sle i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @ugt_i64(i64 %x) { +; CHECK-LABEL: ugt_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #100 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, hi +; CHECK-NEXT: ret + %cmp = icmp ugt i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @uge_i64(i64 %x) { +; CHECK-LABEL: uge_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #99 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, hi +; CHECK-NEXT: ret + %cmp = icmp uge i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @ult_i64(i64 %x) { +; CHECK-LABEL: ult_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #100 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, lo +; CHECK-NEXT: ret + %cmp = icmp ult i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + +define i64 @ule_i64(i64 %x) { +; CHECK-LABEL: ule_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: cmp x0, #101 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x0, x8, lo +; CHECK-NEXT: ret + %cmp = icmp ule i64 %x, 100 + %sub = sub i64 100, %x + %retval.0 = select i1 %cmp, i64 %x, i64 %sub + ret i64 %retval.0 +} + + +define i64 @both(i64 %x) { +; CHECK-LABEL: both: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #100 // =0x64 +; CHECK-NEXT: sub x9, x0, #100 +; CHECK-NEXT: cmp x0, #101 +; CHECK-NEXT: sub x8, x8, x0 +; CHECK-NEXT: csel x0, x8, x9, lo +; CHECK-NEXT: ret + %cmp = icmp ule i64 %x, 100 + %sub1 = sub i64 100, %x + %sub2 = sub i64 %x, 100 + %retval.0 = select i1 %cmp, i64 %sub1, i64 %sub2 + ret i64 %retval.0 +} + +define i32 @qabs(i32 %0) { +; CHECK-LABEL: qabs: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000 +; CHECK-NEXT: cmp w0, w8 +; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff +; CHECK-NEXT: csneg w8, w8, w0, eq +; CHECK-NEXT: cmp w0, #0 +; CHECK-NEXT: csel w0, w0, w8, gt +; CHECK-NEXT: ret + %cmp1 = icmp sgt i32 %0, 0 + %cmp2 = icmp eq i32 %0, -2147483648 + %sub = sub nsw i32 0, %0 + %cond = select i1 %cmp2, i32 2147483647, i32 %sub + %cond6 = select i1 %cmp1, i32 %0, i32 %cond + ret i32 %cond6 +} diff --git a/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll b/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll index 40684b0f3a25..e3263252875f 100644 --- a/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll +++ b/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll @@ -76,11 +76,9 @@ entry: define bfloat @t7(bfloat %x) { ; CHECK-LABEL: t7: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w9, s0 ; CHECK-NEXT: scvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 @@ -101,11 +99,9 @@ entry: define bfloat @t8(bfloat %x) { ; CHECK-LABEL: t8: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu w9, s0 ; CHECK-NEXT: ucvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 @@ -198,11 +194,9 @@ entry: define bfloat @t7_strict(bfloat %x) #0 { ; CHECK-LABEL: t7_strict: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w9, s0 ; CHECK-NEXT: scvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 @@ -223,11 +217,9 @@ entry: define bfloat @t8_strict(bfloat %x) #0 { ; CHECK-LABEL: t8_strict: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu w9, s0 ; CHECK-NEXT: ucvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 diff --git a/llvm/test/CodeGen/AArch64/hwasan-zero-ptr.ll b/llvm/test/CodeGen/AArch64/hwasan-zero-ptr.ll new file mode 100644 index 000000000000..dca39fe03fb1 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/hwasan-zero-ptr.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -filetype asm -o - %s | FileCheck %s + +; This shows that when dereferencing a null pointer, HWASan will call +; __hwasan_check_x4294967071_19_fixed_0_short_v2 +; (N.B. 4294967071 == 2**32 - 239 + 14 == 2**32 - X0 + XZR +; +; The source was generated from llvm/test/Instrumentation/HWAddressSanitizer/zero-ptr.ll. + +; ModuleID = '<stdin>' +source_filename = "<stdin>" +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android10000" + +$hwasan.module_ctor = comdat any + +@__start_hwasan_globals = external hidden constant [0 x i8] +@__stop_hwasan_globals = external hidden constant [0 x i8] +@hwasan.note = private constant { i32, i32, i32, [8 x i8], i32, i32 } { i32 8, i32 8, i32 3, [8 x i8] c"LLVM\00\00\00\00", i32 trunc (i64 sub (i64 ptrtoint (ptr @__start_hwasan_globals to i64), i64 ptrtoint (ptr @hwasan.note to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint (ptr @__stop_hwasan_globals to i64), i64 ptrtoint (ptr @hwasan.note to i64)) to i32) }, section ".note.hwasan.globals", comdat($hwasan.module_ctor), align 4 + +; Function Attrs: sanitize_hwaddress +define void @test_store_to_zeroptr() #0 { +; CHECK-LABEL: test_store_to_zeroptr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -16 +; CHECK-NEXT: bl __hwasan_check_x4294967071_19_fixed_0_short_v2 +; CHECK-NEXT: mov x8, xzr +; CHECK-NEXT: mov w9, #42 // =0x2a +; CHECK-NEXT: str x9, [x8] +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +entry: + %.hwasan.shadow = call ptr asm "", "=r,0"(ptr null) + %b = inttoptr i64 0 to ptr + call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr %b, i32 19, i64 0) + store i64 42, ptr %b, align 8 + ret void +} + +; Function Attrs: nounwind +declare void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr, i32 immarg, i64 immarg) #1 + +attributes #0 = { sanitize_hwaddress } +attributes #1 = { nounwind } + +declare void @__hwasan_init() + +; Function Attrs: nounwind +define internal void @hwasan.module_ctor() #1 comdat { +; CHECK-LABEL: hwasan.module_ctor: +; CHECK: // %bb.0: +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: bl __hwasan_init +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret + call void @__hwasan_init() + ret void +} + +!llvm.module.flags = !{!1} + +!0 = !{ptr @hwasan.note} +!1 = !{i32 4, !"nosanitize_hwaddress", i32 1} diff --git a/llvm/test/CodeGen/AArch64/machine-combiner.ll b/llvm/test/CodeGen/AArch64/machine-combiner.ll index 70a638857ce4..c8df283aace0 100644 --- a/llvm/test/CodeGen/AArch64/machine-combiner.ll +++ b/llvm/test/CodeGen/AArch64/machine-combiner.ll @@ -262,8 +262,8 @@ define half @reassociate_adds_half(half %x0, half %x1, half %x2, half %x3) { ; CHECK-UNSAFE-LABEL: reassociate_adds_half: ; CHECK-UNSAFE: // %bb.0: ; CHECK-UNSAFE-NEXT: fdiv h0, h0, h1 -; CHECK-UNSAFE-NEXT: fadd h1, h3, h2 -; CHECK-UNSAFE-NEXT: fadd h0, h1, h0 +; CHECK-UNSAFE-NEXT: fadd h2, h3, h2 +; CHECK-UNSAFE-NEXT: fadd h0, h2, h0 ; CHECK-UNSAFE-NEXT: ret %t0 = fdiv half %x0, %x1 %t1 = fadd half %x2, %t0 @@ -284,8 +284,8 @@ define half @reassociate_muls_half(half %x0, half %x1, half %x2, half %x3) { ; CHECK-UNSAFE-LABEL: reassociate_muls_half: ; CHECK-UNSAFE: // %bb.0: ; CHECK-UNSAFE-NEXT: fdiv h0, h0, h1 -; CHECK-UNSAFE-NEXT: fmul h1, h3, h2 -; CHECK-UNSAFE-NEXT: fmul h0, h1, h0 +; CHECK-UNSAFE-NEXT: fmul h2, h3, h2 +; CHECK-UNSAFE-NEXT: fmul h0, h2, h0 ; CHECK-UNSAFE-NEXT: ret %t0 = fdiv half %x0, %x1 %t1 = fmul half %x2, %t0 diff --git a/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll b/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll index 17f826356043..a32c53a5a574 100644 --- a/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll +++ b/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll @@ -313,9 +313,8 @@ define void @one_dimensional_with_store(ptr %a, ptr %b, ptr %c, i32 %N) { ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp w9, w10 ; CHECK-NEXT: cset w9, hi -; CHECK-NEXT: cset w10, lo +; CHECK-NEXT: csinv w9, w9, wzr, hs ; CHECK-NEXT: subs x8, x8, #1 -; CHECK-NEXT: sub w9, w9, w10 ; CHECK-NEXT: strb w9, [x2], #1 ; CHECK-NEXT: b.ne .LBB4_1 ; CHECK-NEXT: // %bb.2: // %for.exit diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll index 4bbbe4017631..e7de54036245 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll @@ -9,9 +9,9 @@ define void @a() "sign-return-address"="all" "sign-return-address-key"="b_key" { ; CHECK-LABEL: a: // @a ; CHECK: // %bb.0: ; CHECK-NEXT: .cfi_b_key_frame +; CHECK-NEXT: .cfi_negate_ra_state ; V8A-NEXT: hint #27 ; V83A-NEXT: pacibsp -; CHECK-NEXT: .cfi_negate_ra_state %1 = alloca i32, align 4 %2 = alloca i32, align 4 %3 = alloca i32, align 4 diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll index 6a11bef08c74..a26dda1d5c1f 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll @@ -5,9 +5,9 @@ define void @a() "sign-return-address"="all" { ; CHECK-LABEL: a: // @a -; V8A: hint #25 -; V83A: paciasp -; CHECK-NEXT: .cfi_negate_ra_state +; CHECK: .cfi_negate_ra_state +; V8A-NEXT: hint #25 +; V83A-NEXT: paciasp %1 = alloca i32, align 4 %2 = alloca i32, align 4 %3 = alloca i32, align 4 @@ -52,9 +52,9 @@ define void @b() "sign-return-address"="non-leaf" { define void @c() "sign-return-address"="all" { ; CHECK-LABEL: c: // @c -; V8A: hint #25 -; V83A: paciasp -; CHECK-NEXT .cfi_negate_ra_state +; CHECK: .cfi_negate_ra_state +; V8A-NEXT: hint #25 +; V83A-NEXT: paciasp %1 = alloca i32, align 4 %2 = alloca i32, align 4 %3 = alloca i32, align 4 diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll index 1e7224683c6c..064b2b78c7bc 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll @@ -8,8 +8,8 @@ define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key" ; V8A-LABEL: a: ; V8A: // %bb.0: ; V8A-NEXT: .cfi_b_key_frame -; V8A-NEXT: hint #27 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #27 ; V8A-NEXT: sub sp, sp, #32 ; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; V8A-NEXT: .cfi_def_cfa_offset 32 @@ -26,8 +26,8 @@ define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key" ; V83A-LABEL: a: ; V83A: // %bb.0: ; V83A-NEXT: .cfi_b_key_frame -; V83A-NEXT: pacibsp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: pacibsp ; V83A-NEXT: sub sp, sp, #32 ; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 32 @@ -59,8 +59,8 @@ define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key" ; V8A-LABEL: b: ; V8A: // %bb.0: ; V8A-NEXT: .cfi_b_key_frame -; V8A-NEXT: hint #27 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #27 ; V8A-NEXT: sub sp, sp, #32 ; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; V8A-NEXT: .cfi_def_cfa_offset 32 @@ -77,8 +77,8 @@ define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key" ; V83A-LABEL: b: ; V83A: // %bb.0: ; V83A-NEXT: .cfi_b_key_frame -; V83A-NEXT: pacibsp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: pacibsp ; V83A-NEXT: sub sp, sp, #32 ; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 32 @@ -110,8 +110,8 @@ define i64 @c(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key" ; V8A-LABEL: c: ; V8A: // %bb.0: ; V8A-NEXT: .cfi_b_key_frame -; V8A-NEXT: hint #27 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #27 ; V8A-NEXT: sub sp, sp, #32 ; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; V8A-NEXT: .cfi_def_cfa_offset 32 @@ -128,8 +128,8 @@ define i64 @c(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key" ; V83A-LABEL: c: ; V83A: // %bb.0: ; V83A-NEXT: .cfi_b_key_frame -; V83A-NEXT: pacibsp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: pacibsp ; V83A-NEXT: sub sp, sp, #32 ; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 32 diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir index 9a983cbd6714..218ee6609c80 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir @@ -81,8 +81,8 @@ body: | # CHECK: name: bar # CHECK: bb.0: # CHECK: frame-setup EMITBKEY -# CHECK-NEXT: frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NOT: OUTLINED_FUNCTION_ # CHECK: bb.1: # CHECK-NOT: OUTLINED_FUNCTION_ diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll index 87771f5de4f6..5c45373d8c1d 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll @@ -7,8 +7,8 @@ define void @a() "sign-return-address"="all" { ; V8A-LABEL: a: ; V8A: // %bb.0: -; V8A-NEXT: hint #25 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #25 ; V8A-NEXT: sub sp, sp, #32 ; V8A-NEXT: .cfi_def_cfa_offset 32 ; V8A-NEXT: mov w8, #1 // =0x1 @@ -26,8 +26,8 @@ define void @a() "sign-return-address"="all" { ; ; V83A-LABEL: a: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: sub sp, sp, #32 ; V83A-NEXT: .cfi_def_cfa_offset 32 ; V83A-NEXT: mov w8, #1 // =0x1 @@ -60,8 +60,8 @@ define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" { ; V8A-LABEL: b: ; V8A: // %bb.0: ; V8A-NEXT: .cfi_b_key_frame -; V8A-NEXT: hint #27 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #27 ; V8A-NEXT: sub sp, sp, #32 ; V8A-NEXT: .cfi_def_cfa_offset 32 ; V8A-NEXT: mov w8, #1 // =0x1 @@ -80,8 +80,8 @@ define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" { ; V83A-LABEL: b: ; V83A: // %bb.0: ; V83A-NEXT: .cfi_b_key_frame -; V83A-NEXT: pacibsp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: pacibsp ; V83A-NEXT: sub sp, sp, #32 ; V83A-NEXT: .cfi_def_cfa_offset 32 ; V83A-NEXT: mov w8, #1 // =0x1 @@ -113,8 +113,8 @@ define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" { define void @c() "sign-return-address"="all" { ; V8A-LABEL: c: ; V8A: // %bb.0: -; V8A-NEXT: hint #25 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #25 ; V8A-NEXT: sub sp, sp, #32 ; V8A-NEXT: .cfi_def_cfa_offset 32 ; V8A-NEXT: mov w8, #1 // =0x1 @@ -132,8 +132,8 @@ define void @c() "sign-return-address"="all" { ; ; V83A-LABEL: c: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: sub sp, sp, #32 ; V83A-NEXT: .cfi_def_cfa_offset 32 ; V83A-NEXT: mov w8, #1 // =0x1 diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir index 22e5edef2a93..d4a4b886ec0e 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir @@ -86,11 +86,11 @@ body: | # CHECK: body: | # CHECK-NEXT: bb.0 (%ir-block.0): # CHECK-NEXT: liveins: $lr -# CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK: BL @[[OUTLINED_FUNC:OUTLINED_FUNCTION_[0-9]+]] -# CHECK: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NEXT: RET undef $lr ... @@ -119,11 +119,11 @@ body: | # CHECK: body: | # CHECK-NEXT: bb.0 (%ir-block.0): # CHECK-NEXT: liveins: $lr -# CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK: BL @[[OUTLINED_FUNC]] -# CHECK: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NEXT: RET undef $lr ... @@ -174,22 +174,22 @@ body: | # CHECK: body: | # CHECK-NEXT: bb.0 (%ir-block.0): # CHECK-NEXT: liveins: $lr -# CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NOT: BL @OUTLINED_FUNCTION_{{.*}} -# CHECK: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NEXT: RET undef $lr # CHECK-LABEL: name: illegal1 # CHECK: body: | # CHECK-NEXT: bb.0 (%ir-block.0): # CHECK-NEXT: liveins: $lr -# CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NOT: BL @OUTLINED_FUNCTION_{{.*}} -# CHECK: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp -# CHECK-NEXT: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK: frame-destroy CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NEXT: RET undef $lr # Outlined function that contains only legal sp modifications @@ -198,8 +198,8 @@ body: | # CHECK-NEXT: bb.0: # CHECK-NEXT: liveins: $lr # CHECK-NEXT: {{^ $}} -# CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state +# CHECK-NEXT: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp # CHECK-NEXT: $sp = frame-setup SUBXri $sp, 16, 0 # CHECK: $sp = frame-destroy ADDXri $sp, 16, 0 # CHECK-NEXT: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll index a7ea32952f3b..cb43b3ba3e47 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll @@ -9,8 +9,8 @@ define void @a() #0 { ; CHECK-LABEL: a: // @a ; CHECK: // %bb.0: ; CHECK-NEXT: .cfi_b_key_frame -; CHECK-NEXT: pacibsp ; CHECK-NEXT: .cfi_negate_ra_state +; CHECK-NEXT: pacibsp ; CHECK-NOT: OUTLINED_FUNCTION_ %1 = alloca i32, align 4 %2 = alloca i32, align 4 @@ -33,8 +33,8 @@ define void @b() #0 { ; CHECK-LABEL: b: // @b ; CHECK: // %bb.0: ; CHECK-NEXT: .cfi_b_key_frame -; CHECK-NEXT: pacibsp ; CHECK-NEXT: .cfi_negate_ra_state +; CHECK-NEXT: pacibsp ; CHECK-NOT: OUTLINED_FUNCTION_ %1 = alloca i32, align 4 %2 = alloca i32, align 4 @@ -57,8 +57,8 @@ define void @c() #1 { ; CHECK-LABEL: c: // @c ; CHECK: // %bb.0: ; CHECK-NEXT: .cfi_b_key_frame -; CHECK-NEXT: hint #27 ; CHECK-NEXT: .cfi_negate_ra_state +; CHECK-NEXT: hint #27 ; CHECK-NOT: OUTLINED_FUNCTION_ %1 = alloca i32, align 4 %2 = alloca i32, align 4 diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll index da68ea5bf0db..0ba445553292 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll @@ -10,8 +10,8 @@ declare i32 @thunk_called_fn(i32, i32, i32, i32) define i32 @a() #0 { ; V8A-LABEL: a: ; V8A: // %bb.0: // %entry -; V8A-NEXT: hint #25 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #25 ; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V8A-NEXT: .cfi_def_cfa_offset 16 ; V8A-NEXT: .cfi_offset w30, -16 @@ -27,8 +27,8 @@ define i32 @a() #0 { ; ; V83A-LABEL: a: ; V83A: // %bb.0: // %entry -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -49,8 +49,8 @@ entry: define i32 @b() #0 { ; V8A-LABEL: b: ; V8A: // %bb.0: // %entry -; V8A-NEXT: hint #25 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #25 ; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V8A-NEXT: .cfi_def_cfa_offset 16 ; V8A-NEXT: .cfi_offset w30, -16 @@ -66,8 +66,8 @@ define i32 @b() #0 { ; ; V83A-LABEL: b: ; V83A: // %bb.0: // %entry -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -88,8 +88,8 @@ entry: define hidden i32 @c(ptr %fptr) #0 { ; V8A-LABEL: c: ; V8A: // %bb.0: // %entry -; V8A-NEXT: hint #25 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #25 ; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V8A-NEXT: .cfi_def_cfa_offset 16 ; V8A-NEXT: .cfi_offset w30, -16 @@ -106,8 +106,8 @@ define hidden i32 @c(ptr %fptr) #0 { ; ; V83A-LABEL: c: ; V83A: // %bb.0: // %entry -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -129,8 +129,8 @@ entry: define hidden i32 @d(ptr %fptr) #0 { ; V8A-LABEL: d: ; V8A: // %bb.0: // %entry -; V8A-NEXT: hint #25 ; V8A-NEXT: .cfi_negate_ra_state +; V8A-NEXT: hint #25 ; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V8A-NEXT: .cfi_def_cfa_offset 16 ; V8A-NEXT: .cfi_offset w30, -16 @@ -147,8 +147,8 @@ define hidden i32 @d(ptr %fptr) #0 { ; ; V83A-LABEL: d: ; V83A: // %bb.0: // %entry -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -176,3 +176,5 @@ attributes #0 = { "sign-return-address"="non-leaf" minsize } ; CHECK-NOT: .cfi_negate_ra_state ; CHECK-NOT: auti{{[a,b]}}sp ; CHECK-NOT: hint #{{[29,31]}} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/CodeGen/AArch64/memcmp.ll b/llvm/test/CodeGen/AArch64/memcmp.ll index 4da7c8c95a4e..98ea86b06d6c 100644 --- a/llvm/test/CodeGen/AArch64/memcmp.ll +++ b/llvm/test/CodeGen/AArch64/memcmp.ll @@ -162,8 +162,7 @@ define i32 @length3(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp w8, w9 ; CHECK-NEXT: cset w8, hi -; CHECK-NEXT: cset w9, lo -; CHECK-NEXT: sub w0, w8, w9 +; CHECK-NEXT: csinv w0, w8, wzr, hs ; CHECK-NEXT: ret %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 3) nounwind ret i32 %m @@ -194,8 +193,7 @@ define i32 @length4(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp w8, w9 ; CHECK-NEXT: cset w8, hi -; CHECK-NEXT: cset w9, lo -; CHECK-NEXT: sub w0, w8, w9 +; CHECK-NEXT: csinv w0, w8, wzr, hs ; CHECK-NEXT: ret %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind ret i32 %m @@ -259,6 +257,36 @@ define i1 @length4_gt(ptr %X, ptr %Y) nounwind { ret i1 %c } +define i1 @length4_le(ptr %X, ptr %Y) nounwind { +; CHECK-LABEL: length4_le: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr w8, [x0] +; CHECK-NEXT: ldr w9, [x1] +; CHECK-NEXT: rev w8, w8 +; CHECK-NEXT: rev w9, w9 +; CHECK-NEXT: cmp w8, w9 +; CHECK-NEXT: cset w0, ls +; CHECK-NEXT: ret + %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind + %c = icmp slt i32 %m, 1 + ret i1 %c +} + +define i1 @length4_ge(ptr %X, ptr %Y) nounwind { +; CHECK-LABEL: length4_ge: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr w8, [x0] +; CHECK-NEXT: ldr w9, [x1] +; CHECK-NEXT: rev w8, w8 +; CHECK-NEXT: rev w9, w9 +; CHECK-NEXT: cmp w8, w9 +; CHECK-NEXT: cset w0, hs +; CHECK-NEXT: ret + %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind + %c = icmp sgt i32 %m, -1 + ret i1 %c +} + define i1 @length4_eq_const(ptr %X) nounwind { ; CHECK-LABEL: length4_eq_const: ; CHECK: // %bb.0: @@ -286,8 +314,7 @@ define i32 @length5(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: cset w8, hi -; CHECK-NEXT: cset w9, lo -; CHECK-NEXT: sub w0, w8, w9 +; CHECK-NEXT: csinv w0, w8, wzr, hs ; CHECK-NEXT: ret %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 5) nounwind ret i32 %m @@ -341,8 +368,7 @@ define i32 @length6(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: cset w8, hi -; CHECK-NEXT: cset w9, lo -; CHECK-NEXT: sub w0, w8, w9 +; CHECK-NEXT: csinv w0, w8, wzr, hs ; CHECK-NEXT: ret %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 6) nounwind ret i32 %m @@ -375,18 +401,18 @@ define i32 @length7(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev w8, w8 ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp w8, w9 -; CHECK-NEXT: b.ne .LBB24_3 +; CHECK-NEXT: b.ne .LBB26_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldur w8, [x0, #3] ; CHECK-NEXT: ldur w9, [x1, #3] ; CHECK-NEXT: rev w8, w8 ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp w8, w9 -; CHECK-NEXT: b.ne .LBB24_3 +; CHECK-NEXT: b.ne .LBB26_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB24_3: // %res_block +; CHECK-NEXT: .LBB26_3: // %res_block ; CHECK-NEXT: cmp w8, w9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -403,18 +429,18 @@ define i1 @length7_lt(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev w8, w8 ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp w8, w9 -; CHECK-NEXT: b.ne .LBB25_3 +; CHECK-NEXT: b.ne .LBB27_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldur w8, [x0, #3] ; CHECK-NEXT: ldur w9, [x1, #3] ; CHECK-NEXT: rev w8, w8 ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp w8, w9 -; CHECK-NEXT: b.ne .LBB25_3 +; CHECK-NEXT: b.ne .LBB27_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB25_3: // %res_block +; CHECK-NEXT: .LBB27_3: // %res_block ; CHECK-NEXT: cmp w8, w9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -450,8 +476,7 @@ define i32 @length8(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: cset w8, hi -; CHECK-NEXT: cset w9, lo -; CHECK-NEXT: sub w0, w8, w9 +; CHECK-NEXT: csinv w0, w8, wzr, hs ; CHECK-NEXT: ret %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 8) nounwind ret i32 %m @@ -494,13 +519,13 @@ define i32 @length9(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB30_2 +; CHECK-NEXT: b.ne .LBB32_2 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldrb w8, [x0, #8] ; CHECK-NEXT: ldrb w9, [x1, #8] ; CHECK-NEXT: sub w0, w8, w9 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB30_2: // %res_block +; CHECK-NEXT: .LBB32_2: // %res_block ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs ; CHECK-NEXT: ret @@ -532,7 +557,7 @@ define i32 @length10(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB32_3 +; CHECK-NEXT: b.ne .LBB34_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldrh w8, [x0, #8] ; CHECK-NEXT: ldrh w9, [x1, #8] @@ -541,11 +566,11 @@ define i32 @length10(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: lsr w8, w8, #16 ; CHECK-NEXT: lsr w9, w9, #16 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB32_3 +; CHECK-NEXT: b.ne .LBB34_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB32_3: // %res_block +; CHECK-NEXT: .LBB34_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -578,18 +603,18 @@ define i32 @length11(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB34_3 +; CHECK-NEXT: b.ne .LBB36_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldur x8, [x0, #3] ; CHECK-NEXT: ldur x9, [x1, #3] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB34_3 +; CHECK-NEXT: b.ne .LBB36_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB34_3: // %res_block +; CHECK-NEXT: .LBB36_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -638,18 +663,18 @@ define i32 @length12(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB37_3 +; CHECK-NEXT: b.ne .LBB39_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr w8, [x0, #8] ; CHECK-NEXT: ldr w9, [x1, #8] ; CHECK-NEXT: rev w8, w8 ; CHECK-NEXT: rev w9, w9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB37_3 +; CHECK-NEXT: b.ne .LBB39_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB37_3: // %res_block +; CHECK-NEXT: .LBB39_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -698,18 +723,18 @@ define i32 @length15(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB40_3 +; CHECK-NEXT: b.ne .LBB42_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldur x8, [x0, #7] ; CHECK-NEXT: ldur x9, [x1, #7] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB40_3 +; CHECK-NEXT: b.ne .LBB42_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB40_3: // %res_block +; CHECK-NEXT: .LBB42_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -726,18 +751,18 @@ define i1 @length15_lt(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB41_3 +; CHECK-NEXT: b.ne .LBB43_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldur x8, [x0, #7] ; CHECK-NEXT: ldur x9, [x1, #7] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB41_3 +; CHECK-NEXT: b.ne .LBB43_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB41_3: // %res_block +; CHECK-NEXT: .LBB43_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -758,7 +783,7 @@ define i32 @length15_const(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: movk x8, #12594, lsl #48 ; CHECK-NEXT: cmp x9, x8 -; CHECK-NEXT: b.ne .LBB42_3 +; CHECK-NEXT: b.ne .LBB44_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: mov x8, #13365 // =0x3435 ; CHECK-NEXT: ldur x9, [x0, #7] @@ -767,11 +792,11 @@ define i32 @length15_const(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: movk x8, #14393, lsl #48 ; CHECK-NEXT: cmp x9, x8 -; CHECK-NEXT: b.ne .LBB42_3 +; CHECK-NEXT: b.ne .LBB44_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB42_3: // %res_block +; CHECK-NEXT: .LBB44_3: // %res_block ; CHECK-NEXT: cmp x9, x8 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -806,7 +831,7 @@ define i1 @length15_gt_const(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: movk x8, #12594, lsl #48 ; CHECK-NEXT: cmp x9, x8 -; CHECK-NEXT: b.ne .LBB44_3 +; CHECK-NEXT: b.ne .LBB46_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: mov x8, #13365 // =0x3435 ; CHECK-NEXT: ldur x9, [x0, #7] @@ -815,15 +840,15 @@ define i1 @length15_gt_const(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: movk x8, #14393, lsl #48 ; CHECK-NEXT: cmp x9, x8 -; CHECK-NEXT: b.ne .LBB44_3 +; CHECK-NEXT: b.ne .LBB46_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB44_4 -; CHECK-NEXT: .LBB44_3: // %res_block +; CHECK-NEXT: b .LBB46_4 +; CHECK-NEXT: .LBB46_3: // %res_block ; CHECK-NEXT: cmp x9, x8 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB44_4: // %endblock +; CHECK-NEXT: .LBB46_4: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret @@ -841,18 +866,18 @@ define i32 @length16(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB45_3 +; CHECK-NEXT: b.ne .LBB47_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB45_3 +; CHECK-NEXT: b.ne .LBB47_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB45_3: // %res_block +; CHECK-NEXT: .LBB47_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -883,18 +908,18 @@ define i1 @length16_lt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB47_3 +; CHECK-NEXT: b.ne .LBB49_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB47_3 +; CHECK-NEXT: b.ne .LBB49_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB47_3: // %res_block +; CHECK-NEXT: .LBB49_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -913,22 +938,22 @@ define i1 @length16_gt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB48_3 +; CHECK-NEXT: b.ne .LBB50_3 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB48_3 +; CHECK-NEXT: b.ne .LBB50_3 ; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB48_4 -; CHECK-NEXT: .LBB48_3: // %res_block +; CHECK-NEXT: b .LBB50_4 +; CHECK-NEXT: .LBB50_3: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB48_4: // %endblock +; CHECK-NEXT: .LBB50_4: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret @@ -967,25 +992,25 @@ define i32 @length24(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB50_4 +; CHECK-NEXT: b.ne .LBB52_4 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB50_4 +; CHECK-NEXT: b.ne .LBB52_4 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB50_4 +; CHECK-NEXT: b.ne .LBB52_4 ; CHECK-NEXT: // %bb.3: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB50_4: // %res_block +; CHECK-NEXT: .LBB52_4: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -1019,25 +1044,25 @@ define i1 @length24_lt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB52_4 +; CHECK-NEXT: b.ne .LBB54_4 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB52_4 +; CHECK-NEXT: b.ne .LBB54_4 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB52_4 +; CHECK-NEXT: b.ne .LBB54_4 ; CHECK-NEXT: // %bb.3: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB52_4: // %res_block +; CHECK-NEXT: .LBB54_4: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -1056,29 +1081,29 @@ define i1 @length24_gt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB53_4 +; CHECK-NEXT: b.ne .LBB55_4 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB53_4 +; CHECK-NEXT: b.ne .LBB55_4 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB53_4 +; CHECK-NEXT: b.ne .LBB55_4 ; CHECK-NEXT: // %bb.3: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB53_5 -; CHECK-NEXT: .LBB53_4: // %res_block +; CHECK-NEXT: b .LBB55_5 +; CHECK-NEXT: .LBB55_4: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB53_5: // %endblock +; CHECK-NEXT: .LBB55_5: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret @@ -1122,32 +1147,32 @@ define i32 @length31(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB55_5 +; CHECK-NEXT: b.ne .LBB57_5 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB55_5 +; CHECK-NEXT: b.ne .LBB57_5 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB55_5 +; CHECK-NEXT: b.ne .LBB57_5 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldur x8, [x0, #23] ; CHECK-NEXT: ldur x9, [x1, #23] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB55_5 +; CHECK-NEXT: b.ne .LBB57_5 ; CHECK-NEXT: // %bb.4: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB55_5: // %res_block +; CHECK-NEXT: .LBB57_5: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -1184,32 +1209,32 @@ define i1 @length31_lt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB57_5 +; CHECK-NEXT: b.ne .LBB59_5 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB57_5 +; CHECK-NEXT: b.ne .LBB59_5 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB57_5 +; CHECK-NEXT: b.ne .LBB59_5 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldur x8, [x0, #23] ; CHECK-NEXT: ldur x9, [x1, #23] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB57_5 +; CHECK-NEXT: b.ne .LBB59_5 ; CHECK-NEXT: // %bb.4: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB57_5: // %res_block +; CHECK-NEXT: .LBB59_5: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -1228,36 +1253,36 @@ define i1 @length31_gt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB58_5 +; CHECK-NEXT: b.ne .LBB60_5 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB58_5 +; CHECK-NEXT: b.ne .LBB60_5 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB58_5 +; CHECK-NEXT: b.ne .LBB60_5 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldur x8, [x0, #23] ; CHECK-NEXT: ldur x9, [x1, #23] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB58_5 +; CHECK-NEXT: b.ne .LBB60_5 ; CHECK-NEXT: // %bb.4: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB58_6 -; CHECK-NEXT: .LBB58_5: // %res_block +; CHECK-NEXT: b .LBB60_6 +; CHECK-NEXT: .LBB60_5: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB58_6: // %endblock +; CHECK-NEXT: .LBB60_6: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret @@ -1327,32 +1352,32 @@ define i32 @length32(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB61_5 +; CHECK-NEXT: b.ne .LBB63_5 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB61_5 +; CHECK-NEXT: b.ne .LBB63_5 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB61_5 +; CHECK-NEXT: b.ne .LBB63_5 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB61_5 +; CHECK-NEXT: b.ne .LBB63_5 ; CHECK-NEXT: // %bb.4: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB61_5: // %res_block +; CHECK-NEXT: .LBB63_5: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -1388,32 +1413,32 @@ define i1 @length32_lt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB63_5 +; CHECK-NEXT: b.ne .LBB65_5 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB63_5 +; CHECK-NEXT: b.ne .LBB65_5 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB63_5 +; CHECK-NEXT: b.ne .LBB65_5 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB63_5 +; CHECK-NEXT: b.ne .LBB65_5 ; CHECK-NEXT: // %bb.4: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB63_5: // %res_block +; CHECK-NEXT: .LBB65_5: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -1432,36 +1457,36 @@ define i1 @length32_gt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB64_5 +; CHECK-NEXT: b.ne .LBB66_5 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB64_5 +; CHECK-NEXT: b.ne .LBB66_5 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB64_5 +; CHECK-NEXT: b.ne .LBB66_5 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB64_5 +; CHECK-NEXT: b.ne .LBB66_5 ; CHECK-NEXT: // %bb.4: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB64_6 -; CHECK-NEXT: .LBB64_5: // %res_block +; CHECK-NEXT: b .LBB66_6 +; CHECK-NEXT: .LBB66_5: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB64_6: // %endblock +; CHECK-NEXT: .LBB66_6: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret @@ -1528,46 +1553,46 @@ define i32 @length48(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB67_7 +; CHECK-NEXT: b.ne .LBB69_7 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB67_7 +; CHECK-NEXT: b.ne .LBB69_7 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB67_7 +; CHECK-NEXT: b.ne .LBB69_7 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB67_7 +; CHECK-NEXT: b.ne .LBB69_7 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB67_7 +; CHECK-NEXT: b.ne .LBB69_7 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB67_7 +; CHECK-NEXT: b.ne .LBB69_7 ; CHECK-NEXT: // %bb.6: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB67_7: // %res_block +; CHECK-NEXT: .LBB69_7: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -1606,46 +1631,46 @@ define i1 @length48_lt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB69_7 +; CHECK-NEXT: b.ne .LBB71_7 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB69_7 +; CHECK-NEXT: b.ne .LBB71_7 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB69_7 +; CHECK-NEXT: b.ne .LBB71_7 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB69_7 +; CHECK-NEXT: b.ne .LBB71_7 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB69_7 +; CHECK-NEXT: b.ne .LBB71_7 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB69_7 +; CHECK-NEXT: b.ne .LBB71_7 ; CHECK-NEXT: // %bb.6: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB69_7: // %res_block +; CHECK-NEXT: .LBB71_7: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -1664,50 +1689,50 @@ define i1 @length48_gt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB70_7 +; CHECK-NEXT: b.ne .LBB72_7 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB70_7 +; CHECK-NEXT: b.ne .LBB72_7 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB70_7 +; CHECK-NEXT: b.ne .LBB72_7 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB70_7 +; CHECK-NEXT: b.ne .LBB72_7 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB70_7 +; CHECK-NEXT: b.ne .LBB72_7 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB70_7 +; CHECK-NEXT: b.ne .LBB72_7 ; CHECK-NEXT: // %bb.6: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB70_8 -; CHECK-NEXT: .LBB70_7: // %res_block +; CHECK-NEXT: b .LBB72_8 +; CHECK-NEXT: .LBB72_7: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB70_8: // %endblock +; CHECK-NEXT: .LBB72_8: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret @@ -1785,60 +1810,60 @@ define i32 @length63(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.6: // %loadbb6 ; CHECK-NEXT: ldr x8, [x0, #48] ; CHECK-NEXT: ldr x9, [x1, #48] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.7: // %loadbb7 ; CHECK-NEXT: ldur x8, [x0, #55] ; CHECK-NEXT: ldur x9, [x1, #55] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB73_9 +; CHECK-NEXT: b.ne .LBB75_9 ; CHECK-NEXT: // %bb.8: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB73_9: // %res_block +; CHECK-NEXT: .LBB75_9: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -1883,60 +1908,60 @@ define i1 @length63_lt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.6: // %loadbb6 ; CHECK-NEXT: ldr x8, [x0, #48] ; CHECK-NEXT: ldr x9, [x1, #48] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.7: // %loadbb7 ; CHECK-NEXT: ldur x8, [x0, #55] ; CHECK-NEXT: ldur x9, [x1, #55] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB75_9 +; CHECK-NEXT: b.ne .LBB77_9 ; CHECK-NEXT: // %bb.8: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB75_9: // %res_block +; CHECK-NEXT: .LBB77_9: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -1955,64 +1980,64 @@ define i1 @length63_gt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.6: // %loadbb6 ; CHECK-NEXT: ldr x8, [x0, #48] ; CHECK-NEXT: ldr x9, [x1, #48] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.7: // %loadbb7 ; CHECK-NEXT: ldur x8, [x0, #55] ; CHECK-NEXT: ldur x9, [x1, #55] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB76_9 +; CHECK-NEXT: b.ne .LBB78_9 ; CHECK-NEXT: // %bb.8: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB76_10 -; CHECK-NEXT: .LBB76_9: // %res_block +; CHECK-NEXT: b .LBB78_10 +; CHECK-NEXT: .LBB78_9: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB76_10: // %endblock +; CHECK-NEXT: .LBB78_10: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret @@ -2076,60 +2101,60 @@ define i32 @length64(ptr %X, ptr %Y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.6: // %loadbb6 ; CHECK-NEXT: ldr x8, [x0, #48] ; CHECK-NEXT: ldr x9, [x1, #48] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.7: // %loadbb7 ; CHECK-NEXT: ldr x8, [x0, #56] ; CHECK-NEXT: ldr x9, [x1, #56] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB78_9 +; CHECK-NEXT: b.ne .LBB80_9 ; CHECK-NEXT: // %bb.8: ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB78_9: // %res_block +; CHECK-NEXT: .LBB80_9: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w0, w8, hs @@ -2172,60 +2197,60 @@ define i1 @length64_lt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.6: // %loadbb6 ; CHECK-NEXT: ldr x8, [x0, #48] ; CHECK-NEXT: ldr x9, [x1, #48] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.7: // %loadbb7 ; CHECK-NEXT: ldr x8, [x0, #56] ; CHECK-NEXT: ldr x9, [x1, #56] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB80_9 +; CHECK-NEXT: b.ne .LBB82_9 ; CHECK-NEXT: // %bb.8: ; CHECK-NEXT: lsr w0, wzr, #31 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB80_9: // %res_block +; CHECK-NEXT: .LBB82_9: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs @@ -2244,64 +2269,64 @@ define i1 @length64_gt(ptr %x, ptr %y) nounwind { ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.1: // %loadbb1 ; CHECK-NEXT: ldr x8, [x0, #8] ; CHECK-NEXT: ldr x9, [x1, #8] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.2: // %loadbb2 ; CHECK-NEXT: ldr x8, [x0, #16] ; CHECK-NEXT: ldr x9, [x1, #16] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.3: // %loadbb3 ; CHECK-NEXT: ldr x8, [x0, #24] ; CHECK-NEXT: ldr x9, [x1, #24] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.4: // %loadbb4 ; CHECK-NEXT: ldr x8, [x0, #32] ; CHECK-NEXT: ldr x9, [x1, #32] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.5: // %loadbb5 ; CHECK-NEXT: ldr x8, [x0, #40] ; CHECK-NEXT: ldr x9, [x1, #40] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.6: // %loadbb6 ; CHECK-NEXT: ldr x8, [x0, #48] ; CHECK-NEXT: ldr x9, [x1, #48] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.7: // %loadbb7 ; CHECK-NEXT: ldr x8, [x0, #56] ; CHECK-NEXT: ldr x9, [x1, #56] ; CHECK-NEXT: rev x8, x8 ; CHECK-NEXT: rev x9, x9 ; CHECK-NEXT: cmp x8, x9 -; CHECK-NEXT: b.ne .LBB81_9 +; CHECK-NEXT: b.ne .LBB83_9 ; CHECK-NEXT: // %bb.8: ; CHECK-NEXT: mov w8, wzr -; CHECK-NEXT: b .LBB81_10 -; CHECK-NEXT: .LBB81_9: // %res_block +; CHECK-NEXT: b .LBB83_10 +; CHECK-NEXT: .LBB83_9: // %res_block ; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: mov w8, #-1 // =0xffffffff ; CHECK-NEXT: cneg w8, w8, hs -; CHECK-NEXT: .LBB81_10: // %endblock +; CHECK-NEXT: .LBB83_10: // %endblock ; CHECK-NEXT: cmp w8, #0 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll b/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll index c1b9a4c9dbb7..9ece9edb8434 100644 --- a/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll +++ b/llvm/test/CodeGen/AArch64/neon-partial-reduce-dot-product.ll @@ -367,6 +367,166 @@ entry: ret <4 x i64> %partial.reduce } +define <4 x i32> @udot_no_bin_op(<4 x i32> %acc, <16 x i8> %a){ +; CHECK-DOT-LABEL: udot_no_bin_op: +; CHECK-DOT: // %bb.0: +; CHECK-DOT-NEXT: movi v2.16b, #1 +; CHECK-DOT-NEXT: udot v0.4s, v1.16b, v2.16b +; CHECK-DOT-NEXT: ret +; +; CHECK-NODOT-LABEL: udot_no_bin_op: +; CHECK-NODOT: // %bb.0: +; CHECK-NODOT-NEXT: ushll v2.8h, v1.8b, #0 +; CHECK-NODOT-NEXT: ushll2 v1.8h, v1.16b, #0 +; CHECK-NODOT-NEXT: ushll v3.4s, v1.4h, #0 +; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v2.4h +; CHECK-NODOT-NEXT: uaddw2 v2.4s, v3.4s, v2.8h +; CHECK-NODOT-NEXT: uaddw2 v0.4s, v0.4s, v1.8h +; CHECK-NODOT-NEXT: add v0.4s, v2.4s, v0.4s +; CHECK-NODOT-NEXT: ret + %a.wide = zext <16 x i8> %a to <16 x i32> + %partial.reduce = tail call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %acc, <16 x i32> %a.wide) + ret <4 x i32> %partial.reduce +} + +define <4 x i32> @sdot_no_bin_op(<4 x i32> %acc, <16 x i8> %a){ +; CHECK-DOT-LABEL: sdot_no_bin_op: +; CHECK-DOT: // %bb.0: +; CHECK-DOT-NEXT: movi v2.16b, #1 +; CHECK-DOT-NEXT: sdot v0.4s, v1.16b, v2.16b +; CHECK-DOT-NEXT: ret +; +; CHECK-NODOT-LABEL: sdot_no_bin_op: +; CHECK-NODOT: // %bb.0: +; CHECK-NODOT-NEXT: sshll v2.8h, v1.8b, #0 +; CHECK-NODOT-NEXT: sshll2 v1.8h, v1.16b, #0 +; CHECK-NODOT-NEXT: sshll v3.4s, v1.4h, #0 +; CHECK-NODOT-NEXT: saddw v0.4s, v0.4s, v2.4h +; CHECK-NODOT-NEXT: saddw2 v2.4s, v3.4s, v2.8h +; CHECK-NODOT-NEXT: saddw2 v0.4s, v0.4s, v1.8h +; CHECK-NODOT-NEXT: add v0.4s, v2.4s, v0.4s +; CHECK-NODOT-NEXT: ret + %a.wide = sext <16 x i8> %a to <16 x i32> + %partial.reduce = tail call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<4 x i32> %acc, <16 x i32> %a.wide) + ret <4 x i32> %partial.reduce +} + +define <2 x i32> @udot_no_bin_op_narrow(<2 x i32> %acc, <8 x i8> %a){ +; CHECK-DOT-LABEL: udot_no_bin_op_narrow: +; CHECK-DOT: // %bb.0: +; CHECK-DOT-NEXT: movi v2.8b, #1 +; CHECK-DOT-NEXT: udot v0.2s, v1.8b, v2.8b +; CHECK-DOT-NEXT: ret +; +; CHECK-NODOT-LABEL: udot_no_bin_op_narrow: +; CHECK-NODOT: // %bb.0: +; CHECK-NODOT-NEXT: ushll v1.8h, v1.8b, #0 +; CHECK-NODOT-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NODOT-NEXT: ushll v2.4s, v1.4h, #0 +; CHECK-NODOT-NEXT: ushll2 v3.4s, v1.8h, #0 +; CHECK-NODOT-NEXT: ext v4.16b, v1.16b, v1.16b, #8 +; CHECK-NODOT-NEXT: uaddw v0.4s, v0.4s, v1.4h +; CHECK-NODOT-NEXT: ext v3.16b, v3.16b, v3.16b, #8 +; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8 +; CHECK-NODOT-NEXT: add v0.2s, v3.2s, v0.2s +; CHECK-NODOT-NEXT: uaddw v1.4s, v2.4s, v4.4h +; CHECK-NODOT-NEXT: add v0.2s, v1.2s, v0.2s +; CHECK-NODOT-NEXT: ret + %a.wide = zext <8 x i8> %a to <8 x i32> + %partial.reduce = tail call <2 x i32> @llvm.experimental.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> %acc, <8 x i32> %a.wide) + ret <2 x i32> %partial.reduce +} + +define <2 x i32> @sdot_no_bin_op_narrow(<2 x i32> %acc, <8 x i8> %a){ +; CHECK-DOT-LABEL: sdot_no_bin_op_narrow: +; CHECK-DOT: // %bb.0: +; CHECK-DOT-NEXT: movi v2.8b, #1 +; CHECK-DOT-NEXT: sdot v0.2s, v1.8b, v2.8b +; CHECK-DOT-NEXT: ret +; +; CHECK-NODOT-LABEL: sdot_no_bin_op_narrow: +; CHECK-NODOT: // %bb.0: +; CHECK-NODOT-NEXT: sshll v1.8h, v1.8b, #0 +; CHECK-NODOT-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NODOT-NEXT: sshll v2.4s, v1.4h, #0 +; CHECK-NODOT-NEXT: sshll2 v3.4s, v1.8h, #0 +; CHECK-NODOT-NEXT: ext v4.16b, v1.16b, v1.16b, #8 +; CHECK-NODOT-NEXT: saddw v0.4s, v0.4s, v1.4h +; CHECK-NODOT-NEXT: ext v3.16b, v3.16b, v3.16b, #8 +; CHECK-NODOT-NEXT: ext v2.16b, v2.16b, v2.16b, #8 +; CHECK-NODOT-NEXT: add v0.2s, v3.2s, v0.2s +; CHECK-NODOT-NEXT: saddw v1.4s, v2.4s, v4.4h +; CHECK-NODOT-NEXT: add v0.2s, v1.2s, v0.2s +; CHECK-NODOT-NEXT: ret + %a.wide = sext <8 x i8> %a to <8 x i32> + %partial.reduce = tail call <2 x i32> @llvm.experimental.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> %acc, <8 x i32> %a.wide) + ret <2 x i32> %partial.reduce +} + +define <4 x i64> @udot_no_bin_op_8to64(<4 x i64> %acc, <16 x i8> %a){ +; CHECK-DOT-LABEL: udot_no_bin_op_8to64: +; CHECK-DOT: // %bb.0: +; CHECK-DOT-NEXT: movi v3.16b, #1 +; CHECK-DOT-NEXT: movi v4.2d, #0000000000000000 +; CHECK-DOT-NEXT: udot v4.4s, v2.16b, v3.16b +; CHECK-DOT-NEXT: saddw2 v1.2d, v1.2d, v4.4s +; CHECK-DOT-NEXT: saddw v0.2d, v0.2d, v4.2s +; CHECK-DOT-NEXT: ret +; +; CHECK-NODOT-LABEL: udot_no_bin_op_8to64: +; CHECK-NODOT: // %bb.0: +; CHECK-NODOT-NEXT: ushll v3.8h, v2.8b, #0 +; CHECK-NODOT-NEXT: ushll2 v2.8h, v2.16b, #0 +; CHECK-NODOT-NEXT: ushll v4.4s, v3.4h, #0 +; CHECK-NODOT-NEXT: ushll v5.4s, v2.4h, #0 +; CHECK-NODOT-NEXT: ushll2 v3.4s, v3.8h, #0 +; CHECK-NODOT-NEXT: ushll2 v2.4s, v2.8h, #0 +; CHECK-NODOT-NEXT: uaddw2 v1.2d, v1.2d, v4.4s +; CHECK-NODOT-NEXT: uaddw v0.2d, v0.2d, v4.2s +; CHECK-NODOT-NEXT: uaddl2 v4.2d, v3.4s, v5.4s +; CHECK-NODOT-NEXT: uaddl v3.2d, v3.2s, v5.2s +; CHECK-NODOT-NEXT: uaddw2 v1.2d, v1.2d, v2.4s +; CHECK-NODOT-NEXT: uaddw v0.2d, v0.2d, v2.2s +; CHECK-NODOT-NEXT: add v1.2d, v4.2d, v1.2d +; CHECK-NODOT-NEXT: add v0.2d, v3.2d, v0.2d +; CHECK-NODOT-NEXT: ret + %a.wide = zext <16 x i8> %a to <16 x i64> + %partial.reduce = tail call <4 x i64> @llvm.experimental.vector.partial.reduce.add.v4i64.v16i64(<4 x i64> %acc, <16 x i64> %a.wide) + ret <4 x i64> %partial.reduce +} + +define <4 x i64> @sdot_no_bin_op_8to64(<4 x i64> %acc, <16 x i8> %a){ +; CHECK-DOT-LABEL: sdot_no_bin_op_8to64: +; CHECK-DOT: // %bb.0: +; CHECK-DOT-NEXT: movi v3.16b, #1 +; CHECK-DOT-NEXT: movi v4.2d, #0000000000000000 +; CHECK-DOT-NEXT: sdot v4.4s, v2.16b, v3.16b +; CHECK-DOT-NEXT: saddw2 v1.2d, v1.2d, v4.4s +; CHECK-DOT-NEXT: saddw v0.2d, v0.2d, v4.2s +; CHECK-DOT-NEXT: ret +; +; CHECK-NODOT-LABEL: sdot_no_bin_op_8to64: +; CHECK-NODOT: // %bb.0: +; CHECK-NODOT-NEXT: sshll v3.8h, v2.8b, #0 +; CHECK-NODOT-NEXT: sshll2 v2.8h, v2.16b, #0 +; CHECK-NODOT-NEXT: sshll v4.4s, v3.4h, #0 +; CHECK-NODOT-NEXT: sshll v5.4s, v2.4h, #0 +; CHECK-NODOT-NEXT: sshll2 v3.4s, v3.8h, #0 +; CHECK-NODOT-NEXT: sshll2 v2.4s, v2.8h, #0 +; CHECK-NODOT-NEXT: saddw2 v1.2d, v1.2d, v4.4s +; CHECK-NODOT-NEXT: saddw v0.2d, v0.2d, v4.2s +; CHECK-NODOT-NEXT: saddl2 v4.2d, v3.4s, v5.4s +; CHECK-NODOT-NEXT: saddl v3.2d, v3.2s, v5.2s +; CHECK-NODOT-NEXT: saddw2 v1.2d, v1.2d, v2.4s +; CHECK-NODOT-NEXT: saddw v0.2d, v0.2d, v2.2s +; CHECK-NODOT-NEXT: add v1.2d, v4.2d, v1.2d +; CHECK-NODOT-NEXT: add v0.2d, v3.2d, v0.2d +; CHECK-NODOT-NEXT: ret + %a.wide = sext <16 x i8> %a to <16 x i64> + %partial.reduce = tail call <4 x i64> @llvm.experimental.vector.partial.reduce.add.v4i64.v16i64(<4 x i64> %acc, <16 x i64> %a.wide) + ret <4 x i64> %partial.reduce +} + define <4 x i32> @not_udot(<4 x i32> %acc, <8 x i8> %u, <8 x i8> %s) #0{ ; CHECK-LABEL: not_udot: ; CHECK: // %bb.0: @@ -398,3 +558,91 @@ define <2 x i32> @not_udot_narrow(<2 x i32> %acc, <4 x i8> %u, <4 x i8> %s) { %partial.reduce = tail call <2 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v16i32(<2 x i32> %acc, <4 x i32> %mult) ret <2 x i32> %partial.reduce } + +define <2 x i64> @udot_different_types(<2 x i64> %acc, <8 x i16> %a, <8 x i8> %b){ +; CHECK-LABEL: udot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ushll v2.8h, v2.8b, #0 +; CHECK-NEXT: ushll v3.4s, v1.4h, #0 +; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0 +; CHECK-NEXT: ushll v4.4s, v2.4h, #0 +; CHECK-NEXT: ushll2 v2.4s, v2.8h, #0 +; CHECK-NEXT: umull v5.2d, v1.2s, v2.2s +; CHECK-NEXT: umlal v0.2d, v3.2s, v4.2s +; CHECK-NEXT: umlal2 v0.2d, v1.4s, v2.4s +; CHECK-NEXT: umlal2 v5.2d, v3.4s, v4.4s +; CHECK-NEXT: add v0.2d, v5.2d, v0.2d +; CHECK-NEXT: ret +entry: + %a.wide = zext <8 x i16> %a to <8 x i64> + %b.wide = zext <8 x i8> %b to <8 x i64> + %mult = mul nuw nsw <8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <2 x i64> @llvm.experimental.vector.partial.reduce.add.v2i64.v8i64(<2 x i64> %acc, <8 x i64> %mult) + ret <2 x i64> %partial.reduce +} + +define <2 x i64> @sdot_different_types(<2 x i64> %acc, <8 x i16> %a, <8 x i8> %b){ +; CHECK-LABEL: sdot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: sshll v2.8h, v2.8b, #0 +; CHECK-NEXT: sshll v3.4s, v1.4h, #0 +; CHECK-NEXT: sshll2 v1.4s, v1.8h, #0 +; CHECK-NEXT: sshll v4.4s, v2.4h, #0 +; CHECK-NEXT: sshll2 v2.4s, v2.8h, #0 +; CHECK-NEXT: smull v5.2d, v1.2s, v2.2s +; CHECK-NEXT: smlal v0.2d, v3.2s, v4.2s +; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s +; CHECK-NEXT: smlal2 v5.2d, v3.4s, v4.4s +; CHECK-NEXT: add v0.2d, v5.2d, v0.2d +; CHECK-NEXT: ret +entry: + %a.wide = sext <8 x i16> %a to <8 x i64> + %b.wide = sext <8 x i8> %b to <8 x i64> + %mult = mul nuw nsw <8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <2 x i64> @llvm.experimental.vector.partial.reduce.add.v2i64.v8i64(<2 x i64> %acc, <8 x i64> %mult) + ret <2 x i64> %partial.reduce +} + +define <2 x i64> @usdot_different_types(<2 x i64> %acc, <8 x i16> %a, <8 x i8> %b){ +; CHECK-LABEL: usdot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: sshll v2.8h, v2.8b, #0 +; CHECK-NEXT: ushll v3.4s, v1.4h, #0 +; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0 +; CHECK-NEXT: sshll v4.4s, v2.4h, #0 +; CHECK-NEXT: sshll2 v2.4s, v2.8h, #0 +; CHECK-NEXT: smull v5.2d, v1.2s, v2.2s +; CHECK-NEXT: smlal v0.2d, v3.2s, v4.2s +; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s +; CHECK-NEXT: smlal2 v5.2d, v3.4s, v4.4s +; CHECK-NEXT: add v0.2d, v5.2d, v0.2d +; CHECK-NEXT: ret +entry: + %a.wide = zext <8 x i16> %a to <8 x i64> + %b.wide = sext <8 x i8> %b to <8 x i64> + %mult = mul nuw nsw <8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <2 x i64> @llvm.experimental.vector.partial.reduce.add.v2i64.v8i64(<2 x i64> %acc, <8 x i64> %mult) + ret <2 x i64> %partial.reduce +} + +define <2 x i64> @sudot_different_types(<2 x i64> %acc, <8 x i16> %a, <8 x i8> %b){ +; CHECK-LABEL: sudot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ushll v2.8h, v2.8b, #0 +; CHECK-NEXT: sshll v3.4s, v1.4h, #0 +; CHECK-NEXT: sshll2 v1.4s, v1.8h, #0 +; CHECK-NEXT: ushll v4.4s, v2.4h, #0 +; CHECK-NEXT: ushll2 v2.4s, v2.8h, #0 +; CHECK-NEXT: smull v5.2d, v1.2s, v2.2s +; CHECK-NEXT: smlal v0.2d, v3.2s, v4.2s +; CHECK-NEXT: smlal2 v0.2d, v1.4s, v2.4s +; CHECK-NEXT: smlal2 v5.2d, v3.4s, v4.4s +; CHECK-NEXT: add v0.2d, v5.2d, v0.2d +; CHECK-NEXT: ret +entry: + %a.wide = sext <8 x i16> %a to <8 x i64> + %b.wide = zext <8 x i8> %b to <8 x i64> + %mult = mul nuw nsw <8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <2 x i64> @llvm.experimental.vector.partial.reduce.add.v2i64.v8i64(<2 x i64> %acc, <8 x i64> %mult) + ret <2 x i64> %partial.reduce +} diff --git a/llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll b/llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll index abdfb996fa16..db5b93282e9c 100644 --- a/llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll +++ b/llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll @@ -23,19 +23,11 @@ entry: } define <4 x i32> @v4i32(<4 x i32> %a) { -; CHECK-SD-LABEL: v4i32: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: rev64 v0.4s, v0.4s -; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: v4i32: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI2_0 -; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1 -; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI2_0] -; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: v4i32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev64 v0.4s, v0.4s +; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: ret entry: %V128 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ret <4 x i32> %V128 @@ -52,19 +44,11 @@ entry: } define <8 x i16> @v8i16(<8 x i16> %a) { -; CHECK-SD-LABEL: v8i16: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: rev64 v0.8h, v0.8h -; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: v8i16: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI4_0 -; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1 -; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI4_0] -; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: v8i16: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev64 v0.8h, v0.8h +; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: ret entry: %V128 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ret <8 x i16> %V128 @@ -93,6 +77,22 @@ entry: ret <8 x i16> %V128 } +define <4 x i16> @v8i16_3(<8 x i16> %a) { +; CHECK-SD-LABEL: v8i16_3: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: rev64 v0.4h, v0.4h +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: v8i16_3: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: rev64 v0.8h, v0.8h +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret +entry: + %V128 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0> + ret <4 x i16> %V128 +} + define <4 x i16> @v4i16(<4 x i16> %a) { ; CHECK-LABEL: v4i16: ; CHECK: // %bb.0: // %entry @@ -104,19 +104,11 @@ entry: } define <16 x i8> @v16i8(<16 x i8> %a) { -; CHECK-SD-LABEL: v16i8: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: rev64 v0.16b, v0.16b -; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: v16i8: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI7_0 -; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1 -; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI7_0] -; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: v16i8: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev64 v0.16b, v0.16b +; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: ret entry: %V128 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ret <16 x i8> %V128 @@ -125,18 +117,18 @@ entry: define <16 x i8> @v16i8_2(<8 x i8> %a, <8 x i8> %b) { ; CHECK-SD-LABEL: v16i8_2: ; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: adrp x8, .LCPI8_0 +; CHECK-SD-NEXT: adrp x8, .LCPI9_0 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI8_0] +; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI9_0] ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: v16i8_2: ; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI8_0 +; CHECK-GI-NEXT: adrp x8, .LCPI9_0 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI8_0] +; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI9_0] ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 ; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b ; CHECK-GI-NEXT: ret @@ -166,19 +158,11 @@ entry: } define <4 x float> @v4f32(<4 x float> %a) { -; CHECK-SD-LABEL: v4f32: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: rev64 v0.4s, v0.4s -; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: v4f32: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI11_0 -; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1 -; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI11_0] -; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: v4f32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev64 v0.4s, v0.4s +; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: ret entry: %V128 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ret <4 x float> %V128 @@ -195,19 +179,11 @@ entry: } define <8 x half> @v8f16(<8 x half> %a) { -; CHECK-SD-LABEL: v8f16: -; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: rev64 v0.8h, v0.8h -; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: v8f16: -; CHECK-GI: // %bb.0: // %entry -; CHECK-GI-NEXT: adrp x8, .LCPI13_0 -; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q1 -; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI13_0] -; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b -; CHECK-GI-NEXT: ret +; CHECK-LABEL: v8f16: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev64 v0.8h, v0.8h +; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: ret entry: %V128 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ret <8 x half> %V128 diff --git a/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll b/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll index 373c4969a940..f823d2aa82ac 100644 --- a/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll +++ b/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll @@ -34,8 +34,8 @@ entry: } ;; CHECK-LABEL: __llvm_gcov_writeout: ;; CHECK: .cfi_b_key_frame -;; CHECK-NEXT: pacibsp ;; CHECK-NEXT: .cfi_negate_ra_state +;; CHECK-NEXT: pacibsp define internal void @__llvm_gcov_reset() unnamed_addr #2 { entry: @@ -54,9 +54,9 @@ entry: } ;; CHECK-LABEL: __llvm_gcov_init: ;; CHECK: .cfi_b_key_frame -;; CHECK-NEXT: pacibsp ;; CHECK-NEXT: .cfi_negate_ra_state ;; CHECK-NOT: .cfi_ +;; CHECK-NEXT: pacibsp ;; CHECK: .cfi_endproc attributes #0 = { norecurse nounwind readnone "sign-return-address"="all" "sign-return-address-key"="b_key" } diff --git a/llvm/test/CodeGen/AArch64/ptrauth-arm64-tls-dynamics.ll b/llvm/test/CodeGen/AArch64/ptrauth-arm64-tls-dynamics.ll new file mode 100644 index 000000000000..89731e62dcc1 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/ptrauth-arm64-tls-dynamics.ll @@ -0,0 +1,114 @@ +; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+pauth -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+pauth -relocation-model=pic \ +; RUN: -filetype=obj < %s | llvm-readelf -r -s - | FileCheck --check-prefix=CHECK-OBJ %s +; RUN: not --crash llc -mtriple=aarch64-unknown-linux-gnu -mattr=+pauth -relocation-model=pic \ +; RUN: -global-isel=1 < %s 2>&1 | FileCheck --check-prefix=CHECK-ERR %s + +@general_dynamic_var = external thread_local global i32 + +define i32 @test_generaldynamic() { +; CHECK-LABEL: test_generaldynamic: + + %val = load i32, ptr @general_dynamic_var + ret i32 %val + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc_auth:general_dynamic_var +; CHECK-NEXT: ldr x16, [x[[TLSDESC_HI]], :tlsdesc_auth_lo12:general_dynamic_var] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_auth_lo12:general_dynamic_var +; CHECK-NEXT: blraa x16, x0 +; CHECK-NEXT: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK-NEXT: ldr w0, [x[[TPIDR]], x0] + +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADR_PAGE21 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_LD64_LO12 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADD_LO12 +; CHECK-OBJ-NOT: R_AARCH64_TLSDESC_CALL + +; CHECK-ERR: LLVM ERROR: cannot select: %1:gpr64sp(p0) = G_GLOBAL_VALUE @general_dynamic_var (in function: test_generaldynamic) +} + +define ptr @test_generaldynamic_addr() { +; CHECK-LABEL: test_generaldynamic_addr: + + ret ptr @general_dynamic_var + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc_auth:general_dynamic_var +; CHECK-NEXT: ldr x16, [x[[TLSDESC_HI]], :tlsdesc_auth_lo12:general_dynamic_var] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_auth_lo12:general_dynamic_var +; CHECK-NEXT: blraa x16, x0 +; CHECK-NEXT: mrs [[TP:x[0-9]+]], TPIDR_EL0 +; CHECK-NEXT: add x0, [[TP]], x0 + +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADR_PAGE21 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_LD64_LO12 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADD_LO12 +; CHECK-OBJ-NOT: R_AARCH64_TLSDESC_CALL +} + +;; Note: with signed TLSDESC, general dynamic model is always used, +;; even when local dynamic is requested. + +@local_dynamic_var = external thread_local(localdynamic) global i32 + +define i32 @test_localdynamic() { +; CHECK-LABEL: test_localdynamic: + + %val = load i32, ptr @local_dynamic_var + ret i32 %val + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc_auth:local_dynamic_var +; CHECK-NEXT: ldr x16, [x[[TLSDESC_HI]], :tlsdesc_auth_lo12:local_dynamic_var] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_auth_lo12:local_dynamic_var +; CHECK-NEXT: blraa x16, x0 +; CHECK-NEXT: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK-NEXT: ldr w0, [x[[TPIDR]], x0] + +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADR_PAGE21 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_LD64_LO12 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADD_LO12 +; CHECK-OBJ-NOT: R_AARCH64_TLSDESC_CALL +} + +define ptr @test_localdynamic_addr() { +; CHECK-LABEL: test_localdynamic_addr: + + ret ptr @local_dynamic_var + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc_auth:local_dynamic_var +; CHECK-NEXT: ldr x16, [x[[TLSDESC_HI]], :tlsdesc_auth_lo12:local_dynamic_var] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_auth_lo12:local_dynamic_var +; CHECK-NEXT: blraa x16, x0 +; CHECK-NEXT: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK-NEXT: add x0, x[[TPIDR]], x0 + +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADR_PAGE21 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_LD64_LO12 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADD_LO12 +; CHECK-OBJ-NOT: R_AARCH64_TLSDESC_CALL +} + +@extern_weak_var = extern_weak thread_local global i32 + +define i32 @test_extern_weak() { +; CHECK-LABEL: test_extern_weak: + + %val = load i32, ptr @extern_weak_var + ret i32 %val + +; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc_auth:extern_weak_var +; CHECK-NEXT: ldr x16, [x[[TLSDESC_HI]], :tlsdesc_auth_lo12:extern_weak_var] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_auth_lo12:extern_weak_var +; CHECK-NEXT: blraa x16, x0 +; CHECK-NEXT: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK-NEXT: ldr w0, [x[[TPIDR]], x0] + +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADR_PAGE21 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_LD64_LO12 +; CHECK-OBJ: R_AARCH64_AUTH_TLSDESC_ADD_LO12 +; CHECK-OBJ-NOT: R_AARCH64_TLSDESC_CALL +; CHECK-OBJ: 0000000000000000 0 TLS WEAK DEFAULT UND extern_weak_var +} + +!llvm.module.flags = !{!0} +!0 = !{i32 8, !"ptrauth-elf-got", i32 1} diff --git a/llvm/test/CodeGen/AArch64/reduce-or-opt.ll b/llvm/test/CodeGen/AArch64/reduce-or-opt.ll new file mode 100644 index 000000000000..f5df5ea53c99 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/reduce-or-opt.ll @@ -0,0 +1,193 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+sve | FileCheck %s + +define i64 @select_or_reduce_v2i1(ptr nocapture noundef readonly %src) { +; CHECK-LABEL: select_or_reduce_v2i1: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov x8, xzr +; CHECK-NEXT: .LBB0_1: // %vector.body +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ldr q0, [x0, x8] +; CHECK-NEXT: cmeq v0.2d, v0.2d, #0 +; CHECK-NEXT: umaxv s0, v0.4s +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: tbnz w9, #0, .LBB0_3 +; CHECK-NEXT: // %bb.2: // %vector.body +; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: cmp x8, #16 +; CHECK-NEXT: add x8, x8, #16 +; CHECK-NEXT: b.ne .LBB0_1 +; CHECK-NEXT: .LBB0_3: // %middle.split +; CHECK-NEXT: and x0, x9, #0x1 +; CHECK-NEXT: ret +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index + %wide.load = load <2 x ptr>, ptr %arrayidx, align 8 + %cond = icmp eq <2 x ptr> %wide.load, splat(ptr zeroinitializer) + %index.next = add nuw i64 %index, 2 + %or.reduc = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %cond) + %iv.cmp = icmp eq i64 %index.next, 4 + %exit.cond = or i1 %or.reduc, %iv.cmp + br i1 %exit.cond, label %middle.split, label %vector.body + +middle.split: + %sel = select i1 %or.reduc, i64 1, i64 0 + ret i64 %sel +} + +define i64 @br_or_reduce_v2i1(ptr nocapture noundef readonly %src, ptr noundef readnone %p) { +; CHECK-LABEL: br_or_reduce_v2i1: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov x8, xzr +; CHECK-NEXT: .LBB1_1: // %vector.body +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ldr q0, [x0, x8] +; CHECK-NEXT: cmeq v0.2d, v0.2d, #0 +; CHECK-NEXT: umaxv s0, v0.4s +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: tbnz w9, #0, .LBB1_3 +; CHECK-NEXT: // %bb.2: // %vector.body +; CHECK-NEXT: // in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: cmp x8, #16 +; CHECK-NEXT: add x8, x8, #16 +; CHECK-NEXT: b.ne .LBB1_1 +; CHECK-NEXT: .LBB1_3: // %middle.split +; CHECK-NEXT: tbz w9, #0, .LBB1_5 +; CHECK-NEXT: // %bb.4: // %found +; CHECK-NEXT: mov w8, #56 // =0x38 +; CHECK-NEXT: mov w0, #1 // =0x1 +; CHECK-NEXT: str x8, [x1] +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB1_5: +; CHECK-NEXT: mov x0, xzr +; CHECK-NEXT: ret +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index + %wide.load = load <2 x ptr>, ptr %arrayidx, align 8 + %cond = icmp eq <2 x ptr> %wide.load, splat(ptr zeroinitializer) + %index.next = add nuw i64 %index, 2 + %or.reduc = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %cond) + %iv.cmp = icmp eq i64 %index.next, 4 + %exit.cond = or i1 %or.reduc, %iv.cmp + br i1 %exit.cond, label %middle.split, label %vector.body + +middle.split: + br i1 %or.reduc, label %found, label %notfound + +found: + store i64 56, ptr %p, align 8 + ret i64 1 + +notfound: + ret i64 0 +} + +define i64 @select_or_reduce_nxv2i1(ptr nocapture noundef readonly %src) { +; CHECK-LABEL: select_or_reduce_nxv2i1: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: cntd x8 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: mov x9, xzr +; CHECK-NEXT: neg x10, x8 +; CHECK-NEXT: add x10, x10, #4 +; CHECK-NEXT: .LBB2_1: // %vector.body +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x9, lsl #3] +; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0 +; CHECK-NEXT: b.ne .LBB2_3 +; CHECK-NEXT: // %bb.2: // %vector.body +; CHECK-NEXT: // in Loop: Header=BB2_1 Depth=1 +; CHECK-NEXT: cmp x10, x9 +; CHECK-NEXT: add x9, x9, x8 +; CHECK-NEXT: b.ne .LBB2_1 +; CHECK-NEXT: .LBB2_3: // %middle.split +; CHECK-NEXT: ptest p0, p1.b +; CHECK-NEXT: cset w0, ne +; CHECK-NEXT: ret +entry: + %vscale = tail call i64 @llvm.vscale.i64() + %vf = shl nuw nsw i64 %vscale, 1 + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index + %wide.load = load <vscale x 2 x ptr>, ptr %arrayidx, align 8 + %cond = icmp eq <vscale x 2 x ptr> %wide.load, splat(ptr zeroinitializer) + %index.next = add nuw i64 %index, %vf + %or.reduc = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %cond) + %iv.cmp = icmp eq i64 %index.next, 4 + %exit.cond = or i1 %or.reduc, %iv.cmp + br i1 %exit.cond, label %middle.split, label %vector.body + +middle.split: + %sel = select i1 %or.reduc, i64 1, i64 0 + ret i64 %sel +} + +define i64 @br_or_reduce_nxv2i1(ptr nocapture noundef readonly %src, ptr noundef readnone %p) { +; CHECK-LABEL: br_or_reduce_nxv2i1: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: cntd x8 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: mov x9, xzr +; CHECK-NEXT: neg x10, x8 +; CHECK-NEXT: add x10, x10, #4 +; CHECK-NEXT: .LBB3_1: // %vector.body +; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x9, lsl #3] +; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0 +; CHECK-NEXT: b.ne .LBB3_3 +; CHECK-NEXT: // %bb.2: // %vector.body +; CHECK-NEXT: // in Loop: Header=BB3_1 Depth=1 +; CHECK-NEXT: cmp x10, x9 +; CHECK-NEXT: add x9, x9, x8 +; CHECK-NEXT: b.ne .LBB3_1 +; CHECK-NEXT: .LBB3_3: // %middle.split +; CHECK-NEXT: ptest p0, p1.b +; CHECK-NEXT: b.eq .LBB3_5 +; CHECK-NEXT: // %bb.4: // %found +; CHECK-NEXT: mov w8, #56 // =0x38 +; CHECK-NEXT: mov w0, #1 // =0x1 +; CHECK-NEXT: str x8, [x1] +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB3_5: +; CHECK-NEXT: mov x0, xzr +; CHECK-NEXT: ret +entry: + %vscale = tail call i64 @llvm.vscale.i64() + %vf = shl nuw nsw i64 %vscale, 1 + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index + %wide.load = load <vscale x 2 x ptr>, ptr %arrayidx, align 8 + %cond = icmp eq <vscale x 2 x ptr> %wide.load, splat(ptr zeroinitializer) + %index.next = add nuw i64 %index, %vf + %or.reduc = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %cond) + %iv.cmp = icmp eq i64 %index.next, 4 + %exit.cond = or i1 %or.reduc, %iv.cmp + br i1 %exit.cond, label %middle.split, label %vector.body + +middle.split: + br i1 %or.reduc, label %found, label %notfound + +found: + store i64 56, ptr %p, align 8 + ret i64 1 + +notfound: + ret i64 0 +} + +declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>) +declare i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1>) diff --git a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir index b61fa4be0400..08fc47d9480c 100644 --- a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir +++ b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir @@ -1,5 +1,5 @@ +# RUN: llc -mtriple=aarch64 -o /dev/null -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking -debug-only=regalloc %s 2>&1 | FileCheck %s --check-prefix=CHECK-DBG # RUN: llc -mtriple=aarch64 -verify-machineinstrs -o - -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking %s | FileCheck %s --check-prefix=CHECK -# RUN: llc -mtriple=aarch64 -verify-machineinstrs -o /dev/null -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking -debug-only=regalloc %s 2>&1 | FileCheck %s --check-prefix=CHECK-DBG # REQUIRES: asserts # CHECK-DBG: ********** REGISTER COALESCER ********** @@ -36,3 +36,94 @@ body: | RET_ReallyLR ... +# CHECK-DBG: ********** REGISTER COALESCER ********** +# CHECK-DBG: ********** Function: reproducer +# CHECK-DBG: ********** JOINING INTERVALS *********** +# CHECK-DBG: ********** INTERVALS ********** +# CHECK-DBG: %1 [32r,48B:2)[48B,320r:0)[320r,368B:1) 0@48B-phi 1@320r 2@32r +# CHECK-DBG-SAME: weight:0.000000e+00 +# CHECK-DBG: %3 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0@288r 1@240r 2@80r 3@304B-phi +# CHECK-DBG-SAME: L0000000000000080 [288r,304B:0)[304B,320r:3) 0@288r 1@x 2@x 3@304B-phi +# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0@288r 1@240r 2@80r 3@304B-phi +# CHECK-DBG-SAME: weight:0.000000e+00 +--- +name: reproducer +tracksRegLiveness: true +body: | + bb.0: + %0:gpr32 = MOVi32imm 1 + %1:gpr64 = IMPLICIT_DEF + + bb.1: + + bb.2: + %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + + bb.3: + $nzcv = IMPLICIT_DEF + %4:gpr64 = COPY killed %3 + Bcc 1, %bb.7, implicit killed $nzcv + + bb.4: + $nzcv = IMPLICIT_DEF + Bcc 1, %bb.6, implicit killed $nzcv + + bb.5: + %5:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %4:gpr64 = COPY killed %5 + B %bb.7 + + bb.6: + %4:gpr64 = COPY $xzr + + bb.7: + %7:gpr64 = ADDXrs killed %1, killed %4, 1 + %1:gpr64 = COPY killed %7 + B %bb.1 + +... +# CHECK-DBG: ********** REGISTER COALESCER ********** +# CHECK-DBG: ********** Function: reproducer2 +# CHECK-DBG: ********** JOINING INTERVALS *********** +# CHECK-DBG: ********** INTERVALS ********** +# CHECK-DBG: %1 [32r,48B:2)[48B,304r:0)[304r,352B:1) 0@48B-phi 1@304r 2@32r +# CHECK-DBG-SAME: weight:0.000000e+00 +# CHECK-DBG: %3 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@80r 3@288B-phi +# CHECK-DBG-SAME: L0000000000000080 [224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@x 3@288B-phi +# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@80r 3@288B-phi +# CHECK-DBG-SAME: weight:0.000000e+00 +--- +name: reproducer2 +tracksRegLiveness: true +body: | + bb.0: + %0:gpr32 = MOVi32imm 1 + %1:gpr64 = IMPLICIT_DEF + + bb.1: + + bb.2: + %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + + bb.3: + $nzcv = IMPLICIT_DEF + %4:gpr64 = COPY killed %3 + Bcc 1, %bb.7, implicit killed $nzcv + + bb.4: + $nzcv = IMPLICIT_DEF + Bcc 1, %bb.6, implicit killed $nzcv + + bb.5: + %4:gpr64 = IMPLICIT_DEF + B %bb.7 + + bb.6: + %4:gpr64 = COPY $xzr + + bb.7: + %5:gpr64 = ADDXrs killed %1, killed %4, 1 + %1:gpr64 = COPY killed %5 + B %bb.1 + +... diff --git a/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll index ec7548e1e654..b7fae2bff687 100644 --- a/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll +++ b/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll @@ -7,19 +7,17 @@ define i32 @testmswbf(bfloat %a) { ; CHECK-LABEL: testmswbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintm s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret entry: @@ -31,19 +29,17 @@ entry: define i64 @testmsxbf(bfloat %a) { ; CHECK-LABEL: testmsxbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintm s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs x0, s0 ; CHECK-NEXT: ret entry: @@ -141,19 +137,17 @@ entry: define i32 @testpswbf(bfloat %a) { ; CHECK-LABEL: testpswbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintp s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret entry: @@ -165,19 +159,17 @@ entry: define i64 @testpsxbf(bfloat %a) { ; CHECK-LABEL: testpsxbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintp s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs x0, s0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/shuffle-select.ll b/llvm/test/CodeGen/AArch64/shuffle-select.ll new file mode 100644 index 000000000000..eeccaa170397 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/shuffle-select.ll @@ -0,0 +1,163 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s + +define <8 x i8> @sel_v8i8(<8 x i8> %v0, <8 x i8> %v1) { +; CHECK-LABEL: sel_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: adrp x8, .LCPI0_0 +; CHECK-NEXT: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0] +; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b +; CHECK-NEXT: ret + %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> + ret <8 x i8> %tmp0 +} + +define <16 x i8> @sel_v16i8(<16 x i8> %v0, <16 x i8> %v1) { +; CHECK-LABEL: sel_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI1_0 +; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_0] +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-NEXT: ret + %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31> + ret <16 x i8> %tmp0 +} + +define <16 x i8> @sel_v16i8_poison(<16 x i8> %v0, <16 x i8> %v1) { +; CHECK-LABEL: sel_v16i8_poison: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI2_0 +; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_0] +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-NEXT: ret + %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + ret <16 x i8> %tmp0 +} + +define <16 x i8> @sel_v16i8_unregular(<16 x i8> %v0, <16 x i8> %v1) { +; CHECK-LABEL: sel_v16i8_unregular: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI3_0 +; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0] +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-NEXT: ret + %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31> + ret <16 x i8> %tmp0 +} + +define <4 x i16> @sel_v4i16(<4 x i16> %v0, <4 x i16> %v1) { +; CHECK-LABEL: sel_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: rev32 v0.4h, v0.4h +; CHECK-NEXT: trn2 v0.4h, v0.4h, v1.4h +; CHECK-NEXT: ret + %tmp0 = shufflevector <4 x i16> %v0, <4 x i16> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x i16> %tmp0 +} + +define <8 x i16> @sel_v8i16(<8 x i16> %v0, <8 x i16> %v1) { +; CHECK-LABEL: sel_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI5_0 +; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_0] +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-NEXT: ret + %tmp0 = shufflevector <8 x i16> %v0, <8 x i16> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> + ret <8 x i16> %tmp0 +} + +define <2 x i32> @sel_v2i32(<2 x i32> %v0, <2 x i32> %v1) { +; CHECK-LABEL: sel_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v0.s[1], v1.s[1] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret + %tmp0 = shufflevector <2 x i32> %v0, <2 x i32> %v1, <2 x i32> <i32 0, i32 3> + ret <2 x i32> %tmp0 +} + +define <4 x i32> @sel_v4i32(<4 x i32> %v0, <4 x i32> %v1) { +; CHECK-LABEL: sel_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: rev64 v0.4s, v0.4s +; CHECK-NEXT: trn2 v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret + %tmp0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x i32> %tmp0 +} + +define <2 x i64> @sel_v2i64(<2 x i64> %v0, <2 x i64> %v1) { +; CHECK-LABEL: sel_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v0.d[1], v1.d[1] +; CHECK-NEXT: ret + %tmp0 = shufflevector <2 x i64> %v0, <2 x i64> %v1, <2 x i32> <i32 0, i32 3> + ret <2 x i64> %tmp0 +} + +define <4 x half> @sel_v4f16(<4 x half> %v0, <4 x half> %v1) { +; CHECK-LABEL: sel_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: rev32 v0.4h, v0.4h +; CHECK-NEXT: trn2 v0.4h, v0.4h, v1.4h +; CHECK-NEXT: ret + %tmp0 = shufflevector <4 x half> %v0, <4 x half> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x half> %tmp0 +} + +define <8 x half> @sel_v8f16(<8 x half> %v0, <8 x half> %v1) { +; CHECK-LABEL: sel_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI10_0 +; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_0] +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-NEXT: ret + %tmp0 = shufflevector <8 x half> %v0, <8 x half> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15> + ret <8 x half> %tmp0 +} + +define <2 x float> @sel_v2f32(<2 x float> %v0, <2 x float> %v1) { +; CHECK-LABEL: sel_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v0.s[1], v1.s[1] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret + %tmp0 = shufflevector <2 x float> %v0, <2 x float> %v1, <2 x i32> <i32 0, i32 3> + ret <2 x float> %tmp0 +} + +define <4 x float> @sel_v4f32(<4 x float> %v0, <4 x float> %v1) { +; CHECK-LABEL: sel_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: rev64 v0.4s, v0.4s +; CHECK-NEXT: trn2 v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret + %tmp0 = shufflevector <4 x float> %v0, <4 x float> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7> + ret <4 x float> %tmp0 +} + +define <2 x double> @sel_v2f64(<2 x double> %v0, <2 x double> %v1) { +; CHECK-LABEL: sel_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v0.d[1], v1.d[1] +; CHECK-NEXT: ret + %tmp0 = shufflevector <2 x double> %v0, <2 x double> %v1, <2 x i32> <i32 0, i32 3> + ret <2 x double> %tmp0 +} diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll index 4d4b7c215b97..6ea072846d47 100644 --- a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll +++ b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll @@ -9,8 +9,8 @@ define dso_local i32 @_Z3fooi(i32 %x) #0 { ; CHECK-V8A-LABEL: _Z3fooi: ; CHECK-V8A: // %bb.0: // %entry -; CHECK-V8A-NEXT: hint #25 ; CHECK-V8A-NEXT: .cfi_negate_ra_state +; CHECK-V8A-NEXT: hint #25 ; CHECK-V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-V8A-NEXT: .cfi_def_cfa_offset 16 ; CHECK-V8A-NEXT: .cfi_offset w30, -16 @@ -27,8 +27,8 @@ define dso_local i32 @_Z3fooi(i32 %x) #0 { ; ; CHECK-V83A-LABEL: _Z3fooi: ; CHECK-V83A: // %bb.0: // %entry -; CHECK-V83A-NEXT: paciasp ; CHECK-V83A-NEXT: .cfi_negate_ra_state +; CHECK-V83A-NEXT: paciasp ; CHECK-V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-V83A-NEXT: .cfi_def_cfa_offset 16 ; CHECK-V83A-NEXT: .cfi_offset w30, -16 @@ -62,8 +62,8 @@ return: ; No predecessors! define hidden noundef i32 @baz_async(i32 noundef %a) #0 uwtable(async) { ; CHECK-V8A-LABEL: baz_async: ; CHECK-V8A: // %bb.0: // %entry -; CHECK-V8A-NEXT: hint #25 ; CHECK-V8A-NEXT: .cfi_negate_ra_state +; CHECK-V8A-NEXT: hint #25 ; CHECK-V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-V8A-NEXT: .cfi_def_cfa_offset 16 ; CHECK-V8A-NEXT: .cfi_offset w30, -16 @@ -74,8 +74,8 @@ define hidden noundef i32 @baz_async(i32 noundef %a) #0 uwtable(async) { ; CHECK-V8A-NEXT: bl _Z3bari ; CHECK-V8A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-V8A-NEXT: .cfi_def_cfa_offset 0 -; CHECK-V8A-NEXT: hint #29 ; CHECK-V8A-NEXT: .cfi_negate_ra_state +; CHECK-V8A-NEXT: hint #29 ; CHECK-V8A-NEXT: .cfi_restore w30 ; CHECK-V8A-NEXT: b _Z3bari ; CHECK-V8A-NEXT: .LBB1_2: // %if.else @@ -84,15 +84,15 @@ define hidden noundef i32 @baz_async(i32 noundef %a) #0 uwtable(async) { ; CHECK-V8A-NEXT: add w0, w0, #1 ; CHECK-V8A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-V8A-NEXT: .cfi_def_cfa_offset 0 -; CHECK-V8A-NEXT: hint #29 ; CHECK-V8A-NEXT: .cfi_negate_ra_state +; CHECK-V8A-NEXT: hint #29 ; CHECK-V8A-NEXT: .cfi_restore w30 ; CHECK-V8A-NEXT: ret ; ; CHECK-V83A-LABEL: baz_async: ; CHECK-V83A: // %bb.0: // %entry -; CHECK-V83A-NEXT: paciasp ; CHECK-V83A-NEXT: .cfi_negate_ra_state +; CHECK-V83A-NEXT: paciasp ; CHECK-V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-V83A-NEXT: .cfi_def_cfa_offset 16 ; CHECK-V83A-NEXT: .cfi_offset w30, -16 @@ -103,8 +103,8 @@ define hidden noundef i32 @baz_async(i32 noundef %a) #0 uwtable(async) { ; CHECK-V83A-NEXT: bl _Z3bari ; CHECK-V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-V83A-NEXT: .cfi_def_cfa_offset 0 -; CHECK-V83A-NEXT: autiasp ; CHECK-V83A-NEXT: .cfi_negate_ra_state +; CHECK-V83A-NEXT: autiasp ; CHECK-V83A-NEXT: .cfi_restore w30 ; CHECK-V83A-NEXT: b _Z3bari ; CHECK-V83A-NEXT: .LBB1_2: // %if.else @@ -143,8 +143,8 @@ return: ; preds = %if.else, %if.then define hidden noundef i32 @baz_sync(i32 noundef %a) #0 uwtable(sync) { ; CHECK-V8A-LABEL: baz_sync: ; CHECK-V8A: // %bb.0: // %entry -; CHECK-V8A-NEXT: hint #25 ; CHECK-V8A-NEXT: .cfi_negate_ra_state +; CHECK-V8A-NEXT: hint #25 ; CHECK-V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-V8A-NEXT: .cfi_def_cfa_offset 16 ; CHECK-V8A-NEXT: .cfi_offset w30, -16 @@ -164,8 +164,8 @@ define hidden noundef i32 @baz_sync(i32 noundef %a) #0 uwtable(sync) { ; ; CHECK-V83A-LABEL: baz_sync: ; CHECK-V83A: // %bb.0: // %entry -; CHECK-V83A-NEXT: paciasp ; CHECK-V83A-NEXT: .cfi_negate_ra_state +; CHECK-V83A-NEXT: paciasp ; CHECK-V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-V83A-NEXT: .cfi_def_cfa_offset 16 ; CHECK-V83A-NEXT: .cfi_offset w30, -16 @@ -216,7 +216,7 @@ attributes #0 = { "sign-return-address"="all" } ; CHECK-DUMP-NOT: DW_CFA_remember_state ; CHECK-DUMP-NOT: DW_CFA_restore_state -; CHECK-DUMP: CFA=WSP{{$}} +; CHECK-DUMP: CFA=WSP ; CHECK-DUMP: reg34=1 ; CHECK-DUMP-NOT: reg34=0 @@ -229,6 +229,7 @@ attributes #0 = { "sign-return-address"="all" } ; CHECK-DUMP: DW_CFA_restore_state: ; CHECK-DUMP: DW_CFA_AARCH64_negate_ra_state: +; CHECK-DUMP: CFA=WSP ;; First DW_CFA_AARCH64_negate_ra_state: ; CHECK-DUMP: reg34=1 ;; Second DW_CFA_AARCH64_negate_ra_state: @@ -237,7 +238,6 @@ attributes #0 = { "sign-return-address"="all" } ; CHECK-DUMP: reg34=1 ;; Third DW_CFA_AARCH64_negate_ra_state: ; CHECK-DUMP: reg34=0 -; CHECK-DUMP-NOT: reg34=1 ; baz_sync ; CHECK-DUMP-LABEL: FDE @@ -246,6 +246,6 @@ attributes #0 = { "sign-return-address"="all" } ; CHECK-DUMP-NOT: DW_CFA_remember_state ; CHECK-DUMP-NOT: DW_CFA_restore_state -; CHECK-DUMP: CFA=WSP{{$}} +; CHECK-DUMP: CFA=WSP ; CHECK-DUMP: reg34=1 ; CHECK-DUMP-NOT: reg34=0 diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll index fa689d2b9d7f..f37f12246e24 100644 --- a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll +++ b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll @@ -60,9 +60,9 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr ; COMPAT-LABEL: leaf_sign_all: ; COMPAT: // %bb.0: ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp0: ; COMPAT-NEXT: hint #25 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: adrp x16, .Ltmp0 ; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp0 ; COMPAT-NEXT: hint #39 @@ -72,9 +72,9 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr ; V83A-LABEL: leaf_sign_all: ; V83A: // %bb.0: ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp0: ; V83A-NEXT: paciasp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: adrp x16, .Ltmp0 ; V83A-NEXT: add x16, x16, :lo12:.Ltmp0 ; V83A-NEXT: hint #39 @@ -82,9 +82,9 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr ; ; PAUTHLR-LABEL: leaf_sign_all: ; PAUTHLR: // %bb.0: +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp0: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp0 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp0 ; PAUTHLR-NEXT: retaasppc .Ltmp0 @@ -95,9 +95,9 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a ; COMPAT-LABEL: leaf_clobbers_lr: ; COMPAT: // %bb.0: ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp1: ; COMPAT-NEXT: hint #25 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -114,9 +114,9 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a ; V83A-LABEL: leaf_clobbers_lr: ; V83A: // %bb.0: ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp1: ; V83A-NEXT: paciasp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -131,9 +131,9 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a ; ; PAUTHLR-LABEL: leaf_clobbers_lr: ; PAUTHLR: // %bb.0: +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp1: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; PAUTHLR-NEXT: .cfi_def_cfa_offset 16 ; PAUTHLR-NEXT: .cfi_offset w30, -16 @@ -154,9 +154,9 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return- ; COMPAT-LABEL: non_leaf_sign_all: ; COMPAT: // %bb.0: ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp2: ; COMPAT-NEXT: hint #25 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -171,9 +171,9 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return- ; V83A-LABEL: non_leaf_sign_all: ; V83A: // %bb.0: ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp2: ; V83A-NEXT: paciasp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -186,9 +186,9 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return- ; ; PAUTHLR-LABEL: non_leaf_sign_all: ; PAUTHLR: // %bb.0: +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp2: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; PAUTHLR-NEXT: .cfi_def_cfa_offset 16 ; PAUTHLR-NEXT: .cfi_offset w30, -16 @@ -205,9 +205,9 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re ; COMPAT-LABEL: non_leaf_sign_non_leaf: ; COMPAT: // %bb.0: ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp3: ; COMPAT-NEXT: hint #25 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -222,9 +222,9 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re ; V83A-LABEL: non_leaf_sign_non_leaf: ; V83A: // %bb.0: ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp3: ; V83A-NEXT: paciasp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -237,9 +237,9 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re ; ; PAUTHLR-LABEL: non_leaf_sign_non_leaf: ; PAUTHLR: // %bb.0: +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp3: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; PAUTHLR-NEXT: .cfi_def_cfa_offset 16 ; PAUTHLR-NEXT: .cfi_offset w30, -16 @@ -259,9 +259,9 @@ define i32 @non_leaf_scs(i32 %x) "branch-protection-pauth-lr" "sign-return-addre ; CHECK-NEXT: str x30, [x18], #8 ; CHECK-NEXT: .cfi_escape 0x16, 0x12, 0x02, 0x82, 0x78 // ; CHECK-NEXT: hint #39 +; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: .Ltmp4: ; CHECK-NEXT: paciasp -; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_offset w30, -16 @@ -278,9 +278,9 @@ define i32 @non_leaf_scs(i32 %x) "branch-protection-pauth-lr" "sign-return-addre ; PAUTHLR: // %bb.0: ; PAUTHLR-NEXT: str x30, [x18], #8 ; PAUTHLR-NEXT: .cfi_escape 0x16, 0x12, 0x02, 0x82, 0x78 // +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp4: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; PAUTHLR-NEXT: .cfi_def_cfa_offset 16 ; PAUTHLR-NEXT: .cfi_offset w30, -16 @@ -299,9 +299,9 @@ define i32 @leaf_sign_all_v83(i32 %x) "branch-protection-pauth-lr" "sign-return- ; CHECK-LABEL: leaf_sign_all_v83: ; CHECK: // %bb.0: ; CHECK-NEXT: hint #39 +; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: .Ltmp5: ; CHECK-NEXT: paciasp -; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: adrp x16, .Ltmp5 ; CHECK-NEXT: add x16, x16, :lo12:.Ltmp5 ; CHECK-NEXT: hint #39 @@ -309,9 +309,9 @@ define i32 @leaf_sign_all_v83(i32 %x) "branch-protection-pauth-lr" "sign-return- ; ; PAUTHLR-LABEL: leaf_sign_all_v83: ; PAUTHLR: // %bb.0: +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp5: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp5 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp5 ; PAUTHLR-NEXT: retaasppc .Ltmp5 @@ -324,9 +324,9 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr" ; COMPAT-LABEL: spill_lr_and_tail_call: ; COMPAT: // %bb.0: ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp6: ; COMPAT-NEXT: hint #25 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -343,9 +343,9 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr" ; V83A-LABEL: spill_lr_and_tail_call: ; V83A: // %bb.0: ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp6: ; V83A-NEXT: paciasp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -361,9 +361,9 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr" ; ; PAUTHLR-LABEL: spill_lr_and_tail_call: ; PAUTHLR: // %bb.0: +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp6: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; PAUTHLR-NEXT: .cfi_def_cfa_offset 16 ; PAUTHLR-NEXT: .cfi_offset w30, -16 @@ -384,9 +384,9 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur ; COMPAT-LABEL: leaf_sign_all_a_key: ; COMPAT: // %bb.0: ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp7: ; COMPAT-NEXT: hint #25 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: adrp x16, .Ltmp7 ; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp7 ; COMPAT-NEXT: hint #39 @@ -396,9 +396,9 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur ; V83A-LABEL: leaf_sign_all_a_key: ; V83A: // %bb.0: ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp7: ; V83A-NEXT: paciasp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: adrp x16, .Ltmp7 ; V83A-NEXT: add x16, x16, :lo12:.Ltmp7 ; V83A-NEXT: hint #39 @@ -406,9 +406,9 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur ; ; PAUTHLR-LABEL: leaf_sign_all_a_key: ; PAUTHLR: // %bb.0: +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp7: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp7 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp7 ; PAUTHLR-NEXT: retaasppc .Ltmp7 @@ -420,9 +420,9 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur ; COMPAT: // %bb.0: ; COMPAT-NEXT: .cfi_b_key_frame ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp8: ; COMPAT-NEXT: hint #27 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: adrp x16, .Ltmp8 ; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp8 ; COMPAT-NEXT: hint #39 @@ -433,9 +433,9 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur ; V83A: // %bb.0: ; V83A-NEXT: .cfi_b_key_frame ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp8: ; V83A-NEXT: pacibsp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: adrp x16, .Ltmp8 ; V83A-NEXT: add x16, x16, :lo12:.Ltmp8 ; V83A-NEXT: hint #39 @@ -444,9 +444,9 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur ; PAUTHLR-LABEL: leaf_sign_all_b_key: ; PAUTHLR: // %bb.0: ; PAUTHLR-NEXT: .cfi_b_key_frame +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp8: ; PAUTHLR-NEXT: pacibsppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp8 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp8 ; PAUTHLR-NEXT: retabsppc .Ltmp8 @@ -458,9 +458,9 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "branch-protection-pauth-lr" "sign-r ; CHECK: // %bb.0: ; CHECK-NEXT: .cfi_b_key_frame ; CHECK-NEXT: hint #39 +; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: .Ltmp9: ; CHECK-NEXT: pacibsp -; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: adrp x16, .Ltmp9 ; CHECK-NEXT: add x16, x16, :lo12:.Ltmp9 ; CHECK-NEXT: hint #39 @@ -469,9 +469,9 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "branch-protection-pauth-lr" "sign-r ; PAUTHLR-LABEL: leaf_sign_all_v83_b_key: ; PAUTHLR: // %bb.0: ; PAUTHLR-NEXT: .cfi_b_key_frame +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp9: ; PAUTHLR-NEXT: pacibsppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp9 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp9 ; PAUTHLR-NEXT: retabsppc .Ltmp9 @@ -484,9 +484,9 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r ; COMPAT: // %bb.0: ; COMPAT-NEXT: hint #34 ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp10: ; COMPAT-NEXT: hint #25 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: adrp x16, .Ltmp10 ; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp10 ; COMPAT-NEXT: hint #39 @@ -497,9 +497,9 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r ; V83A: // %bb.0: ; V83A-NEXT: hint #34 ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp10: ; V83A-NEXT: paciasp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: adrp x16, .Ltmp10 ; V83A-NEXT: add x16, x16, :lo12:.Ltmp10 ; V83A-NEXT: hint #39 @@ -508,9 +508,9 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r ; PAUTHLR-LABEL: leaf_sign_all_a_key_bti: ; PAUTHLR: // %bb.0: ; PAUTHLR-NEXT: bti c +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp10: ; PAUTHLR-NEXT: paciasppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp10 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp10 ; PAUTHLR-NEXT: retaasppc .Ltmp10 @@ -524,9 +524,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r ; COMPAT-NEXT: hint #34 ; COMPAT-NEXT: .cfi_b_key_frame ; COMPAT-NEXT: hint #39 +; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: .Ltmp11: ; COMPAT-NEXT: hint #27 -; COMPAT-NEXT: .cfi_negate_ra_state_with_pc ; COMPAT-NEXT: adrp x16, .Ltmp11 ; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp11 ; COMPAT-NEXT: hint #39 @@ -538,9 +538,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r ; V83A-NEXT: hint #34 ; V83A-NEXT: .cfi_b_key_frame ; V83A-NEXT: hint #39 +; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: .Ltmp11: ; V83A-NEXT: pacibsp -; V83A-NEXT: .cfi_negate_ra_state_with_pc ; V83A-NEXT: adrp x16, .Ltmp11 ; V83A-NEXT: add x16, x16, :lo12:.Ltmp11 ; V83A-NEXT: hint #39 @@ -550,9 +550,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r ; PAUTHLR: // %bb.0: ; PAUTHLR-NEXT: bti c ; PAUTHLR-NEXT: .cfi_b_key_frame +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp11: ; PAUTHLR-NEXT: pacibsppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp11 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp11 ; PAUTHLR-NEXT: retabsppc .Ltmp11 @@ -566,9 +566,9 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "si ; CHECK-NEXT: hint #34 ; CHECK-NEXT: .cfi_b_key_frame ; CHECK-NEXT: hint #39 +; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: .Ltmp12: ; CHECK-NEXT: pacibsp -; CHECK-NEXT: .cfi_negate_ra_state_with_pc ; CHECK-NEXT: adrp x16, .Ltmp12 ; CHECK-NEXT: add x16, x16, :lo12:.Ltmp12 ; CHECK-NEXT: hint #39 @@ -578,9 +578,9 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "si ; PAUTHLR: // %bb.0: ; PAUTHLR-NEXT: bti c ; PAUTHLR-NEXT: .cfi_b_key_frame +; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: .Ltmp12: ; PAUTHLR-NEXT: pacibsppc -; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc ; PAUTHLR-NEXT: adrp x16, .Ltmp12 ; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp12 ; PAUTHLR-NEXT: retabsppc .Ltmp12 diff --git a/llvm/test/CodeGen/AArch64/sign-return-address.ll b/llvm/test/CodeGen/AArch64/sign-return-address.ll index dafe0d71ceb5..e0ee0d84ab4f 100644 --- a/llvm/test/CodeGen/AArch64/sign-return-address.ll +++ b/llvm/test/CodeGen/AArch64/sign-return-address.ll @@ -29,15 +29,15 @@ define i32 @leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" { define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" { ; COMPAT-LABEL: leaf_sign_all: ; COMPAT: // %bb.0: -; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: hint #29 ; COMPAT-NEXT: ret ; ; V83A-LABEL: leaf_sign_all: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: retaa ret i32 %x } @@ -45,8 +45,8 @@ define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" { define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf" { ; COMPAT-LABEL: leaf_clobbers_lr: ; COMPAT: // %bb.0: -; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -59,8 +59,8 @@ define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf" { ; ; V83A-LABEL: leaf_clobbers_lr: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -78,8 +78,8 @@ declare i32 @foo(i32) define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" { ; COMPAT-LABEL: non_leaf_sign_all: ; COMPAT: // %bb.0: -; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -90,8 +90,8 @@ define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" { ; ; V83A-LABEL: non_leaf_sign_all: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -105,8 +105,8 @@ define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" { define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" { ; COMPAT-LABEL: non_leaf_sign_non_leaf: ; COMPAT: // %bb.0: -; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -117,8 +117,8 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" { ; ; V83A-LABEL: non_leaf_sign_non_leaf: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -135,8 +135,8 @@ define i32 @non_leaf_scs(i32 %x) "sign-return-address"="non-leaf" shadowcallstac ; CHECK: // %bb.0: ; CHECK-NEXT: str x30, [x18], #8 ; CHECK-NEXT: .cfi_escape 0x16, 0x12, 0x02, 0x82, 0x78 // -; CHECK-NEXT: paciasp ; CHECK-NEXT: .cfi_negate_ra_state +; CHECK-NEXT: paciasp ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_offset w30, -16 @@ -152,8 +152,8 @@ define i32 @non_leaf_scs(i32 %x) "sign-return-address"="non-leaf" shadowcallstac define i32 @leaf_sign_all_v83(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" { ; CHECK-LABEL: leaf_sign_all_v83: ; CHECK: // %bb.0: -; CHECK-NEXT: paciasp ; CHECK-NEXT: .cfi_negate_ra_state +; CHECK-NEXT: paciasp ; CHECK-NEXT: retaa ret i32 %x } @@ -163,8 +163,8 @@ declare fastcc i64 @bar(i64) define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" { ; COMPAT-LABEL: spill_lr_and_tail_call: ; COMPAT: // %bb.0: -; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; COMPAT-NEXT: .cfi_def_cfa_offset 16 ; COMPAT-NEXT: .cfi_offset w30, -16 @@ -177,8 +177,8 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" { ; ; V83A-LABEL: spill_lr_and_tail_call: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; V83A-NEXT: .cfi_def_cfa_offset 16 ; V83A-NEXT: .cfi_offset w30, -16 @@ -196,15 +196,15 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" { define i32 @leaf_sign_all_a_key(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" { ; COMPAT-LABEL: leaf_sign_all_a_key: ; COMPAT: // %bb.0: -; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: hint #29 ; COMPAT-NEXT: ret ; ; V83A-LABEL: leaf_sign_all_a_key: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: retaa ret i32 %x } @@ -213,16 +213,16 @@ define i32 @leaf_sign_all_b_key(i32 %x) "sign-return-address"="all" "sign-return ; COMPAT-LABEL: leaf_sign_all_b_key: ; COMPAT: // %bb.0: ; COMPAT-NEXT: .cfi_b_key_frame -; COMPAT-NEXT: hint #27 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #27 ; COMPAT-NEXT: hint #31 ; COMPAT-NEXT: ret ; ; V83A-LABEL: leaf_sign_all_b_key: ; V83A: // %bb.0: ; V83A-NEXT: .cfi_b_key_frame -; V83A-NEXT: pacibsp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: pacibsp ; V83A-NEXT: retab ret i32 %x } @@ -231,8 +231,8 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "sign-return-address"="all" "target- ; CHECK-LABEL: leaf_sign_all_v83_b_key: ; CHECK: // %bb.0: ; CHECK-NEXT: .cfi_b_key_frame -; CHECK-NEXT: pacibsp ; CHECK-NEXT: .cfi_negate_ra_state +; CHECK-NEXT: pacibsp ; CHECK-NEXT: retab ret i32 %x } @@ -241,15 +241,15 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "sign-return-address"="all" "target- define i32 @leaf_sign_all_a_key_bti(i32 %x) "sign-return-address"="all" "sign-return-address-key"="a_key" "branch-target-enforcement"{ ; COMPAT-LABEL: leaf_sign_all_a_key_bti: ; COMPAT: // %bb.0: -; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #25 ; COMPAT-NEXT: hint #29 ; COMPAT-NEXT: ret ; ; V83A-LABEL: leaf_sign_all_a_key_bti: ; V83A: // %bb.0: -; V83A-NEXT: paciasp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: paciasp ; V83A-NEXT: retaa ret i32 %x } @@ -259,16 +259,16 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "sign-return-address"="all" "sign-re ; COMPAT-LABEL: leaf_sign_all_b_key_bti: ; COMPAT: // %bb.0: ; COMPAT-NEXT: .cfi_b_key_frame -; COMPAT-NEXT: hint #27 ; COMPAT-NEXT: .cfi_negate_ra_state +; COMPAT-NEXT: hint #27 ; COMPAT-NEXT: hint #31 ; COMPAT-NEXT: ret ; ; V83A-LABEL: leaf_sign_all_b_key_bti: ; V83A: // %bb.0: ; V83A-NEXT: .cfi_b_key_frame -; V83A-NEXT: pacibsp ; V83A-NEXT: .cfi_negate_ra_state +; V83A-NEXT: pacibsp ; V83A-NEXT: retab ret i32 %x } @@ -278,8 +278,8 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "sign-return-address"="all" "tar ; CHECK-LABEL: leaf_sign_all_v83_b_key_bti: ; CHECK: // %bb.0: ; CHECK-NEXT: .cfi_b_key_frame -; CHECK-NEXT: pacibsp ; CHECK-NEXT: .cfi_negate_ra_state +; CHECK-NEXT: pacibsp ; CHECK-NEXT: retab ret i32 %x } diff --git a/llvm/test/CodeGen/AArch64/sme-intrinsics-state.ll b/llvm/test/CodeGen/AArch64/sme-intrinsics-state.ll new file mode 100644 index 000000000000..5037772a51ce --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme-intrinsics-state.ll @@ -0,0 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s + + +define i1 @streaming_mode_streaming_compatible() #0 { +; CHECK-LABEL: streaming_mode_streaming_compatible: +; CHECK: // %bb.0: +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: bl __arm_sme_state +; CHECK-NEXT: and w0, w0, #0x1 +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret + %mode = tail call noundef i1 @llvm.aarch64.sme.in.streaming.mode() + ret i1 %mode +} + + +attributes #0 = {nounwind memory(none) "aarch64_pstate_sm_compatible"} diff --git a/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll b/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll index 66d6e0388bbf..66f83c658ff4 100644 --- a/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll +++ b/llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll @@ -316,6 +316,84 @@ entry: ret <vscale x 4 x i64> %partial.reduce } +define <vscale x 4 x i32> @udot_no_bin_op(<vscale x 4 x i32> %acc, <vscale x 16 x i8> %a){ +; CHECK-LABEL: udot_no_bin_op: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z2.b, #1 // =0x1 +; CHECK-NEXT: udot z0.s, z1.b, z2.b +; CHECK-NEXT: ret + %a.ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i32> + %partial.reduce = tail call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %acc, <vscale x 16 x i32> %a.ext) + ret <vscale x 4 x i32> %partial.reduce +} + +define <vscale x 4 x i32> @sdot_no_bin_op(<vscale x 4 x i32> %acc, <vscale x 16 x i8> %a){ +; CHECK-LABEL: sdot_no_bin_op: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z2.b, #1 // =0x1 +; CHECK-NEXT: sdot z0.s, z1.b, z2.b +; CHECK-NEXT: ret + %a.ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i32> + %partial.reduce = tail call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv16i32(<vscale x 4 x i32> %acc, <vscale x 16 x i32> %a.ext) + ret <vscale x 4 x i32> %partial.reduce +} + +define <vscale x 2 x i64> @udot_no_bin_op_wide(<vscale x 2 x i64> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ +; CHECK-LABEL: udot_no_bin_op_wide: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov z2.h, #1 // =0x1 +; CHECK-NEXT: udot z0.d, z1.h, z2.h +; CHECK-NEXT: ret +entry: + %a.wide = zext <vscale x 8 x i16> %a to <vscale x 8 x i64> + %partial.reduce = tail call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %acc, <vscale x 8 x i64> %a.wide) + ret <vscale x 2 x i64> %partial.reduce +} + +define <vscale x 2 x i64> @sdot_no_bin_op_wide(<vscale x 2 x i64> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ +; CHECK-LABEL: sdot_no_bin_op_wide: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov z2.h, #1 // =0x1 +; CHECK-NEXT: sdot z0.d, z1.h, z2.h +; CHECK-NEXT: ret +entry: + %a.wide = sext <vscale x 8 x i16> %a to <vscale x 8 x i64> + %partial.reduce = tail call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %acc, <vscale x 8 x i64> %a.wide) + ret <vscale x 2 x i64> %partial.reduce +} + +define <vscale x 4 x i64> @udot_no_bin_op_8to64(<vscale x 4 x i64> %acc, <vscale x 16 x i8> %a){ +; CHECK-LABEL: udot_no_bin_op_8to64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z3.b, #1 // =0x1 +; CHECK-NEXT: mov z4.s, #0 // =0x0 +; CHECK-NEXT: udot z4.s, z2.b, z3.b +; CHECK-NEXT: sunpklo z2.d, z4.s +; CHECK-NEXT: sunpkhi z3.d, z4.s +; CHECK-NEXT: add z0.d, z0.d, z2.d +; CHECK-NEXT: add z1.d, z1.d, z3.d +; CHECK-NEXT: ret + %a.ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i64> + %partial.reduce = tail call <vscale x 4 x i64> @llvm.experimental.vector.partial.reduce.add.nxv4i64.nxv16i64(<vscale x 4 x i64> %acc, <vscale x 16 x i64> %a.ext) + ret <vscale x 4 x i64> %partial.reduce +} + +define <vscale x 4 x i64> @sdot_no_bin_op_8to64(<vscale x 4 x i64> %acc, <vscale x 16 x i8> %a){ +; CHECK-LABEL: sdot_no_bin_op_8to64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z3.b, #1 // =0x1 +; CHECK-NEXT: mov z4.s, #0 // =0x0 +; CHECK-NEXT: sdot z4.s, z2.b, z3.b +; CHECK-NEXT: sunpklo z2.d, z4.s +; CHECK-NEXT: sunpkhi z3.d, z4.s +; CHECK-NEXT: add z0.d, z0.d, z2.d +; CHECK-NEXT: add z1.d, z1.d, z3.d +; CHECK-NEXT: ret + %a.ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i64> + %partial.reduce = tail call <vscale x 4 x i64> @llvm.experimental.vector.partial.reduce.add.nxv4i64.nxv16i64(<vscale x 4 x i64> %acc, <vscale x 16 x i64> %a.ext) + ret <vscale x 4 x i64> %partial.reduce +} + define <vscale x 4 x i32> @not_udot(<vscale x 4 x i32> %acc, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { ; CHECK-LABEL: not_udot: ; CHECK: // %bb.0: // %entry @@ -419,3 +497,133 @@ entry: %partial.reduce = tail call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %acc, <vscale x 8 x i64> %mult) ret <vscale x 2 x i64> %partial.reduce } + +define <vscale x 2 x i64> @udot_different_types(<vscale x 2 x i64> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i8> %b){ +; CHECK-LABEL: udot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: and z2.h, z2.h, #0xff +; CHECK-NEXT: uunpklo z3.s, z1.h +; CHECK-NEXT: uunpkhi z1.s, z1.h +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: uunpklo z4.s, z2.h +; CHECK-NEXT: uunpkhi z2.s, z2.h +; CHECK-NEXT: uunpklo z5.d, z3.s +; CHECK-NEXT: uunpkhi z3.d, z3.s +; CHECK-NEXT: uunpklo z7.d, z1.s +; CHECK-NEXT: uunpkhi z1.d, z1.s +; CHECK-NEXT: uunpklo z6.d, z4.s +; CHECK-NEXT: uunpkhi z4.d, z4.s +; CHECK-NEXT: uunpklo z24.d, z2.s +; CHECK-NEXT: uunpkhi z2.d, z2.s +; CHECK-NEXT: mul z3.d, z3.d, z4.d +; CHECK-NEXT: mla z0.d, p0/m, z5.d, z6.d +; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d +; CHECK-NEXT: movprfx z1, z3 +; CHECK-NEXT: mla z1.d, p0/m, z7.d, z24.d +; CHECK-NEXT: add z0.d, z1.d, z0.d +; CHECK-NEXT: ret +entry: + %a.wide = zext <vscale x 8 x i16> %a to <vscale x 8 x i64> + %b.wide = zext <vscale x 8 x i8> %b to <vscale x 8 x i64> + %mult = mul nuw nsw <vscale x 8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %acc, <vscale x 8 x i64> %mult) + ret <vscale x 2 x i64> %partial.reduce +} + +define <vscale x 2 x i64> @sdot_different_types(<vscale x 2 x i64> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i8> %b){ +; CHECK-LABEL: sdot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: sunpklo z3.s, z1.h +; CHECK-NEXT: sunpkhi z1.s, z1.h +; CHECK-NEXT: sxtb z2.h, p0/m, z2.h +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: sunpklo z5.d, z3.s +; CHECK-NEXT: sunpkhi z3.d, z3.s +; CHECK-NEXT: sunpklo z7.d, z1.s +; CHECK-NEXT: sunpklo z4.s, z2.h +; CHECK-NEXT: sunpkhi z2.s, z2.h +; CHECK-NEXT: sunpkhi z1.d, z1.s +; CHECK-NEXT: sunpklo z6.d, z4.s +; CHECK-NEXT: sunpkhi z4.d, z4.s +; CHECK-NEXT: sunpklo z24.d, z2.s +; CHECK-NEXT: sunpkhi z2.d, z2.s +; CHECK-NEXT: mul z3.d, z3.d, z4.d +; CHECK-NEXT: mla z0.d, p0/m, z5.d, z6.d +; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d +; CHECK-NEXT: movprfx z1, z3 +; CHECK-NEXT: mla z1.d, p0/m, z7.d, z24.d +; CHECK-NEXT: add z0.d, z1.d, z0.d +; CHECK-NEXT: ret +entry: + %a.wide = sext <vscale x 8 x i16> %a to <vscale x 8 x i64> + %b.wide = sext <vscale x 8 x i8> %b to <vscale x 8 x i64> + %mult = mul nuw nsw <vscale x 8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %acc, <vscale x 8 x i64> %mult) + ret <vscale x 2 x i64> %partial.reduce +} + +define <vscale x 2 x i64> @usdot_different_types(<vscale x 2 x i64> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i8> %b){ +; CHECK-LABEL: usdot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ptrue p0.h +; CHECK-NEXT: uunpklo z3.s, z1.h +; CHECK-NEXT: uunpkhi z1.s, z1.h +; CHECK-NEXT: sxtb z2.h, p0/m, z2.h +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: uunpklo z5.d, z3.s +; CHECK-NEXT: uunpkhi z3.d, z3.s +; CHECK-NEXT: uunpklo z7.d, z1.s +; CHECK-NEXT: sunpklo z4.s, z2.h +; CHECK-NEXT: sunpkhi z2.s, z2.h +; CHECK-NEXT: uunpkhi z1.d, z1.s +; CHECK-NEXT: sunpklo z6.d, z4.s +; CHECK-NEXT: sunpkhi z4.d, z4.s +; CHECK-NEXT: sunpklo z24.d, z2.s +; CHECK-NEXT: sunpkhi z2.d, z2.s +; CHECK-NEXT: mul z3.d, z3.d, z4.d +; CHECK-NEXT: mla z0.d, p0/m, z5.d, z6.d +; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d +; CHECK-NEXT: movprfx z1, z3 +; CHECK-NEXT: mla z1.d, p0/m, z7.d, z24.d +; CHECK-NEXT: add z0.d, z1.d, z0.d +; CHECK-NEXT: ret +entry: + %a.wide = zext <vscale x 8 x i16> %a to <vscale x 8 x i64> + %b.wide = sext <vscale x 8 x i8> %b to <vscale x 8 x i64> + %mult = mul nuw nsw <vscale x 8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %acc, <vscale x 8 x i64> %mult) + ret <vscale x 2 x i64> %partial.reduce +} + +define <vscale x 2 x i64> @sudot_different_types(<vscale x 2 x i64> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i8> %b){ +; CHECK-LABEL: sudot_different_types: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: and z2.h, z2.h, #0xff +; CHECK-NEXT: sunpklo z3.s, z1.h +; CHECK-NEXT: sunpkhi z1.s, z1.h +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: uunpklo z4.s, z2.h +; CHECK-NEXT: uunpkhi z2.s, z2.h +; CHECK-NEXT: sunpklo z5.d, z3.s +; CHECK-NEXT: sunpkhi z3.d, z3.s +; CHECK-NEXT: sunpklo z7.d, z1.s +; CHECK-NEXT: sunpkhi z1.d, z1.s +; CHECK-NEXT: uunpklo z6.d, z4.s +; CHECK-NEXT: uunpkhi z4.d, z4.s +; CHECK-NEXT: uunpklo z24.d, z2.s +; CHECK-NEXT: uunpkhi z2.d, z2.s +; CHECK-NEXT: mul z3.d, z3.d, z4.d +; CHECK-NEXT: mla z0.d, p0/m, z5.d, z6.d +; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d +; CHECK-NEXT: movprfx z1, z3 +; CHECK-NEXT: mla z1.d, p0/m, z7.d, z24.d +; CHECK-NEXT: add z0.d, z1.d, z0.d +; CHECK-NEXT: ret +entry: + %a.wide = sext <vscale x 8 x i16> %a to <vscale x 8 x i64> + %b.wide = zext <vscale x 8 x i8> %b to <vscale x 8 x i64> + %mult = mul nuw nsw <vscale x 8 x i64> %a.wide, %b.wide + %partial.reduce = tail call <vscale x 2 x i64> @llvm.experimental.vector.partial.reduce.add.nxv2i64.nxv8i64(<vscale x 2 x i64> %acc, <vscale x 8 x i64> %mult) + ret <vscale x 2 x i64> %partial.reduce +} diff --git a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll index 7f2eefe5ed72..7f3c1fdc9338 100644 --- a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll +++ b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll @@ -1,26 +1,86 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,SDAG +; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -aarch64-enable-collect-loh=false -global-isel -global-isel-abort=2 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL ; Basic tests from input vector to bitmask ; IR generated from clang for: ; __builtin_convertvector + reinterpret_cast<uint16&> +; GISEL: warning: Instruction selection used fallback path for clang_builtins_undef_concat_convert_to_bitmask4 +; GISEL-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_2xi32 +; GISEL-NEXT: warning: Instruction selection used fallback path for convert_to_bitmask_8xi2 +; GISEL-NEXT: warning: Instruction selection used fallback path for no_direct_convert_for_bad_concat + define i16 @convert_to_bitmask16(<16 x i8> %vec) { ; Bits used in mask -; CHECK-LABEL: convert_to_bitmask16: -; CHECK: ; %bb.0: -; CHECK-NEXT: Lloh0: -; CHECK-NEXT: adrp x8, lCPI0_0@PAGE -; CHECK-NEXT: cmeq.16b v0, v0, #0 -; CHECK-NEXT: Lloh1: -; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF] -; CHECK-NEXT: bic.16b v0, v1, v0 -; CHECK-NEXT: ext.16b v1, v0, v0, #8 -; CHECK-NEXT: zip1.16b v0, v0, v1 -; CHECK-NEXT: addv.8h h0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1 +; SDAG-LABEL: convert_to_bitmask16: +; SDAG: ; %bb.0: +; SDAG-NEXT: adrp x8, lCPI0_0@PAGE +; SDAG-NEXT: cmeq.16b v0, v0, #0 +; SDAG-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF] +; SDAG-NEXT: bic.16b v0, v1, v0 +; SDAG-NEXT: ext.16b v1, v0, v0, #8 +; SDAG-NEXT: zip1.16b v0, v0, v1 +; SDAG-NEXT: addv.8h h0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask16: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: cmeq.16b v0, v0, #0 +; GISEL-NEXT: mvn.16b v0, v0 +; GISEL-NEXT: umov.b w8, v0[1] +; GISEL-NEXT: umov.b w9, v0[0] +; GISEL-NEXT: umov.b w10, v0[2] +; GISEL-NEXT: umov.b w11, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w9, w8, #1, #31 +; GISEL-NEXT: and w8, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[4] +; GISEL-NEXT: orr w8, w9, w8, lsl #2 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[5] +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[6] +; GISEL-NEXT: orr w8, w8, w9, lsl #4 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[7] +; GISEL-NEXT: orr w8, w8, w9, lsl #5 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[8] +; GISEL-NEXT: orr w8, w8, w9, lsl #6 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[9] +; GISEL-NEXT: orr w8, w8, w9, lsl #7 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[10] +; GISEL-NEXT: orr w8, w8, w9, lsl #8 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[11] +; GISEL-NEXT: orr w8, w8, w9, lsl #9 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[12] +; GISEL-NEXT: orr w8, w8, w9, lsl #10 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[13] +; GISEL-NEXT: orr w8, w8, w9, lsl #11 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[14] +; GISEL-NEXT: orr w8, w8, w9, lsl #12 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[15] +; GISEL-NEXT: orr w8, w8, w9, lsl #13 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #14 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #15 +; GISEL-NEXT: strh w8, [sp, #14] +; GISEL-NEXT: and w0, w8, #0xffff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret ; Actual conversion @@ -30,19 +90,50 @@ define i16 @convert_to_bitmask16(<16 x i8> %vec) { } define i16 @convert_to_bitmask8(<8 x i16> %vec) { -; CHECK-LABEL: convert_to_bitmask8: -; CHECK: ; %bb.0: -; CHECK-NEXT: Lloh2: -; CHECK-NEXT: adrp x8, lCPI1_0@PAGE -; CHECK-NEXT: cmeq.8h v0, v0, #0 -; CHECK-NEXT: Lloh3: -; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF] -; CHECK-NEXT: bic.16b v0, v1, v0 -; CHECK-NEXT: addv.8h h0, v0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: and w0, w8, #0xff -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3 +; SDAG-LABEL: convert_to_bitmask8: +; SDAG: ; %bb.0: +; SDAG-NEXT: adrp x8, lCPI1_0@PAGE +; SDAG-NEXT: cmeq.8h v0, v0, #0 +; SDAG-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF] +; SDAG-NEXT: bic.16b v0, v1, v0 +; SDAG-NEXT: addv.8h h0, v0 +; SDAG-NEXT: fmov w8, s0 +; SDAG-NEXT: and w0, w8, #0xff +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask8: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: cmeq.8h v0, v0, #0 +; GISEL-NEXT: mvn.16b v0, v0 +; GISEL-NEXT: xtn.8b v0, v0 +; GISEL-NEXT: umov.b w8, v0[1] +; GISEL-NEXT: umov.b w9, v0[0] +; GISEL-NEXT: umov.b w10, v0[2] +; GISEL-NEXT: umov.b w11, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w9, w8, #1, #31 +; GISEL-NEXT: and w8, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[4] +; GISEL-NEXT: orr w8, w9, w8, lsl #2 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[5] +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[6] +; GISEL-NEXT: orr w8, w8, w9, lsl #4 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[7] +; GISEL-NEXT: orr w8, w8, w9, lsl #5 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #6 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #7 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer @@ -52,18 +143,36 @@ define i16 @convert_to_bitmask8(<8 x i16> %vec) { } define i4 @convert_to_bitmask4(<4 x i32> %vec) { -; CHECK-LABEL: convert_to_bitmask4: -; CHECK: ; %bb.0: -; CHECK-NEXT: Lloh4: -; CHECK-NEXT: adrp x8, lCPI2_0@PAGE -; CHECK-NEXT: cmeq.4s v0, v0, #0 -; CHECK-NEXT: Lloh5: -; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF] -; CHECK-NEXT: bic.16b v0, v1, v0 -; CHECK-NEXT: addv.4s s0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh5 +; SDAG-LABEL: convert_to_bitmask4: +; SDAG: ; %bb.0: +; SDAG-NEXT: adrp x8, lCPI2_0@PAGE +; SDAG-NEXT: cmeq.4s v0, v0, #0 +; SDAG-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF] +; SDAG-NEXT: bic.16b v0, v1, v0 +; SDAG-NEXT: addv.4s s0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask4: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: cmeq.4s v0, v0, #0 +; GISEL-NEXT: mvn.16b v0, v0 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer @@ -74,17 +183,14 @@ define i4 @convert_to_bitmask4(<4 x i32> %vec) { define i8 @convert_to_bitmask2(<2 x i64> %vec) { ; CHECK-LABEL: convert_to_bitmask2: ; CHECK: ; %bb.0: -; CHECK-NEXT: Lloh6: ; CHECK-NEXT: adrp x8, lCPI3_0@PAGE ; CHECK-NEXT: cmeq.2d v0, v0, #0 -; CHECK-NEXT: Lloh7: ; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF] ; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: addp.2d d0, v0 ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x3 ; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh7 %cmp_result = icmp ne <2 x i64> %vec, zeroinitializer @@ -97,16 +203,13 @@ define i8 @convert_to_bitmask2(<2 x i64> %vec) { define i8 @clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) { ; CHECK-LABEL: clang_builtins_undef_concat_convert_to_bitmask4: ; CHECK: ; %bb.0: -; CHECK-NEXT: Lloh8: ; CHECK-NEXT: adrp x8, lCPI4_0@PAGE ; CHECK-NEXT: cmeq.4s v0, v0, #0 -; CHECK-NEXT: Lloh9: ; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF] ; CHECK-NEXT: bic.16b v0, v1, v0 ; CHECK-NEXT: addv.4s s0, v0 ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh8, Lloh9 %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer @@ -117,20 +220,37 @@ define i8 @clang_builtins_undef_concat_convert_to_bitmask4(<4 x i32> %vec) { define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) { -; CHECK-LABEL: convert_to_bitmask_no_compare: -; CHECK: ; %bb.0: -; CHECK-NEXT: and.16b v0, v0, v1 -; CHECK-NEXT: Lloh10: -; CHECK-NEXT: adrp x8, lCPI5_0@PAGE -; CHECK-NEXT: Lloh11: -; CHECK-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF] -; CHECK-NEXT: shl.4s v0, v0, #31 -; CHECK-NEXT: cmlt.4s v0, v0, #0 -; CHECK-NEXT: and.16b v0, v0, v1 -; CHECK-NEXT: addv.4s s0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh10, Lloh11 +; SDAG-LABEL: convert_to_bitmask_no_compare: +; SDAG: ; %bb.0: +; SDAG-NEXT: and.16b v0, v0, v1 +; SDAG-NEXT: adrp x8, lCPI5_0@PAGE +; SDAG-NEXT: ldr q1, [x8, lCPI5_0@PAGEOFF] +; SDAG-NEXT: shl.4s v0, v0, #31 +; SDAG-NEXT: cmlt.4s v0, v0, #0 +; SDAG-NEXT: and.16b v0, v0, v1 +; SDAG-NEXT: addv.4s s0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_no_compare: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: and.16b v0, v0, v1 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp = and <4 x i32> %vec1, %vec2 @@ -140,20 +260,39 @@ define i4 @convert_to_bitmask_no_compare(<4 x i32> %vec1, <4 x i32> %vec2) { } define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32> %vec2) { -; CHECK-LABEL: convert_to_bitmask_with_compare_chain: -; CHECK: ; %bb.0: -; CHECK-NEXT: cmeq.4s v2, v0, #0 -; CHECK-NEXT: cmeq.4s v0, v0, v1 -; CHECK-NEXT: Lloh12: -; CHECK-NEXT: adrp x8, lCPI6_0@PAGE -; CHECK-NEXT: Lloh13: -; CHECK-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF] -; CHECK-NEXT: bic.16b v0, v0, v2 -; CHECK-NEXT: and.16b v0, v0, v1 -; CHECK-NEXT: addv.4s s0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh12, Lloh13 +; SDAG-LABEL: convert_to_bitmask_with_compare_chain: +; SDAG: ; %bb.0: +; SDAG-NEXT: cmeq.4s v2, v0, #0 +; SDAG-NEXT: cmeq.4s v0, v0, v1 +; SDAG-NEXT: adrp x8, lCPI6_0@PAGE +; SDAG-NEXT: ldr q1, [x8, lCPI6_0@PAGEOFF] +; SDAG-NEXT: bic.16b v0, v0, v2 +; SDAG-NEXT: and.16b v0, v0, v1 +; SDAG-NEXT: addv.4s s0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_with_compare_chain: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: cmeq.4s v2, v0, #0 +; GISEL-NEXT: cmeq.4s v0, v0, v1 +; GISEL-NEXT: bic.16b v0, v0, v2 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer @@ -164,21 +303,39 @@ define i4 @convert_to_bitmask_with_compare_chain(<4 x i32> %vec1, <4 x i32> %vec } define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32> %vec2) { -; CHECK-LABEL: convert_to_bitmask_with_trunc_in_chain: -; CHECK: ; %bb.0: -; CHECK-NEXT: cmeq.4s v0, v0, #0 -; CHECK-NEXT: Lloh14: -; CHECK-NEXT: adrp x8, lCPI7_0@PAGE -; CHECK-NEXT: bic.16b v0, v1, v0 -; CHECK-NEXT: Lloh15: -; CHECK-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF] -; CHECK-NEXT: shl.4s v0, v0, #31 -; CHECK-NEXT: cmlt.4s v0, v0, #0 -; CHECK-NEXT: and.16b v0, v0, v1 -; CHECK-NEXT: addv.4s s0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh14, Lloh15 +; SDAG-LABEL: convert_to_bitmask_with_trunc_in_chain: +; SDAG: ; %bb.0: +; SDAG-NEXT: cmeq.4s v0, v0, #0 +; SDAG-NEXT: adrp x8, lCPI7_0@PAGE +; SDAG-NEXT: bic.16b v0, v1, v0 +; SDAG-NEXT: ldr q1, [x8, lCPI7_0@PAGEOFF] +; SDAG-NEXT: shl.4s v0, v0, #31 +; SDAG-NEXT: cmlt.4s v0, v0, #0 +; SDAG-NEXT: and.16b v0, v0, v1 +; SDAG-NEXT: addv.4s s0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_with_trunc_in_chain: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: cmeq.4s v0, v0, #0 +; GISEL-NEXT: bic.16b v0, v1, v0 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer @@ -189,33 +346,82 @@ define i4 @convert_to_bitmask_with_trunc_in_chain(<4 x i32> %vec1, <4 x i32> %ve } define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, <4 x i32> %vec2) { -; CHECK-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain: -; CHECK: ; %bb.0: -; CHECK-NEXT: cmeq.4s v0, v0, #0 -; CHECK-NEXT: cmeq.4s v1, v1, #0 -; CHECK-NEXT: Lloh16: -; CHECK-NEXT: adrp x8, lCPI8_0@PAGE -; CHECK-NEXT: movi d2, #0x000000ffffffff -; CHECK-NEXT: movi d3, #0x00ffffffffffff -; CHECK-NEXT: bic.16b v0, v1, v0 -; CHECK-NEXT: movi d1, #0xffff0000ffff0000 -; CHECK-NEXT: xtn.4h v0, v0 -; CHECK-NEXT: orr.8b v0, v0, v2 -; CHECK-NEXT: movi d2, #0x00ffffffff0000 -; CHECK-NEXT: eor.8b v1, v0, v1 -; CHECK-NEXT: eor.8b v0, v0, v2 -; CHECK-NEXT: mov.h v1[2], wzr -; CHECK-NEXT: orr.8b v0, v0, v3 -; CHECK-NEXT: orr.8b v0, v1, v0 -; CHECK-NEXT: Lloh17: -; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF] -; CHECK-NEXT: shl.4h v0, v0, #15 -; CHECK-NEXT: cmlt.4h v0, v0, #0 -; CHECK-NEXT: and.8b v0, v0, v1 -; CHECK-NEXT: addv.4h h0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh16, Lloh17 +; SDAG-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain: +; SDAG: ; %bb.0: +; SDAG-NEXT: cmeq.4s v0, v0, #0 +; SDAG-NEXT: cmeq.4s v1, v1, #0 +; SDAG-NEXT: adrp x8, lCPI8_0@PAGE +; SDAG-NEXT: movi d2, #0x000000ffffffff +; SDAG-NEXT: movi d3, #0x00ffffffffffff +; SDAG-NEXT: bic.16b v0, v1, v0 +; SDAG-NEXT: movi d1, #0xffff0000ffff0000 +; SDAG-NEXT: xtn.4h v0, v0 +; SDAG-NEXT: orr.8b v0, v0, v2 +; SDAG-NEXT: movi d2, #0x00ffffffff0000 +; SDAG-NEXT: eor.8b v1, v0, v1 +; SDAG-NEXT: eor.8b v0, v0, v2 +; SDAG-NEXT: mov.h v1[2], wzr +; SDAG-NEXT: orr.8b v0, v0, v3 +; SDAG-NEXT: orr.8b v0, v1, v0 +; SDAG-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF] +; SDAG-NEXT: shl.4h v0, v0, #15 +; SDAG-NEXT: cmlt.4h v0, v0, #0 +; SDAG-NEXT: and.8b v0, v0, v1 +; SDAG-NEXT: addv.4h h0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_with_unknown_type_in_long_chain: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: mov w8, #1 ; =0x1 +; GISEL-NEXT: mov w9, #0 ; =0x0 +; GISEL-NEXT: cmeq.4s v5, v0, #0 +; GISEL-NEXT: fmov s2, w8 +; GISEL-NEXT: fmov s4, w9 +; GISEL-NEXT: cmeq.4s v1, v1, #0 +; GISEL-NEXT: mov.16b v3, v2 +; GISEL-NEXT: mov.16b v0, v4 +; GISEL-NEXT: mov.h v4[1], w8 +; GISEL-NEXT: bic.16b v1, v1, v5 +; GISEL-NEXT: mov.16b v5, v2 +; GISEL-NEXT: mov.h v2[1], w8 +; GISEL-NEXT: mov.h v3[1], w8 +; GISEL-NEXT: mov.h v0[1], w8 +; GISEL-NEXT: mov.h v5[1], w8 +; GISEL-NEXT: mov.h v4[2], w8 +; GISEL-NEXT: xtn.4h v1, v1 +; GISEL-NEXT: mov.h v2[2], w8 +; GISEL-NEXT: mov.h v3[2], w9 +; GISEL-NEXT: mov.h v0[2], w9 +; GISEL-NEXT: mov.h v5[2], w9 +; GISEL-NEXT: mov.h v4[3], w9 +; GISEL-NEXT: mov.h v2[3], w9 +; GISEL-NEXT: mov.h v3[3], w9 +; GISEL-NEXT: mov.h v0[3], w8 +; GISEL-NEXT: mov.h v5[3], w8 +; GISEL-NEXT: orr.8b v1, v1, v3 +; GISEL-NEXT: eor.8b v0, v1, v0 +; GISEL-NEXT: eor.8b v1, v4, v1 +; GISEL-NEXT: and.8b v0, v0, v5 +; GISEL-NEXT: orr.8b v1, v2, v1 +; GISEL-NEXT: orr.8b v0, v0, v1 +; GISEL-NEXT: ushll.4s v0, v0, #0 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp1 = icmp ne <4 x i32> %vec1, zeroinitializer @@ -234,21 +440,42 @@ define i4 @convert_to_bitmask_with_unknown_type_in_long_chain(<4 x i32> %vec1, < } define i4 @convert_to_bitmask_with_different_types_in_chain(<4 x i16> %vec1, <4 x i32> %vec2) { -; CHECK-LABEL: convert_to_bitmask_with_different_types_in_chain: -; CHECK: ; %bb.0: -; CHECK-NEXT: cmeq.4s v1, v1, #0 -; CHECK-NEXT: cmeq.4h v0, v0, #0 -; CHECK-NEXT: Lloh18: -; CHECK-NEXT: adrp x8, lCPI9_0@PAGE -; CHECK-NEXT: xtn.4h v1, v1 -; CHECK-NEXT: orn.8b v0, v1, v0 -; CHECK-NEXT: Lloh19: -; CHECK-NEXT: ldr d1, [x8, lCPI9_0@PAGEOFF] -; CHECK-NEXT: and.8b v0, v0, v1 -; CHECK-NEXT: addv.4h h0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh18, Lloh19 +; SDAG-LABEL: convert_to_bitmask_with_different_types_in_chain: +; SDAG: ; %bb.0: +; SDAG-NEXT: cmeq.4s v1, v1, #0 +; SDAG-NEXT: cmeq.4h v0, v0, #0 +; SDAG-NEXT: adrp x8, lCPI9_0@PAGE +; SDAG-NEXT: xtn.4h v1, v1 +; SDAG-NEXT: orn.8b v0, v1, v0 +; SDAG-NEXT: ldr d1, [x8, lCPI9_0@PAGEOFF] +; SDAG-NEXT: and.8b v0, v0, v1 +; SDAG-NEXT: addv.4h h0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_with_different_types_in_chain: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: cmeq.4s v1, v1, #0 +; GISEL-NEXT: cmeq.4h v0, v0, #0 +; GISEL-NEXT: xtn.4h v1, v1 +; GISEL-NEXT: orn.8b v0, v1, v0 +; GISEL-NEXT: ushll.4s v0, v0, #0 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp1 = icmp ne <4 x i16> %vec1, zeroinitializer @@ -259,21 +486,73 @@ define i4 @convert_to_bitmask_with_different_types_in_chain(<4 x i16> %vec1, <4 } define i16 @convert_to_bitmask_without_knowing_type(<16 x i1> %vec) { -; CHECK-LABEL: convert_to_bitmask_without_knowing_type: -; CHECK: ; %bb.0: -; CHECK-NEXT: shl.16b v0, v0, #7 -; CHECK-NEXT: Lloh20: -; CHECK-NEXT: adrp x8, lCPI10_0@PAGE -; CHECK-NEXT: Lloh21: -; CHECK-NEXT: ldr q1, [x8, lCPI10_0@PAGEOFF] -; CHECK-NEXT: cmlt.16b v0, v0, #0 -; CHECK-NEXT: and.16b v0, v0, v1 -; CHECK-NEXT: ext.16b v1, v0, v0, #8 -; CHECK-NEXT: zip1.16b v0, v0, v1 -; CHECK-NEXT: addv.8h h0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh20, Lloh21 +; SDAG-LABEL: convert_to_bitmask_without_knowing_type: +; SDAG: ; %bb.0: +; SDAG-NEXT: shl.16b v0, v0, #7 +; SDAG-NEXT: adrp x8, lCPI10_0@PAGE +; SDAG-NEXT: ldr q1, [x8, lCPI10_0@PAGEOFF] +; SDAG-NEXT: cmlt.16b v0, v0, #0 +; SDAG-NEXT: and.16b v0, v0, v1 +; SDAG-NEXT: ext.16b v1, v0, v0, #8 +; SDAG-NEXT: zip1.16b v0, v0, v1 +; SDAG-NEXT: addv.8h h0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_without_knowing_type: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: umov.b w8, v0[1] +; GISEL-NEXT: umov.b w9, v0[0] +; GISEL-NEXT: umov.b w10, v0[2] +; GISEL-NEXT: umov.b w11, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w9, w8, #1, #31 +; GISEL-NEXT: and w8, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[4] +; GISEL-NEXT: orr w8, w9, w8, lsl #2 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[5] +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[6] +; GISEL-NEXT: orr w8, w8, w9, lsl #4 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[7] +; GISEL-NEXT: orr w8, w8, w9, lsl #5 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[8] +; GISEL-NEXT: orr w8, w8, w9, lsl #6 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[9] +; GISEL-NEXT: orr w8, w8, w9, lsl #7 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[10] +; GISEL-NEXT: orr w8, w8, w9, lsl #8 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[11] +; GISEL-NEXT: orr w8, w8, w9, lsl #9 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[12] +; GISEL-NEXT: orr w8, w8, w9, lsl #10 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[13] +; GISEL-NEXT: orr w8, w8, w9, lsl #11 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[14] +; GISEL-NEXT: orr w8, w8, w9, lsl #12 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[15] +; GISEL-NEXT: orr w8, w8, w9, lsl #13 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #14 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #15 +; GISEL-NEXT: strh w8, [sp, #14] +; GISEL-NEXT: and w0, w8, #0xffff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %bitmask = bitcast <16 x i1> %vec to i16 ret i16 %bitmask @@ -282,16 +561,13 @@ define i16 @convert_to_bitmask_without_knowing_type(<16 x i1> %vec) { define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) { ; CHECK-LABEL: convert_to_bitmask_2xi32: ; CHECK: ; %bb.0: -; CHECK-NEXT: Lloh22: ; CHECK-NEXT: adrp x8, lCPI11_0@PAGE ; CHECK-NEXT: cmeq.2s v0, v0, #0 -; CHECK-NEXT: Lloh23: ; CHECK-NEXT: ldr d1, [x8, lCPI11_0@PAGEOFF] ; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: addp.2s v0, v0, v0 ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh22, Lloh23 %cmp_result = icmp ne <2 x i32> %vec, zeroinitializer %bitmask = bitcast <2 x i1> %cmp_result to i2 @@ -299,19 +575,51 @@ define i2 @convert_to_bitmask_2xi32(<2 x i32> %vec) { } define i4 @convert_to_bitmask_4xi8(<4 x i8> %vec) { -; CHECK-LABEL: convert_to_bitmask_4xi8: -; CHECK: ; %bb.0: -; CHECK-NEXT: bic.4h v0, #255, lsl #8 -; CHECK-NEXT: Lloh24: -; CHECK-NEXT: adrp x8, lCPI12_0@PAGE -; CHECK-NEXT: Lloh25: -; CHECK-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF] -; CHECK-NEXT: cmeq.4h v0, v0, #0 -; CHECK-NEXT: bic.8b v0, v1, v0 -; CHECK-NEXT: addv.4h h0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh24, Lloh25 +; SDAG-LABEL: convert_to_bitmask_4xi8: +; SDAG: ; %bb.0: +; SDAG-NEXT: bic.4h v0, #255, lsl #8 +; SDAG-NEXT: adrp x8, lCPI12_0@PAGE +; SDAG-NEXT: ldr d1, [x8, lCPI12_0@PAGEOFF] +; SDAG-NEXT: cmeq.4h v0, v0, #0 +; SDAG-NEXT: bic.8b v0, v1, v0 +; SDAG-NEXT: addv.4h h0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_4xi8: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: mov w8, #0 ; =0x0 +; GISEL-NEXT: uzp1.8b v0, v0, v0 +; GISEL-NEXT: fmov s1, w8 +; GISEL-NEXT: mov.b v1[1], w8 +; GISEL-NEXT: mov.b v1[2], w8 +; GISEL-NEXT: mov.b v1[3], w8 +; GISEL-NEXT: cmeq.8b v0, v0, v1 +; GISEL-NEXT: mvn.8b v0, v0 +; GISEL-NEXT: umov.b w8, v0[0] +; GISEL-NEXT: umov.b w9, v0[1] +; GISEL-NEXT: mov.s v1[0], w8 +; GISEL-NEXT: umov.b w8, v0[2] +; GISEL-NEXT: mov.s v1[1], w9 +; GISEL-NEXT: umov.b w9, v0[3] +; GISEL-NEXT: mov.s v1[2], w8 +; GISEL-NEXT: mov.s v1[3], w9 +; GISEL-NEXT: mov.s w8, v1[1] +; GISEL-NEXT: mov.s w9, v1[2] +; GISEL-NEXT: fmov w11, s1 +; GISEL-NEXT: mov.s w10, v1[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp_result = icmp ne <4 x i8> %vec, zeroinitializer %bitmask = bitcast <4 x i1> %cmp_result to i4 @@ -322,17 +630,14 @@ define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) { ; CHECK-LABEL: convert_to_bitmask_8xi2: ; CHECK: ; %bb.0: ; CHECK-NEXT: movi.8b v1, #3 -; CHECK-NEXT: Lloh26: ; CHECK-NEXT: adrp x8, lCPI13_0@PAGE ; CHECK-NEXT: and.8b v0, v0, v1 -; CHECK-NEXT: Lloh27: ; CHECK-NEXT: ldr d1, [x8, lCPI13_0@PAGEOFF] ; CHECK-NEXT: cmeq.8b v0, v0, #0 ; CHECK-NEXT: bic.8b v0, v1, v0 ; CHECK-NEXT: addv.8b b0, v0 ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh26, Lloh27 %cmp_result = icmp ne <8 x i2> %vec, zeroinitializer %bitmask = bitcast <8 x i1> %cmp_result to i8 @@ -340,20 +645,39 @@ define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) { } define i4 @convert_to_bitmask_float(<4 x float> %vec) { -; CHECK-LABEL: convert_to_bitmask_float: -; CHECK: ; %bb.0: -; CHECK-NEXT: fcmgt.4s v1, v0, #0.0 -; CHECK-NEXT: fcmlt.4s v0, v0, #0.0 -; CHECK-NEXT: Lloh28: -; CHECK-NEXT: adrp x8, lCPI14_0@PAGE -; CHECK-NEXT: orr.16b v0, v0, v1 -; CHECK-NEXT: Lloh29: -; CHECK-NEXT: ldr q1, [x8, lCPI14_0@PAGEOFF] -; CHECK-NEXT: and.16b v0, v0, v1 -; CHECK-NEXT: addv.4s s0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh28, Lloh29 +; SDAG-LABEL: convert_to_bitmask_float: +; SDAG: ; %bb.0: +; SDAG-NEXT: fcmgt.4s v1, v0, #0.0 +; SDAG-NEXT: fcmlt.4s v0, v0, #0.0 +; SDAG-NEXT: adrp x8, lCPI14_0@PAGE +; SDAG-NEXT: orr.16b v0, v0, v1 +; SDAG-NEXT: ldr q1, [x8, lCPI14_0@PAGEOFF] +; SDAG-NEXT: and.16b v0, v0, v1 +; SDAG-NEXT: addv.4s s0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_to_bitmask_float: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: fcmgt.4s v1, v0, #0.0 +; GISEL-NEXT: fcmlt.4s v0, v0, #0.0 +; GISEL-NEXT: orr.16b v0, v0, v1 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp_result = fcmp one <4 x float> %vec, zeroinitializer @@ -364,24 +688,58 @@ define i4 @convert_to_bitmask_float(<4 x float> %vec) { ; Larger vector types don't map directly, but the can be split/truncated and then converted. ; After the comparison against 0, this is truncated to <8 x i16>, which is valid again. define i8 @convert_large_vector(<8 x i32> %vec) { -; CHECK-LABEL: convert_large_vector: -; CHECK: ; %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: cmeq.4s v1, v1, #0 -; CHECK-NEXT: cmeq.4s v0, v0, #0 -; CHECK-NEXT: Lloh30: -; CHECK-NEXT: adrp x8, lCPI15_0@PAGE -; CHECK-NEXT: uzp1.8h v0, v0, v1 -; CHECK-NEXT: Lloh31: -; CHECK-NEXT: ldr q1, [x8, lCPI15_0@PAGEOFF] -; CHECK-NEXT: bic.16b v0, v1, v0 -; CHECK-NEXT: addv.8h h0, v0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: and w0, w8, #0xff -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh30, Lloh31 +; SDAG-LABEL: convert_large_vector: +; SDAG: ; %bb.0: +; SDAG-NEXT: sub sp, sp, #16 +; SDAG-NEXT: .cfi_def_cfa_offset 16 +; SDAG-NEXT: cmeq.4s v1, v1, #0 +; SDAG-NEXT: cmeq.4s v0, v0, #0 +; SDAG-NEXT: adrp x8, lCPI15_0@PAGE +; SDAG-NEXT: uzp1.8h v0, v0, v1 +; SDAG-NEXT: ldr q1, [x8, lCPI15_0@PAGEOFF] +; SDAG-NEXT: bic.16b v0, v1, v0 +; SDAG-NEXT: addv.8h h0, v0 +; SDAG-NEXT: fmov w8, s0 +; SDAG-NEXT: and w0, w8, #0xff +; SDAG-NEXT: add sp, sp, #16 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_large_vector: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: cmeq.4s v0, v0, #0 +; GISEL-NEXT: cmeq.4s v1, v1, #0 +; GISEL-NEXT: mvn.16b v0, v0 +; GISEL-NEXT: mvn.16b v1, v1 +; GISEL-NEXT: uzp1.8h v0, v0, v1 +; GISEL-NEXT: xtn.8b v0, v0 +; GISEL-NEXT: umov.b w8, v0[1] +; GISEL-NEXT: umov.b w9, v0[0] +; GISEL-NEXT: umov.b w10, v0[2] +; GISEL-NEXT: umov.b w11, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w9, w8, #1, #31 +; GISEL-NEXT: and w8, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[4] +; GISEL-NEXT: orr w8, w9, w8, lsl #2 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[5] +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: umov.b w10, v0[6] +; GISEL-NEXT: orr w8, w8, w9, lsl #4 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.b w11, v0[7] +; GISEL-NEXT: orr w8, w8, w9, lsl #5 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #6 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #7 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp_result = icmp ne <8 x i32> %vec, zeroinitializer @@ -390,20 +748,40 @@ define i8 @convert_large_vector(<8 x i32> %vec) { } define i4 @convert_legalized_illegal_element_size(<4 x i22> %vec) { -; CHECK-LABEL: convert_legalized_illegal_element_size: -; CHECK: ; %bb.0: -; CHECK-NEXT: movi.4s v1, #63, msl #16 -; CHECK-NEXT: Lloh32: -; CHECK-NEXT: adrp x8, lCPI16_0@PAGE -; CHECK-NEXT: cmtst.4s v0, v0, v1 -; CHECK-NEXT: Lloh33: -; CHECK-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF] -; CHECK-NEXT: xtn.4h v0, v0 -; CHECK-NEXT: and.8b v0, v0, v1 -; CHECK-NEXT: addv.4h h0, v0 -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh32, Lloh33 +; SDAG-LABEL: convert_legalized_illegal_element_size: +; SDAG: ; %bb.0: +; SDAG-NEXT: movi.4s v1, #63, msl #16 +; SDAG-NEXT: adrp x8, lCPI16_0@PAGE +; SDAG-NEXT: cmtst.4s v0, v0, v1 +; SDAG-NEXT: ldr d1, [x8, lCPI16_0@PAGEOFF] +; SDAG-NEXT: xtn.4h v0, v0 +; SDAG-NEXT: and.8b v0, v0, v1 +; SDAG-NEXT: addv.4h h0, v0 +; SDAG-NEXT: fmov w0, s0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: convert_legalized_illegal_element_size: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: movi.4s v1, #63, msl #16 +; GISEL-NEXT: and.16b v0, v0, v1 +; GISEL-NEXT: cmeq.4s v0, v0, #0 +; GISEL-NEXT: mvn.16b v0, v0 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: fmov w11, s0 +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w11, w8, #1, #31 +; GISEL-NEXT: and w8, w9, #0x1 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w11, w8, lsl #2 +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp_result = icmp ne <4 x i22> %vec, zeroinitializer %bitmask = bitcast <4 x i1> %cmp_result to i4 @@ -415,7 +793,6 @@ define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) { ; CHECK-LABEL: no_direct_convert_for_bad_concat: ; CHECK: ; %bb.0: ; CHECK-NEXT: cmtst.4s v0, v0, v0 -; CHECK-NEXT: Lloh34: ; CHECK-NEXT: adrp x8, lCPI17_0@PAGE ; CHECK-NEXT: xtn.4h v0, v0 ; CHECK-NEXT: umov.h w9, v0[0] @@ -427,14 +804,12 @@ define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) { ; CHECK-NEXT: umov.h w9, v0[3] ; CHECK-NEXT: mov.b v1[7], w9 ; CHECK-NEXT: shl.8b v0, v1, #7 -; CHECK-NEXT: Lloh35: ; CHECK-NEXT: ldr d1, [x8, lCPI17_0@PAGEOFF] ; CHECK-NEXT: cmlt.8b v0, v0, #0 ; CHECK-NEXT: and.8b v0, v0, v1 ; CHECK-NEXT: addv.8b b0, v0 ; CHECK-NEXT: fmov w0, s0 ; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh34, Lloh35 %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer %vector_pad = shufflevector <4 x i1> poison, <4 x i1> %cmp_result, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 4, i32 5, i32 6, i32 7> @@ -443,47 +818,101 @@ define i8 @no_direct_convert_for_bad_concat(<4 x i32> %vec) { } define <8 x i1> @no_convert_without_direct_bitcast(<8 x i16> %vec) { -; CHECK-LABEL: no_convert_without_direct_bitcast: -; CHECK: ; %bb.0: -; CHECK-NEXT: cmtst.8h v0, v0, v0 -; CHECK-NEXT: xtn.8b v0, v0 -; CHECK-NEXT: ret +; SDAG-LABEL: no_convert_without_direct_bitcast: +; SDAG: ; %bb.0: +; SDAG-NEXT: cmtst.8h v0, v0, v0 +; SDAG-NEXT: xtn.8b v0, v0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: no_convert_without_direct_bitcast: +; GISEL: ; %bb.0: +; GISEL-NEXT: cmeq.8h v0, v0, #0 +; GISEL-NEXT: mvn.16b v0, v0 +; GISEL-NEXT: xtn.8b v0, v0 +; GISEL-NEXT: ret %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer ret <8 x i1> %cmp_result } define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) { -; CHECK-LABEL: no_combine_illegal_num_elements: -; CHECK: ; %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: fmov s1, w4 -; CHECK-NEXT: mov.s v0[1], w1 -; CHECK-NEXT: mov.s v1[1], w5 -; CHECK-NEXT: mov.s v0[2], w2 -; CHECK-NEXT: cmeq.4s v1, v1, #0 -; CHECK-NEXT: mov.s v0[3], w3 -; CHECK-NEXT: cmeq.4s v0, v0, #0 -; CHECK-NEXT: uzp1.8h v0, v0, v1 -; CHECK-NEXT: mvn.16b v0, v0 -; CHECK-NEXT: xtn.8b v0, v0 -; CHECK-NEXT: umov.b w8, v0[0] -; CHECK-NEXT: umov.b w9, v0[1] -; CHECK-NEXT: umov.b w10, v0[2] -; CHECK-NEXT: and w8, w8, #0x1 -; CHECK-NEXT: bfi w8, w9, #1, #1 -; CHECK-NEXT: umov.b w9, v0[3] -; CHECK-NEXT: bfi w8, w10, #2, #1 -; CHECK-NEXT: umov.b w10, v0[4] -; CHECK-NEXT: bfi w8, w9, #3, #1 -; CHECK-NEXT: umov.b w9, v0[5] -; CHECK-NEXT: bfi w8, w10, #4, #1 -; CHECK-NEXT: orr w8, w8, w9, lsl #5 -; CHECK-NEXT: and w0, w8, #0x3f -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; SDAG-LABEL: no_combine_illegal_num_elements: +; SDAG: ; %bb.0: +; SDAG-NEXT: sub sp, sp, #16 +; SDAG-NEXT: .cfi_def_cfa_offset 16 +; SDAG-NEXT: fmov s0, w0 +; SDAG-NEXT: fmov s1, w4 +; SDAG-NEXT: mov.s v0[1], w1 +; SDAG-NEXT: mov.s v1[1], w5 +; SDAG-NEXT: mov.s v0[2], w2 +; SDAG-NEXT: cmeq.4s v1, v1, #0 +; SDAG-NEXT: mov.s v0[3], w3 +; SDAG-NEXT: cmeq.4s v0, v0, #0 +; SDAG-NEXT: uzp1.8h v0, v0, v1 +; SDAG-NEXT: mvn.16b v0, v0 +; SDAG-NEXT: xtn.8b v0, v0 +; SDAG-NEXT: umov.b w8, v0[0] +; SDAG-NEXT: umov.b w9, v0[1] +; SDAG-NEXT: umov.b w10, v0[2] +; SDAG-NEXT: and w8, w8, #0x1 +; SDAG-NEXT: bfi w8, w9, #1, #1 +; SDAG-NEXT: umov.b w9, v0[3] +; SDAG-NEXT: bfi w8, w10, #2, #1 +; SDAG-NEXT: umov.b w10, v0[4] +; SDAG-NEXT: bfi w8, w9, #3, #1 +; SDAG-NEXT: umov.b w9, v0[5] +; SDAG-NEXT: bfi w8, w10, #4, #1 +; SDAG-NEXT: orr w8, w8, w9, lsl #5 +; SDAG-NEXT: and w0, w8, #0x3f +; SDAG-NEXT: add sp, sp, #16 +; SDAG-NEXT: ret +; +; GISEL-LABEL: no_combine_illegal_num_elements: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: .cfi_def_cfa_offset 16 +; GISEL-NEXT: mov.s v0[0], w0 +; GISEL-NEXT: mov.s v1[0], w4 +; GISEL-NEXT: mov.s v2[0], wzr +; GISEL-NEXT: mov.s v0[1], w1 +; GISEL-NEXT: mov.s v1[1], w5 +; GISEL-NEXT: mov.s v2[1], wzr +; GISEL-NEXT: mov.s v0[2], w2 +; GISEL-NEXT: cmeq.4s v1, v1, v2 +; GISEL-NEXT: mvn.16b v1, v1 +; GISEL-NEXT: mov.s v0[3], w3 +; GISEL-NEXT: cmeq.4s v0, v0, #0 +; GISEL-NEXT: mvn.16b v0, v0 +; GISEL-NEXT: mov.s w8, v0[1] +; GISEL-NEXT: mov.s w9, v0[2] +; GISEL-NEXT: mov.s w10, v0[3] +; GISEL-NEXT: mov.h v0[1], w8 +; GISEL-NEXT: mov.s w8, v1[1] +; GISEL-NEXT: mov.h v0[2], w9 +; GISEL-NEXT: mov.h v0[3], w10 +; GISEL-NEXT: mov.h v0[4], v1[0] +; GISEL-NEXT: mov.h v0[5], w8 +; GISEL-NEXT: umov.h w8, v0[1] +; GISEL-NEXT: umov.h w9, v0[0] +; GISEL-NEXT: umov.h w10, v0[2] +; GISEL-NEXT: umov.h w11, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: bfi w9, w8, #1, #31 +; GISEL-NEXT: and w8, w10, #0x1 +; GISEL-NEXT: umov.h w10, v0[4] +; GISEL-NEXT: orr w8, w9, w8, lsl #2 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: umov.h w11, v0[5] +; GISEL-NEXT: orr w8, w8, w9, lsl #3 +; GISEL-NEXT: and w9, w10, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #4 +; GISEL-NEXT: and w9, w11, #0x1 +; GISEL-NEXT: orr w8, w8, w9, lsl #5 +; GISEL-NEXT: and w8, w8, #0x3f +; GISEL-NEXT: strb w8, [sp, #15] +; GISEL-NEXT: and w0, w8, #0xff +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %cmp_result = icmp ne <6 x i32> %vec, zeroinitializer %bitmask = bitcast <6 x i1> %cmp_result to i6 @@ -492,28 +921,220 @@ define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) { ; Only apply the combine when casting a vector to a scalar. define <2 x i8> @vector_to_vector_cast(<16 x i1> %arg) nounwind { -; CHECK-LABEL: vector_to_vector_cast: -; CHECK: ; %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: shl.16b v0, v0, #7 -; CHECK-NEXT: Lloh36: -; CHECK-NEXT: adrp x8, lCPI20_0@PAGE -; CHECK-NEXT: Lloh37: -; CHECK-NEXT: ldr q1, [x8, lCPI20_0@PAGEOFF] -; CHECK-NEXT: add x8, sp, #14 -; CHECK-NEXT: cmlt.16b v0, v0, #0 -; CHECK-NEXT: and.16b v0, v0, v1 -; CHECK-NEXT: ext.16b v1, v0, v0, #8 -; CHECK-NEXT: zip1.16b v0, v0, v1 -; CHECK-NEXT: addv.8h h0, v0 -; CHECK-NEXT: str h0, [sp, #14] -; CHECK-NEXT: ld1.b { v0 }[0], [x8] -; CHECK-NEXT: orr x8, x8, #0x1 -; CHECK-NEXT: ld1.b { v0 }[4], [x8] -; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret -; CHECK-NEXT: .loh AdrpLdr Lloh36, Lloh37 +; SDAG-LABEL: vector_to_vector_cast: +; SDAG: ; %bb.0: +; SDAG-NEXT: sub sp, sp, #16 +; SDAG-NEXT: shl.16b v0, v0, #7 +; SDAG-NEXT: adrp x8, lCPI20_0@PAGE +; SDAG-NEXT: ldr q1, [x8, lCPI20_0@PAGEOFF] +; SDAG-NEXT: add x8, sp, #14 +; SDAG-NEXT: cmlt.16b v0, v0, #0 +; SDAG-NEXT: and.16b v0, v0, v1 +; SDAG-NEXT: ext.16b v1, v0, v0, #8 +; SDAG-NEXT: zip1.16b v0, v0, v1 +; SDAG-NEXT: addv.8h h0, v0 +; SDAG-NEXT: str h0, [sp, #14] +; SDAG-NEXT: ld1.b { v0 }[0], [x8] +; SDAG-NEXT: orr x8, x8, #0x1 +; SDAG-NEXT: ld1.b { v0 }[4], [x8] +; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; SDAG-NEXT: add sp, sp, #16 +; SDAG-NEXT: ret +; +; GISEL-LABEL: vector_to_vector_cast: +; GISEL: ; %bb.0: +; GISEL-NEXT: sub sp, sp, #16 +; GISEL-NEXT: umov.b w8, v0[1] +; GISEL-NEXT: mov d1, v0[1] +; GISEL-NEXT: umov.b w10, v0[1] +; GISEL-NEXT: umov.b w9, v0[0] +; GISEL-NEXT: umov.b w13, v0[0] +; GISEL-NEXT: umov.b w14, v0[2] +; GISEL-NEXT: umov.b w15, v0[3] +; GISEL-NEXT: umov.b w11, v0[2] +; GISEL-NEXT: umov.b w16, v0[4] +; GISEL-NEXT: umov.b w17, v0[5] +; GISEL-NEXT: umov.b w12, v0[3] +; GISEL-NEXT: and w8, w8, #0x1 +; GISEL-NEXT: and w10, w10, #0x1 +; GISEL-NEXT: umov.b w0, v1[1] +; GISEL-NEXT: bfi w9, w8, #1, #31 +; GISEL-NEXT: bfi w13, w10, #1, #31 +; GISEL-NEXT: and w14, w14, #0x1 +; GISEL-NEXT: umov.b w8, v1[0] +; GISEL-NEXT: umov.b w10, v1[2] +; GISEL-NEXT: and w15, w15, #0x1 +; GISEL-NEXT: orr w13, w13, w14, lsl #2 +; GISEL-NEXT: umov.b w14, v1[3] +; GISEL-NEXT: and w11, w11, #0x1 +; GISEL-NEXT: and w0, w0, #0x1 +; GISEL-NEXT: and w16, w16, #0x1 +; GISEL-NEXT: orr w9, w9, w11, lsl #2 +; GISEL-NEXT: orr w13, w13, w15, lsl #3 +; GISEL-NEXT: umov.b w15, v1[4] +; GISEL-NEXT: umov.b w11, v0[6] +; GISEL-NEXT: bfi w8, w0, #1, #31 +; GISEL-NEXT: and w10, w10, #0x1 +; GISEL-NEXT: and w17, w17, #0x1 +; GISEL-NEXT: orr w13, w13, w16, lsl #4 +; GISEL-NEXT: and w14, w14, #0x1 +; GISEL-NEXT: umov.b w0, v0[7] +; GISEL-NEXT: orr w8, w8, w10, lsl #2 +; GISEL-NEXT: umov.b w10, v1[5] +; GISEL-NEXT: umov.b w16, v1[6] +; GISEL-NEXT: orr w13, w13, w17, lsl #5 +; GISEL-NEXT: umov.b w17, v0[4] +; GISEL-NEXT: and w15, w15, #0x1 +; GISEL-NEXT: orr w8, w8, w14, lsl #3 +; GISEL-NEXT: and w12, w12, #0x1 +; GISEL-NEXT: and w11, w11, #0x1 +; GISEL-NEXT: umov.b w14, v1[7] +; GISEL-NEXT: orr w9, w9, w12, lsl #3 +; GISEL-NEXT: orr w11, w13, w11, lsl #6 +; GISEL-NEXT: orr w8, w8, w15, lsl #4 +; GISEL-NEXT: umov.b w15, v0[5] +; GISEL-NEXT: and w10, w10, #0x1 +; GISEL-NEXT: and w0, w0, #0x1 +; GISEL-NEXT: and w12, w17, #0x1 +; GISEL-NEXT: umov.b w13, v0[1] +; GISEL-NEXT: orr w8, w8, w10, lsl #5 +; GISEL-NEXT: and w16, w16, #0x1 +; GISEL-NEXT: orr w9, w9, w12, lsl #4 +; GISEL-NEXT: umov.b w10, v0[0] +; GISEL-NEXT: orr w11, w11, w0, lsl #7 +; GISEL-NEXT: and w14, w14, #0x1 +; GISEL-NEXT: and w12, w15, #0x1 +; GISEL-NEXT: umov.b w15, v0[2] +; GISEL-NEXT: orr w8, w8, w16, lsl #6 +; GISEL-NEXT: orr w9, w9, w12, lsl #5 +; GISEL-NEXT: umov.b w12, v0[6] +; GISEL-NEXT: strb w11, [sp, #8] +; GISEL-NEXT: and w11, w13, #0x1 +; GISEL-NEXT: umov.b w13, v0[3] +; GISEL-NEXT: orr w8, w8, w14, lsl #7 +; GISEL-NEXT: umov.b w14, v0[7] +; GISEL-NEXT: ldr b0, [sp, #8] +; GISEL-NEXT: bfi w10, w11, #1, #31 +; GISEL-NEXT: and w11, w15, #0x1 +; GISEL-NEXT: strb w8, [sp, #9] +; GISEL-NEXT: umov.b w15, v0[4] +; GISEL-NEXT: and w8, w12, #0x1 +; GISEL-NEXT: orr w10, w10, w11, lsl #2 +; GISEL-NEXT: orr w8, w9, w8, lsl #6 +; GISEL-NEXT: and w9, w13, #0x1 +; GISEL-NEXT: umov.b w11, v0[1] +; GISEL-NEXT: orr w9, w10, w9, lsl #3 +; GISEL-NEXT: umov.b w10, v0[5] +; GISEL-NEXT: umov.b w12, v0[0] +; GISEL-NEXT: and w13, w14, #0x1 +; GISEL-NEXT: umov.b w16, v0[2] +; GISEL-NEXT: umov.b w17, v0[3] +; GISEL-NEXT: and w14, w15, #0x1 +; GISEL-NEXT: umov.b w15, v0[2] +; GISEL-NEXT: orr w8, w8, w13, lsl #7 +; GISEL-NEXT: orr w9, w9, w14, lsl #4 +; GISEL-NEXT: umov.b w13, v0[6] +; GISEL-NEXT: and w11, w11, #0x1 +; GISEL-NEXT: umov.b w14, v0[3] +; GISEL-NEXT: strb w8, [sp, #10] +; GISEL-NEXT: and w8, w10, #0x1 +; GISEL-NEXT: bfi w12, w11, #1, #31 +; GISEL-NEXT: orr w8, w9, w8, lsl #5 +; GISEL-NEXT: umov.b w10, v0[4] +; GISEL-NEXT: and w9, w15, #0x1 +; GISEL-NEXT: umov.b w11, v0[7] +; GISEL-NEXT: umov.b w15, v0[1] +; GISEL-NEXT: orr w9, w12, w9, lsl #2 +; GISEL-NEXT: umov.b w12, v0[5] +; GISEL-NEXT: and w13, w13, #0x1 +; GISEL-NEXT: and w14, w14, #0x1 +; GISEL-NEXT: orr w8, w8, w13, lsl #6 +; GISEL-NEXT: umov.b w13, v0[0] +; GISEL-NEXT: orr w9, w9, w14, lsl #3 +; GISEL-NEXT: and w10, w10, #0x1 +; GISEL-NEXT: umov.b w14, v0[6] +; GISEL-NEXT: and w11, w11, #0x1 +; GISEL-NEXT: and w15, w15, #0x1 +; GISEL-NEXT: umov.b w0, v0[3] +; GISEL-NEXT: orr w9, w9, w10, lsl #4 +; GISEL-NEXT: and w10, w12, #0x1 +; GISEL-NEXT: umov.b w12, v0[7] +; GISEL-NEXT: orr w8, w8, w11, lsl #7 +; GISEL-NEXT: bfi w13, w15, #1, #31 +; GISEL-NEXT: and w11, w16, #0x1 +; GISEL-NEXT: orr w9, w9, w10, lsl #5 +; GISEL-NEXT: and w10, w14, #0x1 +; GISEL-NEXT: umov.b w14, v0[4] +; GISEL-NEXT: strb w8, [sp, #11] +; GISEL-NEXT: umov.b w15, v0[1] +; GISEL-NEXT: umov.b w16, v0[3] +; GISEL-NEXT: orr w8, w9, w10, lsl #6 +; GISEL-NEXT: orr w9, w13, w11, lsl #2 +; GISEL-NEXT: and w10, w12, #0x1 +; GISEL-NEXT: and w11, w17, #0x1 +; GISEL-NEXT: umov.b w12, v0[5] +; GISEL-NEXT: umov.b w17, v0[0] +; GISEL-NEXT: orr w8, w8, w10, lsl #7 +; GISEL-NEXT: orr w9, w9, w11, lsl #3 +; GISEL-NEXT: umov.b w10, v0[1] +; GISEL-NEXT: and w11, w14, #0x1 +; GISEL-NEXT: umov.b w14, v0[0] +; GISEL-NEXT: and w15, w15, #0x1 +; GISEL-NEXT: orr w9, w9, w11, lsl #4 +; GISEL-NEXT: umov.b w11, v0[2] +; GISEL-NEXT: umov.b w13, v0[6] +; GISEL-NEXT: and w12, w12, #0x1 +; GISEL-NEXT: bfi w17, w15, #1, #31 +; GISEL-NEXT: umov.b w15, v0[5] +; GISEL-NEXT: orr w9, w9, w12, lsl #5 +; GISEL-NEXT: and w10, w10, #0x1 +; GISEL-NEXT: umov.b w12, v0[2] +; GISEL-NEXT: bfi w14, w10, #1, #31 +; GISEL-NEXT: umov.b w10, v0[4] +; GISEL-NEXT: ldr b1, [sp, #9] +; GISEL-NEXT: and w11, w11, #0x1 +; GISEL-NEXT: and w13, w13, #0x1 +; GISEL-NEXT: strb w8, [sp, #12] +; GISEL-NEXT: orr w11, w14, w11, lsl #2 +; GISEL-NEXT: and w14, w16, #0x1 +; GISEL-NEXT: umov.b w16, v0[4] +; GISEL-NEXT: and w12, w12, #0x1 +; GISEL-NEXT: and w15, w15, #0x1 +; GISEL-NEXT: orr w9, w9, w13, lsl #6 +; GISEL-NEXT: orr w11, w11, w14, lsl #3 +; GISEL-NEXT: orr w12, w17, w12, lsl #2 +; GISEL-NEXT: and w10, w10, #0x1 +; GISEL-NEXT: and w17, w0, #0x1 +; GISEL-NEXT: umov.b w0, v0[5] +; GISEL-NEXT: umov.b w14, v0[6] +; GISEL-NEXT: orr w10, w11, w10, lsl #4 +; GISEL-NEXT: orr w12, w12, w17, lsl #3 +; GISEL-NEXT: umov.b w11, v0[7] +; GISEL-NEXT: and w16, w16, #0x1 +; GISEL-NEXT: umov.b w17, v0[6] +; GISEL-NEXT: orr w10, w10, w15, lsl #5 +; GISEL-NEXT: umov.b w15, v0[7] +; GISEL-NEXT: orr w12, w12, w16, lsl #4 +; GISEL-NEXT: and w16, w0, #0x1 +; GISEL-NEXT: umov.b w0, v0[7] +; GISEL-NEXT: and w14, w14, #0x1 +; GISEL-NEXT: orr w12, w12, w16, lsl #5 +; GISEL-NEXT: orr w10, w10, w14, lsl #6 +; GISEL-NEXT: and w11, w11, #0x1 +; GISEL-NEXT: and w13, w17, #0x1 +; GISEL-NEXT: orr w9, w9, w11, lsl #7 +; GISEL-NEXT: mov.s v0[1], v1[0] +; GISEL-NEXT: orr w11, w12, w13, lsl #6 +; GISEL-NEXT: and w12, w15, #0x1 +; GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; GISEL-NEXT: orr w8, w10, w12, lsl #7 +; GISEL-NEXT: and w10, w0, #0x1 +; GISEL-NEXT: strb w9, [sp, #13] +; GISEL-NEXT: orr w9, w11, w10, lsl #7 +; GISEL-NEXT: strb w8, [sp, #14] +; GISEL-NEXT: strb w9, [sp, #15] +; GISEL-NEXT: add sp, sp, #16 +; GISEL-NEXT: ret %bc = bitcast <16 x i1> %arg to <2 x i8> ret <2 x i8> %bc } diff --git a/llvm/test/CodeGen/AArch64/vecreduce-add.ll b/llvm/test/CodeGen/AArch64/vecreduce-add.ll index 8473f45f6c80..5d6b523f1549 100644 --- a/llvm/test/CodeGen/AArch64/vecreduce-add.ll +++ b/llvm/test/CodeGen/AArch64/vecreduce-add.ll @@ -72,6 +72,24 @@ entry: ret i64 %z } +define i64 @add_v4i32_v4i64_zsext(<4 x i32> %xi) { +; CHECK-LABEL: add_v4i32_v4i64_zsext: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ushll v1.2d, v0.2s, #0 +; CHECK-NEXT: saddw2 v0.2d, v1.2d, v0.4s +; CHECK-NEXT: addp d0, v0.2d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret +entry: + %x = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> <i32 0, i32 1> + %y = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> <i32 2, i32 3> + %xx = zext <2 x i32> %x to <2 x i64> + %yy = sext <2 x i32> %y to <2 x i64> + %zz = add <2 x i64> %xx, %yy + %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %zz) + ret i64 %z +} + define i64 @add_v2i32_v2i64_zext(<2 x i32> %x) { ; CHECK-LABEL: add_v2i32_v2i64_zext: ; CHECK: // %bb.0: // %entry diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll deleted file mode 100644 index aefcad491073..000000000000 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-divergent.ll +++ /dev/null @@ -1,72 +0,0 @@ -; RUN: not llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel-abort=2 -pass-remarks-missed="gisel.*" -verify-machineinstrs=0 -o /dev/null 2>&1 %s | FileCheck -check-prefix=ERR %s - -; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: kernel_dynamic_stackalloc_vgpr_align4) -; ERR-NEXT: warning: Instruction selection used fallback path for kernel_dynamic_stackalloc_vgpr_align4 -; ERR-NEXT: error: <unknown>:0:0: in function kernel_dynamic_stackalloc_vgpr_align4 void (ptr addrspace(1)): unsupported dynamic alloca - -define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_align4(ptr addrspace(1) %ptr) { - %id = call i32 @llvm.amdgcn.workitem.id.x() - %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %id - %n = load i32, ptr addrspace(1) %gep - %alloca = alloca i32, i32 %n, align 4, addrspace(5) - store volatile i32 123, ptr addrspace(5) %alloca - ret void -} - -; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: kernel_dynamic_stackalloc_vgpr_default_align) -; ERR-NEXT: warning: Instruction selection used fallback path for kernel_dynamic_stackalloc_vgpr_default_align -; ERR-NEXT: error: <unknown>:0:0: in function kernel_dynamic_stackalloc_vgpr_default_align void (ptr addrspace(1)): unsupported dynamic alloca - -define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_default_align(ptr addrspace(1) %ptr) { - %id = call i32 @llvm.amdgcn.workitem.id.x() - %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %id - %n = load i32, ptr addrspace(1) %gep - %alloca = alloca i32, i32 %n, addrspace(5) - store volatile i32 123, ptr addrspace(5) %alloca - ret void -} -; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 64 (in function: kernel_dynamic_stackalloc_vgpr_align64) -; ERR-NEXT: warning: Instruction selection used fallback path for kernel_dynamic_stackalloc_vgpr_align64 -; ERR-NEXT: error: <unknown>:0:0: in function kernel_dynamic_stackalloc_vgpr_align64 void (ptr addrspace(1)): unsupported dynamic alloca - -define amdgpu_kernel void @kernel_dynamic_stackalloc_vgpr_align64(ptr addrspace(1) %ptr) { - %id = call i32 @llvm.amdgcn.workitem.id.x() - %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %id - %n = load i32, ptr addrspace(1) %gep - %alloca = alloca i32, i32 %n, align 64, addrspace(5) - store volatile i32 123, ptr addrspace(5) %alloca - ret void -} - -; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: func_dynamic_stackalloc_vgpr_align4) -; ERR-NEXT: warning: Instruction selection used fallback path for func_dynamic_stackalloc_vgpr_align4 -; ERR-NEXT: error: <unknown>:0:0: in function func_dynamic_stackalloc_vgpr_align4 void (i32): unsupported dynamic alloca - -define void @func_dynamic_stackalloc_vgpr_align4(i32 %n) { - %alloca = alloca i32, i32 %n, align 4, addrspace(5) - store volatile i32 456, ptr addrspace(5) %alloca - ret void -} - -; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 1 (in function: func_dynamic_stackalloc_vgpr_default_align) -; ERR-NEXT: warning: Instruction selection used fallback path for func_dynamic_stackalloc_vgpr_default_align -; ERR-NEXT: error: <unknown>:0:0: in function func_dynamic_stackalloc_vgpr_default_align void (i32): unsupported dynamic alloca - -define void @func_dynamic_stackalloc_vgpr_default_align(i32 %n) { - %alloca = alloca i32, i32 %n, addrspace(5) - store volatile i32 456, ptr addrspace(5) %alloca - ret void -} -; ERR: remark: <unknown>:0:0: cannot select: %{{[0-9]+}}:sreg_32(p5) = G_DYN_STACKALLOC %{{[0-9]+}}:vgpr(s32), 64 (in function: func_dynamic_stackalloc_vgpr_align64) -; ERR-NEXT: warning: Instruction selection used fallback path for func_dynamic_stackalloc_vgpr_align64 -; ERR-NEXT: error: <unknown>:0:0: in function func_dynamic_stackalloc_vgpr_align64 void (i32): unsupported dynamic alloca - -define void @func_dynamic_stackalloc_vgpr_align64(i32 %n) { - %alloca = alloca i32, i32 %n, align 64, addrspace(5) - store volatile i32 456, ptr addrspace(5) %alloca - ret void -} - -declare i32 @llvm.amdgcn.workitem.id.x() #0 - -attributes #0 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll index b0f2aac9a42d..7cafa2f608a4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll @@ -3990,6 +3990,116 @@ bb: ret void } +define amdgpu_gs void @sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset(ptr addrspace(5) inreg %sgpr_base, i32 inreg %sidx, i32 %vidx) { +; GFX9-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX9: ; %bb.0: ; %bb +; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s5 +; GFX9-NEXT: v_add_u32_e32 v0, s3, v0 +; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 +; GFX9-NEXT: v_add3_u32 v0, s2, v0, -16 +; GFX9-NEXT: v_mov_b32_e32 v1, 15 +; GFX9-NEXT: scratch_store_dword v0, v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX10: ; %bb.0: ; %bb +; GFX10-NEXT: s_add_u32 s0, s0, s5 +; GFX10-NEXT: s_addc_u32 s1, s1, 0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 +; GFX10-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX10-NEXT: v_mov_b32_e32 v1, 15 +; GFX10-NEXT: v_add_nc_u32_e32 v0, s2, v0 +; GFX10-NEXT: scratch_store_dword v0, v1, off offset:-16 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX940-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX940: ; %bb.0: ; %bb +; GFX940-NEXT: v_add_u32_e32 v0, s1, v0 +; GFX940-NEXT: v_add3_u32 v0, s0, v0, -16 +; GFX940-NEXT: v_mov_b32_e32 v1, 15 +; GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1 +; GFX940-NEXT: s_waitcnt vmcnt(0) +; GFX940-NEXT: s_endpgm +; +; GFX11-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX11: ; %bb.0: ; %bb +; GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX12: ; %bb.0: ; %bb +; GFX12-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; GFX12-NEXT: scratch_store_b32 v0, v1, off offset:-16 scope:SCOPE_SYS +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm +; +; UNALIGNED_GFX9-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX9: ; %bb.0: ; %bb +; UNALIGNED_GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s5 +; UNALIGNED_GFX9-NEXT: v_add_u32_e32 v0, s3, v0 +; UNALIGNED_GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 +; UNALIGNED_GFX9-NEXT: v_add3_u32 v0, s2, v0, -16 +; UNALIGNED_GFX9-NEXT: v_mov_b32_e32 v1, 15 +; UNALIGNED_GFX9-NEXT: scratch_store_dword v0, v1, off +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: s_endpgm +; +; UNALIGNED_GFX10-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX10: ; %bb.0: ; %bb +; UNALIGNED_GFX10-NEXT: s_add_u32 s0, s0, s5 +; UNALIGNED_GFX10-NEXT: s_addc_u32 s1, s1, 0 +; UNALIGNED_GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 +; UNALIGNED_GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 +; UNALIGNED_GFX10-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; UNALIGNED_GFX10-NEXT: v_mov_b32_e32 v1, 15 +; UNALIGNED_GFX10-NEXT: v_add_nc_u32_e32 v0, s2, v0 +; UNALIGNED_GFX10-NEXT: scratch_store_dword v0, v1, off offset:-16 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: s_endpgm +; +; UNALIGNED_GFX940-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX940: ; %bb.0: ; %bb +; UNALIGNED_GFX940-NEXT: v_add_u32_e32 v0, s1, v0 +; UNALIGNED_GFX940-NEXT: v_add3_u32 v0, s0, v0, -16 +; UNALIGNED_GFX940-NEXT: v_mov_b32_e32 v1, 15 +; UNALIGNED_GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1 +; UNALIGNED_GFX940-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX940-NEXT: s_endpgm +; +; UNALIGNED_GFX11-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX11: ; %bb.0: ; %bb +; UNALIGNED_GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; UNALIGNED_GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; UNALIGNED_GFX11-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; UNALIGNED_GFX11-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: s_endpgm +; +; UNALIGNED_GFX12-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX12: ; %bb.0: ; %bb +; UNALIGNED_GFX12-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; UNALIGNED_GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; UNALIGNED_GFX12-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; UNALIGNED_GFX12-NEXT: scratch_store_b32 v0, v1, off offset:-16 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: s_endpgm +bb: + %add1 = add nsw i32 %sidx, %vidx + %add2 = add nsw i32 %add1, -16 + %gep = getelementptr inbounds [16 x i8], ptr addrspace(5) %sgpr_base, i32 0, i32 %add2 + store volatile i32 15, ptr addrspace(5) %gep, align 4 + ret void +} + define amdgpu_gs void @sgpr_base_negative_offset(ptr addrspace(1) %out, ptr addrspace(5) inreg %scevgep) { ; GFX9-LABEL: sgpr_base_negative_offset: ; GFX9: ; %bb.0: ; %entry diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll index 0577117e9d9e..d81faf91801b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll @@ -10,10 +10,10 @@ define float @v_pow_f32(float %x, float %y) { ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -25,19 +25,19 @@ define float @v_pow_f32(float %x, float %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -49,19 +49,19 @@ define float @v_pow_f32(float %x, float %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX9-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -73,17 +73,18 @@ define float @v_pow_f32(float %x, float %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_f32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 @@ -91,32 +92,34 @@ define float @v_pow_f32(float %x, float %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %pow = call float @llvm.pow.f32(float %x, float %y) ret float %pow @@ -127,111 +130,114 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_mov_b32_e32 v4, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v5, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4 -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v4, 1.0, v5, s[4:5] +; GFX6-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v5 +; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4 ; GFX6-NEXT: v_log_f32_e32 v0, v0 -; GFX6-NEXT: v_mul_f32_e32 v1, v1, v4 +; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v4 ; GFX6-NEXT: v_log_f32_e32 v1, v1 -; GFX6-NEXT: v_mov_b32_e32 v6, 0x42000000 -; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc -; GFX6-NEXT: v_sub_f32_e32 v0, v0, v7 -; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5] +; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX6-NEXT: v_sub_f32_e32 v0, v0, v6 +; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5] ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 ; GFX6-NEXT: v_sub_f32_e32 v1, v1, v5 -; GFX6-NEXT: v_mov_b32_e32 v7, 0x42800000 +; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 -; GFX6-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc ; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2 -; GFX6-NEXT: v_add_f32_e32 v0, v0, v8 -; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v7, s[4:5] +; GFX6-NEXT: v_add_f32_e32 v0, v0, v7 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5] ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_exp_f32_e32 v1, v1 -; GFX6-NEXT: v_mov_b32_e32 v4, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX6-NEXT: v_cndmask_b32_e64 v2, 1.0, v4, s[4:5] -; GFX6-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX6-NEXT: v_not_b32_e32 v4, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5] +; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_v2f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v4, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v5, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4 -; GFX8-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4 -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v6 -; GFX8-NEXT: v_cndmask_b32_e64 v4, 1.0, v5, s[4:5] +; GFX8-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; GFX8-NEXT: v_ldexp_f32 v0, v0, v5 +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4 ; GFX8-NEXT: v_log_f32_e32 v0, v0 -; GFX8-NEXT: v_mul_f32_e32 v1, v1, v4 +; GFX8-NEXT: v_ldexp_f32 v1, v1, v4 ; GFX8-NEXT: v_log_f32_e32 v1, v1 -; GFX8-NEXT: v_mov_b32_e32 v6, 0x42000000 -; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc -; GFX8-NEXT: v_sub_f32_e32 v0, v0, v7 -; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5] +; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v6 +; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5] ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 ; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 ; GFX8-NEXT: v_sub_f32_e32 v1, v1, v5 -; GFX8-NEXT: v_mov_b32_e32 v7, 0x42800000 +; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 -; GFX8-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc ; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2 -; GFX8-NEXT: v_add_f32_e32 v0, v0, v8 -; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v7, s[4:5] +; GFX8-NEXT: v_add_f32_e32 v0, v0, v7 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5] ; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX8-NEXT: v_exp_f32_e32 v1, v1 -; GFX8-NEXT: v_mov_b32_e32 v4, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e64 v2, 1.0, v4, s[4:5] -; GFX8-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX8-NEXT: v_not_b32_e32 v4, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5] +; GFX8-NEXT: v_ldexp_f32 v1, v1, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_v2f32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v4, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v5, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v4, 1.0, v5, s[4:5] +; GFX9-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; GFX9-NEXT: v_ldexp_f32 v0, v0, v5 +; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4 ; GFX9-NEXT: v_log_f32_e32 v0, v0 -; GFX9-NEXT: v_mul_f32_e32 v1, v1, v4 +; GFX9-NEXT: v_ldexp_f32 v1, v1, v4 ; GFX9-NEXT: v_log_f32_e32 v1, v1 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x42000000 -; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc -; GFX9-NEXT: v_sub_f32_e32 v0, v0, v7 -; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000 +; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc +; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6 +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5] ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2 ; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 ; GFX9-NEXT: v_sub_f32_e32 v1, v1, v5 -; GFX9-NEXT: v_mov_b32_e32 v7, 0x42800000 +; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc ; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2 -; GFX9-NEXT: v_add_f32_e32 v0, v0, v8 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v7, s[4:5] +; GFX9-NEXT: v_add_f32_e32 v0, v0, v7 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5] ; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_exp_f32_e32 v1, v1 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, v4, s[4:5] -; GFX9-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX9-NEXT: v_not_b32_e32 v4, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5] +; GFX9-NEXT: v_ldexp_f32 v1, v1, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_v2f32: @@ -239,10 +245,12 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x4f800000, s4 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v4 -; GFX10-NEXT: v_mul_f32_e32 v1, v1, v5 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4 +; GFX10-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v4 +; GFX10-NEXT: v_ldexp_f32 v1, v1, v5 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 @@ -257,46 +265,54 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) { ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s4 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v3 -; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x1f800000, vcc_lo -; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x1f800000, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s4 ; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v1, v1 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX10-NEXT: v_ldexp_f32 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_v2f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v5, 1.0, 0x4f800000, s0 -; GFX11-NEXT: v_dual_mul_f32 v0, v0, v4 :: v_dual_mul_f32 v1, v1, v5 -; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo +; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ldexp_f32 v1, v1, v5 ; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: v_log_f32_e32 v1, v1 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v0, v0, v2 :: v_dual_mul_dx9_zero_f32 v1, v1, v3 -; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v4, 5, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_ldexp_f32 v0, v0, v4 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo +; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_add_f32 v1, v1, v3 -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x1f800000, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x1f800000, s0 -; GFX11-NEXT: v_exp_f32_e32 v0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3 +; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v1, v1 +; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3 +; GFX11-NEXT: v_ldexp_f32 v1, v1, v3 +; GFX11-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_exp_f32_e32 v0, v0 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] %pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y) ret <2 x float> %pow @@ -316,9 +332,9 @@ define half @v_pow_f16(half %x, half %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -388,18 +404,18 @@ define <2 x half> @v_pow_v2f16(<2 x half> %x, <2 x half> %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_cvt_f32_f16_e32 v2, v3 -; GFX6-NEXT: v_mov_b32_e32 v3, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v3, vcc +; GFX6-NEXT: v_not_b32_e32 v3, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v4 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc ; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_exp_f32_e32 v1, v1 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v6 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v6 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX6-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; @@ -508,17 +524,17 @@ define <2 x half> @v_pow_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y) { ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v2 ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc ; GFX6-NEXT: v_add_f32_e32 v1, v1, v5 -; GFX6-NEXT: v_mov_b32_e32 v5, 0x1f800000 +; GFX6-NEXT: v_not_b32_e32 v5, 63 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v3 -; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc ; GFX6-NEXT: v_exp_f32_e32 v1, v1 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_exp_f32_e32 v2, v0 -; GFX6-NEXT: v_mul_f32_e32 v0, v1, v6 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v5, vcc -; GFX6-NEXT: v_mul_f32_e32 v1, v2, v1 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v1, v6 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -634,17 +650,17 @@ define <2 x half> @v_pow_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y) { ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3 ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v5 -; GFX6-NEXT: v_mov_b32_e32 v5, 0x1f800000 +; GFX6-NEXT: v_not_b32_e32 v5, 63 ; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v1, v3 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc ; GFX6-NEXT: v_add_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: v_exp_f32_e32 v1, v1 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v5, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v6 -; GFX6-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v6 +; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -764,17 +780,17 @@ define <2 x half> @v_pow_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y) { ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v2, v3 ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc ; GFX6-NEXT: v_add_f32_e32 v2, v2, v5 -; GFX6-NEXT: v_mov_b32_e32 v5, 0x1f800000 +; GFX6-NEXT: v_not_b32_e32 v5, 63 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 -; GFX6-NEXT: v_cndmask_b32_e32 v6, 1.0, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v3 ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc ; GFX6-NEXT: v_exp_f32_e32 v2, v2 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v1, v0 -; GFX6-NEXT: v_mul_f32_e32 v0, v2, v6 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v5, vcc -; GFX6-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v2, v6 +; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] @@ -885,10 +901,10 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) { ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX6-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -900,19 +916,19 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_f32_fabs_lhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX8-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -924,19 +940,19 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_f32_fabs_lhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX9-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -948,17 +964,18 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_f32_fabs_lhs: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| -; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 -; GFX10-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 @@ -966,9 +983,9 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_f32_fabs_lhs: @@ -976,23 +993,24 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 -; GFX11-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %fabs.x = call float @llvm.fabs.f32(float %x) %pow = call float @llvm.pow.f32(float %fabs.x, float %y) @@ -1004,10 +1022,10 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) { ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1019,19 +1037,19 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_f32_fabs_rhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1043,19 +1061,19 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_f32_fabs_rhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX9-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1067,17 +1085,18 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_f32_fabs_rhs: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 @@ -1085,32 +1104,34 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_f32_fabs_rhs: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %fabs.y = call float @llvm.fabs.f32(float %y) %pow = call float @llvm.pow.f32(float %x, float %fabs.y) @@ -1122,10 +1143,10 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX6-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1137,19 +1158,19 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX8-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1161,19 +1182,19 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX9-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1185,17 +1206,18 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0| -; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 -; GFX10-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 @@ -1203,9 +1225,9 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs: @@ -1213,23 +1235,24 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 -; GFX11-NEXT: v_mul_f32_e64 v0, |v0|, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1| -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %fabs.x = call float @llvm.fabs.f32(float %x) %fabs.y = call float @llvm.fabs.f32(float %y) @@ -1241,10 +1264,10 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { ; GFX6-LABEL: v_pow_f32_sgpr_vgpr: ; GFX6: ; %bb.0: ; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX6-NEXT: v_ldexp_f32_e32 v1, s0, v1 ; GFX6-NEXT: v_log_f32_e32 v1, v1 ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1256,18 +1279,18 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_pow_f32_sgpr_vgpr: ; GFX8: ; %bb.0: ; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX8-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX8-NEXT: v_ldexp_f32 v1, s0, v1 ; GFX8-NEXT: v_log_f32_e32 v1, v1 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1279,18 +1302,18 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_pow_f32_sgpr_vgpr: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX9-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX9-NEXT: v_ldexp_f32 v1, s0, v1 ; GFX9-NEXT: v_log_f32_e32 v1, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1302,49 +1325,51 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_pow_f32_sgpr_vgpr: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1 -; GFX10-NEXT: v_mul_f32_e32 v1, s0, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX10-NEXT: v_ldexp_f32 v1, s0, v1 ; GFX10-NEXT: v_log_f32_e32 v1, v1 ; GFX10-NEXT: v_sub_f32_e32 v1, v1, v2 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_pow_f32_sgpr_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s1 -; GFX11-NEXT: v_mul_f32_e32 v1, s0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f32 v1, s0, v1 ; GFX11-NEXT: v_log_f32_e32 v1, v1 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v1, v1, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: ; return to shader part epilog %pow = call float @llvm.pow.f32(float %x, float %y) ret float %pow @@ -1354,10 +1379,10 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { ; GFX6-LABEL: v_pow_f32_vgpr_sgpr: ; GFX6: ; %bb.0: ; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -1369,18 +1394,18 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_pow_f32_vgpr_sgpr: ; GFX8: ; %bb.0: ; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -1392,18 +1417,18 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_pow_f32_vgpr_sgpr: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -1415,16 +1440,17 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_pow_f32_vgpr_sgpr: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1432,31 +1458,33 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_pow_f32_vgpr_sgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: ; return to shader part epilog %pow = call float @llvm.pow.f32(float %x, float %y) ret float %pow @@ -1466,10 +1494,10 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { ; GFX6-LABEL: v_pow_f32_sgpr_sgpr: ; GFX6: ; %bb.0: ; GFX6-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; GFX6-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX6-NEXT: v_ldexp_f32_e32 v0, s0, v0 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -1481,18 +1509,18 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: v_pow_f32_sgpr_sgpr: ; GFX8: ; %bb.0: ; GFX8-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX8-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -1504,18 +1532,18 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: v_pow_f32_sgpr_sgpr: ; GFX9: ; %bb.0: ; GFX9-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX9-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -1527,49 +1555,51 @@ define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: v_pow_f32_sgpr_sgpr: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0 -; GFX10-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s2 -; GFX10-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX10-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: v_pow_f32_sgpr_sgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s2 -; GFX11-NEXT: v_mul_f32_e32 v0, s0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: ; return to shader part epilog %pow = call float @llvm.pow.f32(float %x, float %y) ret float %pow @@ -1580,10 +1610,10 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) { ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX6-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX6-NEXT: v_ldexp_f32_e64 v0, -v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1595,19 +1625,19 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_f32_fneg_lhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX8-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, -v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1619,19 +1649,19 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_f32_fneg_lhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX9-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX9-NEXT: v_ldexp_f32 v0, -v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1643,17 +1673,18 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_f32_fneg_lhs: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, -v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s4 -; GFX10-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX10-NEXT: v_ldexp_f32 v0, -v0, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 @@ -1661,9 +1692,9 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_f32_fneg_lhs: @@ -1671,23 +1702,24 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s0 -; GFX11-NEXT: v_mul_f32_e64 v0, -v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_ldexp_f32 v0, -v0, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %neg.x = fneg float %x %pow = call float @llvm.pow.f32(float %neg.x, float %y) @@ -1699,10 +1731,10 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) { ; GFX6: ; %bb.0: ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX6-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2 ; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1714,19 +1746,19 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) { ; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX6-NEXT: v_exp_f32_e32 v0, v0 -; GFX6-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX6-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX6-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX6-NEXT: v_not_b32_e32 v1, 63 +; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX6-NEXT: s_setpc_b64 s[30:31] ; ; GFX8-LABEL: v_pow_f32_fneg_rhs: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX8-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1738,19 +1770,19 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) { ; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_exp_f32_e32 v0, v0 -; GFX8-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX8-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_pow_f32_fneg_rhs: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4f800000 ; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX9-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc @@ -1762,17 +1794,18 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) { ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_exp_f32_e32 v0, v0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX9-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-NEXT: v_not_b32_e32 v1, 63 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_pow_f32_fneg_rhs: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo ; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2 @@ -1780,32 +1813,34 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) { ; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo ; GFX10-NEXT: v_exp_f32_e32 v0, v0 -; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_pow_f32_fneg_rhs: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, -v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %neg.y = fneg float %y %pow = call float @llvm.pow.f32(float %x, float %neg.y) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir index 55015c6d13d8..cdb67caea12c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir @@ -20,8 +20,8 @@ body: | ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]] ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec ; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_1]] - ; GFX11-TRUE16-NEXT: [[V_CMP_F_F16_t16_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F16_t16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec - ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_t16_e64_]] + ; GFX11-TRUE16-NEXT: [[V_CMP_F_F16_fake16_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F16_fake16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec + ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_fake16_e64_]] ; ; GFX11-FAKE16-LABEL: name: fcmp_false_f16 ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1 @@ -58,8 +58,8 @@ body: | ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]] ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec ; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_1]] - ; GFX11-TRUE16-NEXT: [[V_CMP_TRU_F16_t16_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F16_t16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec - ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_t16_e64_]] + ; GFX11-TRUE16-NEXT: [[V_CMP_TRU_F16_fake16_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F16_fake16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec + ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_fake16_e64_]] ; ; GFX11-FAKE16-LABEL: name: fcmp_true_f16 ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir index 4241f945a87d..ed811d37c3d0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir @@ -20,8 +20,8 @@ body: | ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]] ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec ; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_1]] - ; GFX11-TRUE16-NEXT: [[V_CMP_F_F16_t16_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F16_t16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec - ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_t16_e64_]] + ; GFX11-TRUE16-NEXT: [[V_CMP_F_F16_fake16_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F16_fake16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec + ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_fake16_e64_]] ; ; GFX11-FAKE16-LABEL: name: fcmp_false_f16 ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1 @@ -58,8 +58,8 @@ body: | ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]] ; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, 0, implicit $mode, implicit $exec ; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_1]] - ; GFX11-TRUE16-NEXT: [[V_CMP_TRU_F16_t16_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F16_t16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec - ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_t16_e64_]] + ; GFX11-TRUE16-NEXT: [[V_CMP_TRU_F16_fake16_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F16_fake16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec + ; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_fake16_e64_]] ; ; GFX11-FAKE16-LABEL: name: fcmp_true_f16 ; GFX11-FAKE16: liveins: $vgpr0, $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll index eeb7b138fde3..fe002d69faf6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll @@ -18,9 +18,9 @@ define i16 @v_powi_f16(i16 %l, i32 %r) { ; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc ; GFX7-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX7-NEXT: v_exp_f32_e32 v0, v0 -; GFX7-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX7-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-NEXT: v_not_b32_e32 v1, 63 +; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; @@ -75,53 +75,80 @@ define i16 @v_powi_f16(i16 %l, i32 %r) { } define float @v_powi_f32(float %l, i32 %r) { -; GFX78-LABEL: v_powi_f32: -; GFX78: ; %bb.0: -; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX78-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX78-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; GFX78-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GFX78-NEXT: v_cndmask_b32_e32 v2, 1.0, v3, vcc -; GFX78-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX78-NEXT: v_log_f32_e32 v0, v0 -; GFX78-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GFX78-NEXT: v_mov_b32_e32 v2, 0x42000000 -; GFX78-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc -; GFX78-NEXT: v_sub_f32_e32 v0, v0, v2 -; GFX78-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 -; GFX78-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GFX78-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GFX78-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX78-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GFX78-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX78-NEXT: v_exp_f32_e32 v0, v0 -; GFX78-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX78-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX78-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX78-NEXT: s_setpc_b64 s[30:31] +; GFX7-LABEL: v_powi_f32: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX7-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GFX7-NEXT: v_log_f32_e32 v0, v0 +; GFX7-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX7-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX7-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX7-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX7-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX7-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX7-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX7-NEXT: v_exp_f32_e32 v0, v0 +; GFX7-NEXT: v_not_b32_e32 v1, 63 +; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_powi_f32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX8-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX8-NEXT: v_log_f32_e32 v0, v0 +; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX8-NEXT: v_exp_f32_e32 v0, v0 +; GFX8-NEXT: v_not_b32_e32 v1, 63 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: v_powi_f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 ; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_log_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x1f800000, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_exp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff -; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] %res = call float @llvm.powi.f32.i32(float %l, i32 %r) ret float %res diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir index 5378ce2d1efa..10517a49e697 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir @@ -491,3 +491,132 @@ body: | %1:_(p5) = G_DYN_STACKALLOC %0, 32 S_ENDPGM 0, implicit %1 ... + +--- +name: test_dyn_stackalloc_vgpr_align4 +legalized: true +frameInfo: + maxAlignment: 4 +stack: + - { id: 0, type: variable-sized, alignment: 4 } +body: | + bb.0: + liveins: $vgpr0 + + ; WAVE64-LABEL: name: test_dyn_stackalloc_vgpr_align4 + ; WAVE64: liveins: $vgpr0 + ; WAVE64-NEXT: {{ $}} + ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE64-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.wave.reduce.umax), [[COPY]](s32), 0 + ; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 + ; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32) + ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg + ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5) + ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32) + ; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5) + ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5) + ; + ; WAVE32-LABEL: name: test_dyn_stackalloc_vgpr_align4 + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.wave.reduce.umax), [[COPY]](s32), 0 + ; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 + ; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg + ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5) + ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32) + ; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5) + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5) + %0:_(s32) = COPY $vgpr0 + %1:_(p5) = G_DYN_STACKALLOC %0, 4 + S_ENDPGM 0, implicit %1 +... + +--- +name: test_dyn_stackalloc_vgpr_align16 +legalized: true +frameInfo: + maxAlignment: 16 +stack: + - { id: 0, type: variable-sized, alignment: 16 } +body: | + bb.0: + liveins: $vgpr0 + + ; WAVE64-LABEL: name: test_dyn_stackalloc_vgpr_align16 + ; WAVE64: liveins: $vgpr0 + ; WAVE64-NEXT: {{ $}} + ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE64-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.wave.reduce.umax), [[COPY]](s32), 0 + ; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 + ; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32) + ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg + ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5) + ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32) + ; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD]](p5) + ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5) + ; + ; WAVE32-LABEL: name: test_dyn_stackalloc_vgpr_align16 + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.wave.reduce.umax), [[COPY]](s32), 0 + ; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 + ; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg + ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sgpr(p5) = COPY [[COPY1]](p5) + ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY2]], [[SHL]](s32) + ; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD]](p5) + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](p5) + %0:_(s32) = COPY $vgpr0 + %1:_(p5) = G_DYN_STACKALLOC %0, 16 + S_ENDPGM 0, implicit %1 +... + +--- +name: test_dyn_stackalloc_vgpr_align64 +legalized: true +frameInfo: + maxAlignment: 64 +stack: + - { id: 0, type: variable-sized, alignment: 64 } +body: | + bb.0: + liveins: $vgpr0 + + ; WAVE64-LABEL: name: test_dyn_stackalloc_vgpr_align64 + ; WAVE64: liveins: $vgpr0 + ; WAVE64-NEXT: {{ $}} + ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE64-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.wave.reduce.umax), [[COPY]](s32), 0 + ; WAVE64-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 + ; WAVE64-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32) + ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg + ; WAVE64-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4095 + ; WAVE64-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C1]](s32) + ; WAVE64-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096 + ; WAVE64-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32) + ; WAVE64-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[PTRMASK]], [[SHL]](s32) + ; WAVE64-NEXT: $sp_reg = COPY [[PTR_ADD1]](p5) + ; WAVE64-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5) + ; + ; WAVE32-LABEL: name: test_dyn_stackalloc_vgpr_align64 + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.wave.reduce.umax), [[COPY]](s32), 0 + ; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 + ; WAVE32-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[INTRINSIC_CONVERGENT]], [[C]](s32) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg + ; WAVE32-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2047 + ; WAVE32-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[C1]](s32) + ; WAVE32-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048 + ; WAVE32-NEXT: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32) + ; WAVE32-NEXT: [[PTR_ADD1:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[PTRMASK]], [[SHL]](s32) + ; WAVE32-NEXT: $sp_reg = COPY [[PTR_ADD1]](p5) + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[PTRMASK]](p5) + %0:_(s32) = COPY $vgpr0 + %1:_(p5) = G_DYN_STACKALLOC %0, 64 + S_ENDPGM 0, implicit %1 +... diff --git a/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll b/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll new file mode 100644 index 000000000000..52259c4c2e6e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll @@ -0,0 +1,193 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s + +; Reduce a 64-bit add by a constant if we know the low 32-bits are all +; zero. + +; add i64:x, K if computeTrailingZeros(K) >= 32 +; => build_pair (add x.hi, K.hi), x.lo + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0x40000 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_1(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 4294967296 ; (1 << 32) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_2(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 2 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 8589934592 ; (1 << 33) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_3(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0x80000000 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_4(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0x40000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_1(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 4294967296 ; (1 << 32) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_2(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 2, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 8589934592 ; (1 << 33) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_3(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_4(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_high_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_u32 s0, s0, -1 +; GFX9-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 4294967295 ; (1 << 31) + ret i64 %add +} + +define i64 @v_add_i64_const_high_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 4294967295 ; (1 << 31) + ret i64 %add +} + +define <2 x i64> @v_add_v2i64_splat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_add_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, 1, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %add +} + +define <2 x i64> @v_add_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_add_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, 2, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %add +} + +define amdgpu_ps <2 x i64> @s_add_v2i64_splat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_add_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: s_add_i32 s3, s3, 1 +; GFX9-NEXT: ; return to shader part epilog + %add = add <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %add +} + +define amdgpu_ps <2 x i64> @s_add_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_add_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: s_add_i32 s3, s3, 2 +; GFX9-NEXT: ; return to shader part epilog + %add = add <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %add +} + +; We could reduce this to use a 32-bit add if we use computeKnownBits +define i64 @v_add_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) { +; GFX9-LABEL: v_add_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %add = add i64 %reg, %in.high.bits + ret i64 %add +} + +; We could reduce this to use a 32-bit add if we use computeKnownBits +define amdgpu_ps i64 @s_add_i64_variable_high_bits_known0_0(i64 inreg %reg, i32 inreg %offset.hi32) { +; GFX9-LABEL: s_add_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_u32 s0, s0, 0 +; GFX9-NEXT: s_addc_u32 s1, s1, s2 +; GFX9-NEXT: ; return to shader part epilog + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %add = add i64 %reg, %in.high.bits + ret i64 %add +} diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll index 5b72795ba07e..b128be2186df 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll @@ -1,8 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s -;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s -;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX1030 %s -;RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX1100 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s define float @fmul_select_f32_test1(float %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX7-LABEL: fmul_select_f32_test1: @@ -21,22 +25,22 @@ define float @fmul_select_f32_test1(float %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f32_test1: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test1: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f32_test1: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f32_test1: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float 2.000000e+00, float 1.000000e+00 %ldexp = fmul float %x, %y @@ -60,22 +64,22 @@ define float @fmul_select_f32_test2(float %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f32_test2: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test2: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f32_test2: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f32_test2: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float 5.000000e-01, float 1.000000e+00 %ldexp = fmul float %x, %y @@ -83,49 +87,71 @@ define float @fmul_select_f32_test2(float %x, i32 %bool.arg1, i32 %bool.arg2) { } define <2 x float> @fmul_select_v2f32_test3(<2 x float> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) { -; GFX7-LABEL: fmul_select_v2f32_test3: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX7-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX7-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX7-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_v2f32_test3: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_v2f32_test3: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f32_test3: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 -; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_v2f32_test3: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_v2f32_test3: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_v2f32_test3: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_v2f32_test3: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc +; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-GISEL-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: fmul_select_v2f32_test3: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo +; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_v2f32_test3: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 +; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x float> <float 2.000000e+00, float 2.000000e+00>, <2 x float> <float 1.000000e+00, float 1.000000e+00> %ldexp = fmul <2 x float> %x, %y @@ -133,49 +159,71 @@ define <2 x float> @fmul_select_v2f32_test3(<2 x float> %x, <2 x i32> %bool.arg1 } define <2 x float> @fmul_select_v2f32_test4(<2 x float> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) { -; GFX7-LABEL: fmul_select_v2f32_test4: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX7-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX7-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX7-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_v2f32_test4: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX9-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_v2f32_test4: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1030-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f32_test4: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1100-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 -; GFX1100-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_v2f32_test4: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_v2f32_test4: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_v2f32_test4: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_v2f32_test4: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc +; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-GISEL-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: fmul_select_v2f32_test4: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo +; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_v2f32_test4: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 +; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x float> <float 5.000000e-01, float 5.000000e-01>, <2 x float> <float 1.000000e+00, float 1.000000e+00> %ldexp = fmul <2 x float> %x, %y @@ -199,22 +247,22 @@ define float @fmul_select_f32_test5(float %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f32_test5: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test5: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f32_test5: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, vcc_lo +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f32_test5: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, -1.0, -2.0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float -2.000000e+00, float -1.000000e+00 %ldexp = fmul float %x, %y @@ -222,44 +270,83 @@ define float @fmul_select_f32_test5(float %x, i32 %bool.arg1, i32 %bool.arg2) { } define float @fmul_select_f32_test6(float %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f32_test6: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v3, 0x41000000 -; GFX7-NEXT: v_mov_b32_e32 v4, 0xc0400000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f32_test6: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x41000000 -; GFX9-NEXT: v_mov_b32_e32 v4, 0xc0400000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f32_test6: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0xc0400000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x41000000, v3, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test6: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v3, 0xc0400000 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x41000000, v3, vcc_lo -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f32_test6: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0x41000000 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, 0xc0400000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f32_test6: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0xc0400000 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0x41000000 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f32_test6: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x41000000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xc0400000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f32_test6: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xc0400000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x41000000 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f32_test6: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xc0400000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x41000000, v3, vcc_lo +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f32_test6: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x41000000 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc0400000, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f32_test6: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0xc0400000 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x41000000, v3, vcc_lo +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f32_test6: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x41000000 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc0400000, vcc_lo +; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float -3.000000e+00, float 8.000000e+00 %ldexp = fmul float %x, %y @@ -285,22 +372,22 @@ define float @fmul_select_f32_test7_sel_log2val_pos59_pos92(float %x, i32 %bool. ; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f32_test7_sel_log2val_pos59_pos92: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 0x5c, 59, vcc_lo -; GFX1030-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test7_sel_log2val_pos59_pos92: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0x5c, 59, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f32_test7_sel_log2val_pos59_pos92: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0x5c, 59, vcc_lo +; GFX10-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f32_test7_sel_log2val_pos59_pos92: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0x5c, 59, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float 0x43A0000000000000, float 0x45B0000000000000 %ldexp = fmul float %x, %y @@ -308,44 +395,83 @@ define float @fmul_select_f32_test7_sel_log2val_pos59_pos92(float %x, i32 %bool. } define float @fmul_select_f32_test8(float %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f32_test8: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v3, 0xc1000000 -; GFX7-NEXT: v_mov_b32_e32 v4, 0x41800000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f32_test8: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0xc1000000 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x41800000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f32_test8: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0x41800000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0xc1000000, v3, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test8: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v3, 0x41800000 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0xc1000000, v3, vcc_lo -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f32_test8: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0xc1000000 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, 0x41800000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f32_test8: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0x41800000 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0xc1000000 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f32_test8: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xc1000000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x41800000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f32_test8: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x41800000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xc1000000 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f32_test8: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x41800000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xc1000000, v3, vcc_lo +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f32_test8: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1000000 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x41800000, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f32_test8: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x41800000 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xc1000000, v3, vcc_lo +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f32_test8: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1000000 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x41800000, vcc_lo +; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float 1.600000e+01, float -8.000000e+00 %ldexp = fmul float %x, %y @@ -369,22 +495,22 @@ define float @fmul_select_f32_test9(float %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f32_test9: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 2.0, 0, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test9: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 2.0, 0, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f32_test9: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 2.0, 0, vcc_lo +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f32_test9: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 2.0, 0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float 0.000000e+00, float 2.000000e+00 %ldexp = fmul float %x, %y @@ -410,22 +536,22 @@ define float @fmul_select_f32_test10(float %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f32_test10: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test10: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f32_test10: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo +; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f32_test10: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float -0.000000e+00, float 0.000000e+00 %ldexp = fmul float %x, %y @@ -451,22 +577,22 @@ define float @fmul_select_f32_test11_sel_log2val_pos78_pos56(float %x, i32 %bool ; GFX9-NEXT: v_ldexp_f32 v0, -v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f32_test11_sel_log2val_pos78_pos56: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 56, 0x4e, vcc_lo -; GFX1030-NEXT: v_ldexp_f32 v0, -v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test11_sel_log2val_pos78_pos56: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 56, 0x4e, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f32 v0, -v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f32_test11_sel_log2val_pos78_pos56: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 56, 0x4e, vcc_lo +; GFX10-NEXT: v_ldexp_f32 v0, -v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f32_test11_sel_log2val_pos78_pos56: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 56, 0x4e, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f32 v0, -v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float 0xC4D0000000000000, float 0xC370000000000000 %ldexp = fmul float %x, %y @@ -474,44 +600,83 @@ define float @fmul_select_f32_test11_sel_log2val_pos78_pos56(float %x, i32 %bool } define float @fmul_select_f32_test12_sel_log2val_neg48_pos68(float %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v3, 0x44 -; GFX7-NEXT: v_not_b32_e32 v4, 47 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x44 -; GFX9-NEXT: v_not_b32_e32 v4, 47 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_not_b32_e32 v3, 47 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x44, v3, vcc_lo -; GFX1030-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_not_b32_e32 v3, 47 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x44, v3, vcc_lo -; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0x44 +; GFX7-SDAG-NEXT: v_not_b32_e32 v4, 47 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_not_b32_e32 v3, 47 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0x44 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x44 +; GFX9-SDAG-NEXT: v_not_b32_e32 v4, 47 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_not_b32_e32 v3, 47 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x44 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_not_b32_e32 v3, 47 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x44, v3, vcc_lo +; GFX10-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x44 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xffffffd0, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_not_b32_e32 v3, 47 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x44, v3, vcc_lo +; GFX11-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f32_test12_sel_log2val_neg48_pos68: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x44 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xffffffd0, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, float 0x3CF0000000000000, float 0x4430000000000000 %ldexp = fmul float %x, %y @@ -535,22 +700,22 @@ define double @fmul_select_f64_test1(double %x, i32 %bool.arg1, i32 %bool.arg2) ; GFX9-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f64_test1: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test1: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f64_test1: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test1: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double 2.000000e+00, double 1.000000e+00 %ldexp = fmul double %x, %y @@ -574,22 +739,22 @@ define double @fmul_select_f64_test2(double %x, i32 %bool.arg1, i32 %bool.arg2) ; GFX9-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f64_test2: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test2: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f64_test2: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test2: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double 5.000000e-01, double 1.000000e+00 %ldexp = fmul double %x, %y @@ -619,28 +784,28 @@ define <2 x double> @fmul_select_v2f64_test3(<2 x double> %x, <2 x i32> %bool.ar ; GFX9-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_v2f64_test3: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1030-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1030-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 -; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f64_test3: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1100-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 -; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo -; GFX1100-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_v2f64_test3: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_v2f64_test3: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo +; GFX11-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 1.000000e+00> %ldexp = fmul <2 x double> %x, %y @@ -670,28 +835,28 @@ define <2 x double> @fmul_select_v2f64_test4(<2 x double> %x, <2 x i32> %bool.ar ; GFX9-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_v2f64_test4: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1030-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1030-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 -; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f64_test4: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1100-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 -; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo -; GFX1100-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_v2f64_test4: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX10-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_v2f64_test4: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], v[0:1], v4 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo +; GFX11-NEXT: v_ldexp_f64 v[2:3], v[2:3], v5 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x double> <double 5.000000e-01, double 5.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e+00> %ldexp = fmul <2 x double> %x, %y @@ -715,22 +880,22 @@ define double @fmul_select_f64_test5(double %x, i32 %bool.arg1, i32 %bool.arg2) ; GFX9-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f64_test5: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test5: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f64_test5: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test5: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double -5.000000e-01, double -1.000000e+00 %ldexp = fmul double %x, %y @@ -754,22 +919,22 @@ define double @fmul_select_f64_test6(double %x, i32 %bool.arg1, i32 %bool.arg2) ; GFX9-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f64_test6: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test6: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f64_test6: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test6: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double -2.000000e+00, double -1.000000e+00 %ldexp = fmul double %x, %y @@ -777,44 +942,64 @@ define double @fmul_select_f64_test6(double %x, i32 %bool.arg1, i32 %bool.arg2) } define double @fmul_select_f64_test7(double %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f64_test7: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v4, 0xbff00000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX7-NEXT: v_cndmask_b32_e64 v3, v4, 2.0, vcc -; GFX7-NEXT: v_mov_b32_e32 v2, 0 -; GFX7-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f64_test7: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v4, 0xbff00000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, 2.0, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f64_test7: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_mov_b32_e32 v4, 0 -; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo -; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test7: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_mov_b32_e32 v4, 0 -; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f64_test7: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, 0xbff00000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, v4, 2.0, vcc +; GFX7-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX7-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f64_test7: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v5, 0xbff00000 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, 2.0, vcc +; GFX7-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f64_test7: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xbff00000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v4, 2.0, vcc +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f64_test7: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xbff00000 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, 2.0, vcc +; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: fmul_select_f64_test7: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_mov_b32_e32 v4, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo +; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test7: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0xbff00000, 2.0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double 2.000000e+00, double -1.000000e+00 %ldexp = fmul double %x, %y @@ -838,22 +1023,22 @@ define double @fmul_select_f64_test8(double %x, i32 %bool.arg1, i32 %bool.arg2) ; GFX9-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f64_test8: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_cndmask_b32_e64 v2, 5, 2, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test8: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_cndmask_b32_e64 v2, 5, 2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f64_test8: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 5, 2, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test8: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_cndmask_b32_e64 v2, 5, 2, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double -4.000000e+00, double -3.200000e+01 %ldexp = fmul double %x, %y @@ -883,28 +1068,28 @@ define <2 x double> @fmul_select_v2f64_test9(<2 x double> %x, <2 x i32> %bool.ar ; GFX9-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_v2f64_test9: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1030-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1030-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4 -; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v5 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f64_test9: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1100-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4 -; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo -; GFX1100-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v5 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_v2f64_test9: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX10-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo +; GFX10-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v5 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_v2f64_test9: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f64 v[0:1], -v[0:1], v4 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo +; GFX11-NEXT: v_ldexp_f64 v[2:3], -v[2:3], v5 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x double> <double -2.000000e+00, double -2.000000e+00>, <2 x double> <double -1.000000e+00, double -1.000000e+00> %ldexp = fmul <2 x double> %x, %y @@ -912,60 +1097,115 @@ define <2 x double> @fmul_select_v2f64_test9(<2 x double> %x, <2 x i32> %bool.ar } define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) { -; GFX7-LABEL: fmul_select_v2f64_test10: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mov_b32_e32 v8, 0xbff00000 -; GFX7-NEXT: v_mov_b32_e32 v9, 0x3fe00000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6 -; GFX7-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7 -; GFX7-NEXT: v_mov_b32_e32 v8, 0 -; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc -; GFX7-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] -; GFX7-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_v2f64_test10: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v8, 0xbff00000 -; GFX9-NEXT: v_mov_b32_e32 v9, 0x3fe00000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6 -; GFX9-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7 -; GFX9-NEXT: v_mov_b32_e32 v8, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc -; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] -; GFX9-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_v2f64_test10: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v8, 0x3fe00000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1030-NEXT: v_cndmask_b32_e32 v9, 0xbff00000, v8, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1030-NEXT: v_mov_b32_e32 v8, 0 -; GFX1030-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo -; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] -; GFX1030-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f64_test10: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v8, 0x3fe00000 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-NEXT: v_dual_cndmask_b32 v9, 0xbff00000, v8 :: v_dual_mov_b32 v8, 0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 -; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] -; GFX1100-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_v2f64_test10: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mov_b32_e32 v8, 0xbff00000 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v9, 0x3fe00000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v8, 0 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; GFX7-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX7-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_v2f64_test10: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v10, 0xbff00000 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; GFX7-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX7-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_v2f64_test10: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v8, 0xbff00000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v9, 0x3fe00000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v9, v8, v9, vcc +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v8, 0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; GFX9-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX9-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_v2f64_test10: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0xbff00000 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v6 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v5, v7 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX9-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_v2f64_test10: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v8, 0x3fe00000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v9, 0xbff00000, v8, vcc_lo +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v8, 0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX10-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX10-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_v2f64_test10: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v9, 0xbff00000 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v9, v9, 0x3fe00000, vcc_lo +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_v2f64_test10: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v8, 0x3fe00000 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_dual_cndmask_b32 v9, 0xbff00000, v8 :: v_dual_mov_b32 v8, 0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX11-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_v2f64_test10: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v9, 0xbff00000 :: v_dual_mov_b32 v8, 0 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v6 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v9, v9, 0x3fe00000, vcc_lo +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v5, v7 +; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[8:9] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x double> <double 5.000000e-01, double 2.000000e+00>, <2 x double> <double -1.000000e+00, double 1.000000e+00> %ldexp = fmul <2 x double> %x, %y @@ -973,44 +1213,64 @@ define <2 x double> @fmul_select_v2f64_test10(<2 x double> %x, <2 x i32> %bool.a } define double @fmul_select_f64_test11(double %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f64_test11: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_bfrev_b32_e32 v4, 1 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX7-NEXT: v_cndmask_b32_e64 v3, v4, -2.0, vcc -; GFX7-NEXT: v_mov_b32_e32 v2, 0 -; GFX7-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f64_test11: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_bfrev_b32_e32 v4, 1 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, -2.0, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f64_test11: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_mov_b32_e32 v4, 0 -; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0x80000000, -2.0, vcc_lo -; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test11: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_mov_b32_e32 v4, 0 -; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0x80000000, -2.0, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f64_test11: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_bfrev_b32_e32 v4, 1 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, v4, -2.0, vcc +; GFX7-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX7-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f64_test11: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_bfrev_b32_e32 v5, 1 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -2.0, vcc +; GFX7-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f64_test11: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v4, 1 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v4, -2.0, vcc +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f64_test11: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v5, 1 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, -2.0, vcc +; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: fmul_select_f64_test11: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_mov_b32_e32 v4, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x80000000, -2.0, vcc_lo +; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test11: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x80000000, -2.0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double -2.000000e+00, double -0.000000e+00 %ldexp = fmul double %x, %y @@ -1018,45 +1278,84 @@ define double @fmul_select_f64_test11(double %x, i32 %bool.arg1, i32 %bool.arg2) } define double @fmul_select_f64_test12(double %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f64_test12: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v2, v3 -; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX7-NEXT: v_lshlrev_b32_e32 v3, 31, v2 -; GFX7-NEXT: v_mov_b32_e32 v2, 0 -; GFX7-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f64_test12: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v2, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 31, v2 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f64_test12: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_mov_b32_e32 v2, 0 -; GFX1030-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v3, 31, v3 -; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test12: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 31, v3 -; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f64_test12: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v2, v3 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v3, 31, v2 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX7-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f64_test12: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_bfrev_b32_e32 v5, 1 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc +; GFX7-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f64_test12: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v2, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v3, 31, v2 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f64_test12: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v5, 1 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc +; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f64_test12: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v3 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v3, 31, v3 +; GFX10-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f64_test12: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v5, 0x80000000, 0, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f64_test12: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_ne_u32_e32 vcc_lo, v2, v3 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 31, v3 +; GFX11-SDAG-NEXT: v_mul_f64 v[0:1], v[0:1], v[2:3] +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f64_test12: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v5, 0x80000000, 0, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double 0.000000e+00, double -0.000000e+00 %ldexp = fmul double %x, %y @@ -1084,24 +1383,24 @@ define double @fmul_select_f64_test13(double %x, i32 %bool.arg1, i32 %bool.arg2) ; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f64_test13: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_mov_b32_e32 v4, 0 -; GFX1030-NEXT: v_cndmask_b32_e64 v5, 0x40300000, 0, vcc_lo -; GFX1030-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test13: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: v_mov_b32_e32 v4, 0 -; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0x40300000, 0, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f64_test13: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: v_mov_b32_e32 v4, 0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0x40300000, 0, vcc_lo +; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f64_test13: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: v_mov_b32_e32 v4, 0 +; GFX11-NEXT: v_cndmask_b32_e64 v5, 0x40300000, 0, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], v[4:5] +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double 0.000000e+00, double 1.600000e+01 %ldexp = fmul double %x, %y @@ -1109,44 +1408,83 @@ define double @fmul_select_f64_test13(double %x, i32 %bool.arg1, i32 %bool.arg2) } define double @fmul_select_f64_test14_sel_log2val_pos92_neg27(double %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_not_b32_e32 v4, 26 -; GFX7-NEXT: v_mov_b32_e32 v5, 0x5c -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc -; GFX7-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_not_b32_e32 v4, 26 -; GFX9-NEXT: v_mov_b32_e32 v5, 0x5c -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc -; GFX9-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v4, 0x5c -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0xffffffe5, v4, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v4, 0x5c -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0xffffffe5, v4, vcc_lo -; GFX1100-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_not_b32_e32 v4, 26 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v5, 0x5c +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; GFX7-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0x5c +; GFX7-GISEL-NEXT: v_not_b32_e32 v5, 26 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc +; GFX7-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_not_b32_e32 v4, 26 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x5c +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5c +; GFX9-GISEL-NEXT: v_not_b32_e32 v5, 26 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v4, 0x5c +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0xffffffe5, v4, vcc_lo +; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_not_b32_e32 v4, 26 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0x5c, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v4, 0x5c +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, 0xffffffe5, v4, vcc_lo +; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f64_test14_sel_log2val_pos92_neg27: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_not_b32_e32 v4, 26 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0x5c, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double 0x45B0000000000000, double 0x3E40000000000000 %ldexp = fmul double %x, %y @@ -1154,44 +1492,83 @@ define double @fmul_select_f64_test14_sel_log2val_pos92_neg27(double %x, i32 %bo } define double @fmul_select_f64_test15_sel_log2val_neg42_neg33(double %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_not_b32_e32 v4, 32 -; GFX7-NEXT: v_not_b32_e32 v5, 41 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX7-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc -; GFX7-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_not_b32_e32 v4, 32 -; GFX9-NEXT: v_not_b32_e32 v5, 41 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc -; GFX9-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_not_b32_e32 v4, 41 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0xffffffdf, v4, vcc_lo -; GFX1030-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_not_b32_e32 v4, 41 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0xffffffdf, v4, vcc_lo -; GFX1100-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_not_b32_e32 v4, 32 +; GFX7-SDAG-NEXT: v_not_b32_e32 v5, 41 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; GFX7-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_not_b32_e32 v4, 41 +; GFX7-GISEL-NEXT: v_not_b32_e32 v5, 32 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc +; GFX7-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_not_b32_e32 v4, 32 +; GFX9-SDAG-NEXT: v_not_b32_e32 v5, 41 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_not_b32_e32 v4, 41 +; GFX9-GISEL-NEXT: v_not_b32_e32 v5, 32 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_not_b32_e32 v4, 41 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0xffffffdf, v4, vcc_lo +; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_not_b32_e32 v4, 32 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0xffffffd6, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_not_b32_e32 v4, 41 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, 0xffffffdf, v4, vcc_lo +; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f64_test15_sel_log2val_neg42_neg33: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_not_b32_e32 v4, 32 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0xffffffd6, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, double 0x3D50000000000000, double 0x3DE0000000000000 %ldexp = fmul double %x, %y @@ -1200,40 +1577,82 @@ define double @fmul_select_f64_test15_sel_log2val_neg42_neg33(double %x, i32 %bo define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test1: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f16_test1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f16_test1: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo -; GFX1030-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test1: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test1: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test1: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f16_test1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f16_test1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f16_test1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f16_test1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f16_test1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f16_test1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half 2.000000e+00, half 1.000000e+00 %ldexp = fmul half %x, %y @@ -1241,47 +1660,89 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) { } define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test2: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f16_test2: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc -; GFX9-NEXT: s_movk_i32 s4, 0x8000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff -; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2 -; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f16_test2: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: s_movk_i32 s4, 0x8000 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo -; GFX1030-NEXT: v_med3_i32 v1, v1, s4, 0x7fff -; GFX1030-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test2: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_movk_i32 s0, 0x8000 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_med3_i32 v1, v1, s0, 0x7fff -; GFX1100-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test2: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test2: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f16_test2: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX9-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2 +; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f16_test2: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f16_test2: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff +; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f16_test2: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f16_test2: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_med3_i32 v1, v1, s0, 0x7fff +; GFX11-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f16_test2: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half 5.000000e-01, half 1.000000e+00 %ldexp = fmul half %x, %y @@ -1289,59 +1750,126 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) { } define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) { -; GFX7-LABEL: fmul_select_v2f16_test3: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX7-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX7-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc -; GFX7-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_v2f16_test3: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v5, 0x3c00 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x4000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc -; GFX9-NEXT: v_pack_b32_f16 v1, v1, v2 -; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_v2f16_test3: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v5, 0x4000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo -; GFX1030-NEXT: v_pack_b32_f16 v1, v1, v2 -; GFX1030-NEXT: v_pk_mul_f16 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f16_test3: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v5, 0x4000 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo -; GFX1100-NEXT: v_pack_b32_f16 v1, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_pk_mul_f16 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_v2f16_test3: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_v2f16_test3: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v3 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_v2f16_test3: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x3c00 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x4000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc +; GFX9-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX9-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_v2f16_test3: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4 +; GFX9-GISEL-NEXT: v_med3_i32 v2, v2, v3, v4 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_v2f16_test3: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0x4000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo +; GFX10-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX10-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_v2f16_test3: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1 +; GFX10-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3 +; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_v2f16_test3: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 0x4000 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo +; GFX11-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_v2f16_test3: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v2 +; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x half> <half 2.000000e+00, half 2.000000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00> %ldexp = fmul <2 x half> %x, %y @@ -1349,59 +1877,126 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1, } define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) { -; GFX7-LABEL: fmul_select_v2f16_test4: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1 -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX7-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX7-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc -; GFX7-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_v2f16_test4: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v5, 0x3c00 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x3800 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc -; GFX9-NEXT: v_pack_b32_f16 v1, v1, v2 -; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_v2f16_test4: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v5, 0x3800 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo -; GFX1030-NEXT: v_pack_b32_f16 v1, v1, v2 -; GFX1030-NEXT: v_pk_mul_f16 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2f16_test4: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v5, 0x3800 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo -; GFX1100-NEXT: v_pack_b32_f16 v1, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_pk_mul_f16 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_v2f16_test4: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_v2f16_test4: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v3 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_v2f16_test4: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x3c00 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x3800 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc +; GFX9-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX9-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_v2f16_test4: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4 +; GFX9-GISEL-NEXT: v_med3_i32 v2, v2, v3, v4 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_v2f16_test4: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0x3800 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo +; GFX10-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX10-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_v2f16_test4: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1 +; GFX10-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3 +; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_v2f16_test4: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 0x3800 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo +; GFX11-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_v2f16_test4: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v2 +; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x half> <half 5.000000e-01, half 5.000000e-01>, <2 x half> <half 1.000000e+00, half 1.000000e+00> %ldexp = fmul <2 x half> %x, %y @@ -1409,15 +2004,25 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1, } define half @fmul_select_f16_test5(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test5: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test5: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test5: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: fmul_select_f16_test5: ; GFX9: ; %bb.0: @@ -1427,22 +2032,22 @@ define half @fmul_select_f16_test5(half %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f16_test5: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc_lo -; GFX1030-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test5: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f16_test5: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc_lo +; GFX10-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f16_test5: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half 2.000000e+00, half 8.000000e+00 %ldexp = fmul half %x, %y @@ -1450,46 +2055,88 @@ define half @fmul_select_f16_test5(half %x, i32 %bool.arg1, i32 %bool.arg2) { } define half @fmul_select_f16_test6(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test6: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0x40400000 -; GFX7-NEXT: v_mov_b32_e32 v4, 0xc1000000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f16_test6: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4200 -; GFX9-NEXT: v_mov_b32_e32 v4, 0xc800 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f16_test6: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0xc800 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo -; GFX1030-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test6: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v3, 0xc800 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo -; GFX1100-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test6: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0x40400000 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, 0xc1000000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test6: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0xc800 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0x4200 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f16_test6: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x4200 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xc800 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f16_test6: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xc800 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x4200 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f16_test6: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xc800 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo +; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f16_test6: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x4200 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc800, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f16_test6: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0xc800 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4200, v3, vcc_lo +; GFX11-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f16_test6: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x4200 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc800, vcc_lo +; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half -8.000000e+00, half 3.000000e+00 %ldexp = fmul half %x, %y @@ -1497,45 +2144,87 @@ define half @fmul_select_f16_test6(half %x, i32 %bool.arg1, i32 %bool.arg2) { } define half @fmul_select_f16_test7(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test7: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0x41000000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, -4.0, v3, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f16_test7: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0xc400 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x4800 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f16_test7: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0x4800 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo -; GFX1030-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test7: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v3, 0x4800 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo -; GFX1100-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test7: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0x41000000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, -4.0, v3, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test7: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0x4800 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0xc400 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f16_test7: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xc400 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4800 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f16_test7: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x4800 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xc400 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f16_test7: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x4800 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo +; GFX10-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f16_test7: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xc400 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4800, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f16_test7: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 0x4800 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xc400, v3, vcc_lo +; GFX11-SDAG-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f16_test7: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xc400 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4800, vcc_lo +; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half 8.000000e+00, half -4.000000e+00 %ldexp = fmul half %x, %y @@ -1543,16 +2232,28 @@ define half @fmul_select_f16_test7(half %x, i32 %bool.arg1, i32 %bool.arg2) { } define half @fmul_select_f16_test8(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test8: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_bfrev_b32_e32 v3, 1 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test8: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_bfrev_b32_e32 v3, 1 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test8: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0x8000 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: fmul_select_f16_test8: ; GFX9: ; %bb.0: @@ -1563,22 +2264,22 @@ define half @fmul_select_f16_test8(half %x, i32 %bool.arg1, i32 %bool.arg2) { ; GFX9-NEXT: v_mul_f16_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX1030-LABEL: fmul_select_f16_test8: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo -; GFX1030-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test8: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX10-LABEL: fmul_select_f16_test8: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo +; GFX10-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: fmul_select_f16_test8: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half -0.000000e+00, half 0.000000e+00 %ldexp = fmul half %x, %y @@ -1586,40 +2287,87 @@ define half @fmul_select_f16_test8(half %x, i32 %bool.arg1, i32 %bool.arg2) { } define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test9: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e64 v0, -v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f16_test9: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc -; GFX9-NEXT: v_ldexp_f16_e64 v0, -v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f16_test9: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo -; GFX1030-NEXT: v_ldexp_f16_e64 v0, -v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test9: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_ldexp_f16_e64 v0, -v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test9: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test9: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX7-GISEL-NEXT: v_add_i32_e32 v1, vcc, 5, v1 +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f16_test9: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc +; GFX9-SDAG-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f16_test9: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 5, v1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f16_test9: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo +; GFX10-SDAG-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f16_test9: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 5, v1 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f16_test9: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f16_test9: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v1, 5, v1 +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half -1.600000e+01, half -3.200000e+01 %ldexp = fmul half %x, %y @@ -1627,47 +2375,82 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) { } define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc -; GFX9-NEXT: s_movk_i32 s4, 0x8000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff -; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2 -; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: s_movk_i32 s4, 0x8000 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo -; GFX1030-NEXT: v_med3_i32 v1, v1, s4, 0x7fff -; GFX1030-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_movk_i32 s0, 0x8000 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_med3_i32 v1, v1, s0, 0x7fff -; GFX1100-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX9-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2 +; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo +; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff +; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_med3_i32 v1, v1, s0, 0x7fff +; GFX11-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f16_test10_sel_log2val_neg11_pos11: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 11, -11, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half 0xH1000, half 0xH6800 %ldexp = fmul half %x, %y @@ -1675,47 +2458,82 @@ define half @fmul_select_f16_test10_sel_log2val_neg11_pos11(half %x, i32 %bool.a } define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc -; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc -; GFX9-NEXT: s_movk_i32 s4, 0x8000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff -; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2 -; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: s_movk_i32 s4, 0x8000 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo -; GFX1030-NEXT: v_med3_i32 v1, v1, s4, 0x7fff -; GFX1030-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_movk_i32 s0, 0x8000 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_med3_i32 v1, v1, s0, 0x7fff -; GFX1100-NEXT: v_ldexp_f16_e32 v0, v0, v1 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc +; GFX7-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX9-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2 +; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo +; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff +; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_movk_i32 s0, 0x8000 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_med3_i32 v1, v1, s0, 0x7fff +; GFX11-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_f16_test11_sel_log2val_pos7_neg14: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, -14, 7, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, half 0xH5800, half 0xH0400 %ldexp = fmul half %x, %y @@ -1723,72 +2541,114 @@ define half @fmul_select_f16_test11_sel_log2val_pos7_neg14(half %x, i32 %bool.ar } define bfloat @fmul_select_bf16_test1(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test1: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x3f80 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x4000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test1: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0x4000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test1: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test1: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 1.0, 2.0, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test1: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x3f80 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x4000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat 2.000000e+00, bfloat 1.000000e+00 %ldexp = fmul bfloat %x, %y @@ -1796,72 +2656,114 @@ define bfloat @fmul_select_bf16_test1(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) } define bfloat @fmul_select_bf16_test2(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test2: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test2: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x3f80 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x3f00 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test2: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0x3f00 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test2: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0x3f00 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test2: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 1.0, 0.5, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test2: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test2: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x3f80 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x3f00 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test2: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test2: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x3f00 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test2: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test2: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0x3f00 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test2: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat 5.000000e-01, bfloat 1.000000e+00 %ldexp = fmul bfloat %x, %y @@ -1869,111 +2771,158 @@ define bfloat @fmul_select_bf16_test2(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) } define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) { -; GFX7-LABEL: fmul_select_v2bf16_test3: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; GFX7-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX7-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc -; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_v2bf16_test3: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v5, 0x3f80 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x4000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_mul_f32_e32 v1, v3, v1 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX9-NEXT: v_add3_u32 v3, v3, v1, s4 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_add3_u32 v2, v2, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_v2bf16_test3: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v5, 0x4000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1030-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v1, v3, v1 -; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX1030-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX1030-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX1030-NEXT: v_bfe_u32 v3, v0, 16, 1 -; GFX1030-NEXT: v_add3_u32 v2, v2, v1, 0x7fff -; GFX1030-NEXT: v_or_b32_e32 v5, 0x400000, v0 -; GFX1030-NEXT: v_add3_u32 v3, v3, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo -; GFX1030-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2bf16_test3: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v5, 0x4000 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1100-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX1100-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1100-NEXT: v_or_b32_e32 v5, 0x400000, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-NEXT: v_mul_f32_e32 v1, v3, v1 -; GFX1100-NEXT: v_bfe_u32 v3, v0, 16, 1 -; GFX1100-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-NEXT: v_add3_u32 v3, v3, v0, 0x7fff -; GFX1100-NEXT: v_add3_u32 v2, v2, v1, 0x7fff -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_v2bf16_test3: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 2.0, vcc +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 2.0, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_v2bf16_test3: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v3 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_v2bf16_test3: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x3f80 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x4000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX9-SDAG-NEXT: v_bfe_u32 v3, v1, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-SDAG-NEXT: v_add3_u32 v3, v3, v1, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v2, v0, 16, 1 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_add3_u32 v2, v2, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x7060302 +; GFX9-SDAG-NEXT: v_perm_b32 v0, v0, v1, s4 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_v2bf16_test3: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_v2bf16_test3: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0x4000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo +; GFX10-SDAG-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX10-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-SDAG-NEXT: v_bfe_u32 v2, v1, 16, 1 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v3, v0, 16, 1 +; GFX10-SDAG-NEXT: v_add3_u32 v2, v2, v1, 0x7fff +; GFX10-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v3, v3, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo +; GFX10-SDAG-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_v2bf16_test3: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_v2bf16_test3: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 0x4000 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v3, v0, 16, 1 +; GFX11-SDAG-NEXT: v_bfe_u32 v2, v1, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-NEXT: v_add3_u32 v3, v3, v0, 0x7fff +; GFX11-SDAG-NEXT: v_add3_u32 v2, v2, v1, 0x7fff +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_v2bf16_test3: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x bfloat> <bfloat 2.000000e+00, bfloat 2.000000e+00>, <2 x bfloat> <bfloat 1.000000e+00, bfloat 1.000000e+00> %ldexp = fmul <2 x bfloat> %x, %y @@ -1981,111 +2930,158 @@ define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.a } define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.arg1, <2 x i32> %bool.arg2) { -; GFX7-LABEL: fmul_select_v2bf16_test4: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; GFX7-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 -; GFX7-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc -; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v1, v1, v3 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_v2bf16_test4: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v5, 0x3f80 -; GFX9-NEXT: v_mov_b32_e32 v6, 0x3f00 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_mul_f32_e32 v1, v3, v1 -; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX9-NEXT: v_add3_u32 v3, v3, v1, s4 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: v_bfe_u32 v2, v0, 16, 1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_add3_u32 v2, v2, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc -; GFX9-NEXT: s_mov_b32 s4, 0x7060302 -; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_v2bf16_test4: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v5, 0x3f00 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1030-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX1030-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo -; GFX1030-NEXT: v_mul_f32_e32 v1, v3, v1 -; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX1030-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX1030-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX1030-NEXT: v_bfe_u32 v3, v0, 16, 1 -; GFX1030-NEXT: v_add3_u32 v2, v2, v1, 0x7fff -; GFX1030-NEXT: v_or_b32_e32 v5, 0x400000, v0 -; GFX1030-NEXT: v_add3_u32 v3, v3, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo -; GFX1030-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_v2bf16_test4: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_mov_b32_e32 v5, 0x3f00 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 -; GFX1100-NEXT: v_lshlrev_b32_e32 v3, 16, v0 -; GFX1100-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 -; GFX1100-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1100-NEXT: v_or_b32_e32 v5, 0x400000, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-NEXT: v_mul_f32_e32 v1, v3, v1 -; GFX1100-NEXT: v_bfe_u32 v3, v0, 16, 1 -; GFX1100-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-NEXT: v_add3_u32 v3, v3, v0, 0x7fff -; GFX1100-NEXT: v_add3_u32 v2, v2, v1, 0x7fff -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_v2bf16_test4: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 1.0, 0.5, vcc +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v3, 1.0, 0.5, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_v2bf16_test4: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v3 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_v2bf16_test4: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x3f80 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x3f00 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX9-SDAG-NEXT: v_bfe_u32 v3, v1, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX9-SDAG-NEXT: v_add3_u32 v3, v3, v1, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v2, v0, 16, 1 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_add3_u32 v2, v2, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x7060302 +; GFX9-SDAG-NEXT: v_perm_b32 v0, v0, v1, s4 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_v2bf16_test4: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_v2bf16_test4: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0x3f00 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo +; GFX10-SDAG-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX10-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v2 +; GFX10-SDAG-NEXT: v_bfe_u32 v2, v1, 16, 1 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v3, v0, 16, 1 +; GFX10-SDAG-NEXT: v_add3_u32 v2, v2, v1, 0x7fff +; GFX10-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v3, v3, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo +; GFX10-SDAG-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_v2bf16_test4: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_v2bf16_test4: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 0x3f00 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v3, 16, v0 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3f80, v5, vcc_lo +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4 +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3f80, v5, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_lshlrev_b32 v1, 16, v1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v3, v0, 16, 1 +; GFX11-SDAG-NEXT: v_bfe_u32 v2, v1, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v4, 0x400000, v1 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-NEXT: v_add3_u32 v3, v3, v0, 0x7fff +; GFX11-SDAG-NEXT: v_add3_u32 v2, v2, v1, 0x7fff +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_v2bf16_test4: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2 %y = select <2 x i1> %bool, <2 x bfloat> <bfloat 5.000000e-01, bfloat 5.000000e-01>, <2 x bfloat> <bfloat 1.000000e+00, bfloat 1.000000e+00> %ldexp = fmul <2 x bfloat> %x, %y @@ -2093,73 +3089,108 @@ define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.a } define bfloat @fmul_select_bf16_test5(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test5: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0x41000000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e64 v1, v3, 2.0, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test5: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4100 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x4000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test5: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0x4000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x4100, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test5: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x4100, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test5: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0x41000000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, v3, 2.0, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test5: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test5: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x4100 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test5: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test5: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x4000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4100, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test5: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test5: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4100, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test5: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 3, 1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat 2.000000e+00, bfloat 8.000000e+00 %ldexp = fmul bfloat %x, %y @@ -2167,74 +3198,116 @@ define bfloat @fmul_select_bf16_test5(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) } define bfloat @fmul_select_bf16_test6(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test6: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0x40400000 -; GFX7-NEXT: v_mov_b32_e32 v4, 0xc1000000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test6: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4040 -; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffc100 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test6: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0xffffc100 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x4040, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test6: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0xffffc100 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x4040, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test6: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0x40400000 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, 0xc1000000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test6: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0xc100 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0x4040 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test6: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x4040 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffc100 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test6: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xc100 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x4040 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test6: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xffffc100 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4040, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test6: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x4040 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc100, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test6: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0xffffc100 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4040, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test6: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x4040 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc100, vcc_lo +; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat -8.000000e+00, bfloat 3.000000e+00 %ldexp = fmul bfloat %x, %y @@ -2242,73 +3315,115 @@ define bfloat @fmul_select_bf16_test6(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) } define bfloat @fmul_select_bf16_test7(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test7: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0x41000000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, -4.0, v3, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test7: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0xffffc080 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x4100 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test7: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0x4100 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0xffffc080, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test7: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0xffffc080, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test7: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0x41000000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, -4.0, v3, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test7: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0x4100 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v4, 0xc080 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test7: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xffffc080 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4100 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test7: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x4100 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xc080 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test7: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x4100 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xffffc080, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test7: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xc080 +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4100, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test7: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xffffc080, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test7: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xc080 +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4100, vcc_lo +; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat 8.000000e+00, bfloat -4.000000e+00 %ldexp = fmul bfloat %x, %y @@ -2316,73 +3431,111 @@ define bfloat @fmul_select_bf16_test7(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) } define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test8: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_lshlrev_b32_e32 v1, 31, v1 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test8: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, 15 -; GFX9-NEXT: v_lshlrev_b16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test8: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo -; GFX1030-NEXT: v_lshlrev_b16 v1, 15, v1 -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test8: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_lshlrev_b16 v1, 15, v1 -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test8: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_lshlrev_b32_e32 v1, 31, v1 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test8: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0x8000 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX7-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test8: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 15 +; GFX9-SDAG-NEXT: v_lshlrev_b16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test8: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x8000 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test8: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b16 v1, 15, v1 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test8: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo +; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test8: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshlrev_b16 v1, 15, v1 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test8: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat -0.000000e+00, bfloat 0.000000e+00 %ldexp = fmul bfloat %x, %y @@ -2390,74 +3543,121 @@ define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) } define bfloat @fmul_select_bf16_test9(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test9: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0xc2000000 -; GFX7-NEXT: v_mov_b32_e32 v4, 0xc1800000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test9: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0xffffc200 -; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffc180 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test9: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0xffffc180 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0xffffc200, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test9: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0xffffc180 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0xffffc200, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test9: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0xc2000000 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, 0xc1800000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test9: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX7-GISEL-NEXT: v_add_i32_e32 v1, vcc, 5, v1 +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test9: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xffffc200 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffc180 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test9: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 5, v1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test9: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xffffc180 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xffffc200, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test9: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 5, v1 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test9: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0xffffc180 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xffffc200, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test9: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v1, 5, v1 +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat -1.600000e+01, bfloat -3.200000e+01 %ldexp = fmul bfloat %x, %y @@ -2465,74 +3665,111 @@ define bfloat @fmul_select_bf16_test9(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) } define bfloat @fmul_select_bf16_test10_sel_log2val_pos65_pos56(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_mov_b32_e32 v3, 0xdb800000 -; GFX7-NEXT: v_bfrev_b32_e32 v4, 7 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0xffffdb80 -; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffe000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0xffffe000 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0xffffdb80, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0xffffe000 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0xffffdb80, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v3, 0xdb800000 +; GFX7-SDAG-NEXT: v_bfrev_b32_e32 v4, 7 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, 0x41 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, 56, v3, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xffffdb80 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffe000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x41 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 56, v3, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xffffe000 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xffffdb80, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 56, 0x41, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0xffffe000 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xffffdb80, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 56, 0x41, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat 0xRE000, bfloat 0xRDB80 %ldexp = fmul bfloat %x, %y @@ -2540,74 +3777,111 @@ define bfloat @fmul_select_bf16_test10_sel_log2val_pos65_pos56(bfloat %x, i32 %b } define bfloat @fmul_select_bf16_test11_sel_log2val_neg22_pos25(bfloat %x, i32 %bool.arg1, i32 %bool.arg2) { -; GFX7-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: -; GFX7: ; %bb.0: -; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; GFX7-NEXT: v_bfrev_b32_e32 v3, 50 -; GFX7-NEXT: v_mov_b32_e32 v4, 0x34800000 -; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX7-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x4c00 -; GFX9-NEXT: v_mov_b32_e32 v4, 0x3480 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: v_add3_u32 v1, v1, v0, s4 -; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1030-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: -; GFX1030: ; %bb.0: -; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1030-NEXT: v_mov_b32_e32 v3, 0x3480 -; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1030-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: v_cndmask_b32_e32 v1, 0x4c00, v3, vcc_lo -; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1030-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1030-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1030-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1030-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1030-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1030-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1030-NEXT: s_setpc_b64 s[30:31] -; -; GFX1100-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: -; GFX1100: ; %bb.0: -; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1100-NEXT: v_dual_mov_b32 v3, 0x3480 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_cndmask_b32_e32 v1, 0x4c00, v3, vcc_lo -; GFX1100-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX1100-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX1100-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX1100-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-NEXT: v_add3_u32 v1, v1, v0, 0x7fff -; GFX1100-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX1100-NEXT: s_setpc_b64 s[30:31] +; GFX7-SDAG-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, 1.0, v0 +; GFX7-SDAG-NEXT: v_bfrev_b32_e32 v3, 50 +; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, 0x34800000 +; GFX7-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX7-SDAG-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX7-GISEL-NEXT: v_not_b32_e32 v3, 21 +; GFX7-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX7-GISEL-NEXT: v_cndmask_b32_e32 v1, 25, v3, vcc +; GFX7-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x4c00 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x3480 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_add3_u32 v1, v1, v0, s4 +; GFX9-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX9-SDAG-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_not_b32_e32 v3, 21 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, 25, v3, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x3480 +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4c00, v3, vcc_lo +; GFX10-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX10-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX10-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX10-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX10-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX10-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 25, 0xffffffea, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_dual_mov_b32 v3, 0x3480 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4c00, v3, vcc_lo +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX11-SDAG-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GFX11-SDAG-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GFX11-SDAG-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add3_u32 v1, v1, v0, 0x7fff +; GFX11-SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 25, 0xffffffea, vcc_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %bool = icmp eq i32 %bool.arg1, %bool.arg2 %y = select i1 %bool, bfloat 0xR3480, bfloat 0xR4C00 %ldexp = fmul bfloat %x, %y diff --git a/llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir b/llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir new file mode 100644 index 000000000000..5c7c07632f0d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/dummy-regalloc-priority-advisor.mir @@ -0,0 +1,54 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=greedy,2 -stress-regalloc=4 -stop-after=virtregrewriter,2 -regalloc-enable-priority-advisor=default -o - %s | FileCheck -check-prefixes=CHECK,DEFAULT %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=greedy,2 -stress-regalloc=4 -stop-after=virtregrewriter,2 -regalloc-enable-priority-advisor=dummy -o - %s | FileCheck -check-prefixes=CHECK,DUMMY %s + +# Check that the regalloc-enable-priority-advisor=dummy option works +# and the result is different from the default. Ordinarily %1 would be +# prioritized higher than %0 due to the register class priority + +--- +name: foo +tracksRegLiveness: true +machineFunctionInfo: + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + frameOffsetReg: '$sgpr33' + stackPtrOffsetReg: '$sgpr32' +registers: + - { id: 0, class: vgpr_32 } + - { id: 1, class: vreg_128 } + - { id: 2, class: vgpr_32 } +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + ; DEFAULT-LABEL: name: foo + ; DEFAULT: liveins: $vgpr0, $vgpr1 + ; DEFAULT-NEXT: {{ $}} + ; DEFAULT-NEXT: SI_SPILL_V128_SAVE $vgpr1_vgpr2_vgpr3_vgpr4, %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5) + ; DEFAULT-NEXT: SI_SPILL_V32_SAVE $vgpr0, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; DEFAULT-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 + ; DEFAULT-NEXT: renamable $vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) + ; DEFAULT-NEXT: renamable $vgpr3 = SI_SPILL_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; DEFAULT-NEXT: renamable $vgpr3 = V_ADD_U32_e32 killed $vgpr2, killed $vgpr3, implicit $exec + ; DEFAULT-NEXT: SI_RETURN implicit $vgpr3, implicit $vgpr0, implicit $vgpr1 + ; + ; DUMMY-LABEL: name: foo + ; DUMMY: liveins: $vgpr0, $vgpr1 + ; DUMMY-NEXT: {{ $}} + ; DUMMY-NEXT: SI_SPILL_V128_SAVE $vgpr1_vgpr2_vgpr3_vgpr4, %stack.1, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.1, align 4, addrspace 5) + ; DUMMY-NEXT: SI_SPILL_V32_SAVE $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; DUMMY-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 + ; DUMMY-NEXT: renamable $vgpr2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; DUMMY-NEXT: renamable $vgpr3_vgpr4_vgpr5_vgpr6 = SI_SPILL_V128_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.1, align 4, addrspace 5) + ; DUMMY-NEXT: renamable $vgpr3 = V_ADD_U32_e32 killed $vgpr3, killed $vgpr2, implicit $exec + ; DUMMY-NEXT: SI_RETURN implicit $vgpr3, implicit $vgpr0, implicit $vgpr1 + undef %1.sub0:vreg_128 = COPY $vgpr1 + %0:vgpr_32 = COPY $vgpr0 + S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 + %2:vgpr_32 = V_ADD_U32_e32 %1.sub0, %0, implicit $exec + $vgpr3 = COPY %2 + SI_RETURN implicit $vgpr3, implicit $vgpr0, implicit $vgpr1 + +... + +# CHECK: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll index 73aa87e5c55d..9acb3a42ae10 100644 --- a/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll @@ -1,64 +1,829 @@ -; RUN: not llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=+promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s -; RUN: not llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s -; RUN: not llc -mtriple=r600-- -mcpu=cypress < %s 2>&1 | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-GISEL %s target datalayout = "A5" -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform(i32 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dword s4, s[8:9], 0x0 +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: s_mov_b32 s5, s32 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 2 +; GFX9-SDAG-NEXT: s_add_i32 s4, s4, 15 +; GFX9-SDAG-NEXT: s_and_b32 s4, s4, -16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 6 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_add_i32 s32, s5, s4 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s5 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_uniform: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dword s5, s[8:9], 0x0 +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_lshl2_add_u32 s5, s5, 15 +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, -16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s5, 6 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX11-SDAG-NEXT: s_mov_b32 s32, 16 +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 15 +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0 +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_uniform: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b32 s1, s[4:5], 0x0 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX11-GISEL-NEXT: s_mov_b32 s32, 16 +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, s32 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_lshl2_add_u32 s1, s1, 15 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, -16 +; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1 +; GFX11-GISEL-NEXT: s_endpgm %alloca = alloca i32, i32 %n, addrspace(5) store volatile i32 123, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_over_aligned(i32 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform_over_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dword s4, s[8:9], 0x0 +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x2000 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: s_add_i32 s5, s32, 0x1fff +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 2 +; GFX9-SDAG-NEXT: s_add_i32 s4, s4, 15 +; GFX9-SDAG-NEXT: s_and_b32 s5, s5, 0xffffe000 +; GFX9-SDAG-NEXT: s_and_b32 s4, s4, -16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 10 +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 6 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_add_i32 s32, s5, s4 +; GFX9-SDAG-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_uniform_over_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dword s4, s[8:9], 0x0 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x2000 +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: s_add_u32 s5, s32, 0x1fff +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_lshl2_add_u32 s4, s4, 15 +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, 0xffffe000 +; GFX9-GISEL-NEXT: s_and_b32 s4, s4, -16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 10 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: s_lshl_b32 s4, s4, 6 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_add_u32 s32, s5, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform_over_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x0 +; GFX11-SDAG-NEXT: s_movk_i32 s32, 0x80 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 10 +; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0xfff +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xfffff000 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 15 +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0 +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_uniform_over_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s32, 0x80 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 10 +; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0xfff +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s0, 15 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_and_b32 s0, s0, -16 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: s_endpgm %alloca = alloca i32, i32 %n, align 128, addrspace(5) store volatile i32 10, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_uniform_under_aligned(i32 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform_under_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dword s4, s[8:9], 0x0 +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: s_mov_b32 s5, s32 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 2 +; GFX9-SDAG-NEXT: s_add_i32 s4, s4, 15 +; GFX9-SDAG-NEXT: s_and_b32 s4, s4, -16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 22 +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 6 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_add_i32 s32, s5, s4 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s5 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_uniform_under_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dword s5, s[8:9], 0x0 +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_lshl2_add_u32 s5, s5, 15 +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, -16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 22 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s5, 6 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_uniform_under_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 22 +; GFX11-SDAG-NEXT: s_mov_b32 s32, 16 +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 15 +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0 +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_uniform_under_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b32 s1, s[4:5], 0x0 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 22 +; GFX11-GISEL-NEXT: s_mov_b32 s32, 16 +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, s32 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s0 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_lshl2_add_u32 s1, s1, 15 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, -16 +; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s0, s1 +; GFX11-GISEL-NEXT: s_endpgm %alloca = alloca i32, i32 %n, align 2, addrspace(5) store volatile i32 22, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent() { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB3_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_divergent: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB3_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s32, 16 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB3_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x7b +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_divergent: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s32, 16 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB3_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB3_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_endpgm %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca float, i32 %idx, addrspace(5) store volatile i32 123, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_over_aligned() { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent_over_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x2000 +; GFX9-SDAG-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB4_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_add_i32 s4, s32, 0x1fff +; GFX9-SDAG-NEXT: s_and_b32 s4, s4, 0xffffe000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x1bc +; GFX9-SDAG-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_divergent_over_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x2000 +; GFX9-GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB4_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_add_u32 s5, s32, 0x1fff +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, 0xffffe000 +; GFX9-GISEL-NEXT: s_lshl_b32 s4, s6, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x1bc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: s_add_u32 s32, s5, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent_over_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-SDAG-NEXT: s_movk_i32 s32, 0x80 +; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo +; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0xfff +; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000 +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s3, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s4, v0, s3 +; GFX11-SDAG-NEXT: s_bitset0_b32 s2, s3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s1, s1, s4 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB4_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x1bc +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s0 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_divergent_over_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_movk_i32 s32, 0x80 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB4_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x1bc +; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0xfff +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_endpgm %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca i32, i32 %idx, align 128, addrspace(5) store volatile i32 444, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_divergent_under_aligned() { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent_under_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: v_lshlrev_b32_e32 v0, 4, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB5_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_divergent_under_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 4, 15 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB5_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_divergent_under_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s32, 16 +; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 4, v0 +; GFX11-SDAG-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB5_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x29a +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_divergent_under_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s32, 16 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 4, 15 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB5_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB5_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_endpgm %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca i128, i32 %idx, align 2, addrspace(5) store volatile i32 666, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_multiple_allocas(i32 %n, i32 %m) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_multiple_allocas: +; GFX9-SDAG: ; %bb.0: ; %entry +; GFX9-SDAG-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x2000 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB6_4 +; GFX9-SDAG-NEXT: ; %bb.1: ; %bb.0 +; GFX9-SDAG-NEXT: s_lshl_b32 s5, s5, 2 +; GFX9-SDAG-NEXT: s_add_i32 s5, s5, 15 +; GFX9-SDAG-NEXT: s_add_i32 s6, s32, 0xfff +; GFX9-SDAG-NEXT: s_and_b32 s5, s5, -16 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_and_b32 s9, s6, 0xfffff000 +; GFX9-SDAG-NEXT: s_lshl_b32 s5, s5, 6 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], exec +; GFX9-SDAG-NEXT: s_add_i32 s32, s9, s5 +; GFX9-SDAG-NEXT: .LBB6_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s5, s[6:7] +; GFX9-SDAG-NEXT: v_readlane_b32 s10, v0, s5 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[6:7], s5 +; GFX9-SDAG-NEXT: s_max_u32 s8, s8, s10 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB6_2 +; GFX9-SDAG-NEXT: ; %bb.3: +; GFX9-SDAG-NEXT: s_mov_b32 s5, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s5 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s8, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 3 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-SDAG-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 4 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s5 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: .LBB6_4: ; %bb.1 +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 2 +; GFX9-SDAG-NEXT: s_add_i32 s4, s4, 15 +; GFX9-SDAG-NEXT: s_and_b32 s4, s4, -16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-SDAG-NEXT: s_lshl_b32 s4, s4, 6 +; GFX9-SDAG-NEXT: s_mov_b32 s5, s32 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-SDAG-NEXT: s_add_i32 s32, s5, s4 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s5 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_multiple_allocas: +; GFX9-GISEL: ; %bb.0: ; %entry +; GFX9-GISEL-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x2000 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB6_4 +; GFX9-GISEL-NEXT: ; %bb.1: ; %bb.0 +; GFX9-GISEL-NEXT: s_lshl2_add_u32 s5, s5, 15 +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, -16 +; GFX9-GISEL-NEXT: s_lshl_b32 s6, s5, 6 +; GFX9-GISEL-NEXT: s_add_u32 s5, s32, 0xfff +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, 0xfffff000 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_add_u32 s32, s5, s6 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9-GISEL-NEXT: .LBB6_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9-GISEL-NEXT: v_readlane_b32 s10, v0, s9 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9-GISEL-NEXT: s_max_u32 s8, s8, s10 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB6_2 +; GFX9-GISEL-NEXT: ; %bb.3: +; GFX9-GISEL-NEXT: s_mov_b32 s6, s32 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 3 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: s_lshl_b32 s7, s8, 6 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s6, s7 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: .LBB6_4: ; %bb.1 +; GFX9-GISEL-NEXT: s_lshl2_add_u32 s4, s4, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s5, s32 +; GFX9-GISEL-NEXT: s_and_b32 s4, s4, -16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-GISEL-NEXT: s_lshl_b32 s4, s4, 6 +; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: s_add_u32 s32, s5, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_multiple_allocas: +; GFX11-SDAG: ; %bb.0: ; %entry +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-SDAG-NEXT: s_mov_b32 s2, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_movk_i32 s32, 0x80 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB6_4 +; GFX11-SDAG-NEXT: ; %bb.1: ; %bb.0 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-SDAG-NEXT: s_lshl_b32 s1, s1, 2 +; GFX11-SDAG-NEXT: s_add_i32 s3, s32, 0x7ff +; GFX11-SDAG-NEXT: s_add_i32 s1, s1, 15 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_and_b32 s4, s1, -16 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_and_b32 s1, s3, 0xfffff800 +; GFX11-SDAG-NEXT: s_lshl_b32 s3, s4, 5 +; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: s_mov_b32 s3, exec_lo +; GFX11-SDAG-NEXT: .LBB6_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s4, s3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s5, v0, s4 +; GFX11-SDAG-NEXT: s_bitset0_b32 s3, s4 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s2, s2, s5 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB6_2 +; GFX11-SDAG-NEXT: ; %bb.3: +; GFX11-SDAG-NEXT: s_mov_b32 s3, s32 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v1, 3 :: v_dual_mov_b32 v2, 4 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s2, 5, s3 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v2, s3 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: .LBB6_4: ; %bb.1 +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 +; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 15 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s33 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0 +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_multiple_allocas: +; GFX11-GISEL: ; %bb.0: ; %entry +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-GISEL-NEXT: s_mov_b32 s2, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_movk_i32 s32, 0x80 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB6_4 +; GFX11-GISEL-NEXT: ; %bb.1: ; %bb.0 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-GISEL-NEXT: s_lshl2_add_u32 s1, s1, 15 +; GFX11-GISEL-NEXT: s_add_u32 s3, s32, 0x7ff +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, -16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_lshl_b32 s4, s1, 5 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_and_b32 s1, s3, 0xfffff800 +; GFX11-GISEL-NEXT: s_mov_b32 s3, exec_lo +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s4 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB6_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s4, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s5, v0, s4 +; GFX11-GISEL-NEXT: s_bitset0_b32 s3, s4 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s2, s2, s5 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB6_2 +; GFX11-GISEL-NEXT: ; %bb.3: +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, 3 :: v_dual_mov_b32 v1, 4 +; GFX11-GISEL-NEXT: s_mov_b32 s3, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s2, s2, 5 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v1, s3 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_u32 s32, s3, s2 +; GFX11-GISEL-NEXT: .LBB6_4: ; %bb.1 +; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s0, 15 +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 +; GFX11-GISEL-NEXT: s_and_b32 s0, s0, -16 +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s33 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: s_endpgm entry: %cond = icmp eq i32 %n, 0 %alloca1 = alloca i32, i32 8, addrspace(5) @@ -77,10 +842,206 @@ bb.1: ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define amdgpu_kernel void @test_dynamic_stackalloc_kernel_control_flow(i32 %n, i32 %m) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_kernel_control_flow: +; GFX9-SDAG: ; %bb.0: ; %entry +; GFX9-SDAG-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX9-SDAG-NEXT: s_add_u32 s0, s0, s17 +; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX9-SDAG-NEXT: s_movk_i32 s32, 0x1000 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s4, 0 +; GFX9-SDAG-NEXT: s_cbranch_scc0 .LBB7_6 +; GFX9-SDAG-NEXT: ; %bb.1: ; %bb.1 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], exec +; GFX9-SDAG-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s8, s[6:7] +; GFX9-SDAG-NEXT: v_readlane_b32 s9, v0, s8 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[6:7], s8 +; GFX9-SDAG-NEXT: s_max_u32 s4, s4, s9 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB7_2 +; GFX9-SDAG-NEXT: ; %bb.3: +; GFX9-SDAG-NEXT: s_mov_b32 s6, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s4, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s6 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_cbranch_execnz .LBB7_5 +; GFX9-SDAG-NEXT: .LBB7_4: ; %bb.0 +; GFX9-SDAG-NEXT: s_lshl_b32 s5, s5, 2 +; GFX9-SDAG-NEXT: s_add_i32 s4, s32, 0xfff +; GFX9-SDAG-NEXT: s_add_i32 s5, s5, 15 +; GFX9-SDAG-NEXT: s_and_b32 s4, s4, 0xfffff000 +; GFX9-SDAG-NEXT: s_and_b32 s5, s5, -16 +; GFX9-SDAG-NEXT: s_lshl_b32 s5, s5, 6 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-SDAG-NEXT: s_add_i32 s32, s4, s5 +; GFX9-SDAG-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: .LBB7_5: ; %bb.2 +; GFX9-SDAG-NEXT: s_endpgm +; GFX9-SDAG-NEXT: .LBB7_6: +; GFX9-SDAG-NEXT: s_branch .LBB7_4 +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_kernel_control_flow: +; GFX9-GISEL: ; %bb.0: ; %entry +; GFX9-GISEL-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, s17 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s4, 1 +; GFX9-GISEL-NEXT: s_movk_i32 s32, 0x1000 +; GFX9-GISEL-NEXT: s_cbranch_scc0 .LBB7_4 +; GFX9-GISEL-NEXT: ; %bb.1: ; %bb.1 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9-GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s4, s[6:7] +; GFX9-GISEL-NEXT: v_readlane_b32 s9, v0, s4 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[6:7], s4 +; GFX9-GISEL-NEXT: s_max_u32 s8, s8, s9 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB7_2 +; GFX9-GISEL-NEXT: ; %bb.3: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s6, s8, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s6 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b32 s4, 0 +; GFX9-GISEL-NEXT: .LBB7_4: ; %Flow +; GFX9-GISEL-NEXT: s_xor_b32 s4, s4, 1 +; GFX9-GISEL-NEXT: s_and_b32 s4, s4, 1 +; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB7_6 +; GFX9-GISEL-NEXT: ; %bb.5: ; %bb.0 +; GFX9-GISEL-NEXT: s_lshl2_add_u32 s4, s5, 15 +; GFX9-GISEL-NEXT: s_add_u32 s5, s32, 0xfff +; GFX9-GISEL-NEXT: s_and_b32 s4, s4, -16 +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, 0xfffff000 +; GFX9-GISEL-NEXT: s_lshl_b32 s4, s4, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: s_add_u32 s32, s5, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: .LBB7_6: ; %bb.2 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_kernel_control_flow: +; GFX11-SDAG: ; %bb.0: ; %entry +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s32, 64 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc0 .LBB7_6 +; GFX11-SDAG-NEXT: ; %bb.1: ; %bb.1 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s3, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s4, v0, s3 +; GFX11-SDAG-NEXT: s_bitset0_b32 s2, s3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s4 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB7_2 +; GFX11-SDAG-NEXT: ; %bb.3: +; GFX11-SDAG-NEXT: s_mov_b32 s2, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s2 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s2 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_cbranch_execnz .LBB7_5 +; GFX11-SDAG-NEXT: .LBB7_4: ; %bb.0 +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s1, 2 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 2 +; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 15 +; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0x7ff +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, -16 +; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xfffff800 +; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: s_add_i32 s32, s1, s0 +; GFX11-SDAG-NEXT: .LBB7_5: ; %bb.2 +; GFX11-SDAG-NEXT: s_endpgm +; GFX11-SDAG-NEXT: .LBB7_6: +; GFX11-SDAG-NEXT: s_branch .LBB7_4 +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_kernel_control_flow: +; GFX11-GISEL: ; %bb.0: ; %entry +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GFX11-GISEL-NEXT: s_mov_b32 s2, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s32, 64 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, 1 +; GFX11-GISEL-NEXT: s_cbranch_scc0 .LBB7_4 +; GFX11-GISEL-NEXT: ; %bb.1: ; %bb.1 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, exec_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB7_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s3, s0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s4, v0, s3 +; GFX11-GISEL-NEXT: s_bitset0_b32 s0, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s2, s2, s4 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB7_2 +; GFX11-GISEL-NEXT: ; %bb.3: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 1 +; GFX11-GISEL-NEXT: s_mov_b32 s3, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s2, 5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s3, s0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s3 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: .LBB7_4: ; %Flow +; GFX11-GISEL-NEXT: s_xor_b32 s0, s0, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 1 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB7_6 +; GFX11-GISEL-NEXT: ; %bb.5: ; %bb.0 +; GFX11-GISEL-NEXT: s_lshl2_add_u32 s0, s1, 15 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 2 +; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0x7ff +; GFX11-GISEL-NEXT: s_and_b32 s0, s0, -16 +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff800 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: .LBB7_6: ; %bb.2 +; GFX11-GISEL-NEXT: s_endpgm entry: %cond = icmp eq i32 %n, 0 br i1 %cond, label %bb.0, label %bb.1 @@ -97,62 +1058,1113 @@ bb.2: ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_uniform(i32 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB8_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s9 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB8_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB8_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x7b +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, -16 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB8_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, -16 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, i32 %n, addrspace(5) store volatile i32 123, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_uniform_over_aligned(i32 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0x1fc0 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x4000 +; GFX9-SDAG-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB9_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_add_i32 s4, s32, 0x1fff +; GFX9-SDAG-NEXT: s_and_b32 s4, s4, 0xffffe000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 10 +; GFX9-SDAG-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xc000 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s9 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0x1fc0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x4000 +; GFX9-GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB9_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_add_u32 s5, s32, 0x1fff +; GFX9-GISEL-NEXT: s_lshl_b32 s4, s6, 6 +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, 0xffffe000 +; GFX9-GISEL-NEXT: s_add_u32 s32, s5, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 10 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xc000 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 0x7f +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x100 +; GFX11-SDAG-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB9_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_add_i32 s1, s32, 0xfff +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 10 +; GFX11-SDAG-NEXT: s_and_b32 s1, s1, 0xfffff000 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0xff00 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_over_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 0x7f +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x100 +; GFX11-GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB9_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0xfff +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 10 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xff00 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, i32 %n, align 128, addrspace(5) store volatile i32 10, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_uniform_under_aligned(i32 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB10_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 22 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s9 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB10_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 22 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB10_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 22 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, -16 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_uniform_under_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB10_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 22 +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, -16 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %alloca = alloca i32, i32 %n, align 2, addrspace(5) store volatile i32 22, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_divergent() { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB11_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s9 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB11_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB11_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x7b +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, -16 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB11_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB11_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x7b +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, -16 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca i32, i32 %idx, addrspace(5) store volatile i32 123, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_divergent_over_aligned() { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s10, s33 +; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0x1fc0 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x4000 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-SDAG-NEXT: s_add_i32 s4, s32, 0x1fff +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_and_b32 s6, s4, 0xffffe000 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s7, 0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-SDAG-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s8, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s9, v0, s8 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s8 +; GFX9-SDAG-NEXT: s_max_u32 s7, s7, s9 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB12_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, s7, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x1bc +; GFX9-SDAG-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xc000 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s10 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0x1fc0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xffffe000 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x4000 +; GFX9-GISEL-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB12_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_add_u32 s5, s32, 0x1fff +; GFX9-GISEL-NEXT: s_lshl_b32 s4, s6, 6 +; GFX9-GISEL-NEXT: s_and_b32 s5, s5, 0xffffe000 +; GFX9-GISEL-NEXT: s_add_u32 s32, s5, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x1bc +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xc000 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-SDAG-NEXT: s_mov_b32 s5, s33 +; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 0x7f +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x100 +; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_add_i32 s0, s32, 0xfff +; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX11-SDAG-NEXT: s_and_b32 s0, s0, 0xfffff000 +; GFX11-SDAG-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s3, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s4, v0, s3 +; GFX11-SDAG-NEXT: s_bitset0_b32 s2, s3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s1, s1, s4 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB12_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x1bc +; GFX11-SDAG-NEXT: s_mov_b32 s33, s5 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s0 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0xff00 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_over_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 0x7f +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_and_b32 s33, s33, 0xffffff80 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x100 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB12_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB12_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: s_add_u32 s1, s32, 0xfff +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x1bc +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_and_b32 s1, s1, 0xfffff000 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xff00 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca i32, i32 %idx, align 128, addrspace(5) store volatile i32 444, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_divergent_under_aligned() { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB13_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s9 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB13_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB13_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x29a +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, -16 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_under_aligned: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB13_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB13_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, -16 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %idx = call i32 @llvm.amdgcn.workitem.id.x() %alloca = alloca i32, i32 %idx, align 2, addrspace(5) store volatile i32 666, ptr addrspace(5) %alloca ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_multiple_allocas(i32 %n, i32 %m) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_multiple_allocas: +; GFX9-SDAG: ; %bb.0: ; %entry +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s13, s33 +; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0xfc0 +; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x3000 +; GFX9-SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-SDAG-NEXT: s_cbranch_execz .LBB14_6 +; GFX9-SDAG-NEXT: ; %bb.1: ; %bb.0 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX9-SDAG-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], exec +; GFX9-SDAG-NEXT: s_mov_b32 s10, 0 +; GFX9-SDAG-NEXT: .LBB14_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9-SDAG-NEXT: v_readlane_b32 s11, v1, s9 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9-SDAG-NEXT: s_max_u32 s10, s10, s11 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB14_2 +; GFX9-SDAG-NEXT: ; %bb.3: +; GFX9-SDAG-NEXT: s_add_i32 s6, s32, 0xfff +; GFX9-SDAG-NEXT: s_and_b32 s9, s6, 0xfffff000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, s10, 6, v1 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v31 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX9-SDAG-NEXT: v_and_b32_e32 v1, 0x1ff0, v1 +; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], exec +; GFX9-SDAG-NEXT: s_mov_b32 s10, 0 +; GFX9-SDAG-NEXT: .LBB14_4: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s11, s[6:7] +; GFX9-SDAG-NEXT: v_readlane_b32 s12, v1, s11 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[6:7], s11 +; GFX9-SDAG-NEXT: s_max_u32 s10, s10, s12 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB14_4 +; GFX9-SDAG-NEXT: ; %bb.5: +; GFX9-SDAG-NEXT: s_mov_b32 s6, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, s10, 6, v1 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 3 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s9 +; GFX9-SDAG-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 4 +; GFX9-SDAG-NEXT: buffer_store_dword v1, off, s[0:3], s6 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: .LBB14_6: ; %bb.1 +; GFX9-SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 2 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: .LBB14_7: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s6, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s7, v0, s6 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s6 +; GFX9-SDAG-NEXT: s_max_u32 s8, s8, s7 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB14_7 +; GFX9-SDAG-NEXT: ; %bb.8: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s8, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: buffer_store_dword v1, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xd000 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s13 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_multiple_allocas: +; GFX9-GISEL: ; %bb.0: ; %entry +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b32 s13, s33 +; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0xfc0 +; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x3000 +; GFX9-GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-GISEL-NEXT: s_cbranch_execz .LBB14_6 +; GFX9-GISEL-NEXT: ; %bb.1: ; %bb.0 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x3ff, v31 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9-GISEL-NEXT: s_mov_b32 s9, 0 +; GFX9-GISEL-NEXT: .LBB14_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s10, s[6:7] +; GFX9-GISEL-NEXT: v_readlane_b32 s11, v1, s10 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[6:7], s10 +; GFX9-GISEL-NEXT: s_max_u32 s9, s9, s11 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB14_2 +; GFX9-GISEL-NEXT: ; %bb.3: +; GFX9-GISEL-NEXT: s_add_u32 s7, s32, 0xfff +; GFX9-GISEL-NEXT: s_lshl_b32 s6, s9, 6 +; GFX9-GISEL-NEXT: s_and_b32 s9, s7, 0xfffff000 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v1, v2, 2, 15 +; GFX9-GISEL-NEXT: s_add_u32 s32, s9, s6 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9-GISEL-NEXT: s_mov_b32 s10, 0 +; GFX9-GISEL-NEXT: .LBB14_4: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s11, s[6:7] +; GFX9-GISEL-NEXT: v_readlane_b32 s12, v1, s11 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[6:7], s11 +; GFX9-GISEL-NEXT: s_max_u32 s10, s10, s12 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB14_4 +; GFX9-GISEL-NEXT: ; %bb.5: +; GFX9-GISEL-NEXT: s_mov_b32 s6, s32 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 3 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s9 +; GFX9-GISEL-NEXT: s_lshl_b32 s7, s10, 6 +; GFX9-GISEL-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s6, s7 +; GFX9-GISEL-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: .LBB14_6: ; %bb.1 +; GFX9-GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: .LBB14_7: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s6, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s7, v0, s6 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s6 +; GFX9-GISEL-NEXT: s_max_u32 s8, s8, s7 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB14_7 +; GFX9-GISEL-NEXT: ; %bb.8: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s8, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], s33 +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xd000 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s13 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_multiple_allocas: +; GFX11-SDAG: ; %bb.0: ; %entry +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_mov_b32 s7, s33 +; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 63 +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0xc0 +; GFX11-SDAG-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-SDAG-NEXT: s_cbranch_execz .LBB14_6 +; GFX11-SDAG-NEXT: ; %bb.1: ; %bb.0 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s3, 0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX11-SDAG-NEXT: .LBB14_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s4, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s5, v1, s4 +; GFX11-SDAG-NEXT: s_bitset0_b32 s2, s4 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s3, s3, s5 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB14_2 +; GFX11-SDAG-NEXT: ; %bb.3: +; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0x3ff, v31 +; GFX11-SDAG-NEXT: s_add_i32 s2, s32, 0x7ff +; GFX11-SDAG-NEXT: s_mov_b32 s4, exec_lo +; GFX11-SDAG-NEXT: s_and_b32 s2, s2, 0xfffff800 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v2, s3, 5, s2 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s3, 0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_and_b32_e32 v1, 0x1ff0, v1 +; GFX11-SDAG-NEXT: .LBB14_4: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s5, s4 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s6, v1, s5 +; GFX11-SDAG-NEXT: s_bitset0_b32 s4, s5 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s3, s3, s6 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s4, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB14_4 +; GFX11-SDAG-NEXT: ; %bb.5: +; GFX11-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX11-SDAG-NEXT: v_dual_mov_b32 v2, 3 :: v_dual_mov_b32 v3, 4 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, s3, 5, s4 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v2, s2 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v3, s4 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX11-SDAG-NEXT: .LBB14_6: ; %bb.1 +; GFX11-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, v0, 2, 15 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 2 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX11-SDAG-NEXT: .LBB14_7: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v1, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB14_7 +; GFX11-SDAG-NEXT: ; %bb.8: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 1 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, s0, 5, s1 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v2, s33 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s7 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0xff40 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_multiple_allocas: +; GFX11-GISEL: ; %bb.0: ; %entry +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_mov_b32 s7, s33 +; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 63 +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xc0 +; GFX11-GISEL-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-GISEL-NEXT: s_cbranch_execz .LBB14_6 +; GFX11-GISEL-NEXT: ; %bb.1: ; %bb.0 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v2, v1, 2, 15 +; GFX11-GISEL-NEXT: v_and_b32_e32 v1, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s3, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s2, 0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_and_b32_e32 v2, -16, v2 +; GFX11-GISEL-NEXT: .LBB14_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s4, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s5, v2, s4 +; GFX11-GISEL-NEXT: s_bitset0_b32 s3, s4 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s2, s2, s5 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB14_2 +; GFX11-GISEL-NEXT: ; %bb.3: +; GFX11-GISEL-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX11-GISEL-NEXT: s_lshl_b32 s5, s2, 5 +; GFX11-GISEL-NEXT: s_add_u32 s2, s32, 0x7ff +; GFX11-GISEL-NEXT: s_mov_b32 s4, exec_lo +; GFX11-GISEL-NEXT: s_and_b32 s2, s2, 0xfffff800 +; GFX11-GISEL-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX11-GISEL-NEXT: s_mov_b32 s3, 0 +; GFX11-GISEL-NEXT: s_add_u32 s32, s2, s5 +; GFX11-GISEL-NEXT: .LBB14_4: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s5, s4 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s6, v1, s5 +; GFX11-GISEL-NEXT: s_bitset0_b32 s4, s5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s3, s3, s6 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB14_4 +; GFX11-GISEL-NEXT: ; %bb.5: +; GFX11-GISEL-NEXT: v_dual_mov_b32 v1, 3 :: v_dual_mov_b32 v2, 4 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s3, s3, 5 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v1, s2 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v2, s4 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_u32 s32, s4, s3 +; GFX11-GISEL-NEXT: .LBB14_6: ; %bb.1 +; GFX11-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB14_7: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB14_7 +; GFX11-GISEL-NEXT: ; %bb.8: +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 2 +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s33 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s7 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xff40 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] entry: %cond = icmp eq i32 %n, 0 %alloca1 = alloca i32, i32 8, addrspace(5) @@ -171,10 +2183,272 @@ bb.1: ret void } -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca -; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca - define void @test_dynamic_stackalloc_device_control_flow(i32 %n, i32 %m) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_control_flow: +; GFX9-SDAG: ; %bb.0: ; %entry +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s11, s33 +; GFX9-SDAG-NEXT: s_add_i32 s33, s32, 0xfc0 +; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 +; GFX9-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX9-SDAG-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x2000 +; GFX9-SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-SDAG-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-SDAG-NEXT: s_cbranch_execz .LBB15_4 +; GFX9-SDAG-NEXT: ; %bb.1: ; %bb.1 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-SDAG-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], exec +; GFX9-SDAG-NEXT: .LBB15_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9-SDAG-NEXT: v_readlane_b32 s10, v1, s9 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9-SDAG-NEXT: s_max_u32 s8, s8, s10 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB15_2 +; GFX9-SDAG-NEXT: ; %bb.3: +; GFX9-SDAG-NEXT: s_add_i32 s6, s32, 0xfff +; GFX9-SDAG-NEXT: s_and_b32 s6, s6, 0xfffff000 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v2, s8, 6, v1 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v2 +; GFX9-SDAG-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: ; implicit-def: $vgpr31 +; GFX9-SDAG-NEXT: .LBB15_4: ; %Flow +; GFX9-SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-SDAG-NEXT: s_cbranch_execz .LBB15_8 +; GFX9-SDAG-NEXT: ; %bb.5: ; %bb.0 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[6:7], exec +; GFX9-SDAG-NEXT: s_mov_b32 s8, 0 +; GFX9-SDAG-NEXT: .LBB15_6: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9-SDAG-NEXT: v_readlane_b32 s10, v0, s9 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9-SDAG-NEXT: s_max_u32 s8, s8, s10 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB15_6 +; GFX9-SDAG-NEXT: ; %bb.7: +; GFX9-SDAG-NEXT: s_mov_b32 s6, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s8, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s6 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: .LBB15_8: ; %bb.2 +; GFX9-SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xe000 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s11 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_control_flow: +; GFX9-GISEL: ; %bb.0: ; %entry +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b32 s11, s33 +; GFX9-GISEL-NEXT: s_add_i32 s33, s32, 0xfc0 +; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 +; GFX9-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GFX9-GISEL-NEXT: s_and_b32 s33, s33, 0xfffff000 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x2000 +; GFX9-GISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-GISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GFX9-GISEL-NEXT: s_cbranch_execz .LBB15_4 +; GFX9-GISEL-NEXT: ; %bb.1: ; %bb.1 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v1, 2, 15 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9-GISEL-NEXT: .LBB15_2: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9-GISEL-NEXT: v_readlane_b32 s10, v0, s9 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9-GISEL-NEXT: s_max_u32 s8, s8, s10 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB15_2 +; GFX9-GISEL-NEXT: ; %bb.3: +; GFX9-GISEL-NEXT: s_add_u32 s7, s32, 0xfff +; GFX9-GISEL-NEXT: s_and_b32 s7, s7, 0xfffff000 +; GFX9-GISEL-NEXT: s_lshl_b32 s6, s8, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-GISEL-NEXT: s_add_u32 s32, s7, s6 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: ; implicit-def: $vgpr31 +; GFX9-GISEL-NEXT: .LBB15_4: ; %Flow +; GFX9-GISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] +; GFX9-GISEL-NEXT: s_cbranch_execz .LBB15_8 +; GFX9-GISEL-NEXT: ; %bb.5: ; %bb.0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[6:7], exec +; GFX9-GISEL-NEXT: s_mov_b32 s8, 0 +; GFX9-GISEL-NEXT: .LBB15_6: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s9, s[6:7] +; GFX9-GISEL-NEXT: v_readlane_b32 s10, v0, s9 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[6:7], s9 +; GFX9-GISEL-NEXT: s_max_u32 s8, s8, s10 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB15_6 +; GFX9-GISEL-NEXT: ; %bb.7: +; GFX9-GISEL-NEXT: s_mov_b32 s6, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s7, s8, 6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s6, s7 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: .LBB15_8: ; %bb.2 +; GFX9-GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xe000 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s11 +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_control_flow: +; GFX11-SDAG: ; %bb.0: ; %entry +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_mov_b32 s5, s33 +; GFX11-SDAG-NEXT: s_add_i32 s33, s32, 63 +; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s0, exec_lo +; GFX11-SDAG-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0x80 +; GFX11-SDAG-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX11-SDAG-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-SDAG-NEXT: s_cbranch_execz .LBB15_4 +; GFX11-SDAG-NEXT: ; %bb.1: ; %bb.1 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, v1, 2, 15 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 2 +; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_and_b32_e32 v1, -16, v1 +; GFX11-SDAG-NEXT: .LBB15_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s3, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s4, v1, s3 +; GFX11-SDAG-NEXT: s_bitset0_b32 s2, s3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s1, s1, s4 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB15_2 +; GFX11-SDAG-NEXT: ; %bb.3: +; GFX11-SDAG-NEXT: s_add_i32 s2, s32, 0x7ff +; GFX11-SDAG-NEXT: ; implicit-def: $vgpr31 +; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: s_and_b32 s2, s2, 0xfffff800 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v1, s1, 5, s2 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v0, s2 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v1 +; GFX11-SDAG-NEXT: .LBB15_4: ; %Flow +; GFX11-SDAG-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-SDAG-NEXT: s_cbranch_execz .LBB15_8 +; GFX11-SDAG-NEXT: ; %bb.5: ; %bb.0 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-SDAG-NEXT: s_mov_b32 s2, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s1, 0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x1ff0, v0 +; GFX11-SDAG-NEXT: .LBB15_6: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s3, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s4, v0, s3 +; GFX11-SDAG-NEXT: s_bitset0_b32 s2, s3 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s1, s1, s4 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB15_6 +; GFX11-SDAG-NEXT: ; %bb.7: +; GFX11-SDAG-NEXT: s_mov_b32 s2, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s1, 5, s2 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s2 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: .LBB15_8: ; %bb.2 +; GFX11-SDAG-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_addk_i32 s32, 0xff80 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s5 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_control_flow: +; GFX11-GISEL: ; %bb.0: ; %entry +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_mov_b32 s5, s33 +; GFX11-GISEL-NEXT: s_add_i32 s33, s32, 63 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s0, exec_lo +; GFX11-GISEL-NEXT: s_and_not1_b32 s33, s33, 63 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0x80 +; GFX11-GISEL-NEXT: v_cmpx_ne_u32_e32 0, v0 +; GFX11-GISEL-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX11-GISEL-NEXT: s_cbranch_execz .LBB15_4 +; GFX11-GISEL-NEXT: ; %bb.1: ; %bb.1 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v1, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s2, exec_lo +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB15_2: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s3, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s4, v0, s3 +; GFX11-GISEL-NEXT: s_bitset0_b32 s2, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s1, s1, s4 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB15_2 +; GFX11-GISEL-NEXT: ; %bb.3: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 2 +; GFX11-GISEL-NEXT: s_add_u32 s2, s32, 0x7ff +; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5 +; GFX11-GISEL-NEXT: s_and_b32 s2, s2, 0xfffff800 +; GFX11-GISEL-NEXT: ; implicit-def: $vgpr31 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s2, s1 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s2 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: .LBB15_4: ; %Flow +; GFX11-GISEL-NEXT: s_and_not1_saveexec_b32 s0, s0 +; GFX11-GISEL-NEXT: s_cbranch_execz .LBB15_8 +; GFX11-GISEL-NEXT: ; %bb.5: ; %bb.0 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v31 +; GFX11-GISEL-NEXT: s_mov_b32 s2, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s1, 0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB15_6: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s3, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s4, v0, s3 +; GFX11-GISEL-NEXT: s_bitset0_b32 s2, s3 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s1, s1, s4 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB15_6 +; GFX11-GISEL-NEXT: ; %bb.7: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 1 +; GFX11-GISEL-NEXT: s_mov_b32 s2, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s1, s1, 5 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: s_add_u32 s32, s2, s1 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s2 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: .LBB15_8: ; %bb.2 +; GFX11-GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-GISEL-NEXT: s_addk_i32 s32, 0xff80 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s5 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] entry: %cond = icmp eq i32 %n, 0 br i1 %cond, label %bb.0, label %bb.1 @@ -190,3 +2464,257 @@ bb.1: bb.2: ret void } + +define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i16(i16 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff0, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB16_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s9 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB16_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x7fff0, v0 +; GFX11-SDAG-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB16_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x29a +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, -16 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i16: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: .LBB16_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB16_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, -16 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] + %alloca = alloca i32, i16 %n, align 2, addrspace(5) + store volatile i32 666, ptr addrspace(5) %alloca + ret void +} + +define void @test_dynamic_stackalloc_device_divergent_non_standard_size_i64(i64 %n) { +; GFX9-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-SDAG-NEXT: s_mov_b32 s9, s33 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-SDAG-NEXT: s_mov_b64 s[4:5], exec +; GFX9-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0x400 +; GFX9-SDAG-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-SDAG-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-SDAG-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-SDAG-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-SDAG-NEXT: s_max_u32 s6, s6, s8 +; GFX9-SDAG-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-SDAG-NEXT: s_cbranch_scc1 .LBB17_1 +; GFX9-SDAG-NEXT: ; %bb.2: +; GFX9-SDAG-NEXT: s_mov_b32 s4, s32 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_lshl_add_u32 v0, s6, 6, v0 +; GFX9-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], s4 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-SDAG-NEXT: s_mov_b32 s33, s9 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX9-GISEL-NEXT: s_mov_b32 s9, s33 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], exec +; GFX9-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0x400 +; GFX9-GISEL-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 +; GFX9-GISEL-NEXT: s_ff1_i32_b64 s7, s[4:5] +; GFX9-GISEL-NEXT: v_readlane_b32 s8, v0, s7 +; GFX9-GISEL-NEXT: s_bitset0_b64 s[4:5], s7 +; GFX9-GISEL-NEXT: s_max_u32 s6, s6, s8 +; GFX9-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB17_1 +; GFX9-GISEL-NEXT: ; %bb.2: +; GFX9-GISEL-NEXT: s_mov_b32 s4, s32 +; GFX9-GISEL-NEXT: s_lshl_b32 s5, s6, 6 +; GFX9-GISEL-NEXT: s_add_u32 s32, s4, s5 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-GISEL-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_addk_i32 s32, 0xfc00 +; GFX9-GISEL-NEXT: s_mov_b32 s33, s9 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-SDAG-NEXT: s_mov_b32 s4, s33 +; GFX11-SDAG-NEXT: s_mov_b32 s1, exec_lo +; GFX11-SDAG-NEXT: s_mov_b32 s0, 0 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s32 +; GFX11-SDAG-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, 16 +; GFX11-SDAG-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-SDAG-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-SDAG-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-SDAG-NEXT: s_bitset0_b32 s1, s2 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_max_u32 s0, s0, s3 +; GFX11-SDAG-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-SDAG-NEXT: s_cbranch_scc1 .LBB17_1 +; GFX11-SDAG-NEXT: ; %bb.2: +; GFX11-SDAG-NEXT: s_mov_b32 s1, s32 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x29a +; GFX11-SDAG-NEXT: v_lshl_add_u32 v0, s0, 5, s1 +; GFX11-SDAG-NEXT: s_mov_b32 s33, s4 +; GFX11-SDAG-NEXT: scratch_store_b32 off, v1, s1 dlc +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_readfirstlane_b32 s32, v0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: s_add_i32 s32, s32, -16 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: test_dynamic_stackalloc_device_divergent_non_standard_size_i64: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_lshl_add_u32 v0, v0, 2, 15 +; GFX11-GISEL-NEXT: s_mov_b32 s4, s33 +; GFX11-GISEL-NEXT: s_mov_b32 s1, exec_lo +; GFX11-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s32 +; GFX11-GISEL-NEXT: v_and_b32_e32 v0, -16, v0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, 16 +; GFX11-GISEL-NEXT: .LBB17_1: ; =>This Inner Loop Header: Depth=1 +; GFX11-GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_readlane_b32 s3, v0, s2 +; GFX11-GISEL-NEXT: s_bitset0_b32 s1, s2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-GISEL-NEXT: s_max_u32 s0, s0, s3 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX11-GISEL-NEXT: s_cbranch_scc1 .LBB17_1 +; GFX11-GISEL-NEXT: ; %bb.2: +; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0x29a +; GFX11-GISEL-NEXT: s_mov_b32 s1, s32 +; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GFX11-GISEL-NEXT: s_mov_b32 s33, s4 +; GFX11-GISEL-NEXT: s_add_u32 s32, s1, s0 +; GFX11-GISEL-NEXT: scratch_store_b32 off, v0, s1 dlc +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_add_i32 s32, s32, -16 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] + %alloca = alloca i32, i64 %n, align 2, addrspace(5) + store volatile i32 666, ptr addrspace(5) %alloca + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll b/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll index ebfb5e9ccaa3..a324ba35b155 100644 --- a/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/fdiv_flags.f32.ll @@ -1625,14 +1625,12 @@ define float @v_recip_sqrt_f32_ulp25_contract(float %x) { ; CODEGEN-IEEE-GISEL: ; %bb.0: ; CODEGEN-IEEE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v2, 0x4b800000 ; CODEGEN-IEEE-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 24, vcc +; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; CODEGEN-IEEE-GISEL-NEXT: v_rsq_f32_e32 v0, v0 -; CODEGEN-IEEE-GISEL-NEXT: v_mov_b32_e32 v1, 0x45800000 -; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; CODEGEN-IEEE-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; CODEGEN-IEEE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 12, vcc +; CODEGEN-IEEE-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; CODEGEN-IEEE-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; IR-IEEE-SDAG-LABEL: v_recip_sqrt_f32_ulp25_contract: diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll index 97d642b991f7..5415af02ef89 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll @@ -5249,6 +5249,114 @@ bb: ret void } +define amdgpu_gs void @sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset(ptr addrspace(5) inreg %sgpr_base, i32 inreg %sidx, i32 %vidx) { +; GFX9-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX9: ; %bb.0: ; %bb +; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s5 +; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 +; GFX9-NEXT: s_add_i32 s2, s2, s3 +; GFX9-NEXT: v_add_u32_e32 v0, s2, v0 +; GFX9-NEXT: v_add_u32_e32 v0, -16, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, 15 +; GFX9-NEXT: scratch_store_dword v0, v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX10: ; %bb.0: ; %bb +; GFX10-NEXT: s_add_u32 s0, s0, s5 +; GFX10-NEXT: s_addc_u32 s1, s1, 0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 +; GFX10-NEXT: v_add3_u32 v0, s2, s3, v0 +; GFX10-NEXT: v_mov_b32_e32 v1, 15 +; GFX10-NEXT: scratch_store_dword v0, v1, off offset:-16 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX11: ; %bb.0: ; %bb +; GFX11-NEXT: v_add3_u32 v0, s0, s1, v0 +; GFX11-NEXT: v_mov_b32_e32 v1, 15 +; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX12: ; %bb.0: ; %bb +; GFX12-NEXT: v_mov_b32_e32 v1, 15 +; GFX12-NEXT: s_add_co_i32 s0, s0, s1 +; GFX12-NEXT: scratch_store_b32 v0, v1, s0 offset:-16 scope:SCOPE_SYS +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm +; +; GFX9-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX9-PAL: ; %bb.0: ; %bb +; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] +; GFX9-PAL-NEXT: s_mov_b32 s2, s8 +; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff +; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s5 +; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 +; GFX9-PAL-NEXT: s_add_i32 s0, s0, s1 +; GFX9-PAL-NEXT: v_add_u32_e32 v0, s0, v0 +; GFX9-PAL-NEXT: v_add_u32_e32 v0, -16, v0 +; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off +; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) +; GFX9-PAL-NEXT: s_endpgm +; +; GFX940-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX940: ; %bb.0: ; %bb +; GFX940-NEXT: s_add_i32 s0, s0, s1 +; GFX940-NEXT: v_add_u32_e32 v0, s0, v0 +; GFX940-NEXT: v_add_u32_e32 v0, -16, v0 +; GFX940-NEXT: v_mov_b32_e32 v1, 15 +; GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1 +; GFX940-NEXT: s_waitcnt vmcnt(0) +; GFX940-NEXT: s_endpgm +; +; GFX10-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX10-PAL: ; %bb.0: ; %bb +; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] +; GFX10-PAL-NEXT: s_mov_b32 s2, s8 +; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff +; GFX10-PAL-NEXT: s_add_u32 s2, s2, s5 +; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 +; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 +; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 +; GFX10-PAL-NEXT: v_add3_u32 v0, s0, s1, v0 +; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off offset:-16 +; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-PAL-NEXT: s_endpgm +; +; GFX11-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX11-PAL: ; %bb.0: ; %bb +; GFX11-PAL-NEXT: v_add3_u32 v0, s0, s1, v0 +; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-PAL-NEXT: s_endpgm +; +; GFX12-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX12-PAL: ; %bb.0: ; %bb +; GFX12-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX12-PAL-NEXT: s_add_co_i32 s0, s0, s1 +; GFX12-PAL-NEXT: scratch_store_b32 v0, v1, s0 offset:-16 scope:SCOPE_SYS +; GFX12-PAL-NEXT: s_wait_storecnt 0x0 +; GFX12-PAL-NEXT: s_endpgm +bb: + %add1 = add nsw i32 %sidx, %vidx + %add2 = add nsw i32 %add1, -16 + %gep = getelementptr inbounds [16 x i8], ptr addrspace(5) %sgpr_base, i32 0, i32 %add2 + store volatile i32 15, ptr addrspace(5) %gep, align 4 + ret void +} + define amdgpu_gs void @sgpr_base_negative_offset(ptr addrspace(1) %out, ptr addrspace(5) inreg %scevgep) { ; GFX9-LABEL: sgpr_base_negative_offset: ; GFX9: ; %bb.0: ; %entry diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll index 005e40159f61..822d40f7349b 100644 --- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll @@ -5,6 +5,8 @@ ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX10,GFX10-GISEL ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX12,GFX12-SDAG +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX12,GFX12-GISEL declare half @llvm.fma.f16(half, half, half) declare half @llvm.maxnum.f16(half, half) @@ -27,6 +29,16 @@ define half @test_fma(half %x, half %y, half %z) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fma_f16 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fma: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f16 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %r = call half @llvm.fma.f16(half %x, half %y, half %z) ret half %r } @@ -50,6 +62,16 @@ define half @test_fmac(half %x, half %y, half %z) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fmac_f16_e32 v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmac: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fmac_f16_e32 v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %r = call half @llvm.fma.f16(half %y, half %z, half %x) ret half %r } @@ -81,6 +103,16 @@ define half @test_fmaak(half %x, half %y, half %z) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fmaak_f16 v0, v0, v1, 0x4200 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmaak: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fmaak_f16 v0, v0, v1, 0x4200 +; GFX12-NEXT: s_setpc_b64 s[30:31] %r = call half @llvm.fma.f16(half %x, half %y, half 0xH4200) ret half %r } @@ -112,6 +144,16 @@ define half @test_fmamk(half %x, half %y, half %z) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fmamk_f16 v0, v0, 0x4200, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmamk: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fmamk_f16 v0, v0, 0x4200, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %r = call half @llvm.fma.f16(half %x, half 0xH4200, half %z) ret half %r } @@ -193,6 +235,42 @@ define i32 @test_D139469_f16(half %arg) { ; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-SDAG-LABEL: test_D139469_f16: +; GFX12-SDAG: ; %bb.0: ; %bb +; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-SDAG-NEXT: s_wait_expcnt 0x0 +; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0 +; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0 +; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e +; GFX12-SDAG-NEXT: v_mul_f16_e32 v2, 0x291e, v0 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_fmac_f16_e32 v1, 0x291e, v0 +; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0, v2, v1 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0 +; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-GISEL-LABEL: test_D139469_f16: +; GFX12-GISEL: ; %bb.0: ; %bb +; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-GISEL-NEXT: s_wait_expcnt 0x0 +; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0 +; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0 +; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e +; GFX12-GISEL-NEXT: v_mul_f16_e32 v2, 0x291e, v0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_fmac_f16_e32 v1, 0x291e, v0 +; GFX12-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_cmp_gt_f16_e64 s0, 0, v1 +; GFX12-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0 +; GFX12-GISEL-NEXT: s_wait_alu 0xfffe +; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31] bb: %i = fmul contract half %arg, 0xH291E %i1 = fcmp olt half %i, 0xH0000 @@ -306,6 +384,55 @@ define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) { ; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-SDAG-LABEL: test_D139469_v2f16: +; GFX12-SDAG: ; %bb.0: ; %bb +; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-SDAG-NEXT: s_wait_expcnt 0x0 +; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0 +; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0 +; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX12-SDAG-NEXT: s_movk_i32 s0, 0x211e +; GFX12-SDAG-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1] +; GFX12-SDAG-NEXT: s_wait_alu 0xfffe +; GFX12-SDAG-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s0 op_sel_hi:[0,1,0] +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_pk_min_num_f16 v0, v1, v0 +; GFX12-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX12-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0 +; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1 +; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-GISEL-LABEL: test_D139469_v2f16: +; GFX12-GISEL: ; %bb.0: ; %bb +; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-GISEL-NEXT: s_wait_expcnt 0x0 +; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0 +; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0 +; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e211e +; GFX12-GISEL-NEXT: v_pk_mul_f16 v2, 0x291e291e, v0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_pk_fma_f16 v0, 0x291e291e, v0, v1 +; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX12-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX12-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GFX12-GISEL-NEXT: v_cmp_gt_f16_e64 s0, 0, v0 +; GFX12-GISEL-NEXT: v_cmp_gt_f16_e64 s1, 0, v1 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-GISEL-NEXT: v_cmp_gt_f16_e64 s2, 0, v3 +; GFX12-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0 +; GFX12-GISEL-NEXT: s_wait_alu 0xfffe +; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-GISEL-NEXT: s_or_b32 s0, s1, s2 +; GFX12-GISEL-NEXT: s_wait_alu 0xfffe +; GFX12-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31] bb: %i = fmul contract <2 x half> %arg, <half 0xH291E, half 0xH291E> %i1 = fcmp olt <2 x half> %i, <half 0xH0000, half 0xH0000> diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.ll b/llvm/test/CodeGen/AMDGPU/fmax3.ll index 4b3f0dbbaea9..fbcdbed338e6 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax3.ll @@ -3,6 +3,7 @@ ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12 %s define amdgpu_kernel void @test_fmax3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #0 { ; SI-LABEL: test_fmax3_olt_0_f32: @@ -124,6 +125,36 @@ define amdgpu_kernel void @test_fmax3_olt_0_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_max3_f32 v0, v0, v1, v2 ; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmax3_olt_0_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_b32 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_max3_num_f32 v0, v0, v1, v2 +; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile float, ptr addrspace(1) %aptr, align 4 %b = load volatile float, ptr addrspace(1) %bptr, align 4 %c = load volatile float, ptr addrspace(1) %cptr, align 4 @@ -254,6 +285,36 @@ define amdgpu_kernel void @test_fmax3_olt_1_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_max3_f32 v0, v2, v0, v1 ; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmax3_olt_1_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_b32 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_max3_num_f32 v0, v2, v0, v1 +; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile float, ptr addrspace(1) %aptr, align 4 %b = load volatile float, ptr addrspace(1) %bptr, align 4 %c = load volatile float, ptr addrspace(1) %cptr, align 4 @@ -391,6 +452,36 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_max3_f16 v0, v0, v1, v2 ; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmax3_olt_0_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_max3_num_f16 v0, v0, v1, v2 +; GFX12-NEXT: buffer_store_b16 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile half, ptr addrspace(1) %aptr, align 2 %b = load volatile half, ptr addrspace(1) %bptr, align 2 %c = load volatile half, ptr addrspace(1) %cptr, align 2 @@ -529,6 +620,36 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_max3_f16 v0, v2, v0, v1 ; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmax3_olt_1_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_max3_num_f16 v0, v2, v0, v1 +; GFX12-NEXT: buffer_store_b16 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile half, ptr addrspace(1) %aptr, align 2 %b = load volatile half, ptr addrspace(1) %bptr, align 2 %c = load volatile half, ptr addrspace(1) %cptr, align 2 @@ -594,6 +715,19 @@ define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, < ; GFX11-NEXT: v_pk_max_f16 v0, v2, v0 ; GFX11-NEXT: v_pk_max_f16 v0, v0, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: no_fmax3_v2f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_pk_max_num_f16 v0, v2, v0 +; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v3 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b) %max1 = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %max) diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll index 38b712e044df..269fd52df5c4 100644 --- a/llvm/test/CodeGen/AMDGPU/fmin3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll @@ -3,6 +3,7 @@ ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX12 %s define amdgpu_kernel void @test_fmin3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) #0 { ; SI-LABEL: test_fmin3_olt_0_f32: @@ -124,6 +125,36 @@ define amdgpu_kernel void @test_fmin3_olt_0_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_min3_f32 v0, v0, v1, v2 ; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmin3_olt_0_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_b32 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_min3_num_f32 v0, v0, v1, v2 +; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile float, ptr addrspace(1) %aptr, align 4 %b = load volatile float, ptr addrspace(1) %bptr, align 4 %c = load volatile float, ptr addrspace(1) %cptr, align 4 @@ -254,6 +285,36 @@ define amdgpu_kernel void @test_fmin3_olt_1_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_min3_f32 v0, v2, v0, v1 ; GFX11-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmin3_olt_1_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_b32 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b32 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_min3_num_f32 v0, v2, v0, v1 +; GFX12-NEXT: buffer_store_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile float, ptr addrspace(1) %aptr, align 4 %b = load volatile float, ptr addrspace(1) %bptr, align 4 %c = load volatile float, ptr addrspace(1) %cptr, align 4 @@ -391,6 +452,36 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_min3_f16 v0, v0, v1, v2 ; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmin3_olt_0_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_min3_num_f16 v0, v0, v1, v2 +; GFX12-NEXT: buffer_store_b16 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile half, ptr addrspace(1) %aptr, align 2 %b = load volatile half, ptr addrspace(1) %bptr, align 2 %c = load volatile half, ptr addrspace(1) %cptr, align 2 @@ -529,6 +620,36 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_min3_f16 v0, v2, v0, v1 ; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmin3_olt_1_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_mov_b32 s22, s10 +; GFX12-NEXT: s_mov_b32 s23, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: s_mov_b32 s20, s6 +; GFX12-NEXT: s_mov_b32 s21, s7 +; GFX12-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_min3_num_f16 v0, v2, v0, v1 +; GFX12-NEXT: buffer_store_b16 v0, off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile half, ptr addrspace(1) %aptr, align 2 %b = load volatile half, ptr addrspace(1) %bptr, align 2 %c = load volatile half, ptr addrspace(1) %cptr, align 2 @@ -594,6 +715,19 @@ define <2 x half> @no_fmin3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, < ; GFX11-NEXT: v_pk_min_f16 v0, v2, v0 ; GFX11-NEXT: v_pk_min_f16 v0, v0, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: no_fmin3_v2f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_pk_min_num_f16 v0, v2, v0 +; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v3 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %min = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b) %min1 = call <2 x half> @llvm.minnum.v2f16(<2 x half> %c, <2 x half> %min) @@ -734,6 +868,39 @@ define amdgpu_kernel void @test_fmin3_olt_0_f64(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] ; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmin3_olt_0_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: buffer_load_b64 v[0:1], off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b64 v[2:3], off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s6 +; GFX12-NEXT: s_mov_b32 s13, s7 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1] +; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3] +; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5] +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3] +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile double, ptr addrspace(1) %aptr, align 4 %b = load volatile double, ptr addrspace(1) %bptr, align 4 %c = load volatile double, ptr addrspace(1) %cptr, align 4 @@ -877,6 +1044,39 @@ define amdgpu_kernel void @test_fmin3_olt_1_f64(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: v_min_f64 v[0:1], v[2:3], v[0:1] ; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[8:11], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: test_fmin3_olt_1_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b256 s[0:7], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s10, -1 +; GFX12-NEXT: s_mov_b32 s11, 0x31016000 +; GFX12-NEXT: s_mov_b32 s14, s10 +; GFX12-NEXT: s_mov_b32 s15, s11 +; GFX12-NEXT: s_mov_b32 s18, s10 +; GFX12-NEXT: s_mov_b32 s19, s11 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s2 +; GFX12-NEXT: s_mov_b32 s13, s3 +; GFX12-NEXT: s_mov_b32 s16, s4 +; GFX12-NEXT: s_mov_b32 s17, s5 +; GFX12-NEXT: buffer_load_b64 v[0:1], off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: buffer_load_b64 v[2:3], off, s[16:19], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s12, s6 +; GFX12-NEXT: s_mov_b32 s13, s7 +; GFX12-NEXT: s_mov_b32 s8, s0 +; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[12:15], null scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s9, s1 +; GFX12-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1] +; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[2:3], v[2:3] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[0:1], v[2:3] +; GFX12-NEXT: v_max_num_f64_e32 v[2:3], v[4:5], v[4:5] +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], v[2:3], v[0:1] +; GFX12-NEXT: buffer_store_b64 v[0:1], off, s[8:11], null +; GFX12-NEXT: s_endpgm %a = load volatile double, ptr addrspace(1) %aptr, align 4 %b = load volatile double, ptr addrspace(1) %bptr, align 4 %c = load volatile double, ptr addrspace(1) %cptr, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll index 104e157e9e15..9ae60f99d5e0 100644 --- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll +++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll @@ -3307,489 +3307,459 @@ define amdgpu_ps i32 @s_mul_32_f16(half inreg %x, half inreg %y) { ; -------------------------------------------------------------------- define float @v_mul_f32_select_64_1(i32 %arg, float %x) { -; GFX9-SDAG-LABEL: v_mul_f32_select_64_1: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc -; GFX9-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f32_select_64_1: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f32_select_64_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f32_select_64_1: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f32_select_64_1: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX1011-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] + %cond = icmp eq i32 %arg, 0 + %select.pow2 = select i1 %cond, float 64.0, float 1.0 + %mul = fmul float %x, %select.pow2 + ret float %mul +} + +define float @v_mul_f32_select_1_64(i32 %arg, float %x) { +; GFX9-LABEL: v_mul_f32_select_1_64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f32_select_64_1: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x42800000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f32_select_1_64: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX1011-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] + %cond = icmp eq i32 %arg, 0 + %select.pow2 = select i1 %cond, float 1.0, float 64.0 + %mul = fmul float %x, %select.pow2 + ret float %mul +} + +define float @v_mul_f32_select_n1_n64(i32 %arg, float %x) { +; GFX9-LABEL: v_mul_f32_select_n1_n64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f32_select_64_1: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f32_select_n1_n64: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX1011-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] + %cond = icmp eq i32 %arg, 0 + %select.pow2 = select i1 %cond, float -1.0, float -64.0 + %mul = fmul float %x, %select.pow2 + ret float %mul +} + +define float @v_mul_f32_select_n64_n1(i32 %arg, float %x) { +; GFX9-LABEL: v_mul_f32_select_n64_n1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f32_select_64_1: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x42800000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f32_select_n64_n1: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX1011-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float 64.0, float 1.0 + %select.pow2 = select i1 %cond, float -64.0, float -1.0 %mul = fmul float %x, %select.pow2 ret float %mul } -define float @v_mul_f32_select_1_64(i32 %arg, float %x) { -; GFX9-SDAG-LABEL: v_mul_f32_select_1_64: +define float @v_mul_f32_select_128_64(i32 %arg, float %x) { +; GFX9-SDAG-LABEL: v_mul_f32_select_128_64: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc ; GFX9-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-GISEL-LABEL: v_mul_f32_select_1_64: +; GFX9-GISEL-LABEL: v_mul_f32_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 1.0, vcc -; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f32_select_1_64: +; GFX10-SDAG-LABEL: v_mul_f32_select_128_64: ; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo ; GFX10-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f32_select_1_64: +; GFX10-GISEL-LABEL: v_mul_f32_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0x42800000, 1.0, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f32_select_1_64: +; GFX11-SDAG-LABEL: v_mul_f32_select_128_64: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo ; GFX11-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f32_select_1_64: +; GFX11-GISEL-LABEL: v_mul_f32_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0x42800000, 1.0, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float 1.0, float 64.0 + %select.pow2 = select i1 %cond, float 128.0, float 64.0 %mul = fmul float %x, %select.pow2 ret float %mul } -define float @v_mul_f32_select_n1_n64(i32 %arg, float %x) { -; GFX9-SDAG-LABEL: v_mul_f32_select_n1_n64: +define float @v_mul_f32_select_n128_n64(i32 %arg, float %x) { +; GFX9-SDAG-LABEL: v_mul_f32_select_n128_n64: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc ; GFX9-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-GISEL-LABEL: v_mul_f32_select_n1_n64: +; GFX9-GISEL-LABEL: v_mul_f32_select_n128_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2800000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, -1.0, vcc -; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f32_select_n1_n64: +; GFX10-SDAG-LABEL: v_mul_f32_select_n128_n64: ; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo ; GFX10-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f32_select_n1_n64: +; GFX10-GISEL-LABEL: v_mul_f32_select_n128_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0xc2800000, -1.0, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f32_select_n1_n64: +; GFX11-SDAG-LABEL: v_mul_f32_select_n128_n64: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo ; GFX11-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f32_select_n1_n64: +; GFX11-GISEL-LABEL: v_mul_f32_select_n128_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0xc2800000, -1.0, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float -1.0, float -64.0 + %select.pow2 = select i1 %cond, float -128.0, float -64.0 %mul = fmul float %x, %select.pow2 ret float %mul } -define float @v_mul_f32_select_n64_n1(i32 %arg, float %x) { -; GFX9-SDAG-LABEL: v_mul_f32_select_n64_n1: +define float @v_mul_f32_select_n128_n16(i32 %arg, float %x) { +; GFX9-LABEL: v_mul_f32_select_n128_n16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc +; GFX9-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX1011-LABEL: v_mul_f32_select_n128_n16: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo +; GFX1011-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] + %cond = icmp eq i32 %arg, 0 + %select.pow2 = select i1 %cond, float -128.0, float -16.0 + %mul = fmul float %x, %select.pow2 + ret float %mul +} + +define float @v_contract_mul_add_f32_select_64_1(i32 %arg, float %x, float %y) { +; GFX9-SDAG-LABEL: v_contract_mul_add_f32_select_64_1: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000 ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc -; GFX9-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; GFX9-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-GISEL-LABEL: v_mul_f32_select_n64_n1: +; GFX9-GISEL-LABEL: v_contract_mul_add_f32_select_64_1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2800000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, -1.0, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f32_select_n64_n1: +; GFX10-SDAG-LABEL: v_contract_mul_add_f32_select_64_1: ; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x42800000, vcc_lo +; GFX10-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f32_select_n64_n1: +; GFX10-GISEL-LABEL: v_contract_mul_add_f32_select_64_1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, -1.0, 0xc2800000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f32_select_n64_n1: +; GFX11-SDAG-LABEL: v_contract_mul_add_f32_select_64_1: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x42800000, vcc_lo +; GFX11-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f32_select_n64_n1: +; GFX11-GISEL-LABEL: v_contract_mul_add_f32_select_64_1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, -1.0, 0xc2800000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float -64.0, float -1.0 - %mul = fmul float %x, %select.pow2 - ret float %mul + %select.pow2 = select contract i1 %cond, float 64.0, float 1.0 + %mul = fmul contract float %x, %select.pow2 + %fma = fadd contract float %mul, %y + ret float %fma } -define float @v_mul_f32_select_128_64(i32 %arg, float %x) { -; GFX9-SDAG-LABEL: v_mul_f32_select_128_64: +define float @v_contract_mul_add_f32_select_1_64(i32 %arg, float %x, float %y) { +; GFX9-SDAG-LABEL: v_contract_mul_add_f32_select_1_64: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000 ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc -; GFX9-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v3, 1.0, vcc +; GFX9-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-GISEL-LABEL: v_mul_f32_select_128_64: +; GFX9-GISEL-LABEL: v_contract_mul_add_f32_select_1_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x43000000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f32_select_128_64: +; GFX10-SDAG-LABEL: v_contract_mul_add_f32_select_1_64: ; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0x42800000, 1.0, vcc_lo +; GFX10-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f32_select_128_64: +; GFX10-GISEL-LABEL: v_contract_mul_add_f32_select_1_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x43000000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f32_select_128_64: +; GFX11-SDAG-LABEL: v_contract_mul_add_f32_select_1_64: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0x42800000, 1.0, vcc_lo +; GFX11-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f32_select_128_64: +; GFX11-GISEL-LABEL: v_contract_mul_add_f32_select_1_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x43000000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float 128.0, float 64.0 - %mul = fmul float %x, %select.pow2 - ret float %mul + %select.pow2 = select contract i1 %cond, float 1.0, float 64.0 + %mul = fmul contract float %x, %select.pow2 + %fma = fadd contract float %mul, %y + ret float %fma } -define float @v_mul_f32_select_n128_n64(i32 %arg, float %x) { -; GFX9-SDAG-LABEL: v_mul_f32_select_n128_n64: +define float @v_contract_mul_add_f32_select_n64_n1(i32 %arg, float %x, float %y) { +; GFX9-SDAG-LABEL: v_contract_mul_add_f32_select_n64_n1: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xc2800000 ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc -; GFX9-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, -1.0, v3, vcc +; GFX9-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-GISEL-LABEL: v_mul_f32_select_n128_n64: +; GFX9-GISEL-LABEL: v_contract_mul_add_f32_select_n64_n1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xc3000000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xc2800000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f32_select_n128_n64: +; GFX10-SDAG-LABEL: v_contract_mul_add_f32_select_n64_n1: ; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, -1.0, 0xc2800000, vcc_lo +; GFX10-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f32_select_n128_n64: +; GFX10-GISEL-LABEL: v_contract_mul_add_f32_select_n64_n1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2800000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xc3000000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f32_select_n128_n64: +; GFX11-SDAG-LABEL: v_contract_mul_add_f32_select_n64_n1: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, -1.0, 0xc2800000, vcc_lo +; GFX11-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f32_select_n128_n64: +; GFX11-GISEL-LABEL: v_contract_mul_add_f32_select_n64_n1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2800000 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xc3000000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float -128.0, float -64.0 - %mul = fmul float %x, %select.pow2 - ret float %mul + %select.pow2 = select contract i1 %cond, float -64.0, float -1.0 + %mul = fmul contract float %x, %select.pow2 + %fma = fadd contract float %mul, %y + ret float %fma } -define float @v_mul_f32_select_n128_n16(i32 %arg, float %x) { -; GFX9-SDAG-LABEL: v_mul_f32_select_n128_n16: +define float @v_contract_mul_add_f32_select_n1_n64(i32 %arg, float %x, float %y) { +; GFX9-SDAG-LABEL: v_contract_mul_add_f32_select_n1_n64: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xc2800000 ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc -; GFX9-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v3, -1.0, vcc +; GFX9-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-GISEL-LABEL: v_mul_f32_select_n128_n16: +; GFX9-GISEL-LABEL: v_contract_mul_add_f32_select_n1_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xc3000000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1800000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f32_select_n128_n16: +; GFX10-SDAG-LABEL: v_contract_mul_add_f32_select_n1_n64: ; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0xc2800000, -1.0, vcc_lo +; GFX10-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f32_select_n128_n16: +; GFX10-GISEL-LABEL: v_contract_mul_add_f32_select_n1_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0xc1800000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xc3000000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f32_select_n128_n16: +; GFX11-SDAG-LABEL: v_contract_mul_add_f32_select_n1_n64: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0xc2800000, -1.0, vcc_lo +; GFX11-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f32_select_n128_n16: +; GFX11-GISEL-LABEL: v_contract_mul_add_f32_select_n1_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0xc1800000 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xc3000000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, -v1, v0 +; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float -128.0, float -16.0 - %mul = fmul float %x, %select.pow2 - ret float %mul -} - -define float @v_contract_mul_add_f32_select_64_1(i32 %arg, float %x, float %y) { -; GFX9-LABEL: v_contract_mul_add_f32_select_64_1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc -; GFX9-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1011-LABEL: v_contract_mul_add_f32_select_64_1: -; GFX1011: ; %bb.0: -; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1011-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x42800000, vcc_lo -; GFX1011-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX1011-NEXT: s_setpc_b64 s[30:31] - %cond = icmp eq i32 %arg, 0 - %select.pow2 = select contract i1 %cond, float 64.0, float 1.0 - %mul = fmul contract float %x, %select.pow2 - %fma = fadd contract float %mul, %y - ret float %fma -} - -define float @v_contract_mul_add_f32_select_1_64(i32 %arg, float %x, float %y) { -; GFX9-LABEL: v_contract_mul_add_f32_select_1_64: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x42800000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, 1.0, vcc -; GFX9-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1011-LABEL: v_contract_mul_add_f32_select_1_64: -; GFX1011: ; %bb.0: -; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1011-NEXT: v_cndmask_b32_e64 v0, 0x42800000, 1.0, vcc_lo -; GFX1011-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX1011-NEXT: s_setpc_b64 s[30:31] - %cond = icmp eq i32 %arg, 0 - %select.pow2 = select contract i1 %cond, float 1.0, float 64.0 - %mul = fmul contract float %x, %select.pow2 - %fma = fadd contract float %mul, %y - ret float %fma -} - -define float @v_contract_mul_add_f32_select_n64_n1(i32 %arg, float %x, float %y) { -; GFX9-LABEL: v_contract_mul_add_f32_select_n64_n1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2800000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, -1.0, v3, vcc -; GFX9-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1011-LABEL: v_contract_mul_add_f32_select_n64_n1: -; GFX1011: ; %bb.0: -; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1011-NEXT: v_cndmask_b32_e64 v0, -1.0, 0xc2800000, vcc_lo -; GFX1011-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX1011-NEXT: s_setpc_b64 s[30:31] - %cond = icmp eq i32 %arg, 0 - %select.pow2 = select contract i1 %cond, float -64.0, float -1.0 - %mul = fmul contract float %x, %select.pow2 - %fma = fadd contract float %mul, %y - ret float %fma -} - -define float @v_contract_mul_add_f32_select_n1_n64(i32 %arg, float %x, float %y) { -; GFX9-LABEL: v_contract_mul_add_f32_select_n1_n64: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0xc2800000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, -1.0, vcc -; GFX9-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1011-LABEL: v_contract_mul_add_f32_select_n1_n64: -; GFX1011: ; %bb.0: -; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1011-NEXT: v_cndmask_b32_e64 v0, 0xc2800000, -1.0, vcc_lo -; GFX1011-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX1011-NEXT: s_setpc_b64 s[30:31] - %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, float -1.0, float -64.0 %mul = fmul contract float %x, %select.pow2 %fma = fadd contract float %mul, %y @@ -3810,11 +3780,11 @@ define float @v_contract_mul_add_f32_select_128_64(i32 %arg, float %x, float %y) ; GFX9-GISEL-LABEL: v_contract_mul_add_f32_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x43000000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x42800000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f32 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f32_select_128_64: @@ -3829,10 +3799,11 @@ define float @v_contract_mul_add_f32_select_128_64(i32 %arg, float %x, float %y) ; GFX10-GISEL-LABEL: v_contract_mul_add_f32_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x43000000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f32 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f32_select_128_64: @@ -3847,10 +3818,11 @@ define float @v_contract_mul_add_f32_select_128_64(i32 %arg, float %x, float %y) ; GFX11-GISEL-LABEL: v_contract_mul_add_f32_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x43000000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f32 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, float 128.0, float 64.0 @@ -3860,22 +3832,57 @@ define float @v_contract_mul_add_f32_select_128_64(i32 %arg, float %x, float %y) } define float @v_contract_mul_add_f32_select_128_4(i32 %arg, float %x, float %y) { -; GFX9-LABEL: v_contract_mul_add_f32_select_128_4: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x43000000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, 4.0, v3, vcc -; GFX9-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: v_contract_mul_add_f32_select_128_4: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x43000000 +; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, 4.0, v3, vcc +; GFX9-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX1011-LABEL: v_contract_mul_add_f32_select_128_4: -; GFX1011: ; %bb.0: -; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1011-NEXT: v_cndmask_b32_e64 v0, 4.0, 0x43000000, vcc_lo -; GFX1011-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX1011-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: v_contract_mul_add_f32_select_128_4: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: v_contract_mul_add_f32_select_128_4: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 4.0, 0x43000000, vcc_lo +; GFX10-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: v_contract_mul_add_f32_select_128_4: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: v_contract_mul_add_f32_select_128_4: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 4.0, 0x43000000, vcc_lo +; GFX11-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: v_contract_mul_add_f32_select_128_4: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, float 128.0, float 4.0 %mul = fmul contract float %x, %select.pow2 @@ -3907,143 +3914,102 @@ define float @v_contract_mul_add_f32_select_2_4(i32 %arg, float %x, float %y) { } define float @v_contract_mul_add_f32_select_4_128(i32 %arg, float %x, float %y) { -; GFX9-LABEL: v_contract_mul_add_f32_select_4_128: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v3, 0x43000000 -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, 4.0, vcc -; GFX9-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX1011-LABEL: v_contract_mul_add_f32_select_4_128: -; GFX1011: ; %bb.0: -; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1011-NEXT: v_cndmask_b32_e64 v0, 0x43000000, 4.0, vcc_lo -; GFX1011-NEXT: v_fma_f32 v0, v1, v0, v2 -; GFX1011-NEXT: s_setpc_b64 s[30:31] - %cond = icmp eq i32 %arg, 0 - %select.pow2 = select i1 %cond, float 4.0, float 128.0 - %mul = fmul contract float %x, %select.pow2 - %fma = fadd contract float %mul, %y - ret float %fma -} - -define double @v_mul_f64_select_64_1(i32 %arg, double %x) { -; GFX9-SDAG-LABEL: v_mul_f64_select_64_1: +; GFX9-SDAG-LABEL: v_contract_mul_add_f32_select_4_128: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x43000000 ; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc -; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v3, 4.0, vcc +; GFX9-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-GISEL-LABEL: v_mul_f64_select_64_1: +; GFX9-GISEL-LABEL: v_contract_mul_add_f32_select_4_128: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x40500000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x3ff00000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc +; GFX9-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-SDAG-LABEL: v_mul_f64_select_64_1: +; GFX10-SDAG-LABEL: v_contract_mul_add_f32_select_4_128: ; GFX10-SDAG: ; %bb.0: ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0x43000000, 4.0, vcc_lo +; GFX10-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-GISEL-LABEL: v_mul_f64_select_64_1: +; GFX10-GISEL-LABEL: v_contract_mul_add_f32_select_4_128: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x3ff00000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0x40500000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-SDAG-LABEL: v_mul_f64_select_64_1: +; GFX11-SDAG-LABEL: v_contract_mul_add_f32_select_4_128: ; GFX11-SDAG: ; %bb.0: ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0x43000000, 4.0, vcc_lo +; GFX11-SDAG-NEXT: v_fma_f32 v0, v1, v0, v2 ; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f64_select_64_1: +; GFX11-GISEL-LABEL: v_contract_mul_add_f32_select_4_128: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0x3ff00000 :: v_dual_mov_b32 v3, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0x40500000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 + %select.pow2 = select i1 %cond, float 4.0, float 128.0 + %mul = fmul contract float %x, %select.pow2 + %fma = fadd contract float %mul, %y + ret float %fma +} + +define double @v_mul_f64_select_64_1(i32 %arg, double %x) { +; GFX9-LABEL: v_mul_f64_select_64_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX1011-LABEL: v_mul_f64_select_64_1: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX1011-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] + %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double 64.0, double 1.0 %mul = fmul double %x, %select.pow2 ret double %mul } define double @v_mul_f64_select_1_64(i32 %arg, double %x) { -; GFX9-SDAG-LABEL: v_mul_f64_select_1_64: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc -; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f64_select_1_64: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x3ff00000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x40500000 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-SDAG-LABEL: v_mul_f64_select_1_64: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-GISEL-LABEL: v_mul_f64_select_1_64: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x40500000 -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0x3ff00000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SDAG-LABEL: v_mul_f64_select_1_64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f64_select_1_64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f64_select_1_64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0x40500000 :: v_dual_mov_b32 v3, 0 -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0x3ff00000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f64_select_1_64: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX1011-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double 1.0, double 64.0 %mul = fmul double %x, %select.pow2 @@ -4051,59 +4017,21 @@ define double @v_mul_f64_select_1_64(i32 %arg, double %x) { } define double @v_mul_f64_select_n1_n64(i32 %arg, double %x) { -; GFX9-SDAG-LABEL: v_mul_f64_select_n1_n64: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc -; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f64_select_n1_n64: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xbff00000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xc0500000 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-SDAG-LABEL: v_mul_f64_select_n1_n64: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-GISEL-LABEL: v_mul_f64_select_n1_n64: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0xc0500000 -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0xbff00000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SDAG-LABEL: v_mul_f64_select_n1_n64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f64_select_n1_n64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f64_select_n1_n64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0xc0500000 :: v_dual_mov_b32 v3, 0 -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0xbff00000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f64_select_n1_n64: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX1011-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double -1.0, double -64.0 %mul = fmul double %x, %select.pow2 @@ -4122,12 +4050,10 @@ define double @v_mul_f64_select_128_64(i32 %arg, double %x) { ; GFX9-GISEL-LABEL: v_mul_f64_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x40600000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x40500000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_f64_select_128_64: @@ -4141,11 +4067,10 @@ define double @v_mul_f64_select_128_64(i32 %arg, double %x) { ; GFX10-GISEL-LABEL: v_mul_f64_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x40500000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0x40600000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_f64_select_128_64: @@ -4159,10 +4084,10 @@ define double @v_mul_f64_select_128_64(i32 %arg, double %x) { ; GFX11-GISEL-LABEL: v_mul_f64_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0x40500000 :: v_dual_mov_b32 v3, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0x40600000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double 128.0, double 64.0 @@ -4182,12 +4107,10 @@ define double @v_mul_f64_select_n128_n64(i32 %arg, double %x) { ; GFX9-GISEL-LABEL: v_mul_f64_select_n128_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xc0600000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xc0500000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_f64_select_n128_n64: @@ -4201,11 +4124,10 @@ define double @v_mul_f64_select_n128_n64(i32 %arg, double %x) { ; GFX10-GISEL-LABEL: v_mul_f64_select_n128_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0xc0500000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0xc0600000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_f64_select_n128_n64: @@ -4219,10 +4141,10 @@ define double @v_mul_f64_select_n128_n64(i32 %arg, double %x) { ; GFX11-GISEL-LABEL: v_mul_f64_select_n128_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0xc0500000 :: v_dual_mov_b32 v3, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0xc0600000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double -128.0, double -64.0 @@ -4231,59 +4153,21 @@ define double @v_mul_f64_select_n128_n64(i32 %arg, double %x) { } define double @v_mul_f64_select_n128_n16(i32 %arg, double %x) { -; GFX9-SDAG-LABEL: v_mul_f64_select_n128_n16: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc -; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f64_select_n128_n16: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xc0600000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xc0300000 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-SDAG-LABEL: v_mul_f64_select_n128_n16: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-GISEL-LABEL: v_mul_f64_select_n128_n16: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0xc0300000 -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0xc0600000, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SDAG-LABEL: v_mul_f64_select_n128_n16: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f64_select_n128_n16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc +; GFX9-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f64_select_n128_n16: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0xc0300000 :: v_dual_mov_b32 v3, 0 -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0xc0600000, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[1:2], v[3:4] -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f64_select_n128_n16: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo +; GFX1011-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double -128.0, double -16.0 %mul = fmul double %x, %select.pow2 @@ -4305,12 +4189,10 @@ define double @v_contract_mul_add_f64_select_64_1(i32 %arg, double %x, double %y ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_64_1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x40500000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0x3ff00000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_64_1: @@ -4326,11 +4208,10 @@ define double @v_contract_mul_add_f64_select_64_1(i32 %arg, double %x, double %y ; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_64_1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, 0x3ff00000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40500000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_64_1: @@ -4345,10 +4226,10 @@ define double @v_contract_mul_add_f64_select_64_1(i32 %arg, double %x, double %y ; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_64_1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0x3ff00000 :: v_dual_mov_b32 v5, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40500000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, double 64.0, double 1.0 @@ -4372,12 +4253,10 @@ define double @v_contract_mul_add_f64_select_1_64(i32 %arg, double %x, double %y ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_1_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x3ff00000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0x40500000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_1_64: @@ -4393,11 +4272,10 @@ define double @v_contract_mul_add_f64_select_1_64(i32 %arg, double %x, double %y ; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_1_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, 0x40500000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x3ff00000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_1_64: @@ -4412,10 +4290,10 @@ define double @v_contract_mul_add_f64_select_1_64(i32 %arg, double %x, double %y ; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_1_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0x40500000 :: v_dual_mov_b32 v5, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x3ff00000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, double 1.0, double 64.0 @@ -4439,12 +4317,10 @@ define double @v_contract_mul_add_f64_select_n64_n1(i32 %arg, double %x, double ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_n64_n1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0xc0500000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0xbff00000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_n64_n1: @@ -4460,11 +4336,10 @@ define double @v_contract_mul_add_f64_select_n64_n1(i32 %arg, double %x, double ; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_n64_n1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, 0xbff00000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0xc0500000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_n64_n1: @@ -4479,10 +4354,10 @@ define double @v_contract_mul_add_f64_select_n64_n1(i32 %arg, double %x, double ; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_n64_n1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0xbff00000 :: v_dual_mov_b32 v5, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0xc0500000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, double -64.0, double -1.0 @@ -4506,12 +4381,10 @@ define double @v_contract_mul_add_f64_select_n1_n64(i32 %arg, double %x, double ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_n1_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0xbff00000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0xc0500000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_n1_n64: @@ -4527,11 +4400,10 @@ define double @v_contract_mul_add_f64_select_n1_n64(i32 %arg, double %x, double ; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_n1_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, 0xc0500000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0xbff00000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_n1_n64: @@ -4546,10 +4418,10 @@ define double @v_contract_mul_add_f64_select_n1_n64(i32 %arg, double %x, double ; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_n1_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0xc0500000 :: v_dual_mov_b32 v5, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0xbff00000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], -v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, double -1.0, double -64.0 @@ -4573,12 +4445,11 @@ define double @v_contract_mul_add_f64_select_128_64(i32 %arg, double %x, double ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x40600000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0x40500000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_128_64: @@ -4594,11 +4465,11 @@ define double @v_contract_mul_add_f64_select_128_64(i32 %arg, double %x, double ; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, 0x40500000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40600000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_128_64: @@ -4613,10 +4484,11 @@ define double @v_contract_mul_add_f64_select_128_64(i32 %arg, double %x, double ; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0x40500000 :: v_dual_mov_b32 v5, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40600000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double 128.0, double 64.0 @@ -4640,12 +4512,10 @@ define double @v_contract_mul_add_f64_select_128_4(i32 %arg, double %x, double % ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_128_4: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x40600000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0x40100000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_128_4: @@ -4661,11 +4531,10 @@ define double @v_contract_mul_add_f64_select_128_4(i32 %arg, double %x, double % ; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_128_4: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, 0x40100000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40600000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_128_4: @@ -4680,10 +4549,10 @@ define double @v_contract_mul_add_f64_select_128_4(i32 %arg, double %x, double % ; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_128_4: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0x40100000 :: v_dual_mov_b32 v5, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40600000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double 128.0, double 4.0 @@ -4706,21 +4575,50 @@ define double @v_contract_mul_add_f64_select_2_4(i32 %arg, double %x, double %y) ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_2_4: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x40100000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 2.0, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; -; GFX1011-LABEL: v_contract_mul_add_f64_select_2_4: -; GFX1011: ; %bb.0: -; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1011-NEXT: v_mov_b32_e32 v5, 0 -; GFX1011-NEXT: v_cndmask_b32_e64 v6, 0x40100000, 2.0, vcc_lo -; GFX1011-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] -; GFX1011-NEXT: s_setpc_b64 s[30:31] +; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_2_4: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v6, 0x40100000, 2.0, vcc_lo +; GFX10-SDAG-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_2_4: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0 +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_2_4: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v6, 0x40100000, 2.0, vcc_lo +; GFX11-SDAG-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_2_4: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0 +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double 2.0, double 4.0 %mul = fmul contract double %x, %select.pow2 @@ -4743,12 +4641,10 @@ define double @v_contract_mul_add_f64_select_4_128(i32 %arg, double %x, double % ; GFX9-GISEL-LABEL: v_contract_mul_add_f64_select_4_128: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x40100000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v7, 0x40600000 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc +; GFX9-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f64_select_4_128: @@ -4764,11 +4660,10 @@ define double @v_contract_mul_add_f64_select_4_128(i32 %arg, double %x, double % ; GFX10-GISEL-LABEL: v_contract_mul_add_f64_select_4_128: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, 0x40600000 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40100000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f64_select_4_128: @@ -4783,10 +4678,10 @@ define double @v_contract_mul_add_f64_select_4_128(i32 %arg, double %x, double % ; GFX11-GISEL-LABEL: v_contract_mul_add_f64_select_4_128: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, 0x40600000 :: v_dual_mov_b32 v5, 0 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0x40100000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], v[1:2], v[5:6], v[3:4] +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f64 v[0:1], v[1:2], v0 +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, double 4.0, double 128.0 @@ -4796,57 +4691,21 @@ define double @v_contract_mul_add_f64_select_4_128(i32 %arg, double %x, double % } define half @v_mul_f16_select_64_1(i32 %arg, half %x) { -; GFX9-SDAG-LABEL: v_mul_f16_select_64_1: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc -; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f16_select_64_1: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x5400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-SDAG-LABEL: v_mul_f16_select_64_1: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-GISEL-LABEL: v_mul_f16_select_64_1: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x3c00 -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x5400, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SDAG-LABEL: v_mul_f16_select_64_1: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f16_select_64_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f16_select_64_1: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x3c00 -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x5400, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f16_select_64_1: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX1011-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half 64.0, half 1.0 %mul = fmul half %x, %select.pow2 @@ -4854,57 +4713,21 @@ define half @v_mul_f16_select_64_1(i32 %arg, half %x) { } define half @v_mul_f16_select_1_64(i32 %arg, half %x) { -; GFX9-SDAG-LABEL: v_mul_f16_select_1_64: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc -; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f16_select_1_64: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x3c00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-SDAG-LABEL: v_mul_f16_select_1_64: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-GISEL-LABEL: v_mul_f16_select_1_64: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x5400 -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x3c00, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SDAG-LABEL: v_mul_f16_select_1_64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f16_select_1_64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f16_select_1_64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x5400 -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x3c00, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f16_select_1_64: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX1011-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half 1.0, half 64.0 %mul = fmul half %x, %select.pow2 @@ -4912,57 +4735,21 @@ define half @v_mul_f16_select_1_64(i32 %arg, half %x) { } define half @v_mul_f16_select_n1_n64(i32 %arg, half %x) { -; GFX9-SDAG-LABEL: v_mul_f16_select_n1_n64: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc -; GFX9-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f16_select_n1_n64: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xbc00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-SDAG-LABEL: v_mul_f16_select_n1_n64: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-GISEL-LABEL: v_mul_f16_select_n1_n64: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0xd400 -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xbc00, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SDAG-LABEL: v_mul_f16_select_n1_n64: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f16_select_n1_n64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f16_select_n1_n64: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0xd400 -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xbc00, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f16_select_n1_n64: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX1011-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half -1.0, half -64.0 %mul = fmul half %x, %select.pow2 @@ -4981,11 +4768,13 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) { ; GFX9-GISEL-LABEL: v_mul_f16_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x5800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_f16_select_128_64: @@ -4999,10 +4788,12 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) { ; GFX10-GISEL-LABEL: v_mul_f16_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x5400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x5800, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_f16_select_128_64: @@ -5016,10 +4807,12 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) { ; GFX11-GISEL-LABEL: v_mul_f16_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x5400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0x5800, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half 128.0, half 64.0 @@ -5039,11 +4832,13 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) { ; GFX9-GISEL-LABEL: v_mul_f16_select_n128_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xd800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v2, v3 +; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_f16_select_n128_n64: @@ -5057,10 +4852,12 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) { ; GFX10-GISEL-LABEL: v_mul_f16_select_n128_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0xd400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xd800, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2 +; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_f16_select_n128_n64: @@ -5074,10 +4871,12 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) { ; GFX11-GISEL-LABEL: v_mul_f16_select_n128_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0xd400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xd800, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half -128.0, half -64.0 @@ -5086,57 +4885,21 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) { } define half @v_mul_f16_select_n128_n16(i32 %arg, half %x) { -; GFX9-SDAG-LABEL: v_mul_f16_select_n128_n16: -; GFX9-SDAG: ; %bb.0: -; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc -; GFX9-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0 -; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-GISEL-LABEL: v_mul_f16_select_n128_n16: -; GFX9-GISEL: ; %bb.0: -; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xd800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xcc00 -; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-SDAG-LABEL: v_mul_f16_select_n128_n16: -; GFX10-SDAG: ; %bb.0: -; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo -; GFX10-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0 -; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-GISEL-LABEL: v_mul_f16_select_n128_n16: -; GFX10-GISEL: ; %bb.0: -; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0xcc00 -; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xd800, vcc_lo -; GFX10-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-SDAG-LABEL: v_mul_f16_select_n128_n16: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo -; GFX11-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0 -; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_mul_f16_select_n128_n16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc +; GFX9-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-GISEL-LABEL: v_mul_f16_select_n128_n16: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 0xcc00 -; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, 0xd800, vcc_lo -; GFX11-GISEL-NEXT: v_mul_f16_e32 v0, v1, v0 -; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; GFX1011-LABEL: v_mul_f16_select_n128_n16: +; GFX1011: ; %bb.0: +; GFX1011-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1011-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1011-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo +; GFX1011-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX1011-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half -128.0, half -16.0 %mul = fmul half %x, %select.pow2 @@ -5157,11 +4920,10 @@ define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_64_1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x3c00 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_64_1: @@ -5176,10 +4938,10 @@ define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_64_1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5400, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_64_1: @@ -5194,10 +4956,10 @@ define half @v_contract_mul_add_f16_select_64_1(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_64_1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5400, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, half 64.0, half 1.0 @@ -5220,11 +4982,10 @@ define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_1_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_1_64: @@ -5239,10 +5000,10 @@ define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_1_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x3c00, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_1_64: @@ -5257,10 +5018,10 @@ define half @v_contract_mul_add_f16_select_1_64(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_1_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x3c00, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, half 1.0, half 64.0 @@ -5283,11 +5044,10 @@ define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_n64_n1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xbc00 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_n64_n1: @@ -5302,10 +5062,10 @@ define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_n64_n1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xbc00 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xd400, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_n64_n1: @@ -5320,10 +5080,10 @@ define half @v_contract_mul_add_f16_select_n64_n1(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_n64_n1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xbc00 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xd400, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, half -64.0, half -1.0 @@ -5346,11 +5106,10 @@ define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_n1_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xbc00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xd400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_n1_n64: @@ -5365,10 +5124,10 @@ define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_n1_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xbc00, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_n1_n64: @@ -5383,10 +5142,10 @@ define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_n1_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xbc00, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select contract i1 %cond, half -1.0, half -64.0 @@ -5409,11 +5168,14 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x5800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_128_64: @@ -5428,10 +5190,13 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5800, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_128_64: @@ -5446,10 +5211,13 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5800, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half 128.0, half 64.0 @@ -5472,11 +5240,10 @@ define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_128_4: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x5800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x4400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_128_4: @@ -5491,10 +5258,10 @@ define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_128_4: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x4400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5800, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_128_4: @@ -5509,10 +5276,10 @@ define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_128_4: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x4400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5800, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half 128.0, half 4.0 @@ -5535,11 +5302,14 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_2_4: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x4000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x4400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 2, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_2_4: @@ -5554,10 +5324,13 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_2_4: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x4400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x4000, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_2_4: @@ -5572,10 +5345,13 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_2_4: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x4400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x4000, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0 +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half 2.0, half 4.0 @@ -5598,11 +5374,10 @@ define half @v_contract_mul_add_f16_select_4_128(i32 %arg, half %x, half %y) { ; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_4_128: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x4400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5800 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc -; GFX9-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_4_128: @@ -5617,10 +5392,10 @@ define half @v_contract_mul_add_f16_select_4_128(i32 %arg, half %x, half %y) { ; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_4_128: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x5800 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x4400, vcc_lo -; GFX10-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_f16_select_4_128: @@ -5635,10 +5410,10 @@ define half @v_contract_mul_add_f16_select_4_128(i32 %arg, half %x, half %y) { ; GFX11-GISEL-LABEL: v_contract_mul_add_f16_select_4_128: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x5800 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x4400, vcc_lo -; GFX11-GISEL-NEXT: v_fma_f16 v0, v1, v0, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0 +; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v0, v2 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq i32 %arg, 0 %select.pow2 = select i1 %cond, half 4.0, half 128.0 @@ -5664,15 +5439,13 @@ define <2 x half> @v_mul_v2f16_select_64_1(<2 x i32> %arg, <2 x half> %x) { ; GFX9-GISEL-LABEL: v_mul_v2f16_select_64_1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x3c00 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_v2f16_select_64_1: @@ -5690,14 +5463,14 @@ define <2 x half> @v_mul_v2f16_select_64_1(<2 x i32> %arg, <2 x half> %x) { ; GFX10-GISEL-LABEL: v_mul_v2f16_select_64_1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5400, vcc_lo +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x5400, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_v2f16_select_64_1: @@ -5715,14 +5488,15 @@ define <2 x half> @v_mul_v2f16_select_64_1(<2 x i32> %arg, <2 x half> %x) { ; GFX11-GISEL-LABEL: v_mul_v2f16_select_64_1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5400, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x5400, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v3, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 64.0, half 64.0>, <2 x half> <half 1.0, half 1.0> @@ -5747,15 +5521,13 @@ define <2 x half> @v_mul_v2f16_select_1_64(<2 x i32> %arg, <2 x half> %x) { ; GFX9-GISEL-LABEL: v_mul_v2f16_select_1_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_v2f16_select_1_64: @@ -5773,14 +5545,14 @@ define <2 x half> @v_mul_v2f16_select_1_64(<2 x i32> %arg, <2 x half> %x) { ; GFX10-GISEL-LABEL: v_mul_v2f16_select_1_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x3c00, vcc_lo +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x3c00, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_v2f16_select_1_64: @@ -5798,14 +5570,15 @@ define <2 x half> @v_mul_v2f16_select_1_64(<2 x i32> %arg, <2 x half> %x) { ; GFX11-GISEL-LABEL: v_mul_v2f16_select_1_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x3c00, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x3c00, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v3, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 1.0, half 1.0>, <2 x half> <half 64.0, half 64.0> @@ -5830,15 +5603,14 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) { ; GFX9-GISEL-LABEL: v_mul_v2f16_select_n1_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xbc00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xd400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_v2f16_select_n1_n64: @@ -5856,14 +5628,15 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) { ; GFX10-GISEL-LABEL: v_mul_v2f16_select_n1_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xbc00, vcc_lo +; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xbc00, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_v2f16_select_n1_n64: @@ -5881,14 +5654,16 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) { ; GFX11-GISEL-LABEL: v_mul_v2f16_select_n1_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xbc00, vcc_lo +; GFX11-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xbc00, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v3, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half -1.0, half -1.0>, <2 x half> <half -64.0, half -64.0> @@ -5913,15 +5688,19 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) { ; GFX9-GISEL-LABEL: v_mul_v2f16_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x5800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 6, v1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4 +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_v2f16_select_128_64: @@ -5939,14 +5718,19 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) { ; GFX10-GISEL-LABEL: v_mul_v2f16_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5800, vcc_lo +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x5800, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_v2f16_select_128_64: @@ -5964,14 +5748,20 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) { ; GFX11-GISEL-LABEL: v_mul_v2f16_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x5400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0x5800, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x5800, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 64.0, half 64.0> @@ -5996,15 +5786,20 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) { ; GFX9-GISEL-LABEL: v_mul_v2f16_select_n128_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xd800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xd400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 6, v1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4 +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_v2f16_select_n128_n64: @@ -6022,14 +5817,20 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) { ; GFX10-GISEL-LABEL: v_mul_v2f16_select_n128_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xd800, vcc_lo +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xd800, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_v2f16_select_n128_n64: @@ -6047,14 +5848,21 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) { ; GFX11-GISEL-LABEL: v_mul_v2f16_select_n128_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xd400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xd800, vcc_lo +; GFX11-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3 +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xd800, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half -128.0, half -128.0>, <2 x half> <half -64.0, half -64.0> @@ -6079,15 +5887,14 @@ define <2 x half> @v_mul_v2f16_select_n128_n16(<2 x i32> %arg, <2 x half> %x) { ; GFX9-GISEL-LABEL: v_mul_v2f16_select_n128_n16: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xd800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xcc00 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_mul_v2f16_select_n128_n16: @@ -6105,14 +5912,15 @@ define <2 x half> @v_mul_v2f16_select_n128_n16(<2 x i32> %arg, <2 x half> %x) { ; GFX10-GISEL-LABEL: v_mul_v2f16_select_n128_n16: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0xcc00 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xd800, vcc_lo +; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xd800, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_mul_v2f16_select_n128_n16: @@ -6130,14 +5938,16 @@ define <2 x half> @v_mul_v2f16_select_n128_n16(<2 x i32> %arg, <2 x half> %x) { ; GFX11-GISEL-LABEL: v_mul_v2f16_select_n128_n16: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0xcc00 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, 0xd800, vcc_lo +; GFX11-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 4, 7, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 4, 7, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xd800, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v3, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_mul_f16 v0, v2, v0 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half -128.0, half -128.0>, <2 x half> <half -16.0, half -16.0> @@ -6162,15 +5972,14 @@ define <2 x half> @v_contract_mul_add_v2f16_select_64_1(<2 x i32> %arg, <2 x hal ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_64_1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x3c00 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_64_1: @@ -6188,14 +5997,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_64_1(<2 x i32> %arg, <2 x hal ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_64_1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x3c00 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x5400, vcc_lo +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x5400, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_64_1: @@ -6213,14 +6023,16 @@ define <2 x half> @v_contract_mul_add_v2f16_select_64_1(<2 x i32> %arg, <2 x hal ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_64_1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0x3c00 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x5400, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x5400, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 64.0, half 64.0>, <2 x half> <half 1.0, half 1.0> @@ -6246,15 +6058,14 @@ define <2 x half> @v_contract_mul_add_v2f16_select_1_64(<2 x i32> %arg, <2 x hal ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_1_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x3c00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x5400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_1_64: @@ -6272,14 +6083,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_1_64(<2 x i32> %arg, <2 x hal ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_1_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x3c00, vcc_lo +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x3c00, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_1_64: @@ -6297,14 +6109,16 @@ define <2 x half> @v_contract_mul_add_v2f16_select_1_64(<2 x i32> %arg, <2 x hal ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_1_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x3c00, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x3c00, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 1.0, half 1.0>, <2 x half> <half 64.0, half 64.0> @@ -6330,15 +6144,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_n64_n1: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xd400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xbc00 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_n64_n1: @@ -6356,14 +6170,16 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_n64_n1: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0xbc00 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0xd400, vcc_lo +; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0xd400, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_n64_n1: @@ -6381,14 +6197,17 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n64_n1(<2 x i32> %arg, <2 x h ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_n64_n1: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0xbc00 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0xd400, vcc_lo +; GFX11-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 6, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 6, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0xd400, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half -64.0, half -64.0>, <2 x half> <half -1.0, half -1.0> @@ -6414,15 +6233,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_n1_n64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xbc00 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xd400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_n1_n64: @@ -6440,14 +6259,16 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_n1_n64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0xd400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0xbc00, vcc_lo +; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0xbc00, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_n1_n64: @@ -6465,14 +6286,17 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_n1_n64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0xd400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0xbc00, vcc_lo +; GFX11-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 6, 0, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0xbc00, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half -1.0, half -1.0>, <2 x half> <half -64.0, half -64.0> @@ -6498,15 +6322,20 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_64: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x5400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0 +; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 6, v1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v4, v5 +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v4, v5 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_64: @@ -6524,14 +6353,20 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_64: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x5800, vcc_lo +; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4 ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x5800, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_64: @@ -6549,14 +6384,20 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_64: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0x5400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x5800, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1 +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4 +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v5, v1 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x5800, vcc_lo ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 64.0, half 64.0> @@ -6582,15 +6423,14 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_4: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x5800 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x4400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 2, 7, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_4: @@ -6608,14 +6448,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_4: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x4400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x5800, vcc_lo +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 2, 7, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x5800, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_4: @@ -6633,14 +6474,16 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_4: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0x4400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x5800, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 2, 7, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 2, 7, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x5800, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 4.0, half 4.0> @@ -6666,15 +6509,20 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_2_4: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x4000 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x4400 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 2, v0 +; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 2, v1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xffff8000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7fff +; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v4, v5 +; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v4, v5 +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_2_4: @@ -6692,14 +6540,20 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_2_4: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x4400 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x4000, vcc_lo +; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4 +; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 2, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4 ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x4000, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_2_4: @@ -6717,14 +6571,20 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_2_4: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0x4400 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x4000, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1 +; GFX11-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4 +; GFX11-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v5, v1 ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x4000, vcc_lo ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 2.0, half 2.0>, <2 x half> <half 4.0, half 4.0> @@ -6750,15 +6610,14 @@ define <2 x half> @v_contract_mul_add_v2f16_select_4_128(<2 x i32> %arg, <2 x ha ; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_4_128: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x4400 -; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x5800 ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc ; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc -; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 7, 2, vcc +; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_4_128: @@ -6776,14 +6635,15 @@ define <2 x half> @v_contract_mul_add_v2f16_select_4_128(<2 x i32> %arg, <2 x ha ; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_4_128: ; GFX10-GISEL: ; %bb.0: ; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x5800 ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x4400, vcc_lo +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo ; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 7, 2, vcc_lo ; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x4400, vcc_lo +; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-LABEL: v_contract_mul_add_v2f16_select_4_128: @@ -6801,14 +6661,16 @@ define <2 x half> @v_contract_mul_add_v2f16_select_4_128(<2 x i32> %arg, <2 x ha ; GFX11-GISEL-LABEL: v_contract_mul_add_v2f16_select_4_128: ; GFX11-GISEL: ; %bb.0: ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, 0x5800 ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, v4, 0x4400, vcc_lo +; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 7, 2, vcc_lo ; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0 +; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 7, 2, vcc_lo ; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, 0x4400, vcc_lo +; GFX11-GISEL-NEXT: v_ldexp_f16_e32 v1, v4, v1 ; GFX11-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, v2, v0, v3 +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, v0, v3 ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %cond = icmp eq <2 x i32> %arg, zeroinitializer %select.pow2 = select <2 x i1> %cond, <2 x half> <half 4.0, half 4.0>, <2 x half> <half 128.0, half 128.0> diff --git a/llvm/test/CodeGen/AMDGPU/fract-match.ll b/llvm/test/CodeGen/AMDGPU/fract-match.ll index f6ee007facd7..80b4d64b1236 100644 --- a/llvm/test/CodeGen/AMDGPU/fract-match.ll +++ b/llvm/test/CodeGen/AMDGPU/fract-match.ll @@ -14,6 +14,7 @@ ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=kaveri < %s | FileCheck -check-prefixes=GCN,GFX7 %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s ; Test patterns to match v_fract_* instructions. @@ -103,6 +104,21 @@ define float @safe_math_fract_f32(float %x, ptr addrspace(1) nocapture writeonly ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo ; GFX11-NEXT: global_store_b32 v[1:2], v4, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v3, v0 +; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX12-NEXT: v_floor_f32_e32 v4, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo +; GFX12-NEXT: global_store_b32 v[1:2], v4, off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -181,6 +197,18 @@ define float @safe_math_fract_f32_noinf_check(float %x, ptr addrspace(1) nocaptu ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: global_store_b32 v[1:2], v3, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_f32_noinf_check: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v3, v0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: global_store_b32 v[1:2], v3, off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -263,6 +291,22 @@ define float @no_nan_check_math_fract_f32(float %x, ptr addrspace(1) nocapture w ; GFX11-NEXT: v_min_f32_e32 v4, 0x3f7fffff, v4 ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: no_nan_check_math_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v3, v0 +; GFX12-NEXT: v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v4, v0, v3 +; GFX12-NEXT: global_store_b32 v[1:2], v3, off +; GFX12-NEXT: v_min_num_f32_e32 v4, 0x3f7fffff, v4 +; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc_lo +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -314,6 +358,16 @@ define float @basic_fract_f32_nonans(float nofpclass(nan) %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_f32_nonans: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -362,6 +416,19 @@ define float @basic_fract_f32_flags_minnum(float %x) { ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_f32_flags_minnum: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v0, 0x3f7fffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -409,6 +476,16 @@ define float @basic_fract_f32_flags_fsub(float nofpclass(nan) %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_f32_flags_fsub: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub nsz float %x, %floor @@ -467,6 +544,17 @@ define <2 x float> @basic_fract_v2f32_nonans(<2 x float> nofpclass(nan) %x) { ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: v_fract_f32_e32 v1, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_v2f32_nonans: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: v_fract_f32_e32 v1, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call <2 x float> @llvm.floor.v2f32(<2 x float> %x) %sub = fsub <2 x float> %x, %floor @@ -540,6 +628,20 @@ define float @basic_fract_f32_multi_use_fsub_nonans(float nofpclass(nan) %x, ptr ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: global_store_b32 v[1:2], v3, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_f32_multi_use_fsub_nonans: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v3, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v3, v0, v3 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: global_store_b32 v[1:2], v3, off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -588,6 +690,16 @@ define float @nnan_minnum_fract_f32(float %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: nnan_minnum_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -638,6 +750,19 @@ define float @nnan_fsub_fract_f32(float %x) { ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: nnan_fsub_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v0, 0x3f7fffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub nnan float %x, %floor @@ -686,6 +811,19 @@ define float @nnan_floor_fract_f32(float %x) { ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: nnan_floor_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v0, 0x3f7fffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call nnan float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -733,6 +871,16 @@ define float @nnan_src_fract_f32(float nofpclass(nan) %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: nnan_src_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -782,6 +930,19 @@ define float @not_fract_f32_wrong_const(float nofpclass(nan) %x) { ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7ffffe, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: not_fract_f32_wrong_const: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v0, 0x3f7ffffe, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -831,6 +992,19 @@ define float @not_fract_f32_swapped_fsub(float nofpclass(nan) %x) { ; GFX11-NEXT: v_sub_f32_e32 v0, v1, v0 ; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: not_fract_f32_swapped_fsub: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v1, v0 +; GFX12-NEXT: v_min_num_f32_e32 v0, 0x3f7fffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %floor, %x @@ -880,6 +1054,19 @@ define float @not_fract_f32_not_floor(float nofpclass(nan) %x) { ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: not_fract_f32_not_floor: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_trunc_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v0, 0x3f7fffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.trunc.f32(float %x) %sub = fsub float %x, %floor @@ -929,6 +1116,19 @@ define float @not_fract_f32_different_floor(float %x, float %y) { ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_min_f32_e32 v0, 0x3f7fffff, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: not_fract_f32_different_floor: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v0, 0x3f7fffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %y) %sub = fsub float %x, %floor @@ -978,6 +1178,19 @@ define float @not_fract_f32_maxnum(float nofpclass(nan) %x) { ; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_max_f32_e32 v0, 0x3f7fffff, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: not_fract_f32_maxnum: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX12-NEXT: v_max_num_f32_e32 v0, 0x3f7fffff, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -1000,6 +1213,15 @@ define float @fcmp_uno_check_is_nan_f32(float %x) { ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: fcmp_uno_check_is_nan_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -1054,6 +1276,16 @@ define float @select_nan_fract_f32(float %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: select_nan_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -1107,6 +1339,16 @@ define float @commuted_select_nan_fract_f32(float %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: commuted_select_nan_fract_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -1168,6 +1410,22 @@ define float @wrong_commuted_nan_select_f32(float %x) { ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: wrong_commuted_nan_select_f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f32_e32 v1, v0 +; GFX12-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_sub_f32_e32 v1, v0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v1, 0x3f7fffff, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -1231,6 +1489,16 @@ define half @basic_fract_f16_nonan(half nofpclass(nan) %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f16_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_f16_nonan: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f16_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call half @llvm.floor.f16(half %x) %sub = fsub half %x, %floor @@ -1313,6 +1581,20 @@ define <2 x half> @basic_fract_v2f16_nonan(<2 x half> nofpclass(nan) %x) { ; GFX11-NEXT: v_fract_f16_e32 v1, v1 ; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_v2f16_nonan: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX12-NEXT: v_fract_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_fract_f16_e32 v1, v1 +; GFX12-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call <2 x half> @llvm.floor.v2f16(<2 x half> %x) %sub = fsub <2 x half> %x, %floor @@ -1369,6 +1651,16 @@ define double @basic_fract_f64_nanans(double nofpclass(nan) %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f64_e32 v[0:1], v[0:1] ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: basic_fract_f64_nanans: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f64_e32 v[0:1], v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call double @llvm.floor.f64(double %x) %sub = fsub double %x, %floor @@ -1461,6 +1753,18 @@ define half @safe_math_fract_f16_noinf_check(half %x, ptr addrspace(1) nocapture ; GFX11-NEXT: v_fract_f16_e32 v0, v0 ; GFX11-NEXT: global_store_b16 v[1:2], v3, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_f16_noinf_check: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f16_e32 v3, v0 +; GFX12-NEXT: v_fract_f16_e32 v0, v0 +; GFX12-NEXT: global_store_b16 v[1:2], v3, off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call half @llvm.floor.f16(half %x) %sub = fsub half %x, %floor @@ -1546,6 +1850,18 @@ define double @safe_math_fract_f64_noinf_check(double %x, ptr addrspace(1) nocap ; GFX11-NEXT: v_fract_f64_e32 v[0:1], v[0:1] ; GFX11-NEXT: global_store_b64 v[2:3], v[4:5], off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_f64_noinf_check: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_floor_f64_e32 v[4:5], v[0:1] +; GFX12-NEXT: v_fract_f64_e32 v[0:1], v[0:1] +; GFX12-NEXT: global_store_b64 v[2:3], v[4:5], off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call double @llvm.floor.f64(double %x) %sub = fsub double %x, %floor @@ -1600,6 +1916,16 @@ define float @select_nan_fract_f32_flags_select(float %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: select_nan_fract_f32_flags_select: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -1653,6 +1979,16 @@ define float @select_nan_fract_f32_flags_minnum(float %x) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_fract_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: select_nan_fract_f32_flags_minnum: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call float @llvm.floor.f32(float %x) %sub = fsub float %x, %floor @@ -1769,6 +2105,25 @@ define <2 x float> @safe_math_fract_v2f32(<2 x float> %x, ptr addrspace(1) nocap ; GFX11-NEXT: global_store_b64 v[2:3], v[4:5], off ; GFX11-NEXT: v_cndmask_b32_e64 v1, v7, 0, s0 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_v2f32: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f32_e32 v6, v0 +; GFX12-NEXT: v_cmp_class_f32_e64 s0, v0, 0x204 +; GFX12-NEXT: v_fract_f32_e32 v7, v1 +; GFX12-NEXT: v_floor_f32_e32 v4, v0 +; GFX12-NEXT: v_floor_f32_e32 v5, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0 +; GFX12-NEXT: v_cmp_class_f32_e64 s0, v1, 0x204 +; GFX12-NEXT: global_store_b64 v[2:3], v[4:5], off +; GFX12-NEXT: v_cndmask_b32_e64 v1, v7, 0, s0 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call <2 x float> @llvm.floor.v2f32(<2 x float> %x) %sub = fsub <2 x float> %x, %floor @@ -1881,6 +2236,21 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) nocapture writeon ; GFX11-NEXT: v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0, v5 ; GFX11-NEXT: global_store_b64 v[2:3], v[6:7], off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_f64: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f64_e32 v[4:5], v[0:1] +; GFX12-NEXT: v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]| +; GFX12-NEXT: v_floor_f64_e32 v[6:7], v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-NEXT: v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0, v5 +; GFX12-NEXT: global_store_b64 v[2:3], v[6:7], off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call double @llvm.floor.f64(double %x) %sub = fsub double %x, %floor @@ -2002,6 +2372,21 @@ define half @safe_math_fract_f16(half %x, ptr addrspace(1) nocapture writeonly % ; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo ; GFX11-NEXT: global_store_b16 v[1:2], v4, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f16_e32 v3, v0 +; GFX12-NEXT: v_cmp_neq_f16_e64 vcc_lo, 0x7c00, |v0| +; GFX12-NEXT: v_floor_f16_e32 v4, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc_lo +; GFX12-NEXT: global_store_b16 v[1:2], v4, off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call half @llvm.floor.f16(half %x) %sub = fsub half %x, %floor @@ -2168,6 +2553,29 @@ define <2 x half> @safe_math_fract_v2f16(<2 x half> %x, ptr addrspace(1) nocaptu ; GFX11-NEXT: global_store_b32 v[1:2], v4, off ; GFX11-NEXT: v_pack_b32_f16 v0, v0, v3 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_v2f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GFX12-NEXT: v_fract_f16_e32 v6, v0 +; GFX12-NEXT: v_floor_f16_e32 v5, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_fract_f16_e32 v4, v3 +; GFX12-NEXT: v_cmp_class_f16_e64 s0, v3, 0x204 +; GFX12-NEXT: v_floor_f16_e32 v7, v3 +; GFX12-NEXT: v_cndmask_b32_e64 v3, v4, 0, s0 +; GFX12-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_pack_b32_f16 v4, v5, v7 +; GFX12-NEXT: v_cndmask_b32_e64 v0, v6, 0, s0 +; GFX12-NEXT: global_store_b32 v[1:2], v4, off +; GFX12-NEXT: v_pack_b32_f16 v0, v0, v3 +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call <2 x half> @llvm.floor.v2f16(<2 x half> %x) %sub = fsub <2 x half> %x, %floor @@ -2311,6 +2719,26 @@ define <2 x double> @safe_math_fract_v2f64(<2 x double> %x, ptr addrspace(1) noc ; GFX11-NEXT: v_cndmask_b32_e64 v3, v13, 0, s1 ; GFX11-NEXT: global_store_b128 v[4:5], v[6:9], off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: safe_math_fract_v2f64: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fract_f64_e32 v[10:11], v[0:1] +; GFX12-NEXT: v_cmp_class_f64_e64 s0, v[0:1], 0x204 +; GFX12-NEXT: v_fract_f64_e32 v[12:13], v[2:3] +; GFX12-NEXT: v_cmp_class_f64_e64 s1, v[2:3], 0x204 +; GFX12-NEXT: v_floor_f64_e32 v[8:9], v[2:3] +; GFX12-NEXT: v_floor_f64_e32 v[6:7], v[0:1] +; GFX12-NEXT: v_cndmask_b32_e64 v0, v10, 0, s0 +; GFX12-NEXT: v_cndmask_b32_e64 v1, v11, 0, s0 +; GFX12-NEXT: v_cndmask_b32_e64 v2, v12, 0, s1 +; GFX12-NEXT: v_cndmask_b32_e64 v3, v13, 0, s1 +; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off +; GFX12-NEXT: s_setpc_b64 s[30:31] entry: %floor = tail call <2 x double> @llvm.floor.v2f64(<2 x double> %x) %sub = fsub <2 x double> %x, %floor diff --git a/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll b/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll index b3001819e9aa..c1d5b5857b6b 100644 --- a/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll @@ -2380,14 +2380,12 @@ define float @v_sqrt_f32_ulp2_contractable_rcp(float %x) { ; GISEL-IEEE: ; %bb.0: ; GISEL-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x800000 -; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x4b800000 ; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, 0, 24, vcc +; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GISEL-IEEE-NEXT: v_rsq_f32_e32 v0, v0 -; GISEL-IEEE-NEXT: v_mov_b32_e32 v1, 0x45800000 -; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v1, 0, 12, vcc +; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; GISEL-IEEE-NEXT: s_setpc_b64 s[30:31] ; ; GCN-DAZ-LABEL: v_sqrt_f32_ulp2_contractable_rcp: @@ -2734,20 +2732,18 @@ define <2 x float> @v_sqrt_v2f32_ulp2_contractable_rcp(<2 x float> %x) { ; GISEL-IEEE: ; %bb.0: ; GISEL-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-IEEE-NEXT: v_mov_b32_e32 v2, 0x800000 -; GISEL-IEEE-NEXT: v_mov_b32_e32 v3, 0x4b800000 ; GISEL-IEEE-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 -; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v3, 0, 24, vcc ; GISEL-IEEE-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2 -; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, v0, v4 -; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[4:5] +; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v3 +; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 24, s[4:5] ; GISEL-IEEE-NEXT: v_rsq_f32_e32 v0, v0 -; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, v1, v2 +; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; GISEL-IEEE-NEXT: v_rsq_f32_e32 v1, v1 -; GISEL-IEEE-NEXT: v_mov_b32_e32 v4, 0x45800000 -; GISEL-IEEE-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc -; GISEL-IEEE-NEXT: v_mul_f32_e32 v0, v0, v2 -; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 1.0, v4, s[4:5] -; GISEL-IEEE-NEXT: v_mul_f32_e32 v1, v1, v2 +; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 12, vcc +; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v0, v0, v2 +; GISEL-IEEE-NEXT: v_cndmask_b32_e64 v2, 0, 12, s[4:5] +; GISEL-IEEE-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; GISEL-IEEE-NEXT: s_setpc_b64 s[30:31] ; ; GCN-DAZ-LABEL: v_sqrt_v2f32_ulp2_contractable_rcp: diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir index cefd24032871..85c657789339 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir +++ b/llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir @@ -18,7 +18,7 @@ body: | ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec %0 = IMPLICIT_DEF %1 = COPY %0.sub1 %2 = COPY %0.sub0 @@ -43,7 +43,7 @@ body: | ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, [[COPY1]], 0, killed [[V_MOV_B32_e32_]], 0, killed [[COPY]], 0, 0, 0, implicit $mode, implicit $exec %0 = IMPLICIT_DEF %1 = COPY %0.sub1 %2 = COPY %0.sub0 @@ -68,7 +68,7 @@ body: | ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1 ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, killed [[COPY]], 0, [[COPY1]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec %0 = IMPLICIT_DEF %1 = COPY %0.sub0 %2 = COPY %0.sub1 @@ -90,7 +90,7 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec - ; GFX11-NEXT: [[V_FMA_F16_gfx9_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: [[V_FMA_F16_gfx9_fake16_e64_:%[0-9]+]]:vgpr_32 = V_FMA_F16_gfx9_fake16_e64 0, 16384, 0, killed [[COPY]], 0, [[V_MOV_B32_e32_]], 0, 0, 0, implicit $mode, implicit $exec ; GFX11-NEXT: S_ENDPGM 0 %0:vgpr_32 = COPY killed $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll index 157f91ccc6b1..b2f113f08a91 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll @@ -668,37 +668,32 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0xFFFFFFFF(ptr addrspace(1) define amdgpu_ps float @global_load_saddr_i8_offset_0x100000000(ptr addrspace(1) inreg %sbase) { ; GFX9-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-NEXT: s_add_i32 s3, s3, 1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1] -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_add_i32 s3, s3, 1 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s[0:1] -; GFX11-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_add_i32 s3, s3, 1 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX12-SDAG-NEXT: s_mov_b32 s1, 1 -; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] -; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 +; GFX12-SDAG-NEXT: s_add_co_i32 s3, s3, 1 +; GFX12-SDAG-NEXT: s_load_u8 s0, s[2:3], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-SDAG-NEXT: ; return to shader part epilog @@ -934,37 +929,32 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg0xFFFFFFFF(ptr addrspace( define amdgpu_ps float @global_load_saddr_i8_offset_neg0x100000000(ptr addrspace(1) inreg %sbase) { ; GFX9-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-NEXT: s_add_i32 s3, s3, -1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_add_i32 s3, s3, -1 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s[0:1] -; GFX11-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_add_i32 s3, s3, -1 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 -; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] -; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 +; GFX12-SDAG-NEXT: s_add_co_i32 s3, s3, -1 +; GFX12-SDAG-NEXT: s_load_u8 s0, s[2:3], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-SDAG-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir b/llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir new file mode 100644 index 000000000000..503f27edf70d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir @@ -0,0 +1,204 @@ +# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -simplify-mir -start-before=greedy,2 -stress-regalloc=4 -stop-before=virtregrewriter,2 -o - -verify-regalloc %s 2> %t.err | FileCheck %s +# RUN: FileCheck -check-prefix=ERR %s < %t.err + +# To allocate the vreg_512_align2, the allocation will attempt to +# inflate the register class to av_512_align2. This will ultimately +# not work, and the allocation will fail. There is an unproductive +# live range split, and we end up with a snippet copy of an +# unspillable register. Recursive assignment of interfering ranges +# during last chance recoloring would delete the unspillable snippet +# live range. Make sure there's no use after free when rolling back +# the last chance assignment. + +# ERR: error: <unknown>:0:0: ran out of registers during register allocation in function 'inflated_reg_class_copy_use_after_free' +# ERR: error: <unknown>:0:0: ran out of registers during register allocation in function 'inflated_reg_class_copy_use_after_free_lane_subset' + +--- | + define amdgpu_kernel void @inflated_reg_class_copy_use_after_free() { + ret void + } + + define amdgpu_kernel void @inflated_reg_class_copy_use_after_free_lane_subset() { + ret void + } + +... + +# CHECK-LABEL: name: inflated_reg_class_copy_use_after_free +# CHECK: S_NOP 0, implicit-def [[ORIG_REG:%[0-9]+]].sub0_sub1_sub2_sub3 +# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5) +# CHECK-NEXT: [[RESTORE0:%[0-9]+]]:vreg_512_align2 = SI_SPILL_V512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5) +# CHECK-NEXT: early-clobber [[MFMA0:%[0-9]+]]:vreg_512_align2 = V_MFMA_F32_16X16X1F32_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, [[RESTORE0]], 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit $exec +# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[MFMA0]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY [[MFMA0]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: undef [[SPLIT1:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT0]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT1]].sub0:av_512_align2 = COPY [[SPLIT0]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: undef [[SPLIT2:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT1]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT2]].sub0:av_512_align2 = COPY [[SPLIT1]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: SI_SPILL_AV512_SAVE [[SPLIT2]], %stack.1, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.1, align 4, addrspace 5) +# CHECK-NEXT: [[RESTORE1:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5) +# CHECK-NEXT: undef [[SPLIT3:%[0-9]+]].sub0_sub1:av_512_align2 = COPY [[RESTORE1]].sub0_sub1 +# CHECK-NEXT: [[RESTORE2:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.1, align 4, addrspace 5) +# CHECK-NEXT: undef [[SPLIT3:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[RESTORE2]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT3]].sub0:av_512_align2 = COPY [[RESTORE2]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: undef [[SPLIT4:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT3]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT4]].sub0:av_512_align2 = COPY [[SPLIT3]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: [[SPLIT5:%[0-9]+]].sub2:av_512_align2 = COPY [[SPLIT4]].sub3 +# CHECK-NEXT: undef [[SPLIT6:%[0-9]+]].sub0_sub1_sub2:av_512_align2 = COPY [[SPLIT5]].sub0_sub1_sub2 +# CHECK-NEXT: undef [[SPLIT7:%[0-9]+]].sub0_sub1_sub2:av_512_align2 = COPY [[SPLIT6]].sub0_sub1_sub2 +# CHECK-NEXT: undef [[SPLIT8:%[0-9]+]].sub0:av_512_align2 = COPY [[SPLIT4]].sub0 { +# CHECK-NEXT: internal [[SPLIT8]].sub2:av_512_align2 = COPY [[SPLIT4]].sub2 +# CHECK-NEXT: } +# CHECK-NEXT: [[SPLIT9:%[0-9]+]].sub3:av_512_align2 = COPY [[SPLIT8]].sub2 +# CHECK-NEXT: undef [[SPLIT10:%[0-9]+]].sub0_sub1_sub2_sub3:av_512_align2 = COPY [[SPLIT9]].sub0_sub1_sub2_sub3 +# CHECK-NEXT: undef [[SPLIT13:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_512_align2 = COPY [[SPLIT10]].sub0_sub1_sub2_sub3 +# CHECK-NEXT: [[MFMA_USE1:%[0-9]+]].sub4:vreg_512_align2 = COPY [[SPLIT8]].sub0 +# CHECK-NEXT: [[MFMA_USE1]].sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]].sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[MFMA_USE1]]:vreg_512_align2 = V_MFMA_F32_16X16X1F32_mac_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, [[MFMA_USE1]], 0, 0, 0, implicit $mode, implicit $exec + +--- +name: inflated_reg_class_copy_use_after_free +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true + scratchRSrcReg: '$sgpr72_sgpr73_sgpr74_sgpr75' + stackPtrOffsetReg: '$sgpr32' + occupancy: 7 + vgprForAGPRCopy: '$vgpr255' + sgprForEXECCopy: '$sgpr74_sgpr75' +body: | + bb.0: + liveins: $vgpr0, $sgpr4_sgpr5 + + %0:vgpr_32 = IMPLICIT_DEF + renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed undef renamable $sgpr4_sgpr5, 0, 0 :: (load (s64), addrspace 4) + S_NOP 0, implicit-def undef %1.sub12_sub13_sub14_sub15:vreg_512_align2 + S_NOP 0, implicit-def %1.sub8_sub9_sub10_sub11:vreg_512_align2 + S_NOP 0, implicit-def %1.sub4_sub5_sub6_sub7:vreg_512_align2 + S_NOP 0, implicit-def %1.sub0_sub1_sub2_sub3:vreg_512_align2 + early-clobber %2:vreg_512_align2 = V_MFMA_F32_16X16X1F32_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, %1, 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit $exec + %1.sub2:vreg_512_align2 = COPY %2.sub3 + %1.sub3:vreg_512_align2 = COPY %2.sub2 + %1.sub4:vreg_512_align2 = COPY %2.sub0 + %1.sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1:vreg_512_align2 = V_MFMA_F32_16X16X1F32_mac_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, %1, 0, 0, 0, implicit $mode, implicit $exec + GLOBAL_STORE_DWORDX4_SADDR undef %3:vgpr_32, %1.sub12_sub13_sub14_sub15, undef renamable $sgpr0_sgpr1, 96, 0, implicit $exec :: (store (s128), addrspace 1) + S_ENDPGM 0 + +... + +# This test is similar to except it is still broken when the use +# instruction does not read the full set of lanes after one attempted fix. + +# CHECK-LABEL: name: inflated_reg_class_copy_use_after_free_lane_subset +# CHECK: S_NOP 0, implicit-def [[ORIG_REG:%[0-9]+]].sub0_sub1_sub2_sub3 +# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5) +# CHECK-NEXT: [[RESTORE_0:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5) +# CHECK-NEXT: S_NOP 0, implicit-def early-clobber [[REG1:%[0-9]+]], implicit [[RESTORE_0]].sub0_sub1_sub2_sub3, implicit [[RESTORE_0]].sub4_sub5_sub6_sub7 +# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[REG1]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY [[REG1]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: undef [[SPLIT1:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT0]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT1]].sub0:av_512_align2 = COPY [[SPLIT0]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: undef [[SPLIT2:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT1]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT2]].sub0:av_512_align2 = COPY [[SPLIT1]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: SI_SPILL_AV512_SAVE [[SPLIT2]], %stack.1, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.1, align 4, addrspace 5) +# CHECK-NEXT: [[RESTORE_1:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5) +# CHECK-NEXT: undef [[SPLIT3:%[0-9]+]].sub0_sub1:av_512_align2 = COPY [[RESTORE_1]].sub0_sub1 +# CHECK-NEXT: [[RESTORE_2:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.1, align 4, addrspace 5) +# CHECK-NEXT: undef [[SPLIT4:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[RESTORE_2]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT4]].sub0:av_512_align2 = COPY [[RESTORE_2]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: undef [[SPLIT5:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT4]].sub2_sub3 { +# CHECK-NEXT: internal [[SPLIT5]].sub0:av_512_align2 = COPY [[SPLIT4]].sub0 +# CHECK-NEXT: } +# CHECK-NEXT: [[SPLIT3]].sub2:av_512_align2 = COPY [[SPLIT5]].sub3 +# CHECK-NEXT: undef [[SPLIT6:%[0-9]+]].sub0_sub1_sub2:av_512_align2 = COPY [[SPLIT3]].sub0_sub1_sub2 +# CHECK-NEXT: undef [[SPLIT7:%[0-9]+]].sub0_sub1_sub2:av_512_align2 = COPY [[SPLIT6]].sub0_sub1_sub2 +# CHECK-NEXT: undef [[SPLIT8:%[0-9]+]].sub0:av_512_align2 = COPY [[SPLIT5]].sub0 { +# CHECK-NEXT: internal [[SPLIT8]].sub2:av_512_align2 = COPY [[SPLIT5]].sub2 +# CHECK-NEXT: } +# CHECK-NEXT: [[SPLIT7]].sub3:av_512_align2 = COPY [[SPLIT8]].sub2 +# CHECK-NEXT: undef [[SPLIT9:%[0-9]+]].sub0_sub1_sub2_sub3:av_512_align2 = COPY [[SPLIT7]].sub0_sub1_sub2_sub3 +# CHECK-NEXT: undef [[LAST_USE:%[0-9]+]].sub0_sub1_sub2_sub3:vreg_512_align2 = COPY [[SPLIT9]].sub0_sub1_sub2_sub3 +# CHECK-NEXT: [[LAST_USE]].sub4:vreg_512_align2 = COPY [[SPLIT8]].sub0 +# CHECK-NEXT: [[LAST_USE]].sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: [[LAST_USE]].sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec +# CHECK-NEXT: S_NOP 0, implicit-def [[LAST_USE]], implicit [[LAST_USE]].sub0_sub1_sub2_sub3, implicit [[LAST_USE]].sub4_sub5_sub6_sub7, implicit [[LAST_USE]].sub8_sub9_sub10_sub11 + +--- +name: inflated_reg_class_copy_use_after_free_lane_subset +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true + scratchRSrcReg: '$sgpr72_sgpr73_sgpr74_sgpr75' + stackPtrOffsetReg: '$sgpr32' + occupancy: 7 + vgprForAGPRCopy: '$vgpr255' + sgprForEXECCopy: '$sgpr74_sgpr75' +body: | + bb.0: + liveins: $vgpr0, $sgpr4_sgpr5 + + %0:vgpr_32 = IMPLICIT_DEF + renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed undef renamable $sgpr4_sgpr5, 0, 0 :: (load (s64), addrspace 4) + S_NOP 0, implicit-def undef %1.sub12_sub13_sub14_sub15:vreg_512_align2 + S_NOP 0, implicit-def %1.sub8_sub9_sub10_sub11:vreg_512_align2 + S_NOP 0, implicit-def %1.sub4_sub5_sub6_sub7:vreg_512_align2 + S_NOP 0, implicit-def %1.sub0_sub1_sub2_sub3:vreg_512_align2 + S_NOP 0, implicit-def early-clobber %2:vreg_512_align2, implicit %1.sub0_sub1_sub2_sub3, implicit %1.sub4_sub5_sub6_sub7 + %1.sub2:vreg_512_align2 = COPY %2.sub3 + %1.sub3:vreg_512_align2 = COPY %2.sub2 + %1.sub4:vreg_512_align2 = COPY %2.sub0 + %1.sub5:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub6:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub7:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub8:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub9:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub10:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub11:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub12:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub13:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub14:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + %1.sub15:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec + S_NOP 0, implicit-def %1:vreg_512_align2, implicit %1.sub0_sub1_sub2_sub3, implicit %1.sub4_sub5_sub6_sub7, implicit %1.sub8_sub9_sub10_sub11 + GLOBAL_STORE_DWORDX4_SADDR undef %3:vgpr_32, %1.sub12_sub13_sub14_sub15, undef renamable $sgpr0_sgpr1, 96, 0, implicit $exec :: (store (s128), addrspace 1) + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll index cf9fdbdc3439..2ceaca3497ec 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll @@ -8,16 +8,16 @@ define amdgpu_kernel void @s_input_output_i128() { ; GFX908-LABEL: name: s_input_output_i128 ; GFX908: bb.0 (%ir-block.0): - ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:SGPR_128 */, def %12 + ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7471114 /* regdef:SGPR_128 */, def %12 ; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %12 - ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7405577 /* reguse:SGPR_128 */, [[COPY]] + ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7471113 /* reguse:SGPR_128 */, [[COPY]] ; GFX908-NEXT: S_ENDPGM 0 ; ; GFX90A-LABEL: name: s_input_output_i128 ; GFX90A: bb.0 (%ir-block.0): - ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:SGPR_128 */, def %10 + ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7471114 /* regdef:SGPR_128 */, def %10 ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %10 - ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7405577 /* reguse:SGPR_128 */, [[COPY]] + ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7471113 /* reguse:SGPR_128 */, [[COPY]] ; GFX90A-NEXT: S_ENDPGM 0 %val = tail call i128 asm sideeffect "; def $0", "=s"() call void asm sideeffect "; use $0", "s"(i128 %val) diff --git a/llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll b/llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll new file mode 100644 index 000000000000..1a87887e28d7 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/issue121601-combine-concat-vectors-assumes-f16.ll @@ -0,0 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s + +define <4 x float> @issue121601(bfloat %fptrunc) { +; CHECK-LABEL: issue121601: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; CHECK-NEXT: v_mov_b32_e32 v1, v0 +; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, 0 +; CHECK-NEXT: s_setpc_b64 s[30:31] +bb: + %bitcast = bitcast bfloat %fptrunc to <1 x bfloat> + %shufflevector = shufflevector <1 x bfloat> %bitcast, <1 x bfloat> zeroinitializer, <2 x i32> zeroinitializer + %fpext = fpext <2 x bfloat> %shufflevector to <2 x float> + %shufflevector1 = shufflevector <2 x float> %fpext, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x float> %shufflevector1 +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll index 3ff759a5cdb9..867025adca94 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll @@ -4,6 +4,7 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX12 %s define amdgpu_kernel void @cos_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) { ; GFX6-LABEL: cos_f16: @@ -80,6 +81,19 @@ define amdgpu_kernel void @cos_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) { ; GFX11-NEXT: v_cos_f16_e32 v1, v1 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: cos_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_cos_f16_e32 v1, v1 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX12-NEXT: s_endpgm %a.val = load half, ptr addrspace(1) %a %r.val = call half @llvm.cos.f16(half %a.val) store half %r.val, ptr addrspace(1) %r @@ -188,6 +202,24 @@ define amdgpu_kernel void @cos_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) { ; GFX11-NEXT: v_pack_b32_f16 v1, v1, v2 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: cos_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_mul_f16_e32 v2, 0.15915494, v2 +; GFX12-NEXT: v_cos_f16_e32 v1, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) +; GFX12-NEXT: v_cos_f16_e32 v2, v2 +; GFX12-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_endpgm %a.val = load <2 x half>, ptr addrspace(1) %a %r.val = call <2 x half> @llvm.cos.v2f16(<2 x half> %a.val) store <2 x half> %r.val, ptr addrspace(1) %r diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll index ac515808a0d8..333d428c84bc 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll @@ -41,10 +41,10 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) { ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; SI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-GISEL-NEXT: s_mov_b32 s2, -1 -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-GISEL-NEXT: s_endpgm ; @@ -78,9 +78,9 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) { ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; VI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v2, v0, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 ; VI-GISEL-NEXT: flat_store_dword v[0:1], v2 @@ -115,9 +115,9 @@ define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) { ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s0, v0 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] @@ -203,7 +203,7 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000 +; SI-GISEL-NEXT: v_not_b32_e32 v2, 63 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 @@ -213,10 +213,10 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; SI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0 ; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0 -; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v3, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 @@ -252,7 +252,7 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000 +; VI-GISEL-NEXT: v_not_b32_e32 v2, 63 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 @@ -262,10 +262,10 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; VI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0 ; VI-GISEL-NEXT: v_exp_f32_e32 v3, v3 ; VI-GISEL-NEXT: v_exp_f32_e32 v1, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0 -; VI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] +; VI-GISEL-NEXT: v_ldexp_f32 v0, v3, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5 ; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] @@ -300,7 +300,7 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000 +; GFX900-GISEL-NEXT: v_not_b32_e32 v2, 63 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0 @@ -310,10 +310,10 @@ define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s11, v0 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v3, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] ; GFX900-GISEL-NEXT: s_endpgm @@ -421,17 +421,17 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000 +; SI-GISEL-NEXT: v_not_b32_e32 v3, 63 ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc ; SI-GISEL-NEXT: v_add_f32_e32 v0, s0, v0 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v4 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc ; SI-GISEL-NEXT: v_add_f32_e32 v4, s1, v4 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1 @@ -439,11 +439,11 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; SI-GISEL-NEXT: v_exp_f32_e32 v4, v4 ; SI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v2, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v4, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 -; SI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v2, v3 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8 ; SI-GISEL-NEXT: s_endpgm @@ -487,16 +487,16 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000 +; VI-GISEL-NEXT: v_not_b32_e32 v3, 63 ; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc ; VI-GISEL-NEXT: v_add_f32_e32 v0, s0, v0 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v4 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc ; VI-GISEL-NEXT: v_add_f32_e32 v4, s1, v4 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1 @@ -504,10 +504,10 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; VI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1 ; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4 ; VI-GISEL-NEXT: v_exp_f32_e32 v2, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; VI-GISEL-NEXT: v_ldexp_f32 v1, v4, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v2, v2, v3 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 ; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2] @@ -551,15 +551,15 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000 +; GFX900-GISEL-NEXT: v_not_b32_e32 v3, 63 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s0, v0 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v4 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc ; GFX900-GISEL-NEXT: v_add_f32_e32 v4, s1, v4 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1 @@ -567,10 +567,10 @@ define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s2, v1 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v4, v4 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v4, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v2, v3 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7] ; GFX900-GISEL-NEXT: s_endpgm @@ -710,7 +710,7 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000 +; SI-GISEL-NEXT: v_not_b32_e32 v4, 63 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc @@ -720,22 +720,22 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v5 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1] ; SI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5 ; SI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2 ; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5 ; SI-GISEL-NEXT: v_exp_f32_e32 v3, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2 -; SI-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] +; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, v5, v2 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, v3, v4 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 @@ -787,7 +787,7 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000 +; VI-GISEL-NEXT: v_not_b32_e32 v4, 63 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc @@ -797,22 +797,22 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1 ; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1] +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v5 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5 +; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v5 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1] ; VI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5 ; VI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2 ; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5 ; VI-GISEL-NEXT: v_exp_f32_e32 v3, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] +; VI-GISEL-NEXT: v_ldexp_f32 v2, v5, v2 +; VI-GISEL-NEXT: v_ldexp_f32 v3, v3, v4 ; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2 ; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3] @@ -863,7 +863,7 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000 +; GFX900-GISEL-NEXT: v_not_b32_e32 v4, 63 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc @@ -873,22 +873,22 @@ define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s9, v1 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1] +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v5 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1] ; GFX900-GISEL-NEXT: v_add_f32_e32 v5, s10, v5 ; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s11, v2 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] +; GFX900-GISEL-NEXT: v_ldexp_f32 v2, v5, v2 +; GFX900-GISEL-NEXT: v_ldexp_f32 v3, v3, v4 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm @@ -1006,19 +1006,19 @@ define float @v_exp2_f32(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32: ; VI-SDAG: ; %bb.0: @@ -1034,6 +1034,20 @@ define float @v_exp2_f32(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1048,6 +1062,20 @@ define float @v_exp2_f32(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1076,19 +1104,19 @@ define float @v_exp2_fabs_f32(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_fabs_f32: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_fabs_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_fabs_f32: ; VI-SDAG: ; %bb.0: @@ -1104,6 +1132,20 @@ define float @v_exp2_fabs_f32(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_fabs_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_fabs_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1118,6 +1160,20 @@ define float @v_exp2_fabs_f32(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_fabs_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_fabs_f32: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1147,19 +1203,19 @@ define float @v_exp2_fneg_fabs_f32(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_fneg_fabs_f32: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_sub_f32_e64 v0, v1, |v0| -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_fneg_fabs_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_sub_f32_e64 v0, v1, |v0| +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_fneg_fabs_f32: ; VI-SDAG: ; %bb.0: @@ -1175,6 +1231,20 @@ define float @v_exp2_fneg_fabs_f32(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_fneg_fabs_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_sub_f32_e64 v0, v1, |v0| +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_fneg_fabs_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1189,6 +1259,20 @@ define float @v_exp2_fneg_fabs_f32(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_fneg_fabs_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e64 v0, v1, |v0| +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_fneg_fabs_f32: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1219,19 +1303,19 @@ define float @v_exp2_fneg_f32(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_fneg_f32: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_fneg_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_fneg_f32: ; VI-SDAG: ; %bb.0: @@ -1247,6 +1331,20 @@ define float @v_exp2_fneg_f32(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_fneg_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_fneg_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1261,6 +1359,20 @@ define float @v_exp2_fneg_f32(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_fneg_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_fneg_f32: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1290,19 +1402,19 @@ define float @v_exp2_f32_fast(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_fast: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_fast: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_fast: ; VI-SDAG: ; %bb.0: @@ -1318,6 +1430,20 @@ define float @v_exp2_f32_fast(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_fast: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_fast: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1332,6 +1458,20 @@ define float @v_exp2_f32_fast(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_fast: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_fast: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1360,19 +1500,19 @@ define float @v_exp2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_unsafe_math_attr: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_unsafe_math_attr: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_unsafe_math_attr: ; VI-SDAG: ; %bb.0: @@ -1388,6 +1528,20 @@ define float @v_exp2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_unsafe_math_attr: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_unsafe_math_attr: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1402,6 +1556,20 @@ define float @v_exp2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_unsafe_math_attr: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_unsafe_math_attr: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1430,19 +1598,19 @@ define float @v_exp2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_approx_fn_attr: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_approx_fn_attr: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_approx_fn_attr: ; VI-SDAG: ; %bb.0: @@ -1458,6 +1626,20 @@ define float @v_exp2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_approx_fn_attr: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_approx_fn_attr: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1472,6 +1654,20 @@ define float @v_exp2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_approx_fn_attr: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_approx_fn_attr: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1500,19 +1696,19 @@ define float @v_exp2_f32_ninf(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_ninf: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_ninf: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_ninf: ; VI-SDAG: ; %bb.0: @@ -1528,6 +1724,20 @@ define float @v_exp2_f32_ninf(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_ninf: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_ninf: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1542,6 +1752,20 @@ define float @v_exp2_f32_ninf(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_ninf: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_ninf: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1570,19 +1794,19 @@ define float @v_exp2_f32_afn(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_afn: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_afn: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_afn: ; VI-SDAG: ; %bb.0: @@ -1598,6 +1822,20 @@ define float @v_exp2_f32_afn(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_afn: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_afn: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1612,6 +1850,20 @@ define float @v_exp2_f32_afn(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_afn: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_afn: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1660,19 +1912,19 @@ define float @v_exp2_f32_afn_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_afn_dynamic: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_afn_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_afn_dynamic: ; VI-SDAG: ; %bb.0: @@ -1688,6 +1940,20 @@ define float @v_exp2_f32_afn_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_afn_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_afn_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1702,6 +1968,20 @@ define float @v_exp2_f32_afn_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_afn_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_afn_dynamic: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1730,19 +2010,19 @@ define float @v_fabs_exp2_f32_afn(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_fabs_exp2_f32_afn: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_fabs_exp2_f32_afn: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_fabs_exp2_f32_afn: ; VI-SDAG: ; %bb.0: @@ -1758,6 +2038,20 @@ define float @v_fabs_exp2_f32_afn(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_fabs_exp2_f32_afn: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_fabs_exp2_f32_afn: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1772,6 +2066,20 @@ define float @v_fabs_exp2_f32_afn(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_fabs_exp2_f32_afn: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_fabs_exp2_f32_afn: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1821,19 +2129,19 @@ define float @v_exp2_f32_nnan(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_nnan: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_nnan: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_nnan: ; VI-SDAG: ; %bb.0: @@ -1849,6 +2157,20 @@ define float @v_exp2_f32_nnan(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_nnan: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_nnan: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1863,6 +2185,20 @@ define float @v_exp2_f32_nnan(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_nnan: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_nnan: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -1911,19 +2247,19 @@ define float @v_exp2_f32_nnan_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_nnan_dynamic: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_nnan_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_nnan_dynamic: ; VI-SDAG: ; %bb.0: @@ -1939,6 +2275,20 @@ define float @v_exp2_f32_nnan_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_nnan_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_nnan_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1953,6 +2303,20 @@ define float @v_exp2_f32_nnan_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_nnan_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_nnan_dynamic: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -2001,19 +2365,19 @@ define float @v_exp2_f32_ninf_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_ninf_dynamic: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_ninf_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_ninf_dynamic: ; VI-SDAG: ; %bb.0: @@ -2029,6 +2393,20 @@ define float @v_exp2_f32_ninf_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_ninf_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_ninf_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2043,6 +2421,20 @@ define float @v_exp2_f32_ninf_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_ninf_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_ninf_dynamic: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -2071,19 +2463,19 @@ define float @v_exp2_f32_nnan_ninf(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_nnan_ninf: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_nnan_ninf: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_nnan_ninf: ; VI-SDAG: ; %bb.0: @@ -2099,6 +2491,20 @@ define float @v_exp2_f32_nnan_ninf(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_nnan_ninf: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_nnan_ninf: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2113,6 +2519,20 @@ define float @v_exp2_f32_nnan_ninf(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_nnan_ninf: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_nnan_ninf: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -2161,19 +2581,19 @@ define float @v_exp2_f32_nnan_ninf_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_nnan_ninf_dynamic: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_nnan_ninf_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_nnan_ninf_dynamic: ; VI-SDAG: ; %bb.0: @@ -2189,6 +2609,20 @@ define float @v_exp2_f32_nnan_ninf_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_nnan_ninf_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_nnan_ninf_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2203,6 +2637,20 @@ define float @v_exp2_f32_nnan_ninf_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_nnan_ninf_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_nnan_ninf_dynamic: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -2251,19 +2699,19 @@ define float @v_exp2_f32_dynamic_mode(float %in) #1 { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_dynamic_mode: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_dynamic_mode: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_dynamic_mode: ; VI-SDAG: ; %bb.0: @@ -2279,6 +2727,20 @@ define float @v_exp2_f32_dynamic_mode(float %in) #1 { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_dynamic_mode: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_dynamic_mode: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2293,6 +2755,20 @@ define float @v_exp2_f32_dynamic_mode(float %in) #1 { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_dynamic_mode: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_dynamic_mode: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -2313,20 +2789,50 @@ define float @v_exp2_f32_undef() { ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, 0x7fc00000 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_undef: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000 -; GCN-GISEL-NEXT: v_add_f32_e32 v1, s4, v1 -; GCN-GISEL-NEXT: v_add_f32_e64 v2, s4, 0 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_undef: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000 +; SI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1 +; SI-GISEL-NEXT: v_add_f32_e64 v2, s4, 0 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; VI-GISEL-LABEL: v_exp2_f32_undef: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000 +; VI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1 +; VI-GISEL-NEXT: v_add_f32_e64 v2, s4, 0 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-GISEL-LABEL: v_exp2_f32_undef: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000 +; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s4, v1 +; GFX900-GISEL-NEXT: v_add_f32_e64 v2, s4, 0 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; R600-LABEL: v_exp2_f32_undef: ; R600: ; %bb.0: @@ -3359,19 +3865,19 @@ define float @v_exp2_f32_contract(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_contract: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_contract: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_contract: ; VI-SDAG: ; %bb.0: @@ -3387,6 +3893,20 @@ define float @v_exp2_f32_contract(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_contract: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_contract: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -3401,6 +3921,20 @@ define float @v_exp2_f32_contract(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_contract: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_contract: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -3449,19 +3983,19 @@ define float @v_exp2_f32_contract_nnan_ninf(float %in) { ; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GCN-GISEL-LABEL: v_exp2_f32_contract_nnan_ninf: -; GCN-GISEL: ; %bb.0: -; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 -; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 -; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0 -; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000 -; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc -; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_exp2_f32_contract_nnan_ninf: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_exp2_f32_contract_nnan_ninf: ; VI-SDAG: ; %bb.0: @@ -3477,6 +4011,20 @@ define float @v_exp2_f32_contract_nnan_ninf(float %in) { ; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_exp2_f32_contract_nnan_ninf: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_not_b32_e32 v1, 63 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_exp2_f32_contract_nnan_ninf: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -3491,6 +4039,20 @@ define float @v_exp2_f32_contract_nnan_ninf(float %in) { ; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_exp2_f32_contract_nnan_ninf: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; R600-LABEL: v_exp2_f32_contract_nnan_ninf: ; R600: ; %bb.0: ; R600-NEXT: CF_END @@ -3518,3 +4080,5 @@ declare <3 x half> @llvm.exp2.v3f16(<3 x half>) #2 attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN-GISEL: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll index b9fef0834cb2..88ef7a936393 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll @@ -3,11 +3,13 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-SDAG %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-SDAG %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-GISEL %s define { half, i32 } @test_frexp_f16_i32(half %a) { ; GFX6-SDAG-LABEL: test_frexp_f16_i32: @@ -50,6 +52,19 @@ define { half, i32 } @test_frexp_f16_i32(half %a) { ; GFX11-NEXT: v_bfe_i32 v1, v1, 0, 16 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f16_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v1, v0 +; GFX12-NEXT: v_frexp_mant_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f16_i32: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -96,6 +111,16 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) { ; GFX11-NEXT: v_frexp_mant_f16_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f16_i32_only_use_fract: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f16_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f16_i32_only_use_fract: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -145,6 +170,18 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) { ; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f16_i32_only_use_exp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f16_i32_only_use_exp: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -221,6 +258,25 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) { ; GFX11-NEXT: v_bfe_i32 v2, v4, 0, 16 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_v2f16_v2i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX12-NEXT: v_frexp_mant_f16_e32 v2, v0 +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_frexp_mant_f16_e32 v3, v1 +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v4, v1 +; GFX12-NEXT: v_bfe_i32 v1, v0, 0, 16 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_pack_b32_f16 v0, v2, v3 +; GFX12-NEXT: v_bfe_i32 v2, v4, 0, 16 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_v2f16_v2i32: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -311,6 +367,20 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) { ; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_v2f16_v2i32_only_use_fract: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX12-NEXT: v_frexp_mant_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_frexp_mant_f16_e32 v1, v1 +; GFX12-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_v2f16_v2i32_only_use_fract: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -386,6 +456,22 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) { ; GFX11-NEXT: v_bfe_i32 v1, v1, 0, 16 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_v2f16_v2i32_only_use_exp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v1, v1 +; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_v2f16_v2i32_only_use_exp: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -463,6 +549,19 @@ define { half, i16 } @test_frexp_f16_i16(half %a) { ; GFX11-NEXT: v_mov_b32_e32 v0, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f16_i16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f16_e32 v2, v0 +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_mov_b32_e32 v0, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f16_i16: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -509,6 +608,16 @@ define half @test_frexp_f16_i16_only_use_fract(half %a) { ; GFX11-NEXT: v_frexp_mant_f16_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f16_i16_only_use_fract: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f16_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f16_i16_only_use_fract: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -554,6 +663,16 @@ define i16 @test_frexp_f16_i16_only_use_exp(half %a) { ; GFX11-NEXT: v_frexp_exp_i16_f16_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f16_i16_only_use_exp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_exp_i16_f16_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f16_i16_only_use_exp: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -623,6 +742,19 @@ define { float, i32 } @test_frexp_f32_i32(float %a) { ; GFX11-NEXT: v_mov_b32_e32 v0, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f32_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f32_e32 v2, v0 +; GFX12-NEXT: v_frexp_exp_i32_f32_e32 v1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_mov_b32_e32 v0, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f32_i32: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -665,6 +797,16 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) { ; GFX11-NEXT: v_frexp_mant_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f32_i32_only_use_fract: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f32_i32_only_use_fract: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -706,6 +848,16 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) { ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f32_i32_only_use_exp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f32_i32_only_use_exp: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -771,6 +923,21 @@ define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) { ; GFX11-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_v2f32_v2i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f32_e32 v4, v0 +; GFX12-NEXT: v_frexp_mant_f32_e32 v5, v1 +; GFX12-NEXT: v_frexp_exp_i32_f32_e32 v2, v0 +; GFX12-NEXT: v_frexp_exp_i32_f32_e32 v3, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v1, v5 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_v2f32_v2i32: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -846,6 +1013,17 @@ define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) { ; GFX11-NEXT: v_frexp_mant_f32_e32 v1, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_v2f32_v2i32_only_use_fract: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f32_e32 v0, v0 +; GFX12-NEXT: v_frexp_mant_f32_e32 v1, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_v2f32_v2i32_only_use_fract: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -896,6 +1074,17 @@ define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) { ; GFX11-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_v2f32_v2i32_only_use_exp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_exp_i32_f32_e32 v0, v0 +; GFX12-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_v2f32_v2i32_only_use_exp: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -954,6 +1143,19 @@ define { double, i32 } @test_frexp_f64_i32(double %a) { ; GFX11-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f64_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f64_e32 v[3:4], v[0:1] +; GFX12-NEXT: v_frexp_exp_i32_f64_e32 v2, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_dual_mov_b32 v0, v3 :: v_dual_mov_b32 v1, v4 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f64_i32: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1000,6 +1202,16 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) { ; GFX11-NEXT: v_frexp_mant_f64_e32 v[0:1], v[0:1] ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f64_i32_only_use_fract: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f64_e32 v[0:1], v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f64_i32_only_use_fract: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1044,6 +1256,16 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) { ; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1] ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_f64_i32_only_use_exp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_f64_i32_only_use_exp: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1116,6 +1338,22 @@ define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) { ; GFX11-NEXT: v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; +; GFX12-LABEL: test_frexp_v2f64_v2i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f64_e32 v[8:9], v[0:1] +; GFX12-NEXT: v_frexp_mant_f64_e32 v[6:7], v[2:3] +; GFX12-NEXT: v_frexp_exp_i32_f64_e32 v4, v[0:1] +; GFX12-NEXT: v_frexp_exp_i32_f64_e32 v5, v[2:3] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 +; GFX12-NEXT: v_dual_mov_b32 v2, v6 :: v_dual_mov_b32 v3, v7 +; GFX12-NEXT: s_setpc_b64 s[30:31] +; ; GFX6-GISEL-LABEL: test_frexp_v2f64_v2i32: ; GFX6-GISEL: ; %bb.0: ; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1174,6 +1412,17 @@ define <2 x double> @test_frexp_v2f64_v2i32_only_use_fract(<2 x double> %a) { ; GFX11-NEXT: v_frexp_mant_f64_e32 v[0:1], v[0:1] ; GFX11-NEXT: v_frexp_mant_f64_e32 v[2:3], v[2:3] ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_frexp_v2f64_v2i32_only_use_fract: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_mant_f64_e32 v[0:1], v[0:1] +; GFX12-NEXT: v_frexp_mant_f64_e32 v[2:3], v[2:3] +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a) %result.0 = extractvalue { <2 x double>, <2 x i32> } %result, 0 ret <2 x double> %result.0 @@ -1213,6 +1462,17 @@ define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) { ; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1] ; GFX11-NEXT: v_frexp_exp_i32_f64_e32 v1, v[2:3] ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_frexp_v2f64_v2i32_only_use_exp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_frexp_exp_i32_f64_e32 v0, v[0:1] +; GFX12-NEXT: v_frexp_exp_i32_f64_e32 v1, v[2:3] +; GFX12-NEXT: s_setpc_b64 s[30:31] %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a) %result.1 = extractvalue { <2 x double>, <2 x i32> } %result, 1 ret <2 x i32> %result.1 @@ -1235,3 +1495,5 @@ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memo ; GCN: {{.*}} ; GFX11-GISEL: {{.*}} ; GFX11-SDAG: {{.*}} +; GFX12-GISEL: {{.*}} +; GFX12-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll index 218e41faa703..b850428a03c0 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll @@ -45,16 +45,17 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) { ; SI-GISEL-NEXT: s_load_dword s0, s[4:5], 0xb ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 +; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0 ; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4 ; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 @@ -64,7 +65,6 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) { ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-GISEL-NEXT: s_endpgm ; @@ -104,25 +104,25 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) { ; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c ; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 -; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3 +; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 -; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 -; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2 @@ -162,25 +162,25 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) { ; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0 -; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4 -; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 -; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v0 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v5 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 +; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x41b17218 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -218,24 +218,26 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 -; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_mov_b32 v1, 0 -; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log_f32: @@ -358,35 +360,36 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217 -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2 -; SI-GISEL-NEXT: v_log_f32_e32 v2, v2 -; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s6, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v1, v1 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 -; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v2 -; SI-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6 -; SI-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7 -; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] +; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1 +; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5 +; SI-GISEL-NEXT: v_fma_f32 v6, v1, v3, v6 +; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 -; SI-GISEL-NEXT: v_log_f32_e32 v1, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s7, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 -; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1 -; SI-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2 -; SI-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3 -; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v5 +; SI-GISEL-NEXT: v_fma_f32 v2, v5, v2, -v1 +; SI-GISEL-NEXT: v_fma_f32 v2, v5, v3, v2 +; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1] ; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 @@ -445,42 +448,43 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2 -; VI-GISEL-NEXT: v_log_f32_e32 v2, v2 -; VI-GISEL-NEXT: v_and_b32_e32 v4, 0xfffff000, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v5, v2, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s6, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v1, v1 +; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v1 +; VI-GISEL-NEXT: v_sub_f32_e32 v4, v1, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v5 -; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4 ; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3 ; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v3 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 -; VI-GISEL-NEXT: v_log_f32_e32 v1, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s7, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v0 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x41b17218 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 -; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v1 -; VI-GISEL-NEXT: v_sub_f32_e32 v5, v1, v2 +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v3 +; VI-GISEL-NEXT: v_sub_f32_e32 v5, v3, v1 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v5 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6 ; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5 ; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 -; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 +; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1] ; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4 @@ -531,37 +535,38 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf +; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s10, v2 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v2 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, -v6 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v4, v7 ; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s11, v0 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc -; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3 -; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1] -; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s11, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v7, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v6 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v3, -v1 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v4, v3 +; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[0:1] +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -608,31 +613,37 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s4 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s5 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s2, v0 :: v_dual_mul_f32 v1, s3, v1 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, 0x3f317217, v0 :: v_dual_mul_f32 v3, 0x3f317217, v1 +; GFX1100-GISEL-NEXT: v_dual_mul_f32 v3, 0x3f317217, v1 :: v_dual_lshlrev_b32 v0, 5, v0 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3f317217, v1, -v3 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v5, 0x3377d1cf, v1 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_dual_add_f32 v3, v3, v5 :: v_dual_mul_f32 v2, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s5 ; GFX1100-GISEL-NEXT: v_fma_f32 v4, 0x3f317217, v0, -v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3f317217, v1, -v3 -; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v4, 0x3377d1cf, v0 :: v_dual_fmac_f32 v5, 0x3377d1cf, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_add_f32 v3, v3, v5 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v4, 0x3377d1cf, v0 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s4 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s5 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1| -; GFX1100-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v3 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_mov_b32 v2, 0 ; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5 ; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm @@ -808,49 +819,51 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) { ; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf -; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 -; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v0 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7 -; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] +; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 +; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v0 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v2, -v5 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, v6 +; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 1.0, v2, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v6, s9, v6 -; SI-GISEL-NEXT: v_log_f32_e32 v6, v6 -; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, s9, v5 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v6 -; SI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1 -; SI-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8 -; SI-GISEL-NEXT: v_log_f32_e32 v2, v1 -; SI-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9 -; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3] -; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1] -; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6 -; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v2 -; SI-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6 -; SI-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3 -; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc -; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_fma_f32 v8, v5, v2, -v7 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_fma_f32 v8, v5, v3, v8 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1 +; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; SI-GISEL-NEXT: v_log_f32_e32 v8, v1 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v5|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v7, s[2:3] +; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 +; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v8 +; SI-GISEL-NEXT: v_fma_f32 v2, v8, v2, -v5 +; SI-GISEL-NEXT: v_fma_f32 v2, v8, v3, v2 +; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v8|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc ; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8 @@ -927,12 +940,13 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v3 @@ -943,45 +957,46 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) { ; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3 ; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 ; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v2, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v3, s9, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3 +; VI-GISEL-NEXT: v_ldexp_f32 v3, s9, v3 ; VI-GISEL-NEXT: v_log_f32_e32 v3, v3 -; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x41b17218 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v3 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x41b17218 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v3 +; VI-GISEL-NEXT: v_sub_f32_e32 v6, v3, v5 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 -; VI-GISEL-NEXT: v_sub_f32_e32 v7, v3, v6 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7 -; VI-GISEL-NEXT: v_log_f32_e32 v2, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v5 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v6, s[2:3] -; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[0:1] +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_log_f32_e32 v6, v1 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v5, s[2:3] +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[0:1] ; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 -; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v6, v2, v3 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6 +; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v6 +; VI-GISEL-NEXT: v_sub_f32_e32 v5, v6, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v5 ; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v3 ; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v6 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v6|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1] +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 @@ -1046,49 +1061,51 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) { ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf ; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v0 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v2, -v6 ; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7 ; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 1.0, v2, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s9, v6 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6 +; GFX900-GISEL-NEXT: v_ldexp_f32 v6, s9, v6 ; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc ; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v6 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1 -; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v2, -v8 +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 ; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1 ; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 +; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v1 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3] ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1] ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v2 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3 -; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc -; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v9 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v2, -v6 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v4, v2 +; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v6, v2 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v9|, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v2, s[0:1] +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v7, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4 ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -1156,49 +1173,55 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1 -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s3 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s7 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x41b17218, s6 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s3 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1 -; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x41b17218, s6 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3f317217, v2 :: v_dual_lshlrev_b32 v0, 5, v0 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_fma_f32 v8, 0x3f317217, v2, -v5 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3377d1cf, v2 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317217, v0 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v6, 0x3f317217, v0, -v3 +; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v6, 0x3377d1cf, v0 :: v_dual_lshlrev_b32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1 +; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x41b17218, s7 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v2 +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1 ; GFX1100-GISEL-NEXT: v_fma_f32 v7, 0x3f317217, v1, -v4 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v6, 0x3377d1cf, v0 -; GFX1100-GISEL-NEXT: v_fma_f32 v8, 0x3f317217, v2, -v5 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v7, 0x3377d1cf, v1 -; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x41b17218, s7 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v4, v4, v7 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1| -; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v8, 0x3377d1cf, v2 :: v_dual_mov_b32 v3, 0 +; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2| -; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v10 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v8 :: v_dual_sub_f32 v0, v0, v9 +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v9 :: v_dual_sub_f32 v1, v1, v10 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6 @@ -1433,62 +1456,65 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) { ; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3f317217 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3377d1cf -; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 +; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7 -; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v1 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6 +; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s9, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v1, v1 -; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v1 -; SI-GISEL-NEXT: v_fma_f32 v9, v1, v4, -v8 -; SI-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9 +; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x41b17218 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v1 +; SI-GISEL-NEXT: v_fma_f32 v8, v1, v3, -v7 +; SI-GISEL-NEXT: v_fma_f32 v8, v1, v4, v8 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 -; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v9, s10, v9 -; SI-GISEL-NEXT: v_log_f32_e32 v9, v9 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3] -; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1] +; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 5, v8 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v8, s10, v8 +; SI-GISEL-NEXT: v_log_f32_e32 v8, v8 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] +; SI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] -; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v9 -; SI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; SI-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8 -; SI-GISEL-NEXT: v_log_f32_e32 v3, v2 -; SI-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10 -; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v10 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3] -; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v3 -; SI-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8 -; SI-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4 -; SI-GISEL-NEXT: v_add_f32_e32 v4, v8, v4 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v8 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_fma_f32 v9, v8, v3, -v7 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; SI-GISEL-NEXT: v_fma_f32 v9, v8, v4, v9 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s11, v2 +; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v9 +; SI-GISEL-NEXT: v_log_f32_e32 v9, v2 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v8|, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v7, s[2:3] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v9 +; SI-GISEL-NEXT: v_fma_f32 v3, v9, v3, -v7 +; SI-GISEL-NEXT: v_fma_f32 v3, v9, v4, v3 +; SI-GISEL-NEXT: v_add_f32_e32 v3, v7, v3 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v9|, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[0:1] ; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 -; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-GISEL-NEXT: s_endpgm ; @@ -1581,12 +1607,13 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v1 @@ -1597,62 +1624,64 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) { ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 ; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s9, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v1, v1 -; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x41b17218 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v1 -; VI-GISEL-NEXT: v_sub_f32_e32 v7, v1, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7 -; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x41b17218 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v1 +; VI-GISEL-NEXT: v_sub_f32_e32 v6, v1, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6 -; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 1.0, v3, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v7, s10, v7 -; VI-GISEL-NEXT: v_log_f32_e32 v7, v7 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3] -; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[0:1] -; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v7 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6 +; VI-GISEL-NEXT: v_ldexp_f32 v6, s10, v6 +; VI-GISEL-NEXT: v_log_f32_e32 v6, v6 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3] +; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v6 +; VI-GISEL-NEXT: v_sub_f32_e32 v7, v6, v5 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v8, v7, v6 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v8 -; VI-GISEL-NEXT: v_mul_f32_e32 v10, 0x3805fdf4, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; VI-GISEL-NEXT: v_add_f32_e32 v9, v10, v9 -; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317000, v8 -; VI-GISEL-NEXT: v_log_f32_e32 v3, v2 -; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v6, s[2:3] -; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v3 -; VI-GISEL-NEXT: v_sub_f32_e32 v7, v3, v6 ; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 ; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5 +; VI-GISEL-NEXT: v_ldexp_f32 v2, s11, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7 +; VI-GISEL-NEXT: v_log_f32_e32 v7, v2 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[2:3] +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v7 +; VI-GISEL-NEXT: v_sub_f32_e32 v6, v7, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[0:1] +; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] ; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4 ; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5 @@ -1730,61 +1759,64 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) { ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3f317217 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3377d1cf ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3377d1cf ; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v1 ; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v7 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s9, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x41b17218 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc ; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v1 -; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v4, -v8 +; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v3, -v8 ; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v9, s10, v9 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v9, 5, v9 +; GFX900-GISEL-NEXT: v_ldexp_f32 v9, s10, v9 ; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v9 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3] ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v9 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8 -; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v3, -v8 +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 ; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10 +; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s11, v2 ; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v10 +; GFX900-GISEL-NEXT: v_log_f32_e32 v10, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3] ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc ; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v3 -; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8 -; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4 -; GFX900-GISEL-NEXT: v_add_f32_e32 v4, v8, v4 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1] -; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v10 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v3, -v8 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v5, v3 +; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v8, v3 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v10|, v6 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[0:1] +; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v5 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -1860,60 +1892,67 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0 -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s6 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s7 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s8 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x4f800000, s9 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, s2, v2 :: v_dual_mul_f32 v3, s3, v3 -; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_3) -; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x41b17218, s7 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x41b17218, s8 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x41b17218, s9 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3f317217, v0 :: v_dual_mul_f32 v6, 0x3f317217, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v2 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v8, 0x3f317217, v3 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1 +; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v7 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v8 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v7, v7, v12 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v7, 0x3f317217, v2 :: v_dual_mul_f32 v8, 0x3f317217, v3 +; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3f317217, v0 :: v_dual_add_f32 v8, v8, v13 +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3f317217, v0, -v5 ; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3f317217, v1, -v6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v7 -; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v8 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v10, 0x3377d1cf, v0 :: v_dual_fmac_f32 v11, 0x3377d1cf, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3 ; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_dual_add_f32 v7, v7, v12 :: v_dual_add_f32 v8, v8, v13 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2| -; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_sub_f32 v1, v1, v9 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_sub_f32 v0, v0, v4 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3| -; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v3, v3, v8 :: v_dual_sub_f32 v2, v2, v14 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v9 :: v_dual_sub_f32 v2, v2, v14 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v3, v3, v15 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1] +; GFX1100-GISEL-NEXT: global_store_b128 v5, v[0:3], s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log_v4f32: @@ -2126,10 +2165,10 @@ define float @v_log_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2175,16 +2214,16 @@ define float @v_log_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -2224,10 +2263,10 @@ define float @v_log_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2270,21 +2309,22 @@ define float @v_log_f32(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2329,10 +2369,10 @@ define float @v_log_fabs_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2378,16 +2418,16 @@ define float @v_log_fabs_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -2427,10 +2467,10 @@ define float @v_log_fabs_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2475,20 +2515,22 @@ define float @v_log_fabs_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2534,10 +2576,10 @@ define float @v_log_fneg_fabs_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2583,16 +2625,16 @@ define float @v_log_fneg_fabs_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -2632,10 +2674,10 @@ define float @v_log_fneg_fabs_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2680,20 +2722,22 @@ define float @v_log_fneg_fabs_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -|v0| ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2740,10 +2784,10 @@ define float @v_log_fneg_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2789,16 +2833,16 @@ define float @v_log_fneg_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -2838,10 +2882,10 @@ define float @v_log_fneg_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -2885,20 +2929,22 @@ define float @v_log_fneg_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -3304,10 +3350,10 @@ define float @v_log_f32_ninf(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -3353,16 +3399,16 @@ define float @v_log_f32_ninf(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -3402,10 +3448,10 @@ define float @v_log_f32_ninf(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -3448,21 +3494,22 @@ define float @v_log_f32_ninf(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4038,10 +4085,10 @@ define float @v_log_f32_nnan(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -4087,16 +4134,16 @@ define float @v_log_f32_nnan(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -4136,10 +4183,10 @@ define float @v_log_f32_nnan(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -4182,21 +4229,22 @@ define float @v_log_f32_nnan(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4381,10 +4429,10 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -4430,16 +4478,16 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -4479,10 +4527,10 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -4525,21 +4573,22 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4724,10 +4773,10 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -4773,16 +4822,16 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -4822,10 +4871,10 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -4868,21 +4917,22 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4924,10 +4974,10 @@ define float @v_log_f32_nnan_ninf(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -4967,16 +5017,16 @@ define float @v_log_f32_nnan_ninf(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v0 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v0 +; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317000, v0 ; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -5010,10 +5060,10 @@ define float @v_log_f32_nnan_ninf(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -5051,18 +5101,20 @@ define float @v_log_f32_nnan_ninf(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -5207,10 +5259,10 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -5250,16 +5302,16 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v0 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v0 +; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317000, v0 ; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -5293,10 +5345,10 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -5334,18 +5386,20 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -5419,10 +5473,10 @@ define float @v_log_f32_dynamic_mode(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -5468,16 +5522,16 @@ define float @v_log_f32_dynamic_mode(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1 @@ -5517,10 +5571,10 @@ define float @v_log_f32_dynamic_mode(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf @@ -5563,21 +5617,22 @@ define float @v_log_f32_dynamic_mode(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll index fd50d1b60fbd..d09df7583733 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll @@ -45,16 +45,17 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) { ; SI-GISEL-NEXT: s_load_dword s0, s[4:5], 0xb ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 +; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0 ; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4 ; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 @@ -64,7 +65,6 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) { ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b ; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-GISEL-NEXT: s_endpgm ; @@ -104,25 +104,25 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) { ; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c ; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 -; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3 +; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 -; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 -; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2 @@ -162,25 +162,25 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) { ; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0 -; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4 -; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1 -; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v0 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v2, -v5 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 +; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x411a209b +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -218,24 +218,26 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 -; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v0, v0, v1 :: v_dual_mov_b32 v1, 0 -; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log10_f32: @@ -358,35 +360,36 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2 -; SI-GISEL-NEXT: v_log_f32_e32 v2, v2 -; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s6, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v1, v1 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 -; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v2 -; SI-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6 -; SI-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7 -; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] +; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1 +; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5 +; SI-GISEL-NEXT: v_fma_f32 v6, v1, v3, v6 +; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 -; SI-GISEL-NEXT: v_log_f32_e32 v1, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s7, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 -; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1 -; SI-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2 -; SI-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3 -; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v5 +; SI-GISEL-NEXT: v_fma_f32 v2, v5, v2, -v1 +; SI-GISEL-NEXT: v_fma_f32 v2, v5, v3, v2 +; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1] ; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 @@ -445,42 +448,43 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v2, s6, v2 -; VI-GISEL-NEXT: v_log_f32_e32 v2, v2 -; VI-GISEL-NEXT: v_and_b32_e32 v4, 0xfffff000, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v5, v2, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s6, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v1, v1 +; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v1 +; VI-GISEL-NEXT: v_sub_f32_e32 v4, v1, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v5 -; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4 ; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3 ; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v3 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 -; VI-GISEL-NEXT: v_log_f32_e32 v1, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s7, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v0 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x411a209b ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 -; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xfffff000, v1 -; VI-GISEL-NEXT: v_sub_f32_e32 v5, v1, v2 +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v3 +; VI-GISEL-NEXT: v_sub_f32_e32 v5, v3, v1 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v5 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6 ; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5 ; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 -; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v3 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 +; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v5 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1] ; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4 @@ -531,37 +535,38 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf +; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s10, v2 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v2 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v3, -v6 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v2, v4, v7 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, -v6 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v4, v7 ; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v1|, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s11, v0 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc -; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v3, -v2 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v1, v4, v3 -; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[0:1] -; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s11, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v7, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v6 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v3, -v1 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v6, v4, v3 +; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v7, s[0:1] +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -608,31 +613,37 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s4 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s5 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s2, v0 :: v_dual_mul_f32 v1, s3, v1 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, 0x3e9a209a, v0 :: v_dual_mul_f32 v3, 0x3e9a209a, v1 +; GFX1100-GISEL-NEXT: v_dual_mul_f32 v3, 0x3e9a209a, v1 :: v_dual_lshlrev_b32 v0, 5, v0 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3e9a209a, v1, -v3 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v5, 0x3284fbcf, v1 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_dual_add_f32 v3, v3, v5 :: v_dual_mul_f32 v2, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s5 ; GFX1100-GISEL-NEXT: v_fma_f32 v4, 0x3e9a209a, v0, -v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_fma_f32 v5, 0x3e9a209a, v1, -v3 -; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v4, 0x3284fbcf, v0 :: v_dual_fmac_f32 v5, 0x3284fbcf, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_dual_add_f32 v2, v2, v4 :: v_dual_add_f32 v3, v3, v5 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v4, 0x3284fbcf, v0 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v2, v2, v4 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s4 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s5 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1| -; GFX1100-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v1, v3 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_mov_b32 v2, 0 ; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5 ; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm @@ -808,49 +819,51 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf -; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 -; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v0 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7 -; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] +; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 +; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v0 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v2, -v5 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, v6 +; SI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 1.0, v2, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v6, s9, v6 -; SI-GISEL-NEXT: v_log_f32_e32 v6, v6 -; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b -; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v5, s9, v5 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 +; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b +; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v6 -; SI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1 -; SI-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8 -; SI-GISEL-NEXT: v_log_f32_e32 v2, v1 -; SI-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9 -; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3] -; SI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1] -; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6 -; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v2 -; SI-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6 -; SI-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3 -; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc -; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_fma_f32 v8, v5, v2, -v7 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_fma_f32 v8, v5, v3, v8 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1 +; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; SI-GISEL-NEXT: v_log_f32_e32 v8, v1 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v5|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v5, v7, s[2:3] +; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v6, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 +; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v8 +; SI-GISEL-NEXT: v_fma_f32 v2, v8, v2, -v5 +; SI-GISEL-NEXT: v_fma_f32 v2, v8, v3, v2 +; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v8|, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc ; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8 @@ -927,12 +940,13 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v3 @@ -943,45 +957,46 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3 ; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 ; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v2 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v2, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v3, s9, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3 +; VI-GISEL-NEXT: v_ldexp_f32 v3, s9, v3 ; VI-GISEL-NEXT: v_log_f32_e32 v3, v3 -; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x411a209b -; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v3 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x411a209b +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v3 +; VI-GISEL-NEXT: v_sub_f32_e32 v6, v3, v5 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 -; VI-GISEL-NEXT: v_sub_f32_e32 v7, v3, v6 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7 -; VI-GISEL-NEXT: v_log_f32_e32 v2, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v5 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v6, s[2:3] -; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v5, s[0:1] +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_log_f32_e32 v6, v1 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v3|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, v5, s[2:3] +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v4, s[0:1] ; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 -; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v6, v2, v3 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6 +; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xfffff000, v6 +; VI-GISEL-NEXT: v_sub_f32_e32 v5, v6, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v5 ; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v3 ; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v6 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v5, vcc +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v5 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v6|, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v3, s[0:1] +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 @@ -1046,49 +1061,51 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf ; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v0 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v6 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v2, -v6 ; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, v7 ; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 1.0, v2, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, s9, v6 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6 +; GFX900-GISEL-NEXT: v_ldexp_f32 v6, s9, v6 ; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v6 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc ; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v6 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s10, v1 -; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v3, -v8 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v2, -v8 +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 ; GFX900-GISEL-NEXT: v_fma_f32 v9, v6, v4, v9 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1 ; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 +; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v1 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v5 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v8, s[2:3] ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v7, s[0:1] ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v2 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v3, -v6 -; GFX900-GISEL-NEXT: v_fma_f32 v3, v2, v4, v3 -; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v2|, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v7, vcc -; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v9 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v2, -v6 +; GFX900-GISEL-NEXT: v_fma_f32 v2, v9, v4, v2 +; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v6, v2 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v9|, v5 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v2, s[0:1] +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v7, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v4 ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -1156,49 +1173,55 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1 -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s3 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s7 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x411a209b, s6 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s3 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1 -; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 0x411a209b, s6 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v2 :: v_dual_lshlrev_b32 v0, 5, v0 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_fma_f32 v8, 0x3e9a209a, v2, -v5 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v8, 0x3284fbcf, v2 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v5, v5, v8 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v0 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v6, 0x3e9a209a, v0, -v3 +; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v6, 0x3284fbcf, v0 :: v_dual_lshlrev_b32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1 +; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x411a209b, s7 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v2 +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1 ; GFX1100-GISEL-NEXT: v_fma_f32 v7, 0x3e9a209a, v1, -v4 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v6, 0x3284fbcf, v0 -; GFX1100-GISEL-NEXT: v_fma_f32 v8, 0x3e9a209a, v2, -v5 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v7, 0x3284fbcf, v1 -; GFX1100-GISEL-NEXT: v_add_f32_e32 v3, v3, v6 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x411a209b, s7 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v4, v4, v7 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1| -; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v8, 0x3284fbcf, v2 :: v_dual_mov_b32 v3, 0 +; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2| -; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v10 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v8 :: v_dual_sub_f32 v0, v0, v9 +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v9 :: v_dual_sub_f32 v1, v1, v10 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6 @@ -1433,62 +1456,65 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3e9a209a +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a +; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3284fbcf -; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 +; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1 -; SI-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7 -; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v7 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v1 +; SI-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6 +; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v6 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v5 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s9, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v1, v1 -; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b -; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v1 -; SI-GISEL-NEXT: v_fma_f32 v9, v1, v4, -v8 -; SI-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9 +; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x411a209b +; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v1 +; SI-GISEL-NEXT: v_fma_f32 v8, v1, v3, -v7 +; SI-GISEL-NEXT: v_fma_f32 v8, v1, v4, v8 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 -; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v9, s10, v9 -; SI-GISEL-NEXT: v_log_f32_e32 v9, v9 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3] -; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1] +; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 5, v8 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v8, s10, v8 +; SI-GISEL-NEXT: v_log_f32_e32 v8, v8 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] +; SI-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, v6, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] -; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v9 -; SI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; SI-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8 -; SI-GISEL-NEXT: v_log_f32_e32 v3, v2 -; SI-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10 -; SI-GISEL-NEXT: v_add_f32_e32 v8, v8, v10 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3] -; SI-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8 -; SI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v3 -; SI-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8 -; SI-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4 -; SI-GISEL-NEXT: v_add_f32_e32 v4, v8, v4 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v8 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_fma_f32 v9, v8, v3, -v7 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; SI-GISEL-NEXT: v_fma_f32 v9, v8, v4, v9 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s11, v2 +; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v9 +; SI-GISEL-NEXT: v_log_f32_e32 v9, v2 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v8|, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v7, s[2:3] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v7 +; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v9 +; SI-GISEL-NEXT: v_fma_f32 v3, v9, v3, -v7 +; SI-GISEL-NEXT: v_fma_f32 v3, v9, v4, v3 +; SI-GISEL-NEXT: v_add_f32_e32 v3, v7, v3 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v9|, v5 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[0:1] ; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 -; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-GISEL-NEXT: s_endpgm ; @@ -1581,12 +1607,13 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v4, v0, v1 @@ -1597,62 +1624,64 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 ; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5 ; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v4 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v3 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s9, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v1, v1 -; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x411a209b -; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v1 -; VI-GISEL-NEXT: v_sub_f32_e32 v7, v1, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 -; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7 -; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x411a209b +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v1 +; VI-GISEL-NEXT: v_sub_f32_e32 v6, v1, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6 -; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v7, 1.0, v3, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v7, s10, v7 -; VI-GISEL-NEXT: v_log_f32_e32 v7, v7 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3] -; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v5, s[0:1] -; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v7 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v6 +; VI-GISEL-NEXT: v_ldexp_f32 v6, s10, v6 +; VI-GISEL-NEXT: v_log_f32_e32 v6, v6 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3] +; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v6 +; VI-GISEL-NEXT: v_sub_f32_e32 v7, v6, v5 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v8, v7, v6 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v8 -; VI-GISEL-NEXT: v_mul_f32_e32 v10, 0x369a84fb, v6 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; VI-GISEL-NEXT: v_add_f32_e32 v9, v10, v9 -; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a2000, v8 -; VI-GISEL-NEXT: v_log_f32_e32 v3, v2 -; VI-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v6, s[2:3] -; VI-GISEL-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6 -; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xfffff000, v3 -; VI-GISEL-NEXT: v_sub_f32_e32 v7, v3, v6 ; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7 -; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 ; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5 +; VI-GISEL-NEXT: v_ldexp_f32 v2, s11, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7 +; VI-GISEL-NEXT: v_log_f32_e32 v7, v2 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, v6, v5, s[2:3] +; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5 +; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xfffff000, v7 +; VI-GISEL-NEXT: v_sub_f32_e32 v6, v7, v5 +; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v6 +; VI-GISEL-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8 ; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6 -; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v5, s[0:1] +; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v8 +; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5 +; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v6 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, v3 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] ; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4 ; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5 @@ -1730,61 +1759,64 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3e9a209a +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a +; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3284fbcf ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3284fbcf ; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x7f800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 -; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v4, -v1 +; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v3, -v1 ; GFX900-GISEL-NEXT: v_fma_f32 v7, v0, v5, v7 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v7 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], |v0|, v6 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s9, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x411a209b ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc ; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v8 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v1 -; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v4, -v8 +; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v3, -v8 ; GFX900-GISEL-NEXT: v_fma_f32 v9, v1, v5, v9 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v9 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v9, 1.0, v3, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v9, s10, v9 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v9, 5, v9 +; GFX900-GISEL-NEXT: v_ldexp_f32 v9, s10, v9 ; GFX900-GISEL-NEXT: v_log_f32_e32 v9, v9 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v6 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[2:3] ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, v7, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v8 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v9 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v4, -v8 -; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v3, -v8 +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 ; GFX900-GISEL-NEXT: v_fma_f32 v10, v9, v5, v10 +; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s11, v2 ; GFX900-GISEL-NEXT: v_add_f32_e32 v8, v8, v10 +; GFX900-GISEL-NEXT: v_log_f32_e32 v10, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v9|, v6 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, v9, v8, s[2:3] ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v7, vcc ; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v8 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v3 -; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v4, -v8 -; GFX900-GISEL-NEXT: v_fma_f32 v4, v3, v5, v4 -; GFX900-GISEL-NEXT: v_add_f32_e32 v4, v8, v4 -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, v6 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v7, s[0:1] -; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v10 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v3, -v8 +; GFX900-GISEL-NEXT: v_fma_f32 v3, v10, v5, v3 +; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v8, v3 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v10|, v6 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v7, s[0:1] +; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v5 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -1860,60 +1892,67 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0 -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s6 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s7 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s8 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x4f800000, s9 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, s2, v2 :: v_dual_mul_f32 v3, s3, v3 -; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_3) -; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 0x411a209b, s7 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 0x411a209b, s8 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 0x411a209b, s9 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v0 :: v_dual_mul_f32 v6, 0x3e9a209a, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v2 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v3 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1 +; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v7 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v8 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3 +; GFX1100-GISEL-NEXT: v_add_f32_e32 v7, v7, v12 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v7, 0x3e9a209a, v2 :: v_dual_mul_f32 v8, 0x3e9a209a, v3 +; GFX1100-GISEL-NEXT: v_dual_mul_f32 v5, 0x3e9a209a, v0 :: v_dual_add_f32 v8, v8, v13 +; GFX1100-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1100-GISEL-NEXT: v_fma_f32 v10, 0x3e9a209a, v0, -v5 ; GFX1100-GISEL-NEXT: v_fma_f32 v11, 0x3e9a209a, v1, -v6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v7 -; GFX1100-GISEL-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v8 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v10, 0x3284fbcf, v0 :: v_dual_fmac_f32 v11, 0x3284fbcf, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3 ; GFX1100-GISEL-NEXT: v_dual_add_f32 v5, v5, v10 :: v_dual_add_f32 v6, v6, v11 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_dual_add_f32 v7, v7, v12 :: v_dual_add_f32 v8, v8, v13 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2| -; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_sub_f32 v1, v1, v9 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_sub_f32 v0, v0, v4 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3| -; GFX1100-GISEL-NEXT: v_dual_cndmask_b32 v3, v3, v8 :: v_dual_sub_f32 v2, v2, v14 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v9 :: v_dual_sub_f32 v2, v2, v14 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v3, v3, v15 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1] +; GFX1100-GISEL-NEXT: global_store_b128 v5, v[0:3], s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log10_v4f32: @@ -2126,10 +2165,10 @@ define float @v_log10_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2175,16 +2214,16 @@ define float @v_log10_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -2224,10 +2263,10 @@ define float @v_log10_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2270,21 +2309,22 @@ define float @v_log10_f32(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2329,10 +2369,10 @@ define float @v_log10_fabs_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2378,16 +2418,16 @@ define float @v_log10_fabs_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -2427,10 +2467,10 @@ define float @v_log10_fabs_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2475,20 +2515,22 @@ define float @v_log10_fabs_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2534,10 +2576,10 @@ define float @v_log10_fneg_fabs_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2583,16 +2625,16 @@ define float @v_log10_fneg_fabs_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -2632,10 +2674,10 @@ define float @v_log10_fneg_fabs_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2680,20 +2722,22 @@ define float @v_log10_fneg_fabs_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -|v0| ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2740,10 +2784,10 @@ define float @v_log10_fneg_f32(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2789,16 +2833,16 @@ define float @v_log10_fneg_f32(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -2838,10 +2882,10 @@ define float @v_log10_fneg_f32(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -2885,20 +2929,22 @@ define float @v_log10_fneg_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0| +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -3304,10 +3350,10 @@ define float @v_log10_f32_ninf(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -3353,16 +3399,16 @@ define float @v_log10_f32_ninf(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -3402,10 +3448,10 @@ define float @v_log10_f32_ninf(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -3448,21 +3494,22 @@ define float @v_log10_f32_ninf(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4038,10 +4085,10 @@ define float @v_log10_f32_nnan(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -4087,16 +4134,16 @@ define float @v_log10_f32_nnan(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -4136,10 +4183,10 @@ define float @v_log10_f32_nnan(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -4182,21 +4229,22 @@ define float @v_log10_f32_nnan(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4381,10 +4429,10 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -4430,16 +4478,16 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -4479,10 +4527,10 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -4525,21 +4573,22 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4724,10 +4773,10 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -4773,16 +4822,16 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -4822,10 +4871,10 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -4868,21 +4917,22 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -4924,10 +4974,10 @@ define float @v_log10_f32_nnan_ninf(float %in) { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -4967,16 +5017,16 @@ define float @v_log10_f32_nnan_ninf(float %in) { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v0 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v0 +; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a2000, v0 ; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -5010,10 +5060,10 @@ define float @v_log10_f32_nnan_ninf(float %in) { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -5051,18 +5101,20 @@ define float @v_log10_f32_nnan_ninf(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -5207,10 +5259,10 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -5250,16 +5302,16 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v0 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v0 +; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a2000, v0 ; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v2 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -5293,10 +5345,10 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -5334,18 +5386,20 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -5419,10 +5473,10 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 { ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -5468,16 +5522,16 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 { ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 ; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 -; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1 -; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v1 +; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2 +; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v4 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2 ; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v3 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1 @@ -5517,10 +5571,10 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 { ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf @@ -5563,21 +5617,22 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0 ; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31] ; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll index 2c5a9f58a199..8b3b79b0b1bd 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll @@ -36,14 +36,14 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) { ; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb ; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-GISEL-NEXT: s_mov_b32 s2, -1 ; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -74,13 +74,13 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) { ; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c ; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s2, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -108,20 +108,19 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) { ; ; GFX900-GISEL-LABEL: s_log2_f32: ; GFX900-GISEL: ; %bb.0: -; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c -; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 -; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -147,20 +146,22 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) { ; ; GFX1100-GISEL-LABEL: s_log2_f32: ; GFX1100-GISEL: ; %bb.0: -; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GFX1100-GISEL-NEXT: s_clause 0x1 +; GFX1100-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c +; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s2 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s2 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 -; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s3 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v1 :: v_dual_mov_b32 v1, 0 -; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: global_store_b32 v2, v0, s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_f32: @@ -242,21 +243,22 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; SI-GISEL: ; %bb.0: ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 1.0, v1, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v3, s6, v3 -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 -; SI-GISEL-NEXT: v_log_f32_e32 v3, v3 -; SI-GISEL-NEXT: v_log_f32_e32 v1, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v3, v0 -; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s6, v2 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s7, v0 +; SI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v3, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1 ; SI-GISEL-NEXT: s_mov_b32 s6, -1 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 @@ -291,21 +293,22 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; VI-GISEL: ; %bb.0: ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 1.0, v1, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v3, s6, v3 -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s7, v0 -; VI-GISEL-NEXT: v_log_f32_e32 v3, v3 -; VI-GISEL-NEXT: v_log_f32_e32 v1, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v3, v0 -; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v2, s6, v2 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s7, v0 +; VI-GISEL-NEXT: v_log_f32_e32 v2, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1] +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v2, v0 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5 ; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1] @@ -339,22 +342,23 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 1.0, v1, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, v1, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, s10, v3 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s11, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3 +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v3, s10, v3 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s11, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v3 -; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] +; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1] ; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v3, v0 -; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -387,23 +391,28 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in) ; GFX1100-GISEL-LABEL: s_log2_v2f32: ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s4 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s5 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s5 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s2, v0 :: v_dual_mul_f32 v1, s3, v1 -; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3 -; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0 -; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v3 :: v_dual_lshlrev_b32 v0, 5, v0 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX1100-GISEL-NEXT: global_store_b64 v4, v[0:1], s[0:1] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_v2f32: @@ -506,32 +515,34 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; ; SI-GISEL-LABEL: s_log2_v3f32: ; SI-GISEL: ; %bb.0: -; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd -; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 +; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000 +; SI-GISEL-NEXT: s_mov_b32 s6, -1 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc -; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1 -; SI-GISEL-NEXT: s_mov_b32 s6, -1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, s9, v3 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v3, v3 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1 ; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc -; SI-GISEL-NEXT: v_mul_f32_e32 v4, s1, v4 -; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s[0:1] -; SI-GISEL-NEXT: v_log_f32_e32 v4, v4 -; SI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1 -; SI-GISEL-NEXT: v_log_f32_e32 v2, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; SI-GISEL-NEXT: v_log_f32_e32 v4, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 -; SI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8 ; SI-GISEL-NEXT: s_endpgm @@ -571,32 +582,34 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; ; VI-GISEL-LABEL: s_log2_v3f32: ; VI-GISEL: ; %bb.0: -; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 +; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 +; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 -; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24 +; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc -; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 5, v3 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v3, s9, v3 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1 ; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc -; VI-GISEL-NEXT: v_mul_f32_e32 v4, s1, v4 -; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1 -; VI-GISEL-NEXT: v_log_f32_e32 v4, v4 -; VI-GISEL-NEXT: v_log_f32_e32 v2, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] -; VI-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 -; VI-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5 +; VI-GISEL-NEXT: v_log_f32_e32 v3, v3 +; VI-GISEL-NEXT: v_log_f32_e32 v4, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1] +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v3, v1 +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2 +; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2 ; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2] ; VI-GISEL-NEXT: s_endpgm ; @@ -637,28 +650,30 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42000000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s0, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1 ; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v2, vcc -; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, s1, v4 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4 +; GFX900-GISEL-NEXT: v_ldexp_f32 v4, s1, v4 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v2, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v4 -; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v4, v1 -; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v2, v3 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2 ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -702,33 +717,40 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in) ; ; GFX1100-GISEL-LABEL: s_log2_v3f32: ; GFX1100-GISEL: ; %bb.0: +; GFX1100-GISEL-NEXT: s_clause 0x1 ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 +; GFX1100-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_mov_b32_e32 v6, 0 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s3 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s7 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s6 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s3 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s7 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s3 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1 -; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v3 :: v_dual_mov_b32 v3, 0 ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2 +; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v3 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v5 -; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1] +; GFX1100-GISEL-NEXT: global_store_b96 v6, v[0:2], s[4:5] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_v3f32: @@ -865,34 +887,37 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 +; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 +; SI-GISEL-NEXT: s_mov_b32 s6, -1 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; SI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; SI-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s9, v1 ; SI-GISEL-NEXT: v_log_f32_e32 v1, v1 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc -; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[0:1] ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] -; SI-GISEL-NEXT: v_mul_f32_e32 v5, s10, v5 -; SI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; SI-GISEL-NEXT: v_log_f32_e32 v5, v5 -; SI-GISEL-NEXT: v_log_f32_e32 v3, v2 -; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc -; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] -; SI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2 -; SI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 -; SI-GISEL-NEXT: s_mov_b32 s6, -1 +; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4 +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v4, s10, v4 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s11, v2 +; SI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; SI-GISEL-NEXT: v_log_f32_e32 v5, v2 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc +; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; SI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2 +; SI-GISEL-NEXT: v_sub_f32_e32 v3, v5, v3 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; SI-GISEL-NEXT: s_endpgm @@ -942,33 +967,36 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 +; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; VI-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 -; VI-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v1, s9, v1 ; VI-GISEL-NEXT: v_log_f32_e32 v1, v1 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc -; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 -; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v3, s[0:1] ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] -; VI-GISEL-NEXT: v_mul_f32_e32 v5, s10, v5 -; VI-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 -; VI-GISEL-NEXT: v_log_f32_e32 v5, v5 -; VI-GISEL-NEXT: v_log_f32_e32 v3, v2 -; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc -; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] -; VI-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2 -; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 +; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v4 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 5, v4 +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; VI-GISEL-NEXT: v_ldexp_f32 v4, s10, v4 +; VI-GISEL-NEXT: v_ldexp_f32 v2, s11, v2 +; VI-GISEL-NEXT: v_log_f32_e32 v4, v4 +; VI-GISEL-NEXT: v_log_f32_e32 v5, v2 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc +; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] +; VI-GISEL-NEXT: v_sub_f32_e32 v2, v4, v2 +; VI-GISEL-NEXT: v_sub_f32_e32 v3, v5, v3 ; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2 ; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3] @@ -1018,34 +1046,37 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x4f800000 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x42000000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42000000 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, s8, v0 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, v3, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v0, 5, v0 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0 +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s9, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s9, v1 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v4, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc ; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v4, s[0:1] +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, v3, s[0:1] ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2 ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v5 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v3, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v3, s[0:1] -; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, s10, v5 -; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, s11, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v5, 5, v5 +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v2, 5, v2 +; GFX900-GISEL-NEXT: v_ldexp_f32 v5, s10, v5 +; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s11, v2 ; GFX900-GISEL-NEXT: v_log_f32_e32 v5, v5 -; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v2 -; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc -; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v4, s[0:1] +; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v2 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, v3, s[0:1] ; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, v5, v2 -; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v3, v4 -; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, v6, v3 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: s_endpgm ; @@ -1095,39 +1126,46 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in) ; ; GFX1100-GISEL-LABEL: s_log2_v4f32: ; GFX1100-GISEL: ; %bb.0: +; GFX1100-GISEL-NEXT: s_clause 0x1 ; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 +; GFX1100-GISEL-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 +; GFX1100-GISEL-NEXT: v_mov_b32_e32 v8, 0 ; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1 -; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0 ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s3 +; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s2 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x4f800000, s6 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s7 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x4f800000, s8 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x4f800000, s9 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s7 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s9 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s6 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1 -; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, s2, v2 :: v_dual_mul_f32 v3, s3, v3 -; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s8 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s9 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s8 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, v1 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v0, 5, v0 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, v0 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_lshlrev_b32 v3, 5, v3 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, v3 ; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s7 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 0x42000000, s8 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 0x42000000, s9 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_3) | instid1(VALU_DEP_3) -; GFX1100-GISEL-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_sub_f32 v1, v1, v5 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff -; GFX1100-GISEL-NEXT: v_dual_sub_f32 v2, v2, v6 :: v_dual_sub_f32 v3, v3, v7 -; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0 -; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1] +; GFX1100-GISEL-NEXT: v_dual_sub_f32 v3, v3, v7 :: v_dual_lshlrev_b32 v2, 5, v2 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, v2 +; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2 +; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff +; GFX1100-GISEL-NEXT: v_sub_f32_e32 v2, v2, v6 +; GFX1100-GISEL-NEXT: global_store_b128 v8, v[0:3], s[4:5] ; GFX1100-GISEL-NEXT: s_endpgm ; ; R600-LABEL: s_log2_v4f32: @@ -1243,19 +1281,19 @@ define float @v_log2_f32(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32: ; VI-SDAG: ; %bb.0: @@ -1271,6 +1309,20 @@ define float @v_log2_f32(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1285,6 +1337,20 @@ define float @v_log2_f32(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1304,10 +1370,12 @@ define float @v_log2_f32(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1341,19 +1409,19 @@ define float @v_log2_fabs_f32(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_fabs_f32: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_fabs_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_fabs_f32: ; VI-SDAG: ; %bb.0: @@ -1369,6 +1437,20 @@ define float @v_log2_fabs_f32(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_fabs_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_fabs_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1383,6 +1465,20 @@ define float @v_log2_fabs_f32(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_fabs_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_fabs_f32: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1403,10 +1499,11 @@ define float @v_log2_fabs_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1441,19 +1538,19 @@ define float @v_log2_fneg_fabs_f32(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_fneg_fabs_f32: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_fneg_fabs_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_fneg_fabs_f32: ; VI-SDAG: ; %bb.0: @@ -1469,6 +1566,20 @@ define float @v_log2_fneg_fabs_f32(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_fneg_fabs_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_fneg_fabs_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1483,6 +1594,20 @@ define float @v_log2_fneg_fabs_f32(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_fneg_fabs_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_fneg_fabs_f32: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1503,10 +1628,11 @@ define float @v_log2_fneg_fabs_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -|v0| ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1542,19 +1668,19 @@ define float @v_log2_fneg_f32(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_fneg_f32: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_fneg_f32: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_fneg_f32: ; VI-SDAG: ; %bb.0: @@ -1570,6 +1696,20 @@ define float @v_log2_fneg_f32(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_fneg_f32: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_fneg_f32: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1584,6 +1724,20 @@ define float @v_log2_fneg_f32(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_fneg_f32: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_fneg_f32: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1604,10 +1758,11 @@ define float @v_log2_fneg_f32(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0 ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, -v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1642,19 +1797,19 @@ define float @v_log2_f32_fast(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_fast: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_fast: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_fast: ; VI-SDAG: ; %bb.0: @@ -1670,6 +1825,20 @@ define float @v_log2_f32_fast(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_fast: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_fast: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1684,6 +1853,20 @@ define float @v_log2_f32_fast(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_fast: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_fast: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1703,10 +1886,12 @@ define float @v_log2_f32_fast(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1740,19 +1925,19 @@ define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_unsafe_math_attr: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_unsafe_math_attr: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_unsafe_math_attr: ; VI-SDAG: ; %bb.0: @@ -1768,6 +1953,20 @@ define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_unsafe_math_attr: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_unsafe_math_attr: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1782,6 +1981,20 @@ define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_unsafe_math_attr: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_unsafe_math_attr: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1801,10 +2014,12 @@ define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1838,19 +2053,19 @@ define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_approx_fn_attr: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_approx_fn_attr: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_approx_fn_attr: ; VI-SDAG: ; %bb.0: @@ -1866,6 +2081,20 @@ define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_approx_fn_attr: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_approx_fn_attr: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1880,6 +2109,20 @@ define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_approx_fn_attr: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_approx_fn_attr: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1899,10 +2142,12 @@ define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -1936,19 +2181,19 @@ define float @v_log2_f32_ninf(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_ninf: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_ninf: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_ninf: ; VI-SDAG: ; %bb.0: @@ -1964,6 +2209,20 @@ define float @v_log2_f32_ninf(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_ninf: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_ninf: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1978,6 +2237,20 @@ define float @v_log2_f32_ninf(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_ninf: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_ninf: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1997,10 +2270,12 @@ define float @v_log2_f32_ninf(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2034,19 +2309,19 @@ define float @v_log2_f32_afn(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_afn: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_afn: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_afn: ; VI-SDAG: ; %bb.0: @@ -2062,6 +2337,20 @@ define float @v_log2_f32_afn(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_afn: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_afn: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2076,6 +2365,20 @@ define float @v_log2_f32_afn(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_afn: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_afn: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2095,10 +2398,12 @@ define float @v_log2_f32_afn(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2158,19 +2463,19 @@ define float @v_log2_f32_afn_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_afn_dynamic: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_afn_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_afn_dynamic: ; VI-SDAG: ; %bb.0: @@ -2186,6 +2491,20 @@ define float @v_log2_f32_afn_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_afn_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_afn_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2200,6 +2519,20 @@ define float @v_log2_f32_afn_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_afn_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_afn_dynamic: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2219,10 +2552,12 @@ define float @v_log2_f32_afn_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2256,19 +2591,19 @@ define float @v_fabs_log2_f32_afn(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_fabs_log2_f32_afn: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_fabs_log2_f32_afn: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_fabs_log2_f32_afn: ; VI-SDAG: ; %bb.0: @@ -2284,6 +2619,20 @@ define float @v_fabs_log2_f32_afn(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_fabs_log2_f32_afn: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_fabs_log2_f32_afn: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2298,6 +2647,20 @@ define float @v_fabs_log2_f32_afn(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_fabs_log2_f32_afn: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_fabs_log2_f32_afn: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2318,10 +2681,11 @@ define float @v_fabs_log2_f32_afn(float %in) { ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0| ; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, s0 -; GFX1100-GISEL-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0 -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2382,19 +2746,19 @@ define float @v_log2_f32_nnan(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_nnan: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_nnan: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_nnan: ; VI-SDAG: ; %bb.0: @@ -2410,6 +2774,20 @@ define float @v_log2_f32_nnan(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_nnan: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_nnan: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2424,6 +2802,20 @@ define float @v_log2_f32_nnan(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_nnan: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_nnan: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2443,10 +2835,12 @@ define float @v_log2_f32_nnan(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2506,19 +2900,19 @@ define float @v_log2_f32_nnan_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_nnan_dynamic: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_nnan_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_nnan_dynamic: ; VI-SDAG: ; %bb.0: @@ -2534,6 +2928,20 @@ define float @v_log2_f32_nnan_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_nnan_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_nnan_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2548,6 +2956,20 @@ define float @v_log2_f32_nnan_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_nnan_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_nnan_dynamic: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2567,10 +2989,12 @@ define float @v_log2_f32_nnan_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2630,19 +3054,19 @@ define float @v_log2_f32_ninf_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_ninf_dynamic: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_ninf_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_ninf_dynamic: ; VI-SDAG: ; %bb.0: @@ -2658,6 +3082,20 @@ define float @v_log2_f32_ninf_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_ninf_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_ninf_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2672,6 +3110,20 @@ define float @v_log2_f32_ninf_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_ninf_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_ninf_dynamic: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2691,10 +3143,12 @@ define float @v_log2_f32_ninf_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2728,19 +3182,19 @@ define float @v_log2_f32_nnan_ninf(float %in) { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_nnan_ninf: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_nnan_ninf: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_nnan_ninf: ; VI-SDAG: ; %bb.0: @@ -2756,6 +3210,20 @@ define float @v_log2_f32_nnan_ninf(float %in) { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_nnan_ninf: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_nnan_ninf: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2770,6 +3238,20 @@ define float @v_log2_f32_nnan_ninf(float %in) { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_nnan_ninf: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_nnan_ninf: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2789,10 +3271,12 @@ define float @v_log2_f32_nnan_ninf(float %in) { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2852,19 +3336,19 @@ define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic: ; VI-SDAG: ; %bb.0: @@ -2880,6 +3364,20 @@ define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2894,6 +3392,20 @@ define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2913,10 +3425,12 @@ define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 @@ -2976,19 +3490,19 @@ define float @v_log2_f32_dynamic_mode(float %in) #1 { ; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; -; GFX689-GISEL-LABEL: v_log2_f32_dynamic_mode: -; GFX689-GISEL: ; %bb.0: -; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GFX689-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v2, vcc -; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0 -; GFX689-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 -; GFX689-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GFX689-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31] +; SI-GISEL-LABEL: v_log2_f32_dynamic_mode: +; SI-GISEL: ; %bb.0: +; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; VI-SDAG-LABEL: v_log2_f32_dynamic_mode: ; VI-SDAG: ; %bb.0: @@ -3004,6 +3518,20 @@ define float @v_log2_f32_dynamic_mode(float %in) #1 { ; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; VI-GISEL-LABEL: v_log2_f32_dynamic_mode: +; VI-GISEL: ; %bb.0: +; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; VI-GISEL-NEXT: v_log_f32_e32 v0, v0 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX900-SDAG-LABEL: v_log2_f32_dynamic_mode: ; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -3018,6 +3546,20 @@ define float @v_log2_f32_dynamic_mode(float %in) #1 { ; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; +; GFX900-GISEL-LABEL: v_log2_f32_dynamic_mode: +; GFX900-GISEL: ; %bb.0: +; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000 +; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 +; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0 +; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000 +; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] +; ; GFX1100-SDAG-LABEL: v_log2_f32_dynamic_mode: ; GFX1100-SDAG: ; %bb.0: ; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -3037,10 +3579,12 @@ define float @v_log2_f32_dynamic_mode(float %in) #1 { ; GFX1100-GISEL: ; %bb.0: ; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo -; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1 +; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1 ; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo +; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff ; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll index 4de0c548ad38..795ed6d542a1 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll @@ -3,6 +3,7 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX89,VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX89,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX12 %s declare half @llvm.rint.f16(half %a) declare <2 x half> @llvm.rint.v2f16(<2 x half> %a) @@ -63,6 +64,24 @@ define amdgpu_kernel void @rint_f16( ; GFX11-NEXT: v_rndne_f16_e32 v0, v0 ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: rint_f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_rndne_f16_e32 v0, v0 +; GFX12-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX12-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a) { entry: @@ -168,6 +187,28 @@ define amdgpu_kernel void @rint_v2f16( ; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX11-NEXT: buffer_store_b32 v0, off, s[4:7], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: rint_v2f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX12-NEXT: v_rndne_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_rndne_f16_e32 v1, v1 +; GFX12-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX12-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX12-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a) { entry: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll index 2bb89fdabda7..6927636ad04a 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll @@ -4,6 +4,7 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX11 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX12 %s define amdgpu_kernel void @sin_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) { ; GFX6-LABEL: sin_f16: @@ -80,6 +81,19 @@ define amdgpu_kernel void @sin_f16(ptr addrspace(1) %r, ptr addrspace(1) %a) { ; GFX11-NEXT: v_sin_f16_e32 v1, v1 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: sin_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_sin_f16_e32 v1, v1 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX12-NEXT: s_endpgm %a.val = load half, ptr addrspace(1) %a %r.val = call half @llvm.sin.f16(half %a.val) store half %r.val, ptr addrspace(1) %r @@ -188,6 +202,24 @@ define amdgpu_kernel void @sin_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) { ; GFX11-NEXT: v_pack_b32_f16 v1, v1, v2 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: sin_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX12-NEXT: v_mul_f16_e32 v1, 0.15915494, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_mul_f16_e32 v2, 0.15915494, v2 +; GFX12-NEXT: v_sin_f16_e32 v1, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) +; GFX12-NEXT: v_sin_f16_e32 v2, v2 +; GFX12-NEXT: v_pack_b32_f16 v1, v1, v2 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_endpgm %a.val = load <2 x half>, ptr addrspace(1) %a %r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val) store <2 x half> %r.val, ptr addrspace(1) %r diff --git a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll index 47777e3853e8..0d58afd1812d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll @@ -2,6 +2,7 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s declare half @llvm.trunc.f16(half %a) declare <2 x half> @llvm.trunc.v2f16(<2 x half> %a) @@ -62,6 +63,24 @@ define amdgpu_kernel void @trunc_f16( ; GFX11-NEXT: v_trunc_f16_e32 v0, v0 ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: trunc_f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_trunc_f16_e32 v0, v0 +; GFX12-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX12-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a) { entry: @@ -147,6 +166,28 @@ define amdgpu_kernel void @trunc_v2f16( ; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX11-NEXT: buffer_store_b32 v0, off, s[4:7], 0 ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: trunc_v2f16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: s_mov_b32 s6, -1 +; GFX12-NEXT: s_mov_b32 s7, 0x31016000 +; GFX12-NEXT: s_mov_b32 s10, s6 +; GFX12-NEXT: s_mov_b32 s11, s7 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s8, s2 +; GFX12-NEXT: s_mov_b32 s9, s3 +; GFX12-NEXT: s_mov_b32 s4, s0 +; GFX12-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX12-NEXT: s_mov_b32 s5, s1 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX12-NEXT: v_trunc_f16_e32 v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_trunc_f16_e32 v1, v1 +; GFX12-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX12-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX12-NEXT: s_endpgm ptr addrspace(1) %r, ptr addrspace(1) %a) { entry: diff --git a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll index 33007e5b285d..3be17f9538d0 100644 --- a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll +++ b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll @@ -1333,5 +1333,668 @@ define i48 @mad_i48_i48(i48 %arg0, i48 %arg1, i48 %arg2) #0 { ret i48 %a } +define i64 @lshr_mad_i64_1(i64 %arg0, i64 %arg1) #0 { +; CI-LABEL: lshr_mad_i64_1: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_movk_i32 s4, 0xfc19 +; CI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; CI-NEXT: v_sub_i32_e32 v1, vcc, v3, v1 +; CI-NEXT: v_mov_b32_e32 v0, v2 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_1: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: s_movk_i32 s4, 0xfc19 +; SI-NEXT: v_mul_hi_u32 v2, v1, s4 +; SI-NEXT: v_mul_lo_u32 v3, v1, s4 +; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_movk_i32 s4, 0xfc19 +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; GFX9-NEXT: v_sub_u32_e32 v1, v3, v1 +; GFX9-NEXT: v_mov_b32_e32 v0, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: lshr_mad_i64_1: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0xfffffc19, v1, v[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_sub_nc_u32_e32 v1, v3, v1 +; GFX11-NEXT: v_mov_b32_e32 v0, v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, 0xfffffc19, v1, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_sub_nc_u32_e32 v1, v3, v1 +; GFX12-NEXT: v_mov_b32_e32 v0, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %lsh = lshr i64 %arg0, 32 + %mul = mul i64 %lsh, s0xfffffffffffffc19 + %mad = add i64 %mul, %arg0 + + ret i64 %mad +} + +define i64 @lshr_mad_i64_2(i64 %arg0) #0 { +; CI-LABEL: lshr_mad_i64_2: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_movk_i32 s4, 0xd1 +; CI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; CI-NEXT: v_sub_i32_e32 v1, vcc, v3, v1 +; CI-NEXT: v_mov_b32_e32 v0, v2 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_2: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: s_movk_i32 s4, 0xd1 +; SI-NEXT: v_mul_hi_u32 v2, v1, s4 +; SI-NEXT: v_mul_lo_u32 v3, v1, s4 +; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_movk_i32 s4, 0xd1 +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; GFX9-NEXT: v_sub_u32_e32 v1, v3, v1 +; GFX9-NEXT: v_mov_b32_e32 v0, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: lshr_mad_i64_2: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0xd1, v1, v[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_sub_nc_u32_e32 v1, v3, v1 +; GFX11-NEXT: v_mov_b32_e32 v0, v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_2: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, 0xd1, v1, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_sub_nc_u32_e32 v1, v3, v1 +; GFX12-NEXT: v_mov_b32_e32 v0, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %lsh = lshr i64 %arg0, 32 + %mul = mul i64 %lsh, s0xffffffff000000d1 + %mad = add i64 %mul, %arg0 + + ret i64 %mad +} + +define i64 @lshr_mad_i64_3(i64 %arg0) #0 { +; CI-LABEL: lshr_mad_i64_3: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_movk_i32 s4, 0xfc88 +; CI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; CI-NEXT: v_sub_i32_e32 v1, vcc, v3, v1 +; CI-NEXT: v_mov_b32_e32 v0, v2 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_3: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: s_movk_i32 s4, 0xfc88 +; SI-NEXT: v_mul_hi_u32 v2, v1, s4 +; SI-NEXT: v_mul_lo_u32 v3, v1, s4 +; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_movk_i32 s4, 0xfc88 +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; GFX9-NEXT: v_sub_u32_e32 v1, v3, v1 +; GFX9-NEXT: v_mov_b32_e32 v0, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: lshr_mad_i64_3: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0xfffffc88, v1, v[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_sub_nc_u32_e32 v1, v3, v1 +; GFX11-NEXT: v_mov_b32_e32 v0, v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_3: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, 0xfffffc88, v1, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_sub_nc_u32_e32 v1, v3, v1 +; GFX12-NEXT: v_mov_b32_e32 v0, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %lsh = lshr i64 %arg0, 32 + %mul = mul i64 s0xfffffffffffffc88, %lsh + %mad = add i64 %mul, %arg0 + + ret i64 %mad +} + +define i64 @lshr_mad_i64_4(i32 %arg0, i64 %arg1) #0 { +; CI-LABEL: lshr_mad_i64_4: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_mul_lo_u32 v3, v2, v0 +; CI-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v1, v0, 0 +; CI-NEXT: s_movk_i32 s4, 0xfc88 +; CI-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[1:2] +; CI-NEXT: v_sub_i32_e32 v1, vcc, v1, v2 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_4: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mul_lo_u32 v2, v2, v0 +; SI-NEXT: v_mul_hi_u32 v3, v1, v0 +; SI-NEXT: s_movk_i32 s4, 0xfc88 +; SI-NEXT: v_mul_lo_u32 v0, v1, v0 +; SI-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; SI-NEXT: v_mul_hi_u32 v3, v2, s4 +; SI-NEXT: v_mul_lo_u32 v1, v2, s4 +; SI-NEXT: v_sub_i32_e32 v3, vcc, v3, v2 +; SI-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v0, 0 +; GFX9-NEXT: v_mov_b32_e32 v6, v5 +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v2, v0, v[6:7] +; GFX9-NEXT: v_mov_b32_e32 v5, v2 +; GFX9-NEXT: s_movk_i32 s4, 0xfc88 +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[4:5] +; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: lshr_mad_i64_4: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v1, v0, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v1, v4 +; GFX11-NEXT: v_mad_u64_u32 v[5:6], null, v2, v0, v[1:2] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_mov_b32_e32 v4, v5 +; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, 0xfffffc88, v5, v[3:4] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_sub_nc_u32_e32 v1, v1, v5 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_4: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v1, v0, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mov_b32_e32 v1, v4 +; GFX12-NEXT: v_mad_co_u64_u32 v[5:6], null, v2, v0, v[1:2] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mov_b32_e32 v4, v5 +; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, 0xfffffc88, v5, v[3:4] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_sub_nc_u32_e32 v1, v1, v5 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %ext = zext i32 %arg0 to i64 + %mul1 = mul i64 %arg1, %ext + %lsh = lshr i64 %mul1, 32 + %mul2 = mul i64 %lsh, s0xfffffffffffffc88 + %mad = add i64 %mul2, %mul1 + ret i64 %mad +} + +define i64 @lshr_mad_i64_negative_1(i64 %arg0) #0 { +; CI-LABEL: lshr_mad_i64_negative_1: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_lshrrev_b32_e32 v2, 4, v1 +; CI-NEXT: s_movk_i32 s4, 0xfc19 +; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v2, s4, v[0:1] +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_negative_1: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v2, 4, v1 +; SI-NEXT: s_movk_i32 s4, 0xfc19 +; SI-NEXT: v_mul_lo_u32 v3, v2, s4 +; SI-NEXT: v_mul_hi_i32 v2, v2, s4 +; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_negative_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 4, v1 +; GFX9-NEXT: s_movk_i32 s4, 0xfc19 +; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v2, s4, v[0:1] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX1100-LABEL: lshr_mad_i64_negative_1: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_lshrrev_b32_e32 v4, 4, v1 +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-NEXT: v_mad_i64_i32 v[2:3], null, 0xfffffc19, v4, v[0:1] +; GFX1100-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX1150-LABEL: lshr_mad_i64_negative_1: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1150-NEXT: v_lshrrev_b32_e32 v2, 4, v1 +; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, 0xfffffc19, v2, v[0:1] +; GFX1150-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_negative_1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_lshrrev_b32_e32 v2, 4, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, 0xfffffc19, v2, v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] + %lsh = lshr i64 %arg0, 36 + %mul = mul i64 %lsh, s0xfffffffffffffc19 + %mad = add i64 %mul, %arg0 + + ret i64 %mad +} + +define i64 @lshr_mad_i64_negative_2(i64 %arg0) #0 { +; CI-LABEL: lshr_mad_i64_negative_2: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_movk_i32 s4, 0xd1 +; CI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; CI-NEXT: v_lshlrev_b32_e32 v0, 8, v1 +; CI-NEXT: v_sub_i32_e32 v1, vcc, v3, v0 +; CI-NEXT: v_mov_b32_e32 v0, v2 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_negative_2: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: s_movk_i32 s4, 0xd1 +; SI-NEXT: v_mul_hi_u32 v2, v1, s4 +; SI-NEXT: v_mul_lo_u32 v4, v1, s4 +; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v1 +; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 +; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_negative_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_movk_i32 s4, 0xd1 +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1] +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v1 +; GFX9-NEXT: v_sub_u32_e32 v1, v3, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: lshr_mad_i64_negative_2: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0xd1, v1, v[0:1] +; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_sub_nc_u32_e32 v1, v3, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_negative_2: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, 0xd1, v1, v[0:1] +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 8, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_sub_nc_u32_e32 v1, v3, v0 +; GFX12-NEXT: v_mov_b32_e32 v0, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %lsh = lshr i64 %arg0, 32 + %mul = mul i64 %lsh, s0xffffff00000000d1 + %mad = add i64 %mul, %arg0 + + ret i64 %mad +} + +define i64 @lshr_mad_i64_negative_3(i64 %arg0) #0 { +; CI-LABEL: lshr_mad_i64_negative_3: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_lshr_b64 v[2:3], v[0:1], 22 +; CI-NEXT: v_and_b32_e32 v2, 0xfffffc00, v2 +; CI-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; CI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc +; CI-NEXT: v_add_i32_e32 v0, vcc, 1, v0 +; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_negative_3: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_lshr_b64 v[2:3], v[0:1], 22 +; SI-NEXT: v_and_b32_e32 v2, 0xfffffc00, v2 +; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc +; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_negative_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshrrev_b64 v[2:3], 22, v[0:1] +; GFX9-NEXT: v_and_b32_e32 v2, 0xfffffc00, v2 +; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: lshr_mad_i64_negative_3: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_lshrrev_b64 v[2:3], 22, v[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_and_b32_e32 v2, 0xfffffc00, v2 +; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_negative_3: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_lshrrev_b64 v[2:3], 22, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_and_b32_e32 v2, 0xfffffc00, v2 +; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX12-NEXT: s_setpc_b64 s[30:31] + %op = add i64 %arg0, 1 + %lsh = lshr i64 %arg0, 32 + %mul = mul i64 %lsh, s0xfffffffffffffc00 + %mad = add i64 %mul, %op + + ret i64 %mad +} + +define i64 @lshr_mad_i64_negative_4(i64 %arg0) #0 { +; CI-LABEL: lshr_mad_i64_negative_4: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v0, v[0:1] +; CI-NEXT: v_mul_lo_u32 v0, v1, v1 +; CI-NEXT: v_add_i32_e32 v1, vcc, v0, v3 +; CI-NEXT: v_mov_b32_e32 v0, v2 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_negative_4: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mul_hi_u32 v2, v1, v0 +; SI-NEXT: v_mul_lo_u32 v3, v1, v1 +; SI-NEXT: v_mul_lo_u32 v4, v1, v0 +; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_negative_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v0, v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v0, v3 +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v1, v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v0, v2 +; GFX9-NEXT: v_mov_b32_e32 v1, v4 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX1100-LABEL: lshr_mad_i64_negative_4: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_mad_u64_u32 v[2:3], null, v1, v0, v[0:1] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1100-NEXT: v_mov_b32_e32 v0, v3 +; GFX1100-NEXT: v_mad_u64_u32 v[3:4], null, v1, v1, v[0:1] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX1150-LABEL: lshr_mad_i64_negative_4: +; GFX1150: ; %bb.0: +; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1150-NEXT: v_mad_u64_u32 v[3:4], null, v1, v0, v[0:1] +; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1150-NEXT: v_mov_b32_e32 v0, v4 +; GFX1150-NEXT: v_mad_u64_u32 v[1:2], null, v1, v1, v[0:1] +; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX1150-NEXT: v_mov_b32_e32 v0, v3 +; GFX1150-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_negative_4: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v1, v0, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_mov_b32_e32 v0, v4 +; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v1, v1, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-NEXT: v_mov_b32_e32 v0, v3 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %lsh = lshr i64 %arg0, 32 + %mul = mul i64 %lsh, %arg0 + %mad = add i64 %mul, %arg0 + + ret i64 %mad +} + +define amdgpu_ps i64 @lshr_mad_i64_sgpr(i64 inreg %arg0) #0 { +; CI-LABEL: lshr_mad_i64_sgpr: +; CI: ; %bb.0: +; CI-NEXT: v_mov_b32_e32 v0, s0 +; CI-NEXT: v_mov_b32_e32 v2, 0xffff1c18 +; CI-NEXT: v_mov_b32_e32 v1, s1 +; CI-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s1, v2, v[0:1] +; CI-NEXT: v_subrev_i32_e32 v1, vcc, s1, v1 +; CI-NEXT: v_readfirstlane_b32 s0, v0 +; CI-NEXT: v_readfirstlane_b32 s1, v1 +; CI-NEXT: ; return to shader part epilog +; +; SI-LABEL: lshr_mad_i64_sgpr: +; SI: ; %bb.0: +; SI-NEXT: v_mov_b32_e32 v0, 0xffff1c18 +; SI-NEXT: v_mul_hi_u32 v0, s1, v0 +; SI-NEXT: s_mul_i32 s2, s1, 0xffff1c18 +; SI-NEXT: v_readfirstlane_b32 s3, v0 +; SI-NEXT: s_sub_i32 s3, s3, s1 +; SI-NEXT: s_add_u32 s0, s2, s0 +; SI-NEXT: s_addc_u32 s1, s3, s1 +; SI-NEXT: ; return to shader part epilog +; +; GFX9-LABEL: lshr_mad_i64_sgpr: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_mul_hi_u32 s2, s1, 0xffff1c18 +; GFX9-NEXT: s_sub_i32 s2, s2, s1 +; GFX9-NEXT: s_mul_i32 s3, s1, 0xffff1c18 +; GFX9-NEXT: s_add_u32 s0, s3, s0 +; GFX9-NEXT: s_addc_u32 s1, s2, s1 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: lshr_mad_i64_sgpr: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mul_hi_u32 s2, s1, 0xffff1c18 +; GFX11-NEXT: s_mul_i32 s3, s1, 0xffff1c18 +; GFX11-NEXT: s_sub_i32 s2, s2, s1 +; GFX11-NEXT: s_add_u32 s0, s3, s0 +; GFX11-NEXT: s_addc_u32 s1, s2, s1 +; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: lshr_mad_i64_sgpr: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mov_b32 s4, 0xffff1c18 +; GFX12-NEXT: s_mov_b32 s3, 0 +; GFX12-NEXT: s_mov_b32 s2, s1 +; GFX12-NEXT: s_mov_b32 s5, -1 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_u64 s[2:3], s[2:3], s[4:5] +; GFX12-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-NEXT: ; return to shader part epilog + %lsh = lshr i64 %arg0, 32 + %mul = mul i64 %lsh, s0xffffffffffff1c18 + %mad = add i64 %mul, %arg0 + + ret i64 %mad +} + +define <2 x i64> @lshr_mad_i64_vec(<2 x i64> %arg0) #0 { +; CI-LABEL: lshr_mad_i64_vec: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: s_mov_b32 s4, 0xffff1c18 +; CI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[0:1] +; CI-NEXT: s_mov_b32 s4, 0xffff1118 +; CI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v3, s4, v[2:3] +; CI-NEXT: v_sub_i32_e32 v1, vcc, v5, v1 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v7, v3 +; CI-NEXT: v_mov_b32_e32 v0, v4 +; CI-NEXT: v_mov_b32_e32 v2, v6 +; CI-NEXT: s_setpc_b64 s[30:31] +; +; SI-LABEL: lshr_mad_i64_vec: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: s_mov_b32 s4, 0xffff1118 +; SI-NEXT: v_mul_lo_u32 v4, v3, s4 +; SI-NEXT: v_mul_hi_u32 v5, v3, s4 +; SI-NEXT: s_mov_b32 s4, 0xffff1c18 +; SI-NEXT: v_mul_hi_u32 v6, v1, s4 +; SI-NEXT: v_mul_lo_u32 v7, v1, s4 +; SI-NEXT: v_sub_i32_e32 v5, vcc, v5, v3 +; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v1 +; SI-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc +; SI-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; SI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc +; SI-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: lshr_mad_i64_vec: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b32 s4, 0xffff1c18 +; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[0:1] +; GFX9-NEXT: s_mov_b32 s4, 0xffff1118 +; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v3, s4, v[2:3] +; GFX9-NEXT: v_sub_u32_e32 v1, v5, v1 +; GFX9-NEXT: v_sub_u32_e32 v3, v7, v3 +; GFX9-NEXT: v_mov_b32_e32 v0, v4 +; GFX9-NEXT: v_mov_b32_e32 v2, v6 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: lshr_mad_i64_vec: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, 0xffff1c18, v1, v[0:1] +; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffff1118, v3, v[2:3] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_sub_nc_u32_e32 v1, v5, v1 +; GFX11-NEXT: v_mov_b32_e32 v0, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_sub_nc_u32_e32 v3, v7, v3 +; GFX11-NEXT: v_mov_b32_e32 v2, v6 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: lshr_mad_i64_vec: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mad_co_u64_u32 v[4:5], null, 0xffff1c18, v1, v[0:1] +; GFX12-NEXT: v_mad_co_u64_u32 v[6:7], null, 0xffff1118, v3, v[2:3] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_sub_nc_u32_e32 v1, v5, v1 +; GFX12-NEXT: v_mov_b32_e32 v0, v4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_sub_nc_u32_e32 v3, v7, v3 +; GFX12-NEXT: v_mov_b32_e32 v2, v6 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %lsh = lshr <2 x i64> %arg0, <i64 32, i64 32> + %mul = mul <2 x i64> %lsh, <i64 s0xffffffffffff1c18, i64 s0xffffffffffff1118> + %mad = add <2 x i64> %mul, %arg0 + + ret <2 x i64> %mad +} + attributes #0 = { nounwind } attributes #1 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.ll index 5e46fd6b28d2..fa15a42aef2a 100644 --- a/llvm/test/CodeGen/AMDGPU/maximumnum.ll +++ b/llvm/test/CodeGen/AMDGPU/maximumnum.ll @@ -1838,11 +1838,11 @@ define <3 x half> @v_maximumnum_v3f16(<3 x half> %x, <3 x half> %y) { ; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 ; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 ; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_max_f16_e32 v2, v3, v3 +; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_max_f16_e32 v1, v1, v3 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_max_f16_e32 v1, v1, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximumnum_v3f16: @@ -1904,8 +1904,8 @@ define <3 x half> @v_maximumnum_v3f16_nnan(<3 x half> %x, <3 x half> %y) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v3 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximumnum_v3f16_nnan: @@ -1947,20 +1947,20 @@ define <4 x half> @v_maximumnum_v4f16(<4 x half> %x, <4 x half> %y) { ; GFX8-LABEL: v_maximumnum_v4f16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v5, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v4, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v5, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v4, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v6, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX8-NEXT: v_max_f16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX8-NEXT: v_max_f16_e32 v1, v1, v3 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v5 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximumnum_v4f16: @@ -2020,12 +2020,12 @@ define <4 x half> @v_maximumnum_v4f16_nnan(<4 x half> %x, <4 x half> %y) { ; GFX8-LABEL: v_maximumnum_v4f16_nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_max_f16_sdwa v2, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v3 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v5 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximumnum_v4f16_nnan: @@ -2067,27 +2067,27 @@ define <6 x half> @v_maximumnum_v6f16(<6 x half> %x, <6 x half> %y) { ; GFX8-LABEL: v_maximumnum_v6f16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_sdwa v6, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v7, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 -; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v6, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v7, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_max_f16_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v0, v0, v3 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v6 -; GFX8-NEXT: v_max_f16_sdwa v3, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v6, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v7, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v7, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v8, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e32 v5, v5, v5 +; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 ; GFX8-NEXT: v_max_f16_e32 v4, v4, v4 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX8-NEXT: v_max_f16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v2, v2, v5 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v4 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX8-NEXT: v_max_f16_sdwa v3, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v4, v5, v5 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v4 -; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v3 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v8 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v7 +; GFX8-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximumnum_v6f16: @@ -2159,34 +2159,34 @@ define <8 x half> @v_maximumnum_v8f16(<8 x half> %x, <8 x half> %y) { ; GFX8-LABEL: v_maximumnum_v8f16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_sdwa v8, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_e32 v4, v4, v4 -; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v8, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v9, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_max_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v0, v0, v4 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v8 -; GFX8-NEXT: v_max_f16_sdwa v4, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v9, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v10, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v9, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v10, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v11, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v10, v11, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v11, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v12, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e32 v7, v7, v7 +; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 +; GFX8-NEXT: v_max_f16_e32 v6, v6, v6 +; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 ; GFX8-NEXT: v_max_f16_e32 v5, v5, v5 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX8-NEXT: v_max_f16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v4, v4, v4 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v11, v12, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v3, v3, v7 +; GFX8-NEXT: v_max_f16_e32 v2, v2, v6 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v5 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 -; GFX8-NEXT: v_max_f16_sdwa v4, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v5, v6, v6 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v5 -; GFX8-NEXT: v_or_b32_e32 v2, v2, v4 -; GFX8-NEXT: v_max_f16_sdwa v4, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v5, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v5, v7, v7 -; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 -; GFX8-NEXT: v_max_f16_e32 v3, v3, v5 -; GFX8-NEXT: v_or_b32_e32 v3, v3, v4 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v4 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v11 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v10 +; GFX8-NEXT: v_or_b32_e32 v2, v2, v9 +; GFX8-NEXT: v_or_b32_e32 v3, v3, v8 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_maximumnum_v8f16: diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.ll index 9e0b7daf38de..f5fb85d63b8e 100644 --- a/llvm/test/CodeGen/AMDGPU/minimumnum.ll +++ b/llvm/test/CodeGen/AMDGPU/minimumnum.ll @@ -1792,11 +1792,11 @@ define <3 x half> @v_minimumnum_v3f16(<3 x half> %x, <3 x half> %y) { ; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 ; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 ; GFX8-NEXT: v_min_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_max_f16_e32 v2, v3, v3 +; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 +; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_min_f16_e32 v1, v1, v3 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_min_f16_e32 v1, v1, v2 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimumnum_v3f16: @@ -1858,8 +1858,8 @@ define <3 x half> @v_minimumnum_v3f16_nnan(<3 x half> %x, <3 x half> %y) { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX8-NEXT: v_min_f16_e32 v1, v1, v3 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimumnum_v3f16_nnan: @@ -1901,20 +1901,20 @@ define <4 x half> @v_minimumnum_v4f16(<4 x half> %x, <4 x half> %y) { ; GFX8-LABEL: v_minimumnum_v4f16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v5, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v4, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v5, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_min_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v4, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v6, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX8-NEXT: v_min_f16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_min_f16_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX8-NEXT: v_min_f16_e32 v1, v1, v3 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v5 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimumnum_v4f16: @@ -1974,12 +1974,12 @@ define <4 x half> @v_minimumnum_v4f16_nnan(<4 x half> %x, <4 x half> %y) { ; GFX8-LABEL: v_minimumnum_v4f16_nnan: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 -; GFX8-NEXT: v_min_f16_sdwa v2, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_min_f16_e32 v1, v1, v3 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX8-NEXT: v_min_f16_e32 v0, v0, v2 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v5 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimumnum_v4f16_nnan: @@ -2021,27 +2021,27 @@ define <6 x half> @v_minimumnum_v6f16(<6 x half> %x, <6 x half> %y) { ; GFX8-LABEL: v_minimumnum_v6f16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_sdwa v6, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v7, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 -; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v6, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v7, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_min_f16_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_f16_e32 v0, v0, v3 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v6 -; GFX8-NEXT: v_max_f16_sdwa v3, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v6, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v7, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_sdwa v7, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v8, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e32 v5, v5, v5 +; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 ; GFX8-NEXT: v_max_f16_e32 v4, v4, v4 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX8-NEXT: v_min_f16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_min_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_min_f16_e32 v2, v2, v5 ; GFX8-NEXT: v_min_f16_e32 v1, v1, v4 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX8-NEXT: v_max_f16_sdwa v3, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_min_f16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v4, v5, v5 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX8-NEXT: v_min_f16_e32 v2, v2, v4 -; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: v_min_f16_e32 v0, v0, v3 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v8 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v7 +; GFX8-NEXT: v_or_b32_e32 v2, v2, v6 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimumnum_v6f16: @@ -2113,34 +2113,34 @@ define <8 x half> @v_minimumnum_v8f16(<8 x half> %x, <8 x half> %y) { ; GFX8-LABEL: v_minimumnum_v8f16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_max_f16_sdwa v8, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_e32 v4, v4, v4 -; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_max_f16_sdwa v8, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v9, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX8-NEXT: v_min_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_f16_e32 v0, v0, v4 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v8 -; GFX8-NEXT: v_max_f16_sdwa v4, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v9, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v10, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_sdwa v9, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v10, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v11, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_min_f16_sdwa v10, v11, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_sdwa v11, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_sdwa v12, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_max_f16_e32 v7, v7, v7 +; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 +; GFX8-NEXT: v_max_f16_e32 v6, v6, v6 +; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 ; GFX8-NEXT: v_max_f16_e32 v5, v5, v5 ; GFX8-NEXT: v_max_f16_e32 v1, v1, v1 -; GFX8-NEXT: v_min_f16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_max_f16_e32 v4, v4, v4 +; GFX8-NEXT: v_max_f16_e32 v0, v0, v0 +; GFX8-NEXT: v_min_f16_sdwa v11, v12, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_min_f16_e32 v3, v3, v7 +; GFX8-NEXT: v_min_f16_e32 v2, v2, v6 ; GFX8-NEXT: v_min_f16_e32 v1, v1, v5 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 -; GFX8-NEXT: v_max_f16_sdwa v4, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_min_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v5, v6, v6 -; GFX8-NEXT: v_max_f16_e32 v2, v2, v2 -; GFX8-NEXT: v_min_f16_e32 v2, v2, v5 -; GFX8-NEXT: v_or_b32_e32 v2, v2, v4 -; GFX8-NEXT: v_max_f16_sdwa v4, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_max_f16_sdwa v5, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX8-NEXT: v_min_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_max_f16_e32 v5, v7, v7 -; GFX8-NEXT: v_max_f16_e32 v3, v3, v3 -; GFX8-NEXT: v_min_f16_e32 v3, v3, v5 -; GFX8-NEXT: v_or_b32_e32 v3, v3, v4 +; GFX8-NEXT: v_min_f16_e32 v0, v0, v4 +; GFX8-NEXT: v_or_b32_e32 v0, v0, v11 +; GFX8-NEXT: v_or_b32_e32 v1, v1, v10 +; GFX8-NEXT: v_or_b32_e32 v2, v2, v9 +; GFX8-NEXT: v_or_b32_e32 v3, v3, v8 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_minimumnum_v8f16: diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll index 73f3d4c037ad..774a22fb907d 100644 --- a/llvm/test/CodeGen/AMDGPU/minmax.ll +++ b/llvm/test/CodeGen/AMDGPU/minmax.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12 %s define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-LABEL: test_minmax_i32: @@ -8,6 +10,16 @@ define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b) %sminmax = call i32 @llvm.smin.i32(i32 %smax, i32 %c) ret i32 %sminmax @@ -45,6 +57,16 @@ define i32 @test_minmax_commuted_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_commuted_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b) %sminmax = call i32 @llvm.smin.i32(i32 %c, i32 %smax) ret i32 %sminmax @@ -56,6 +78,16 @@ define i32 @test_maxmin_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b) %smaxmin = call i32 @llvm.smax.i32(i32 %smin, i32 %c) ret i32 %smaxmin @@ -67,6 +99,16 @@ define i32 @test_maxmin_commuted_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_commuted_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b) %smaxmin = call i32 @llvm.smax.i32(i32 %c, i32 %smin) ret i32 %smaxmin @@ -79,6 +121,17 @@ define void @test_smed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) { ; GFX11-NEXT: v_med3_i32 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_smed3_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_i32 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call i32 @llvm.smin.i32(i32 %x, i32 %y) %tmp1 = call i32 @llvm.smax.i32(i32 %x, i32 %y) %tmp2 = call i32 @llvm.smin.i32(i32 %tmp1, i32 %z) @@ -93,6 +146,16 @@ define i32 @test_minmax_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b) %uminmax = call i32 @llvm.umin.i32(i32 %umax, i32 %c) ret i32 %uminmax @@ -130,6 +193,16 @@ define i32 @test_minmax_commuted_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_commuted_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b) %uminmax = call i32 @llvm.umin.i32(i32 %c, i32 %umax) ret i32 %uminmax @@ -141,6 +214,16 @@ define i32 @test_maxmin_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b) %umaxmin = call i32 @llvm.umax.i32(i32 %umin, i32 %c) ret i32 %umaxmin @@ -152,6 +235,16 @@ define i32 @test_maxmin_commuted_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_commuted_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b) %umaxmin = call i32 @llvm.umax.i32(i32 %c, i32 %umin) ret i32 %umaxmin @@ -164,6 +257,17 @@ define void @test_umed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) { ; GFX11-NEXT: v_med3_u32 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_umed3_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_u32 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call i32 @llvm.umin.i32(i32 %x, i32 %y) %tmp1 = call i32 @llvm.umax.i32(i32 %x, i32 %y) %tmp2 = call i32 @llvm.umin.i32(i32 %tmp1, i32 %z) @@ -173,44 +277,88 @@ define void @test_umed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) { } define float @test_minmax_f32_ieee_true(float %a, float %b, float %c) { -; SDAG-LABEL: test_minmax_f32_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; SDAG-NEXT: v_max_f32_e32 v2, v2, v2 -; SDAG-NEXT: v_maxmin_f32 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_minmax_f32_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] ; -; GISEL-LABEL: test_minmax_f32_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GISEL-NEXT: v_max_f32_e32 v2, v2, v2 -; GISEL-NEXT: v_maxmin_f32 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; GISEL-GFX11-LABEL: test_minmax_f32_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_minmax_f32_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_minmax_f32_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %max = call float @llvm.maxnum.f32(float %a, float %b) %minmax = call float @llvm.minnum.f32(float %max, float %c) ret float %minmax } define amdgpu_ps void @s_test_minmax_f32_ieee_false(float inreg %a, float inreg %b, float inreg %c, ptr addrspace(1) inreg %out) { -; SDAG-LABEL: s_test_minmax_f32_ieee_false: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; SDAG-NEXT: s_mov_b32 s5, s4 -; SDAG-NEXT: s_mov_b32 s4, s3 -; SDAG-NEXT: v_maxmin_f32 v0, s0, s1, v0 -; SDAG-NEXT: global_store_b32 v1, v0, s[4:5] -; SDAG-NEXT: s_endpgm +; SDAG-GFX11-LABEL: s_test_minmax_f32_ieee_false: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX11-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX11-NEXT: v_maxmin_f32 v0, s0, s1, v0 +; SDAG-GFX11-NEXT: global_store_b32 v1, v0, s[4:5] +; SDAG-GFX11-NEXT: s_endpgm ; -; GISEL-LABEL: s_test_minmax_f32_ieee_false: -; GISEL: ; %bb.0: -; GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; GISEL-NEXT: s_mov_b32 s6, s3 -; GISEL-NEXT: s_mov_b32 s7, s4 -; GISEL-NEXT: v_maxmin_f32 v0, s0, s1, v0 -; GISEL-NEXT: global_store_b32 v1, v0, s[6:7] -; GISEL-NEXT: s_endpgm +; GISEL-GFX11-LABEL: s_test_minmax_f32_ieee_false: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX11-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX11-NEXT: v_maxmin_f32 v0, s0, s1, v0 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[6:7] +; GISEL-GFX11-NEXT: s_endpgm +; +; SDAG-GFX12-LABEL: s_test_minmax_f32_ieee_false: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX12-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX12-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, s0, s1, v0 +; SDAG-GFX12-NEXT: global_store_b32 v1, v0, s[4:5] +; SDAG-GFX12-NEXT: s_endpgm +; +; GISEL-GFX12-LABEL: s_test_minmax_f32_ieee_false: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_max_num_f32 s0, s0, s1 +; GISEL-GFX12-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX12-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX12-NEXT: s_min_num_f32 s0, s0, s2 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX12-NEXT: global_store_b32 v1, v0, s[6:7] +; GISEL-GFX12-NEXT: s_endpgm %smax = call float @llvm.maxnum.f32(float %a, float %b) %sminmax = call float @llvm.minnum.f32(float %smax, float %c) store float %sminmax, ptr addrspace(1) %out @@ -222,27 +370,56 @@ define amdgpu_ps float @test_minmax_commuted_f32_ieee_false(float %a, float %b, ; GFX11: ; %bb.0: ; GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_minmax_commuted_f32_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %max = call float @llvm.maxnum.f32(float %a, float %b) %minmax = call float @llvm.minnum.f32(float %c, float %max) ret float %minmax } define float @test_maxmin_f32_ieee_true(float %a, float %b, float %c) { -; SDAG-LABEL: test_maxmin_f32_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; SDAG-NEXT: v_max_f32_e32 v2, v2, v2 -; SDAG-NEXT: v_minmax_f32 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_maxmin_f32_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] ; -; GISEL-LABEL: test_maxmin_f32_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GISEL-NEXT: v_max_f32_e32 v2, v2, v2 -; GISEL-NEXT: v_minmax_f32 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; GISEL-GFX11-LABEL: test_maxmin_f32_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_maxmin_f32_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_maxmin_f32_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %min = call float @llvm.minnum.f32(float %a, float %b) %maxmin = call float @llvm.maxnum.f32(float %min, float %c) ret float %maxmin @@ -253,6 +430,11 @@ define amdgpu_ps float @test_maxmin_commuted_f32_ieee_false(float %a, float %b, ; GFX11: ; %bb.0: ; GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_maxmin_commuted_f32_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %min = call float @llvm.minnum.f32(float %a, float %b) %maxmin = call float @llvm.maxnum.f32(float %c, float %min) ret float %maxmin @@ -265,6 +447,17 @@ define void @test_med3_f32(ptr addrspace(1) %arg, float %x, float %y, float %z) ; GFX11-NEXT: v_med3_f32 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_med3_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_num_f32 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call float @llvm.minnum.f32(float %x, float %y) %tmp1 = call float @llvm.maxnum.f32(float %x, float %y) %tmp2 = call float @llvm.minnum.f32(float %tmp1, float %z) @@ -278,29 +471,54 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) { ; GFX11: ; %bb.0: ; GFX11-NEXT: v_maxmin_f16 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_minmax_f16_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maxmin_num_f16 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %max = call half @llvm.maxnum.f16(half %a, half %b) %minmax = call half @llvm.minnum.f16(half %max, half %c) ret half %minmax } define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b, half inreg %c, ptr addrspace(1) inreg %out) { -; SDAG-LABEL: s_test_minmax_f16_ieee_false: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; SDAG-NEXT: s_mov_b32 s5, s4 -; SDAG-NEXT: s_mov_b32 s4, s3 -; SDAG-NEXT: v_maxmin_f16 v0, s0, s1, v0 -; SDAG-NEXT: global_store_b16 v1, v0, s[4:5] -; SDAG-NEXT: s_endpgm +; SDAG-GFX11-LABEL: s_test_minmax_f16_ieee_false: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX11-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX11-NEXT: v_maxmin_f16 v0, s0, s1, v0 +; SDAG-GFX11-NEXT: global_store_b16 v1, v0, s[4:5] +; SDAG-GFX11-NEXT: s_endpgm ; -; GISEL-LABEL: s_test_minmax_f16_ieee_false: -; GISEL: ; %bb.0: -; GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; GISEL-NEXT: s_mov_b32 s6, s3 -; GISEL-NEXT: s_mov_b32 s7, s4 -; GISEL-NEXT: v_maxmin_f16 v0, s0, s1, v0 -; GISEL-NEXT: global_store_b16 v1, v0, s[6:7] -; GISEL-NEXT: s_endpgm +; GISEL-GFX11-LABEL: s_test_minmax_f16_ieee_false: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX11-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX11-NEXT: v_maxmin_f16 v0, s0, s1, v0 +; GISEL-GFX11-NEXT: global_store_b16 v1, v0, s[6:7] +; GISEL-GFX11-NEXT: s_endpgm +; +; SDAG-GFX12-LABEL: s_test_minmax_f16_ieee_false: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX12-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX12-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX12-NEXT: v_maxmin_num_f16 v0, s0, s1, v0 +; SDAG-GFX12-NEXT: global_store_b16 v1, v0, s[4:5] +; SDAG-GFX12-NEXT: s_endpgm +; +; GISEL-GFX12-LABEL: s_test_minmax_f16_ieee_false: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_max_num_f16 s0, s0, s1 +; GISEL-GFX12-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX12-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX12-NEXT: s_min_num_f16 s0, s0, s2 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX12-NEXT: global_store_b16 v1, v0, s[6:7] +; GISEL-GFX12-NEXT: s_endpgm %smax = call half @llvm.maxnum.f16(half %a, half %b) %sminmax = call half @llvm.minnum.f16(half %smax, half %c) store half %sminmax, ptr addrspace(1) %out @@ -308,23 +526,49 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b } define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) { -; SDAG-LABEL: test_minmax_commuted_f16_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_max_f16_e32 v1, v1, v1 -; SDAG-NEXT: v_max_f16_e32 v0, v0, v0 -; SDAG-NEXT: v_max_f16_e32 v2, v2, v2 -; SDAG-NEXT: v_maxmin_f16 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GISEL-LABEL: test_minmax_commuted_f16_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_max_f16_e32 v0, v0, v0 -; GISEL-NEXT: v_max_f16_e32 v1, v1, v1 -; GISEL-NEXT: v_max_f16_e32 v2, v2, v2 -; GISEL-NEXT: v_maxmin_f16 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_minmax_commuted_f16_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; SDAG-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_maxmin_f16 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX11-LABEL: test_minmax_commuted_f16_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; GISEL-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_maxmin_f16 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_minmax_commuted_f16_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_maxmin_num_f16 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_minmax_commuted_f16_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_maxmin_num_f16 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %max = call half @llvm.maxnum.f16(half %a, half %b) %minmax = call half @llvm.minnum.f16(half %c, half %max) ret half %minmax @@ -335,29 +579,60 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) { ; GFX11: ; %bb.0: ; GFX11-NEXT: v_minmax_f16 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_maxmin_f16_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_minmax_num_f16 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %min = call half @llvm.minnum.f16(half %a, half %b) %maxmin = call half @llvm.maxnum.f16(half %min, half %c) ret half %maxmin } define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) { -; SDAG-LABEL: test_maxmin_commuted_f16_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_max_f16_e32 v1, v1, v1 -; SDAG-NEXT: v_max_f16_e32 v0, v0, v0 -; SDAG-NEXT: v_max_f16_e32 v2, v2, v2 -; SDAG-NEXT: v_minmax_f16 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GISEL-LABEL: test_maxmin_commuted_f16_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_max_f16_e32 v0, v0, v0 -; GISEL-NEXT: v_max_f16_e32 v1, v1, v1 -; GISEL-NEXT: v_max_f16_e32 v2, v2, v2 -; GISEL-NEXT: v_minmax_f16 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_maxmin_commuted_f16_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; SDAG-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_minmax_f16 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX11-LABEL: test_maxmin_commuted_f16_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; GISEL-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_minmax_f16 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_maxmin_commuted_f16_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_minmax_num_f16 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_maxmin_commuted_f16_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_minmax_num_f16 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %min = call half @llvm.minnum.f16(half %a, half %b) %maxmin = call half @llvm.maxnum.f16(half %c, half %min) ret half %maxmin @@ -370,6 +645,17 @@ define void @test_med3_f16(ptr addrspace(1) %arg, half %x, half %y, half %z) #0 ; GFX11-NEXT: v_med3_f16 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b16 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_med3_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_num_f16 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b16 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call half @llvm.minnum.f16(half %x, half %y) %tmp1 = call half @llvm.maxnum.f16(half %x, half %y) %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %z) diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll new file mode 100644 index 000000000000..a9b8663a48de --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll @@ -0,0 +1,120 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 %s -o - | FileCheck %s --check-prefixes=GFX942 +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 %s -o - | FileCheck %s --check-prefixes=GFX908 + +define amdgpu_kernel void @matmul_kernel(i32 %a0, i32 %a1) { +; GFX942-LABEL: matmul_kernel: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; GFX942-NEXT: v_mov_b32_e32 v1, 0 +; GFX942-NEXT: s_mov_b32 s2, 0 +; GFX942-NEXT: v_accvgpr_write_b32 a0, v1 +; GFX942-NEXT: s_mov_b32 s3, 0 +; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_cmp_lg_u32 s0, 0 +; GFX942-NEXT: s_cselect_b64 s[0:1], -1, 0 +; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX942-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0 +; GFX942-NEXT: s_branch .LBB0_2 +; GFX942-NEXT: .LBB0_1: ; %bb2 +; GFX942-NEXT: ; in Loop: Header=BB0_2 Depth=1 +; GFX942-NEXT: s_or_b32 s4, s3, 1 +; GFX942-NEXT: s_ashr_i32 s5, s3, 31 +; GFX942-NEXT: s_mov_b32 s3, s2 +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX942-NEXT: v_accvgpr_read_b32 v0, a0 +; GFX942-NEXT: v_mov_b32_e32 v2, v1 +; GFX942-NEXT: v_mov_b32_e32 v3, v1 +; GFX942-NEXT: v_accvgpr_write_b32 a0, v0 +; GFX942-NEXT: v_accvgpr_write_b32 a1, v1 +; GFX942-NEXT: v_accvgpr_write_b32 a2, v2 +; GFX942-NEXT: v_accvgpr_write_b32 a3, v3 +; GFX942-NEXT: s_and_b32 s3, s5, s4 +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_mfma_f32_16x16x16_f16 a[0:3], v[4:5], v[4:5], a[0:3] +; GFX942-NEXT: s_cbranch_execz .LBB0_4 +; GFX942-NEXT: .LBB0_2: ; %bb +; GFX942-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-NEXT: s_and_b64 vcc, exec, s[0:1] +; GFX942-NEXT: s_cbranch_vccz .LBB0_1 +; GFX942-NEXT: ; %bb.3: +; GFX942-NEXT: ; implicit-def: $sgpr3 +; GFX942-NEXT: .LBB0_4: ; %common.ret +; GFX942-NEXT: s_endpgm +; +; GFX908-LABEL: matmul_kernel: +; GFX908: ; %bb.0: ; %entry +; GFX908-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX908-NEXT: v_mov_b32_e32 v1, 0 +; GFX908-NEXT: s_mov_b32 s2, 0 +; GFX908-NEXT: s_mov_b32 s3, 0 +; GFX908-NEXT: v_accvgpr_write_b32 a0, v1 +; GFX908-NEXT: s_waitcnt lgkmcnt(0) +; GFX908-NEXT: s_cmp_lg_u32 s0, 0 +; GFX908-NEXT: s_cselect_b64 s[0:1], -1, 0 +; GFX908-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX908-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0 +; GFX908-NEXT: s_branch .LBB0_2 +; GFX908-NEXT: .LBB0_1: ; %bb2 +; GFX908-NEXT: ; in Loop: Header=BB0_2 Depth=1 +; GFX908-NEXT: s_or_b32 s4, s3, 1 +; GFX908-NEXT: s_ashr_i32 s5, s3, 31 +; GFX908-NEXT: s_mov_b32 s3, s2 +; GFX908-NEXT: s_nop 3 +; GFX908-NEXT: v_accvgpr_read_b32 v0, a0 +; GFX908-NEXT: v_mov_b32_e32 v5, s3 +; GFX908-NEXT: v_mov_b32_e32 v4, s2 +; GFX908-NEXT: v_mov_b32_e32 v2, v1 +; GFX908-NEXT: v_mov_b32_e32 v3, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a0, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a1, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a2, v2 +; GFX908-NEXT: v_accvgpr_write_b32 a3, v3 +; GFX908-NEXT: s_and_b32 s3, s5, s4 +; GFX908-NEXT: v_mfma_f32_16x16x16f16 a[0:3], v[4:5], v[4:5], a[0:3] +; GFX908-NEXT: s_cbranch_execz .LBB0_4 +; GFX908-NEXT: .LBB0_2: ; %bb +; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX908-NEXT: s_and_b64 vcc, exec, s[0:1] +; GFX908-NEXT: s_cbranch_vccz .LBB0_1 +; GFX908-NEXT: ; %bb.3: +; GFX908-NEXT: ; implicit-def: $sgpr3 +; GFX908-NEXT: .LBB0_4: ; %common.ret +; GFX908-NEXT: s_endpgm +entry: + br label %bb + +bb: + %i = phi { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } [ %i10, %bb2 ], [ zeroinitializer, %entry ] + %i1 = phi i32 [ %i5, %bb2 ], [ 0, %entry ] + %c0 = icmp ne i32 %a0, 0 + br i1 %c0, label %bb2, label %bb11 + +bb2: + %i3 = or i32 %i1, 1 + %i4 = icmp slt i32 %i1, 0 + %i5 = select i1 %i4, i32 %i3, i32 0 + %i6 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 123 + %i7 = insertelement <4 x float> zeroinitializer, float %i6, i32 0 + %i8 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i7, i32 0, i32 0, i32 0) + %i9 = extractelement <4 x float> %i8, i32 0 + %i10 = insertvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } zeroinitializer, float %i9, 123 + br label %bb + +bb11: + %c1 = icmp ne i32 %a1, 0 + br i1 %c1, label %bb12, label %common.ret + +common.ret: + ret void + +bb12: + %i13 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 0 + %i14 = insertelement <4 x float> zeroinitializer, float %i13, i32 0 + %i15 = insertelement <4 x float> %i14, float 0.000000e+00, i32 0 + %i16 = insertelement <4 x float> %i15, float 0.000000e+00, i32 0 + br label %common.ret +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half>, <4 x half>, <4 x float>, i32 immarg, i32 immarg, i32 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir new file mode 100644 index 000000000000..5c83170563e5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir @@ -0,0 +1,235 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE + +... +--- +name: test +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: test + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $sgpr4_sgpr5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; CHECK-NEXT: S_BITCMP1_B32 killed [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; CHECK-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc + ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B32_e32_]] + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec + ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_CNDMASK_B32_e64_]], 1, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %24, %bb.3 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %11, %bb.3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[PHI]] + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 + ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[PHI1]], 1, implicit-def dead $scc + ; CHECK-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[PHI1]], 31, implicit-def dead $scc + ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 killed [[S_ASHR_I32_]], killed [[S_OR_B32_]], implicit-def dead $scc + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:areg_128_align2 = COPY [[REG_SEQUENCE]] + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY4]], [[COPY4]], killed [[COPY5]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_32 = PHI [[DEF]], %bb.1, [[S_AND_B32_]], %bb.2 + ; CHECK-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.1, [[V_MFMA_F32_16X16X16F16_e64_]].sub0, %bb.2 + ; CHECK-NEXT: [[PHI4:%[0-9]+]]:sreg_64_xexec = PHI [[S_MOV_B64_]], %bb.1, [[S_MOV_B64_1]], %bb.2 + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[PHI4]], implicit $exec + ; CHECK-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_CNDMASK_B32_e64_1]], 1, implicit $exec + ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc + ; CHECK-NEXT: S_BRANCH %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: S_ENDPGM 0 + ; + ; COALESCE-LABEL: name: test + ; COALESCE: bb.0: + ; COALESCE-NEXT: successors: %bb.1(0x80000000) + ; COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0 + ; COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc + ; COALESCE-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec + ; COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec + ; COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec + ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.1: + ; COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1 + ; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc + ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc + ; COALESCE-NEXT: S_BRANCH %bb.2 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.2: + ; COALESCE-NEXT: successors: %bb.3(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_MOV_B32_1]], 1, implicit-def dead $scc + ; COALESCE-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[S_MOV_B32_1]], 31, implicit-def dead $scc + ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_ASHR_I32_]], [[S_OR_B32_]], implicit-def dead $scc + ; COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]] + ; COALESCE-NEXT: [[COPY2:%[0-9]+]]:areg_128_align2 = COPY [[V_MOV_B32_e32_]] + ; COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.3: + ; COALESCE-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec + ; COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec + ; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc + ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc + ; COALESCE-NEXT: S_BRANCH %bb.4 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.4: + ; COALESCE-NEXT: successors: %bb.5(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.5: + ; COALESCE-NEXT: S_ENDPGM 0 + ; + ; GFX908-COALESCE-LABEL: name: test + ; GFX908-COALESCE: bb.0: + ; GFX908-COALESCE-NEXT: successors: %bb.1(0x80000000) + ; GFX908-COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; GFX908-COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; GFX908-COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0 + ; GFX908-COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc + ; GFX908-COALESCE-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec + ; GFX908-COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec + ; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.1: + ; GFX908-COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1 + ; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc + ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc + ; GFX908-COALESCE-NEXT: S_BRANCH %bb.2 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.2: + ; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_MOV_B32_1]], 1, implicit-def dead $scc + ; GFX908-COALESCE-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[S_MOV_B32_1]], 31, implicit-def dead $scc + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_ASHR_I32_]], [[S_OR_B32_]], implicit-def dead $scc + ; GFX908-COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; GFX908-COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]] + ; GFX908-COALESCE-NEXT: [[COPY2:%[0-9]+]]:areg_128_align2 = COPY [[V_MOV_B32_e32_]] + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.3: + ; GFX908-COALESCE-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec + ; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec + ; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc + ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc + ; GFX908-COALESCE-NEXT: S_BRANCH %bb.4 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.4: + ; GFX908-COALESCE-NEXT: successors: %bb.5(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.5: + ; GFX908-COALESCE-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1 + liveins: $sgpr4_sgpr5 + + %0:sgpr_64(p4) = COPY $sgpr4_sgpr5 + %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + S_BITCMP1_B32 killed %1, 0, implicit-def $scc + %2:sgpr_32 = S_MOV_B32 0 + %3:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc + %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %5:sreg_32 = IMPLICIT_DEF + %6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec + %7:sreg_64_xexec = V_CMP_NE_U32_e64 %6, 1, implicit $exec + + bb.1: + successors: %bb.2, %bb.3 + + %8:vgpr_32 = PHI %4, %bb.0, %9, %bb.3 + %10:sreg_32 = PHI %2, %bb.0, %11, %bb.3 + %12:agpr_32 = COPY %8 + %13:sreg_64 = S_MOV_B64 -1 + $vcc = S_AND_B64 $exec, %7, implicit-def $scc + S_CBRANCH_VCCNZ %bb.3, implicit $vcc + S_BRANCH %bb.2 + + bb.2: + successors: %bb.3 + + %14:sreg_32 = S_OR_B32 %10, 1, implicit-def dead $scc + %15:sreg_32 = S_ASHR_I32 %10, 31, implicit-def dead $scc + %16:sreg_32 = S_AND_B32 killed %15, killed %14, implicit-def dead $scc + %17:vreg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3 + %18:sreg_64 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1 + %19:vreg_64_align2 = COPY %18 + %20:areg_128_align2 = COPY %17 + %21:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %19, %19, killed %20, 0, 0, 0, implicit $mode, implicit $exec + %22:vgpr_32 = COPY %21.sub0 + %23:sreg_64 = S_MOV_B64 0 + + bb.3: + successors: %bb.4, %bb.1 + + %11:sreg_32 = PHI %5, %bb.1, %16, %bb.2 + %24:agpr_32 = PHI %12, %bb.1, %21.sub0, %bb.2 + %25:sreg_64_xexec = PHI %13, %bb.1, %23, %bb.2 + %9:vgpr_32 = COPY %24 + %26:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %25, implicit $exec + %27:sreg_64_xexec = V_CMP_NE_U32_e64 %26, 1, implicit $exec + $vcc = S_AND_B64 $exec, %27, implicit-def $scc + S_CBRANCH_VCCNZ %bb.1, implicit $vcc + S_BRANCH %bb.4 + + bb.4: + successors: %bb.5 + + bb.5: + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir new file mode 100644 index 000000000000..49c0aaf9fb39 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir @@ -0,0 +1,182 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE + +... +--- +name: test +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: test + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $sgpr4_sgpr5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; CHECK-NEXT: S_BITCMP0_B32 killed [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_4:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_4]], %subreg.sub3 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_1:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_2:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_3:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_2]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_MFMA_F32_16X16X16F16_e64_3]].sub0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_]], %bb.1, [[V_MFMA_F32_16X16X16F16_e64_3]].sub0, %bb.2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI]] + ; CHECK-NEXT: [[V_CVT_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_PACK_B32_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_PACK_B32_F16_e64 0, killed [[V_CVT_F16_F32_e64_]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_PACK_B32_F16_e64_]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1 + ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3 + ; CHECK-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE2]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + ; CHECK-NEXT: S_ENDPGM 0 + ; + ; COALESCE-LABEL: name: test + ; COALESCE: bb.0: + ; COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0 + ; COALESCE-NEXT: S_BITCMP0_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.1: + ; COALESCE-NEXT: successors: %bb.3(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; COALESCE-NEXT: S_BRANCH %bb.3 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.2: + ; COALESCE-NEXT: successors: %bb.3(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]].sub0_sub1 + ; COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_1:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_2:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_2]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.3: + ; COALESCE-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; COALESCE-NEXT: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY2]], implicit $mode, implicit $exec + ; COALESCE-NEXT: undef [[V_PACK_B32_F16_e64_:%[0-9]+]].sub0:vreg_64_align2 = nofpexcept V_PACK_B32_F16_e64 0, [[V_CVT_F16_F32_e32_]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_PACK_B32_F16_e64_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[V_PACK_B32_F16_e64_]], [[S_MOV_B32_]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + ; COALESCE-NEXT: S_ENDPGM 0 + ; + ; GFX908-COALESCE-LABEL: name: test + ; GFX908-COALESCE: bb.0: + ; GFX908-COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; GFX908-COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; GFX908-COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0 + ; GFX908-COALESCE-NEXT: S_BITCMP0_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; GFX908-COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.1: + ; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; GFX908-COALESCE-NEXT: S_BRANCH %bb.3 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.2: + ; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub1:areg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_1]].sub0 + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub2:areg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_1]].sub0 + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub3:areg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_1]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]].sub0_sub1 + ; GFX908-COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_ACCVGPR_WRITE_B32_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_1:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_2:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_2]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.3: + ; GFX908-COALESCE-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; GFX908-COALESCE-NEXT: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY2]], implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: undef [[V_PACK_B32_F16_e64_:%[0-9]+]].sub0:vreg_64_align2 = nofpexcept V_PACK_B32_F16_e64 0, [[V_CVT_F16_F32_e32_]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_PACK_B32_F16_e64_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[V_PACK_B32_F16_e64_]], [[S_MOV_B32_]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + ; GFX908-COALESCE-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.2, %bb.1 + liveins: $sgpr4_sgpr5 + + %0:sgpr_64(p4) = COPY $sgpr4_sgpr5 + %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + %2:sgpr_32 = S_MOV_B32 0 + S_BITCMP0_B32 killed %1, 0, implicit-def $scc + S_CBRANCH_SCC0 %bb.2, implicit $scc + + bb.1: + successors: %bb.3 + + %3:sgpr_32 = COPY %2 + %4:vgpr_32 = COPY %3, implicit $exec + S_BRANCH %bb.3 + + bb.2: + successors: %bb.3 + + %5:sgpr_32 = S_MOV_B32 0 + %6:vgpr_32 = COPY %5 + %7:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %8:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %9:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %10:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %11:areg_128_align2 = REG_SEQUENCE %7, %subreg.sub0, %8, %subreg.sub1, %9, %subreg.sub2, %10, %subreg.sub3 + %12:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %5, %subreg.sub1 + %13:vreg_64_align2 = COPY %12 + %14:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %11, 0, 0, 0, implicit $mode, implicit $exec + %15:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %14, 0, 0, 0, implicit $mode, implicit $exec + %16:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %15, 0, 0, 0, implicit $mode, implicit $exec + %17:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %16, 0, 0, 0, implicit $mode, implicit $exec + %18:vgpr_32 = COPY %17.sub0 + %19:vgpr_32 = COPY %18 + + bb.3: + %20:vgpr_32 = PHI %4, %bb.1, %19, %bb.2 + %21:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, %20, 0, 0, implicit $mode, implicit $exec + %22:vgpr_32 = nofpexcept V_PACK_B32_F16_e64 0, killed %21, 0, %2, 0, 0, implicit $mode, implicit $exec + %23:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %24:vreg_64_align2 = REG_SEQUENCE %22, %subreg.sub0, killed %23, %subreg.sub1 + %25:sgpr_128 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1, %2, %subreg.sub2, %2, %subreg.sub3 + %26:vreg_64_align2 = COPY %24 + BUFFER_STORE_DWORDX2_OFFSET_exact killed %26, killed %25, %2, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll index 98d5f3097153..a2a0107a6f7d 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -1372,20 +1372,19 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v1, v0 ; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc ; GFX8-NEXT: s_movk_i32 s0, 0xf000 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v3 -; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v4, vcc +; GFX8-NEXT: v_add_u32_e32 v7, vcc, s0, v3 +; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v4, vcc ; GFX8-NEXT: s_movk_i32 s0, 0xf800 -; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[3:4] -; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[5:6] +; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[3:4] +; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[7:8] ; GFX8-NEXT: v_add_u32_e32 v9, vcc, s0, v3 ; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc ; GFX8-NEXT: flat_load_dwordx2 v[9:10], v[9:10] -; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0, v3 -; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 1, v4, vcc +; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v4 ; GFX8-NEXT: flat_load_dwordx2 v[3:4], v[3:4] ; GFX8-NEXT: s_waitcnt vmcnt(2) -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v5, v7 -; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v6, v8, vcc +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v7, v5 +; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc ; GFX8-NEXT: s_waitcnt vmcnt(1) ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v9, v0 ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc @@ -1416,32 +1415,32 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 7, v0 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff8000, v1 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff8000, v1 ; GFX9-NEXT: v_mov_b32_e32 v1, s35 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s34, v12 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s34, v10 ; GFX9-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 1, v1, vcc -; GFX9-NEXT: global_load_dwordx2 v[2:3], v[0:1], off -; GFX9-NEXT: global_load_dwordx2 v[6:7], v[4:5], off offset:-4096 ; GFX9-NEXT: s_movk_i32 s0, 0xf000 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: global_load_dwordx2 v[8:9], v[4:5], off -; GFX9-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc +; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off +; GFX9-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: global_load_dwordx2 v[8:9], v[2:3], off offset:2048 +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v7, vcc +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v3, vcc ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc -; GFX9-NEXT: global_store_dwordx2 v12, v[0:1], s[34:35] +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_store_dwordx2 v10, v[0:1], s[34:35] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: Offset64: @@ -1477,8 +1476,7 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off ; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 1, v1, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v1 ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off ; GFX10-NEXT: global_load_dwordx2 v[10:11], v[0:1], off @@ -1517,25 +1515,25 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 1, v1, vcc_lo -; GFX11-NEXT: global_load_b64 v[2:3], v[0:1], off -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0xfffff000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x2 -; GFX11-NEXT: global_load_b64 v[6:7], v[4:5], off offset:-4096 -; GFX11-NEXT: global_load_b64 v[4:5], v[4:5], off -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:2048 +; GFX11-NEXT: global_load_b64 v[4:5], v[2:3], off +; GFX11-NEXT: global_load_b64 v[6:7], v[0:1], off +; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off offset:2048 +; GFX11-NEXT: v_add_nc_u32_e32 v1, 1, v1 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v6, v2 -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v6 +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo +; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo ; GFX11-NEXT: global_store_b64 v8, v[0:1], s[34:35] ; GFX11-NEXT: s_endpgm entry: @@ -2408,18 +2406,17 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX8-NEXT: v_mov_b32_e32 v3, 3 ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0 -; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v2, vcc +; GFX8-NEXT: v_add_u32_e32 v3, vcc, v1, v0 +; GFX8-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GFX8-NEXT: s_movk_i32 s0, 0x800 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, s0, v0 -; GFX8-NEXT: v_addc_u32_e32 v4, vcc, -1, v6, vcc -; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0, v0 -; GFX8-NEXT: v_addc_u32_e32 v6, vcc, -1, v6, vcc -; GFX8-NEXT: flat_load_dwordx2 v[3:4], v[3:4] +; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v3 +; GFX8-NEXT: v_addc_u32_e32 v6, vcc, -1, v0, vcc +; GFX8-NEXT: v_add_u32_e32 v4, vcc, -1, v0 ; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[5:6] +; GFX8-NEXT: flat_load_dwordx2 v[3:4], v[3:4] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 -; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc +; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 +; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GFX8-NEXT: flat_store_dwordx2 v[1:2], v[3:4] ; GFX8-NEXT: s_endpgm ; @@ -2450,14 +2447,13 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX9-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc -; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:-2048 -; GFX9-NEXT: global_load_dwordx2 v[6:7], v[2:3], off +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0x1000, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off offset:-2048 +; GFX9-NEXT: global_load_dwordx2 v[6:7], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v5, vcc @@ -2490,15 +2486,14 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_add_co_u32 v1, s0, s34, v8 ; GFX10-NEXT: v_add_co_ci_u32_e64 v2, s0, s35, 0, s0 -; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v1, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v3 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v4, vcc_lo -; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0, v3 -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v4, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x800, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v1, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1 ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off -; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off +; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v4 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v5, vcc_lo @@ -2525,19 +2520,18 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX11-NEXT: v_add_co_u32 v1, s0, s34, v4 ; GFX11-NEXT: v_add_co_ci_u32_e64 v2, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v3, vcc_lo, v1, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v3 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v5, vcc_lo -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0, v3 -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0x1000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v1, vcc_lo +; GFX11-NEXT: v_add_nc_u32_e32 v1, -1, v1 ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:-2048 -; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off +; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off offset:-2048 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo ; GFX11-NEXT: global_store_b64 v4, v[0:1], s[34:35] ; GFX11-NEXT: s_endpgm entry: diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll index ba428df273db..a439f8df10a2 100644 --- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll +++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll @@ -3,32 +3,17 @@ ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s define amdgpu_cs float @v_s_exp_f32(float inreg %src) { -; GFX12-SDAG-LABEL: v_s_exp_f32: -; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_cmp_lt_f32 s0, 0xc2fc0000 -; GFX12-SDAG-NEXT: s_cselect_b32 s1, 0x42800000, 0 -; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) -; GFX12-SDAG-NEXT: s_add_f32 s0, s0, s1 -; GFX12-SDAG-NEXT: s_cselect_b32 s1, 0xffffffc0, 0 -; GFX12-SDAG-NEXT: v_s_exp_f32 s0, s0 -; GFX12-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_1) -; GFX12-SDAG-NEXT: v_ldexp_f32 v0, s0, s1 -; GFX12-SDAG-NEXT: ; return to shader part epilog -; -; GFX12-GISEL-LABEL: v_s_exp_f32: -; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_cmp_lt_f32 s0, 0xc2fc0000 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x42800000, 0 -; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) -; GFX12-GISEL-NEXT: s_add_f32 s0, s0, s1 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x1f800000, 1.0 -; GFX12-GISEL-NEXT: v_s_exp_f32 s0, s0 -; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) -; GFX12-GISEL-NEXT: s_mul_f32 s0, s0, s1 -; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX12-GISEL-NEXT: ; return to shader part epilog +; GFX12-LABEL: v_s_exp_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_cmp_lt_f32 s0, 0xc2fc0000 +; GFX12-NEXT: s_cselect_b32 s1, 0x42800000, 0 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) +; GFX12-NEXT: s_add_f32 s0, s0, s1 +; GFX12-NEXT: s_cselect_b32 s1, 0xffffffc0, 0 +; GFX12-NEXT: v_s_exp_f32 s0, s0 +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) +; GFX12-NEXT: v_ldexp_f32 v0, s0, s1 +; GFX12-NEXT: ; return to shader part epilog %result = call float @llvm.exp2.f32(float %src) ret float %result } @@ -88,16 +73,16 @@ define amdgpu_cs float @v_s_log_f32(float inreg %src) { ; GFX12-GISEL-LABEL: v_s_log_f32: ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: s_cmp_lt_f32 s0, 0x800000 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x4f800000, 1.0 -; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) -; GFX12-GISEL-NEXT: s_mul_f32 s0, s0, s1 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x42000000, 0 -; GFX12-GISEL-NEXT: v_s_log_f32 s0, s0 -; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) -; GFX12-GISEL-NEXT: s_sub_f32 s0, s0, s1 +; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX12-GISEL-NEXT: s_lshl_b32 s2, s1, 5 +; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX12-GISEL-NEXT: v_ldexp_f32 v0, s0, s2 +; GFX12-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0 +; GFX12-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1) +; GFX12-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0 ; GFX12-GISEL-NEXT: ; return to shader part epilog %result = call float @llvm.log2.f32(float %src) ret float %result @@ -322,19 +307,18 @@ define amdgpu_cs float @srcmods_abs_f32(float inreg %src) { ; ; GFX12-GISEL-LABEL: srcmods_abs_f32: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_bitset0_b32 s0, 31 +; GFX12-GISEL-NEXT: s_and_b32 s1, s0, 0x7fffffff ; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX12-GISEL-NEXT: s_cmp_lt_f32 s0, 0x800000 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x4f800000, 1.0 -; GFX12-GISEL-NEXT: s_mul_f32 s0, s0, s1 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x42000000, 0 -; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) -; GFX12-GISEL-NEXT: v_s_log_f32 s0, s0 -; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: s_sub_f32 s0, s0, s1 +; GFX12-GISEL-NEXT: s_cmp_lt_f32 s1, 0x800000 +; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0 +; GFX12-GISEL-NEXT: s_lshl_b32 s2, s1, 5 +; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX12-GISEL-NEXT: v_ldexp_f32 v0, |s0|, s2 +; GFX12-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX12-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) -; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0 ; GFX12-GISEL-NEXT: ; return to shader part epilog %abs = call float @llvm.fabs.f32(float %src) %result = call float @llvm.log2.f32(float %abs) @@ -362,19 +346,18 @@ define amdgpu_cs float @srcmods_neg_f32(float inreg %src) { ; ; GFX12-GISEL-LABEL: srcmods_neg_f32: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_xor_b32 s0, s0, 0x80000000 +; GFX12-GISEL-NEXT: s_xor_b32 s1, s0, 0x80000000 ; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX12-GISEL-NEXT: s_cmp_lt_f32 s0, 0x800000 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x4f800000, 1.0 -; GFX12-GISEL-NEXT: s_mul_f32 s0, s0, s1 -; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x42000000, 0 -; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) -; GFX12-GISEL-NEXT: v_s_log_f32 s0, s0 -; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: s_sub_f32 s0, s0, s1 +; GFX12-GISEL-NEXT: s_cmp_lt_f32 s1, 0x800000 +; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0 +; GFX12-GISEL-NEXT: s_lshl_b32 s2, s1, 5 +; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GFX12-GISEL-NEXT: v_ldexp_f32 v0, -s0, s2 +; GFX12-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX12-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX12-GISEL-NEXT: s_wait_alu 0xfffe -; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) -; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0 ; GFX12-GISEL-NEXT: ; return to shader part epilog %neg = fneg float %src %result = call float @llvm.log2.f32(float %neg) diff --git a/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir b/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir new file mode 100644 index 000000000000..3879f6dccf9d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir @@ -0,0 +1,85 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=register-coalescer -o - %s | FileCheck %s + +# This used to assert due to trying to rematerialize V_MOV_B64_PSEUDO +# at copy to $vgpr1. This would assert since this would clobber the +# live value in $vgpr0. + +--- +name: rematerialize_physreg_sub_def_already_live_at_def_assert +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_already_live_at_def_assert + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: $vgpr1 = COPY [[V_MOV_B]].sub1 + ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit killed $vgpr1 + %0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + %1:vgpr_32 = COPY %0.sub1 + $vgpr0 = V_MOV_B32_e32 0, implicit $exec + $vgpr1 = COPY %1 + SI_RETURN implicit $vgpr0, implicit killed $vgpr1 +... + +# Same as previous, except with an IMPLICIT_DEF +--- +name: rematerialize_physreg_sub_def_already_live_at_def_assert_implicit_def +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_already_live_at_def_assert_implicit_def + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: $vgpr1 = COPY [[DEF]].sub1 + ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit killed $vgpr1 + %0:vreg_64 = IMPLICIT_DEF + %1:vgpr_32 = COPY %0.sub1 + $vgpr0 = V_MOV_B32_e32 0, implicit $exec + $vgpr1 = COPY %1 + SI_RETURN implicit $vgpr0, implicit killed $vgpr1 +... + +--- +name: rematerialize_physreg_sub_def_no_live_sub_def_0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_no_live_sub_def_0 + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1 + ; CHECK-NEXT: SI_RETURN implicit killed $vgpr1 + %0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + %1:vgpr_32 = COPY %0.sub1 + $vgpr1 = COPY %1 + SI_RETURN implicit killed $vgpr1 +... + +--- +name: rematerialize_physreg_sub_def_no_live_sub_def_1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_no_live_sub_def_1 + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $vgpr1_vgpr2 = V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1 + ; CHECK-NEXT: SI_RETURN implicit killed $vgpr1 + %0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + %1:vgpr_32 = COPY %0.sub0 + $vgpr1 = COPY %1 + SI_RETURN implicit killed $vgpr1 +... diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index 3e8768c98b5c..96dd6276f7e3 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -1065,100 +1065,37 @@ define amdgpu_kernel void @s_test_sdiv24_48(ptr addrspace(1) %out, i48 %x, i48 % ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv24_48: -; GCN-IR: ; %bb.0: ; %_udiv-special-cases -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb -; GCN-IR-NEXT: s_mov_b32 s15, 0 -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_sext_i32_i16 s1, s1 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 24 -; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 -; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 -; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 24 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[0:1], 16 -; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31 -; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 -; GCN-IR-NEXT: s_mov_b32 s1, s0 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[2:3], 16 -; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 -; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1] -; GCN-IR-NEXT: s_mov_b32 s3, s2 -; GCN-IR-NEXT: s_sub_u32 s12, s6, s0 -; GCN-IR-NEXT: s_subb_u32 s13, s7, s0 -; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3] -; GCN-IR-NEXT: s_sub_u32 s6, s6, s2 -; GCN-IR-NEXT: s_subb_u32 s7, s7, s2 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[12:13], 0 -; GCN-IR-NEXT: s_flbit_i32_b64 s14, s[6:7] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] -; GCN-IR-NEXT: s_flbit_i32_b64 s20, s[12:13] -; GCN-IR-NEXT: s_sub_u32 s16, s14, s20 -; GCN-IR-NEXT: s_subb_u32 s17, 0, 0 -; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[16:17], 63 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63 -; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19] -; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec -; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13 -; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12 -; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[22:23] -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 -; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: s_add_u32 s18, s16, 1 -; GCN-IR-NEXT: s_addc_u32 s19, s17, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0 -; GCN-IR-NEXT: s_sub_i32 s16, 63, s16 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16 -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 -; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s18 -; GCN-IR-NEXT: s_add_u32 s18, s6, -1 -; GCN-IR-NEXT: s_addc_u32 s19, s7, -1 -; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] -; GCN-IR-NEXT: s_add_u32 s12, s8, s20 -; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 -; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 -; GCN-IR-NEXT: s_mov_b32 s9, 0 -; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while -; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 -; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11] -; GCN-IR-NEXT: s_sub_u32 s8, s18, s16 -; GCN-IR-NEXT: s_subb_u32 s8, s19, s17 -; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 -; GCN-IR-NEXT: s_mov_b32 s15, s14 -; GCN-IR-NEXT: s_and_b32 s8, s14, 1 -; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7] -; GCN-IR-NEXT: s_sub_u32 s16, s16, s14 -; GCN-IR-NEXT: s_subb_u32 s17, s17, s15 -; GCN-IR-NEXT: s_add_u32 s12, s12, 1 -; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0 -; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3 -; GCN-IR-NEXT: .LBB9_4: ; %Flow4 -; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7] -; GCN-IR-NEXT: .LBB9_5: ; %udiv-end -; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] -; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1] -; GCN-IR-NEXT: s_sub_u32 s0, s2, s0 -; GCN-IR-NEXT: s_subb_u32 s1, s3, s1 +; GCN-IR: ; %bb.0: +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4 -; GCN-IR-NEXT: s_waitcnt expcnt(0) -; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: s_sext_i32_i16 s1, s9 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 +; GCN-IR-NEXT: v_alignbit_b32 v0, s1, v0, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: s_sext_i32_i16 s0, s3 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s2 +; GCN-IR-NEXT: v_alignbit_b32 v2, s0, v2, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v4 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, v3 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: s_endpgm %1 = ashr i48 %x, 24 %2 = ashr i48 %y, 24 diff --git a/llvm/test/CodeGen/AMDGPU/smed3.ll b/llvm/test/CodeGen/AMDGPU/smed3.ll index e0d0ddce208c..ddf6297bc27a 100644 --- a/llvm/test/CodeGen/AMDGPU/smed3.ll +++ b/llvm/test/CodeGen/AMDGPU/smed3.ll @@ -1,6 +1,8 @@ ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s declare i32 @llvm.amdgcn.workitem.id.x() #0 @@ -98,6 +100,8 @@ declare i64 @llvm.smin.i64(i64, i64) ; VI: v_max_i16_e32 [[MAX:v[0-9]]], 12, {{v[0-9]}} ; VI: v_min_i16_e32 {{v[0-9]}}, 17, [[MAX]] ; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +; GFX11-TRUE16: v_med3_i16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, 12, 17 +; GFX11-FAKE16: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 define amdgpu_kernel void @v_test_smed3_r_i_i_i16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr i16, ptr addrspace(1) %aptr, i32 %tid @@ -686,6 +690,8 @@ bb: ; VI: v_max_i16 ; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_i16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_smed3_i16_pat_0(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -707,6 +713,8 @@ bb: ; GCN-LABEL: {{^}}v_test_smed3_i16_pat_1: ; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_i16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_smed3_i16_pat_1(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index cb8f82db92bb..23364e860d15 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -1188,109 +1188,39 @@ define amdgpu_kernel void @s_test_srem24_48(ptr addrspace(1) %out, i48 %x, i48 % ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem24_48: -; GCN-IR: ; %bb.0: ; %_udiv-special-cases -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb -; GCN-IR-NEXT: s_mov_b32 s13, 0 +; GCN-IR: ; %bb.0: +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_sext_i32_i16 s1, s1 ; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 24 -; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 24 -; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 -; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], 16 -; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[0:1], 16 -; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31 -; GCN-IR-NEXT: s_mov_b32 s1, s0 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 16 -; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] -; GCN-IR-NEXT: s_sub_u32 s2, s2, s0 -; GCN-IR-NEXT: s_subb_u32 s3, s3, s0 -; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31 -; GCN-IR-NEXT: s_mov_b32 s11, s10 -; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[10:11] -; GCN-IR-NEXT: s_sub_u32 s6, s6, s10 -; GCN-IR-NEXT: s_subb_u32 s7, s7, s10 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0 -; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[6:7] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] -; GCN-IR-NEXT: s_flbit_i32_b64 s20, s[2:3] -; GCN-IR-NEXT: s_sub_u32 s14, s12, s20 -; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 -; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[14:15], 63 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[14:15], 63 -; GCN-IR-NEXT: s_or_b64 s[16:17], s[10:11], s[16:17] -; GCN-IR-NEXT: s_and_b64 s[10:11], s[16:17], exec -; GCN-IR-NEXT: s_cselect_b32 s11, 0, s3 -; GCN-IR-NEXT: s_cselect_b32 s10, 0, s2 -; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 -; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: s_add_u32 s16, s14, 1 -; GCN-IR-NEXT: s_addc_u32 s17, s15, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[16:17], 0 -; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[2:3], s14 -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 -; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s16 -; GCN-IR-NEXT: s_add_u32 s18, s6, -1 -; GCN-IR-NEXT: s_addc_u32 s19, s7, -1 -; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13] -; GCN-IR-NEXT: s_add_u32 s12, s8, s20 -; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 -; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 -; GCN-IR-NEXT: s_mov_b32 s9, 0 -; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while -; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 -; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[8:9] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[16:17], s[10:11] -; GCN-IR-NEXT: s_sub_u32 s8, s18, s14 -; GCN-IR-NEXT: s_subb_u32 s8, s19, s15 -; GCN-IR-NEXT: s_ashr_i32 s16, s8, 31 -; GCN-IR-NEXT: s_mov_b32 s17, s16 -; GCN-IR-NEXT: s_and_b32 s8, s16, 1 -; GCN-IR-NEXT: s_and_b64 s[16:17], s[16:17], s[6:7] -; GCN-IR-NEXT: s_sub_u32 s14, s14, s16 -; GCN-IR-NEXT: s_subb_u32 s15, s15, s17 -; GCN-IR-NEXT: s_add_u32 s12, s12, 1 -; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0 -; GCN-IR-NEXT: s_mov_b64 s[16:17], s[8:9] -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3 -; GCN-IR-NEXT: .LBB9_4: ; %Flow4 -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] -; GCN-IR-NEXT: .LBB9_5: ; %udiv-end -; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 -; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, v0 -; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x9 -; GCN-IR-NEXT: s_mul_i32 s4, s6, s11 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v0 -; GCN-IR-NEXT: s_mul_i32 s4, s7, s10 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v0 -; GCN-IR-NEXT: s_mul_i32 s4, s6, s10 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s4 -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s2, v1 -; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc -; GCN-IR-NEXT: v_xor_b32_e32 v1, s0, v1 -; GCN-IR-NEXT: v_xor_b32_e32 v0, s1, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 -; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1 -; GCN-IR-NEXT: s_mov_b32 s15, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s14, -1 -; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v0, v2, vcc -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: buffer_store_short v0, off, s[12:15], 0 offset:4 -; GCN-IR-NEXT: buffer_store_dword v1, off, s[12:15], 0 +; GCN-IR-NEXT: s_sext_i32_i16 s5, s5 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 +; GCN-IR-NEXT: v_alignbit_b32 v0, s5, v0, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s2 +; GCN-IR-NEXT: v_alignbit_b32 v2, s3, v2, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-IR-NEXT: v_xor_b32_e32 v5, v2, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 30, v5 +; GCN-IR-NEXT: v_or_b32_e32 v5, 1, v5 +; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-IR-NEXT: v_mad_f32 v3, -v4, v1, v3 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: s_endpgm %1 = ashr i48 %x, 24 %2 = ashr i48 %y, 24 diff --git a/llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll b/llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll new file mode 100644 index 000000000000..f52f1164f2ba --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll @@ -0,0 +1,193 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s + +; Reduce a 64-bit sub by a constant if we know the low 32-bits are all +; zero. + +; sub i64:x, K if computeTrailingZeros(K) >= 32 +; => build_pair (sub x.hi, K.hi), x.lo + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0xfffc0000 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_1(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 4294967296 ; (1 << 32) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_2(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -2 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 8589934592 ; (1 << 33) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_3(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0x80000000 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_4(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0xfffc0000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_1(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 4294967296 ; (1 << 32) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_2(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -2, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 8589934592 ; (1 << 33) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_3(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_4(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_high_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_u32 s0, s0, 1 +; GFX9-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 4294967295 ; (1 << 31) + ret i64 %sub +} + +define i64 @v_sub_i64_const_high_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 4294967295 ; (1 << 31) + ret i64 %sub +} + +define <2 x i64> @v_sub_v2i64_splat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_sub_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, -1, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %sub +} + +define <2 x i64> @v_sub_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_sub_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, -2, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %sub +} + +define amdgpu_ps <2 x i64> @s_sub_v2i64_splat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_sub_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: s_add_i32 s3, s3, -1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %sub +} + +define amdgpu_ps <2 x i64> @s_sub_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_sub_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: s_add_i32 s3, s3, -2 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %sub +} + +; We could reduce this to use a 32-bit sub if we use computeKnownBits +define i64 @v_sub_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) { +; GFX9-LABEL: v_sub_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, 0, v0 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %sub = sub i64 %reg, %in.high.bits + ret i64 %sub +} + +; We could reduce this to use a 32-bit sub if we use computeKnownBits +define amdgpu_ps i64 @s_sub_i64_variable_high_bits_known0_0(i64 inreg %reg, i32 inreg %offset.hi32) { +; GFX9-LABEL: s_sub_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_sub_u32 s0, s0, 0 +; GFX9-NEXT: s_subb_u32 s1, s1, s2 +; GFX9-NEXT: ; return to shader part epilog + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %sub = sub i64 %reg, %in.high.bits + ret i64 %sub +} diff --git a/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir b/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir new file mode 100644 index 000000000000..831570800d06 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir @@ -0,0 +1,94 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -stress-regalloc=4 -verify-regalloc -start-before=greedy,2 -stop-after=virtregrewriter,2 -o - %s | FileCheck %s + +# This testcase hit a situation where greedy would hit a use after +# free during last chance recoloring. This case successfully allocates +# after, but is extremely sensitive to the exact allocation ordering. + +--- +name: swdev502267_use_after_free_last_chance_recoloring_alloc_succeeds +tracksRegLiveness: true +stack: + - { id: 0, size: 16 } +machineFunctionInfo: + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + frameOffsetReg: '$sgpr33' + stackPtrOffsetReg: '$sgpr32' +body: | + ; CHECK-LABEL: name: swdev502267_use_after_free_last_chance_recoloring_alloc_succeeds + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $vgpr4_vgpr5 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $vgpr6_vgpr7_vgpr8_vgpr9 = GLOBAL_LOAD_DWORDX4 killed renamable $vgpr4_vgpr5, 0, 0, implicit $exec :: (volatile load (s128), addrspace 1) + ; CHECK-NEXT: renamable $vgpr4 = V_FMA_F32_e64 0, $vgpr6, 0, $vgpr6, 0, $vgpr3, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: renamable $vgpr5 = V_FMA_F32_e64 0, $vgpr7, 0, $vgpr7, 0, $vgpr2, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: SI_SPILL_AV128_SAVE $vgpr6_vgpr7_vgpr8_vgpr9, %stack.2, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr6 = V_FMA_F32_e64 0, killed $vgpr8, 0, $vgpr8, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: renamable $vgpr7 = IMPLICIT_DEF + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3:0x00000000000000FF, $vgpr4_vgpr5_vgpr6_vgpr7:0x00000000000000FF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SI_SPILL_AV128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.1, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr0 = V_FMA_F32_e64 0, $vgpr6, 0, $vgpr6, 0, killed $vgpr2, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: SI_SPILL_V128_SAVE $vgpr4_vgpr5_vgpr6_vgpr7, %stack.4, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.4, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr0 = V_TRUNC_F32_e32 killed $vgpr0, implicit $mode, implicit $exec + ; CHECK-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; CHECK-NEXT: renamable $vgpr0 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr5 = nofpexcept V_DIV_FIXUP_F32_e64 0, killed $vgpr0, 0, killed $vgpr7, 0, killed $vgpr5, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: renamable $vgpr0 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; CHECK-NEXT: renamable $vgpr9 = COPY killed renamable $vgpr5 + ; CHECK-NEXT: renamable $vgpr4_vgpr5_vgpr6_vgpr7 = SI_SPILL_V128_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.4, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr8 = nofpexcept V_FMA_F32_e64 1, killed $vgpr0, 0, killed $vgpr6, 0, killed $vgpr4, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: renamable $vgpr2_vgpr3 = COPY killed renamable $vgpr8_vgpr9 + ; CHECK-NEXT: renamable $vgpr0 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $vgpr4_vgpr5_vgpr6_vgpr7 = SI_SPILL_V128_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.4, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr6_vgpr7_vgpr8_vgpr9 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr0 = nofpexcept V_DIV_FIXUP_F32_e64 0, killed $vgpr0, 0, killed $vgpr4, 0, killed $vgpr6, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: renamable $vgpr4_vgpr5_vgpr6_vgpr7 = SI_SPILL_V128_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.4, align 4, addrspace 5) + ; CHECK-NEXT: renamable $vgpr6_vgpr7_vgpr8_vgpr9 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: dead renamable $vgpr1 = V_FMA_F32_e64 0, killed $vgpr5, 0, $vgpr5, 0, killed $vgpr7, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: dead renamable $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load (s128), addrspace 5) + ; CHECK-NEXT: renamable $vgpr4_vgpr5 = IMPLICIT_DEF + ; CHECK-NEXT: GLOBAL_STORE_DWORDX4 killed renamable $vgpr4_vgpr5, renamable $vgpr0_vgpr1_vgpr2_vgpr3, 0, 0, implicit $exec :: (volatile store (s128), addrspace 1) + ; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_AV128_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3:0x00000000000000FF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: SI_RETURN implicit $vgpr0_vgpr1_vgpr2_vgpr3 + bb.0: + liveins: $vgpr0_vgpr1_vgpr2_vgpr3 + + %0:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3 + %1:vreg_64_align2 = IMPLICIT_DEF + %2:vgpr_32 = IMPLICIT_DEF + %3:vreg_128_align2 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, implicit $exec :: (volatile load (s128), addrspace 1) + undef %4.sub0:vreg_128_align2 = V_FMA_F32_e64 0, %3.sub0, 0, %3.sub0, 0, %0.sub3, 0, 0, implicit $mode, implicit $exec + %4.sub1:vreg_128_align2 = V_FMA_F32_e64 0, %3.sub1, 0, %3.sub1, 0, %0.sub2, 0, 0, implicit $mode, implicit $exec + %4.sub2:vreg_128_align2 = V_FMA_F32_e64 0, %3.sub2, 0, %3.sub2, 0, %0.sub1, 0, 0, implicit $mode, implicit $exec + %4.sub3:vreg_128_align2 = IMPLICIT_DEF + S_CBRANCH_EXECZ %bb.2, implicit $exec + + bb.1: + %5:vgpr_32 = V_FMA_F32_e64 0, %4.sub2, 0, %4.sub2, 0, %3.sub2, 0, 0, implicit $mode, implicit $exec + %6:vgpr_32 = V_TRUNC_F32_e32 %5, implicit $mode, implicit $exec + undef %7.sub3:vreg_128_align2 = nofpexcept V_DIV_FIXUP_F32_e64 0, %2, 0, %4.sub3, 0, %3.sub3, 0, 0, implicit $mode, implicit $exec + %7.sub2:vreg_128_align2 = nofpexcept V_FMA_F32_e64 1, %6, 0, %4.sub2, 0, %3.sub2, 0, 0, implicit $mode, implicit $exec + %7.sub0:vreg_128_align2 = nofpexcept V_DIV_FIXUP_F32_e64 0, %2, 0, %4.sub0, 0, %3.sub0, 0, 0, implicit $mode, implicit $exec + %8:vgpr_32 = V_FMA_F32_e64 0, %4.sub1, 0, %4.sub1, 0, %3.sub1, 0, 0, implicit $mode, implicit $exec + %9:vreg_128_align2 = SCRATCH_LOAD_DWORDX4_SADDR %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load (s128), addrspace 5) + GLOBAL_STORE_DWORDX4 %1, %7, 0, 0, implicit $exec :: (volatile store (s128), addrspace 1) + + bb.2: + $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %0 + SI_RETURN implicit $vgpr0_vgpr1_vgpr2_vgpr3 + +... diff --git a/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll b/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll new file mode 100644 index 000000000000..f0b3d334af67 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll @@ -0,0 +1,23 @@ +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs=0 -O0 2> %t.err < %s | FileCheck %s +; RUN: FileCheck -check-prefix=ERR %s < %t.err + +; FIXME: This error will be fixed by supporting arbitrary divergent +; dynamic allocas by performing a wave umax of the size. + +; ERR: error: <unknown>:0:0: in function move_to_valu_assert_srd_is_physreg_swdev503538 i32 (ptr addrspace(1)): illegal VGPR to SGPR copy + +; CHECK: ; illegal copy v0 to s32 + +define i32 @move_to_valu_assert_srd_is_physreg_swdev503538(ptr addrspace(1) %ptr) { +entry: + %idx = load i32, ptr addrspace(1) %ptr, align 4 + %zero = extractelement <4 x i32> zeroinitializer, i32 %idx + %alloca = alloca [2048 x i8], i32 %zero, align 8, addrspace(5) + %ld = load i32, ptr addrspace(5) %alloca, align 8 + call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 2048, i1 false) + ret i32 %ld +} + +declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg) #0 + +attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) } diff --git a/llvm/test/CodeGen/AMDGPU/umed3.ll b/llvm/test/CodeGen/AMDGPU/umed3.ll index 557d023c45f9..4726e81ceb8c 100644 --- a/llvm/test/CodeGen/AMDGPU/umed3.ll +++ b/llvm/test/CodeGen/AMDGPU/umed3.ll @@ -1,6 +1,8 @@ ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-TRUE16 %s declare i32 @llvm.amdgcn.workitem.id.x() #0 @@ -84,6 +86,8 @@ define amdgpu_kernel void @v_test_umed3_r_i_i_i64(ptr addrspace(1) %out, ptr add ; VI: v_max_u16_e32 [[MAX:v[0-9]]], 12, {{v[0-9]}} ; VI: v_min_u16_e32 {{v[0-9]}}, 17, [[MAX]] ; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +; GFX11-TRUE16: v_med3_u16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, 12, 17 +; GFX11-FAKE16: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 define amdgpu_kernel void @v_test_umed3_r_i_i_i16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr i16, ptr addrspace(1) %aptr, i32 %tid @@ -707,6 +711,8 @@ bb: ; VI: v_max_u16 ; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_u16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_umed3_i16_pat_0(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -728,6 +734,8 @@ bb: ; GCN-LABEL: {{^}}v_test_umed3_i16_pat_1: ; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_u16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_umed3_i16_pat_1(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: %tid = call i32 @llvm.amdgcn.workitem.id.x() diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir b/llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir index ad4ad6df73e7..b663acb8ce3f 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir @@ -67,7 +67,7 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: S_WAITCNT 0 ; GCN-NEXT: $vgpr0 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec - ; GCN-NEXT: CFI_INSTRUCTION offset $vgpr0_lo16, 16 + ; GCN-NEXT: CFI_INSTRUCTION offset $vgpr0, 16 $vgpr0 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec CFI_INSTRUCTION offset $vgpr0, 16 diff --git a/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir new file mode 100644 index 000000000000..92c983e2bfd1 --- /dev/null +++ b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir @@ -0,0 +1,41 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=armv7-- -run-pass=machine-sink | FileCheck %s + +name: sink-store-load-dep +tracksRegLiveness: true +stack: + - { id: 0, type: default, size: 8, alignment: 8 } +body: | + bb.0: + ; CHECK-LABEL: name: sink-store-load-dep + ; CHECK: bb.0: + ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32)) + ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16)) + ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK: bb.2: + ; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg + %0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32)) + %1:gpr = MOVi 55296, 14, $noreg, $noreg + %2:gpr = ADDri %0:gpr, 0, 14, $noreg, $noreg + %3:gpr = LDRH killed %2:gpr, $noreg, 0, 14, $noreg :: (load (s16)) + %4:gpr = MOVi 0, 14, $noreg, $noreg + early-clobber %5:gpr = STRH_PRE %1:gpr, %0:gpr, %4:gpr, 0, 14, $noreg + %6:gpr = SUBri killed %0:gpr, 0, 14, $noreg, $noreg + CMPri %6:gpr, 0, 14, $noreg, implicit-def $cpsr + Bcc %bb.2, 3, $cpsr + B %bb.1 + + bb.1: + %8:gpr = MOVi 0, 14, $noreg, $noreg + $r0 = COPY %8:gpr + BX_RET 14, $noreg, implicit $r0 + + bb.2: + %9:gpr = MOVi %3:gpr, 14, $noreg, $noreg + $r0 = COPY %9:gpr + BX_RET 14, $noreg, implicit $r0 +... diff --git a/llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll b/llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll new file mode 100644 index 000000000000..501f15192d27 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll @@ -0,0 +1,60 @@ +; RUN: opt -S -dxil-op-lower %s | FileCheck %s +; Before SM6.2 ByteAddressBuffer and StructuredBuffer lower to bufferLoad. + +target triple = "dxil-pc-shadermodel6.1-compute" + +; CHECK-LABEL: define void @loadf32_struct +define void @loadf32_struct(i32 %index) { + %buffer = call target("dx.RawBuffer", float, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 0) + %load = call {float, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_0_0_0t( + target("dx.RawBuffer", float, 0, 0, 0) %buffer, + i32 %index, + i32 0) + + ret void +} + +; CHECK-LABEL: define void @loadv4f32_byte +define void @loadv4f32_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle %{{.*}}, i32 %offset, i32 0) + %load = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_i8_0_0_0t( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, + i32 %offset, + i32 0) + + ret void +} + +; CHECK-LABEL: define void @loadnested +define void @loadnested(i32 %index) { + %buffer = call + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATAI32:%.*]] = call %dx.types.ResRet.i32 @dx.op.bufferLoad.i32(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 0) + %loadi32 = call {i32, i1} @llvm.dx.resource.load.rawbuffer.i32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 0) + + ; CHECK: [[DATAF32:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 4) + %loadf32 = call {<4 x float>, i1} @llvm.dx.resource.load.rawbuffer.v4f32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 4) + + ; CHECK: [[DATAF16:%.*]] = call %dx.types.ResRet.f16 @dx.op.bufferLoad.f16(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 20) + %loadf16 = call {<3 x half>, i1} @llvm.dx.resource.load.rawbuffer.v3f16( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 20) + + ret void +} diff --git a/llvm/test/CodeGen/DirectX/BufferLoad.ll b/llvm/test/CodeGen/DirectX/BufferLoad.ll index 7f1291bf4a5c..86e2217a8e76 100644 --- a/llvm/test/CodeGen/DirectX/BufferLoad.ll +++ b/llvm/test/CodeGen/DirectX/BufferLoad.ll @@ -17,8 +17,9 @@ define void @loadv4f32() { ; CHECK-NOT: %dx.resource.casthandle ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load0 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 0) + %data0 = extractvalue {<4 x float>, i1} %load0, 0 ; The extract order depends on the users, so don't enforce that here. ; CHECK-DAG: [[VAL0_0:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 0 @@ -34,8 +35,9 @@ define void @loadv4f32() { call void @scalar_user(float %data0_2) ; CHECK: [[DATA4:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 4, i32 undef) - %data4 = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load4 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 4) + %data4 = extractvalue {<4 x float>, i1} %load4, 0 ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA4]], 0 ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA4]], 1 @@ -48,8 +50,9 @@ define void @loadv4f32() { call void @vector_user(<4 x float> %data4) ; CHECK: [[DATA12:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 12, i32 undef) - %data12 = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load12 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 12) + %data12 = extractvalue {<4 x float>, i1} %load12, 0 ; CHECK: [[DATA12_3:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA12]], 3 %data12_3 = extractelement <4 x float> %data12, i32 3 @@ -70,8 +73,9 @@ define void @index_dynamic(i32 %bufindex, i32 %elemindex) { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[LOAD:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 %bufindex, i32 undef) - %load = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 %bufindex) + %data = extractvalue {<4 x float>, i1} %load, 0 ; CHECK: [[ALLOCA:%.*]] = alloca [4 x float] ; CHECK: [[V0:%.*]] = extractvalue %dx.types.ResRet.f32 [[LOAD]], 0 @@ -89,10 +93,10 @@ define void @index_dynamic(i32 %bufindex, i32 %elemindex) { ; ; CHECK: [[PTR:%.*]] = getelementptr inbounds [4 x float], ptr [[ALLOCA]], i32 0, i32 %elemindex ; CHECK: [[X:%.*]] = load float, ptr [[PTR]] - %data = extractelement <4 x float> %load, i32 %elemindex + %x = extractelement <4 x float> %data, i32 %elemindex ; CHECK: call void @scalar_user(float [[X]]) - call void @scalar_user(float %data) + call void @scalar_user(float %x) ret void } @@ -105,8 +109,9 @@ define void @loadf32() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call float @llvm.dx.resource.load.typedbuffer( + %load0 = call {float, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", float, 0, 0, 0) %buffer, i32 0) + %data0 = extractvalue {float, i1} %load0, 0 ; CHECK: [[VAL0:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 0 ; CHECK: call void @scalar_user(float [[VAL0]]) @@ -123,7 +128,7 @@ define void @loadv2f32() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <2 x float> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<2 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <2 x float>, 0, 0, 0) %buffer, i32 0) ret void @@ -137,7 +142,7 @@ define void @loadv4f32_checkbit() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call {<4 x float>, i1} @llvm.dx.resource.loadchecked.typedbuffer.f32( + %data0 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer.f32( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 0) ; CHECK: [[STATUS:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 4 @@ -158,7 +163,7 @@ define void @loadv4i32() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.i32 @dx.op.bufferLoad.i32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x i32> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<4 x i32>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) %buffer, i32 0) ret void @@ -172,7 +177,7 @@ define void @loadv4f16() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f16 @dx.op.bufferLoad.f16(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x half> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<4 x half>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x half>, 0, 0, 0) %buffer, i32 0) ret void @@ -186,7 +191,7 @@ define void @loadv4i16() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.i16 @dx.op.bufferLoad.i16(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x i16> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<4 x i16>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x i16>, 0, 0, 0) %buffer, i32 0) ret void diff --git a/llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll b/llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll new file mode 100644 index 000000000000..b8a6649baf68 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll @@ -0,0 +1,24 @@ +; We use llc for this test so that we don't abort after the first error. +; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s + +target triple = "dxil-pc-shadermodel6.2-compute" + +declare void @v4f64_user(<4 x double>) + +; Can't load 64 bit types directly until SM6.3 (byteaddressbuf.Load<int64_t4>) +; CHECK: error: +; CHECK-SAME: in function loadv4f64_byte +; CHECK-SAME: Cannot create RawBufferLoad operation: Invalid overload type +define void @loadv4f64_byte(i32 %offset) "hlsl.export" { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + %load = call {<4 x double>, i1} @llvm.dx.resource.load.rawbuffer.v4i64( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, i32 %offset, i32 0) + %data = extractvalue {<4 x double>, i1} %load, 0 + + call void @v4f64_user(<4 x double> %data) + + ret void +} diff --git a/llvm/test/CodeGen/DirectX/RawBufferLoad.ll b/llvm/test/CodeGen/DirectX/RawBufferLoad.ll new file mode 100644 index 000000000000..586b9c44e95d --- /dev/null +++ b/llvm/test/CodeGen/DirectX/RawBufferLoad.ll @@ -0,0 +1,232 @@ +; RUN: opt -S -dxil-op-lower %s | FileCheck %s + +target triple = "dxil-pc-shadermodel6.6-compute" + +declare void @f32_user(float) +declare void @v4f32_user(<4 x float>) +declare void @i32_user(i32) +declare void @v4i32_user(<4 x i32>) +declare void @v3f16_user(<3 x half>) +declare void @v4f64_user(<4 x double>) + +; CHECK-LABEL: define void @loadf32_struct +define void @loadf32_struct(i32 %index) { + %buffer = call target("dx.RawBuffer", float, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 1, i32 4) + %load = call {float, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_0_0_0t( + target("dx.RawBuffer", float, 0, 0, 0) %buffer, + i32 %index, + i32 0) + %data = extractvalue {float, i1} %load, 0 + + ; CHECK: [[VAL:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: call void @f32_user(float [[VAL]]) + call void @f32_user(float %data) + + ret void +} + +; CHECK-LABEL: define void @loadf32_byte +define void @loadf32_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %offset, i32 0, i8 1, i32 4) + %load = call {float, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_i8_0_0_0t( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, + i32 %offset, + i32 0) + %data = extractvalue {float, i1} %load, 0 + + ; CHECK: [[VAL:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: call void @f32_user(float [[VAL]]) + call void @f32_user(float %data) + + ret void +} + +; CHECK-LABEL: define void @loadv4f32_struct +define void @loadv4f32_struct(i32 %index) { + %buffer = call target("dx.RawBuffer", <4 x float>, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f32_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 15, i32 4) + %load = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_v4f32_0_0_0t( + target("dx.RawBuffer", <4 x float>, 0, 0, 0) %buffer, + i32 %index, + i32 0) + %data = extractvalue {<4 x float>, i1} %load, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %data) + + ret void +} + +; CHECK-LABEL: define void @loadv4f32_byte +define void @loadv4f32_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %offset, i32 0, i8 15, i32 4) + %load = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_i8_0_0_0t( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, + i32 %offset, + i32 0) + %data = extractvalue {<4 x float>, i1} %load, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %data) + + ret void +} + +; CHECK-LABEL: define void @loadelements +define void @loadelements(i32 %index) { + %buffer = call target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATAF32:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 15, i32 4) + %loadf32 = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.v4f32( + target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0, 0) %buffer, + i32 %index, + i32 0) + %dataf32 = extractvalue {<4 x float>, i1} %loadf32, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %dataf32) + + ; CHECK: [[DATAI32:%.*]] = call %dx.types.ResRet.i32 @dx.op.rawBufferLoad.i32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 1, i8 15, i32 4) + %loadi32 = call {<4 x i32>, i1} + @llvm.dx.resource.load.rawbuffer.v4i32( + target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0, 0) %buffer, + i32 %index, + i32 1) + %datai32 = extractvalue {<4 x i32>, i1} %loadi32, 0 + + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 0 + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 1 + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 2 + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 3 + ; CHECK: insertelement <4 x i32> undef + ; CHECK: insertelement <4 x i32> + ; CHECK: insertelement <4 x i32> + ; CHECK: insertelement <4 x i32> + ; CHECK: call void @v4i32_user(<4 x i32> + call void @v4i32_user(<4 x i32> %datai32) + + ret void +} + +; CHECK-LABEL: define void @loadnested +define void @loadnested(i32 %index) { + %buffer = call + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATAI32:%.*]] = call %dx.types.ResRet.i32 @dx.op.rawBufferLoad.i32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 1, i32 4) + %loadi32 = call {i32, i1} @llvm.dx.resource.load.rawbuffer.i32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 0) + %datai32 = extractvalue {i32, i1} %loadi32, 0 + + ; CHECK: [[VALI32:%.*]] = extractvalue %dx.types.ResRet.i32 [[DATAI32]], 0 + ; CHECK: call void @i32_user(i32 [[VALI32]]) + call void @i32_user(i32 %datai32) + + ; CHECK: [[DATAF32:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 4, i8 15, i32 4) + %loadf32 = call {<4 x float>, i1} @llvm.dx.resource.load.rawbuffer.v4f32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 4) + %dataf32 = extractvalue {<4 x float>, i1} %loadf32, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %dataf32) + + ; CHECK: [[DATAF16:%.*]] = call %dx.types.ResRet.f16 @dx.op.rawBufferLoad.f16(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 20, i8 7, i32 2) + %loadf16 = call {<3 x half>, i1} @llvm.dx.resource.load.rawbuffer.v3f16( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 20) + %dataf16 = extractvalue {<3 x half>, i1} %loadf16, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f16 [[DATAF16]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f16 [[DATAF16]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f16 [[DATAF16]], 2 + ; CHECK: insertelement <3 x half> undef + ; CHECK: insertelement <3 x half> + ; CHECK: insertelement <3 x half> + ; CHECK: call void @v3f16_user(<3 x half> + call void @v3f16_user(<3 x half> %dataf16) + + ret void +} + +; byteaddressbuf.Load<int64_t4> +; CHECK-LABEL: define void @loadv4f64_byte +define void @loadv4f64_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f64 @dx.op.rawBufferLoad.f64(i32 139, %dx.types.Handle %{{.*}}, i32 %offset, i32 0, i8 15, i32 8) + %load = call {<4 x double>, i1} @llvm.dx.resource.load.rawbuffer.v4i64( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, i32 %offset, i32 0) + %data = extractvalue {<4 x double>, i1} %load, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 3 + ; CHECK: insertelement <4 x double> undef + ; CHECK: insertelement <4 x double> + ; CHECK: insertelement <4 x double> + ; CHECK: insertelement <4 x double> + ; CHECK: call void @v4f64_user(<4 x double> + call void @v4f64_user(<4 x double> %data) + + ret void +} diff --git a/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll b/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll index 9b7e7fd04f60..8769e6ec66d8 100644 --- a/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll +++ b/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll @@ -15,17 +15,19 @@ define void @load_float4(i32 %index, i32 %elemindex) { %ptr = call ptr @llvm.dx.resource.getpointer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) %vec_data = load <4 x float>, ptr %ptr call void @use_float4(<4 x float> %vec_data) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 ; CHECK: extractelement <4 x float> %[[VALUE]], i32 1 %y_ptr = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 1 %y_data = load float, ptr %y_ptr call void @use_float(float %y_data) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 ; CHECK: extractelement <4 x float> %[[VALUE]], i32 %elemindex %dynamic = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 %elemindex %dyndata = load float, ptr %dynamic diff --git a/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll b/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll index 17606408cadf..0b7882ac722e 100644 --- a/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll +++ b/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll @@ -18,21 +18,24 @@ define void @store_float4(<4 x float> %data, i32 %index, i32 %elemindex) { ; Store just the .x component %scalar = extractelement <4 x float> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 0 + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[VEC]], float %scalar, i32 0 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) store float %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 1 + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[VEC]], float %scalar, i32 1 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 4 store float %scalar, ptr %y_ptr ; Store to one of the elements dynamically - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 %elemindex + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[VEC]], float %scalar, i32 %elemindex ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) %dynamic = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 %elemindex store float %scalar, ptr %dynamic @@ -56,14 +59,16 @@ define void @store_half4(<4 x half> %data, i32 %index) { ; Store just the .x component %scalar = extractelement <4 x half> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[LOAD]], half %scalar, i32 0 + ; CHECK: %[[LOAD:.*]] = call { <4 x half>, i1 } @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x half>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[VEC]], half %scalar, i32 0 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) store half %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[LOAD]], half %scalar, i32 1 + ; CHECK: %[[LOAD:.*]] = call { <4 x half>, i1 } @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x half>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[VEC]], half %scalar, i32 1 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 2 store half %scalar, ptr %y_ptr @@ -87,14 +92,16 @@ define void @store_double2(<2 x double> %data, i32 %index) { ; Store just the .x component %scalar = extractelement <2 x double> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[LOAD]], double %scalar, i32 0 + ; CHECK: %[[LOAD:.*]] = call { <2 x double>, i1 } @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <2 x double>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[VEC]], double %scalar, i32 0 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) store double %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[LOAD]], double %scalar, i32 1 + ; CHECK: %[[LOAD:.*]] = call { <2 x double>, i1 } @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <2 x double>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[VEC]], double %scalar, i32 1 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 8 store double %scalar, ptr %y_ptr diff --git a/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll b/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll index c837b36a19e1..cd21adc11a9b 100644 --- a/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll +++ b/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll @@ -29,18 +29,20 @@ entry: %0 = call i32 @llvm.dx.flattened.thread.id.in.group() ; CHECK-NOT: load {{.*}} ptr @In %1 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4 - ; CSE: call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t - %2 = call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %1, i32 %0) + ; CSE: call noundef { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t + %load = call noundef {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %1, i32 %0) + %2 = extractvalue {<4 x float>, i1} %load, 0 ; CHECK-NOT: load {{.*}} ptr @In %3 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4 - %4 = call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %3, i32 %0) + %load2 = call noundef {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %3, i32 %0) + %4 = extractvalue {<4 x float>, i1} %load2, 0 %add.i = fadd <4 x float> %2, %4 call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, i32 %0, <4 x float> %add.i) ; CHECK: ret void ret void } -; CSE-DAG: declare <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) [[ROAttr:#[0-9]+]] +; CSE-DAG: declare { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) [[ROAttr:#[0-9]+]] ; CSE-DAG: declare void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <4 x float>) [[WOAttr:#[0-9]+]] attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="8,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll index 26223359dfdf..060d54f961c7 100644 --- a/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll @@ -17,8 +17,9 @@ target triple = "dxil-pc-shadermodel6.7-library" define <4 x float> @multicomponent() #0 { %res = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) - %val = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %res, i32 0) + %val = extractvalue {<4 x float>, i1} %load, 0 ret <4 x float> %val } @@ -26,8 +27,9 @@ define <4 x float> @multicomponent() #0 { define float @onecomponent() #0 { %res = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) - %val = call float @llvm.dx.resource.load.typedbuffer( + %load = call {float, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", float, 1, 0, 0) %res, i32 0) + %val = extractvalue {float, i1} %load, 0 ret float %val } diff --git a/llvm/test/CodeGen/Hexagon/loopIdiom.ll b/llvm/test/CodeGen/Hexagon/loopIdiom.ll new file mode 100644 index 000000000000..9c3df674a493 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/loopIdiom.ll @@ -0,0 +1,75 @@ +; RUN: opt -debug -S -march=hexagon -O2 < %s | FileCheck %s +; REQUIRES: asserts +; CHECK: define dso_local void @complexMultAccum +target triple = "hexagon" + +; Function Attrs: noinline nounwind +define dso_local void @complexMultAccum(i32 noundef %n) #0 { +entry: + %n.addr = alloca i32, align 4 + %run_c_code = alloca i8, align 1 + %run_asm_code = alloca i8, align 1 + %iOutter = alloca i32, align 4 + %iOutter1 = alloca i32, align 4 + store i32 %n, ptr %n.addr, align 4 + store i8 1, ptr %run_c_code, align 1 + store i8 0, ptr %run_asm_code, align 1 + %0 = load i8, ptr %run_c_code, align 1 + %tobool = icmp ne i8 %0, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, ptr %iOutter, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %if.then + %1 = load i32, ptr %iOutter, align 4 + %cmp = icmp slt i32 %1, 2 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + br label %for.inc + +for.inc: ; preds = %for.body + %2 = load i32, ptr %iOutter, align 4 + %inc = add nsw i32 %2, 1 + store i32 %inc, ptr %iOutter, align 4 + br label %for.cond, !llvm.loop !3 + +for.end: ; preds = %for.cond + store i32 0, ptr %iOutter1, align 4 + br label %for.cond2 + +for.cond2: ; preds = %for.inc5, %for.end + %3 = load i32, ptr %iOutter1, align 4 + %cmp3 = icmp slt i32 %3, 2 + br i1 %cmp3, label %for.body4, label %for.end7 + +for.body4: ; preds = %for.cond2 + br label %for.inc5 + +for.inc5: ; preds = %for.body4 + %4 = load i32, ptr %iOutter1, align 4 + %inc6 = add nsw i32 %4, 1 + store i32 %inc6, ptr %iOutter1, align 4 + br label %for.cond2, !llvm.loop !5 + +for.end7: ; preds = %for.cond2 + br label %if.end + +if.end: ; preds = %for.end7, %entry + ret void +} + +attributes #0 = { noinline nounwind "approx-func-fp-math"="true" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv79" "target-features"="+v79,-long-calls" "unsafe-fp-math"="true" } + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"frame-pointer", i32 2} +!2 = !{!"LLVM Clang"} +!3 = distinct !{!3, !4} +!4 = !{!"llvm.loop.mustprogress"} +!5 = distinct !{!5, !4} + diff --git a/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll b/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll index fc0c7ad1686e..e0a93e3051bf 100644 --- a/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll +++ b/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll @@ -315,9 +315,9 @@ define void @test_la_tls_le(i32 signext %n) { ; LA32-LABEL: test_la_tls_le: ; LA32: # %bb.0: # %entry ; LA32-NEXT: move $a1, $zero -; LA32-NEXT: lu12i.w $a2, %le_hi20(le) -; LA32-NEXT: ori $a2, $a2, %le_lo12(le) -; LA32-NEXT: add.w $a2, $a2, $tp +; LA32-NEXT: lu12i.w $a2, %le_hi20_r(le) +; LA32-NEXT: add.w $a2, $a2, $tp, %le_add_r(le) +; LA32-NEXT: addi.w $a2, $a2, %le_lo12_r(le) ; LA32-NEXT: .p2align 4, , 16 ; LA32-NEXT: .LBB4_1: # %loop ; LA32-NEXT: # =>This Inner Loop Header: Depth=1 @@ -330,12 +330,13 @@ define void @test_la_tls_le(i32 signext %n) { ; LA64-LABEL: test_la_tls_le: ; LA64: # %bb.0: # %entry ; LA64-NEXT: move $a1, $zero -; LA64-NEXT: lu12i.w $a2, %le_hi20(le) -; LA64-NEXT: ori $a2, $a2, %le_lo12(le) +; LA64-NEXT: lu12i.w $a2, %le_hi20_r(le) +; LA64-NEXT: add.d $a2, $a2, $tp, %le_add_r(le) +; LA64-NEXT: addi.d $a2, $a2, %le_lo12_r(le) ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB4_1: # %loop ; LA64-NEXT: # =>This Inner Loop Header: Depth=1 -; LA64-NEXT: ldx.w $zero, $a2, $tp +; LA64-NEXT: ld.w $zero, $a2, 0 ; LA64-NEXT: addi.w $a1, $a1, 1 ; LA64-NEXT: blt $a1, $a0, .LBB4_1 ; LA64-NEXT: # %bb.2: # %ret diff --git a/llvm/test/CodeGen/LoongArch/mir-target-flags.ll b/llvm/test/CodeGen/LoongArch/mir-target-flags.ll index f530e3ef237c..3bc8a8d30958 100644 --- a/llvm/test/CodeGen/LoongArch/mir-target-flags.ll +++ b/llvm/test/CodeGen/LoongArch/mir-target-flags.ll @@ -28,8 +28,9 @@ define void @caller() nounwind { ; CHECK-NEXT: target-flags(loongarch-got-pc-lo) @t_ld ; CHECK: target-flags(loongarch-ie-pc-hi) @t_ie ; CHECK-NEXT: target-flags(loongarch-ie-pc-lo) @t_ie -; CHECK: target-flags(loongarch-le-hi) @t_le -; CHECK-NEXT: target-flags(loongarch-le-lo) @t_le +; CHECK: target-flags(loongarch-le-hi-r) @t_le +; CHECK-NEXT: target-flags(loongarch-le-add-r) @t_le +; CHECK-NEXT: target-flags(loongarch-le-lo-r) @t_le ; CHECK: target-flags(loongarch-call-plt) @callee1 ; CHECK: target-flags(loongarch-call) @callee2 %a = load volatile i32, ptr @g_e diff --git a/llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll b/llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll index c7de3dcf2ecf..3390f7fe14ae 100644 --- a/llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll +++ b/llvm/test/CodeGen/LoongArch/psabi-restricted-scheduling.ll @@ -1,4 +1,3 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --post-RA-scheduler=0 < %s \ ; RUN: | FileCheck %s --check-prefix=MEDIUM_NO_SCH ; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --post-RA-scheduler=1 < %s \ @@ -7,6 +6,14 @@ ; RUN: | FileCheck %s --check-prefix=LARGE_NO_SCH ; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=large --relocation-model=pic --post-RA-scheduler=1 < %s \ ; RUN: | FileCheck %s --check-prefix=LARGE_SCH +; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --enable-tlsdesc \ +; RUN: --post-RA-scheduler=0 < %s | FileCheck %s --check-prefix=MEDIUMDESC_NO_SCH +; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=medium --relocation-model=pic --enable-tlsdesc \ +; RUN: --post-RA-scheduler=1 < %s | FileCheck %s --check-prefix=MEDIUMDESC_SCH +; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=large --relocation-model=pic --enable-tlsdesc \ +; RUN: --post-RA-scheduler=0 < %s | FileCheck %s --check-prefix=LARGEDESC_NO_SCH +; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=large --relocation-model=pic --enable-tlsdesc \ +; RUN: --post-RA-scheduler=1 < %s | FileCheck %s --check-prefix=LARGEDESC_SCH @g = dso_local global i64 zeroinitializer, align 4 @G = global i64 zeroinitializer, align 4 @@ -194,3 +201,69 @@ define void @foo() nounwind { %v_ie = load volatile i64, ptr @ie ret void } + +define void @baz() nounwind { +; MEDIUMDESC_NO_SCH-LABEL: baz: +; MEDIUMDESC_NO_SCH: # %bb.0: +; MEDIUMDESC_NO_SCH-NEXT: addi.d $sp, $sp, -16 +; MEDIUMDESC_NO_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; MEDIUMDESC_NO_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd) +; MEDIUMDESC_NO_SCH-NEXT: addi.d $a0, $a0, %desc_pc_lo12(gd) +; MEDIUMDESC_NO_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd) +; MEDIUMDESC_NO_SCH-NEXT: jirl $ra, $ra, %desc_call(gd) +; MEDIUMDESC_NO_SCH-NEXT: add.d $a0, $a0, $tp +; MEDIUMDESC_NO_SCH-NEXT: ld.d $zero, $a0, 0 +; MEDIUMDESC_NO_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; MEDIUMDESC_NO_SCH-NEXT: addi.d $sp, $sp, 16 +; MEDIUMDESC_NO_SCH-NEXT: ret +; +; MEDIUMDESC_SCH-LABEL: baz: +; MEDIUMDESC_SCH: # %bb.0: +; MEDIUMDESC_SCH-NEXT: addi.d $sp, $sp, -16 +; MEDIUMDESC_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; MEDIUMDESC_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd) +; MEDIUMDESC_SCH-NEXT: addi.d $a0, $a0, %desc_pc_lo12(gd) +; MEDIUMDESC_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd) +; MEDIUMDESC_SCH-NEXT: jirl $ra, $ra, %desc_call(gd) +; MEDIUMDESC_SCH-NEXT: add.d $a0, $a0, $tp +; MEDIUMDESC_SCH-NEXT: ld.d $zero, $a0, 0 +; MEDIUMDESC_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; MEDIUMDESC_SCH-NEXT: addi.d $sp, $sp, 16 +; MEDIUMDESC_SCH-NEXT: ret +; +; LARGEDESC_NO_SCH-LABEL: baz: +; LARGEDESC_NO_SCH: # %bb.0: +; LARGEDESC_NO_SCH-NEXT: addi.d $sp, $sp, -16 +; LARGEDESC_NO_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; LARGEDESC_NO_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd) +; LARGEDESC_NO_SCH-NEXT: addi.d $a1, $zero, %desc_pc_lo12(gd) +; LARGEDESC_NO_SCH-NEXT: lu32i.d $a1, %desc64_pc_lo20(gd) +; LARGEDESC_NO_SCH-NEXT: lu52i.d $a1, $a1, %desc64_pc_hi12(gd) +; LARGEDESC_NO_SCH-NEXT: add.d $a0, $a0, $a1 +; LARGEDESC_NO_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd) +; LARGEDESC_NO_SCH-NEXT: jirl $ra, $ra, %desc_call(gd) +; LARGEDESC_NO_SCH-NEXT: add.d $a0, $a0, $tp +; LARGEDESC_NO_SCH-NEXT: ld.d $zero, $a0, 0 +; LARGEDESC_NO_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; LARGEDESC_NO_SCH-NEXT: addi.d $sp, $sp, 16 +; LARGEDESC_NO_SCH-NEXT: ret +; +; LARGEDESC_SCH-LABEL: baz: +; LARGEDESC_SCH: # %bb.0: +; LARGEDESC_SCH-NEXT: addi.d $sp, $sp, -16 +; LARGEDESC_SCH-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; LARGEDESC_SCH-NEXT: pcalau12i $a0, %desc_pc_hi20(gd) +; LARGEDESC_SCH-NEXT: addi.d $a1, $zero, %desc_pc_lo12(gd) +; LARGEDESC_SCH-NEXT: lu32i.d $a1, %desc64_pc_lo20(gd) +; LARGEDESC_SCH-NEXT: lu52i.d $a1, $a1, %desc64_pc_hi12(gd) +; LARGEDESC_SCH-NEXT: add.d $a0, $a0, $a1 +; LARGEDESC_SCH-NEXT: ld.d $ra, $a0, %desc_ld(gd) +; LARGEDESC_SCH-NEXT: jirl $ra, $ra, %desc_call(gd) +; LARGEDESC_SCH-NEXT: add.d $a0, $a0, $tp +; LARGEDESC_SCH-NEXT: ld.d $zero, $a0, 0 +; LARGEDESC_SCH-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; LARGEDESC_SCH-NEXT: addi.d $sp, $sp, 16 +; LARGEDESC_SCH-NEXT: ret + %v_gd = load volatile i64, ptr @gd + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/tls-models.ll b/llvm/test/CodeGen/LoongArch/tls-models.ll index dbd7bf6a8126..e3a8ace3bc7e 100644 --- a/llvm/test/CodeGen/LoongArch/tls-models.ll +++ b/llvm/test/CodeGen/LoongArch/tls-models.ll @@ -330,16 +330,16 @@ entry: define ptr @f4() nounwind { ; LA32PIC-LABEL: f4: ; LA32PIC: # %bb.0: # %entry -; LA32PIC-NEXT: lu12i.w $a0, %le_hi20(le) -; LA32PIC-NEXT: ori $a0, $a0, %le_lo12(le) -; LA32PIC-NEXT: add.w $a0, $a0, $tp +; LA32PIC-NEXT: lu12i.w $a0, %le_hi20_r(le) +; LA32PIC-NEXT: add.w $a0, $a0, $tp, %le_add_r(le) +; LA32PIC-NEXT: addi.w $a0, $a0, %le_lo12_r(le) ; LA32PIC-NEXT: ret ; ; LA64PIC-LABEL: f4: ; LA64PIC: # %bb.0: # %entry -; LA64PIC-NEXT: lu12i.w $a0, %le_hi20(le) -; LA64PIC-NEXT: ori $a0, $a0, %le_lo12(le) -; LA64PIC-NEXT: add.d $a0, $a0, $tp +; LA64PIC-NEXT: lu12i.w $a0, %le_hi20_r(le) +; LA64PIC-NEXT: add.d $a0, $a0, $tp, %le_add_r(le) +; LA64PIC-NEXT: addi.d $a0, $a0, %le_lo12_r(le) ; LA64PIC-NEXT: ret ; ; LA64LARGEPIC-LABEL: f4: @@ -353,16 +353,16 @@ define ptr @f4() nounwind { ; ; LA32NOPIC-LABEL: f4: ; LA32NOPIC: # %bb.0: # %entry -; LA32NOPIC-NEXT: lu12i.w $a0, %le_hi20(le) -; LA32NOPIC-NEXT: ori $a0, $a0, %le_lo12(le) -; LA32NOPIC-NEXT: add.w $a0, $a0, $tp +; LA32NOPIC-NEXT: lu12i.w $a0, %le_hi20_r(le) +; LA32NOPIC-NEXT: add.w $a0, $a0, $tp, %le_add_r(le) +; LA32NOPIC-NEXT: addi.w $a0, $a0, %le_lo12_r(le) ; LA32NOPIC-NEXT: ret ; ; LA64NOPIC-LABEL: f4: ; LA64NOPIC: # %bb.0: # %entry -; LA64NOPIC-NEXT: lu12i.w $a0, %le_hi20(le) -; LA64NOPIC-NEXT: ori $a0, $a0, %le_lo12(le) -; LA64NOPIC-NEXT: add.d $a0, $a0, $tp +; LA64NOPIC-NEXT: lu12i.w $a0, %le_hi20_r(le) +; LA64NOPIC-NEXT: add.d $a0, $a0, $tp, %le_add_r(le) +; LA64NOPIC-NEXT: addi.d $a0, $a0, %le_lo12_r(le) ; LA64NOPIC-NEXT: ret ; ; LA64LARGENOPIC-LABEL: f4: @@ -376,16 +376,16 @@ define ptr @f4() nounwind { ; ; LA32DESC-LABEL: f4: ; LA32DESC: # %bb.0: # %entry -; LA32DESC-NEXT: lu12i.w $a0, %le_hi20(le) -; LA32DESC-NEXT: ori $a0, $a0, %le_lo12(le) -; LA32DESC-NEXT: add.w $a0, $a0, $tp +; LA32DESC-NEXT: lu12i.w $a0, %le_hi20_r(le) +; LA32DESC-NEXT: add.w $a0, $a0, $tp, %le_add_r(le) +; LA32DESC-NEXT: addi.w $a0, $a0, %le_lo12_r(le) ; LA32DESC-NEXT: ret ; ; LA64DESC-LABEL: f4: ; LA64DESC: # %bb.0: # %entry -; LA64DESC-NEXT: lu12i.w $a0, %le_hi20(le) -; LA64DESC-NEXT: ori $a0, $a0, %le_lo12(le) -; LA64DESC-NEXT: add.d $a0, $a0, $tp +; LA64DESC-NEXT: lu12i.w $a0, %le_hi20_r(le) +; LA64DESC-NEXT: add.d $a0, $a0, $tp, %le_add_r(le) +; LA64DESC-NEXT: addi.d $a0, $a0, %le_lo12_r(le) ; LA64DESC-NEXT: ret ; ; DESC64-LABEL: f4: diff --git a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir index d2b063a05713..b2abff75880c 100644 --- a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir +++ b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir @@ -25,8 +25,8 @@ alignment: 4 tracksRegLiveness: true frameInfo: maxCallFrameSize: 0 -#CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp #CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state +#CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp #CHECK: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp body: | bb.0.entry: @@ -42,8 +42,8 @@ tracksRegLiveness: true frameInfo: maxCallFrameSize: 0 #CHECK: frame-setup EMITBKEY -#CHECK: frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp #CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state +#CHECK: frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp #CHECK: frame-destroy AUTIBSP implicit-def $lr, implicit $lr, implicit $sp body: | bb.0.entry: @@ -59,8 +59,8 @@ tracksRegLiveness: true frameInfo: maxCallFrameSize: 0 #CHECK: frame-setup PACM -#CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol > #CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state_with_pc +#CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol > #CHECK: frame-destroy PACM #CHECK: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp body: | diff --git a/llvm/test/CodeGen/NVPTX/b52037.ll b/llvm/test/CodeGen/NVPTX/b52037.ll index 5d1c390909f6..b6317dfb2859 100644 --- a/llvm/test/CodeGen/NVPTX/b52037.ll +++ b/llvm/test/CodeGen/NVPTX/b52037.ll @@ -39,7 +39,7 @@ declare %int3 @hoge(i32, i32, i32) local_unnamed_addr declare i64 @foo() local_unnamed_addr -define void @barney(ptr nocapture readonly %arg) local_unnamed_addr { +define ptx_kernel void @barney(ptr nocapture readonly %arg) local_unnamed_addr { bb: tail call void asm sideeffect "// KEEP", ""() #1 %tmp = alloca %struct.zot, align 16 @@ -210,9 +210,6 @@ bb14: ; preds = %bb49.i.lr.ph, %bb49 attributes #0 = { argmemonly mustprogress nofree nounwind willreturn } attributes #1 = { nounwind } -!nvvm.annotations = !{!0} - -!0 = !{ptr @barney, !"kernel", i32 1} !1 = !{!2, !11, i64 64} !2 = !{!"_ZTSN7cuneibs22neiblist_iterator_coreE", !3, i64 0, !3, i64 8, !6, i64 16, !8, i64 32, !9, i64 44, !10, i64 48, !11, i64 64, !9, i64 72, !4, i64 76, !9, i64 80} !3 = !{!"any pointer", !4, i64 0} diff --git a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll index 03cdeb9683ab..8be3a66b7f48 100644 --- a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll @@ -182,8 +182,8 @@ define <2 x bfloat> @test_fneg(<2 x bfloat> %a) #0 { ; CHECK-NEXT: .reg .b32 %r<3>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.u32 %r1, [test_fneg_param_0]; -; CHECK-NEXT: xor.b32 %r2, %r1, -2147450880; +; CHECK-NEXT: ld.param.b32 %r1, [test_fneg_param_0]; +; CHECK-NEXT: neg.bf16x2 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; %r = fneg <2 x bfloat> %a @@ -532,8 +532,8 @@ define <2 x bfloat> @test_fabs(<2 x bfloat> %a) #0 { ; CHECK-NEXT: .reg .b32 %r<3>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.u32 %r1, [test_fabs_param_0]; -; CHECK-NEXT: and.b32 %r2, %r1, 2147450879; +; CHECK-NEXT: ld.param.b32 %r1, [test_fabs_param_0]; +; CHECK-NEXT: abs.bf16x2 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; %r = call <2 x bfloat> @llvm.fabs.f16(<2 x bfloat> %a) diff --git a/llvm/test/CodeGen/NVPTX/bug21465.ll b/llvm/test/CodeGen/NVPTX/bug21465.ll index 9b1f1049c648..76300e3cfdc5 100644 --- a/llvm/test/CodeGen/NVPTX/bug21465.ll +++ b/llvm/test/CodeGen/NVPTX/bug21465.ll @@ -8,7 +8,7 @@ target triple = "nvptx64-unknown-unknown" %struct.S = type { i32, i32 } ; Function Attrs: nounwind -define void @_Z11TakesStruct1SPi(ptr byval(%struct.S) nocapture readonly %input, ptr nocapture %output) #0 { +define ptx_kernel void @_Z11TakesStruct1SPi(ptr byval(%struct.S) nocapture readonly %input, ptr nocapture %output) #0 { entry: ; CHECK-LABEL: @_Z11TakesStruct1SPi ; PTX-LABEL: .visible .entry _Z11TakesStruct1SPi( @@ -23,7 +23,3 @@ entry: } attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - -!nvvm.annotations = !{!0} - -!0 = !{ptr @_Z11TakesStruct1SPi, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/bug22322.ll b/llvm/test/CodeGen/NVPTX/bug22322.ll index e3656fd16b21..ace31667184b 100644 --- a/llvm/test/CodeGen/NVPTX/bug22322.ll +++ b/llvm/test/CodeGen/NVPTX/bug22322.ll @@ -8,7 +8,7 @@ target triple = "nvptx64-nvidia-cuda" ; Function Attrs: nounwind ; CHECK-LABEL: some_kernel -define void @some_kernel(ptr nocapture %dst) #0 { +define ptx_kernel void @some_kernel(ptr nocapture %dst) #0 { _ZL11compute_vecRK6float3jb.exit: %ret_vec.sroa.8.i = alloca float, align 4 %0 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() @@ -55,8 +55,5 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "n attributes #1 = { nounwind readnone } attributes #2 = { nounwind } -!nvvm.annotations = !{!0} !llvm.ident = !{!1} - -!0 = !{ptr @some_kernel, !"kernel", i32 1} !1 = !{!"clang version 3.5.1 (tags/RELEASE_351/final)"} diff --git a/llvm/test/CodeGen/NVPTX/bug26185.ll b/llvm/test/CodeGen/NVPTX/bug26185.ll index 00c97fb381e0..193df7f86ca7 100644 --- a/llvm/test/CodeGen/NVPTX/bug26185.ll +++ b/llvm/test/CodeGen/NVPTX/bug26185.ll @@ -8,7 +8,7 @@ target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-unknown-unknown" ; CHECK-LABEL: ex_zext -define void @ex_zext(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_zext(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.u8 %val = load i8, ptr %data @@ -19,7 +19,7 @@ entry: } ; CHECK-LABEL: ex_sext -define void @ex_sext(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_sext(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.u8 %val = load i8, ptr %data @@ -30,7 +30,7 @@ entry: } ; CHECK-LABEL: ex_zext_v2 -define void @ex_zext_v2(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_zext_v2(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.v2.u8 %val = load <2 x i8>, ptr %data @@ -41,7 +41,7 @@ entry: } ; CHECK-LABEL: ex_sext_v2 -define void @ex_sext_v2(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_sext_v2(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.v2.u8 %val = load <2 x i8>, ptr %data @@ -51,8 +51,3 @@ entry: ret void } -!nvvm.annotations = !{!0,!1,!2,!3} -!0 = !{ptr @ex_zext, !"kernel", i32 1} -!1 = !{ptr @ex_sext, !"kernel", i32 1} -!2 = !{ptr @ex_zext_v2, !"kernel", i32 1} -!3 = !{ptr @ex_sext_v2, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll b/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll index 19f4ef8ec77b..1c9d271902fd 100644 --- a/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll +++ b/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll @@ -16,7 +16,7 @@ ; } ; CHECK: .visible .entry kernel_func -define void @kernel_func(ptr %a) { +define ptx_kernel void @kernel_func(ptr %a) { entry: %buf = alloca [16 x i8], align 4 @@ -56,7 +56,3 @@ entry: } declare void @callee(ptr, ptr) - -!nvvm.annotations = !{!0} - -!0 = !{ptr @kernel_func, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/cluster-dim.ll b/llvm/test/CodeGen/NVPTX/cluster-dim.ll index c9258addbe04..9275c895b224 100644 --- a/llvm/test/CodeGen/NVPTX/cluster-dim.ll +++ b/llvm/test/CodeGen/NVPTX/cluster-dim.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 | FileCheck -check-prefixes=CHECK90 %s ; RUN: %if ptxas-12.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 | %ptxas-verify -arch=sm_90 %} -define void @kernel_func_clusterxyz() { +define ptx_kernel void @kernel_func_clusterxyz() { ; CHECK80-LABEL: kernel_func_clusterxyz( ; CHECK80: { ; CHECK80-EMPTY: @@ -23,7 +23,6 @@ define void @kernel_func_clusterxyz() { } -!nvvm.annotations = !{!1, !2} +!nvvm.annotations = !{!1} -!1 = !{ptr @kernel_func_clusterxyz, !"kernel", i32 1} -!2 = !{ptr @kernel_func_clusterxyz, !"cluster_dim_x", i32 3, !"cluster_dim_y", i32 5, !"cluster_dim_z", i32 7} +!1 = !{ptr @kernel_func_clusterxyz, !"cluster_dim_x", i32 3, !"cluster_dim_y", i32 5, !"cluster_dim_z", i32 7} diff --git a/llvm/test/CodeGen/NVPTX/disjoint-or-addr.ll b/llvm/test/CodeGen/NVPTX/disjoint-or-addr.ll new file mode 100644 index 000000000000..1b1bb91d5c79 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/disjoint-or-addr.ll @@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck %s +; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %} +target triple = "nvptx64-nvidia-cuda" + +@a = external global ptr align 16 + +define i32 @test_disjoint_or_addr(i16 %a) { +; CHECK-LABEL: test_disjoint_or_addr( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<2>; +; CHECK-NEXT: .reg .b64 %rd<3>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: mov.u64 %rd1, a; +; CHECK-NEXT: cvta.global.u64 %rd2, %rd1; +; CHECK-NEXT: ld.u32 %r1, [%rd2+8]; +; CHECK-NEXT: st.param.b32 [func_retval0], %r1; +; CHECK-NEXT: ret; + %a1 = ptrtoint ptr @a to i64 + %a2 = or disjoint i64 %a1, 8 + %a3 = inttoptr i64 %a2 to ptr + %v = load i32, ptr %a3 + ret i32 %v +} diff --git a/llvm/test/CodeGen/NVPTX/fabs-fneg-free.ll b/llvm/test/CodeGen/NVPTX/fabs-fneg-free.ll new file mode 100644 index 000000000000..9031f33939f2 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/fabs-fneg-free.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck %s +; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %} +target triple = "nvptx64-nvidia-cuda" + +define float @fabs_free(i32 %in) { +; CHECK-LABEL: fabs_free( +; CHECK: { +; CHECK-NEXT: .reg .f32 %f<3>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.f32 %f1, [fabs_free_param_0]; +; CHECK-NEXT: abs.f32 %f2, %f1; +; CHECK-NEXT: st.param.f32 [func_retval0], %f2; +; CHECK-NEXT: ret; + %b = bitcast i32 %in to float + %f = call float @llvm.fabs.f32(float %b) + ret float %f +} + +define float @fneg_free(i32 %in) { +; CHECK-LABEL: fneg_free( +; CHECK: { +; CHECK-NEXT: .reg .f32 %f<3>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.f32 %f1, [fneg_free_param_0]; +; CHECK-NEXT: neg.f32 %f2, %f1; +; CHECK-NEXT: st.param.f32 [func_retval0], %f2; +; CHECK-NEXT: ret; + %b = bitcast i32 %in to float + %f = fneg float %b + ret float %f +} diff --git a/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll b/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll index 43e4dfca1456..2b6631154e38 100644 --- a/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll +++ b/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll @@ -12,7 +12,7 @@ target triple = "nvptx-nvidia-cuda" @myconst = internal constant i32 420, align 4 -define void @foo(ptr %a, ptr %b) { +define ptx_kernel void @foo(ptr %a, ptr %b) { ; Expect one load -- @myconst isn't loaded from, because we know its value ; statically. ; CHECK: ld.global.u32 @@ -24,7 +24,3 @@ define void @foo(ptr %a, ptr %b) { store i32 %ld2, ptr %b ret void } - - -!nvvm.annotations = !{!0} -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/i1-array-global.ll b/llvm/test/CodeGen/NVPTX/i1-array-global.ll index ff3848b6f8f7..20b376f94c0d 100644 --- a/llvm/test/CodeGen/NVPTX/i1-array-global.ll +++ b/llvm/test/CodeGen/NVPTX/i1-array-global.ll @@ -7,13 +7,9 @@ target triple = "nvptx-nvidia-cuda" @global_cst = private constant [6 x i1] [i1 true, i1 false, i1 true, i1 false, i1 true, i1 false] ; CHECK: .global .align 1 .b8 global_cst[6] = {1, 0, 1, 0, 1} -define void @kernel(i32 %i, ptr %out) { +define ptx_kernel void @kernel(i32 %i, ptr %out) { %5 = getelementptr inbounds i1, ptr @global_cst, i32 %i %6 = load i1, ptr %5, align 1 store i1 %6, ptr %out, align 1 ret void } - -!nvvm.annotations = !{!0} -!0 = !{ptr @kernel, !"kernel", i32 1} - diff --git a/llvm/test/CodeGen/NVPTX/i1-ext-load.ll b/llvm/test/CodeGen/NVPTX/i1-ext-load.ll index 83f8f80919f8..f5f1dd9fcf0e 100644 --- a/llvm/test/CodeGen/NVPTX/i1-ext-load.ll +++ b/llvm/test/CodeGen/NVPTX/i1-ext-load.ll @@ -5,7 +5,7 @@ target triple = "nvptx-nvidia-cuda" -define void @foo(ptr noalias readonly %ptr, ptr noalias %retval) { +define ptx_kernel void @foo(ptr noalias readonly %ptr, ptr noalias %retval) { ; CHECK-LABEL: foo( ; CHECK: .reg .b16 %rs<2>; ; CHECK: .reg .b32 %r<4>; @@ -28,7 +28,3 @@ define void @foo(ptr noalias readonly %ptr, ptr noalias %retval) { store i32 %and, ptr %retval ret void } - -!nvvm.annotations = !{!0} - -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/i1-global.ll b/llvm/test/CodeGen/NVPTX/i1-global.ll index 17af1fa29e6c..60d2ccd46419 100644 --- a/llvm/test/CodeGen/NVPTX/i1-global.ll +++ b/llvm/test/CodeGen/NVPTX/i1-global.ll @@ -8,13 +8,9 @@ target triple = "nvptx-nvidia-cuda" @mypred = addrspace(1) global i1 true, align 1 -define void @foo(i1 %p, ptr %out) { +define ptx_kernel void @foo(i1 %p, ptr %out) { %ld = load i1, ptr addrspace(1) @mypred %val = zext i1 %ld to i32 store i32 %val, ptr %out ret void } - - -!nvvm.annotations = !{!0} -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/i1-param.ll b/llvm/test/CodeGen/NVPTX/i1-param.ll index 3c74ee6aaa3b..14d417bca459 100644 --- a/llvm/test/CodeGen/NVPTX/i1-param.ll +++ b/llvm/test/CodeGen/NVPTX/i1-param.ll @@ -9,12 +9,8 @@ target triple = "nvptx-nvidia-cuda" ; CHECK: .entry foo ; CHECK: .param .u8 foo_param_0 ; CHECK: .param .u64 .ptr .align 1 foo_param_1 -define void @foo(i1 %p, ptr %out) { +define ptx_kernel void @foo(i1 %p, ptr %out) { %val = zext i1 %p to i32 store i32 %val, ptr %out ret void } - - -!nvvm.annotations = !{!0} -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/intr-range.ll b/llvm/test/CodeGen/NVPTX/intr-range.ll index 2f3e08a039f5..86776ab09efc 100644 --- a/llvm/test/CodeGen/NVPTX/intr-range.ll +++ b/llvm/test/CodeGen/NVPTX/intr-range.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --version 5 ; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -mcpu=sm_20 -passes=nvvm-intr-range | FileCheck %s -define i32 @test_maxntid() { -; CHECK-LABEL: define i32 @test_maxntid( +define ptx_kernel i32 @test_maxntid() { +; CHECK-LABEL: define ptx_kernel i32 @test_maxntid( ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 96) i32 @llvm.nvvm.read.ptx.sreg.tid.x() ; CHECK-NEXT: [[TMP3:%.*]] = call range(i32 0, 96) i32 @llvm.nvvm.read.ptx.sreg.tid.y() @@ -31,8 +31,8 @@ define i32 @test_maxntid() { ret i32 %11 } -define i32 @test_reqntid() { -; CHECK-LABEL: define i32 @test_reqntid( +define ptx_kernel i32 @test_reqntid() { +; CHECK-LABEL: define ptx_kernel i32 @test_reqntid( ; CHECK-SAME: ) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 20) i32 @llvm.nvvm.read.ptx.sreg.tid.x() ; CHECK-NEXT: [[TMP5:%.*]] = call range(i32 0, 20) i32 @llvm.nvvm.read.ptx.sreg.tid.y() @@ -64,8 +64,8 @@ define i32 @test_reqntid() { ;; A case like this could occur if a function with the sreg intrinsic was ;; inlined into a kernel where the tid metadata is present, ensure the range is ;; updated. -define i32 @test_inlined() { -; CHECK-LABEL: define i32 @test_inlined( +define ptx_kernel i32 @test_inlined() { +; CHECK-LABEL: define ptx_kernel i32 @test_inlined( ; CHECK-SAME: ) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 4) i32 @llvm.nvvm.read.ptx.sreg.tid.x() ; CHECK-NEXT: ret i32 [[TMP1]] @@ -83,6 +83,6 @@ declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y() declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z() !nvvm.annotations = !{!0, !1, !2} -!0 = !{ptr @test_maxntid, !"kernel", i32 1, !"maxntidx", i32 32, !"maxntidz", i32 3} -!1 = !{ptr @test_reqntid, !"kernel", i32 1, !"reqntidx", i32 20} -!2 = !{ptr @test_inlined, !"kernel", i32 1, !"maxntidx", i32 4} +!0 = !{ptr @test_maxntid, !"maxntidx", i32 32, !"maxntidz", i32 3} +!1 = !{ptr @test_reqntid, !"reqntidx", i32 20} +!2 = !{ptr @test_inlined, !"maxntidx", i32 4} diff --git a/llvm/test/CodeGen/NVPTX/kernel-param-align.ll b/llvm/test/CodeGen/NVPTX/kernel-param-align.ll index 93d428d6fe6f..2889d2d89a85 100644 --- a/llvm/test/CodeGen/NVPTX/kernel-param-align.ll +++ b/llvm/test/CodeGen/NVPTX/kernel-param-align.ll @@ -10,7 +10,7 @@ ; CHECK: .param .u64 .ptr .shared .align 8 func_align_param_3 ; CHECK: .param .u64 .ptr .const .align 16 func_align_param_4 ; CHECK: .param .u64 .ptr .local .align 32 func_align_param_5 -define void @func_align(ptr nocapture readonly align 1 %input, +define ptx_kernel void @func_align(ptr nocapture readonly align 1 %input, ptr nocapture align 2 %out, ptr addrspace(1) align 4 %global, ptr addrspace(3) align 8 %shared, @@ -27,7 +27,7 @@ entry: ; CHECK: .param .u64 .ptr .shared .align 1 func_noalign_param_3 ; CHECK: .param .u64 .ptr .const .align 1 func_noalign_param_4 ; CHECK: .param .u64 .ptr .local .align 1 func_noalign_param_5 -define void @func_noalign(ptr nocapture readonly %input, +define ptx_kernel void @func_noalign(ptr nocapture readonly %input, ptr nocapture %out, ptr addrspace(1) %global, ptr addrspace(3) %shared, @@ -36,7 +36,3 @@ define void @func_noalign(ptr nocapture readonly %input, entry: ret void } - -!nvvm.annotations = !{!0, !1} -!0 = !{ptr @func_align, !"kernel", i32 1} -!1 = !{ptr @func_noalign, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll b/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll index bdaeccd53fac..dc1917f3b150 100644 --- a/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll +++ b/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll @@ -10,7 +10,7 @@ target triple = "nvptx64-unknown-unknown" ; SM20: ld.global.f32 ; SM35-LABEL: .visible .entry foo1( ; SM35: ld.global.nc.f32 -define void @foo1(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo1(ptr noalias readonly %from, ptr %to) { %1 = load float, ptr %from store float %1, ptr %to ret void @@ -20,7 +20,7 @@ define void @foo1(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.f64 ; SM35-LABEL: .visible .entry foo2( ; SM35: ld.global.nc.f64 -define void @foo2(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo2(ptr noalias readonly %from, ptr %to) { %1 = load double, ptr %from store double %1, ptr %to ret void @@ -30,7 +30,7 @@ define void @foo2(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u16 ; SM35-LABEL: .visible .entry foo3( ; SM35: ld.global.nc.u16 -define void @foo3(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo3(ptr noalias readonly %from, ptr %to) { %1 = load i16, ptr %from store i16 %1, ptr %to ret void @@ -40,7 +40,7 @@ define void @foo3(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u32 ; SM35-LABEL: .visible .entry foo4( ; SM35: ld.global.nc.u32 -define void @foo4(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo4(ptr noalias readonly %from, ptr %to) { %1 = load i32, ptr %from store i32 %1, ptr %to ret void @@ -50,7 +50,7 @@ define void @foo4(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u64 ; SM35-LABEL: .visible .entry foo5( ; SM35: ld.global.nc.u64 -define void @foo5(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo5(ptr noalias readonly %from, ptr %to) { %1 = load i64, ptr %from store i64 %1, ptr %to ret void @@ -63,7 +63,7 @@ define void @foo5(ptr noalias readonly %from, ptr %to) { ; SM35-LABEL: .visible .entry foo6( ; SM35: ld.global.nc.u64 ; SM35: ld.global.nc.u64 -define void @foo6(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo6(ptr noalias readonly %from, ptr %to) { %1 = load i128, ptr %from store i128 %1, ptr %to ret void @@ -73,7 +73,7 @@ define void @foo6(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.u8 ; SM35-LABEL: .visible .entry foo7( ; SM35: ld.global.nc.v2.u8 -define void @foo7(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo7(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i8>, ptr %from store <2 x i8> %1, ptr %to ret void @@ -83,7 +83,7 @@ define void @foo7(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u32 ; SM35-LABEL: .visible .entry foo8( ; SM35: ld.global.nc.u32 -define void @foo8(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo8(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i16>, ptr %from store <2 x i16> %1, ptr %to ret void @@ -93,7 +93,7 @@ define void @foo8(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.u32 ; SM35-LABEL: .visible .entry foo9( ; SM35: ld.global.nc.v2.u32 -define void @foo9(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo9(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i32>, ptr %from store <2 x i32> %1, ptr %to ret void @@ -103,7 +103,7 @@ define void @foo9(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.u64 ; SM35-LABEL: .visible .entry foo10( ; SM35: ld.global.nc.v2.u64 -define void @foo10(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo10(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i64>, ptr %from store <2 x i64> %1, ptr %to ret void @@ -113,7 +113,7 @@ define void @foo10(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.f32 ; SM35-LABEL: .visible .entry foo11( ; SM35: ld.global.nc.v2.f32 -define void @foo11(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo11(ptr noalias readonly %from, ptr %to) { %1 = load <2 x float>, ptr %from store <2 x float> %1, ptr %to ret void @@ -123,7 +123,7 @@ define void @foo11(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.f64 ; SM35-LABEL: .visible .entry foo12( ; SM35: ld.global.nc.v2.f64 -define void @foo12(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo12(ptr noalias readonly %from, ptr %to) { %1 = load <2 x double>, ptr %from store <2 x double> %1, ptr %to ret void @@ -133,7 +133,7 @@ define void @foo12(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u32 ; SM35-LABEL: .visible .entry foo13( ; SM35: ld.global.nc.u32 -define void @foo13(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo13(ptr noalias readonly %from, ptr %to) { %1 = load <4 x i8>, ptr %from store <4 x i8> %1, ptr %to ret void @@ -143,7 +143,7 @@ define void @foo13(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v4.u16 ; SM35-LABEL: .visible .entry foo14( ; SM35: ld.global.nc.v4.u16 -define void @foo14(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo14(ptr noalias readonly %from, ptr %to) { %1 = load <4 x i16>, ptr %from store <4 x i16> %1, ptr %to ret void @@ -153,7 +153,7 @@ define void @foo14(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v4.u32 ; SM35-LABEL: .visible .entry foo15( ; SM35: ld.global.nc.v4.u32 -define void @foo15(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo15(ptr noalias readonly %from, ptr %to) { %1 = load <4 x i32>, ptr %from store <4 x i32> %1, ptr %to ret void @@ -163,7 +163,7 @@ define void @foo15(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v4.f32 ; SM35-LABEL: .visible .entry foo16( ; SM35: ld.global.nc.v4.f32 -define void @foo16(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo16(ptr noalias readonly %from, ptr %to) { %1 = load <4 x float>, ptr %from store <4 x float> %1, ptr %to ret void @@ -175,7 +175,7 @@ define void @foo16(ptr noalias readonly %from, ptr %to) { ; SM35-LABEL: .visible .entry foo17( ; SM35: ld.global.nc.v2.f64 ; SM35: ld.global.nc.v2.f64 -define void @foo17(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo17(ptr noalias readonly %from, ptr %to) { %1 = load <4 x double>, ptr %from store <4 x double> %1, ptr %to ret void @@ -185,7 +185,7 @@ define void @foo17(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u64 ; SM35-LABEL: .visible .entry foo18( ; SM35: ld.global.nc.u64 -define void @foo18(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo18(ptr noalias readonly %from, ptr %to) { %1 = load ptr, ptr %from store ptr %1, ptr %to ret void @@ -196,7 +196,7 @@ define void @foo18(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.f32 ; SM35-LABEL: .visible .entry foo19( ; SM35: ld.global.nc.f32 -define void @foo19(ptr noalias readonly %from, ptr %to, i32 %n) { +define ptx_kernel void @foo19(ptr noalias readonly %from, ptr %to, i32 %n) { entry: br label %loop @@ -243,24 +243,3 @@ define void @notkernel2(ptr addrspace(1) noalias readonly %from, ptr %to) { store float %1, ptr %to ret void } - -!nvvm.annotations = !{!1 ,!2 ,!3 ,!4 ,!5 ,!6, !7 ,!8 ,!9 ,!10 ,!11 ,!12, !13, !14, !15, !16, !17, !18, !19} -!1 = !{ptr @foo1, !"kernel", i32 1} -!2 = !{ptr @foo2, !"kernel", i32 1} -!3 = !{ptr @foo3, !"kernel", i32 1} -!4 = !{ptr @foo4, !"kernel", i32 1} -!5 = !{ptr @foo5, !"kernel", i32 1} -!6 = !{ptr @foo6, !"kernel", i32 1} -!7 = !{ptr @foo7, !"kernel", i32 1} -!8 = !{ptr @foo8, !"kernel", i32 1} -!9 = !{ptr @foo9, !"kernel", i32 1} -!10 = !{ptr @foo10, !"kernel", i32 1} -!11 = !{ptr @foo11, !"kernel", i32 1} -!12 = !{ptr @foo12, !"kernel", i32 1} -!13 = !{ptr @foo13, !"kernel", i32 1} -!14 = !{ptr @foo14, !"kernel", i32 1} -!15 = !{ptr @foo15, !"kernel", i32 1} -!16 = !{ptr @foo16, !"kernel", i32 1} -!17 = !{ptr @foo17, !"kernel", i32 1} -!18 = !{ptr @foo18, !"kernel", i32 1} -!19 = !{ptr @foo19, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/local-stack-frame.ll b/llvm/test/CodeGen/NVPTX/local-stack-frame.ll index e42f2303cdf7..f21ff974a2c6 100644 --- a/llvm/test/CodeGen/NVPTX/local-stack-frame.ll +++ b/llvm/test/CodeGen/NVPTX/local-stack-frame.ll @@ -29,7 +29,7 @@ define void @foo(i32 %a) { ; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0]; ; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0; ; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}}; -define void @foo2(i32 %a) { +define ptx_kernel void @foo2(i32 %a) { %local = alloca i32, align 4 store i32 %a, ptr %local call void @bar(ptr %local) @@ -38,8 +38,6 @@ define void @foo2(i32 %a) { declare void @bar(ptr %a) -!nvvm.annotations = !{!0} -!0 = !{ptr @foo2, !"kernel", i32 1} ; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}}; ; PTX32-NOT: cvta.local.u32 %SP, %SPL; diff --git a/llvm/test/CodeGen/NVPTX/lower-alloca.ll b/llvm/test/CodeGen/NVPTX/lower-alloca.ll index 8f2d55151b31..530b48b3d3e3 100644 --- a/llvm/test/CodeGen/NVPTX/lower-alloca.ll +++ b/llvm/test/CodeGen/NVPTX/lower-alloca.ll @@ -6,7 +6,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" target triple = "nvptx64-unknown-unknown" -define void @kernel() { +define ptx_kernel void @kernel() { ; LABEL: @lower_alloca ; PTX-LABEL: .visible .entry kernel( %A = alloca i32 @@ -37,7 +37,5 @@ define void @alloca_in_explicit_local_as() { declare void @callee(ptr) declare void @callee_addrspace5(ptr addrspace(5)) -!nvvm.annotations = !{!0} !nvvm.annotations = !{!1} -!0 = !{ptr @kernel, !"kernel", i32 1} !1 = !{ptr @alloca_in_explicit_local_as, !"alloca_in_explicit_local_as", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll b/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll index 9cfe9192772b..208d4f0ef32a 100644 --- a/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll +++ b/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll @@ -29,7 +29,7 @@ define dso_local noundef i32 @non_kernel_function(ptr nocapture noundef readonly ; PTX-NEXT: .reg .pred %p<2>; ; PTX-NEXT: .reg .b16 %rs<3>; ; PTX-NEXT: .reg .b32 %r<11>; -; PTX-NEXT: .reg .b64 %rd<10>; +; PTX-NEXT: .reg .b64 %rd<9>; ; PTX-EMPTY: ; PTX-NEXT: // %bb.0: // %entry ; PTX-NEXT: mov.u64 %SPL, __local_depot0; @@ -38,23 +38,22 @@ define dso_local noundef i32 @non_kernel_function(ptr nocapture noundef readonly ; PTX-NEXT: and.b16 %rs2, %rs1, 1; ; PTX-NEXT: setp.eq.b16 %p1, %rs2, 1; ; PTX-NEXT: ld.param.s32 %rd1, [non_kernel_function_param_2]; -; PTX-NEXT: add.u64 %rd2, %SP, 0; -; PTX-NEXT: or.b64 %rd3, %rd2, 8; -; PTX-NEXT: ld.param.u64 %rd4, [non_kernel_function_param_0+8]; -; PTX-NEXT: st.u64 [%rd3], %rd4; -; PTX-NEXT: ld.param.u64 %rd5, [non_kernel_function_param_0]; -; PTX-NEXT: st.u64 [%SP], %rd5; -; PTX-NEXT: mov.u64 %rd6, gi; -; PTX-NEXT: cvta.global.u64 %rd7, %rd6; -; PTX-NEXT: selp.b64 %rd8, %rd2, %rd7, %p1; -; PTX-NEXT: add.s64 %rd9, %rd8, %rd1; -; PTX-NEXT: ld.u8 %r1, [%rd9]; -; PTX-NEXT: ld.u8 %r2, [%rd9+1]; +; PTX-NEXT: ld.param.u64 %rd2, [non_kernel_function_param_0+8]; +; PTX-NEXT: st.u64 [%SP+8], %rd2; +; PTX-NEXT: ld.param.u64 %rd3, [non_kernel_function_param_0]; +; PTX-NEXT: st.u64 [%SP], %rd3; +; PTX-NEXT: mov.u64 %rd4, gi; +; PTX-NEXT: cvta.global.u64 %rd5, %rd4; +; PTX-NEXT: add.u64 %rd6, %SP, 0; +; PTX-NEXT: selp.b64 %rd7, %rd6, %rd5, %p1; +; PTX-NEXT: add.s64 %rd8, %rd7, %rd1; +; PTX-NEXT: ld.u8 %r1, [%rd8]; +; PTX-NEXT: ld.u8 %r2, [%rd8+1]; ; PTX-NEXT: shl.b32 %r3, %r2, 8; ; PTX-NEXT: or.b32 %r4, %r3, %r1; -; PTX-NEXT: ld.u8 %r5, [%rd9+2]; +; PTX-NEXT: ld.u8 %r5, [%rd8+2]; ; PTX-NEXT: shl.b32 %r6, %r5, 16; -; PTX-NEXT: ld.u8 %r7, [%rd9+3]; +; PTX-NEXT: ld.u8 %r7, [%rd8+3]; ; PTX-NEXT: shl.b32 %r8, %r7, 24; ; PTX-NEXT: or.b32 %r9, %r8, %r6; ; PTX-NEXT: or.b32 %r10, %r9, %r4; @@ -68,7 +67,7 @@ entry: ret i32 %0, !dbg !23 } -define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %out, i32 %n) { +define ptx_kernel void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %out, i32 %n) { ; PTX-LABEL: grid_const_int( ; PTX: { ; PTX-NEXT: .reg .b32 %r<4>; @@ -82,7 +81,7 @@ define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %ou ; PTX-NEXT: add.s32 %r3, %r2, %r1; ; PTX-NEXT: st.global.u32 [%rd2], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_int( +; OPT-LABEL: define ptx_kernel void @grid_const_int( ; OPT-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], i32 [[INPUT2:%.*]], ptr [[OUT:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUT2:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUT3:%.*]] = addrspacecast ptr addrspace(1) [[OUT2]] to ptr @@ -91,6 +90,7 @@ define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %ou ; OPT-NEXT: [[ADD:%.*]] = add i32 [[TMP]], [[INPUT2]] ; OPT-NEXT: store i32 [[ADD]], ptr [[OUT3]], align 4 ; OPT-NEXT: ret void +; %tmp = load i32, ptr %input1, align 4 %add = add i32 %tmp, %input2 store i32 %add, ptr %out @@ -99,7 +99,7 @@ define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %ou %struct.s = type { i32, i32 } -define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ +define ptx_kernel void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ; PTX-LABEL: grid_const_struct( ; PTX: { ; PTX-NEXT: .reg .b32 %r<4>; @@ -113,7 +113,7 @@ define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ; PTX-NEXT: add.s32 %r3, %r1, %r2; ; PTX-NEXT: st.global.u32 [%rd2], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_struct( +; OPT-LABEL: define ptx_kernel void @grid_const_struct( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[OUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUT4:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUT5:%.*]] = addrspacecast ptr addrspace(1) [[OUT4]] to ptr @@ -125,6 +125,7 @@ define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ; OPT-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[TMP2]] ; OPT-NEXT: store i32 [[ADD]], ptr [[OUT5]], align 4 ; OPT-NEXT: ret void +; %gep1 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 0 %gep2 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 1 %int1 = load i32, ptr %gep1 @@ -134,7 +135,7 @@ define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ret void } -define void @grid_const_escape(ptr byval(%struct.s) align 4 %input) { +define ptx_kernel void @grid_const_escape(ptr byval(%struct.s) align 4 %input) { ; PTX-LABEL: grid_const_escape( ; PTX: { ; PTX-NEXT: .reg .b32 %r<3>; @@ -159,17 +160,18 @@ define void @grid_const_escape(ptr byval(%struct.s) align 4 %input) { ; PTX-NEXT: ld.param.b32 %r1, [retval0]; ; PTX-NEXT: } // callseq 0 ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INPUT_PARAM:%.*]] = addrspacecast ptr [[INPUT]] to ptr addrspace(101) ; OPT-NEXT: [[INPUT_PARAM_GEN:%.*]] = call ptr @llvm.nvvm.ptr.param.to.gen.p0.p101(ptr addrspace(101) [[INPUT_PARAM]]) ; OPT-NEXT: [[CALL:%.*]] = call i32 @escape(ptr [[INPUT_PARAM_GEN]]) ; OPT-NEXT: ret void +; %call = call i32 @escape(ptr %input) ret void } -define void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 %a, ptr byval(i32) align 4 %b) { +define ptx_kernel void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 %a, ptr byval(i32) align 4 %b) { ; PTX-LABEL: multiple_grid_const_escape( ; PTX: { ; PTX-NEXT: .local .align 4 .b8 __local_depot4[4]; @@ -212,7 +214,7 @@ define void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 ; PTX-NEXT: ld.param.b32 %r2, [retval0]; ; PTX-NEXT: } // callseq 1 ; PTX-NEXT: ret; -; OPT-LABEL: define void @multiple_grid_const_escape( +; OPT-LABEL: define ptx_kernel void @multiple_grid_const_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], i32 [[A:%.*]], ptr byval(i32) align 4 [[B:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[B_PARAM:%.*]] = addrspacecast ptr [[B]] to ptr addrspace(101) ; OPT-NEXT: [[B_PARAM_GEN:%.*]] = call ptr @llvm.nvvm.ptr.param.to.gen.p0.p101(ptr addrspace(101) [[B_PARAM]]) @@ -222,13 +224,14 @@ define void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 ; OPT-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 ; OPT-NEXT: [[CALL:%.*]] = call i32 @escape3(ptr [[INPUT_PARAM_GEN]], ptr [[A_ADDR]], ptr [[B_PARAM_GEN]]) ; OPT-NEXT: ret void +; %a.addr = alloca i32, align 4 store i32 %a, ptr %a.addr, align 4 %call = call i32 @escape3(ptr %input, ptr %a.addr, ptr %b) ret void } -define void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr %addr) { +define ptx_kernel void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr %addr) { ; PTX-LABEL: grid_const_memory_escape( ; PTX: { ; PTX-NEXT: .reg .b64 %rd<6>; @@ -241,7 +244,7 @@ define void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr % ; PTX-NEXT: cvta.param.u64 %rd5, %rd4; ; PTX-NEXT: st.global.u64 [%rd3], %rd5; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_memory_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_memory_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[ADDR:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[ADDR4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1) ; OPT-NEXT: [[ADDR5:%.*]] = addrspacecast ptr addrspace(1) [[ADDR4]] to ptr @@ -249,11 +252,12 @@ define void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr % ; OPT-NEXT: [[INPUT1:%.*]] = call ptr @llvm.nvvm.ptr.param.to.gen.p0.p101(ptr addrspace(101) [[INPUT_PARAM]]) ; OPT-NEXT: store ptr [[INPUT1]], ptr [[ADDR5]], align 8 ; OPT-NEXT: ret void +; store ptr %input, ptr %addr, align 8 ret void } -define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, ptr %result) { +define ptx_kernel void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, ptr %result) { ; PTX-LABEL: grid_const_inlineasm_escape( ; PTX: { ; PTX-NEXT: .reg .b64 %rd<8>; @@ -271,7 +275,7 @@ define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, pt ; PTX-NEXT: st.global.u64 [%rd6], %rd1; ; PTX-NEXT: ret; ; PTX-NOT .local -; OPT-LABEL: define void @grid_const_inlineasm_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_inlineasm_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[RESULT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[RESULT4:%.*]] = addrspacecast ptr [[RESULT]] to ptr addrspace(1) ; OPT-NEXT: [[RESULT5:%.*]] = addrspacecast ptr addrspace(1) [[RESULT4]] to ptr @@ -282,6 +286,7 @@ define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, pt ; OPT-NEXT: [[TMP2:%.*]] = call i64 asm "add.s64 $0, $1, $2 ; OPT-NEXT: store i64 [[TMP2]], ptr [[RESULT5]], align 8 ; OPT-NEXT: ret void +; %tmpptr1 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 0 %tmpptr2 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 1 %1 = call i64 asm "add.s64 $0, $1, $2;", "=l,l,l"(ptr %tmpptr1, ptr %tmpptr2) #1 @@ -289,7 +294,7 @@ define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, pt ret void } -define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { +define ptx_kernel void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ; PTX-LABEL: grid_const_partial_escape( ; PTX: { ; PTX-NEXT: .reg .b32 %r<5>; @@ -319,7 +324,7 @@ define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ; PTX-NEXT: ld.param.b32 %r3, [retval0]; ; PTX-NEXT: } // callseq 2 ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_partial_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_partial_escape( ; OPT-SAME: ptr byval(i32) [[INPUT:%.*]], ptr [[OUTPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUTPUT4:%.*]] = addrspacecast ptr [[OUTPUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUTPUT5:%.*]] = addrspacecast ptr addrspace(1) [[OUTPUT4]] to ptr @@ -330,6 +335,7 @@ define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ; OPT-NEXT: store i32 [[TWICE]], ptr [[OUTPUT5]], align 4 ; OPT-NEXT: [[CALL:%.*]] = call i32 @escape(ptr [[INPUT1_GEN]]) ; OPT-NEXT: ret void +; %val = load i32, ptr %input %twice = add i32 %val, %val store i32 %twice, ptr %output @@ -337,7 +343,7 @@ define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ret void } -define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %output) { +define ptx_kernel i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %output) { ; PTX-LABEL: grid_const_partial_escapemem( ; PTX: { ; PTX-NEXT: .reg .b32 %r<6>; @@ -369,7 +375,7 @@ define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %outpu ; PTX-NEXT: } // callseq 3 ; PTX-NEXT: st.param.b32 [func_retval0], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define i32 @grid_const_partial_escapemem( +; OPT-LABEL: define ptx_kernel i32 @grid_const_partial_escapemem( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) [[INPUT:%.*]], ptr [[OUTPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUTPUT4:%.*]] = addrspacecast ptr [[OUTPUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUTPUT5:%.*]] = addrspacecast ptr addrspace(1) [[OUTPUT4]] to ptr @@ -383,6 +389,7 @@ define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %outpu ; OPT-NEXT: [[ADD:%.*]] = add i32 [[VAL1]], [[VAL2]] ; OPT-NEXT: [[CALL2:%.*]] = call i32 @escape(ptr [[PTR1]]) ; OPT-NEXT: ret i32 [[ADD]] +; %ptr1 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 0 %val1 = load i32, ptr %ptr1 %ptr2 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 1 @@ -393,7 +400,7 @@ define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %outpu ret i32 %add } -define void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { +define ptx_kernel void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { ; PTX-LABEL: grid_const_phi( ; PTX: { ; PTX-NEXT: .reg .pred %p<2>; @@ -415,7 +422,7 @@ define void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { ; PTX-NEXT: ld.u32 %r2, [%rd8]; ; PTX-NEXT: st.global.u32 [%rd1], %r2; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_phi( +; OPT-LABEL: define ptx_kernel void @grid_const_phi( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) ; OPT-NEXT: [[INOUT2:%.*]] = addrspacecast ptr addrspace(1) [[INOUT1]] to ptr @@ -435,6 +442,7 @@ define void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { ; OPT-NEXT: [[VALLOADED:%.*]] = load i32, ptr [[PTRNEW]], align 4 ; OPT-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; OPT-NEXT: ret void +; %val = load i32, ptr %inout %less = icmp slt i32 %val, 0 @@ -453,7 +461,7 @@ merge: } ; NOTE: %input2 is *not* grid_constant -define void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval(%struct.s) %input2, ptr %inout) { +define ptx_kernel void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval(%struct.s) %input2, ptr %inout) { ; PTX-LABEL: grid_const_phi_ngc( ; PTX: { ; PTX-NEXT: .reg .pred %p<2>; @@ -478,7 +486,7 @@ define void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval( ; PTX-NEXT: ld.u32 %r2, [%rd11]; ; PTX-NEXT: st.global.u32 [%rd1], %r2; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_phi_ngc( +; OPT-LABEL: define ptx_kernel void @grid_const_phi_ngc( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) ; OPT-NEXT: [[INOUT2:%.*]] = addrspacecast ptr addrspace(1) [[INOUT1]] to ptr @@ -500,6 +508,7 @@ define void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval( ; OPT-NEXT: [[VALLOADED:%.*]] = load i32, ptr [[PTRNEW]], align 4 ; OPT-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; OPT-NEXT: ret void +; %val = load i32, ptr %inout %less = icmp slt i32 %val, 0 br i1 %less, label %first, label %second @@ -517,7 +526,7 @@ merge: } ; NOTE: %input2 is *not* grid_constant -define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %inout) { +define ptx_kernel void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %inout) { ; PTX-LABEL: grid_const_select( ; PTX: { ; PTX-NEXT: .reg .pred %p<2>; @@ -539,7 +548,7 @@ define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; PTX-NEXT: ld.u32 %r2, [%rd9]; ; PTX-NEXT: st.global.u32 [%rd3], %r2; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_select( +; OPT-LABEL: define ptx_kernel void @grid_const_select( ; OPT-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) ; OPT-NEXT: [[INOUT2:%.*]] = addrspacecast ptr addrspace(1) [[INOUT1]] to ptr @@ -553,6 +562,7 @@ define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; OPT-NEXT: [[VALLOADED:%.*]] = load i32, ptr [[PTRNEW]], align 4 ; OPT-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; OPT-NEXT: ret void +; %val = load i32, ptr %inout %less = icmp slt i32 %val, 0 %ptrnew = select i1 %less, ptr %input1, ptr %input2 @@ -561,7 +571,7 @@ define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ret void } -define i32 @grid_const_ptrtoint(ptr byval(i32) %input) { +define ptx_kernel i32 @grid_const_ptrtoint(ptr byval(i32) %input) { ; PTX-LABEL: grid_const_ptrtoint( ; PTX: { ; PTX-NEXT: .reg .b32 %r<4>; @@ -576,7 +586,7 @@ define i32 @grid_const_ptrtoint(ptr byval(i32) %input) { ; PTX-NEXT: add.s32 %r3, %r1, %r2; ; PTX-NEXT: st.param.b32 [func_retval0], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define i32 @grid_const_ptrtoint( +; OPT-LABEL: define ptx_kernel i32 @grid_const_ptrtoint( ; OPT-SAME: ptr byval(i32) align 4 [[INPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INPUT2:%.*]] = addrspacecast ptr [[INPUT]] to ptr addrspace(101) ; OPT-NEXT: [[INPUT3:%.*]] = load i32, ptr addrspace(101) [[INPUT2]], align 4 @@ -584,6 +594,7 @@ define i32 @grid_const_ptrtoint(ptr byval(i32) %input) { ; OPT-NEXT: [[PTRVAL:%.*]] = ptrtoint ptr [[INPUT1]] to i32 ; OPT-NEXT: [[KEEPALIVE:%.*]] = add i32 [[INPUT3]], [[PTRVAL]] ; OPT-NEXT: ret i32 [[KEEPALIVE]] +; %val = load i32, ptr %input %ptrval = ptrtoint ptr %input to i32 %keepalive = add i32 %val, %ptrval @@ -598,40 +609,40 @@ declare dso_local ptr @escape3(ptr, ptr, ptr) local_unnamed_addr !nvvm.annotations = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23} -!0 = !{ptr @grid_const_int, !"kernel", i32 1, !"grid_constant", !1} +!0 = !{ptr @grid_const_int, !"grid_constant", !1} !1 = !{i32 1} -!2 = !{ptr @grid_const_struct, !"kernel", i32 1, !"grid_constant", !3} +!2 = !{ptr @grid_const_struct, !"grid_constant", !3} !3 = !{i32 1} -!4 = !{ptr @grid_const_escape, !"kernel", i32 1, !"grid_constant", !5} +!4 = !{ptr @grid_const_escape, !"grid_constant", !5} !5 = !{i32 1} -!6 = !{ptr @multiple_grid_const_escape, !"kernel", i32 1, !"grid_constant", !7} +!6 = !{ptr @multiple_grid_const_escape, !"grid_constant", !7} !7 = !{i32 1, i32 3} -!8 = !{ptr @grid_const_memory_escape, !"kernel", i32 1, !"grid_constant", !9} +!8 = !{ptr @grid_const_memory_escape, !"grid_constant", !9} !9 = !{i32 1} -!10 = !{ptr @grid_const_inlineasm_escape, !"kernel", i32 1, !"grid_constant", !11} +!10 = !{ptr @grid_const_inlineasm_escape, !"grid_constant", !11} !11 = !{i32 1} -!12 = !{ptr @grid_const_partial_escape, !"kernel", i32 1, !"grid_constant", !13} +!12 = !{ptr @grid_const_partial_escape, !"grid_constant", !13} !13 = !{i32 1} -!14 = !{ptr @grid_const_partial_escapemem, !"kernel", i32 1, !"grid_constant", !15} +!14 = !{ptr @grid_const_partial_escapemem, !"grid_constant", !15} !15 = !{i32 1} -!16 = !{ptr @grid_const_phi, !"kernel", i32 1, !"grid_constant", !17} +!16 = !{ptr @grid_const_phi, !"grid_constant", !17} !17 = !{i32 1} -!18 = !{ptr @grid_const_phi_ngc, !"kernel", i32 1, !"grid_constant", !19} +!18 = !{ptr @grid_const_phi_ngc, !"grid_constant", !19} !19 = !{i32 1} -!20 = !{ptr @grid_const_select, !"kernel", i32 1, !"grid_constant", !21} +!20 = !{ptr @grid_const_select, !"grid_constant", !21} !21 = !{i32 1} -!22 = !{ptr @grid_const_ptrtoint, !"kernel", i32 1, !"grid_constant", !23} +!22 = !{ptr @grid_const_ptrtoint, !"grid_constant", !23} !23 = !{i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-args.ll b/llvm/test/CodeGen/NVPTX/lower-args.ll index eba4f273fa70..269bba75dc5f 100644 --- a/llvm/test/CodeGen/NVPTX/lower-args.ll +++ b/llvm/test/CodeGen/NVPTX/lower-args.ll @@ -65,7 +65,7 @@ define void @load_padding(ptr nocapture readonly byval(%class.padded) %arg) { } ; COMMON-LABEL: ptr_generic -define void @ptr_generic(ptr %out, ptr %in) { +define ptx_kernel void @ptr_generic(ptr %out, ptr %in) { ; IRC: %in3 = addrspacecast ptr %in to ptr addrspace(1) ; IRC: %in4 = addrspacecast ptr addrspace(1) %in3 to ptr ; IRC: %out1 = addrspacecast ptr %out to ptr addrspace(1) @@ -87,7 +87,7 @@ define void @ptr_generic(ptr %out, ptr %in) { } ; COMMON-LABEL: ptr_nongeneric -define void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { +define ptx_kernel void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { ; IR-NOT: addrspacecast ; PTX-NOT: cvta.to.global ; PTX: ld.const.u32 @@ -98,7 +98,7 @@ define void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { } ; COMMON-LABEL: ptr_as_int - define void @ptr_as_int(i64 noundef %i, i32 noundef %v) { + define ptx_kernel void @ptr_as_int(i64 noundef %i, i32 noundef %v) { ; IR: [[P:%.*]] = inttoptr i64 %i to ptr ; IRC: [[P1:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1) ; IRC: addrspacecast ptr addrspace(1) [[P1]] to ptr @@ -121,7 +121,7 @@ define void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { %struct.S = type { i64 } ; COMMON-LABEL: ptr_as_int_aggr -define void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) align 8 %s, i32 noundef %v) { +define ptx_kernel void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) align 8 %s, i32 noundef %v) { ; IR: [[S:%.*]] = addrspacecast ptr %s to ptr addrspace(101) ; IR: [[I:%.*]] = load i64, ptr addrspace(101) [[S]], align 8 ; IR: [[P0:%.*]] = inttoptr i64 [[I]] to ptr @@ -146,8 +146,3 @@ define void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) ali ; Function Attrs: convergent nounwind declare dso_local ptr @escape(ptr) local_unnamed_addr -!nvvm.annotations = !{!0, !1, !2, !3} -!0 = !{ptr @ptr_generic, !"kernel", i32 1} -!1 = !{ptr @ptr_nongeneric, !"kernel", i32 1} -!2 = !{ptr @ptr_as_int, !"kernel", i32 1} -!3 = !{ptr @ptr_as_int_aggr, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-byval-args.ll b/llvm/test/CodeGen/NVPTX/lower-byval-args.ll index 5c52626a711f..26102722a483 100644 --- a/llvm/test/CodeGen/NVPTX/lower-byval-args.ll +++ b/llvm/test/CodeGen/NVPTX/lower-byval-args.ll @@ -24,8 +24,8 @@ declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture read declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2 ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only( +define dso_local ptx_kernel void @read_only(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -35,7 +35,7 @@ define dso_local void @read_only(ptr nocapture noundef writeonly %out, ptr nocap ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -45,7 +45,7 @@ define dso_local void @read_only(ptr nocapture noundef writeonly %out, ptr nocap ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only( +; COPY-LABEL: define dso_local ptx_kernel void @read_only( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -62,8 +62,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only_gep(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only_gep( +define dso_local ptx_kernel void @read_only_gep(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only_gep( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -74,7 +74,7 @@ define dso_local void @read_only_gep(ptr nocapture noundef writeonly %out, ptr n ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only_gep( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only_gep( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -85,7 +85,7 @@ define dso_local void @read_only_gep(ptr nocapture noundef writeonly %out, ptr n ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only_gep( +; COPY-LABEL: define dso_local ptx_kernel void @read_only_gep( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -104,8 +104,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only_gep_asc(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only_gep_asc( +define dso_local ptx_kernel void @read_only_gep_asc(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only_gep_asc( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -116,7 +116,7 @@ define dso_local void @read_only_gep_asc(ptr nocapture noundef writeonly %out, p ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only_gep_asc( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only_gep_asc( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -127,7 +127,7 @@ define dso_local void @read_only_gep_asc(ptr nocapture noundef writeonly %out, p ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only_gep_asc( +; COPY-LABEL: define dso_local ptx_kernel void @read_only_gep_asc( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -148,8 +148,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only_gep_asc0( +define dso_local ptx_kernel void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only_gep_asc0( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -164,7 +164,7 @@ define dso_local void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only_gep_asc0( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only_gep_asc0( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -179,7 +179,7 @@ define dso_local void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only_gep_asc0( +; COPY-LABEL: define dso_local ptx_kernel void @read_only_gep_asc0( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -202,8 +202,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr( +define dso_local ptx_kernel void @escape_ptr(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr( ; SM_60-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -214,7 +214,7 @@ define dso_local void @escape_ptr(ptr nocapture noundef readnone %out, ptr nound ; SM_60-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[S3]]) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr( ; SM_70-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -225,7 +225,7 @@ define dso_local void @escape_ptr(ptr nocapture noundef readnone %out, ptr nound ; SM_70-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[S3]]) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr( ; COPY-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -240,8 +240,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr_gep( +define dso_local ptx_kernel void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr_gep( ; SM_60-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -253,7 +253,7 @@ define dso_local void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr n ; SM_60-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[B]]) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr_gep( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr_gep( ; SM_70-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -265,7 +265,7 @@ define dso_local void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr n ; SM_70-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[B]]) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr_gep( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr_gep( ; COPY-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -282,8 +282,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr_store( +define dso_local ptx_kernel void @escape_ptr_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr_store( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -294,7 +294,7 @@ define dso_local void @escape_ptr_store(ptr nocapture noundef writeonly %out, pt ; SM_60-NEXT: store ptr [[S3]], ptr [[OUT2]], align 8 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr_store( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr_store( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -305,7 +305,7 @@ define dso_local void @escape_ptr_store(ptr nocapture noundef writeonly %out, pt ; SM_70-NEXT: store ptr [[S3]], ptr [[OUT2]], align 8 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr_store( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr_store( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -320,8 +320,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr_gep_store( +define dso_local ptx_kernel void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr_gep_store( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -333,7 +333,7 @@ define dso_local void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out ; SM_60-NEXT: store ptr [[B]], ptr [[OUT2]], align 8 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr_gep_store( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr_gep_store( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -345,7 +345,7 @@ define dso_local void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out ; SM_70-NEXT: store ptr [[B]], ptr [[OUT2]], align 8 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr_gep_store( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr_gep_store( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -362,8 +362,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptrtoint( +define dso_local ptx_kernel void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptrtoint( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -375,7 +375,7 @@ define dso_local void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr ; SM_60-NEXT: store i64 [[I]], ptr [[OUT2]], align 8 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptrtoint( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptrtoint( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -387,7 +387,7 @@ define dso_local void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr ; SM_70-NEXT: store i64 [[I]], ptr [[OUT2]], align 8 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptrtoint( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptrtoint( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -404,8 +404,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @memcpy_from_param(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @memcpy_from_param( +define dso_local ptx_kernel void @memcpy_from_param(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @memcpy_from_param( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -414,7 +414,7 @@ define dso_local void @memcpy_from_param(ptr nocapture noundef writeonly %out, p ; SM_60-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @memcpy_from_param( +; SM_70-LABEL: define dso_local ptx_kernel void @memcpy_from_param( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -423,7 +423,7 @@ define dso_local void @memcpy_from_param(ptr nocapture noundef writeonly %out, p ; SM_70-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @memcpy_from_param( +; COPY-LABEL: define dso_local ptx_kernel void @memcpy_from_param( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -438,8 +438,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @memcpy_from_param_noalign (ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @memcpy_from_param_noalign( +define dso_local ptx_kernel void @memcpy_from_param_noalign (ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @memcpy_from_param_noalign( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -448,7 +448,7 @@ define dso_local void @memcpy_from_param_noalign (ptr nocapture noundef writeonl ; SM_60-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @memcpy_from_param_noalign( +; SM_70-LABEL: define dso_local ptx_kernel void @memcpy_from_param_noalign( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -457,7 +457,7 @@ define dso_local void @memcpy_from_param_noalign (ptr nocapture noundef writeonl ; SM_70-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @memcpy_from_param_noalign( +; COPY-LABEL: define dso_local ptx_kernel void @memcpy_from_param_noalign( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 8 @@ -472,8 +472,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr nocapture noundef readnone byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @memcpy_to_param( +define dso_local ptx_kernel void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr nocapture noundef readnone byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @memcpy_to_param( ; SM_60-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef readnone byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -484,7 +484,7 @@ define dso_local void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr n ; SM_60-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[S3]], ptr [[IN2]], i64 16, i1 true) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @memcpy_to_param( +; SM_70-LABEL: define dso_local ptx_kernel void @memcpy_to_param( ; SM_70-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef readnone byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -495,7 +495,7 @@ define dso_local void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr n ; SM_70-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[S3]], ptr [[IN2]], i64 16, i1 true) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @memcpy_to_param( +; COPY-LABEL: define dso_local ptx_kernel void @memcpy_to_param( ; COPY-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef readnone byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -510,8 +510,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @copy_on_store(ptr nocapture noundef readonly %in, ptr nocapture noundef byval(%struct.S) align 4 %s, i1 noundef zeroext %b) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @copy_on_store( +define dso_local ptx_kernel void @copy_on_store(ptr nocapture noundef readonly %in, ptr nocapture noundef byval(%struct.S) align 4 %s, i1 noundef zeroext %b) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @copy_on_store( ; SM_60-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]], i1 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -523,7 +523,7 @@ define dso_local void @copy_on_store(ptr nocapture noundef readonly %in, ptr noc ; SM_60-NEXT: store i32 [[I]], ptr [[S3]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @copy_on_store( +; SM_70-LABEL: define dso_local ptx_kernel void @copy_on_store( ; SM_70-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]], i1 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -535,7 +535,7 @@ define dso_local void @copy_on_store(ptr nocapture noundef readonly %in, ptr noc ; SM_70-NEXT: store i32 [[I]], ptr [[S3]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @copy_on_store( +; COPY-LABEL: define dso_local ptx_kernel void @copy_on_store( ; COPY-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]], i1 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -551,8 +551,8 @@ bb: ret void } -define void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { -; SM_60-LABEL: define void @test_select( +define ptx_kernel void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { +; SM_60-LABEL: define ptx_kernel void @test_select( ; SM_60-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[OUT7:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -568,7 +568,7 @@ define void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ; SM_60-NEXT: store i32 [[VALLOADED]], ptr [[OUT8]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define void @test_select( +; SM_70-LABEL: define ptx_kernel void @test_select( ; SM_70-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[OUT1:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -582,7 +582,7 @@ define void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ; SM_70-NEXT: store i32 [[VALLOADED]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define void @test_select( +; COPY-LABEL: define ptx_kernel void @test_select( ; COPY-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[INPUT23:%.*]] = alloca i32, align 4 @@ -603,8 +603,8 @@ bb: ret void } -define void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { -; SM_60-LABEL: define void @test_select_write( +define ptx_kernel void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { +; SM_60-LABEL: define ptx_kernel void @test_select_write( ; SM_60-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[OUT5:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -619,7 +619,7 @@ define void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; SM_60-NEXT: store i32 1, ptr [[PTRNEW]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define void @test_select_write( +; SM_70-LABEL: define ptx_kernel void @test_select_write( ; SM_70-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[OUT5:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -634,7 +634,7 @@ define void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; SM_70-NEXT: store i32 1, ptr [[PTRNEW]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define void @test_select_write( +; COPY-LABEL: define ptx_kernel void @test_select_write( ; COPY-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[INPUT23:%.*]] = alloca i32, align 4 @@ -653,8 +653,8 @@ bb: ret void } -define void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, ptr %inout, i1 %cond) { -; SM_60-LABEL: define void @test_phi( +define ptx_kernel void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, ptr %inout, i1 %cond) { +; SM_60-LABEL: define ptx_kernel void @test_phi( ; SM_60-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[INOUT7:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) @@ -678,7 +678,7 @@ define void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) ; SM_60-NEXT: store i32 [[VALLOADED]], ptr [[INOUT8]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define void @test_phi( +; SM_70-LABEL: define ptx_kernel void @test_phi( ; SM_70-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) @@ -700,7 +700,7 @@ define void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) ; SM_70-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define void @test_phi( +; COPY-LABEL: define ptx_kernel void @test_phi( ; COPY-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[INPUT23:%.*]] = alloca [[STRUCT_S]], align 8 @@ -740,8 +740,8 @@ merge: ; preds = %second, %first ret void } -define void @test_phi_write(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, i1 %cond) { -; COMMON-LABEL: define void @test_phi_write( +define ptx_kernel void @test_phi_write(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, i1 %cond) { +; COMMON-LABEL: define ptx_kernel void @test_phi_write( ; COMMON-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; COMMON-NEXT: [[BB:.*:]] ; COMMON-NEXT: [[INPUT24:%.*]] = alloca [[STRUCT_S]], align 8 @@ -784,29 +784,11 @@ attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: readwrite attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) } !llvm.module.flags = !{!0, !1, !2, !3} -!nvvm.annotations = !{!4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !23} !llvm.ident = !{!20, !21} !0 = !{i32 2, !"SDK Version", [2 x i32] [i32 11, i32 8]} !1 = !{i32 1, !"wchar_size", i32 4} !2 = !{i32 4, !"nvvm-reflect-ftz", i32 0} !3 = !{i32 7, !"frame-pointer", i32 2} -!4 = !{ptr @read_only, !"kernel", i32 1} -!5 = !{ptr @escape_ptr, !"kernel", i32 1} -!6 = !{ptr @escape_ptr_gep, !"kernel", i32 1} -!7 = !{ptr @escape_ptr_store, !"kernel", i32 1} -!8 = !{ptr @escape_ptr_gep_store, !"kernel", i32 1} -!9 = !{ptr @escape_ptrtoint, !"kernel", i32 1} -!10 = !{ptr @memcpy_from_param, !"kernel", i32 1} -!11 = !{ptr @memcpy_to_param, !"kernel", i32 1} -!12 = !{ptr @copy_on_store, !"kernel", i32 1} -!13 = !{ptr @read_only_gep, !"kernel", i32 1} -!14 = !{ptr @read_only_gep_asc, !"kernel", i32 1} -!15 = !{ptr @read_only_gep_asc0, !"kernel", i32 1} -!16 = !{ptr @test_select, !"kernel", i32 1} -!17 = !{ptr @test_phi, !"kernel", i32 1} -!18 = !{ptr @test_phi_write, !"kernel", i32 1} -!19 = !{ptr @test_select_write, !"kernel", i32 1} !20 = !{!"clang version 20.0.0git"} !21 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"} -!23 = !{ptr @memcpy_from_param_noalign, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll b/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll index f8b3b4b9b8c4..4ee1ca3ad4b1 100644 --- a/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll +++ b/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll @@ -43,7 +43,7 @@ define internal void @bar() { ret void } -; CHECK-LABEL: define weak_odr void @"nvptx$device$init"() { +; CHECK-LABEL: define weak_odr ptx_kernel void @"nvptx$device$init"() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[BEGIN:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__init_array_start, align 8 ; CHECK-NEXT: [[STOP:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__init_array_end, align 8 @@ -60,7 +60,7 @@ define internal void @bar() { ; CHECK-NEXT: ret void ; ; -; CHECK-LABEL: define weak_odr void @"nvptx$device$fini"() { +; CHECK-LABEL: define weak_odr ptx_kernel void @"nvptx$device$fini"() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[BEGIN:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__fini_array_start, align 8 ; CHECK-NEXT: [[STOP:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__fini_array_end, align 8 @@ -82,12 +82,10 @@ define internal void @bar() { ; CHECK: while.end: ; CHECK-NEXT: ret void -; CHECK: [[META0:![0-9]+]] = !{ptr @"nvptx$device$init", !"kernel", i32 1} ; CHECK: [[META1:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxntidx", i32 1} ; CHECK: [[META2:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxntidy", i32 1} ; CHECK: [[META3:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxntidz", i32 1} ; CHECK: [[META4:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxclusterrank", i32 1} -; CHECK: [[META5:![0-9]+]] = !{ptr @"nvptx$device$fini", !"kernel", i32 1} ; CHECK: [[META6:![0-9]+]] = !{ptr @"nvptx$device$fini", !"maxntidx", i32 1} ; CHECK: [[META7:![0-9]+]] = !{ptr @"nvptx$device$fini", !"maxntidy", i32 1} ; CHECK: [[META8:![0-9]+]] = !{ptr @"nvptx$device$fini", !"maxntidz", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll b/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll index 9ec690a68e7e..2e64c2559481 100644 --- a/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll +++ b/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll @@ -6,7 +6,7 @@ target triple = "nvptx64-nvidia-cuda" ; Verify that both %input and %output are converted to global pointers and then ; addrspacecast'ed back to the original type. -define void @kernel(ptr %input, ptr %output) { +define ptx_kernel void @kernel(ptr %input, ptr %output) { ; CHECK-LABEL: .visible .entry kernel( ; CHECK: cvta.to.global.u64 ; CHECK: cvta.to.global.u64 @@ -17,7 +17,7 @@ define void @kernel(ptr %input, ptr %output) { ret void } -define void @kernel2(ptr addrspace(1) %input, ptr addrspace(1) %output) { +define ptx_kernel void @kernel2(ptr addrspace(1) %input, ptr addrspace(1) %output) { ; CHECK-LABEL: .visible .entry kernel2( ; CHECK-NOT: cvta.to.global.u64 %1 = load float, ptr addrspace(1) %input, align 4 @@ -29,7 +29,7 @@ define void @kernel2(ptr addrspace(1) %input, ptr addrspace(1) %output) { %struct.S = type { ptr, ptr } -define void @ptr_in_byval_kernel(ptr byval(%struct.S) %input, ptr %output) { +define ptx_kernel void @ptr_in_byval_kernel(ptr byval(%struct.S) %input, ptr %output) { ; CHECK-LABEL: .visible .entry ptr_in_byval_kernel( ; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_kernel_param_1] ; CHECK: cvta.to.global.u64 %[[optr_g:.*]], %[[optr]]; @@ -60,7 +60,3 @@ define void @ptr_in_byval_func(ptr byval(%struct.S) %input, ptr %output) { ret void } -!nvvm.annotations = !{!0, !1, !2} -!0 = !{ptr @kernel, !"kernel", i32 1} -!1 = !{ptr @kernel2, !"kernel", i32 1} -!2 = !{ptr @ptr_in_byval_kernel, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/maxclusterrank.ll b/llvm/test/CodeGen/NVPTX/maxclusterrank.ll index 3389e090aac5..c445c34c1842 100644 --- a/llvm/test/CodeGen/NVPTX/maxclusterrank.ll +++ b/llvm/test/CodeGen/NVPTX/maxclusterrank.ll @@ -11,16 +11,15 @@ target triple = "nvptx64-unknown-unknown" ; Make sure that for SM version prior to 90 `.maxclusterrank` directive is ; sielently ignored. -define dso_local void @_Z18TestMaxClusterRankv() { +define dso_local ptx_kernel void @_Z18TestMaxClusterRankv() { entry: %a = alloca i32, align 4 store volatile i32 1, ptr %a, align 4 ret void } -!nvvm.annotations = !{!0, !1, !2, !3} +!nvvm.annotations = !{!1, !2, !3} -!0 = !{ptr @_Z18TestMaxClusterRankv, !"kernel", i32 1} !1 = !{ptr @_Z18TestMaxClusterRankv, !"maxntidx", i32 128} !2 = !{ptr @_Z18TestMaxClusterRankv, !"minctasm", i32 2} !3 = !{ptr @_Z18TestMaxClusterRankv, !"maxclusterrank", i32 8} diff --git a/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll b/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll index 2bc6d4cfa7f6..2a0c5ab7299b 100644 --- a/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll +++ b/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll @@ -66,7 +66,4 @@ if.end17: ; preds = %if.else13, %if.then } ; Function Attrs: noduplicate nounwind -declare void @llvm.nvvm.barrier0() #2 - -!0 = !{ptr @foo, !"kernel", i32 1} -!1 = !{null, !"align", i32 8} +declare void @llvm.nvvm.barrier0() #2
\ No newline at end of file diff --git a/llvm/test/CodeGen/NVPTX/noreturn.ll b/llvm/test/CodeGen/NVPTX/noreturn.ll index 2161d70a8852..6c11d0a9376a 100644 --- a/llvm/test/CodeGen/NVPTX/noreturn.ll +++ b/llvm/test/CodeGen/NVPTX/noreturn.ll @@ -27,7 +27,7 @@ define void @true_noreturn0() #0 { ; CHECK: .entry ignore_kernel_noreturn() ; CHECK-NOT: .noreturn -define void @ignore_kernel_noreturn() #0 { +define ptx_kernel void @ignore_kernel_noreturn() #0 { unreachable } @@ -35,7 +35,7 @@ define void @ignore_kernel_noreturn() #0 { ; CHECK: prototype_{{[0-9]+}} : .callprototype ()_ (.param .b32 _) .noreturn; ; CHECK: prototype_{{[0-9]+}} : .callprototype (.param .b32 _) _ (.param .b32 _); -define void @callprototype_noreturn(i32) { +define ptx_kernel void @callprototype_noreturn(i32) { %fn = load ptr, ptr addrspace(1) @function_pointer call void %fn(i32 %0) #0 %non_void = bitcast ptr %fn to ptr @@ -44,8 +44,3 @@ define void @callprototype_noreturn(i32) { } attributes #0 = { noreturn } - -!nvvm.annotations = !{!0, !1} - -!0 = !{ptr @ignore_kernel_noreturn, !"kernel", i32 1} -!1 = !{ptr @callprototype_noreturn, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll b/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll index 48162eaba257..9a78d31302e1 100644 --- a/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll +++ b/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll @@ -3,7 +3,7 @@ target triple = "nvptx-unknown-nvcl" -define void @foo(i64 %img, i64 %sampler, ptr align 32 %v1, ptr %v2) { +define ptx_kernel void @foo(i64 %img, i64 %sampler, ptr align 32 %v1, ptr %v2) { ; The parameter alignment is determined by the align attribute (default 1). ; CHECK-LABEL: .entry foo( ; CHECK: .param .u64 .ptr .align 32 foo_param_2 @@ -11,7 +11,6 @@ define void @foo(i64 %img, i64 %sampler, ptr align 32 %v1, ptr %v2) { ret void } -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} +!nvvm.annotations = !{!2, !3} !2 = !{ptr @foo, !"rdoimage", i32 0} !3 = !{ptr @foo, !"sampler", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll index ac5875c6ab10..83cb3cde48de 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll @@ -1,9 +1,9 @@ ; Libdevice in recent CUDA versions relies on __CUDA_ARCH reflecting GPU type. ; Verify that __nvvm_reflect() is replaced with an appropriate value. ; -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_20 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_20 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM20 -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_35 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_35 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM35 @"$str" = private addrspace(1) constant [12 x i8] c"__CUDA_ARCH\00" diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll index 9d383218dce8..bf8d6e2cca30 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll @@ -1,8 +1,8 @@ ; Verify that __nvvm_reflect_ocl() is replaced with an appropriate value ; -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_20 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_20 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM20 -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_35 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_35 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM35 @"$str" = private addrspace(4) constant [12 x i8] c"__CUDA_ARCH\00" diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll index 46ab79d9858c..19c74df30370 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll @@ -3,12 +3,12 @@ ; RUN: cat %s > %t.noftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz -; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK ; RUN: cat %s > %t.ftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz -; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK @str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00" @@ -43,7 +43,7 @@ exit: declare i32 @llvm.nvvm.reflect(ptr) -; CHECK-LABEL: define noundef i32 @intrinsic +; CHECK-LABEL: define i32 @intrinsic define i32 @intrinsic() { ; CHECK-NOT: call i32 @llvm.nvvm.reflect ; USE_FTZ_0: ret i32 0 diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll index 2ed9f7c11bcf..244b44fea9b8 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll @@ -3,12 +3,12 @@ ; RUN: cat %s > %t.noftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz -; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK ; RUN: cat %s > %t.ftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz -; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK @str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00" @@ -43,7 +43,8 @@ exit: declare i32 @llvm.nvvm.reflect(ptr) -; CHECK-LABEL: define noundef i32 @intrinsic +; CHECK-LABEL: define i32 @intrinsic + define i32 @intrinsic() { ; CHECK-NOT: call i32 @llvm.nvvm.reflect ; USE_FTZ_0: ret i32 0 diff --git a/llvm/test/CodeGen/NVPTX/refl1.ll b/llvm/test/CodeGen/NVPTX/refl1.ll index 34db3bb1a1a9..99b83f49ff9b 100644 --- a/llvm/test/CodeGen/NVPTX/refl1.ll +++ b/llvm/test/CodeGen/NVPTX/refl1.ll @@ -5,7 +5,7 @@ target triple = "nvptx-nvidia-cuda" ; Function Attrs: nounwind ; CHECK: .entry foo -define void @foo(ptr nocapture %a) #0 { +define ptx_kernel void @foo(ptr nocapture %a) #0 { %val = load float, ptr %a %tan = tail call fastcc float @__nv_fast_tanf(float %val) store float %tan, ptr %a @@ -34,7 +34,3 @@ entry: attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { alwaysinline inlinehint nounwind readnone } - -!nvvm.annotations = !{!0} - -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/reg-copy.ll b/llvm/test/CodeGen/NVPTX/reg-copy.ll index f66ef195c625..20396c4cc69f 100644 --- a/llvm/test/CodeGen/NVPTX/reg-copy.ll +++ b/llvm/test/CodeGen/NVPTX/reg-copy.ll @@ -4,7 +4,7 @@ target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-unknown-unknown" -define void @PR24303(ptr %f) { +define ptx_kernel void @PR24303(ptr %f) { ; CHECK-LABEL: .visible .entry PR24303( ; Do not use mov.f or mov.u to convert between float and int. ; CHECK-NOT: mov.{{f|u}}{{32|64}} %f{{[0-9]+}}, %r{{[0-9]+}} @@ -217,7 +217,3 @@ _ZN12cuda_builtinmlIfEENS_7complexIT_EERKS3_S5_.exit: ; preds = %if.then.93.i, % } declare float @llvm.nvvm.fabs.f(float) - -!nvvm.annotations = !{!0} - -!0 = !{ptr @PR24303, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/simple-call.ll b/llvm/test/CodeGen/NVPTX/simple-call.ll index 3580604d429d..991ae04b91b6 100644 --- a/llvm/test/CodeGen/NVPTX/simple-call.ll +++ b/llvm/test/CodeGen/NVPTX/simple-call.ll @@ -10,7 +10,7 @@ define float @device_func(float %a) noinline { } ; CHECK: .entry kernel_func -define void @kernel_func(ptr %a) { +define ptx_kernel void @kernel_func(ptr %a) { %val = load float, ptr %a ; CHECK: call.uni (retval0), ; CHECK: device_func, @@ -18,9 +18,3 @@ define void @kernel_func(ptr %a) { store float %mul, ptr %a ret void } - - - -!nvvm.annotations = !{!1} - -!1 = !{ptr @kernel_func, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll b/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll index 504dcdeb3370..7a7904a2f042 100644 --- a/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll +++ b/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll @@ -10,7 +10,7 @@ declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32) declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1)) -define void @foo(i64 %img, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) { ; CHECK-LABEL: foo( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -34,7 +34,7 @@ define void @foo(i64 %img, ptr %red, i32 %idx) { @surf0 = internal addrspace(1) global i64 0, align 8 -define void @bar(ptr %red, i32 %idx) { +define ptx_kernel void @bar(ptr %red, i32 %idx) { ; CHECK-LABEL: bar( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -56,11 +56,5 @@ define void @bar(ptr %red, i32 %idx) { ret void } - - - -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @bar, !"kernel", i32 1} -!3 = !{ptr addrspace(1) @surf0, !"surface", i32 1} - +!nvvm.annotations = !{!1} +!1 = !{ptr addrspace(1) @surf0, !"surface", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/surf-read.ll b/llvm/test/CodeGen/NVPTX/surf-read.ll index e0cebd60d7dd..cd11b5617076 100644 --- a/llvm/test/CodeGen/NVPTX/surf-read.ll +++ b/llvm/test/CodeGen/NVPTX/surf-read.ll @@ -6,7 +6,7 @@ target triple = "nvptx64-unknown-nvcl" declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32) ; CHECK: .entry foo -define void @foo(i64 %img, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) { ; CHECK: suld.b.1d.b32.trap {%r[[RED:[0-9]+]]}, [foo_param_0, {%r{{[0-9]+}}}] %val = tail call i32 @llvm.nvvm.suld.1d.i32.trap(i64 %img, i32 %idx) ; CHECK: cvt.rn.f32.s32 %f[[REDF:[0-9]+]], %r[[RED]] @@ -16,6 +16,5 @@ define void @foo(i64 %img, ptr %red, i32 %idx) { ret void } -!nvvm.annotations = !{!1, !2} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @foo, !"rdwrimage", i32 0} +!nvvm.annotations = !{!1} +!1 = !{ptr @foo, !"rdwrimage", i32 0} diff --git a/llvm/test/CodeGen/NVPTX/surf-tex.py b/llvm/test/CodeGen/NVPTX/surf-tex.py index 9607a58856ba..90d67666f1ed 100644 --- a/llvm/test/CodeGen/NVPTX/surf-tex.py +++ b/llvm/test/CodeGen/NVPTX/surf-tex.py @@ -224,11 +224,6 @@ def get_ptx_surface(target): def get_surface_metadata(target, fun_ty, fun_name, has_surface_param): metadata = [] - md_kernel = '!{{{fun_ty} @{fun_name}, !"kernel", i32 1}}'.format( - fun_ty=fun_ty, fun_name=fun_name - ) - metadata.append(md_kernel) - if target == "cuda": # When a parameter is lowered as a .surfref, it still has the # corresponding ld.param.u64, which is illegal. Do not emit the @@ -263,14 +258,14 @@ def gen_suld_tests(target, global_surf): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} ${reg_ret}, [${reg_surf}, ${reg_access}] ; - define void @${test_name}_param(i64 %s, ${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %s, ${retty}* %ret, ${access}) { %val = tail call ${retty} @${intrinsic}(i64 %s, ${access}) store ${retty} %val, ${retty}* %ret ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} ${reg_ret}, [${global_surf}, ${reg_access}] - define void @${test_name}_global(${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_global(${retty}* %ret, ${access}) { %gs = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_surf}) %val = tail call ${retty} @${intrinsic}(i64 %gs, ${access}) store ${retty} %val, ${retty}* %ret @@ -356,13 +351,13 @@ def gen_sust_tests(target, global_surf): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} [${reg_surf}, ${reg_access}], ${reg_value} ; - define void @${test_name}_param(i64 %s, ${value}, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %s, ${value}, ${access}) { tail call void @${intrinsic}(i64 %s, ${access}, ${value}) ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} [${global_surf}, ${reg_access}], ${reg_value} - define void @${test_name}_global(${value}, ${access}) { + define ptx_kernel void @${test_name}_global(${value}, ${access}) { %gs = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_surf}) tail call void @${intrinsic}(i64 %gs, ${access}, ${value}) ret void @@ -420,19 +415,13 @@ def gen_sust_tests(target, global_surf): generated_items.append((params["intrinsic"], params["instruction"])) fun_name = test_name + "_param" - fun_ty = "void (i64, {value_ty}, {access_ty})*".format( - value_ty=get_llvm_value_type(vec, ctype), - access_ty=get_llvm_surface_access_type(geom), - ) + fun_ty = "ptr" generated_metadata += get_surface_metadata( target, fun_ty, fun_name, has_surface_param=True ) fun_name = test_name + "_global" - fun_ty = "void ({value_ty}, {access_ty})*".format( - value_ty=get_llvm_value_type(vec, ctype), - access_ty=get_llvm_surface_access_type(geom), - ) + fun_ty = "ptr" generated_metadata += get_surface_metadata( target, fun_ty, fun_name, has_surface_param=False ) @@ -559,11 +548,6 @@ def get_ptx_global_sampler(target, global_sampler): def get_texture_metadata(target, fun_ty, fun_name, has_texture_params): metadata = [] - md_kernel = '!{{{fun_ty} @{fun_name}, !"kernel", i32 1}}'.format( - fun_ty=fun_ty, fun_name=fun_name - ) - metadata.append(md_kernel) - if target == "cuda": # When a parameter is lowered as a .texref, it still has the # corresponding ld.param.u64, which is illegal. Do not emit the @@ -615,14 +599,14 @@ def gen_tex_tests(target, global_tex, global_sampler): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} ${ptx_ret}, [${ptx_tex}, ${ptx_access}] - define void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { %val = tail call ${retty} @${intrinsic}(i64 %tex, ${sampler} ${access}) store ${retty} %val, ${retty}* %ret ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} ${ptx_ret}, [${global_tex}, ${ptx_global_sampler} ${ptx_access}] - define void @${test_name}_global(${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_global(${retty}* %ret, ${access}) { %gt = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_tex}) ${get_sampler_handle} %val = tail call ${retty} @${intrinsic}(i64 %gt, ${sampler} ${access}) @@ -799,14 +783,14 @@ def gen_tld4_tests(target, global_tex, global_sampler): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} ${ptx_ret}, [${ptx_tex}, ${ptx_access}] - define void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { %val = tail call ${retty} @${intrinsic}(i64 %tex, ${sampler} ${access}) store ${retty} %val, ${retty}* %ret ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} ${ptx_ret}, [${global_tex}, ${ptx_global_sampler} ${ptx_access}] - define void @${test_name}_global(${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_global(${retty}* %ret, ${access}) { %gt = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_tex}) ${get_sampler_handle} %val = tail call ${retty} @${intrinsic}(i64 %gt, ${sampler} ${access}) diff --git a/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll b/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll index 881ea459feb4..5dc44cb1925b 100644 --- a/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll +++ b/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll @@ -10,7 +10,7 @@ declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32) declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1)) -define void @foo(i64 %img, i32 %val, i32 %idx) { +define ptx_kernel void @foo(i64 %img, i32 %val, i32 %idx) { ; CHECK-LABEL: foo( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -30,7 +30,7 @@ define void @foo(i64 %img, i32 %val, i32 %idx) { @surf0 = internal addrspace(1) global i64 0, align 8 -define void @bar(i32 %val, i32 %idx) { +define ptx_kernel void @bar(i32 %val, i32 %idx) { ; CHECK-LABEL: bar( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -47,8 +47,6 @@ define void @bar(i32 %val, i32 %idx) { } -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @bar, !"kernel", i32 1} -!3 = !{ptr addrspace(1) @surf0, !"surface", i32 1} +!nvvm.annotations = !{!1} +!1 = !{ptr addrspace(1) @surf0, !"surface", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/surf-write.ll b/llvm/test/CodeGen/NVPTX/surf-write.ll index 258bb6d8b5b7..0e1f0cc70099 100644 --- a/llvm/test/CodeGen/NVPTX/surf-write.ll +++ b/llvm/test/CodeGen/NVPTX/surf-write.ll @@ -6,12 +6,11 @@ target triple = "nvptx-unknown-nvcl" declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32) ; CHECK: .entry foo -define void @foo(i64 %img, i32 %val, i32 %idx) { +define ptx_kernel void @foo(i64 %img, i32 %val, i32 %idx) { ; CHECK: sust.b.1d.b32.trap [foo_param_0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}} tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val) ret void } -!nvvm.annotations = !{!1, !2} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @foo, !"wroimage", i32 0} +!nvvm.annotations = !{!1} +!1 = !{ptr @foo, !"wroimage", i32 0} diff --git a/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll b/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll index ba556d2d9bd6..61837bde82ec 100644 --- a/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll +++ b/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll @@ -10,7 +10,7 @@ target triple = "nvptx-unknown-cuda" declare { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64, i32) declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1)) -define void @foo(i64 %img, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) { ; CHECK-LABEL: foo( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<2>; @@ -34,7 +34,7 @@ define void @foo(i64 %img, ptr %red, i32 %idx) { @tex0 = internal addrspace(1) global i64 0, align 8 -define void @bar(ptr %red, i32 %idx) { +define ptx_kernel void @bar(ptr %red, i32 %idx) { ; CHECK-LABEL: bar( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<2>; @@ -57,7 +57,7 @@ define void @bar(ptr %red, i32 %idx) { declare float @texfunc(i64) -define void @baz(ptr %red, i32 %idx) { +define ptx_kernel void @baz(ptr %red, i32 %idx) { ; CHECK-LABEL: baz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<2>; @@ -93,8 +93,5 @@ define void @baz(ptr %red, i32 %idx) { ret void } -!nvvm.annotations = !{!1, !2, !3, !4} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @bar, !"kernel", i32 1} -!3 = !{ptr addrspace(1) @tex0, !"texture", i32 1} -!4 = !{ptr @baz, !"kernel", i32 1} +!nvvm.annotations = !{!1} +!1 = !{ptr addrspace(1) @tex0, !"texture", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/tex-read.ll b/llvm/test/CodeGen/NVPTX/tex-read.ll index d11aea45a65f..d74c89f5abc8 100644 --- a/llvm/test/CodeGen/NVPTX/tex-read.ll +++ b/llvm/test/CodeGen/NVPTX/tex-read.ll @@ -6,7 +6,7 @@ target triple = "nvptx64-unknown-nvcl" declare { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64, i64, i32) ; CHECK: .entry foo -define void @foo(i64 %img, i64 %sampler, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, i64 %sampler, ptr %red, i32 %idx) { ; CHECK: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]+]]}, [foo_param_0, foo_param_1, {%r{{[0-9]+}}}] %val = tail call { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64 %img, i64 %sampler, i32 %idx) %ret = extractvalue { float, float, float, float } %val, 0 @@ -15,7 +15,6 @@ define void @foo(i64 %img, i64 %sampler, ptr %red, i32 %idx) { ret void } -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} +!nvvm.annotations = !{!2, !3} !2 = !{ptr @foo, !"rdoimage", i32 0} !3 = !{ptr @foo, !"sampler", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/unreachable.ll b/llvm/test/CodeGen/NVPTX/unreachable.ll index 286f3588a754..80cf938d48b5 100644 --- a/llvm/test/CodeGen/NVPTX/unreachable.ll +++ b/llvm/test/CodeGen/NVPTX/unreachable.ll @@ -21,7 +21,7 @@ target triple = "nvptx-unknown-cuda" declare void @throw() #0 declare void @llvm.trap() #0 -define void @kernel_func() { +define ptx_kernel void @kernel_func() { ; NO-TRAP-UNREACHABLE-LABEL: kernel_func( ; NO-TRAP-UNREACHABLE: { ; NO-TRAP-UNREACHABLE-EMPTY: @@ -102,6 +102,3 @@ define void @kernel_func_2() { } attributes #0 = { noreturn } - -!nvvm.annotations = !{!1} -!1 = !{ptr @kernel_func, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/variadics-backend.ll b/llvm/test/CodeGen/NVPTX/variadics-backend.ll index cb54812dea6d..f7ed690efabc 100644 --- a/llvm/test/CodeGen/NVPTX/variadics-backend.ll +++ b/llvm/test/CodeGen/NVPTX/variadics-backend.ll @@ -153,7 +153,7 @@ define dso_local i32 @variadics2(i32 noundef %first, ...) { ; CHECK-PTX-NEXT: .reg .b64 %SPL; ; CHECK-PTX-NEXT: .reg .b16 %rs<6>; ; CHECK-PTX-NEXT: .reg .b32 %r<7>; -; CHECK-PTX-NEXT: .reg .b64 %rd<11>; +; CHECK-PTX-NEXT: .reg .b64 %rd<7>; ; CHECK-PTX-EMPTY: ; CHECK-PTX-NEXT: // %bb.0: // %entry ; CHECK-PTX-NEXT: mov.u64 %SPL, __local_depot2; @@ -163,24 +163,20 @@ define dso_local i32 @variadics2(i32 noundef %first, ...) { ; CHECK-PTX-NEXT: add.s64 %rd2, %rd1, 7; ; CHECK-PTX-NEXT: and.b64 %rd3, %rd2, -8; ; CHECK-PTX-NEXT: ld.u32 %r2, [%rd3]; -; CHECK-PTX-NEXT: or.b64 %rd4, %rd3, 4; -; CHECK-PTX-NEXT: ld.s8 %r3, [%rd4]; -; CHECK-PTX-NEXT: or.b64 %rd5, %rd3, 5; -; CHECK-PTX-NEXT: or.b64 %rd6, %rd3, 7; -; CHECK-PTX-NEXT: ld.u8 %rs1, [%rd6]; +; CHECK-PTX-NEXT: ld.s8 %r3, [%rd3+4]; +; CHECK-PTX-NEXT: ld.u8 %rs1, [%rd3+7]; ; CHECK-PTX-NEXT: st.u8 [%SP+2], %rs1; -; CHECK-PTX-NEXT: ld.u8 %rs2, [%rd5]; -; CHECK-PTX-NEXT: or.b64 %rd7, %rd3, 6; -; CHECK-PTX-NEXT: ld.u8 %rs3, [%rd7]; +; CHECK-PTX-NEXT: ld.u8 %rs2, [%rd3+5]; +; CHECK-PTX-NEXT: ld.u8 %rs3, [%rd3+6]; ; CHECK-PTX-NEXT: shl.b16 %rs4, %rs3, 8; ; CHECK-PTX-NEXT: or.b16 %rs5, %rs4, %rs2; ; CHECK-PTX-NEXT: st.u16 [%SP], %rs5; -; CHECK-PTX-NEXT: ld.u64 %rd8, [%rd3+8]; +; CHECK-PTX-NEXT: ld.u64 %rd4, [%rd3+8]; ; CHECK-PTX-NEXT: add.s32 %r4, %r1, %r2; ; CHECK-PTX-NEXT: add.s32 %r5, %r4, %r3; -; CHECK-PTX-NEXT: cvt.u64.u32 %rd9, %r5; -; CHECK-PTX-NEXT: add.s64 %rd10, %rd9, %rd8; -; CHECK-PTX-NEXT: cvt.u32.u64 %r6, %rd10; +; CHECK-PTX-NEXT: cvt.u64.u32 %rd5, %r5; +; CHECK-PTX-NEXT: add.s64 %rd6, %rd5, %rd4; +; CHECK-PTX-NEXT: cvt.u32.u64 %r6, %rd6; ; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-PTX-NEXT: ret; entry: @@ -219,7 +215,7 @@ define dso_local i32 @bar() { ; CHECK-PTX-NEXT: .reg .b64 %SPL; ; CHECK-PTX-NEXT: .reg .b16 %rs<10>; ; CHECK-PTX-NEXT: .reg .b32 %r<4>; -; CHECK-PTX-NEXT: .reg .b64 %rd<8>; +; CHECK-PTX-NEXT: .reg .b64 %rd<7>; ; CHECK-PTX-EMPTY: ; CHECK-PTX-NEXT: // %bb.0: // %entry ; CHECK-PTX-NEXT: mov.u64 %SPL, __local_depot3; @@ -240,17 +236,16 @@ define dso_local i32 @bar() { ; CHECK-PTX-NEXT: st.u16 [%SP], %rs8; ; CHECK-PTX-NEXT: mov.b32 %r1, 1; ; CHECK-PTX-NEXT: st.u32 [%SP+8], %r1; -; CHECK-PTX-NEXT: add.u64 %rd5, %SP, 8; -; CHECK-PTX-NEXT: or.b64 %rd6, %rd5, 4; ; CHECK-PTX-NEXT: mov.b16 %rs9, 1; -; CHECK-PTX-NEXT: st.u8 [%rd6], %rs9; -; CHECK-PTX-NEXT: mov.b64 %rd7, 1; -; CHECK-PTX-NEXT: st.u64 [%SP+16], %rd7; +; CHECK-PTX-NEXT: st.u8 [%SP+12], %rs9; +; CHECK-PTX-NEXT: mov.b64 %rd5, 1; +; CHECK-PTX-NEXT: st.u64 [%SP+16], %rd5; +; CHECK-PTX-NEXT: add.u64 %rd6, %SP, 8; ; CHECK-PTX-NEXT: { // callseq 1, 0 ; CHECK-PTX-NEXT: .param .b32 param0; ; CHECK-PTX-NEXT: st.param.b32 [param0], 1; ; CHECK-PTX-NEXT: .param .b64 param1; -; CHECK-PTX-NEXT: st.param.b64 [param1], %rd5; +; CHECK-PTX-NEXT: st.param.b64 [param1], %rd6; ; CHECK-PTX-NEXT: .param .b32 retval0; ; CHECK-PTX-NEXT: call.uni (retval0), ; CHECK-PTX-NEXT: variadics2, diff --git a/llvm/test/CodeGen/PowerPC/global-merge-aix-zero-size-struct.ll b/llvm/test/CodeGen/PowerPC/global-merge-aix-zero-size-struct.ll new file mode 100644 index 000000000000..ec6fd7ee4cf4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/global-merge-aix-zero-size-struct.ll @@ -0,0 +1,20 @@ +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 < %s | FileCheck %s + +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 --filetype=obj -o %t.o < %s +; RUN: llvm-objdump --syms %t.o | FileCheck %s --check-prefix=OBJ + +%struct.anon = type {} + +@a = internal constant %struct.anon zeroinitializer, align 1 +@b = internal constant [6 x i8] c"hello\00", align 1 + +; CHECK: .csect L.._MergedGlobals[RO],2 +; CHECK-NEXT: .lglobl a # @_MergedGlobals +; CHECK-NEXT: .lglobl b +; CHECK-NEXT: a: +; CHECK-NEXT: b: +; CHECK-NEXT: .string "hello" + +; OBJ: 0000000000000000 l .text 0000000000000006 L.._MergedGlobals +; OBJ-NEXT: 0000000000000000 l .text (csect: L.._MergedGlobals) 0000000000000000 a +; OBJ-NEXT: 0000000000000000 l .text (csect: L.._MergedGlobals) 0000000000000000 b diff --git a/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll b/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll index 83763f5ef76a..2c5ad949dcc5 100644 --- a/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll +++ b/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -print-lsr-output 2>&1 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -stop-after=loop-reduce | FileCheck %s ; The icmp is a post-inc use, and the increment is in %bb11, but the ; scevgep needs to be inserted in %bb so that it is dominated by %t. diff --git a/llvm/test/CodeGen/PowerPC/memcmp.ll b/llvm/test/CodeGen/PowerPC/memcmp.ll index 0634534b9c9d..39f926999731 100644 --- a/llvm/test/CodeGen/PowerPC/memcmp.ll +++ b/llvm/test/CodeGen/PowerPC/memcmp.ll @@ -6,13 +6,12 @@ define signext i32 @memcmp8(ptr nocapture readonly %buffer1, ptr nocapture reado ; CHECK: # %bb.0: ; CHECK-NEXT: ldbrx 3, 0, 3 ; CHECK-NEXT: ldbrx 4, 0, 4 -; CHECK-NEXT: subc 5, 4, 3 -; CHECK-NEXT: subfe 5, 4, 4 -; CHECK-NEXT: subc 4, 3, 4 -; CHECK-NEXT: subfe 3, 3, 3 -; CHECK-NEXT: neg 5, 5 +; CHECK-NEXT: cmpld 3, 4 +; CHECK-NEXT: subc 3, 4, 3 +; CHECK-NEXT: subfe 3, 4, 4 +; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: neg 3, 3 -; CHECK-NEXT: sub 3, 5, 3 +; CHECK-NEXT: isellt 3, 4, 3 ; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 8) @@ -24,12 +23,11 @@ define signext i32 @memcmp4(ptr nocapture readonly %buffer1, ptr nocapture reado ; CHECK: # %bb.0: ; CHECK-NEXT: lwbrx 3, 0, 3 ; CHECK-NEXT: lwbrx 4, 0, 4 +; CHECK-NEXT: cmplw 3, 4 ; CHECK-NEXT: sub 5, 4, 3 -; CHECK-NEXT: sub 3, 3, 4 +; CHECK-NEXT: li 3, -1 ; CHECK-NEXT: rldicl 5, 5, 1, 63 -; CHECK-NEXT: rldicl 3, 3, 1, 63 -; CHECK-NEXT: sub 3, 5, 3 -; CHECK-NEXT: extsw 3, 3 +; CHECK-NEXT: isellt 3, 3, 5 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 4) ret i32 %call diff --git a/llvm/test/CodeGen/PowerPC/memcmpIR.ll b/llvm/test/CodeGen/PowerPC/memcmpIR.ll index 0a8bec7dc0e3..b57d2b5116b7 100644 --- a/llvm/test/CodeGen/PowerPC/memcmpIR.ll +++ b/llvm/test/CodeGen/PowerPC/memcmpIR.ll @@ -59,22 +59,14 @@ define signext i32 @test2(ptr nocapture readonly %buffer1, ptr nocapture readonl ; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr ; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]]) ; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]]) - ; CHECK-NEXT: [[CMP1:%[0-9]+]] = icmp ugt i32 [[BSWAP1]], [[BSWAP2]] - ; CHECK-NEXT: [[CMP2:%[0-9]+]] = icmp ult i32 [[BSWAP1]], [[BSWAP2]] - ; CHECK-NEXT: [[Z1:%[0-9]+]] = zext i1 [[CMP1]] to i32 - ; CHECK-NEXT: [[Z2:%[0-9]+]] = zext i1 [[CMP2]] to i32 - ; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i32 [[Z1]], [[Z2]] - ; CHECK-NEXT: ret i32 [[SUB]] + ; CHECK-NEXT: [[UCMP:%[0-9]+]] = call i32 @llvm.ucmp.i32.i32(i32 [[BSWAP1]], i32 [[BSWAP2]]) + ; CHECK-NEXT: ret i32 [[UCMP]] ; CHECK-BE-LABEL: @test2( ; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, ptr ; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr - ; CHECK-BE-NEXT: [[CMP1:%[0-9]+]] = icmp ugt i32 [[LOAD1]], [[LOAD2]] - ; CHECK-BE-NEXT: [[CMP2:%[0-9]+]] = icmp ult i32 [[LOAD1]], [[LOAD2]] - ; CHECK-BE-NEXT: [[Z1:%[0-9]+]] = zext i1 [[CMP1]] to i32 - ; CHECK-BE-NEXT: [[Z2:%[0-9]+]] = zext i1 [[CMP2]] to i32 - ; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i32 [[Z1]], [[Z2]] - ; CHECK-BE-NEXT: ret i32 [[SUB]] + ; CHECK-BE-NEXT: [[UCMP:%[0-9]+]] = call i32 @llvm.ucmp.i32.i32(i32 [[LOAD1]], i32 [[LOAD2]]) + ; CHECK-BE-NEXT: ret i32 [[UCMP]] entry: %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 4) diff --git a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll index 025a5ad787fb..2f0b92964c13 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll @@ -13,6 +13,8 @@ $bar1 = comdat any @bar2 = global i32 0, align 4, comdat($bar1) declare i32 @call_foo(i32, ...) +declare i32 @call_strictfp() strictfp +declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) define i32 @foo() { entry: @@ -21,6 +23,23 @@ entry: ret i32 %0 } +define i32 @foo1() strictfp { +entry: + %call = call i32 (i32, ...) @call_foo(i32 0) + ret i32 %call +} + +define i32 @foo1_strictfp() strictfp { +entry: + %call = call i32 () @call_strictfp() + ret i32 %call +} + +define void @foo2(ptr %a) { + call void @llvm.memset.p0.i64(ptr align 1 %a, i8 1, i64 1000, i1 false) + ret void +} + define i32 @load() { entry: %0 = load i32, ptr @bar1 @@ -49,6 +68,31 @@ entry: ; LARGE-SECUREPLT: addi 30, 30, .LTOC-.L0$pb@l ; LARGE-SECUREPLT: bl call_foo@PLT+32768 +; LARGE-SECUREPLT-LABEL: foo1: +; LARGE-SECUREPLT: .L1$pb: +; LARGE-SECUREPLT-NEXT: crxor 6, 6, 6 +; LARGE-SECUREPLT-NEXT: mflr 30 +; LARGE-SECUREPLT-NEXT: addis 30, 30, .LTOC-.L1$pb@ha +; LARGE-SECUREPLT-NEXT: addi 30, 30, .LTOC-.L1$pb@l +; LARGE-SECUREPLT-NEXT: li 3, 0 +; LARGE-SECUREPLT-NEXT: bl call_foo@PLT+32768 + +; LARGE-SECUREPLT-LABEL: foo1_strictfp: +; LARGE-SECUREPLT: .L2$pb: +; LARGE-SECUREPLT-NEXT: mflr 30 +; LARGE-SECUREPLT-NEXT: addis 30, 30, .LTOC-.L2$pb@ha +; LARGE-SECUREPLT-NEXT: addi 30, 30, .LTOC-.L2$pb@l +; LARGE-SECUREPLT-NEXT: bl call_strictfp@PLT+32768 + +; LARGE-SECUREPLT-LABEL: foo2: +; LARGE-SECUREPLT: .L3$pb: +; LARGE-SECUREPLT: mflr 30 +; LARGE-SECUREPLT-NEXT: addis 30, 30, .LTOC-.L3$pb@ha +; LARGE-SECUREPLT-NEXT: addi 30, 30, .LTOC-.L3$pb@l +; LARGE-SECUREPLT: bl memset@PLT+32768 + +; LARGE-SECUREPLT-LABEEL: load: + ; LARGE: .section .bss.bar1,"awG",@nobits,bar1,comdat ; LARGE: bar1: ; LARGE: .section .bss.bar2,"awG",@nobits,bar1,comdat diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll index b6799c8a88e0..f62f70ca7ac1 100644 --- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll +++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll @@ -11,24 +11,35 @@ define i8 @scalar_to_vector_half(ptr nocapture readonly %ad) { ; P9LE-LABEL: scalar_to_vector_half: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: lhz r3, 0(r3) +; P9LE-NEXT: lxsihzx v2, 0, r3 +; P9LE-NEXT: li r3, 0 +; P9LE-NEXT: vsplth v2, v2, 3 +; P9LE-NEXT: vextubrx r3, r3, v2 ; P9LE-NEXT: blr ; ; P9BE-LABEL: scalar_to_vector_half: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: lhz r3, 0(r3) -; P9BE-NEXT: srwi r3, r3, 24 +; P9BE-NEXT: lxsihzx v2, 0, r3 +; P9BE-NEXT: li r3, 0 +; P9BE-NEXT: vsplth v2, v2, 3 +; P9BE-NEXT: vextublx r3, r3, v2 ; P9BE-NEXT: blr ; ; P8LE-LABEL: scalar_to_vector_half: ; P8LE: # %bb.0: # %entry ; P8LE-NEXT: lhz r3, 0(r3) +; P8LE-NEXT: mtfprd f0, r3 +; P8LE-NEXT: mffprd r3, f0 +; P8LE-NEXT: clrldi r3, r3, 56 ; P8LE-NEXT: blr ; ; P8BE-LABEL: scalar_to_vector_half: ; P8BE: # %bb.0: # %entry ; P8BE-NEXT: lhz r3, 0(r3) -; P8BE-NEXT: srwi r3, r3, 24 +; P8BE-NEXT: sldi r3, r3, 48 +; P8BE-NEXT: mtfprd f0, r3 +; P8BE-NEXT: mffprd r3, f0 +; P8BE-NEXT: rldicl r3, r3, 8, 56 ; P8BE-NEXT: blr entry: %0 = load <2 x i8>, ptr %ad, align 1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll b/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll index ff56ab193c48..0fd23a7d346d 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll @@ -14,7 +14,7 @@ define i32 @add_positive_low_bound_reject(i32 %a) nounwind { ; ; RV64I-LABEL: add_positive_low_bound_reject: ; RV64I: # %bb.0: -; RV64I-NEXT: addi a0, a0, 2047 +; RV64I-NEXT: addiw a0, a0, 2047 ; RV64I-NEXT: ret %1 = add i32 %a, 2047 ret i32 %1 @@ -30,7 +30,7 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_positive_low_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, 2047 -; RV64I-NEXT: addi a0, a0, 1 +; RV64I-NEXT: addiw a0, a0, 1 ; RV64I-NEXT: ret %1 = add i32 %a, 2048 ret i32 %1 @@ -46,7 +46,7 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_positive_high_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, 2047 -; RV64I-NEXT: addi a0, a0, 2047 +; RV64I-NEXT: addiw a0, a0, 2047 ; RV64I-NEXT: ret %1 = add i32 %a, 4094 ret i32 %1 @@ -63,8 +63,8 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind { ; RV64I-LABEL: add_positive_high_bound_reject: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 1 -; RV64I-NEXT: addiw a1, a1, -1 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addi a1, a1, -1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: ret %1 = add i32 %a, 4095 ret i32 %1 @@ -78,7 +78,7 @@ define i32 @add_negative_high_bound_reject(i32 %a) nounwind { ; ; RV64I-LABEL: add_negative_high_bound_reject: ; RV64I: # %bb.0: -; RV64I-NEXT: addi a0, a0, -2048 +; RV64I-NEXT: addiw a0, a0, -2048 ; RV64I-NEXT: ret %1 = add i32 %a, -2048 ret i32 %1 @@ -94,7 +94,7 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_negative_high_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, -2048 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: addiw a0, a0, -1 ; RV64I-NEXT: ret %1 = add i32 %a, -2049 ret i32 %1 @@ -110,7 +110,7 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_negative_low_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, -2048 -; RV64I-NEXT: addi a0, a0, -2048 +; RV64I-NEXT: addiw a0, a0, -2048 ; RV64I-NEXT: ret %1 = add i32 %a, -4096 ret i32 %1 @@ -127,8 +127,8 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind { ; RV64I-LABEL: add_negative_low_bound_reject: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 1048575 -; RV64I-NEXT: addiw a1, a1, -1 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addi a1, a1, -1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: ret %1 = add i32 %a, -4097 ret i32 %1 @@ -144,7 +144,7 @@ define i32 @add32_accept(i32 %a) nounwind { ; RV64I-LABEL: add32_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, 2047 -; RV64I-NEXT: addi a0, a0, 952 +; RV64I-NEXT: addiw a0, a0, 952 ; RV64I-NEXT: ret %1 = add i32 %a, 2999 ret i32 %1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll index ee414992a524..f1c0fccb78a3 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll @@ -37,7 +37,7 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) { ; RV64IM-NEXT: slli a1, a1, 56 ; RV64IM-NEXT: srai a0, a0, 56 ; RV64IM-NEXT: srai a1, a1, 56 -; RV64IM-NEXT: add a0, a0, a1 +; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = sext i8 %a to i32 @@ -58,7 +58,7 @@ define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) { ; RV64IM: # %bb.0: # %entry ; RV64IM-NEXT: andi a0, a0, 255 ; RV64IM-NEXT: andi a1, a1, 255 -; RV64IM-NEXT: add a0, a0, a1 +; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = zext i8 %a to i32 @@ -78,7 +78,7 @@ define i32 @add_i32(i32 %a, i32 %b) { ; ; RV64IM-LABEL: add_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: add a0, a0, a1 +; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = add i32 %a, %b @@ -93,7 +93,7 @@ define i32 @addi_i32(i32 %a) { ; ; RV64IM-LABEL: addi_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: addi a0, a0, 1234 +; RV64IM-NEXT: addiw a0, a0, 1234 ; RV64IM-NEXT: ret entry: %0 = add i32 %a, 1234 @@ -108,7 +108,7 @@ define i32 @sub_i32(i32 %a, i32 %b) { ; ; RV64IM-LABEL: sub_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: sub a0, a0, a1 +; RV64IM-NEXT: subw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = sub i32 %a, %b @@ -123,7 +123,7 @@ define i32 @subi_i32(i32 %a) { ; ; RV64IM-LABEL: subi_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: addi a0, a0, -1234 +; RV64IM-NEXT: addiw a0, a0, -1234 ; RV64IM-NEXT: ret entry: %0 = sub i32 %a, 1234 @@ -138,7 +138,7 @@ define i32 @neg_i32(i32 %a) { ; ; RV64IM-LABEL: neg_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: neg a0, a0 +; RV64IM-NEXT: negw a0, a0 ; RV64IM-NEXT: ret entry: %0 = sub i32 0, %a diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll new file mode 100644 index 000000000000..3a55189076de --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll @@ -0,0 +1,453 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=RV32I +; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=RV32ZBB +; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=RV64I +; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=RV64ZBB + +define i32 @expanded_neg_abs32(i32 %x) { +; RV32I-LABEL: expanded_neg_abs32: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: blt a0, a1, .LBB0_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB0_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs32: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: min a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs32: +; RV64I: # %bb.0: +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: blt a2, a1, .LBB0_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB0_2: +; RV64I-NEXT: negw a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs32: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: negw a1, a0 +; RV64ZBB-NEXT: sext.w a0, a0 +; RV64ZBB-NEXT: max a0, a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.smax.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i32 @expanded_neg_abs32_unsigned(i32 %x) { +; RV32I-LABEL: expanded_neg_abs32_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: bltu a0, a1, .LBB1_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB1_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs32_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: minu a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs32_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: bltu a2, a1, .LBB1_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB1_2: +; RV64I-NEXT: negw a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs32_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: negw a1, a0 +; RV64ZBB-NEXT: sext.w a0, a0 +; RV64ZBB-NEXT: maxu a0, a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.umax.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i64 @expanded_neg_abs64(i64 %x) { +; RV32I-LABEL: expanded_neg_abs64: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB2_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: slt a4, a1, a2 +; RV32I-NEXT: beqz a4, .LBB2_3 +; RV32I-NEXT: j .LBB2_4 +; RV32I-NEXT: .LBB2_2: +; RV32I-NEXT: sltu a4, a0, a3 +; RV32I-NEXT: bnez a4, .LBB2_4 +; RV32I-NEXT: .LBB2_3: +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: .LBB2_4: +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: snez a1, a3 +; RV32I-NEXT: neg a2, a2 +; RV32I-NEXT: sub a1, a2, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs64: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB2_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: slt a4, a1, a2 +; RV32ZBB-NEXT: beqz a4, .LBB2_3 +; RV32ZBB-NEXT: j .LBB2_4 +; RV32ZBB-NEXT: .LBB2_2: +; RV32ZBB-NEXT: sltu a4, a0, a3 +; RV32ZBB-NEXT: bnez a4, .LBB2_4 +; RV32ZBB-NEXT: .LBB2_3: +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: .LBB2_4: +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: snez a1, a3 +; RV32ZBB-NEXT: neg a2, a2 +; RV32ZBB-NEXT: sub a1, a2, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs64: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: blt a0, a1, .LBB2_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB2_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs64: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: min a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.smax.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} + +define i64 @expanded_neg_abs64_unsigned(i64 %x) { +; RV32I-LABEL: expanded_neg_abs64_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB3_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: sltu a4, a1, a2 +; RV32I-NEXT: beqz a4, .LBB3_3 +; RV32I-NEXT: j .LBB3_4 +; RV32I-NEXT: .LBB3_2: +; RV32I-NEXT: sltu a4, a0, a3 +; RV32I-NEXT: bnez a4, .LBB3_4 +; RV32I-NEXT: .LBB3_3: +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: .LBB3_4: +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: snez a1, a3 +; RV32I-NEXT: neg a2, a2 +; RV32I-NEXT: sub a1, a2, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs64_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB3_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: sltu a4, a1, a2 +; RV32ZBB-NEXT: beqz a4, .LBB3_3 +; RV32ZBB-NEXT: j .LBB3_4 +; RV32ZBB-NEXT: .LBB3_2: +; RV32ZBB-NEXT: sltu a4, a0, a3 +; RV32ZBB-NEXT: bnez a4, .LBB3_4 +; RV32ZBB-NEXT: .LBB3_3: +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: .LBB3_4: +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: snez a1, a3 +; RV32ZBB-NEXT: neg a2, a2 +; RV32ZBB-NEXT: sub a1, a2, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs64_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: bltu a0, a1, .LBB3_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB3_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs64_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: minu a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.umax.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} + +define i32 @expanded_neg_inv_abs32(i32 %x) { +; RV32I-LABEL: expanded_neg_inv_abs32: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: blt a1, a0, .LBB4_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB4_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs32: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: max a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs32: +; RV64I: # %bb.0: +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: blt a1, a2, .LBB4_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB4_2: +; RV64I-NEXT: negw a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs32: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: negw a1, a0 +; RV64ZBB-NEXT: sext.w a0, a0 +; RV64ZBB-NEXT: min a0, a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.smin.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i32 @expanded_neg_inv_abs32_unsigned(i32 %x) { +; RV32I-LABEL: expanded_neg_inv_abs32_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: bltu a1, a0, .LBB5_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB5_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs32_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: maxu a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs32_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: bltu a1, a2, .LBB5_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB5_2: +; RV64I-NEXT: negw a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs32_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: negw a1, a0 +; RV64ZBB-NEXT: sext.w a0, a0 +; RV64ZBB-NEXT: minu a0, a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.umin.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i64 @expanded_neg_inv_abs64(i64 %x) { +; RV32I-LABEL: expanded_neg_inv_abs64: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB6_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: slt a4, a2, a1 +; RV32I-NEXT: beqz a4, .LBB6_3 +; RV32I-NEXT: j .LBB6_4 +; RV32I-NEXT: .LBB6_2: +; RV32I-NEXT: sltu a4, a3, a0 +; RV32I-NEXT: bnez a4, .LBB6_4 +; RV32I-NEXT: .LBB6_3: +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: .LBB6_4: +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: snez a1, a3 +; RV32I-NEXT: neg a2, a2 +; RV32I-NEXT: sub a1, a2, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs64: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB6_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: slt a4, a2, a1 +; RV32ZBB-NEXT: beqz a4, .LBB6_3 +; RV32ZBB-NEXT: j .LBB6_4 +; RV32ZBB-NEXT: .LBB6_2: +; RV32ZBB-NEXT: sltu a4, a3, a0 +; RV32ZBB-NEXT: bnez a4, .LBB6_4 +; RV32ZBB-NEXT: .LBB6_3: +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: .LBB6_4: +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: snez a1, a3 +; RV32ZBB-NEXT: neg a2, a2 +; RV32ZBB-NEXT: sub a1, a2, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs64: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: blt a1, a0, .LBB6_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB6_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs64: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: max a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.smin.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} + +define i64 @expanded_neg_inv_abs64_unsigned(i64 %x) { +; RV32I-LABEL: expanded_neg_inv_abs64_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB7_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: sltu a4, a2, a1 +; RV32I-NEXT: beqz a4, .LBB7_3 +; RV32I-NEXT: j .LBB7_4 +; RV32I-NEXT: .LBB7_2: +; RV32I-NEXT: sltu a4, a3, a0 +; RV32I-NEXT: bnez a4, .LBB7_4 +; RV32I-NEXT: .LBB7_3: +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: .LBB7_4: +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: snez a1, a3 +; RV32I-NEXT: neg a2, a2 +; RV32I-NEXT: sub a1, a2, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs64_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB7_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: sltu a4, a2, a1 +; RV32ZBB-NEXT: beqz a4, .LBB7_3 +; RV32ZBB-NEXT: j .LBB7_4 +; RV32ZBB-NEXT: .LBB7_2: +; RV32ZBB-NEXT: sltu a4, a3, a0 +; RV32ZBB-NEXT: bnez a4, .LBB7_4 +; RV32ZBB-NEXT: .LBB7_3: +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: .LBB7_4: +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: snez a1, a3 +; RV32ZBB-NEXT: neg a2, a2 +; RV32ZBB-NEXT: sub a1, a2, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs64_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: bltu a1, a0, .LBB7_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB7_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs64_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: maxu a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.umin.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll index 9c7fd6895d37..360e84d37ec8 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll @@ -21,6 +21,7 @@ define i32 @constant_to_rhs(i32 %x) { ; RV64-O0-NEXT: mv a1, a0 ; RV64-O0-NEXT: li a0, 1 ; RV64-O0-NEXT: add a0, a0, a1 +; RV64-O0-NEXT: sext.w a0, a0 ; RV64-O0-NEXT: ret ; ; RV32-OPT-LABEL: constant_to_rhs: @@ -30,7 +31,7 @@ define i32 @constant_to_rhs(i32 %x) { ; ; RV64-OPT-LABEL: constant_to_rhs: ; RV64-OPT: # %bb.0: -; RV64-OPT-NEXT: addi a0, a0, 1 +; RV64-OPT-NEXT: addiw a0, a0, 1 ; RV64-OPT-NEXT: ret %a = add i32 1, %x ret i32 %a diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll index 385156b3b99d..487869922658 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll @@ -1,9 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 - ; RUN: llc -mtriple=riscv32 -mattr=+zfa,d -global-isel < %s \ -; RUN: | FileCheck %s +; RUN: | FileCheck %s --check-prefixes=CHECK,RV32IDZFA ; RUN: llc -mtriple=riscv64 -mattr=+zfa,d -global-isel < %s \ -; RUN: | FileCheck %s +; RUN: | FileCheck %s --check-prefixes=CHECK,RV64DZFA define double @fceil(double %a) { @@ -86,3 +85,32 @@ define double @fminimum(double %a, double %b) { %c = call double @llvm.minimum.f64(double %a, double %b) ret double %c } + +define i64 @fmvh_x_d(double %fa) { +; RV32IDZFA-LABEL: fmvh_x_d: +; RV32IDZFA: # %bb.0: +; RV32IDZFA-NEXT: fmv.x.w a0, fa0 +; RV32IDZFA-NEXT: fmvh.x.d a1, fa0 +; RV32IDZFA-NEXT: ret +; +; RV64DZFA-LABEL: fmvh_x_d: +; RV64DZFA: # %bb.0: +; RV64DZFA-NEXT: fmv.x.d a0, fa0 +; RV64DZFA-NEXT: ret + %i = bitcast double %fa to i64 + ret i64 %i +} + +define double @fmvp_d_x(i64 %a) { +; RV32IDZFA-LABEL: fmvp_d_x: +; RV32IDZFA: # %bb.0: +; RV32IDZFA-NEXT: fmvp.d.x fa0, a0, a1 +; RV32IDZFA-NEXT: ret +; +; RV64DZFA-LABEL: fmvp_d_x: +; RV64DZFA: # %bb.0: +; RV64DZFA-NEXT: fmv.d.x fa0, a0 +; RV64DZFA-NEXT: ret + %or = bitcast i64 %a to double + ret double %or +} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll index 72f0ab159f0a..234f33841206 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll @@ -96,12 +96,19 @@ define ptr @freeze_ptr(ptr %x) { %struct.T = type { i32, i32 } define i32 @freeze_struct(ptr %p) { -; CHECK-LABEL: freeze_struct: -; CHECK: # %bb.0: -; CHECK-NEXT: lw a1, 0(a0) -; CHECK-NEXT: lw a0, 4(a0) -; CHECK-NEXT: add a0, a1, a0 -; CHECK-NEXT: ret +; RV32-LABEL: freeze_struct: +; RV32: # %bb.0: +; RV32-NEXT: lw a1, 0(a0) +; RV32-NEXT: lw a0, 4(a0) +; RV32-NEXT: add a0, a1, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: freeze_struct: +; RV64: # %bb.0: +; RV64-NEXT: lw a1, 0(a0) +; RV64-NEXT: lw a0, 4(a0) +; RV64-NEXT: addw a0, a1, a0 +; RV64-NEXT: ret %s = load %struct.T, ptr %p %y1 = freeze %struct.T %s %v1 = extractvalue %struct.T %y1, 0 @@ -111,12 +118,19 @@ define i32 @freeze_struct(ptr %p) { } define i32 @freeze_anonstruct(ptr %p) { -; CHECK-LABEL: freeze_anonstruct: -; CHECK: # %bb.0: -; CHECK-NEXT: lw a1, 0(a0) -; CHECK-NEXT: lw a0, 4(a0) -; CHECK-NEXT: add a0, a1, a0 -; CHECK-NEXT: ret +; RV32-LABEL: freeze_anonstruct: +; RV32: # %bb.0: +; RV32-NEXT: lw a1, 0(a0) +; RV32-NEXT: lw a0, 4(a0) +; RV32-NEXT: add a0, a1, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: freeze_anonstruct: +; RV64: # %bb.0: +; RV64-NEXT: lw a1, 0(a0) +; RV64-NEXT: lw a0, 4(a0) +; RV64-NEXT: addw a0, a1, a0 +; RV64-NEXT: ret %s = load {i32, i32}, ptr %p %y1 = freeze {i32, i32} %s %v1 = extractvalue {i32, i32} %y1, 0 @@ -141,7 +155,7 @@ define i32 @freeze_anonstruct2(ptr %p) { ; RV64-NEXT: lw a0, 0(a0) ; RV64-NEXT: slli a1, a1, 48 ; RV64-NEXT: srli a1, a1, 48 -; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: addw a0, a0, a1 ; RV64-NEXT: ret %s = load {i32, i16}, ptr %p %y1 = freeze {i32, i16} %s @@ -168,7 +182,7 @@ define i32 @freeze_anonstruct2_sext(ptr %p) { ; RV64-NEXT: lw a0, 0(a0) ; RV64-NEXT: slli a1, a1, 48 ; RV64-NEXT: srai a1, a1, 48 -; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: addw a0, a0, a1 ; RV64-NEXT: ret %s = load {i32, i16}, ptr %p %y1 = freeze {i32, i16} %s @@ -180,12 +194,19 @@ define i32 @freeze_anonstruct2_sext(ptr %p) { } define i32 @freeze_array(ptr %p) nounwind { -; CHECK-LABEL: freeze_array: -; CHECK: # %bb.0: -; CHECK-NEXT: lw a1, 0(a0) -; CHECK-NEXT: lw a0, 4(a0) -; CHECK-NEXT: add a0, a1, a0 -; CHECK-NEXT: ret +; RV32-LABEL: freeze_array: +; RV32: # %bb.0: +; RV32-NEXT: lw a1, 0(a0) +; RV32-NEXT: lw a0, 4(a0) +; RV32-NEXT: add a0, a1, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: freeze_array: +; RV64: # %bb.0: +; RV64-NEXT: lw a1, 0(a0) +; RV64-NEXT: lw a0, 4(a0) +; RV64-NEXT: addw a0, a1, a0 +; RV64-NEXT: ret %s = load [2 x i32], ptr %p %y1 = freeze [2 x i32] %s %v1 = extractvalue [2 x i32] %y1, 0 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll index 1156edffe919..31a78d4f72ce 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll @@ -98,7 +98,7 @@ define i32 @abs32(i32 %x) { ; RV64I-LABEL: abs32: ; RV64I: # %bb.0: ; RV64I-NEXT: sraiw a1, a0, 31 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir index a27e2b80cd98..dbc13840a026 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir @@ -23,7 +23,7 @@ # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # # DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices -# DEBUG-NEXT: .. opcode [[SUB_OPC]] is aliased to [[ADD_OPC]] +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # @@ -59,7 +59,6 @@ # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # # DEBUG-NEXT: G_AND (opcode {{[0-9]+}}): 1 type index, 0 imm indices -# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir index 22ce8a0fd0df..78a2227b84a3 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir @@ -86,9 +86,10 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64) ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]] - ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]] - ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32 - ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SEXT_INREG]], [[ASHR]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: abs_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir index 48b65a1dd6ba..8f2b9f36eb9f 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir @@ -69,7 +69,8 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] - ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir index f2ec70933261..eed1aac8f6c1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir @@ -339,7 +339,7 @@ body: | ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] - ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 %2:_(s64) = COPY $x10 @@ -454,10 +454,11 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] - ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 - ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 - ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] - ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG1]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 %2:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir index 57fc513dc9e3..e28572d05207 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir @@ -145,7 +145,8 @@ body: | ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -64769 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] - ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s32) = G_CONSTANT i32 -64769 %1:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir index 6cc5477b85a4..62d731351ffd 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir @@ -59,7 +59,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s8) = G_TRUNC %1(s64) @@ -129,7 +130,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s16) = G_TRUNC %1(s64) @@ -175,16 +177,19 @@ body: | ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C2]](s64) ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]] - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C7]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C8]] ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]] @@ -192,7 +197,8 @@ body: | ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[C10]](s64) ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR8]] - ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: ctlz_i32 @@ -328,7 +334,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s8) = G_TRUNC %1(s64) @@ -398,7 +405,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s16) = G_TRUNC %1(s64) @@ -444,16 +452,19 @@ body: | ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C2]](s64) ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]] - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C7]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C8]] ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]] @@ -461,7 +472,8 @@ body: | ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[C10]](s64) ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR8]] - ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: ctlz_zero_undef_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir index 1493514394bd..c61c46df0a43 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir @@ -129,18 +129,21 @@ body: | ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C4]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C5]](s64) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C5]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C6]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C6]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[C7]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir index 252e79280af6..87155bb8b743 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir @@ -131,7 +131,8 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[SEXT_INREG]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] @@ -139,18 +140,21 @@ body: | ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C2]] ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C5]] ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG2]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG2]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD2]], 32 ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG3]], [[C7]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]] @@ -351,7 +355,8 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[SEXT_INREG]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] @@ -359,18 +364,21 @@ body: | ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C2]] ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C5]] ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG2]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG2]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD2]], 32 ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG3]], [[C7]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir index f3bc1ce28cfa..aff7d4d3ec1e 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir @@ -30,8 +30,9 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C]] ; CHECK-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir index 4689a7dd219a..776f5f53fafb 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir @@ -88,9 +88,10 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]] - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND1]] ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SLLW]], [[SRLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) @@ -233,9 +234,10 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND]] - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND1]] ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SRLW]], [[SLLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir index bf8c8d690f07..d162bfcca1bc 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir @@ -16,8 +16,8 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) @@ -97,7 +97,8 @@ body: | ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483648 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) + ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG3]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) @@ -173,10 +174,11 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) - ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 - ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 - ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG1]](s64), [[SEXT_INREG2]] ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[TRUNC]] @@ -250,7 +252,8 @@ body: | ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483648 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) + ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG3]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir index da3ab9e1a527..7ab07ee0d70d 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir @@ -69,7 +69,8 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] - ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll index 0b876fed59c1..9df319e73a11 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll @@ -18,7 +18,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -30,15 +30,15 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -75,7 +75,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -87,15 +87,15 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -133,15 +133,14 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: li s0, 32 -; RV64I-NEXT: addi a0, a0, -1 -; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: addiw a0, a0, -1 ; RV64I-NEXT: li a1, 32 -; RV64I-NEXT: beqz a2, .LBB2_2 +; RV64I-NEXT: beqz a0, .LBB2_2 ; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -153,15 +152,15 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -200,7 +199,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a0, a0, 1 ; RV64I-NEXT: lui a1, 349525 ; RV64I-NEXT: or a0, s0, a0 -; RV64I-NEXT: addiw a1, a1, 1365 +; RV64I-NEXT: addi a1, a1, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -212,15 +211,15 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -271,7 +270,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: srliw a0, a0, 2 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srli a2, a0, 4 @@ -283,15 +282,15 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -299,7 +298,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: li a1, 32 -; RV64I-NEXT: sub a0, a1, a0 +; RV64I-NEXT: subw a0, a1, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: .cfi_restore ra ; RV64I-NEXT: addi sp, sp, 16 @@ -408,19 +407,19 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -451,19 +450,19 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -493,19 +492,19 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a1, s0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -549,19 +548,19 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a1, s0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -669,18 +668,18 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 -; RV64I-NEXT: addiw a2, a2, 1365 +; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -706,18 +705,18 @@ define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 -; RV64I-NEXT: addiw a2, a2, 1365 +; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -746,19 +745,19 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: lui a1, 349525 -; RV64I-NEXT: addiw a1, a1, 1365 +; RV64I-NEXT: addi a1, a1, 1365 ; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -1057,7 +1056,7 @@ define i32 @abs_i32(i32 %x) { ; RV64I-LABEL: abs_i32: ; RV64I: # %bb.0: ; RV64I-NEXT: sraiw a1, a0, 31 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll index 4346e04ecda6..daeb2e69c83b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll @@ -97,7 +97,7 @@ define i32 @scmp.32.32(i32 %x, i32 %y) nounwind { ; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: slt a2, a1, a0 ; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.scmp(i32 %x, i32 %y) ret i32 %1 @@ -122,7 +122,7 @@ define i32 @scmp.32.64(i64 %x, i64 %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slt a2, a1, a0 ; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.scmp(i64 %x, i64 %y) ret i32 %1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll index 9784c58dca4f..463883b371ca 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll @@ -97,7 +97,7 @@ define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind { ; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i32 %x, i32 %y) ret i32 %1 @@ -115,7 +115,7 @@ define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i32 %x, i32 %y) ret i32 %1 @@ -135,7 +135,7 @@ define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind { ; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i32 %x, i32 %y) ret i32 %1 @@ -160,7 +160,7 @@ define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i64 %x, i64 %y) ret i32 %1 diff --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll index 47b6c07cc699..d7f62ae83434 100644 --- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll +++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll @@ -1,17 +1,28 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=RV64 %s +; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefixes=RV64,NO-ZBA %s +; RUN: llc -mtriple=riscv64 -mattr=+zba < %s | FileCheck -check-prefixes=RV64,ZBA %s define void @add_sext_shl_moreOneUse_add(ptr %array1, i32 %a, i32 %b) { -; RV64-LABEL: add_sext_shl_moreOneUse_add: -; RV64: # %bb.0: # %entry -; RV64-NEXT: addi a3, a1, 5 -; RV64-NEXT: sext.w a1, a1 -; RV64-NEXT: slli a1, a1, 2 -; RV64-NEXT: add a0, a1, a0 -; RV64-NEXT: sw a2, 20(a0) -; RV64-NEXT: sw a2, 24(a0) -; RV64-NEXT: sw a3, 140(a0) -; RV64-NEXT: ret +; NO-ZBA-LABEL: add_sext_shl_moreOneUse_add: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a3, a1, 5 +; NO-ZBA-NEXT: sext.w a1, a1 +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: add a0, a1, a0 +; NO-ZBA-NEXT: sw a2, 20(a0) +; NO-ZBA-NEXT: sw a2, 24(a0) +; NO-ZBA-NEXT: sw a3, 140(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_sext_shl_moreOneUse_add: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a3, a1, 5 +; ZBA-NEXT: sext.w a1, a1 +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: sw a2, 20(a0) +; ZBA-NEXT: sw a2, 24(a0) +; ZBA-NEXT: sw a3, 140(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 5 %idxprom = sext i32 %add to i64 @@ -29,19 +40,32 @@ entry: } define void @add_sext_shl_moreOneUse_addexceedsign12(ptr %array1, i32 %a, i32 %b) { -; RV64-LABEL: add_sext_shl_moreOneUse_addexceedsign12: -; RV64: # %bb.0: # %entry -; RV64-NEXT: addi a3, a1, 2047 -; RV64-NEXT: lui a4, 2 -; RV64-NEXT: sext.w a1, a1 -; RV64-NEXT: addi a3, a3, 1 -; RV64-NEXT: slli a1, a1, 2 -; RV64-NEXT: add a0, a0, a4 -; RV64-NEXT: add a0, a0, a1 -; RV64-NEXT: sw a2, 0(a0) -; RV64-NEXT: sw a3, 4(a0) -; RV64-NEXT: sw a2, 120(a0) -; RV64-NEXT: ret +; NO-ZBA-LABEL: add_sext_shl_moreOneUse_addexceedsign12: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a3, a1, 2047 +; NO-ZBA-NEXT: lui a4, 2 +; NO-ZBA-NEXT: sext.w a1, a1 +; NO-ZBA-NEXT: addi a3, a3, 1 +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: add a0, a0, a4 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: sw a2, 0(a0) +; NO-ZBA-NEXT: sw a3, 4(a0) +; NO-ZBA-NEXT: sw a2, 120(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_sext_shl_moreOneUse_addexceedsign12: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a3, a1, 2047 +; ZBA-NEXT: lui a4, 2 +; ZBA-NEXT: sext.w a1, a1 +; ZBA-NEXT: addi a3, a3, 1 +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: add a0, a0, a4 +; ZBA-NEXT: sw a2, 0(a0) +; ZBA-NEXT: sw a3, 4(a0) +; ZBA-NEXT: sw a2, 120(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 2048 %idxprom = sext i32 %add to i64 @@ -57,16 +81,26 @@ entry: } define void @add_sext_shl_moreOneUse_sext(ptr %array1, i32 %a, i32 %b) { -; RV64-LABEL: add_sext_shl_moreOneUse_sext: -; RV64: # %bb.0: # %entry -; RV64-NEXT: sext.w a1, a1 -; RV64-NEXT: addi a3, a1, 5 -; RV64-NEXT: slli a1, a1, 2 -; RV64-NEXT: add a0, a1, a0 -; RV64-NEXT: sw a2, 20(a0) -; RV64-NEXT: sw a2, 24(a0) -; RV64-NEXT: sd a3, 140(a0) -; RV64-NEXT: ret +; NO-ZBA-LABEL: add_sext_shl_moreOneUse_sext: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: sext.w a1, a1 +; NO-ZBA-NEXT: addi a3, a1, 5 +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: add a0, a1, a0 +; NO-ZBA-NEXT: sw a2, 20(a0) +; NO-ZBA-NEXT: sw a2, 24(a0) +; NO-ZBA-NEXT: sd a3, 140(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_sext_shl_moreOneUse_sext: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: sext.w a1, a1 +; ZBA-NEXT: addi a3, a1, 5 +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: sw a2, 20(a0) +; ZBA-NEXT: sw a2, 24(a0) +; ZBA-NEXT: sd a3, 140(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 5 %idxprom = sext i32 %add to i64 @@ -85,20 +119,34 @@ entry: ; test of jumpping, find add's operand has one more use can simplified define void @add_sext_shl_moreOneUse_add_inSelect(ptr %array1, i32 signext %a, i32 %b, i32 signext %x) { -; RV64-LABEL: add_sext_shl_moreOneUse_add_inSelect: -; RV64: # %bb.0: # %entry -; RV64-NEXT: addi a4, a1, 5 -; RV64-NEXT: mv a5, a4 -; RV64-NEXT: bgtz a3, .LBB3_2 -; RV64-NEXT: # %bb.1: # %entry -; RV64-NEXT: mv a5, a2 -; RV64-NEXT: .LBB3_2: # %entry -; RV64-NEXT: slli a1, a1, 2 -; RV64-NEXT: add a0, a1, a0 -; RV64-NEXT: sw a5, 20(a0) -; RV64-NEXT: sw a5, 24(a0) -; RV64-NEXT: sw a4, 140(a0) -; RV64-NEXT: ret +; NO-ZBA-LABEL: add_sext_shl_moreOneUse_add_inSelect: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a4, a1, 5 +; NO-ZBA-NEXT: mv a5, a4 +; NO-ZBA-NEXT: bgtz a3, .LBB3_2 +; NO-ZBA-NEXT: # %bb.1: # %entry +; NO-ZBA-NEXT: mv a5, a2 +; NO-ZBA-NEXT: .LBB3_2: # %entry +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: add a0, a1, a0 +; NO-ZBA-NEXT: sw a5, 20(a0) +; NO-ZBA-NEXT: sw a5, 24(a0) +; NO-ZBA-NEXT: sw a4, 140(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_sext_shl_moreOneUse_add_inSelect: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a4, a1, 5 +; ZBA-NEXT: mv a5, a4 +; ZBA-NEXT: bgtz a3, .LBB3_2 +; ZBA-NEXT: # %bb.1: # %entry +; ZBA-NEXT: mv a5, a2 +; ZBA-NEXT: .LBB3_2: # %entry +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: sw a5, 20(a0) +; ZBA-NEXT: sw a5, 24(a0) +; ZBA-NEXT: sw a4, 140(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 5 %cmp = icmp sgt i32 %x, 0 @@ -118,23 +166,40 @@ entry: } define void @add_sext_shl_moreOneUse_add_inSelect_addexceedsign12(ptr %array1, i32 signext %a, i32 %b, i32 signext %x) { -; RV64-LABEL: add_sext_shl_moreOneUse_add_inSelect_addexceedsign12: -; RV64: # %bb.0: # %entry -; RV64-NEXT: addi a4, a1, 2047 -; RV64-NEXT: lui a5, 2 -; RV64-NEXT: slli a6, a1, 2 -; RV64-NEXT: addi a1, a4, 1 -; RV64-NEXT: add a0, a0, a6 -; RV64-NEXT: add a0, a0, a5 -; RV64-NEXT: mv a4, a1 -; RV64-NEXT: bgtz a3, .LBB4_2 -; RV64-NEXT: # %bb.1: # %entry -; RV64-NEXT: mv a4, a2 -; RV64-NEXT: .LBB4_2: # %entry -; RV64-NEXT: sw a4, 0(a0) -; RV64-NEXT: sw a4, 4(a0) -; RV64-NEXT: sw a1, 120(a0) -; RV64-NEXT: ret +; NO-ZBA-LABEL: add_sext_shl_moreOneUse_add_inSelect_addexceedsign12: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a4, a1, 2047 +; NO-ZBA-NEXT: lui a5, 2 +; NO-ZBA-NEXT: slli a6, a1, 2 +; NO-ZBA-NEXT: addi a1, a4, 1 +; NO-ZBA-NEXT: add a0, a0, a6 +; NO-ZBA-NEXT: add a0, a0, a5 +; NO-ZBA-NEXT: mv a4, a1 +; NO-ZBA-NEXT: bgtz a3, .LBB4_2 +; NO-ZBA-NEXT: # %bb.1: # %entry +; NO-ZBA-NEXT: mv a4, a2 +; NO-ZBA-NEXT: .LBB4_2: # %entry +; NO-ZBA-NEXT: sw a4, 0(a0) +; NO-ZBA-NEXT: sw a4, 4(a0) +; NO-ZBA-NEXT: sw a1, 120(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_sext_shl_moreOneUse_add_inSelect_addexceedsign12: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a4, a1, 2047 +; ZBA-NEXT: lui a5, 2 +; ZBA-NEXT: addi a4, a4, 1 +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: add a0, a0, a5 +; ZBA-NEXT: mv a1, a4 +; ZBA-NEXT: bgtz a3, .LBB4_2 +; ZBA-NEXT: # %bb.1: # %entry +; ZBA-NEXT: mv a1, a2 +; ZBA-NEXT: .LBB4_2: # %entry +; ZBA-NEXT: sw a1, 0(a0) +; ZBA-NEXT: sw a1, 4(a0) +; ZBA-NEXT: sw a4, 120(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 2048 %cmp = icmp sgt i32 %x, 0 @@ -152,20 +217,34 @@ entry: } define void @add_shl_moreOneUse_inSelect(ptr %array1, i64 %a, i64 %b, i64 %x) { -; RV64-LABEL: add_shl_moreOneUse_inSelect: -; RV64: # %bb.0: # %entry -; RV64-NEXT: addi a4, a1, 5 -; RV64-NEXT: mv a5, a4 -; RV64-NEXT: bgtz a3, .LBB5_2 -; RV64-NEXT: # %bb.1: # %entry -; RV64-NEXT: mv a5, a2 -; RV64-NEXT: .LBB5_2: # %entry -; RV64-NEXT: slli a1, a1, 3 -; RV64-NEXT: add a0, a1, a0 -; RV64-NEXT: sd a5, 40(a0) -; RV64-NEXT: sd a5, 48(a0) -; RV64-NEXT: sd a4, 280(a0) -; RV64-NEXT: ret +; NO-ZBA-LABEL: add_shl_moreOneUse_inSelect: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a4, a1, 5 +; NO-ZBA-NEXT: mv a5, a4 +; NO-ZBA-NEXT: bgtz a3, .LBB5_2 +; NO-ZBA-NEXT: # %bb.1: # %entry +; NO-ZBA-NEXT: mv a5, a2 +; NO-ZBA-NEXT: .LBB5_2: # %entry +; NO-ZBA-NEXT: slli a1, a1, 3 +; NO-ZBA-NEXT: add a0, a1, a0 +; NO-ZBA-NEXT: sd a5, 40(a0) +; NO-ZBA-NEXT: sd a5, 48(a0) +; NO-ZBA-NEXT: sd a4, 280(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_inSelect: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a4, a1, 5 +; ZBA-NEXT: mv a5, a4 +; ZBA-NEXT: bgtz a3, .LBB5_2 +; ZBA-NEXT: # %bb.1: # %entry +; ZBA-NEXT: mv a5, a2 +; ZBA-NEXT: .LBB5_2: # %entry +; ZBA-NEXT: sh3add a0, a1, a0 +; ZBA-NEXT: sd a5, 40(a0) +; ZBA-NEXT: sd a5, 48(a0) +; ZBA-NEXT: sd a4, 280(a0) +; ZBA-NEXT: ret entry: %add = add nsw i64 %a, 5 %cmp = icmp sgt i64 %x, 0 @@ -180,3 +259,103 @@ entry: store i64 %add, ptr %arrayidx6 ret void } + +define i64 @add_shl_moreOneUse_sh1add(i64 %x) { +; NO-ZBA-LABEL: add_shl_moreOneUse_sh1add: +; NO-ZBA: # %bb.0: +; NO-ZBA-NEXT: ori a1, a0, 1 +; NO-ZBA-NEXT: slli a0, a0, 1 +; NO-ZBA-NEXT: ori a0, a0, 2 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_sh1add: +; ZBA: # %bb.0: +; ZBA-NEXT: ori a0, a0, 1 +; ZBA-NEXT: sh1add a0, a0, a0 +; ZBA-NEXT: ret + %or = or i64 %x, 1 + %mul = shl i64 %or, 1 + %add = add i64 %mul, %or + ret i64 %add +} + +define i64 @add_shl_moreOneUse_sh2add(i64 %x) { +; NO-ZBA-LABEL: add_shl_moreOneUse_sh2add: +; NO-ZBA: # %bb.0: +; NO-ZBA-NEXT: ori a1, a0, 1 +; NO-ZBA-NEXT: slli a0, a0, 2 +; NO-ZBA-NEXT: ori a0, a0, 4 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_sh2add: +; ZBA: # %bb.0: +; ZBA-NEXT: ori a0, a0, 1 +; ZBA-NEXT: sh2add a0, a0, a0 +; ZBA-NEXT: ret + %or = or i64 %x, 1 + %mul = shl i64 %or, 2 + %add = add i64 %mul, %or + ret i64 %add +} + +define i64 @add_shl_moreOneUse_sh3add(i64 %x) { +; NO-ZBA-LABEL: add_shl_moreOneUse_sh3add: +; NO-ZBA: # %bb.0: +; NO-ZBA-NEXT: ori a1, a0, 1 +; NO-ZBA-NEXT: slli a0, a0, 3 +; NO-ZBA-NEXT: ori a0, a0, 8 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_sh3add: +; ZBA: # %bb.0: +; ZBA-NEXT: ori a0, a0, 1 +; ZBA-NEXT: sh3add a0, a0, a0 +; ZBA-NEXT: ret + %or = or i64 %x, 1 + %mul = shl i64 %or, 3 + %add = add i64 %mul, %or + ret i64 %add +} + +;; Covers a case which previously crashed (pr119527) +define i64 @add_shl_sext(i32 %1) { +; RV64-LABEL: add_shl_sext: +; RV64: # %bb.0: +; RV64-NEXT: addi a1, a0, 3 +; RV64-NEXT: sllw a0, a1, a0 +; RV64-NEXT: ret + %3 = add i32 %1, 3 + %4 = shl i32 %3, %1 + %5 = sext i32 %4 to i64 + ret i64 %5 +} + +define i64 @add_shl_moreOneUse_sh4add(i64 %x) { +; RV64-LABEL: add_shl_moreOneUse_sh4add: +; RV64: # %bb.0: +; RV64-NEXT: ori a1, a0, 1 +; RV64-NEXT: slli a0, a0, 4 +; RV64-NEXT: ori a0, a0, 16 +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: ret + %or = or i64 %x, 1 + %mul = shl i64 %or, 4 + %add = add i64 %mul, %or + ret i64 %add +} + +define i64 @add_shl_rhs_constant(i64 %x, i64 %y) { +; RV64-LABEL: add_shl_rhs_constant: +; RV64: # %bb.0: +; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: slli a0, a0, 3 +; RV64-NEXT: ret + %a = add i64 %x, 1 + %b = add i64 %y, %a + %c = shl i64 %b, 3 + %d = add i64 %c, -8 + ret i64 %d +} diff --git a/llvm/test/CodeGen/RISCV/add_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_shl_constant.ll index 71b61868b8c8..a4da9e268364 100644 --- a/llvm/test/CodeGen/RISCV/add_shl_constant.ll +++ b/llvm/test/CodeGen/RISCV/add_shl_constant.ll @@ -1,13 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 < %s | FileCheck -check-prefix=RV32 %s +; RUN: llc -mtriple=riscv32 < %s | FileCheck -check-prefixes=RV32,NO-ZBA %s +; RUN: llc -mtriple=riscv32 -mattr=+zba < %s | FileCheck -check-prefixes=RV32,ZBA %s define i32 @add_shl_oneUse(i32 %x, i32 %y) nounwind { -; RV32-LABEL: add_shl_oneUse: -; RV32: # %bb.0: -; RV32-NEXT: slli a0, a0, 3 -; RV32-NEXT: add a0, a0, a1 -; RV32-NEXT: addi a0, a0, 984 -; RV32-NEXT: ret +; NO-ZBA-LABEL: add_shl_oneUse: +; NO-ZBA: # %bb.0: +; NO-ZBA-NEXT: slli a0, a0, 3 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: addi a0, a0, 984 +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_oneUse: +; ZBA: # %bb.0: +; ZBA-NEXT: addi a0, a0, 123 +; ZBA-NEXT: sh3add a0, a0, a1 +; ZBA-NEXT: ret %add.0 = add i32 %x, 123 %shl = shl i32 %add.0, 3 %add.1 = add i32 %shl, %y @@ -15,15 +22,24 @@ define i32 @add_shl_oneUse(i32 %x, i32 %y) nounwind { } define void @add_shl_moreOneUse_inStore(ptr %array1, i32 %a, i32 %b) { -; RV32-LABEL: add_shl_moreOneUse_inStore: -; RV32: # %bb.0: # %entry -; RV32-NEXT: addi a3, a1, 5 -; RV32-NEXT: slli a1, a1, 2 -; RV32-NEXT: add a0, a0, a1 -; RV32-NEXT: sw a2, 20(a0) -; RV32-NEXT: sw a2, 24(a0) -; RV32-NEXT: sw a3, 140(a0) -; RV32-NEXT: ret +; NO-ZBA-LABEL: add_shl_moreOneUse_inStore: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a3, a1, 5 +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: sw a2, 20(a0) +; NO-ZBA-NEXT: sw a2, 24(a0) +; NO-ZBA-NEXT: sw a3, 140(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_inStore: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a3, a1, 5 +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: sw a2, 20(a0) +; ZBA-NEXT: sw a2, 24(a0) +; ZBA-NEXT: sw a3, 140(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 5 %arrayidx = getelementptr inbounds i32, ptr %array1, i32 %add @@ -37,18 +53,30 @@ entry: } define void @add_shl_moreOneUse_inStore_addexceedsign12(ptr %array1, i32 %a, i32 %b) { -; RV32-LABEL: add_shl_moreOneUse_inStore_addexceedsign12: -; RV32: # %bb.0: # %entry -; RV32-NEXT: addi a3, a1, 2047 -; RV32-NEXT: lui a4, 2 -; RV32-NEXT: slli a1, a1, 2 -; RV32-NEXT: addi a3, a3, 1 -; RV32-NEXT: add a0, a0, a1 -; RV32-NEXT: add a0, a0, a4 -; RV32-NEXT: sw a2, 0(a0) -; RV32-NEXT: sw a3, 4(a0) -; RV32-NEXT: sw a2, 120(a0) -; RV32-NEXT: ret +; NO-ZBA-LABEL: add_shl_moreOneUse_inStore_addexceedsign12: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a3, a1, 2047 +; NO-ZBA-NEXT: lui a4, 2 +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: addi a3, a3, 1 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: add a0, a0, a4 +; NO-ZBA-NEXT: sw a2, 0(a0) +; NO-ZBA-NEXT: sw a3, 4(a0) +; NO-ZBA-NEXT: sw a2, 120(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_inStore_addexceedsign12: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a3, a1, 2047 +; ZBA-NEXT: lui a4, 2 +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: addi a3, a3, 1 +; ZBA-NEXT: add a0, a0, a4 +; ZBA-NEXT: sw a2, 0(a0) +; ZBA-NEXT: sw a3, 4(a0) +; ZBA-NEXT: sw a2, 120(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 2048 %arrayidx = getelementptr inbounds i32, ptr %array1, i32 %add @@ -62,20 +90,34 @@ entry: } define void @add_shl_moreOneUse_inSelect(ptr %array1, i32 %a, i32 %b, i32 %x) { -; RV32-LABEL: add_shl_moreOneUse_inSelect: -; RV32: # %bb.0: # %entry -; RV32-NEXT: addi a4, a1, 5 -; RV32-NEXT: mv a5, a4 -; RV32-NEXT: bgtz a3, .LBB3_2 -; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: mv a5, a2 -; RV32-NEXT: .LBB3_2: # %entry -; RV32-NEXT: slli a1, a1, 2 -; RV32-NEXT: add a0, a0, a1 -; RV32-NEXT: sw a5, 20(a0) -; RV32-NEXT: sw a5, 24(a0) -; RV32-NEXT: sw a4, 140(a0) -; RV32-NEXT: ret +; NO-ZBA-LABEL: add_shl_moreOneUse_inSelect: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a4, a1, 5 +; NO-ZBA-NEXT: mv a5, a4 +; NO-ZBA-NEXT: bgtz a3, .LBB3_2 +; NO-ZBA-NEXT: # %bb.1: # %entry +; NO-ZBA-NEXT: mv a5, a2 +; NO-ZBA-NEXT: .LBB3_2: # %entry +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: sw a5, 20(a0) +; NO-ZBA-NEXT: sw a5, 24(a0) +; NO-ZBA-NEXT: sw a4, 140(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_inSelect: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a4, a1, 5 +; ZBA-NEXT: mv a5, a4 +; ZBA-NEXT: bgtz a3, .LBB3_2 +; ZBA-NEXT: # %bb.1: # %entry +; ZBA-NEXT: mv a5, a2 +; ZBA-NEXT: .LBB3_2: # %entry +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: sw a5, 20(a0) +; ZBA-NEXT: sw a5, 24(a0) +; ZBA-NEXT: sw a4, 140(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 5 %cmp = icmp sgt i32 %x, 0 @@ -91,23 +133,40 @@ entry: } define void @add_shl_moreOneUse_inSelect_addexceedsign12(ptr %array1, i32 %a, i32 %b, i32 %x) { -; RV32-LABEL: add_shl_moreOneUse_inSelect_addexceedsign12: -; RV32: # %bb.0: # %entry -; RV32-NEXT: addi a4, a1, 2047 -; RV32-NEXT: addi a4, a4, 1 -; RV32-NEXT: mv a5, a4 -; RV32-NEXT: bgtz a3, .LBB4_2 -; RV32-NEXT: # %bb.1: # %entry -; RV32-NEXT: mv a5, a2 -; RV32-NEXT: .LBB4_2: # %entry -; RV32-NEXT: lui a2, 2 -; RV32-NEXT: slli a1, a1, 2 -; RV32-NEXT: add a0, a0, a1 -; RV32-NEXT: add a0, a0, a2 -; RV32-NEXT: sw a5, 0(a0) -; RV32-NEXT: sw a5, 4(a0) -; RV32-NEXT: sw a4, 120(a0) -; RV32-NEXT: ret +; NO-ZBA-LABEL: add_shl_moreOneUse_inSelect_addexceedsign12: +; NO-ZBA: # %bb.0: # %entry +; NO-ZBA-NEXT: addi a4, a1, 2047 +; NO-ZBA-NEXT: addi a4, a4, 1 +; NO-ZBA-NEXT: mv a5, a4 +; NO-ZBA-NEXT: bgtz a3, .LBB4_2 +; NO-ZBA-NEXT: # %bb.1: # %entry +; NO-ZBA-NEXT: mv a5, a2 +; NO-ZBA-NEXT: .LBB4_2: # %entry +; NO-ZBA-NEXT: lui a2, 2 +; NO-ZBA-NEXT: slli a1, a1, 2 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: add a0, a0, a2 +; NO-ZBA-NEXT: sw a5, 0(a0) +; NO-ZBA-NEXT: sw a5, 4(a0) +; NO-ZBA-NEXT: sw a4, 120(a0) +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_inSelect_addexceedsign12: +; ZBA: # %bb.0: # %entry +; ZBA-NEXT: addi a4, a1, 2047 +; ZBA-NEXT: addi a4, a4, 1 +; ZBA-NEXT: mv a5, a4 +; ZBA-NEXT: bgtz a3, .LBB4_2 +; ZBA-NEXT: # %bb.1: # %entry +; ZBA-NEXT: mv a5, a2 +; ZBA-NEXT: .LBB4_2: # %entry +; ZBA-NEXT: lui a2, 2 +; ZBA-NEXT: sh2add a0, a1, a0 +; ZBA-NEXT: add a0, a0, a2 +; ZBA-NEXT: sw a5, 0(a0) +; ZBA-NEXT: sw a5, 4(a0) +; ZBA-NEXT: sw a4, 120(a0) +; ZBA-NEXT: ret entry: %add = add nsw i32 %a, 2048 %cmp = icmp sgt i32 %x, 0 @@ -121,3 +180,77 @@ entry: store i32 %add, ptr %arrayidx6 ret void } + +define i32 @add_shl_moreOneUse_sh1add(i32 %x) { +; NO-ZBA-LABEL: add_shl_moreOneUse_sh1add: +; NO-ZBA: # %bb.0: +; NO-ZBA-NEXT: ori a1, a0, 1 +; NO-ZBA-NEXT: slli a0, a0, 1 +; NO-ZBA-NEXT: ori a0, a0, 2 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_sh1add: +; ZBA: # %bb.0: +; ZBA-NEXT: ori a0, a0, 1 +; ZBA-NEXT: sh1add a0, a0, a0 +; ZBA-NEXT: ret + %or = or i32 %x, 1 + %mul = shl i32 %or, 1 + %add = add i32 %mul, %or + ret i32 %add +} + +define i32 @add_shl_moreOneUse_sh2add(i32 %x) { +; NO-ZBA-LABEL: add_shl_moreOneUse_sh2add: +; NO-ZBA: # %bb.0: +; NO-ZBA-NEXT: ori a1, a0, 1 +; NO-ZBA-NEXT: slli a0, a0, 2 +; NO-ZBA-NEXT: ori a0, a0, 4 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_sh2add: +; ZBA: # %bb.0: +; ZBA-NEXT: ori a0, a0, 1 +; ZBA-NEXT: sh2add a0, a0, a0 +; ZBA-NEXT: ret + %or = or i32 %x, 1 + %mul = shl i32 %or, 2 + %add = add i32 %mul, %or + ret i32 %add +} + +define i32 @add_shl_moreOneUse_sh3add(i32 %x) { +; NO-ZBA-LABEL: add_shl_moreOneUse_sh3add: +; NO-ZBA: # %bb.0: +; NO-ZBA-NEXT: ori a1, a0, 1 +; NO-ZBA-NEXT: slli a0, a0, 3 +; NO-ZBA-NEXT: ori a0, a0, 8 +; NO-ZBA-NEXT: add a0, a0, a1 +; NO-ZBA-NEXT: ret +; +; ZBA-LABEL: add_shl_moreOneUse_sh3add: +; ZBA: # %bb.0: +; ZBA-NEXT: ori a0, a0, 1 +; ZBA-NEXT: sh3add a0, a0, a0 +; ZBA-NEXT: ret + %or = or i32 %x, 1 + %mul = shl i32 %or, 3 + %add = add i32 %mul, %or + ret i32 %add +} + +define i32 @add_shl_moreOneUse_sh4add(i32 %x) { +; RV32-LABEL: add_shl_moreOneUse_sh4add: +; RV32: # %bb.0: +; RV32-NEXT: ori a1, a0, 1 +; RV32-NEXT: slli a0, a0, 4 +; RV32-NEXT: ori a0, a0, 16 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: ret + %or = or i32 %x, 1 + %mul = shl i32 %or, 4 + %add = add i32 %mul, %or + ret i32 %add +} diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index f63bc944ccf2..c0fcc6f61111 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -82,6 +82,9 @@ ; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s ; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm %s -o - | FileCheck --check-prefix=RV32XQCICM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s @@ -294,6 +297,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s ; Tests for profile features. ; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s @@ -391,6 +396,9 @@ ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2" ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2" +; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p2" +; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2" +; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2" ; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2" ; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2" ; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2" @@ -601,6 +609,8 @@ ; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0" ; RV64SMCTR: .attribute 5, "rv64i2p1_smctr1p0_sscsrind1p0" ; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0" +; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0" +; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" ; RVI20U32: .attribute 5, "rv32i2p1" ; RVI20U64: .attribute 5, "rv64i2p1" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 99db90c5fa92..70fbda47a14a 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -15,6 +15,8 @@ ; CHECK: e - 'E' (Embedded Instruction Set with 16 GPRs). ; CHECK: experimental - Experimental intrinsics. ; CHECK: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. +; CHECK: experimental-sdext - 'Sdext' (External debugger). +; CHECK: experimental-sdtrig - 'Sdtrig' (Debugger triggers). ; CHECK: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level). ; CHECK: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level). ; CHECK: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). diff --git a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll index 4c47b5f741fa..2c428cf4ac87 100644 --- a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll +++ b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll @@ -20,7 +20,7 @@ define void @f2(ptr noundef %x) #0 { ; CHECK-NEXT: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprtc = COPY $x10 - ; CHECK-NEXT: PseudoTAILIndirect [[COPY]], implicit $x2, cfi-type 12345678 + ; CHECK-NEXT: PseudoTAILIndirect [[COPY]], csr_ilp32_lp64, implicit $x2, cfi-type 12345678 tail call void %x() [ "kcfi"(i32 12345678) ] ret void } diff --git a/llvm/test/CodeGen/RISCV/kcfi-mir.ll b/llvm/test/CodeGen/RISCV/kcfi-mir.ll index f9f383a35358..0c0d39a8bf87 100644 --- a/llvm/test/CodeGen/RISCV/kcfi-mir.ll +++ b/llvm/test/CodeGen/RISCV/kcfi-mir.ll @@ -30,7 +30,7 @@ define void @f2(ptr noundef %x) #0 { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: BUNDLE implicit-def $x6, implicit-def $x6_w, implicit-def $x6_h, implicit-def $x7, implicit-def $x7_w, implicit-def $x7_h, implicit-def $x28, implicit-def $x28_w, implicit-def $x28_h, implicit-def $x29, implicit-def $x29_w, implicit-def $x29_h, implicit-def $x30, implicit-def $x30_w, implicit-def $x30_h, implicit-def $x31, implicit-def $x31_w, implicit-def $x31_h, implicit killed $x10, implicit $x2 { ; CHECK-NEXT: KCFI_CHECK $x10, 12345678, implicit-def $x6, implicit-def $x7, implicit-def $x28, implicit-def $x29, implicit-def $x30, implicit-def $x31 - ; CHECK-NEXT: PseudoTAILIndirect killed $x10, implicit $x2 + ; CHECK-NEXT: PseudoTAILIndirect killed $x10, csr_ilp32_lp64, implicit $x2 ; CHECK-NEXT: } tail call void %x() [ "kcfi"(i32 12345678) ] ret void diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll index d529ae6ecd0a..f9086ba9d635 100644 --- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll +++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll @@ -2449,82 +2449,72 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV32-ZBB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV32-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: srli a2, a2, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: srli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a0, 2(a0) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a2, 2(a0) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lhu a0, 0(a0) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a3, 2(a1) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lhu a1, 0(a1) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a2, a2, 16 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a3, a3, 16 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a0, 2(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a2, 2(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 2(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 16 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 16 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV32-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: srli a2, a2, 16 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: srli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lhu a2, 0(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lbu a0, 2(a0) +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lhu a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: pack a0, a2, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: pack a1, a3, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a0, 2(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a2, 2(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a3, 2(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a2, a2, 16 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a3, a3, 16 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_3: @@ -2658,9 +2648,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_4: @@ -2671,9 +2661,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a1, a1, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_4: @@ -2682,9 +2672,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_4: @@ -2695,9 +2685,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a1, a1, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_4: @@ -2845,22 +2835,19 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_5: ; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB26_2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a0, 4(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB26_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a2, 4(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 4(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_5: @@ -2883,22 +2870,17 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_5: ; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB26_2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a2, 0(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a0, 4(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB26_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a1, a3, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_5: @@ -3052,28 +3034,19 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_6: ; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a0, 4(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: -; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB27_3: # %res_block -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a2, 4(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a3, 4(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_6: @@ -3102,28 +3075,17 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind optsize { ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_6: ; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a0, 4(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB27_3: # %res_block -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a2, 0(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a0, 4(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a3, 0(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a1, 4(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a1, a3, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_6: @@ -3500,9 +3462,9 @@ define i32 @memcmp_size_8(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_8: @@ -3533,9 +3495,9 @@ define i32 @memcmp_size_8(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_8: diff --git a/llvm/test/CodeGen/RISCV/memcmp.ll b/llvm/test/CodeGen/RISCV/memcmp.ll index 860c3a94abc0..f0290298e362 100644 --- a/llvm/test/CodeGen/RISCV/memcmp.ll +++ b/llvm/test/CodeGen/RISCV/memcmp.ll @@ -2710,6 +2710,216 @@ entry: ret i1 %ret } +define i1 @bcmp_le_zero(ptr %s1, ptr %s2) nounwind { +; CHECK-ALIGNED-RV32-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV32: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-NEXT: call bcmp +; CHECK-ALIGNED-RV32-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-NEXT: ret +; +; CHECK-ALIGNED-RV64-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV64: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-NEXT: call bcmp +; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBB-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV32-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBB-NEXT: call bcmp +; CHECK-ALIGNED-RV32-ZBB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBB-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV64-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBB-NEXT: call bcmp +; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBKB-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV32-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: call bcmp +; CHECK-ALIGNED-RV32-ZBKB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBKB-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV64-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: call bcmp +; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV32-V-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-V-NEXT: call bcmp +; CHECK-ALIGNED-RV32-V-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-V-NEXT: ret +; +; CHECK-ALIGNED-RV64-V-LABEL: bcmp_le_zero: +; CHECK-ALIGNED-RV64-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-V-NEXT: call bcmp +; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-V-NEXT: ret +; +; CHECK-UNALIGNED-LABEL: bcmp_le_zero: +; CHECK-UNALIGNED: # %bb.0: # %entry +; CHECK-UNALIGNED-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-NEXT: xor a0, a0, a1 +; CHECK-UNALIGNED-NEXT: snez a0, a0 +; CHECK-UNALIGNED-NEXT: slti a0, a0, 1 +; CHECK-UNALIGNED-NEXT: ret +entry: + %bcmp = call signext i32 @bcmp(ptr %s1, ptr %s2, iXLen 4) + %ret = icmp slt i32 %bcmp, 1 + ret i1 %ret +} + +define i1 @bcmp_ge_zero(ptr %s1, ptr %s2) nounwind { +; CHECK-ALIGNED-RV32-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV32: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-NEXT: call bcmp +; CHECK-ALIGNED-RV32-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-NEXT: ret +; +; CHECK-ALIGNED-RV64-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV64: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-NEXT: call bcmp +; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBB-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV32-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBB-NEXT: call bcmp +; CHECK-ALIGNED-RV32-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBB-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV64-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBB-NEXT: call bcmp +; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBKB-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV32-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: call bcmp +; CHECK-ALIGNED-RV32-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBKB-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV64-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: call bcmp +; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV32-V-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-V-NEXT: call bcmp +; CHECK-ALIGNED-RV32-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-V-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-V-NEXT: ret +; +; CHECK-ALIGNED-RV64-V-LABEL: bcmp_ge_zero: +; CHECK-ALIGNED-RV64-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-V-NEXT: call bcmp +; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-V-NEXT: ret +; +; CHECK-UNALIGNED-LABEL: bcmp_ge_zero: +; CHECK-UNALIGNED: # %bb.0: # %entry +; CHECK-UNALIGNED-NEXT: li a0, 1 +; CHECK-UNALIGNED-NEXT: ret +entry: + %bcmp = call signext i32 @bcmp(ptr %s1, ptr %s2, iXLen 4) + %ret = icmp sgt i32 %bcmp, -1 + ret i1 %ret +} + define i32 @memcmp_size_0(ptr %s1, ptr %s2) nounwind { ; CHECK-LABEL: memcmp_size_0: ; CHECK: # %bb.0: # %entry @@ -3145,82 +3355,72 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind { ; ; CHECK-UNALIGNED-RV32-ZBB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV32-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: srli a2, a2, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: srli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a0, 2(a0) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a2, 2(a0) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lhu a0, 0(a0) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a3, 2(a1) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lhu a1, 0(a1) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a2, a2, 16 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a3, a3, 16 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a0, 2(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a2, 2(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 2(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 16 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 16 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV32-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: srli a2, a2, 16 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: srli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lhu a2, 0(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lbu a0, 2(a0) +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lhu a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: pack a0, a2, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: pack a1, a3, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_3: ; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB24_2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a0, 2(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a1, 2(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB24_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a2, 2(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a3, 2(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a2, a2, 16 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a3, a3, 16 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_3: @@ -3354,9 +3554,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_4: @@ -3367,9 +3567,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a1, a1, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_4: @@ -3378,9 +3578,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_4: @@ -3391,9 +3591,9 @@ define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a1, a1, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_4: @@ -3527,13 +3727,13 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB26_2 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB28_2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a0, 4(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a1, 4(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sub a0, a0, a1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB26_2: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB28_2: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -3541,22 +3741,19 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind { ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_5: ; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB26_2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a0, 4(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB26_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a2, 4(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 4(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_5: @@ -3565,13 +3762,13 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB26_2 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB28_2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lbu a0, 4(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lbu a1, 4(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sub a0, a0, a1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB26_2: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB28_2: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -3579,22 +3776,17 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind { ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_5: ; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB26_2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a2, 0(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a0, 4(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB26_2: # %res_block -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a1, a3, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_5: @@ -3728,7 +3920,7 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB27_3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB29_3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lh a0, 4(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lh a1, 4(a1) @@ -3736,11 +3928,11 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: srli a2, a2, 16 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: srli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB27_3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB29_3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV32-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB27_3: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB29_3: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -3748,28 +3940,19 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind { ; ; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_size_6: ; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a0, 4(a0) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: lh a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: -; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB27_3: # %res_block -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a2, 4(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a3, 4(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_6: @@ -3778,7 +3961,7 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB27_3 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB29_3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lh a0, 4(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lh a1, 4(a1) @@ -3786,11 +3969,11 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: srli a2, a2, 16 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: srli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB27_3 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB29_3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB27_3: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB29_3: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -3798,28 +3981,17 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind { ; ; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_size_6: ; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a2, 0(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a3, 0(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a0, 4(a0) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lh a1, 4(a1) -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 48 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB27_3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB27_3: # %res_block -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a2, 0(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a0, 4(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lwu a3, 0(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a1, 4(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: pack a1, a3, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_6: @@ -3953,17 +4125,17 @@ define i32 @memcmp_size_7(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 3(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 3(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV32-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB28_3: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB30_3: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -3977,7 +4149,7 @@ define i32 @memcmp_size_7(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 32 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a0, 3(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a1, 3(a1) @@ -3985,11 +4157,11 @@ define i32 @memcmp_size_7(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a2, a2, 32 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB28_3: # %res_block +; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB30_3: # %res_block ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 @@ -4001,17 +4173,17 @@ define i32 @memcmp_size_7(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 3(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 3(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB28_3: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB30_3: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -4025,7 +4197,7 @@ define i32 @memcmp_size_7(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 32 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a0, 3(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a1, 3(a1) @@ -4033,11 +4205,11 @@ define i32 @memcmp_size_7(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a2, a2, 32 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB28_3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB30_3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB28_3: # %res_block +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB30_3: # %res_block ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 @@ -4174,17 +4346,17 @@ define i32 @memcmp_size_8(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB29_3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB31_3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 4(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 4(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB29_3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB31_3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV32-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB29_3: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB31_3: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -4196,9 +4368,9 @@ define i32 @memcmp_size_8(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_size_8: @@ -4207,17 +4379,17 @@ define i32 @memcmp_size_8(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB29_3 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB31_3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 4(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 4(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB29_3 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB31_3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB29_3: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB31_3: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -4229,9 +4401,9 @@ define i32 @memcmp_size_8(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a1, a0 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a0, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a2, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a2, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sub a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret ; ; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_size_8: @@ -4365,29 +4537,29 @@ define i32 @memcmp_size_15(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 11(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 11(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV32-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB30_5: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB32_5: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -4399,17 +4571,17 @@ define i32 @memcmp_size_15(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB30_3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB32_3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a0, 7(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 7(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB30_3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB32_3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB30_3: # %res_block +; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB32_3: # %res_block ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 @@ -4421,29 +4593,29 @@ define i32 @memcmp_size_15(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 11(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 11(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB30_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB30_5: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB32_5: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -4455,17 +4627,17 @@ define i32 @memcmp_size_15(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB30_3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB32_3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a0, 7(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 7(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB30_3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB32_3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB30_3: # %res_block +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB32_3: # %res_block ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 @@ -4602,29 +4774,29 @@ define i32 @memcmp_size_16(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 12(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 12(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV32-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB31_5: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB33_5: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -4636,17 +4808,17 @@ define i32 @memcmp_size_16(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB31_3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB33_3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a0, 8(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 8(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB31_3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB33_3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB31_3: # %res_block +; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB33_3: # %res_block ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 @@ -4658,29 +4830,29 @@ define i32 @memcmp_size_16(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 12(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 12(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB31_5 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB31_5: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB33_5: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -4692,17 +4864,17 @@ define i32 @memcmp_size_16(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB31_3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB33_3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a0, 8(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 8(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB31_3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB33_3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB31_3: # %res_block +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB33_3: # %res_block ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 @@ -4839,53 +5011,53 @@ define i32 @memcmp_size_31(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 12(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 12(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 16(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 16(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 20(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 20(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 24(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 24(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 27(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 27(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV32-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB32_9: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB34_9: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -4897,29 +5069,29 @@ define i32 @memcmp_size_31(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a0, 23(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 23(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB32_5: # %res_block +; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB34_5: # %res_block ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 @@ -4931,53 +5103,53 @@ define i32 @memcmp_size_31(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 12(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 12(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 16(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 16(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 20(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 20(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 24(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 24(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 27(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 27(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB32_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB34_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB32_9: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB34_9: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -4989,29 +5161,29 @@ define i32 @memcmp_size_31(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a0, 23(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 23(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB32_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB32_5: # %res_block +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB34_5: # %res_block ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 @@ -5148,53 +5320,53 @@ define i32 @memcmp_size_32(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 12(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 12(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 16(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 16(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 20(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 20(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a2, 24(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a3, 24(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 28(a0) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 28(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV32-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB33_9: # %res_block +; CHECK-UNALIGNED-RV32-ZBB-NEXT: .LBB35_9: # %res_block ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: ori a0, a0, 1 @@ -5206,29 +5378,29 @@ define i32 @memcmp_size_32(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a0, 24(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 24(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB33_5: # %res_block +; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB35_5: # %res_block ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 @@ -5240,53 +5412,53 @@ define i32 @memcmp_size_32(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 0(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 4(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 4(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 8(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 8(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 12(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 12(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 16(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 16(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 20(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 20(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a2, 24(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a3, 24(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 28(a0) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 28(a1) ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB33_9 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: bne a2, a3, .LBB35_9 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB33_9: # %res_block +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: .LBB35_9: # %res_block ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ori a0, a0, 1 @@ -5298,29 +5470,29 @@ define i32 @memcmp_size_32(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a0, 24(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 24(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB33_5 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.4: ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB33_5: # %res_block +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB35_5: # %res_block ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 @@ -5417,53 +5589,53 @@ define i32 @memcmp_size_63(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 24(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 24(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 32(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 32(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 40(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 40(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 48(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 48(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a0, 55(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 55(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB34_9: # %res_block +; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB36_9: # %res_block ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 @@ -5475,53 +5647,53 @@ define i32 @memcmp_size_63(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 24(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 24(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 32(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 32(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 40(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 40(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 48(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 48(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a0, 55(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 55(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB34_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB36_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB34_9: # %res_block +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB36_9: # %res_block ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 @@ -5608,53 +5780,53 @@ define i32 @memcmp_size_64(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 24(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 24(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 32(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 32(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 40(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 40(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a2, 48(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a3, 48(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a0, 56(a0) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ld a1, 56(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV64-ZBB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB35_9: # %res_block +; CHECK-UNALIGNED-RV64-ZBB-NEXT: .LBB37_9: # %res_block ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: ori a0, a0, 1 @@ -5666,53 +5838,53 @@ define i32 @memcmp_size_64(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.1: # %loadbb1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 8(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 8(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.2: # %loadbb2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 16(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 16(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.3: # %loadbb3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 24(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 24(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.4: # %loadbb4 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 32(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 32(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.5: # %loadbb5 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 40(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 40(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.6: # %loadbb6 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a2, 48(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a3, 48(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a3 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.7: # %loadbb7 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a0, 56(a0) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ld a1, 56(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a2, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a3, a1 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB35_9 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: bne a2, a3, .LBB37_9 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: # %bb.8: ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: li a0, 0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB35_9: # %res_block +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: .LBB37_9: # %res_block ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a2, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: neg a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ori a0, a0, 1 @@ -6374,5 +6546,381 @@ entry: %ret = icmp sgt i32 %memcmp, 0 ret i1 %ret } + +define i1 @memcmp_le_zero(ptr %s1, ptr %s2) nounwind { +; CHECK-ALIGNED-RV32-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV32: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-NEXT: call memcmp +; CHECK-ALIGNED-RV32-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-NEXT: ret +; +; CHECK-ALIGNED-RV64-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV64: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-NEXT: call memcmp +; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBB-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV32-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBB-NEXT: call memcmp +; CHECK-ALIGNED-RV32-ZBB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBB-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV64-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBB-NEXT: call memcmp +; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBKB-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV32-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: call memcmp +; CHECK-ALIGNED-RV32-ZBKB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBKB-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV64-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: call memcmp +; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV32-V-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-V-NEXT: call memcmp +; CHECK-ALIGNED-RV32-V-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-V-NEXT: ret +; +; CHECK-ALIGNED-RV64-V-LABEL: memcmp_le_zero: +; CHECK-ALIGNED-RV64-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-V-NEXT: call memcmp +; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 1 +; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-V-NEXT: ret +; +; CHECK-UNALIGNED-RV32-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV32: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-UNALIGNED-RV32-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV32-NEXT: call memcmp +; CHECK-UNALIGNED-RV32-NEXT: slti a0, a0, 1 +; CHECK-UNALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-UNALIGNED-RV32-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV32-NEXT: ret +; +; CHECK-UNALIGNED-RV64-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV64: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-UNALIGNED-RV64-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV64-NEXT: call memcmp +; CHECK-UNALIGNED-RV64-NEXT: slti a0, a0, 1 +; CHECK-UNALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-UNALIGNED-RV64-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV64-NEXT: ret +; +; CHECK-UNALIGNED-RV32-ZBB-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV32-ZBB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret +; +; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret +; +; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV32-ZBKB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret +; +; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a1, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret +; +; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-V-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-UNALIGNED-RV32-V-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV32-V-NEXT: call memcmp +; CHECK-UNALIGNED-RV32-V-NEXT: slti a0, a0, 1 +; CHECK-UNALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-UNALIGNED-RV32-V-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV32-V-NEXT: ret +; +; CHECK-UNALIGNED-RV64-V-LABEL: memcmp_le_zero: +; CHECK-UNALIGNED-RV64-V: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-V-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-UNALIGNED-RV64-V-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV64-V-NEXT: call memcmp +; CHECK-UNALIGNED-RV64-V-NEXT: slti a0, a0, 1 +; CHECK-UNALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-UNALIGNED-RV64-V-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV64-V-NEXT: ret +entry: + %memcmp = call signext i32 @memcmp(ptr %s1, ptr %s2, iXLen 4) + %ret = icmp slt i32 %memcmp, 1 + ret i1 %ret +} + +define i1 @memcmp_ge_zero(ptr %s1, ptr %s2) nounwind { +; CHECK-ALIGNED-RV32-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV32: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-NEXT: call memcmp +; CHECK-ALIGNED-RV32-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-NEXT: ret +; +; CHECK-ALIGNED-RV64-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV64: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-NEXT: call memcmp +; CHECK-ALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBB-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV32-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBB-NEXT: call memcmp +; CHECK-ALIGNED-RV32-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBB-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV64-ZBB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBB-NEXT: call memcmp +; CHECK-ALIGNED-RV64-ZBB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBB-NEXT: ret +; +; CHECK-ALIGNED-RV32-ZBKB-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV32-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: call memcmp +; CHECK-ALIGNED-RV32-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV64-ZBKB-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV64-ZBKB: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-ZBKB-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: call memcmp +; CHECK-ALIGNED-RV64-ZBKB-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-ZBKB-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret +; +; CHECK-ALIGNED-RV32-V-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-ALIGNED-RV32-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV32-V-NEXT: call memcmp +; CHECK-ALIGNED-RV32-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV32-V-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-ALIGNED-RV32-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV32-V-NEXT: ret +; +; CHECK-ALIGNED-RV64-V-LABEL: memcmp_ge_zero: +; CHECK-ALIGNED-RV64-V: # %bb.0: # %entry +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, -16 +; CHECK-ALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-ALIGNED-RV64-V-NEXT: li a2, 4 +; CHECK-ALIGNED-RV64-V-NEXT: call memcmp +; CHECK-ALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-ALIGNED-RV64-V-NEXT: xori a0, a0, 1 +; CHECK-ALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-ALIGNED-RV64-V-NEXT: addi sp, sp, 16 +; CHECK-ALIGNED-RV64-V-NEXT: ret +; +; CHECK-UNALIGNED-RV32-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV32: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-UNALIGNED-RV32-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV32-NEXT: call memcmp +; CHECK-UNALIGNED-RV32-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV32-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-UNALIGNED-RV32-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV32-NEXT: ret +; +; CHECK-UNALIGNED-RV64-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV64: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-UNALIGNED-RV64-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV64-NEXT: call memcmp +; CHECK-UNALIGNED-RV64-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-UNALIGNED-RV64-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV64-NEXT: ret +; +; CHECK-UNALIGNED-RV32-ZBB-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV32-ZBB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a0, a0, a1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: ret +; +; CHECK-UNALIGNED-RV64-ZBB-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV64-ZBB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a0, a0, a1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: ret +; +; CHECK-UNALIGNED-RV32-ZBKB-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV32-ZBKB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: sltu a0, a0, a1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV32-ZBKB-NEXT: ret +; +; CHECK-UNALIGNED-RV64-ZBKB-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV64-ZBKB: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a0, 0(a0) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lw a1, 0(a1) +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a1, a1, 32 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: sltu a0, a0, a1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: ret +; +; CHECK-UNALIGNED-RV32-V-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV32-V: # %bb.0: # %entry +; CHECK-UNALIGNED-RV32-V-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV32-V-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK-UNALIGNED-RV32-V-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV32-V-NEXT: call memcmp +; CHECK-UNALIGNED-RV32-V-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV32-V-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV32-V-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK-UNALIGNED-RV32-V-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV32-V-NEXT: ret +; +; CHECK-UNALIGNED-RV64-V-LABEL: memcmp_ge_zero: +; CHECK-UNALIGNED-RV64-V: # %bb.0: # %entry +; CHECK-UNALIGNED-RV64-V-NEXT: addi sp, sp, -16 +; CHECK-UNALIGNED-RV64-V-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-UNALIGNED-RV64-V-NEXT: li a2, 4 +; CHECK-UNALIGNED-RV64-V-NEXT: call memcmp +; CHECK-UNALIGNED-RV64-V-NEXT: slti a0, a0, 0 +; CHECK-UNALIGNED-RV64-V-NEXT: xori a0, a0, 1 +; CHECK-UNALIGNED-RV64-V-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-UNALIGNED-RV64-V-NEXT: addi sp, sp, 16 +; CHECK-UNALIGNED-RV64-V-NEXT: ret +entry: + %memcmp = call signext i32 @memcmp(ptr %s1, ptr %s2, iXLen 4) + %ret = icmp sgt i32 %memcmp, -1 + ret i1 %ret +} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; CHECK-ALIGNED: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/neg-abs.ll b/llvm/test/CodeGen/RISCV/neg-abs.ll index 7d6a6d7ed4ce..fe19a4fa8bbd 100644 --- a/llvm/test/CodeGen/RISCV/neg-abs.ll +++ b/llvm/test/CodeGen/RISCV/neg-abs.ll @@ -258,3 +258,447 @@ define i64 @neg_abs64_multiuse(i64 %x, ptr %y) { %neg = sub nsw i64 0, %abs ret i64 %neg } + +define i32 @expanded_neg_abs32(i32 %x) { +; RV32I-LABEL: expanded_neg_abs32: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: blt a0, a1, .LBB6_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB6_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs32: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: min a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs32: +; RV64I: # %bb.0: +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: blt a1, a0, .LBB6_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: .LBB6_2: +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs32: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: sext.w a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: max a0, a0, a1 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.smax.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i32 @expanded_neg_abs32_unsigned(i32 %x) { +; RV32I-LABEL: expanded_neg_abs32_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: bltu a0, a1, .LBB7_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB7_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs32_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: minu a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs32_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: bltu a1, a0, .LBB7_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: .LBB7_2: +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs32_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: sext.w a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: maxu a0, a0, a1 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.umax.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i64 @expanded_neg_abs64(i64 %x) { +; RV32I-LABEL: expanded_neg_abs64: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB8_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: slt a4, a1, a2 +; RV32I-NEXT: beqz a4, .LBB8_3 +; RV32I-NEXT: j .LBB8_4 +; RV32I-NEXT: .LBB8_2: +; RV32I-NEXT: sltu a4, a0, a3 +; RV32I-NEXT: bnez a4, .LBB8_4 +; RV32I-NEXT: .LBB8_3: +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: .LBB8_4: +; RV32I-NEXT: snez a0, a3 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs64: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB8_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: slt a4, a1, a2 +; RV32ZBB-NEXT: beqz a4, .LBB8_3 +; RV32ZBB-NEXT: j .LBB8_4 +; RV32ZBB-NEXT: .LBB8_2: +; RV32ZBB-NEXT: sltu a4, a0, a3 +; RV32ZBB-NEXT: bnez a4, .LBB8_4 +; RV32ZBB-NEXT: .LBB8_3: +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: .LBB8_4: +; RV32ZBB-NEXT: snez a0, a3 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs64: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: blt a0, a1, .LBB8_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB8_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs64: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: min a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.smax.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} + +define i64 @expanded_neg_abs64_unsigned(i64 %x) { +; RV32I-LABEL: expanded_neg_abs64_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB9_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: sltu a4, a1, a2 +; RV32I-NEXT: beqz a4, .LBB9_3 +; RV32I-NEXT: j .LBB9_4 +; RV32I-NEXT: .LBB9_2: +; RV32I-NEXT: sltu a4, a0, a3 +; RV32I-NEXT: bnez a4, .LBB9_4 +; RV32I-NEXT: .LBB9_3: +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: .LBB9_4: +; RV32I-NEXT: snez a0, a3 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_abs64_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB9_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: sltu a4, a1, a2 +; RV32ZBB-NEXT: beqz a4, .LBB9_3 +; RV32ZBB-NEXT: j .LBB9_4 +; RV32ZBB-NEXT: .LBB9_2: +; RV32ZBB-NEXT: sltu a4, a0, a3 +; RV32ZBB-NEXT: bnez a4, .LBB9_4 +; RV32ZBB-NEXT: .LBB9_3: +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: .LBB9_4: +; RV32ZBB-NEXT: snez a0, a3 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_abs64_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: bltu a0, a1, .LBB9_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB9_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_abs64_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: minu a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.umax.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} + +define i32 @expanded_neg_inv_abs32(i32 %x) { +; RV32I-LABEL: expanded_neg_inv_abs32: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: blt a1, a0, .LBB10_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB10_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs32: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: max a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs32: +; RV64I: # %bb.0: +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: blt a0, a1, .LBB10_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: .LBB10_2: +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs32: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: sext.w a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: min a0, a0, a1 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.smin.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i32 @expanded_neg_inv_abs32_unsigned(i32 %x) { +; RV32I-LABEL: expanded_neg_inv_abs32_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: bltu a1, a0, .LBB11_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: .LBB11_2: +; RV32I-NEXT: neg a0, a1 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs32_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: maxu a0, a0, a1 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs32_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: sext.w a1, a0 +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: bltu a0, a1, .LBB11_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a0, a1 +; RV64I-NEXT: .LBB11_2: +; RV64I-NEXT: negw a0, a0 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs32_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: sext.w a1, a0 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: minu a0, a0, a1 +; RV64ZBB-NEXT: negw a0, a0 +; RV64ZBB-NEXT: ret + %n = sub i32 0, %x + %t = call i32 @llvm.umin.i32(i32 %n, i32 %x) + %r = sub i32 0, %t + ret i32 %r +} + +define i64 @expanded_neg_inv_abs64(i64 %x) { +; RV32I-LABEL: expanded_neg_inv_abs64: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB12_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: slt a4, a2, a1 +; RV32I-NEXT: beqz a4, .LBB12_3 +; RV32I-NEXT: j .LBB12_4 +; RV32I-NEXT: .LBB12_2: +; RV32I-NEXT: sltu a4, a3, a0 +; RV32I-NEXT: bnez a4, .LBB12_4 +; RV32I-NEXT: .LBB12_3: +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: .LBB12_4: +; RV32I-NEXT: snez a0, a3 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs64: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB12_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: slt a4, a2, a1 +; RV32ZBB-NEXT: beqz a4, .LBB12_3 +; RV32ZBB-NEXT: j .LBB12_4 +; RV32ZBB-NEXT: .LBB12_2: +; RV32ZBB-NEXT: sltu a4, a3, a0 +; RV32ZBB-NEXT: bnez a4, .LBB12_4 +; RV32ZBB-NEXT: .LBB12_3: +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: .LBB12_4: +; RV32ZBB-NEXT: snez a0, a3 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs64: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: blt a1, a0, .LBB12_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB12_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs64: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: max a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.smin.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} + +define i64 @expanded_neg_inv_abs64_unsigned(i64 %x) { +; RV32I-LABEL: expanded_neg_inv_abs64_unsigned: +; RV32I: # %bb.0: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a3, a1 +; RV32I-NEXT: sub a2, a3, a2 +; RV32I-NEXT: neg a3, a0 +; RV32I-NEXT: beq a2, a1, .LBB13_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: sltu a4, a2, a1 +; RV32I-NEXT: beqz a4, .LBB13_3 +; RV32I-NEXT: j .LBB13_4 +; RV32I-NEXT: .LBB13_2: +; RV32I-NEXT: sltu a4, a3, a0 +; RV32I-NEXT: bnez a4, .LBB13_4 +; RV32I-NEXT: .LBB13_3: +; RV32I-NEXT: mv a2, a1 +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: .LBB13_4: +; RV32I-NEXT: snez a0, a3 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: neg a0, a3 +; RV32I-NEXT: ret +; +; RV32ZBB-LABEL: expanded_neg_inv_abs64_unsigned: +; RV32ZBB: # %bb.0: +; RV32ZBB-NEXT: snez a2, a0 +; RV32ZBB-NEXT: neg a3, a1 +; RV32ZBB-NEXT: sub a2, a3, a2 +; RV32ZBB-NEXT: neg a3, a0 +; RV32ZBB-NEXT: beq a2, a1, .LBB13_2 +; RV32ZBB-NEXT: # %bb.1: +; RV32ZBB-NEXT: sltu a4, a2, a1 +; RV32ZBB-NEXT: beqz a4, .LBB13_3 +; RV32ZBB-NEXT: j .LBB13_4 +; RV32ZBB-NEXT: .LBB13_2: +; RV32ZBB-NEXT: sltu a4, a3, a0 +; RV32ZBB-NEXT: bnez a4, .LBB13_4 +; RV32ZBB-NEXT: .LBB13_3: +; RV32ZBB-NEXT: mv a2, a1 +; RV32ZBB-NEXT: mv a3, a0 +; RV32ZBB-NEXT: .LBB13_4: +; RV32ZBB-NEXT: snez a0, a3 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: neg a1, a0 +; RV32ZBB-NEXT: neg a0, a3 +; RV32ZBB-NEXT: ret +; +; RV64I-LABEL: expanded_neg_inv_abs64_unsigned: +; RV64I: # %bb.0: +; RV64I-NEXT: neg a1, a0 +; RV64I-NEXT: bltu a1, a0, .LBB13_2 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: mv a1, a0 +; RV64I-NEXT: .LBB13_2: +; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBB-LABEL: expanded_neg_inv_abs64_unsigned: +; RV64ZBB: # %bb.0: +; RV64ZBB-NEXT: neg a1, a0 +; RV64ZBB-NEXT: maxu a0, a0, a1 +; RV64ZBB-NEXT: ret + %n = sub i64 0, %x + %t = call i64 @llvm.umin.i64(i64 %n, i64 %x) + %r = sub i64 0, %t + ret i64 %r +} diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll index 1da76c1673d6..2272c17bcef0 100644 --- a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll +++ b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll @@ -109,6 +109,25 @@ define i64 @addmul6(i64 %a, i64 %b) { ret i64 %d } +define i64 @disjointormul6(i64 %a, i64 %b) { +; RV64I-LABEL: disjointormul6: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a2, a0, 1 +; RV64I-NEXT: slli a0, a0, 3 +; RV64I-NEXT: sub a0, a0, a2 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: disjointormul6: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 +; RV64XTHEADBA-NEXT: th.addsl a0, a1, a0, 1 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 6 + %d = or disjoint i64 %c, %b + ret i64 %d +} + define i64 @addmul10(i64 %a, i64 %b) { ; RV64I-LABEL: addmul10: ; RV64I: # %bb.0: @@ -423,8 +442,8 @@ define i64 @add255mul180(i64 %a) { ; RV64XTHEADBA: # %bb.0: ; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 ; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 -; RV64XTHEADBA-NEXT: li a1, 255 -; RV64XTHEADBA-NEXT: th.addsl a0, a1, a0, 2 +; RV64XTHEADBA-NEXT: slli a0, a0, 2 +; RV64XTHEADBA-NEXT: addi a0, a0, 255 ; RV64XTHEADBA-NEXT: ret %c = mul i64 %a, 180 %d = add i64 %c, 255 @@ -642,6 +661,39 @@ define i64 @mul288(i64 %a) { ret i64 %c } +define i64 @sh1add_imm(i64 %0) { +; CHECK-LABEL: sh1add_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 1 +; CHECK-NEXT: addi a0, a0, 5 +; CHECK-NEXT: ret + %a = shl i64 %0, 1 + %b = add i64 %a, 5 + ret i64 %b +} + +define i64 @sh2add_imm(i64 %0) { +; CHECK-LABEL: sh2add_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 2 +; CHECK-NEXT: addi a0, a0, -6 +; CHECK-NEXT: ret + %a = shl i64 %0, 2 + %b = add i64 %a, -6 + ret i64 %b +} + +define i64 @sh3add_imm(i64 %0) { +; CHECK-LABEL: sh3add_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 3 +; CHECK-NEXT: addi a0, a0, 7 +; CHECK-NEXT: ret + %a = shl i64 %0, 3 + %b = add i64 %a, 7 + ret i64 %b +} + define i64 @mul258(i64 %a) { ; RV64I-LABEL: mul258: ; RV64I: # %bb.0: @@ -983,12 +1035,18 @@ define i64 @add4104(i64 %a) { } define i64 @add4104_2(i64 %a) { -; CHECK-LABEL: add4104_2: -; CHECK: # %bb.0: -; CHECK-NEXT: lui a1, 1 -; CHECK-NEXT: addiw a1, a1, 8 -; CHECK-NEXT: or a0, a0, a1 -; CHECK-NEXT: ret +; RV64I-LABEL: add4104_2: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a1, 1 +; RV64I-NEXT: addiw a1, a1, 8 +; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: add4104_2: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: li a1, 1026 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 +; RV64XTHEADBA-NEXT: ret %c = or disjoint i64 %a, 4104 ret i64 %c } diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll index 10d24927d9b7..4d34621cd5f2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll @@ -1445,10 +1445,9 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale ; RV32-NEXT: addi a6, sp, 8 ; RV32-NEXT: sw a4, 8(sp) ; RV32-NEXT: sw zero, 12(sp) -; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v9, (a6), zero ; RV32-NEXT: lui a4, 61681 -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v10, v8, a3, v0.t ; RV32-NEXT: addi a5, a5, -256 ; RV32-NEXT: vand.vx v11, v8, a5, v0.t @@ -1595,9 +1594,7 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64_unmasked(<vscale x 1 x i64> %va ; RV32-NEXT: vand.vx v13, v8, a1 ; RV32-NEXT: vand.vx v12, v12, a1 ; RV32-NEXT: vor.vv v11, v12, v11 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v12, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v13, v13, a4 ; RV32-NEXT: vor.vv v10, v10, v13 ; RV32-NEXT: vsrl.vi v13, v8, 8 @@ -1730,10 +1727,9 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale ; RV32-NEXT: addi a6, sp, 8 ; RV32-NEXT: sw a4, 8(sp) ; RV32-NEXT: sw zero, 12(sp) -; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v10, (a6), zero ; RV32-NEXT: lui a4, 61681 -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v12, v8, a3, v0.t ; RV32-NEXT: addi a5, a5, -256 ; RV32-NEXT: vand.vx v14, v8, a5, v0.t @@ -1880,9 +1876,7 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64_unmasked(<vscale x 2 x i64> %va ; RV32-NEXT: vand.vx v18, v8, a1 ; RV32-NEXT: vand.vx v16, v16, a1 ; RV32-NEXT: vor.vv v10, v16, v10 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v16, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v18, v18, a4 ; RV32-NEXT: vor.vv v12, v12, v18 ; RV32-NEXT: vsrl.vi v18, v8, 8 @@ -2015,10 +2009,9 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale ; RV32-NEXT: addi a6, sp, 8 ; RV32-NEXT: sw a4, 8(sp) ; RV32-NEXT: sw zero, 12(sp) -; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v12, (a6), zero ; RV32-NEXT: lui a4, 61681 -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a3, v0.t ; RV32-NEXT: addi a5, a5, -256 ; RV32-NEXT: vand.vx v20, v8, a5, v0.t @@ -2165,9 +2158,7 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64_unmasked(<vscale x 4 x i64> %va ; RV32-NEXT: vand.vx v28, v8, a1 ; RV32-NEXT: vand.vx v24, v24, a1 ; RV32-NEXT: vor.vv v12, v24, v12 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v28, v28, a4 ; RV32-NEXT: vor.vv v16, v16, v28 ; RV32-NEXT: vsrl.vi v28, v8, 8 @@ -2315,7 +2306,6 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 3 @@ -2323,7 +2313,6 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vand.vx v24, v8, a3, v0.t ; RV32-NEXT: vsll.vi v24, v24, 24, v0.t ; RV32-NEXT: addi a5, sp, 16 @@ -2528,9 +2517,7 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64_unmasked(<vscale x 7 x i64> %va ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v0, v8, 8 @@ -2704,7 +2691,6 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 3 @@ -2712,7 +2698,6 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vand.vx v24, v8, a3, v0.t ; RV32-NEXT: vsll.vi v24, v24, 24, v0.t ; RV32-NEXT: addi a5, sp, 16 @@ -2917,9 +2902,7 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v0, v8, 8 diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll index 0dc1d0c32ac4..0c58cca0f947 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll @@ -523,11 +523,9 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v9, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v10, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v10, v8, a0, v0.t ; RV32-NEXT: vlse64.v v11, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v10, v10, a4, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vand.vx v10, v8, a5, v0.t @@ -538,7 +536,7 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t -; RV32-NEXT: vand.vx v12, v12, a1, v0.t +; RV32-NEXT: vand.vx v12, v12, a0, v0.t ; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t ; RV32-NEXT: vand.vx v12, v12, a5, v0.t @@ -609,15 +607,13 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsll.vx v10, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v11, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a4 -; RV32-NEXT: vand.vx v13, v8, a1 -; RV32-NEXT: vand.vx v12, v12, a1 +; RV32-NEXT: vand.vx v13, v8, a0 +; RV32-NEXT: vand.vx v12, v12, a0 ; RV32-NEXT: vor.vv v11, v12, v11 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v12, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v13, v13, a4 ; RV32-NEXT: vor.vv v10, v10, v13 ; RV32-NEXT: vsrl.vi v13, v8, 8 @@ -695,11 +691,9 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v10, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v12, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m2, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v12, v8, a0, v0.t ; RV32-NEXT: vlse64.v v14, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v12, v12, a4, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t ; RV32-NEXT: vand.vx v12, v8, a5, v0.t @@ -710,7 +704,7 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 ; RV32-NEXT: vor.vv v10, v10, v12, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t -; RV32-NEXT: vand.vx v16, v16, a1, v0.t +; RV32-NEXT: vand.vx v16, v16, a0, v0.t ; RV32-NEXT: vor.vv v12, v16, v12, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t ; RV32-NEXT: vand.vx v16, v16, a5, v0.t @@ -781,15 +775,13 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsll.vx v12, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v14, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a4 -; RV32-NEXT: vand.vx v18, v8, a1 -; RV32-NEXT: vand.vx v16, v16, a1 +; RV32-NEXT: vand.vx v18, v8, a0 +; RV32-NEXT: vand.vx v16, v16, a0 ; RV32-NEXT: vor.vv v14, v16, v14 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v16, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v18, v18, a4 ; RV32-NEXT: vor.vv v12, v12, v18 ; RV32-NEXT: vsrl.vi v18, v8, 8 @@ -867,11 +859,9 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v20, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m4, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v20, v8, a0, v0.t ; RV32-NEXT: vlse64.v v12, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v20, v20, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v20, v0.t ; RV32-NEXT: vand.vx v20, v8, a5, v0.t @@ -882,7 +872,7 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 ; RV32-NEXT: vor.vv v16, v16, v20, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t -; RV32-NEXT: vand.vx v24, v24, a1, v0.t +; RV32-NEXT: vand.vx v24, v24, a0, v0.t ; RV32-NEXT: vor.vv v20, v24, v20, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t ; RV32-NEXT: vand.vx v24, v24, a5, v0.t @@ -953,15 +943,13 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsll.vx v16, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v20, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a4 -; RV32-NEXT: vand.vx v28, v8, a1 -; RV32-NEXT: vand.vx v24, v24, a1 +; RV32-NEXT: vand.vx v28, v8, a0 +; RV32-NEXT: vand.vx v24, v24, a0 ; RV32-NEXT: vor.vv v20, v24, v20 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v28, v28, a4 ; RV32-NEXT: vor.vv v16, v16, v28 ; RV32-NEXT: vsrl.vi v28, v8, 8 @@ -1043,51 +1031,49 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v24, v8, a0, v0.t ; RV32-NEXT: vsll.vx v24, v24, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 4 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, 4080 +; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: vsll.vi v24, v24, 24, v0.t +; RV32-NEXT: addi a3, sp, 16 +; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill +; RV32-NEXT: vand.vv v24, v8, v16, v0.t +; RV32-NEXT: vsll.vi v16, v24, 8, v0.t +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 -; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb -; RV32-NEXT: slli a3, a3, 3 +; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; RV32-NEXT: vand.vx v24, v8, a3, v0.t -; RV32-NEXT: vsll.vi v24, v24, 24, v0.t -; RV32-NEXT: addi a0, sp, 16 -; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill -; RV32-NEXT: vand.vv v24, v8, v16, v0.t -; RV32-NEXT: vsll.vi v16, v24, 8, v0.t -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t -; RV32-NEXT: vand.vx v24, v24, a1, v0.t +; RV32-NEXT: vand.vx v24, v24, a0, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t -; RV32-NEXT: vand.vx v24, v24, a3, v0.t +; RV32-NEXT: vand.vx v24, v24, a1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 @@ -1193,24 +1179,22 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v24, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v0, v8, a4 -; RV32-NEXT: vand.vx v0, v0, a1 +; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vor.vv v16, v0, v16 -; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: slli a2, a2, 3 -; RV32-NEXT: add a2, sp, a2 -; RV32-NEXT: addi a2, a2, 16 -; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill -; RV32-NEXT: vand.vx v0, v8, a1 +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vand.vx v0, v8, a0 ; RV32-NEXT: vsll.vx v0, v0, a4 ; RV32-NEXT: vor.vv v16, v24, v0 -; RV32-NEXT: addi a1, sp, 16 -; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: addi a0, sp, 16 +; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vlse64.v v0, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v24, v8, 8 @@ -1221,7 +1205,6 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 ; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v24, v24, 8 ; RV32-NEXT: vor.vv v8, v8, v24 -; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: csrr a0, vlenb @@ -1318,51 +1301,49 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v24, v8, a0, v0.t ; RV32-NEXT: vsll.vx v24, v24, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 4 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, 4080 +; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: vsll.vi v24, v24, 24, v0.t +; RV32-NEXT: addi a3, sp, 16 +; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill +; RV32-NEXT: vand.vv v24, v8, v16, v0.t +; RV32-NEXT: vsll.vi v16, v24, 8, v0.t +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 -; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb -; RV32-NEXT: slli a3, a3, 3 +; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; RV32-NEXT: vand.vx v24, v8, a3, v0.t -; RV32-NEXT: vsll.vi v24, v24, 24, v0.t -; RV32-NEXT: addi a0, sp, 16 -; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill -; RV32-NEXT: vand.vv v24, v8, v16, v0.t -; RV32-NEXT: vsll.vi v16, v24, 8, v0.t -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t -; RV32-NEXT: vand.vx v24, v24, a1, v0.t +; RV32-NEXT: vand.vx v24, v24, a0, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t -; RV32-NEXT: vand.vx v24, v24, a3, v0.t +; RV32-NEXT: vand.vx v24, v24, a1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 @@ -1468,24 +1449,22 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v24, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v0, v8, a4 -; RV32-NEXT: vand.vx v0, v0, a1 +; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vor.vv v16, v0, v16 -; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: slli a2, a2, 3 -; RV32-NEXT: add a2, sp, a2 -; RV32-NEXT: addi a2, a2, 16 -; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill -; RV32-NEXT: vand.vx v0, v8, a1 +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vand.vx v0, v8, a0 ; RV32-NEXT: vsll.vx v0, v0, a4 ; RV32-NEXT: vor.vv v16, v24, v0 -; RV32-NEXT: addi a1, sp, 16 -; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: addi a0, sp, 16 +; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vlse64.v v0, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v24, v8, 8 @@ -1496,7 +1475,6 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 ; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v24, v24, 8 ; RV32-NEXT: vor.vv v8, v8, v24 -; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: csrr a0, vlenb @@ -1716,11 +1694,9 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v9, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v10, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v10, v8, a0, v0.t ; RV32-NEXT: vlse64.v v11, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v10, v10, a4, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vand.vx v10, v8, a5, v0.t @@ -1731,7 +1707,7 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1 ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t -; RV32-NEXT: vand.vx v12, v12, a1, v0.t +; RV32-NEXT: vand.vx v12, v12, a0, v0.t ; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t ; RV32-NEXT: vand.vx v12, v12, a5, v0.t diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-neg-abs.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-neg-abs.ll new file mode 100644 index 000000000000..6f1efb6885de --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-neg-abs.ll @@ -0,0 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s + +define <2 x i64> @expanded_fixed_neg_abs64(<2 x i64> %x) { +; CHECK-LABEL: expanded_fixed_neg_abs64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: ret + %t = sub <2 x i64> <i64 0, i64 0>, %x + %t1 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %t, <2 x i64> %x) + %t2 = sub <2 x i64> <i64 0, i64 0>, %t1 + ret <2 x i64> %t2 +} + +define <2 x i64> @expanded_fixed_neg_abs64_unsigned(<2 x i64> %x) { +; CHECK-LABEL: expanded_fixed_neg_abs64_unsigned: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: ret + %t = sub <2 x i64> <i64 0, i64 0>, %x + %t1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %t, <2 x i64> %x) + %t2 = sub <2 x i64> <i64 0, i64 0>, %t1 + ret <2 x i64> %t2 +} + +define <2 x i64> @expanded_fixed_neg_inv_abs64(<2 x i64> %x) { +; CHECK-LABEL: expanded_fixed_neg_inv_abs64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: ret + %t = sub <2 x i64> <i64 0, i64 0>, %x + %t1 = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %t, <2 x i64> %x) + %t2 = sub <2 x i64> <i64 0, i64 0>, %t1 + ret <2 x i64> %t2 +} + +define <2 x i64> @expanded_fixed_neg_inv_abs64_unsigned(<2 x i64> %x) { +; CHECK-LABEL: expanded_fixed_neg_inv_abs64_unsigned: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; CHECK-NEXT: vrsub.vi v9, v8, 0 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: ret + %t = sub <2 x i64> <i64 0, i64 0>, %x + %t1 = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %t, <2 x i64> %x) + %t2 = sub <2 x i64> <i64 0, i64 0>, %t1 + ret <2 x i64> %t2 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll index 15793eaada07..66952cac8e00 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll @@ -1254,12 +1254,10 @@ define void @copysign_neg_trunc_v4f16_v4f32(ptr %x, ptr %y) { define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) { ; ZVFH-LABEL: copysign_neg_trunc_v3f16_v3f32: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vsetivli zero, 3, e32, m1, ta, ma +; ZVFH-NEXT: vsetivli zero, 3, e16, mf2, ta, ma ; ZVFH-NEXT: vle32.v v8, (a1) ; ZVFH-NEXT: vle16.v v9, (a0) -; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFH-NEXT: vfncvt.f.f.w v10, v8 -; ZVFH-NEXT: vsetivli zero, 3, e16, mf2, ta, ma ; ZVFH-NEXT: vfsgnjn.vv v8, v9, v10 ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -1272,9 +1270,7 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) { ; ZVFHMIN-NEXT: lui a1, 8 ; ZVFHMIN-NEXT: addi a2, a1, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a2 -; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vxor.vx v9, v10, a1 ; ZVFHMIN-NEXT: vand.vx v9, v9, a1 ; ZVFHMIN-NEXT: vor.vv v8, v8, v9 @@ -4013,9 +4009,10 @@ define void @trunc_v6f16(ptr %x) { ; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -4197,10 +4194,11 @@ define void @ceil_v6f16(ptr %x) { ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 ; ZVFH-NEXT: fsrmi a1, 3 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a1 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -4388,10 +4386,11 @@ define void @floor_v6f16(ptr %x) { ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 ; ZVFH-NEXT: fsrmi a1, 2 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a1 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -4579,10 +4578,11 @@ define void @round_v6f16(ptr %x) { ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 ; ZVFH-NEXT: fsrmi a1, 4 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a1 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll index 59c7feb53ce9..80e462c93769 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll @@ -1142,9 +1142,7 @@ define void @mulhu_v6i16(ptr %x) { ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a1, %hi(.LCPI67_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI67_0) -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v9, (a1) -; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll index 4f0f5dd78c94..bf8baafc4a25 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll @@ -530,7 +530,7 @@ define i32 @reduce_and_16xi32_prefix5(ptr %p) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 5, e32, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; CHECK-NEXT: vredand.vs v8, v8, v10 @@ -725,7 +725,7 @@ define i32 @reduce_umin_16xi32_prefix5(ptr %p) { ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; RV32-NEXT: vle32.v v8, (a0) -; RV32-NEXT: vsetivli zero, 5, e32, m1, ta, ma +; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32-NEXT: vmv.v.i v10, -1 ; RV32-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; RV32-NEXT: vredminu.vs v8, v8, v10 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll index 4e06d0094d94..bb05eb5368ae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll @@ -168,11 +168,12 @@ define <4 x i64> @m2_splat_into_slide_two_source_v2_lo(<4 x i64> %v1, <4 x i64> define <4 x i64> @m2_splat_into_slide_two_source(<4 x i64> %v1, <4 x i64> %v2) vscale_range(2,2) { ; CHECK-LABEL: m2_splat_into_slide_two_source: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-NEXT: vslidedown.vi v13, v10, 1 -; CHECK-NEXT: vslideup.vi v13, v11, 1 +; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma +; CHECK-NEXT: vmv.v.i v0, 12 +; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vrgather.vi v12, v8, 0 -; CHECK-NEXT: vmv2r.v v8, v12 +; CHECK-NEXT: vslideup.vi v12, v10, 1, v0.t +; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret %res = shufflevector <4 x i64> %v1, <4 x i64> %v2, <4 x i32> <i32 0, i32 0, i32 5, i32 6> ret <4 x i64> %res @@ -182,17 +183,18 @@ define void @shuffle1(ptr %explicit_0, ptr %explicit_1) vscale_range(2,2) { ; CHECK-LABEL: shuffle1: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, a0, 252 -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-NEXT: vid.v v10 +; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma -; CHECK-NEXT: vle32.v v11, (a0) -; CHECK-NEXT: vmv.v.i v0, 5 -; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vsrl.vi v10, v10, 1 -; CHECK-NEXT: vadd.vi v10, v10, 1 -; CHECK-NEXT: vrgather.vv v9, v11, v10, v0.t +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: li a0, 175 +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vsrl.vi v8, v8, 1 +; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: vadd.vi v8, v8, 1 +; CHECK-NEXT: vrgather.vv v11, v9, v8 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: addi a0, a1, 672 ; CHECK-NEXT: vs2r.v v8, (a0) ; CHECK-NEXT: ret @@ -209,15 +211,15 @@ define void @shuffle1(ptr %explicit_0, ptr %explicit_1) vscale_range(2,2) { define <16 x float> @shuffle2(<4 x float> %a) vscale_range(2,2) { ; CHECK-LABEL: shuffle2: ; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: li a0, -97 +; CHECK-NEXT: vadd.vv v9, v9, v9 +; CHECK-NEXT: vrsub.vi v9, v9, 4 +; CHECK-NEXT: vmv.s.x v0, a0 +; CHECK-NEXT: vrgather.vv v13, v8, v9 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma -; CHECK-NEXT: vmv1r.v v12, v8 -; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu -; CHECK-NEXT: vid.v v13 -; CHECK-NEXT: vadd.vv v13, v13, v13 -; CHECK-NEXT: vmv.v.i v0, 6 -; CHECK-NEXT: vrsub.vi v13, v13, 4 -; CHECK-NEXT: vrgather.vv v9, v12, v13, v0.t +; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: ret %b = extractelement <4 x float> %a, i32 2 %c = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %b, i32 5 @@ -229,15 +231,16 @@ define <16 x float> @shuffle2(<4 x float> %a) vscale_range(2,2) { define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vscale_range(2,2) { ; RV32-LABEL: extract_any_extend_vector_inreg_v16i64: ; RV32: # %bb.0: -; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma +; RV32-NEXT: li a1, 16 +; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV32-NEXT: vmv.v.i v16, 0 -; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV32-NEXT: vmv.v.i v0, 1 +; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: li a1, 32 -; RV32-NEXT: vrgather.vi v18, v15, 1, v0.t -; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma +; RV32-NEXT: vrgather.vi v16, v8, 15, v0.t +; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV32-NEXT: vslidedown.vx v8, v16, a0 ; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret @@ -255,14 +258,13 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vsca ; RV64-NEXT: addi s0, sp, 256 ; RV64-NEXT: .cfi_def_cfa s0, 0 ; RV64-NEXT: andi sp, sp, -128 -; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; RV64-NEXT: vmv.v.i v0, 1 +; RV64-NEXT: li a1, -17 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma -; RV64-NEXT: vmv.v.i v16, 0 -; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; RV64-NEXT: vrgather.vi v18, v15, 1, v0.t +; RV64-NEXT: vmv.s.x v0, a1 +; RV64-NEXT: vrgather.vi v16, v8, 15 +; RV64-NEXT: vmerge.vim v8, v16, 0, v0 ; RV64-NEXT: mv s2, sp -; RV64-NEXT: vs8r.v v16, (s2) +; RV64-NEXT: vs8r.v v8, (s2) ; RV64-NEXT: andi a0, a0, 15 ; RV64-NEXT: li a1, 8 ; RV64-NEXT: call __muldi3 @@ -288,16 +290,21 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vsca define <4 x double> @shuffles_add(<4 x double> %0, <4 x double> %1) vscale_range(2,2) { ; CHECK-LABEL: shuffles_add: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu -; CHECK-NEXT: vmv1r.v v13, v10 -; CHECK-NEXT: vslideup.vi v13, v11, 1 -; CHECK-NEXT: vmv1r.v v8, v9 -; CHECK-NEXT: vmv.v.i v0, 1 -; CHECK-NEXT: vrgather.vi v12, v9, 0 -; CHECK-NEXT: vmv1r.v v9, v11 -; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-NEXT: vfadd.vv v8, v12, v8 +; CHECK-NEXT: vrgather.vi v12, v8, 2 +; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; CHECK-NEXT: vid.v v14 +; CHECK-NEXT: vmv.v.i v0, 12 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; CHECK-NEXT: vrgather.vi v16, v8, 3 +; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; CHECK-NEXT: vadd.vv v8, v14, v14 +; CHECK-NEXT: vadd.vi v9, v8, -4 +; CHECK-NEXT: vadd.vi v8, v8, -3 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu +; CHECK-NEXT: vrgatherei16.vv v12, v10, v9, v0.t +; CHECK-NEXT: vrgatherei16.vv v16, v10, v8, v0.t +; CHECK-NEXT: vfadd.vv v8, v12, v16 ; CHECK-NEXT: ret %3 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 2, i32 4, i32 6> %4 = shufflevector <4 x double> %0, <4 x double> %1, <4 x i32> <i32 undef, i32 3, i32 5, i32 7> @@ -305,3 +312,91 @@ define <4 x double> @shuffles_add(<4 x double> %0, <4 x double> %1) vscale_range ret <4 x double> %5 } +define <16 x i32> @m4_square_num_of_shuffles_in_chunks(<16 x i32> %0) vscale_range(2,2) { +; CHECK-LABEL: m4_square_num_of_shuffles_in_chunks: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui a0, %hi(.LCPI17_0) +; CHECK-NEXT: addi a0, a0, %lo(.LCPI17_0) +; CHECK-NEXT: vl1r.v v12, (a0) +; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; CHECK-NEXT: vsext.vf2 v16, v12 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 +; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %1 = shufflevector <16 x i32> %0, <16 x i32> poison, <16 x i32> <i32 0, i32 5, i32 8, i32 12, i32 1, i32 4, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15> + ret <16 x i32> %1 +} + +define <16 x i32> @m4_linear_num_of_shuffles_in_chunks(<16 x i32> %0) vscale_range(2,2) { +; CHECK-LABEL: m4_linear_num_of_shuffles_in_chunks: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui a0, %hi(.LCPI18_0) +; CHECK-NEXT: addi a0, a0, %lo(.LCPI18_0) +; CHECK-NEXT: vl2re16.v v16, (a0) +; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 +; CHECK-NEXT: vmv.v.v v8, v12 +; CHECK-NEXT: ret +entry: + %1 = shufflevector <16 x i32> %0, <16 x i32> poison, <16 x i32> <i32 poison, i32 poison, i32 8, i32 12, i32 poison, i32 poison, i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 11, i32 poison> + ret <16 x i32> %1 +} + +define i64 @multi_chunks_shuffle(<32 x i32> %0) vscale_range(8,8) { +; RV32-LABEL: multi_chunks_shuffle: +; RV32: # %bb.0: # %entry +; RV32-NEXT: vsetivli zero, 16, e32, m1, ta, ma +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: li a0, 32 +; RV32-NEXT: li a1, 63 +; RV32-NEXT: vwsubu.vx v12, v10, a0 +; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; RV32-NEXT: vmv.v.x v10, a0 +; RV32-NEXT: lui a0, 61681 +; RV32-NEXT: addi a0, a0, -241 +; RV32-NEXT: vand.vx v12, v12, a1 +; RV32-NEXT: vand.vx v10, v10, a1 +; RV32-NEXT: vsrl.vv v12, v8, v12 +; RV32-NEXT: vsll.vv v8, v8, v10 +; RV32-NEXT: vmv.s.x v0, a0 +; RV32-NEXT: vor.vv v8, v8, v12 +; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: vmerge.vvm v8, v10, v8, v0 +; RV32-NEXT: vrgather.vi v10, v8, 2 +; RV32-NEXT: vor.vv v8, v8, v10 +; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32-NEXT: vslidedown.vi v8, v8, 1 +; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: srai a1, a0, 31 +; RV32-NEXT: ret +; +; RV64-LABEL: multi_chunks_shuffle: +; RV64: # %bb.0: # %entry +; RV64-NEXT: li a0, 32 +; RV64-NEXT: vsetivli zero, 16, e64, m2, ta, ma +; RV64-NEXT: vsrl.vx v10, v8, a0 +; RV64-NEXT: vsll.vx v8, v8, a0 +; RV64-NEXT: lui a0, 61681 +; RV64-NEXT: addi a0, a0, -241 +; RV64-NEXT: vor.vv v8, v8, v10 +; RV64-NEXT: vmv.s.x v0, a0 +; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; RV64-NEXT: vmv.v.i v10, 0 +; RV64-NEXT: vmerge.vvm v8, v10, v8, v0 +; RV64-NEXT: vrgather.vi v10, v8, 2 +; RV64-NEXT: vor.vv v8, v8, v10 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64-NEXT: vslidedown.vi v8, v8, 1 +; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: ret +entry: + %1 = shufflevector <32 x i32> %0, <32 x i32> zeroinitializer, <32 x i32> <i32 1, i32 0, i32 3, i32 2, i32 37, i32 36, i32 39, i32 38, i32 9, i32 8, i32 11, i32 10, i32 45, i32 44, i32 47, i32 46, i32 17, i32 16, i32 19, i32 18, i32 53, i32 52, i32 55, i32 54, i32 25, i32 24, i32 27, i32 26, i32 61, i32 60, i32 63, i32 62> + %2 = shufflevector <32 x i32> zeroinitializer, <32 x i32> %1, <32 x i32> <i32 3, i32 34, i32 33, i32 0, i32 7, i32 38, i32 37, i32 4, i32 11, i32 42, i32 41, i32 8, i32 15, i32 46, i32 45, i32 12, i32 19, i32 50, i32 49, i32 16, i32 23, i32 54, i32 53, i32 20, i32 27, i32 58, i32 57, i32 24, i32 31, i32 62, i32 61, i32 28> + %3 = or <32 x i32> %1, %2 + %4 = extractelement <32 x i32> %3, i64 1 + %conv199 = sext i32 %4 to i64 + ret i64 %conv199 +} diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll index 5d407caf7151..05254e60b65b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll @@ -473,6 +473,7 @@ define <32 x i64> @select_evl_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c) ; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-NEXT: vle64.v v16, (a1) ; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll index 7649d60def11..33fe73a097e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll @@ -582,14 +582,14 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -616,13 +616,13 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -652,14 +652,14 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -686,13 +686,13 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -722,15 +722,15 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v16, v12, v14, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t @@ -758,13 +758,13 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 ; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0 @@ -796,15 +796,15 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v12, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v24, v16, v20, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 ; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t @@ -832,13 +832,13 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0 @@ -876,15 +876,15 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill @@ -927,10 +927,10 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24 ; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v24, v0 @@ -995,64 +995,62 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: csrr a4, vlenb -; ZVFHMIN-NEXT: slli a4, a4, 5 +; ZVFHMIN-NEXT: li a5, 24 +; ZVFHMIN-NEXT: mul a4, a4, a5 ; ZVFHMIN-NEXT: add a4, sp, a4 ; ZVFHMIN-NEXT: addi a4, a4, 16 ; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v0, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb ; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: li a3, 25 +; ZVFHMIN-NEXT: mul a2, a2, a3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vl8r.v v0, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v8, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 @@ -1070,35 +1068,43 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v24, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv8r.v v8, v16 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vmv1r.v v0, v24 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb ; ZVFHMIN-NEXT: li a1, 24 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t +; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload @@ -1110,7 +1116,7 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: li a1, 25 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 @@ -1152,68 +1158,61 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vmv8r.v v0, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v8, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v0, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t +; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 4 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v13, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v13 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload @@ -1221,7 +1220,8 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill @@ -1229,43 +1229,49 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vmv1r.v v0, v7 ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16 ; ZVFHMIN-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll index 8e448fcda9c5..c65712e9965a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll @@ -582,14 +582,14 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -616,13 +616,13 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -652,14 +652,14 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -686,13 +686,13 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -722,15 +722,15 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v16, v12, v14, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t @@ -758,13 +758,13 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 ; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0 @@ -796,15 +796,15 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v12, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v24, v16, v20, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 ; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t @@ -832,13 +832,13 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0 @@ -876,15 +876,15 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill @@ -927,10 +927,10 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24 ; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v24, v0 @@ -995,64 +995,62 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: csrr a4, vlenb -; ZVFHMIN-NEXT: slli a4, a4, 5 +; ZVFHMIN-NEXT: li a5, 24 +; ZVFHMIN-NEXT: mul a4, a4, a5 ; ZVFHMIN-NEXT: add a4, sp, a4 ; ZVFHMIN-NEXT: addi a4, a4, 16 ; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v0, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb ; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: li a3, 25 +; ZVFHMIN-NEXT: mul a2, a2, a3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vl8r.v v0, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v8, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 @@ -1070,35 +1068,43 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v24, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv8r.v v8, v16 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vmv1r.v v0, v24 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb ; ZVFHMIN-NEXT: li a1, 24 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t +; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload @@ -1110,7 +1116,7 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: li a1, 25 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 @@ -1152,68 +1158,61 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vmv8r.v v0, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v8, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v0, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t +; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 4 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v13, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v13 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload @@ -1221,7 +1220,8 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill @@ -1229,43 +1229,49 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vmv1r.v v0, v7 ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16 ; ZVFHMIN-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll index 2fda344690bf..6787c8c24c87 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll @@ -18,7 +18,7 @@ entry: define i64 @reduce_add2(<4 x i64> %v) { ; CHECK-LABEL: reduce_add2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vmv.v.i v10, 8 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vredsum.vs v8, v8, v10 diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll index 70b53841bff4..06f48762e24c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll @@ -1658,10 +1658,10 @@ define <vscale x 1 x i1> @fcmp_oeq_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oeq", <vscale x 1 x i1> %m, i32 %evl) @@ -1678,11 +1678,11 @@ define <vscale x 1 x i1> @fcmp_oeq_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1701,11 +1701,11 @@ define <vscale x 1 x i1> @fcmp_oeq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1723,10 +1723,10 @@ define <vscale x 1 x i1> @fcmp_ogt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ogt", <vscale x 1 x i1> %m, i32 %evl) @@ -1743,11 +1743,11 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1766,11 +1766,11 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1788,10 +1788,10 @@ define <vscale x 1 x i1> @fcmp_oge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oge_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oge", <vscale x 1 x i1> %m, i32 %evl) @@ -1808,11 +1808,11 @@ define <vscale x 1 x i1> @fcmp_oge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1831,11 +1831,11 @@ define <vscale x 1 x i1> @fcmp_oge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1853,10 +1853,10 @@ define <vscale x 1 x i1> @fcmp_olt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_olt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"olt", <vscale x 1 x i1> %m, i32 %evl) @@ -1873,11 +1873,11 @@ define <vscale x 1 x i1> @fcmp_olt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1896,11 +1896,11 @@ define <vscale x 1 x i1> @fcmp_olt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1918,10 +1918,10 @@ define <vscale x 1 x i1> @fcmp_ole_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ole_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ole", <vscale x 1 x i1> %m, i32 %evl) @@ -1938,11 +1938,11 @@ define <vscale x 1 x i1> @fcmp_ole_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1961,11 +1961,11 @@ define <vscale x 1 x i1> @fcmp_ole_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1985,10 +1985,10 @@ define <vscale x 1 x i1> @fcmp_one_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_one_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2009,11 +2009,11 @@ define <vscale x 1 x i1> @fcmp_one_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_one_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2036,11 +2036,11 @@ define <vscale x 1 x i1> @fcmp_one_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v9, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2062,10 +2062,10 @@ define <vscale x 1 x i1> @fcmp_ord_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ord_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v9, v8 @@ -2088,14 +2088,14 @@ define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v9, v8 ; ZVFHMIN-NEXT: ret @@ -2119,14 +2119,14 @@ define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret @@ -2147,10 +2147,10 @@ define <vscale x 1 x i1> @fcmp_ueq_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -2171,11 +2171,11 @@ define <vscale x 1 x i1> @fcmp_ueq_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -2198,11 +2198,11 @@ define <vscale x 1 x i1> @fcmp_ueq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v9, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -2223,10 +2223,10 @@ define <vscale x 1 x i1> @fcmp_ugt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2245,11 +2245,11 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2270,11 +2270,11 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2294,10 +2294,10 @@ define <vscale x 1 x i1> @fcmp_uge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uge_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2316,11 +2316,11 @@ define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2341,11 +2341,11 @@ define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2365,10 +2365,10 @@ define <vscale x 1 x i1> @fcmp_ult_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ult_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2387,11 +2387,11 @@ define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2412,11 +2412,11 @@ define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2436,10 +2436,10 @@ define <vscale x 1 x i1> @fcmp_ule_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ule_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2458,11 +2458,11 @@ define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2483,11 +2483,11 @@ define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2506,10 +2506,10 @@ define <vscale x 1 x i1> @fcmp_une_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_une_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"une", <vscale x 1 x i1> %m, i32 %evl) @@ -2526,11 +2526,11 @@ define <vscale x 1 x i1> @fcmp_une_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_une_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -2549,11 +2549,11 @@ define <vscale x 1 x i1> @fcmp_une_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -2573,10 +2573,10 @@ define <vscale x 1 x i1> @fcmp_uno_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uno_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2599,14 +2599,14 @@ define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 ; ZVFHMIN-NEXT: ret @@ -2630,14 +2630,14 @@ define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret @@ -2658,10 +2658,10 @@ define <vscale x 3 x i1> @fcmp_oeq_vv_nxv3f16(<vscale x 3 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv3f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2681,10 +2681,10 @@ define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2703,11 +2703,11 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2728,11 +2728,11 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2752,10 +2752,10 @@ define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2774,11 +2774,11 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2799,11 +2799,11 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2823,10 +2823,10 @@ define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oge_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2845,11 +2845,11 @@ define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2870,11 +2870,11 @@ define <vscale x 8 x i1> @fcmp_oge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2894,10 +2894,10 @@ define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_olt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2916,11 +2916,11 @@ define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2941,11 +2941,11 @@ define <vscale x 8 x i1> @fcmp_olt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2965,10 +2965,10 @@ define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ole_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2987,11 +2987,11 @@ define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3012,11 +3012,11 @@ define <vscale x 8 x i1> @fcmp_ole_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3037,10 +3037,10 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_one_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -3061,11 +3061,11 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -3088,11 +3088,11 @@ define <vscale x 8 x i1> @fcmp_one_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -3114,13 +3114,13 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ord_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3142,14 +3142,14 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v10, v8 ; ZVFHMIN-NEXT: ret @@ -3173,14 +3173,14 @@ define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3201,10 +3201,10 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -3225,11 +3225,11 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -3252,11 +3252,11 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -3277,10 +3277,10 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3299,11 +3299,11 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3324,11 +3324,11 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3348,10 +3348,10 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uge_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3370,11 +3370,11 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3395,11 +3395,11 @@ define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3419,10 +3419,10 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ult_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3441,11 +3441,11 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3466,11 +3466,11 @@ define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3490,10 +3490,10 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ule_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3512,11 +3512,11 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3537,11 +3537,11 @@ define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3561,10 +3561,10 @@ define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_une_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3583,11 +3583,11 @@ define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3608,11 +3608,11 @@ define <vscale x 8 x i1> @fcmp_une_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3633,13 +3633,13 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uno_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3661,14 +3661,14 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v10, v8 ; ZVFHMIN-NEXT: ret @@ -3692,14 +3692,14 @@ define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3829,14 +3829,14 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a7, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vmv8r.v v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli t0, a0, 4 -; ZVFHMIN-NEXT: add a0, t0, a0 +; ZVFHMIN-NEXT: slli a7, a0, 4 +; ZVFHMIN-NEXT: add a0, a7, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill @@ -3844,7 +3844,7 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: vmv1r.v v0, v24 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a7, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v6, v16, v8, v0.t ; ZVFHMIN-NEXT: bltu a6, a4, .LBB171_2 ; ZVFHMIN-NEXT: # %bb.1: @@ -3857,16 +3857,16 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a6, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a7, a0, 4 -; ZVFHMIN-NEXT: add a0, a7, a0 +; ZVFHMIN-NEXT: slli a6, a0, 4 +; ZVFHMIN-NEXT: add a0, a6, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 -; ZVFHMIN-NEXT: vsetvli zero, a6, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v5, v24, v8, v0.t ; ZVFHMIN-NEXT: add a0, a3, a3 ; ZVFHMIN-NEXT: bltu a2, a5, .LBB171_4 @@ -3881,6 +3881,9 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: vl1r.v v7, (a6) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli a6, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a3 +; ZVFHMIN-NEXT: sltu a6, a2, a5 +; ZVFHMIN-NEXT: addi a6, a6, -1 +; ZVFHMIN-NEXT: and a5, a6, a5 ; ZVFHMIN-NEXT: csrr a6, vlenb ; ZVFHMIN-NEXT: mv a7, a6 ; ZVFHMIN-NEXT: slli a6, a6, 3 @@ -3890,31 +3893,28 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: add a6, sp, a6 ; ZVFHMIN-NEXT: addi a6, a6, 16 ; ZVFHMIN-NEXT: vl8r.v v16, (a6) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a6, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a5, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: csrr a6, vlenb -; ZVFHMIN-NEXT: slli a7, a6, 4 -; ZVFHMIN-NEXT: add a6, a7, a6 -; ZVFHMIN-NEXT: add a6, sp, a6 -; ZVFHMIN-NEXT: addi a6, a6, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: csrr a6, vlenb -; ZVFHMIN-NEXT: slli a7, a6, 5 -; ZVFHMIN-NEXT: add a6, a7, a6 -; ZVFHMIN-NEXT: add a6, sp, a6 -; ZVFHMIN-NEXT: addi a6, a6, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a6) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a5, vlenb +; ZVFHMIN-NEXT: slli a6, a5, 4 +; ZVFHMIN-NEXT: add a5, a6, a5 +; ZVFHMIN-NEXT: add a5, sp, a5 +; ZVFHMIN-NEXT: addi a5, a5, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: csrr a5, vlenb +; ZVFHMIN-NEXT: slli a6, a5, 5 +; ZVFHMIN-NEXT: add a5, a6, a5 +; ZVFHMIN-NEXT: add a5, sp, a5 +; ZVFHMIN-NEXT: addi a5, a5, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 -; ZVFHMIN-NEXT: sltu a6, a2, a5 -; ZVFHMIN-NEXT: addi a6, a6, -1 -; ZVFHMIN-NEXT: and a5, a6, a5 -; ZVFHMIN-NEXT: csrr a6, vlenb -; ZVFHMIN-NEXT: slli a7, a6, 4 -; ZVFHMIN-NEXT: add a6, a7, a6 -; ZVFHMIN-NEXT: add a6, sp, a6 -; ZVFHMIN-NEXT: addi a6, a6, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a6) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a5, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a5, vlenb +; ZVFHMIN-NEXT: slli a6, a5, 4 +; ZVFHMIN-NEXT: add a5, a6, a5 +; ZVFHMIN-NEXT: add a5, sp, a5 +; ZVFHMIN-NEXT: addi a5, a5, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v4, v24, v8, v0.t ; ZVFHMIN-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslideup.vx v5, v6, a3 @@ -3923,16 +3923,16 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: mv a2, a4 ; ZVFHMIN-NEXT: .LBB171_6: ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 -; ZVFHMIN-NEXT: csrr a4, vlenb -; ZVFHMIN-NEXT: slli a5, a4, 5 -; ZVFHMIN-NEXT: add a4, a5, a4 -; ZVFHMIN-NEXT: add a4, sp, a4 -; ZVFHMIN-NEXT: addi a4, a4, 16 -; ZVFHMIN-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a4, a2, 5 +; ZVFHMIN-NEXT: add a2, a4, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslideup.vx v8, v4, a3 diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll index 61cc754e21df..9c733b17dc6e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll @@ -2367,9 +2367,8 @@ define <vscale x 1 x i1> @icmp_eq_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2394,9 +2393,8 @@ define <vscale x 1 x i1> @icmp_eq_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmseq.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2451,9 +2449,8 @@ define <vscale x 1 x i1> @icmp_ne_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsne.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2478,9 +2475,8 @@ define <vscale x 1 x i1> @icmp_ne_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsne.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2535,9 +2531,8 @@ define <vscale x 1 x i1> @icmp_ugt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2562,9 +2557,8 @@ define <vscale x 1 x i1> @icmp_ugt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2619,9 +2613,8 @@ define <vscale x 1 x i1> @icmp_uge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2647,9 +2640,8 @@ define <vscale x 1 x i1> @icmp_uge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2704,9 +2696,8 @@ define <vscale x 1 x i1> @icmp_ult_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2731,9 +2722,8 @@ define <vscale x 1 x i1> @icmp_ult_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2788,9 +2778,8 @@ define <vscale x 1 x i1> @icmp_sgt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2815,9 +2804,8 @@ define <vscale x 1 x i1> @icmp_sgt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2872,9 +2860,8 @@ define <vscale x 1 x i1> @icmp_sge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2900,9 +2887,8 @@ define <vscale x 1 x i1> @icmp_sge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2957,9 +2943,8 @@ define <vscale x 1 x i1> @icmp_slt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2984,9 +2969,8 @@ define <vscale x 1 x i1> @icmp_slt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -3041,9 +3025,8 @@ define <vscale x 1 x i1> @icmp_sle_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -3068,9 +3051,8 @@ define <vscale x 1 x i1> @icmp_sle_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -3129,9 +3111,8 @@ define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmseq.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3158,9 +3139,8 @@ define <vscale x 8 x i1> @icmp_eq_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmseq.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3220,9 +3200,8 @@ define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsne.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3249,9 +3228,8 @@ define <vscale x 8 x i1> @icmp_ne_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsne.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3311,9 +3289,8 @@ define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3340,9 +3317,8 @@ define <vscale x 8 x i1> @icmp_ugt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3402,9 +3378,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsleu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3432,9 +3407,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsleu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3494,9 +3468,8 @@ define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3523,9 +3496,8 @@ define <vscale x 8 x i1> @icmp_ult_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3585,9 +3557,8 @@ define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3614,9 +3585,8 @@ define <vscale x 8 x i1> @icmp_sgt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3676,9 +3646,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3706,9 +3675,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3768,9 +3736,8 @@ define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3797,9 +3764,8 @@ define <vscale x 8 x i1> @icmp_slt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3859,9 +3825,8 @@ define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3888,9 +3853,8 @@ define <vscale x 8 x i1> @icmp_sle_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll index fee6799e992f..77f3cf3ca498 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll @@ -1487,9 +1487,8 @@ define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1514,9 +1513,8 @@ define <vscale x 1 x i64> @vadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1583,9 +1581,8 @@ define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1610,9 +1607,8 @@ define <vscale x 2 x i64> @vadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1679,9 +1675,8 @@ define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1706,9 +1701,8 @@ define <vscale x 4 x i64> @vadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1775,9 +1769,8 @@ define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1802,9 +1795,8 @@ define <vscale x 8 x i64> @vadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll index b0c5a72f6f9e..4866bb06f19e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll @@ -1314,9 +1314,8 @@ define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1341,9 +1340,8 @@ define <vscale x 1 x i64> @vand_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1410,9 +1408,8 @@ define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1437,9 +1434,8 @@ define <vscale x 2 x i64> @vand_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1506,9 +1502,8 @@ define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1533,9 +1528,8 @@ define <vscale x 4 x i64> @vand_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1602,9 +1596,8 @@ define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1629,9 +1622,8 @@ define <vscale x 8 x i64> @vand_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll index 32992301bd39..763b2908b102 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll @@ -1115,9 +1115,8 @@ define <vscale x 1 x i64> @vandn_vx_vp_nxv1i64(i64 %a, <vscale x 1 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1139,9 +1138,8 @@ define <vscale x 1 x i64> @vandn_vx_vp_nxv1i64(i64 %a, <vscale x 1 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 @@ -1208,9 +1206,8 @@ define <vscale x 2 x i64> @vandn_vx_vp_nxv2i64(i64 %a, <vscale x 2 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v10, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1232,9 +1229,8 @@ define <vscale x 2 x i64> @vandn_vx_vp_nxv2i64(i64 %a, <vscale x 2 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v10, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 @@ -1301,9 +1297,8 @@ define <vscale x 4 x i64> @vandn_vx_vp_nxv4i64(i64 %a, <vscale x 4 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v12, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1325,9 +1320,8 @@ define <vscale x 4 x i64> @vandn_vx_vp_nxv4i64(i64 %a, <vscale x 4 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v12, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 @@ -1394,9 +1388,8 @@ define <vscale x 8 x i64> @vandn_vx_vp_nxv8i64(i64 %a, <vscale x 8 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v16, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1418,9 +1411,8 @@ define <vscale x 8 x i64> @vandn_vx_vp_nxv8i64(i64 %a, <vscale x 8 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v16, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll index 2814be2792de..03e4e1f445be 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll @@ -893,9 +893,8 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -920,9 +919,8 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -969,9 +967,8 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -996,9 +993,8 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1045,9 +1041,8 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1072,9 +1067,8 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1121,9 +1115,8 @@ define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1148,9 +1141,8 @@ define <vscale x 8 x i64> @vdiv_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll index 3e913d4f682e..2f35f91d77a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll @@ -892,9 +892,8 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -919,9 +918,8 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -968,9 +966,8 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -995,9 +992,8 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1044,9 +1040,8 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1071,9 +1066,8 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1120,9 +1114,8 @@ define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1147,9 +1140,8 @@ define <vscale x 8 x i64> @vdivu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll index 87bc9f27d6dc..31359c3f68ec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -679,10 +679,10 @@ define <vscale x 1 x half> @vfadd_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -700,10 +700,10 @@ define <vscale x 1 x half> @vfadd_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -722,11 +722,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -747,11 +747,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16_commute(<vscale x 1 x half> %va, ha ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -772,11 +772,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -797,11 +797,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16_unmasked_commute(<vscale x 1 x half ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_unmasked_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v8, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -823,10 +823,10 @@ define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -844,10 +844,10 @@ define <vscale x 2 x half> @vfadd_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -866,11 +866,11 @@ define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -891,11 +891,11 @@ define <vscale x 2 x half> @vfadd_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -917,10 +917,10 @@ define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -938,10 +938,10 @@ define <vscale x 4 x half> @vfadd_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -960,11 +960,11 @@ define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -985,11 +985,11 @@ define <vscale x 4 x half> @vfadd_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -1011,10 +1011,10 @@ define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1032,10 +1032,10 @@ define <vscale x 8 x half> @vfadd_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1054,11 +1054,11 @@ define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1079,11 +1079,11 @@ define <vscale x 8 x half> @vfadd_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1105,10 +1105,10 @@ define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfadd_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1126,10 +1126,10 @@ define <vscale x 16 x half> @vfadd_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfadd_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1148,11 +1148,11 @@ define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1173,11 +1173,11 @@ define <vscale x 16 x half> @vfadd_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1205,23 +1205,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1231,10 +1230,11 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB48_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1266,22 +1266,21 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1291,9 +1290,10 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB49_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1324,14 +1324,10 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -1352,15 +1348,18 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1370,20 +1369,21 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB50_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1416,16 +1416,10 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -1436,18 +1430,22 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1457,14 +1455,15 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB51_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll index 061af454aa8b..2205769d3494 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -641,10 +641,10 @@ define <vscale x 1 x half> @vfdiv_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -662,10 +662,10 @@ define <vscale x 1 x half> @vfdiv_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -684,11 +684,11 @@ define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -709,11 +709,11 @@ define <vscale x 1 x half> @vfdiv_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -735,10 +735,10 @@ define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -756,10 +756,10 @@ define <vscale x 2 x half> @vfdiv_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -778,11 +778,11 @@ define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -803,11 +803,11 @@ define <vscale x 2 x half> @vfdiv_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -829,10 +829,10 @@ define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -850,10 +850,10 @@ define <vscale x 4 x half> @vfdiv_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -872,11 +872,11 @@ define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -897,11 +897,11 @@ define <vscale x 4 x half> @vfdiv_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -923,10 +923,10 @@ define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -944,10 +944,10 @@ define <vscale x 8 x half> @vfdiv_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -966,11 +966,11 @@ define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -991,11 +991,11 @@ define <vscale x 8 x half> @vfdiv_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1017,10 +1017,10 @@ define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1038,10 +1038,10 @@ define <vscale x 16 x half> @vfdiv_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1060,11 +1060,11 @@ define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1085,11 +1085,11 @@ define <vscale x 16 x half> @vfdiv_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1117,23 +1117,22 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1143,10 +1142,11 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB44_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1178,22 +1178,21 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1203,9 +1202,10 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB45_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1236,14 +1236,10 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -1264,15 +1260,18 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1282,20 +1281,21 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB46_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1328,16 +1328,10 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -1348,18 +1342,22 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1369,14 +1367,15 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB47_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll index 02d6229e9924..5d998c4e739d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll @@ -290,10 +290,10 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -311,10 +311,10 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -334,10 +334,10 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -355,10 +355,10 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -378,10 +378,10 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -399,10 +399,10 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -422,10 +422,10 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -443,10 +443,10 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -466,10 +466,10 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfmax_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -487,10 +487,10 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfmax_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -516,23 +516,22 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -542,10 +541,11 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB22_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -577,22 +577,21 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -602,9 +601,10 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB23_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll index f7f80299785d..48a4c1386900 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll @@ -290,10 +290,10 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -311,10 +311,10 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -334,10 +334,10 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -355,10 +355,10 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -378,10 +378,10 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -399,10 +399,10 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -422,10 +422,10 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -443,10 +443,10 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -466,10 +466,10 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfmin_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -487,10 +487,10 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfmin_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -516,23 +516,22 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -542,10 +541,11 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB22_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -577,22 +577,21 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -602,9 +601,10 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB23_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll index 7e5523044a01..06f74dd99574 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -19,10 +19,10 @@ define <vscale x 1 x half> @vfmul_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -40,10 +40,10 @@ define <vscale x 1 x half> @vfmul_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -62,11 +62,11 @@ define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -87,11 +87,11 @@ define <vscale x 1 x half> @vfmul_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -113,10 +113,10 @@ define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -134,10 +134,10 @@ define <vscale x 2 x half> @vfmul_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -156,11 +156,11 @@ define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -181,11 +181,11 @@ define <vscale x 2 x half> @vfmul_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -207,10 +207,10 @@ define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -228,10 +228,10 @@ define <vscale x 4 x half> @vfmul_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -250,11 +250,11 @@ define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -275,11 +275,11 @@ define <vscale x 4 x half> @vfmul_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -301,10 +301,10 @@ define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -322,10 +322,10 @@ define <vscale x 8 x half> @vfmul_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -344,11 +344,11 @@ define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -369,11 +369,11 @@ define <vscale x 8 x half> @vfmul_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -395,10 +395,10 @@ define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfmul_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -416,10 +416,10 @@ define <vscale x 16 x half> @vfmul_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfmul_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -438,11 +438,11 @@ define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -463,11 +463,11 @@ define <vscale x 16 x half> @vfmul_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -495,23 +495,22 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -521,10 +520,11 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB20_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -556,22 +556,21 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -581,9 +580,10 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB21_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -614,14 +614,10 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -642,15 +638,18 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -660,20 +659,21 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB22_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -706,16 +706,10 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -726,18 +720,22 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -747,14 +745,15 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB23_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll index b7f2133144e7..575d50d11f0a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll @@ -42,9 +42,9 @@ define <vscale x 2 x i1> @vfptosi_nxv2i1_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptosi_nxv2i1_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t ; ZVFHMIN-NEXT: ret @@ -62,9 +62,9 @@ define <vscale x 2 x i1> @vfptosi_nxv2i1_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptosi_nxv2i1_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll index d990c74c67d5..e33ab98c0f85 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll @@ -130,9 +130,8 @@ define <vscale x 2 x i7> @vfptosi_v4i7_v4f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfptosi_v4i7_v4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -153,9 +152,8 @@ define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptosi_nxv2i8_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -174,9 +172,8 @@ define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptosi_nxv2i8_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0 @@ -196,9 +193,8 @@ define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptosi_nxv2i16_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -214,9 +210,8 @@ define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptosi_nxv2i16_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -235,9 +230,9 @@ define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptosi_nxv2i32_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -254,9 +249,9 @@ define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptosi_nxv2i32_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -276,9 +271,9 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptosi_nxv2i64_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.rtz.x.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -286,21 +281,13 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc } define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) { -; ZVFH-LABEL: vfptosi_nxv2i64_nxv2f16_unmasked: -; ZVFH: # %bb.0: -; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFH-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFH-NEXT: vfwcvt.rtz.x.f.v v8, v10 -; ZVFH-NEXT: ret -; -; ZVFHMIN-LABEL: vfptosi_nxv2i64_nxv2f16_unmasked: -; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.rtz.x.f.v v8, v10 -; ZVFHMIN-NEXT: ret +; CHECK-LABEL: vfptosi_nxv2i64_nxv2f16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10 +; CHECK-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) ret <vscale x 2 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll index 8ac5992bd5eb..e1d0ad475858 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll @@ -42,9 +42,9 @@ define <vscale x 2 x i1> @vfptoui_nxv2i1_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptoui_nxv2i1_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t ; ZVFHMIN-NEXT: ret @@ -62,9 +62,9 @@ define <vscale x 2 x i1> @vfptoui_nxv2i1_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptoui_nxv2i1_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll index 3b24a648d97f..86222ecfadfe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll @@ -130,9 +130,8 @@ define <vscale x 2 x i7> @vfptoui_v4i7_v4f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfptoui_v4i7_v4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -153,9 +152,8 @@ define <vscale x 2 x i8> @vfptoui_nxv2i8_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptoui_nxv2i8_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -174,9 +172,8 @@ define <vscale x 2 x i8> @vfptoui_nxv2i8_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptoui_nxv2i8_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0 @@ -196,9 +193,8 @@ define <vscale x 2 x i16> @vfptoui_nxv2i16_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptoui_nxv2i16_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptoui.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -214,9 +210,8 @@ define <vscale x 2 x i16> @vfptoui_nxv2i16_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptoui_nxv2i16_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptoui.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -235,9 +230,9 @@ define <vscale x 2 x i32> @vfptoui_nxv2i32_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptoui_nxv2i32_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptoui.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -254,9 +249,9 @@ define <vscale x 2 x i32> @vfptoui_nxv2i32_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptoui_nxv2i32_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptoui.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -276,9 +271,9 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptoui_nxv2i64_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptoui.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -286,21 +281,13 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc } define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) { -; ZVFH-LABEL: vfptoui_nxv2i64_nxv2f16_unmasked: -; ZVFH: # %bb.0: -; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFH-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFH-NEXT: vfwcvt.rtz.xu.f.v v8, v10 -; ZVFH-NEXT: ret -; -; ZVFHMIN-LABEL: vfptoui_nxv2i64_nxv2f16_unmasked: -; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v10 -; ZVFHMIN-NEXT: ret +; CHECK-LABEL: vfptoui_nxv2i64_nxv2f16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10 +; CHECK-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptoui.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) ret <vscale x 2 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll index 8e57be1e0697..e94d0a60bbfc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll @@ -242,9 +242,9 @@ define <vscale x 1 x half> @vfsqrt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -262,9 +262,9 @@ define <vscale x 1 x half> @vfsqrt_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -284,9 +284,9 @@ define <vscale x 2 x half> @vfsqrt_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -304,9 +304,9 @@ define <vscale x 2 x half> @vfsqrt_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -326,9 +326,9 @@ define <vscale x 4 x half> @vfsqrt_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v10, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -346,9 +346,9 @@ define <vscale x 4 x half> @vfsqrt_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v10, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -368,9 +368,9 @@ define <vscale x 8 x half> @vfsqrt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v12, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -388,9 +388,9 @@ define <vscale x 8 x half> @vfsqrt_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v12, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -410,9 +410,9 @@ define <vscale x 16 x half> @vfsqrt_vv_nxv16f16(<vscale x 16 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -430,9 +430,9 @@ define <vscale x 16 x half> @vfsqrt_vv_nxv16f16_unmasked(<vscale x 16 x half> %v ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -458,13 +458,13 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16(<vscale x 32 x half> %va, <vscal ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 +; ZVFHMIN-NEXT: sltu a4, a0, a3 +; ZVFHMIN-NEXT: addi a4, a4, -1 +; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 -; ZVFHMIN-NEXT: sltu a2, a0, a3 -; ZVFHMIN-NEXT: addi a2, a2, -1 -; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v24, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24 @@ -472,9 +472,10 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16(<vscale x 32 x half> %va, <vscal ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v16 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -498,14 +499,14 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16_unmasked(<vscale x 32 x half> %v ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 +; ZVFHMIN-NEXT: sltu a4, a0, a3 +; ZVFHMIN-NEXT: addi a4, a4, -1 +; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 -; ZVFHMIN-NEXT: sltu a2, a0, a3 -; ZVFHMIN-NEXT: addi a2, a2, -1 -; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -513,8 +514,9 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16_unmasked(<vscale x 32 x half> %v ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll index d034f65479a1..56ed560f9ec9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -641,10 +641,10 @@ define <vscale x 1 x half> @vfsub_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -662,10 +662,10 @@ define <vscale x 1 x half> @vfsub_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -684,11 +684,11 @@ define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -709,11 +709,11 @@ define <vscale x 1 x half> @vfsub_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -735,10 +735,10 @@ define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -756,10 +756,10 @@ define <vscale x 2 x half> @vfsub_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -778,11 +778,11 @@ define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -803,11 +803,11 @@ define <vscale x 2 x half> @vfsub_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -829,10 +829,10 @@ define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -850,10 +850,10 @@ define <vscale x 4 x half> @vfsub_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -872,11 +872,11 @@ define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -897,11 +897,11 @@ define <vscale x 4 x half> @vfsub_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -923,10 +923,10 @@ define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -944,10 +944,10 @@ define <vscale x 8 x half> @vfsub_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -966,11 +966,11 @@ define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -991,11 +991,11 @@ define <vscale x 8 x half> @vfsub_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1017,10 +1017,10 @@ define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfsub_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1038,10 +1038,10 @@ define <vscale x 16 x half> @vfsub_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfsub_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1060,11 +1060,11 @@ define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1085,11 +1085,11 @@ define <vscale x 16 x half> @vfsub_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1117,23 +1117,22 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1143,10 +1142,11 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB44_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1178,22 +1178,21 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1203,9 +1202,10 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB45_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1236,14 +1236,10 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -1264,15 +1260,18 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1282,20 +1281,21 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB46_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1328,16 +1328,10 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -1348,18 +1342,22 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1369,14 +1367,15 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB47_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll index 6cd3884f029f..a1d548e1878b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll @@ -143,9 +143,8 @@ define <vscale x 1 x float> @vfmacc_vf_nxv1f32(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -170,9 +169,8 @@ define <vscale x 1 x float> @vfmacc_vf_nxv1f32_commute(<vscale x 1 x half> %va, ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -198,9 +196,8 @@ define <vscale x 1 x float> @vfmacc_vf_nxv1f32_unmasked(<vscale x 1 x half> %va, ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -225,9 +222,8 @@ define <vscale x 1 x float> @vfmacc_vf_nxv1f32_tu(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_tu: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, tu, mu @@ -254,9 +250,8 @@ define <vscale x 1 x float> @vfmacc_vf_nxv1f32_commute_tu(<vscale x 1 x half> %v ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_commute_tu: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, tu, mu @@ -283,9 +278,8 @@ define <vscale x 1 x float> @vfmacc_vf_nxv1f32_unmasked_tu(<vscale x 1 x half> % ; ZVFHMIN-LABEL: vfmacc_vf_nxv1f32_unmasked_tu: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, tu, ma @@ -362,9 +356,8 @@ define <vscale x 2 x float> @vfmacc_vf_nxv2f32(<vscale x 2 x half> %va, half %b, ; ZVFHMIN-LABEL: vfmacc_vf_nxv2f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -389,9 +382,8 @@ define <vscale x 2 x float> @vfmacc_vf_nxv2f32_unmasked(<vscale x 2 x half> %va, ; ZVFHMIN-LABEL: vfmacc_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -468,9 +460,8 @@ define <vscale x 4 x float> @vfmacc_vf_nxv4f32(<vscale x 4 x half> %va, half %b, ; ZVFHMIN-LABEL: vfmacc_vf_nxv4f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -495,9 +486,8 @@ define <vscale x 4 x float> @vfmacc_vf_nxv4f32_unmasked(<vscale x 4 x half> %va, ; ZVFHMIN-LABEL: vfmacc_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -574,9 +564,8 @@ define <vscale x 8 x float> @vfmacc_vf_nxv8f32(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: vfmacc_vf_nxv8f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -601,9 +590,8 @@ define <vscale x 8 x float> @vfmacc_vf_nxv8f32_unmasked(<vscale x 8 x half> %va, ; ZVFHMIN-LABEL: vfmacc_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -696,9 +684,8 @@ define <vscale x 16 x float> @vfmacc_vf_nxv16f32(<vscale x 16 x half> %va, half ; ZVFHMIN-LABEL: vfmacc_vf_nxv16f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -723,9 +710,8 @@ define <vscale x 16 x float> @vfmacc_vf_nxv16f32_unmasked(<vscale x 16 x half> % ; ZVFHMIN-LABEL: vfmacc_vf_nxv16f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll index c92a79e49c16..94b80075ac14 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll @@ -120,9 +120,8 @@ define <vscale x 1 x float> @vmfsac_vf_nxv1f32(<vscale x 1 x half> %a, half %b, ; ZVFHMIN-LABEL: vmfsac_vf_nxv1f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -148,9 +147,8 @@ define <vscale x 1 x float> @vmfsac_vf_nxv1f32_commute(<vscale x 1 x half> %a, h ; ZVFHMIN-LABEL: vmfsac_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -177,9 +175,8 @@ define <vscale x 1 x float> @vmfsac_vf_nxv1f32_unmasked(<vscale x 1 x half> %a, ; ZVFHMIN-LABEL: vmfsac_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -255,9 +252,8 @@ define <vscale x 2 x float> @vmfsac_vf_nxv2f32(<vscale x 2 x half> %a, half %b, ; ZVFHMIN-LABEL: vmfsac_vf_nxv2f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -283,9 +279,8 @@ define <vscale x 2 x float> @vmfsac_vf_nxv2f32_commute(<vscale x 2 x half> %a, h ; ZVFHMIN-LABEL: vmfsac_vf_nxv2f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -312,9 +307,8 @@ define <vscale x 2 x float> @vmfsac_vf_nxv2f32_unmasked(<vscale x 2 x half> %a, ; ZVFHMIN-LABEL: vmfsac_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -392,9 +386,8 @@ define <vscale x 4 x float> @vmfsac_vf_nxv4f32(<vscale x 4 x half> %a, half %b, ; ZVFHMIN-LABEL: vmfsac_vf_nxv4f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -420,9 +413,8 @@ define <vscale x 4 x float> @vmfsac_vf_nxv4f32_commute(<vscale x 4 x half> %a, h ; ZVFHMIN-LABEL: vmfsac_vf_nxv4f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -449,9 +441,8 @@ define <vscale x 4 x float> @vmfsac_vf_nxv4f32_unmasked(<vscale x 4 x half> %a, ; ZVFHMIN-LABEL: vmfsac_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -529,9 +520,8 @@ define <vscale x 8 x float> @vmfsac_vf_nxv8f32(<vscale x 8 x half> %a, half %b, ; ZVFHMIN-LABEL: vmfsac_vf_nxv8f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -557,9 +547,8 @@ define <vscale x 8 x float> @vmfsac_vf_nxv8f32_commute(<vscale x 8 x half> %a, h ; ZVFHMIN-LABEL: vmfsac_vf_nxv8f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -586,9 +575,8 @@ define <vscale x 8 x float> @vmfsac_vf_nxv8f32_unmasked(<vscale x 8 x half> %a, ; ZVFHMIN-LABEL: vmfsac_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll index 0a0bc6696a9f..ea457069bcdf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll @@ -71,9 +71,8 @@ define <vscale x 1 x float> @vfnmacc_vf_nxv1f32(<vscale x 1 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv1f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -101,9 +100,8 @@ define <vscale x 1 x float> @vfnmacc_vf_nxv1f32_commute(<vscale x 1 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -131,9 +129,8 @@ define <vscale x 1 x float> @vfnmacc_vf_nxv1f32_unmasked(<vscale x 1 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -212,9 +209,8 @@ define <vscale x 2 x float> @vfnmacc_vf_nxv2f32(<vscale x 2 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv2f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -242,9 +238,8 @@ define <vscale x 2 x float> @vfnmacc_vf_nxv2f32_commute(<vscale x 2 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv2f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -272,9 +267,8 @@ define <vscale x 2 x float> @vfnmacc_vf_nxv2f32_unmasked(<vscale x 2 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -355,9 +349,8 @@ define <vscale x 4 x float> @vfnmacc_vf_nxv4f32(<vscale x 4 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv4f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -385,9 +378,8 @@ define <vscale x 4 x float> @vfnmacc_vf_nxv4f32_commute(<vscale x 4 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv4f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -415,9 +407,8 @@ define <vscale x 4 x float> @vfnmacc_vf_nxv4f32_unmasked(<vscale x 4 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -498,9 +489,8 @@ define <vscale x 8 x float> @vfnmacc_vf_nxv8f32(<vscale x 8 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv8f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -528,9 +518,8 @@ define <vscale x 8 x float> @vfnmacc_vf_nxv8f32_commute(<vscale x 8 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv8f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -558,9 +547,8 @@ define <vscale x 8 x float> @vfnmacc_vf_nxv8f32_unmasked(<vscale x 8 x half> %a, ; ZVFHMIN-LABEL: vfnmacc_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -657,9 +645,8 @@ define <vscale x 16 x float> @vfnmacc_vf_nxv16f32(<vscale x 16 x half> %a, half ; ZVFHMIN-LABEL: vfnmacc_vf_nxv16f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -687,9 +674,8 @@ define <vscale x 16 x float> @vfnmacc_vf_nxv16f32_commute(<vscale x 16 x half> % ; ZVFHMIN-LABEL: vfnmacc_vf_nxv16f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -717,9 +703,8 @@ define <vscale x 16 x float> @vfnmacc_vf_nxv16f32_unmasked(<vscale x 16 x half> ; ZVFHMIN-LABEL: vfnmacc_vf_nxv16f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll index b5f7ef338086..4956da531c8c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll @@ -69,9 +69,8 @@ define <vscale x 1 x float> @vfnmsac_vf_nxv1f32(<vscale x 1 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv1f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -97,9 +96,8 @@ define <vscale x 1 x float> @vfnmsac_vf_nxv1f32_commute(<vscale x 1 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv1f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -126,9 +124,8 @@ define <vscale x 1 x float> @vfnmsac_vf_nxv1f32_unmasked(<vscale x 1 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv1f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma @@ -204,9 +201,8 @@ define <vscale x 2 x float> @vfnmsac_vf_nxv2f32(<vscale x 2 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv2f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -232,9 +228,8 @@ define <vscale x 2 x float> @vfnmsac_vf_nxv2f32_commute(<vscale x 2 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv2f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v11, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -261,9 +256,8 @@ define <vscale x 2 x float> @vfnmsac_vf_nxv2f32_unmasked(<vscale x 2 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv2f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma @@ -341,9 +335,8 @@ define <vscale x 4 x float> @vfnmsac_vf_nxv4f32(<vscale x 4 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv4f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -369,9 +362,8 @@ define <vscale x 4 x float> @vfnmsac_vf_nxv4f32_commute(<vscale x 4 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv4f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -398,9 +390,8 @@ define <vscale x 4 x float> @vfnmsac_vf_nxv4f32_unmasked(<vscale x 4 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv4f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma @@ -478,9 +469,8 @@ define <vscale x 8 x float> @vfnmsac_vf_nxv8f32(<vscale x 8 x half> %a, half %b, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv8f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -506,9 +496,8 @@ define <vscale x 8 x float> @vfnmsac_vf_nxv8f32_commute(<vscale x 8 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv8f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -535,9 +524,8 @@ define <vscale x 8 x float> @vfnmsac_vf_nxv8f32_unmasked(<vscale x 8 x half> %a, ; ZVFHMIN-LABEL: vfnmsac_vf_nxv8f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma @@ -631,9 +619,8 @@ define <vscale x 16 x float> @vfnmsac_vf_nxv16f32(<vscale x 16 x half> %a, half ; ZVFHMIN-LABEL: vfnmsac_vf_nxv16f32: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -659,9 +646,8 @@ define <vscale x 16 x float> @vfnmsac_vf_nxv16f32_commute(<vscale x 16 x half> % ; ZVFHMIN-LABEL: vfnmsac_vf_nxv16f32_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v4, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma @@ -688,9 +674,8 @@ define <vscale x 16 x float> @vfnmsac_vf_nxv16f32_unmasked(<vscale x 16 x half> ; ZVFHMIN-LABEL: vfnmsac_vf_nxv16f32_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv.v.x v24, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir index b304769b2773..c4a383454610 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir @@ -513,6 +513,36 @@ body: | %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 ... --- +name: vfnop_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vfnop_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 +... +--- +name: vfnop_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vfnop_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 4 /* e16 */, 0 +... +--- +name: vfnop_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vfnop_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 +... +--- name: vseN_v body: | bb.0: @@ -543,6 +573,86 @@ body: | PseudoVSE8_V_MF2 %x, $noreg, 1, 3 /* e8 */ ... --- +name: vsm_v +body: | + bb.0: + ; CHECK-LABEL: name: vsm_v + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B8 %x, $noreg, 1, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + PseudoVSM_V_B8 %x, $noreg, 1, 0 +... +--- +name: vsm_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vsm_v_incompatible_emul + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B16 %x, $noreg, 1, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + PseudoVSM_V_B16 %x, $noreg, 1, 0 +... +--- +name: vleN_v +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vleN_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v_incompatible_eew + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 +... +--- +name: vleN_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v_incompatible_emul + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %x:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vlm_v +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, 1, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */ + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 +... +--- +name: vlm_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v_incompatible_eew + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 +... +--- +name: vlm_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v_incompatible_emul + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */ + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 +... +--- name: vsseN_v body: | bb.0: @@ -675,6 +785,56 @@ body: | %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 ... --- +name: vluxeiN_v_idx_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 +... +--- +name: vluxeiN_v_idx_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 +... +--- +name: vluxeiN_v_vd +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_vd + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vluxeiN_v_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_vd_incompatible_eew + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 +... +--- +name: vluxeiN_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_vd_incompatible_emul + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- name: vmop_mm body: | bb.0: @@ -1064,3 +1224,116 @@ body: | %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0 ... +name: vred_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vred_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 +... +--- +name: vred_vs1_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 +... +--- +name: vred_vs1_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 4 /* e16 */, 0 +... +--- +name: vred_vs1_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 +... +--- +name: vred_other_user_is_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_other_user_is_vl0 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 +... +--- +name: vred_both_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_both_vl0 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 +... +--- +name: vred_vl0_and_vlreg +body: | + bb.0: + ; CHECK-LABEL: name: vred_vl0_and_vlreg + ; CHECK: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 +... +--- +name: vred_vlreg_and_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vlreg_and_vl0 + ; CHECK: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 /* tu, mu */ + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 +... +--- +name: vred_other_user_is_vl2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_other_user_is_vl2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 +... diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir index 3f966b036589..0a366f4fd89c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir @@ -110,4 +110,24 @@ body: | %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1, 3 /* e8 */, 0 ... +--- +name: vfcvt_x_f_v_nofpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfcvt_x_f_v_nofpexcept + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vfcvt_x_f_v_fpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfcvt_x_f_v_fpexcept + ; CHECK: %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... diff --git a/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir b/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir new file mode 100644 index 000000000000..e8f7957de47c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir @@ -0,0 +1,13 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s + +--- +name: vleN_v_volatile +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ :: (volatile load (<vscale x 1 x s64>)) + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 :: (volatile load (<vscale x 1 x s64>)) + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll index 333117c8dce2..c334e70f1f35 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll @@ -1654,9 +1654,9 @@ define <vscale x 1 x i64> @vmacc_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vmacc.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1685,9 +1685,9 @@ define <vscale x 1 x i64> @vmacc_vx_nxv1i64_unmasked(<vscale x 1 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; RV32-NEXT: vmacc.vv v9, v8, v10 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1729,9 +1729,8 @@ define <vscale x 1 x i64> @vmacc_vx_nxv1i64_ta(<vscale x 1 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmacc.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv.v.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1791,9 +1790,9 @@ define <vscale x 2 x i64> @vmacc_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; RV32-NEXT: vmacc.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1822,9 +1821,9 @@ define <vscale x 2 x i64> @vmacc_vx_nxv2i64_unmasked(<vscale x 2 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, ma ; RV32-NEXT: vmacc.vv v10, v8, v12 ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1866,9 +1865,8 @@ define <vscale x 2 x i64> @vmacc_vx_nxv2i64_ta(<vscale x 2 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmacc.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1928,9 +1926,9 @@ define <vscale x 4 x i64> @vmacc_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; RV32-NEXT: vmacc.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -1959,9 +1957,9 @@ define <vscale x 4 x i64> @vmacc_vx_nxv4i64_unmasked(<vscale x 4 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, ma ; RV32-NEXT: vmacc.vv v12, v8, v16 ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2003,9 +2001,8 @@ define <vscale x 4 x i64> @vmacc_vx_nxv4i64_ta(<vscale x 4 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmacc.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2067,9 +2064,9 @@ define <vscale x 8 x i64> @vmacc_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu ; RV32-NEXT: vmacc.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2098,9 +2095,9 @@ define <vscale x 8 x i64> @vmacc_vx_nxv8i64_unmasked(<vscale x 8 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, ma ; RV32-NEXT: vmacc.vv v16, v8, v24 ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2143,9 +2140,8 @@ define <vscale x 8 x i64> @vmacc_vx_nxv8i64_ta(<vscale x 8 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmacc.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll index 7818e99c5562..3df0763fdc75 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll @@ -1124,9 +1124,8 @@ define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1151,9 +1150,8 @@ define <vscale x 1 x i64> @vmax_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1200,9 +1198,8 @@ define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1227,9 +1224,8 @@ define <vscale x 2 x i64> @vmax_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1276,9 +1272,8 @@ define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1303,9 +1298,8 @@ define <vscale x 4 x i64> @vmax_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1352,9 +1346,8 @@ define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1379,9 +1372,8 @@ define <vscale x 8 x i64> @vmax_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll index 674b0b806000..8147d467be04 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll @@ -1123,9 +1123,8 @@ define <vscale x 1 x i64> @vmaxu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1150,9 +1149,8 @@ define <vscale x 1 x i64> @vmaxu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1199,9 +1197,8 @@ define <vscale x 2 x i64> @vmaxu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1226,9 +1223,8 @@ define <vscale x 2 x i64> @vmaxu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1275,9 +1271,8 @@ define <vscale x 4 x i64> @vmaxu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1302,9 +1297,8 @@ define <vscale x 4 x i64> @vmaxu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1351,9 +1345,8 @@ define <vscale x 8 x i64> @vmaxu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1378,9 +1371,8 @@ define <vscale x 8 x i64> @vmaxu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll index 79631cd80594..614bd4cbde9e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll @@ -1124,9 +1124,8 @@ define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1151,9 +1150,8 @@ define <vscale x 1 x i64> @vmin_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1200,9 +1198,8 @@ define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1227,9 +1224,8 @@ define <vscale x 2 x i64> @vmin_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1276,9 +1272,8 @@ define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1303,9 +1298,8 @@ define <vscale x 4 x i64> @vmin_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1352,9 +1346,8 @@ define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1379,9 +1372,8 @@ define <vscale x 8 x i64> @vmin_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll index bc93b62fab7f..21160553af59 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll @@ -1123,9 +1123,8 @@ define <vscale x 1 x i64> @vminu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1150,9 +1149,8 @@ define <vscale x 1 x i64> @vminu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1199,9 +1197,8 @@ define <vscale x 2 x i64> @vminu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1226,9 +1223,8 @@ define <vscale x 2 x i64> @vminu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1275,9 +1271,8 @@ define <vscale x 4 x i64> @vminu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1302,9 +1297,8 @@ define <vscale x 4 x i64> @vminu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1351,9 +1345,8 @@ define <vscale x 8 x i64> @vminu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1378,9 +1371,8 @@ define <vscale x 8 x i64> @vminu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll index b63098b64e29..f0907e41cd43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll @@ -934,9 +934,8 @@ define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -961,9 +960,8 @@ define <vscale x 1 x i64> @vmul_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1010,9 +1008,8 @@ define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1037,9 +1034,8 @@ define <vscale x 2 x i64> @vmul_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1086,9 +1082,8 @@ define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1113,9 +1108,8 @@ define <vscale x 4 x i64> @vmul_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1162,9 +1156,8 @@ define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1189,9 +1182,8 @@ define <vscale x 8 x i64> @vmul_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll index 2e0daa66c82a..3484d288088a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll @@ -1654,9 +1654,9 @@ define <vscale x 1 x i64> @vnmsac_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vnmsac.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1685,9 +1685,9 @@ define <vscale x 1 x i64> @vnmsac_vx_nxv1i64_unmasked(<vscale x 1 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; RV32-NEXT: vnmsac.vv v9, v8, v10 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1729,9 +1729,8 @@ define <vscale x 1 x i64> @vnmsac_vx_nxv1i64_ta(<vscale x 1 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vnmsac.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv.v.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1791,9 +1790,9 @@ define <vscale x 2 x i64> @vnmsac_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; RV32-NEXT: vnmsac.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1822,9 +1821,9 @@ define <vscale x 2 x i64> @vnmsac_vx_nxv2i64_unmasked(<vscale x 2 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, ma ; RV32-NEXT: vnmsac.vv v10, v8, v12 ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1866,9 +1865,8 @@ define <vscale x 2 x i64> @vnmsac_vx_nxv2i64_ta(<vscale x 2 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vnmsac.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1928,9 +1926,9 @@ define <vscale x 4 x i64> @vnmsac_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; RV32-NEXT: vnmsac.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -1959,9 +1957,9 @@ define <vscale x 4 x i64> @vnmsac_vx_nxv4i64_unmasked(<vscale x 4 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, ma ; RV32-NEXT: vnmsac.vv v12, v8, v16 ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2003,9 +2001,8 @@ define <vscale x 4 x i64> @vnmsac_vx_nxv4i64_ta(<vscale x 4 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vnmsac.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2067,9 +2064,9 @@ define <vscale x 8 x i64> @vnmsac_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu ; RV32-NEXT: vnmsac.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2098,9 +2095,9 @@ define <vscale x 8 x i64> @vnmsac_vx_nxv8i64_unmasked(<vscale x 8 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, ma ; RV32-NEXT: vnmsac.vv v16, v8, v24 ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2143,9 +2140,8 @@ define <vscale x 8 x i64> @vnmsac_vx_nxv8i64_ta(<vscale x 8 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vnmsac.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll index ef281c52838f..e864d71fdad1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll @@ -1326,9 +1326,8 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1353,9 +1352,8 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1422,9 +1420,8 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1449,9 +1446,8 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1518,9 +1514,8 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1545,9 +1540,8 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1614,9 +1608,8 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1641,9 +1634,8 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll index d99fd036b4fc..ce9d6c5ab91a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll @@ -785,8 +785,7 @@ define zeroext i1 @vreduce_and_nxv128i1(<vscale x 128 x i1> %v) { ; CHECK-LABEL: vreduce_and_nxv128i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-NEXT: vmand.mm v8, v0, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v0, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -814,8 +813,7 @@ define zeroext i1 @vreduce_smax_nxv128i1(<vscale x 128 x i1> %v) { ; CHECK-LABEL: vreduce_smax_nxv128i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-NEXT: vmand.mm v8, v0, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v0, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -829,8 +827,7 @@ define zeroext i1 @vreduce_umin_nxv128i1(<vscale x 128 x i1> %v) { ; CHECK-LABEL: vreduce_umin_nxv128i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma -; CHECK-NEXT: vmand.mm v8, v0, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v0, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -892,8 +889,7 @@ define zeroext i1 @vreduce_and_nxv256i1(<vscale x 256 x i1> %v) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v0, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -925,8 +921,7 @@ define zeroext i1 @vreduce_smax_nxv256i1(<vscale x 256 x i1> %v) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v0, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -942,8 +937,7 @@ define zeroext i1 @vreduce_umin_nxv256i1(<vscale x 256 x i1> %v) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v0, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -1019,8 +1013,7 @@ define zeroext i1 @vreduce_and_nxv512i1(<vscale x 512 x i1> %v) { ; CHECK-NEXT: vmand.mm v11, v0, v11 ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v11, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -1060,8 +1053,7 @@ define zeroext i1 @vreduce_smax_nxv512i1(<vscale x 512 x i1> %v) { ; CHECK-NEXT: vmand.mm v11, v0, v11 ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v11, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -1081,8 +1073,7 @@ define zeroext i1 @vreduce_umin_nxv512i1(<vscale x 512 x i1> %v) { ; CHECK-NEXT: vmand.mm v11, v0, v11 ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v11, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -1186,8 +1177,7 @@ define zeroext i1 @vreduce_and_nxv1024i1(<vscale x 1024 x i1> %v) { ; CHECK-NEXT: vmand.mm v11, v15, v11 ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v11, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -1243,8 +1233,7 @@ define zeroext i1 @vreduce_smax_nxv1024i1(<vscale x 1024 x i1> %v) { ; CHECK-NEXT: vmand.mm v11, v15, v11 ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v11, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret @@ -1272,8 +1261,7 @@ define zeroext i1 @vreduce_umin_nxv1024i1(<vscale x 1024 x i1> %v) { ; CHECK-NEXT: vmand.mm v11, v15, v11 ; CHECK-NEXT: vmand.mm v8, v8, v10 ; CHECK-NEXT: vmand.mm v9, v11, v9 -; CHECK-NEXT: vmand.mm v8, v9, v8 -; CHECK-NEXT: vmnot.m v8, v8 +; CHECK-NEXT: vmnand.mm v8, v9, v8 ; CHECK-NEXT: vcpop.m a0, v8 ; CHECK-NEXT: seqz a0, a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll index 3273274a70b4..66ba2697fe5f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll @@ -893,9 +893,8 @@ define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -920,9 +919,8 @@ define <vscale x 1 x i64> @vrem_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -969,9 +967,8 @@ define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -996,9 +993,8 @@ define <vscale x 2 x i64> @vrem_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1045,9 +1041,8 @@ define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1072,9 +1067,8 @@ define <vscale x 4 x i64> @vrem_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1121,9 +1115,8 @@ define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1148,9 +1141,8 @@ define <vscale x 8 x i64> @vrem_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll index 6b588d0917ff..4608661eb5df 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll @@ -892,9 +892,8 @@ define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -919,9 +918,8 @@ define <vscale x 1 x i64> @vremu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -968,9 +966,8 @@ define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -995,9 +992,8 @@ define <vscale x 2 x i64> @vremu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1044,9 +1040,8 @@ define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1071,9 +1066,8 @@ define <vscale x 4 x i64> @vremu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1120,9 +1114,8 @@ define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1147,9 +1140,8 @@ define <vscale x 8 x i64> @vremu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll index 0f38e9408fb5..c41139c64eb0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll @@ -842,9 +842,8 @@ define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -869,9 +868,8 @@ define <vscale x 1 x i64> @vrsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -918,9 +916,8 @@ define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v10, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -945,9 +942,8 @@ define <vscale x 2 x i64> @vrsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -994,9 +990,8 @@ define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v12, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1021,9 +1016,8 @@ define <vscale x 4 x i64> @vrsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1070,9 +1064,8 @@ define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1097,9 +1090,8 @@ define <vscale x 8 x i64> @vrsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll index 575d041b091d..e471f4b2e92b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll @@ -1425,9 +1425,8 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1452,9 +1451,8 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1521,9 +1519,8 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1548,9 +1545,8 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1617,9 +1613,8 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1644,9 +1639,8 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1713,9 +1707,8 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1740,9 +1733,8 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll index c9ed72bc63da..f76a2b4b78bc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll @@ -1424,9 +1424,8 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1451,9 +1450,8 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1520,9 +1518,8 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1547,9 +1544,8 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1616,9 +1612,8 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1643,9 +1638,8 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1712,9 +1706,8 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1739,9 +1732,8 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll index 001f74450352..c041a165a594 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll @@ -131,10 +131,9 @@ declare <vscale x 2 x half> @llvm.vp.sitofp.nxv2f16.nxv2i7(<vscale x 2 x i7>, <v define <vscale x 2 x half> @vsitofp_nxv2f16_nxv2i7(<vscale x 2 x i7> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { ; ZVFH-LABEL: vsitofp_nxv2f16_nxv2i7: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vsetvli a1, zero, e8, mf4, ta, ma +; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; ZVFH-NEXT: vadd.vv v8, v8, v8 ; ZVFH-NEXT: vsra.vi v9, v8, 1 -; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; ZVFH-NEXT: vfwcvt.f.x.v v8, v9, v0.t ; ZVFH-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll index c0da928a72e9..ebf8d5eeb40b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll @@ -1468,9 +1468,8 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1495,9 +1494,8 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1566,9 +1564,8 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1593,9 +1590,8 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1664,9 +1660,8 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1691,9 +1686,8 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1762,9 +1756,8 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1789,9 +1782,8 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll index b602f11e2c80..d54901c93d53 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll @@ -1466,9 +1466,8 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1493,9 +1492,8 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1564,9 +1562,8 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1591,9 +1588,8 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1662,9 +1658,8 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1689,9 +1684,8 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1760,9 +1754,8 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1787,9 +1780,8 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll index 65ba791fe780..e28da6bc4ec6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll @@ -922,9 +922,8 @@ define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -949,9 +948,8 @@ define <vscale x 1 x i64> @vsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -998,9 +996,8 @@ define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1025,9 +1022,8 @@ define <vscale x 2 x i64> @vsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1074,9 +1070,8 @@ define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1101,9 +1096,8 @@ define <vscale x 4 x i64> @vsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1150,9 +1144,8 @@ define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1177,9 +1170,8 @@ define <vscale x 8 x i64> @vsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll index 06d85193e3b6..3d27a1eaf22e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll @@ -124,9 +124,8 @@ define <vscale x 2 x half> @vuitofp_nxv2f16_nxv2i7(<vscale x 2 x i7> %va, <vscal ; ZVFH-LABEL: vuitofp_nxv2f16_nxv2i7: ; ZVFH: # %bb.0: ; ZVFH-NEXT: li a1, 127 -; ZVFH-NEXT: vsetvli a2, zero, e8, mf4, ta, ma -; ZVFH-NEXT: vand.vx v9, v8, a1 ; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma +; ZVFH-NEXT: vand.vx v9, v8, a1 ; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9, v0.t ; ZVFH-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll index f3dd7ec48881..1694a7af0a0b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll @@ -1694,9 +1694,8 @@ define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1721,9 +1720,8 @@ define <vscale x 1 x i64> @vxor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1810,9 +1808,8 @@ define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1837,9 +1834,8 @@ define <vscale x 2 x i64> @vxor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1926,9 +1922,8 @@ define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1953,9 +1948,8 @@ define <vscale x 4 x i64> @vxor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2042,9 +2036,8 @@ define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2069,9 +2062,8 @@ define <vscale x 8 x i64> @vxor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll b/llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll new file mode 100644 index 000000000000..c8832bf49dd6 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/xcvmem-heuristic.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O3 -mtriple=riscv32 -mattr=+m,+xcvmem -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK + +define i32 @test_heuristic(ptr %b, i32 %e, i1 %0) { +; CHECK-LABEL: test_heuristic: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: add a3, a0, a1 +; CHECK-NEXT: andi a2, a2, 1 +; CHECK-NEXT: .LBB0_1: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: cv.lbu a1, (a3), 1 +; CHECK-NEXT: addi a0, a0, 1 +; CHECK-NEXT: beqz a2, .LBB0_1 +; CHECK-NEXT: # %bb.2: # %exit +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: ret +entry: + %1 = getelementptr i8, ptr %b, i32 %e + br label %loop + +loop: ; preds = %loop, %entry + %2 = phi ptr [ %b, %entry ], [ %7, %loop ] + %3 = phi ptr [ %1, %entry ], [ %8, %loop ] + %4 = load i8, ptr %2, align 1 + %5 = load i8, ptr %3, align 1 + %6 = zext i8 %5 to i32 + %7 = getelementptr i8, ptr %2, i32 1 + %8 = getelementptr i8, ptr %3, i32 1 + br i1 %0, label %exit, label %loop + +exit: ; preds = %loop + ret i32 %6 +} diff --git a/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll b/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll index f8207c56a565..5ce4a1954c5f 100644 --- a/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll +++ b/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; CHECK-SPIRV: %[[#Int:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#Int:]] = OpTypeInt 32 0 ; CHECK-SPIRV-DAG: %[[#MemScope_CrossDevice:]] = OpConstant %[[#Int]] 0 ; CHECK-SPIRV-DAG: %[[#MemSemEqual_SeqCst:]] = OpConstant %[[#Int]] 16 ; CHECK-SPIRV-DAG: %[[#MemSemUnequal_Acquire:]] = OpConstant %[[#Int]] 2 diff --git a/llvm/test/CodeGen/SPIRV/event-zero-const.ll b/llvm/test/CodeGen/SPIRV/event-zero-const.ll index f3f20a0fb2f4..523d2ad9825f 100644 --- a/llvm/test/CodeGen/SPIRV/event-zero-const.ll +++ b/llvm/test/CodeGen/SPIRV/event-zero-const.ll @@ -4,10 +4,10 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK: %[[#LongTy:]] = OpTypeInt 64 0 -; CHECK: %[[#EventTy:]] = OpTypeEvent -; CHECK: %[[#LongNull:]] = OpConstantNull %[[#LongTy]] -; CHECK: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent +; CHECK-DAG: %[[#LongNull:]] = OpConstantNull %[[#LongTy]] +; CHECK-DAG: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] ; CHECK: OpFunction ; CHECK: OpINotEqual %[[#]] %[[#]] %[[#LongNull]] ; CHECK: OpGroupAsyncCopy %[[#EventTy]] %[[#]] %[[#]] %[[#]] %[[#]] %[[#]] %[[#EventNull]] diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll index 368c5d4a3298..80309e96db00 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll @@ -1,16 +1,17 @@ -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled -; XFAIL: expensive_checks - ; CHECK-DAG: OpName %[[I9:.*]] "_ZN13BaseIncrement9incrementEPi" ; CHECK-DAG: OpName %[[I29:.*]] "_ZN12IncrementBy29incrementEPi" ; CHECK-DAG: OpName %[[I49:.*]] "_ZN12IncrementBy49incrementEPi" ; CHECK-DAG: OpName %[[I89:.*]] "_ZN12IncrementBy89incrementEPi" +; CHECK-DAG: OpName %[[Foo:.*]] "foo" ; CHECK-DAG: %[[TyVoid:.*]] = OpTypeVoid -; CHECK-DAG: %[[TyArr:.*]] = OpTypeArray +; CHECK-DAG: %[[TyInt32:.*]] = OpTypeInt 32 0 +; CHECK-DAG: %[[TyInt8:.*]] = OpTypeInt 8 0 +; CHECK-DAG: %[[Const8:.*]] = OpConstant %[[TyInt32]] 8 +; CHECK-DAG: %[[TyArr:.*]] = OpTypeArray %[[TyInt8]] %[[Const8]] ; CHECK-DAG: %[[TyStruct1:.*]] = OpTypeStruct %[[TyArr]] ; CHECK-DAG: %[[TyStruct2:.*]] = OpTypeStruct %[[TyStruct1]] ; CHECK-DAG: %[[TyPtrStruct2:.*]] = OpTypePointer Generic %[[TyStruct2]] @@ -18,16 +19,21 @@ ; CHECK-DAG: %[[TyPtrFun:.*]] = OpTypePointer Generic %[[TyFun]] ; CHECK-DAG: %[[TyPtrPtrFun:.*]] = OpTypePointer Generic %[[TyPtrFun]] -; CHECK: %[[I9]] = OpFunction -; CHECK: %[[I29]] = OpFunction -; CHECK: %[[I49]] = OpFunction -; CHECK: %[[I89]] = OpFunction +; CHECK-DAG: %[[I9]] = OpFunction +; CHECK-DAG: %[[I29]] = OpFunction +; CHECK-DAG: %[[I49]] = OpFunction +; CHECK-DAG: %[[I89]] = OpFunction + +; CHECK: %[[Foo]] = OpFunction +; CHECK-4: OpFunctionParameter ; CHECK: %[[Arg1:.*]] = OpPhi %[[TyPtrStruct2]] ; CHECK: %[[VTbl:.*]] = OpBitcast %[[TyPtrPtrFun]] %[[#]] ; CHECK: %[[FP:.*]] = OpLoad %[[TyPtrFun]] %[[VTbl]] ; CHECK: %[[#]] = OpFunctionPointerCallINTEL %[[TyVoid]] %[[FP]] %[[Arg1]] %[[#]] +; CHECK-NO: OpFunction + %"cls::id" = type { %"cls::detail::array" } %"cls::detail::array" = type { [1 x i64] } %struct.obj_storage_t = type { %"struct.aligned_storage<BaseIncrement, IncrementBy2, IncrementBy4, IncrementBy8>::type" } diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll index 75ad382f05ff..b96da631c0a8 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll @@ -1,9 +1,6 @@ -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled -; XFAIL: expensive_checks - ; CHECK-DAG: OpCapability FunctionPointersINTEL ; CHECK-DAG: OpCapability Int64 ; CHECK: OpExtension "SPV_INTEL_function_pointers" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll index d38de216c223..8edecc1329d0 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll @@ -2,15 +2,9 @@ ; pointers/PtrCast-null-in-OpSpecConstantOp.ll (that is OpSpecConstantOp with ptr-cast operation) correctly ; work also for function pointers. -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - --spirv-ext=+SPV_INTEL_function_pointers | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - --spirv-ext=+SPV_INTEL_function_pointers | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled -; XFAIL: expensive_checks - -; Running with -verify-machineinstrs would lead to "Reading virtual register without a def" -; error, because OpConstantFunctionPointerINTEL forward-refers to a function definition. - ; CHECK-COUNT-3: %[[#]] = OpSpecConstantOp %[[#]] 121 %[[#]] ; CHECK-COUNT-3: OpPtrCastToGeneric diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll index e006651d49e4..91286d5bf32e 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll @@ -31,20 +31,20 @@ ; CHECK-DAG: %[[#Const123:]] = OpConstant %[[#Int32Ty]] 123 ; CHECK-DAG: %[[#Const42:]] = OpConstant %[[#DoubleTy:]] 42 -; CHECK: %[[#Dialect:]] = OpAsmTargetINTEL "spirv64-unknown-unknown" +; CHECK-DAG: %[[#Dialect:]] = OpAsmTargetINTEL "spirv64-unknown-unknown" ; CHECK-NO: OpAsmTargetINTEL -; CHECK: %[[#Asm1:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "" -; CHECK: %[[#Asm2:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "nop" "" -; CHECK: %[[#Asm3:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "~{cc},~{memory}" -; CHECK: %[[#Asm4:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun2Ty:]] %[[#Dialect]] "clobber_out $0" "=&r" -; CHECK: %[[#Asm5:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun3Ty]] %[[#Dialect]] "icmd $0 $1" "=r,r" -; CHECK: %[[#Asm6:]] = OpAsmINTEL %[[#FloatTy]] %[[#Fun4Ty]] %[[#Dialect]] "fcmd $0 $1" "=r,r" -; CHECK: %[[#Asm7:]] = OpAsmINTEL %[[#HalfTy]] %[[#Fun5Ty]] %[[#Dialect]] "fcmdext $0 $1 $2" "=r,r,r" -; CHECK: %[[#Asm8:]] = OpAsmINTEL %[[#Int8Ty]] %[[#Fun6Ty]] %[[#Dialect]] "cmdext $0 $3 $1 $2" "=r,r,r,r" -; CHECK: %[[#Asm9:]] = OpAsmINTEL %[[#Int64Ty]] %[[#Fun7Ty]] %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r" -; CHECK: %[[#Asm10:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "r,r" -; CHECK: %[[#Asm11:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "i,i" +; CHECK-DAG: %[[#Asm1:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "" +; CHECK-DAG: %[[#Asm2:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "nop" "" +; CHECK-DAG: %[[#Asm3:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "~{cc},~{memory}" +; CHECK-DAG: %[[#Asm4:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun2Ty:]] %[[#Dialect]] "clobber_out $0" "=&r" +; CHECK-DAG: %[[#Asm5:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun3Ty]] %[[#Dialect]] "icmd $0 $1" "=r,r" +; CHECK-DAG: %[[#Asm6:]] = OpAsmINTEL %[[#FloatTy]] %[[#Fun4Ty]] %[[#Dialect]] "fcmd $0 $1" "=r,r" +; CHECK-DAG: %[[#Asm7:]] = OpAsmINTEL %[[#HalfTy]] %[[#Fun5Ty]] %[[#Dialect]] "fcmdext $0 $1 $2" "=r,r,r" +; CHECK-DAG: %[[#Asm8:]] = OpAsmINTEL %[[#Int8Ty]] %[[#Fun6Ty]] %[[#Dialect]] "cmdext $0 $3 $1 $2" "=r,r,r,r" +; CHECK-DAG: %[[#Asm9:]] = OpAsmINTEL %[[#Int64Ty]] %[[#Fun7Ty]] %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r" +; CHECK-DAG: %[[#Asm10:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "r,r" +; CHECK-DAG: %[[#Asm11:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "i,i" ; CHECK-NO: OpAsmINTEL ; CHECK: OpFunction diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll index 8ecd0a2b25eb..bd07ba1316ec 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll @@ -6,9 +6,11 @@ ; CHECK: OpCapability ShaderClockKHR ; CHECK: OpExtension "SPV_KHR_shader_clock" -; CHECK-DAG: [[uint:%[a-z0-9_]+]] = OpTypeInt 32 +; CHECK-DAG: [[uint:%[a-z0-9_]+]] = OpTypeInt 32 0 ; CHECK-DAG: [[ulong:%[a-z0-9_]+]] = OpTypeInt 64 ; CHECK-DAG: [[v2uint:%[a-z0-9_]+]] = OpTypeVector [[uint]] 2 +; CHECK-DAG: OpConstant [[uint]] 8 +; CHECK-DAG: OpConstant [[uint]] 16 ; CHECK-DAG: [[uint_1:%[a-z0-9_]+]] = OpConstant [[uint]] 1 ; CHECK-DAG: [[uint_2:%[a-z0-9_]+]] = OpConstant [[uint]] 2 ; CHECK-DAG: [[uint_3:%[a-z0-9_]+]] = OpConstant [[uint]] 3 diff --git a/llvm/test/CodeGen/SPIRV/global-var-name-linkage.ll b/llvm/test/CodeGen/SPIRV/global-var-name-linkage.ll new file mode 100644 index 000000000000..4501819ce494 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/global-var-name-linkage.ll @@ -0,0 +1,59 @@ +; Check names and decoration of global variables. + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: OpName %[[#id18:]] "G1" +; CHECK-DAG: OpName %[[#id22:]] "g1" +; CHECK-DAG: OpName %[[#id23:]] "g2" +; CHECK-DAG: OpName %[[#id27:]] "g4" +; CHECK-DAG: OpName %[[#id30:]] "c1" +; CHECK-DAG: OpName %[[#id31:]] "n_t" +; CHECK-DAG: OpName %[[#id32:]] "w" +; CHECK-DAG: OpName %[[#id34:]] "a.b" +; CHECK-DAG: OpName %[[#id35:]] "e" +; CHECK-DAG: OpName %[[#id36:]] "y.z" +; CHECK-DAG: OpName %[[#id38:]] "x" + +; CHECK-NOT: OpDecorate %[[#id18]] LinkageAttributes +; CHECK-DAG: OpDecorate %[[#id18]] Constant +; CHECK-DAG: OpDecorate %[[#id22]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id22]] LinkageAttributes "g1" Export +; CHECK-DAG: OpDecorate %[[#id23]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id27]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id27]] LinkageAttributes "g4" Export +; CHECK-DAG: OpDecorate %[[#id30]] Constant +; CHECK-DAG: OpDecorate %[[#id30]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id30]] LinkageAttributes "c1" Export +; CHECK-DAG: OpDecorate %[[#id31]] Constant +; CHECK-DAG: OpDecorate %[[#id31]] LinkageAttributes "n_t" Import +; CHECK-DAG: OpDecorate %[[#id32]] Constant +; CHECK-DAG: OpDecorate %[[#id32]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id32]] LinkageAttributes "w" Export +; CHECK-DAG: OpDecorate %[[#id34]] Constant +; CHECK-DAG: OpDecorate %[[#id34]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id35]] LinkageAttributes "e" Import +; CHECK-DAG: OpDecorate %[[#id36]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id38]] Constant +; CHECK-DAG: OpDecorate %[[#id38]] Alignment 4 + +%"class.sycl::_V1::nd_item" = type { i8 } + +@G1 = private unnamed_addr addrspace(1) constant %"class.sycl::_V1::nd_item" poison, align 1 +@g1 = addrspace(1) global i32 1, align 4 +@g2 = internal addrspace(1) global i32 2, align 4 +@g4 = common addrspace(1) global i32 0, align 4 +@c1 = addrspace(2) constant [2 x i32] [i32 0, i32 1], align 4 +@n_t = external addrspace(2) constant [256 x i32] +@w = addrspace(1) constant i32 0, align 4 +@a.b = internal addrspace(2) constant [2 x i32] [i32 2, i32 3], align 4 +@e = external addrspace(1) global i32 +@y.z = internal addrspace(1) global i32 0, align 4 +@x = internal addrspace(2) constant float 1.000000e+00, align 4 + +define internal spir_func void @foo(ptr addrspace(4) align 1 %arg) { + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupID.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupID.ll new file mode 100644 index 000000000000..92947f7865ce --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupID.ll @@ -0,0 +1,52 @@ +; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#int:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#v3int:]] = OpTypeVector %[[#int]] 3 +; CHECK-DAG: %[[#ptr_Input_v3int:]] = OpTypePointer Input %[[#v3int]] +; CHECK-DAG: %[[#tempvar:]] = OpUndef %[[#v3int]] +; CHECK-DAG: %[[#WorkgroupId:]] = OpVariable %[[#ptr_Input_v3int]] Input + +; CHECK-DAG: OpEntryPoint GLCompute {{.*}} %[[#WorkgroupId]] +; CHECK-DAG: OpName %[[#WorkgroupId]] "__spirv_BuiltInWorkgroupId" +; CHECK-DAG: OpDecorate %[[#WorkgroupId]] LinkageAttributes "__spirv_BuiltInWorkgroupId" Import +; CHECK-DAG: OpDecorate %[[#WorkgroupId]] BuiltIn WorkgroupId + +target triple = "spirv-unknown-vulkan-library" + +declare void @group_id_user(<3 x i32>) + +; Function Attrs: convergent noinline norecurse +define void @main() #1 { +entry: + +; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#WorkgroupId]] +; CHECK: %[[#load0:]] = OpCompositeExtract %[[#int]] %[[#load]] 0 + %1 = call i32 @llvm.spv.group.id(i32 0) + +; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load0]] %[[#tempvar]] + %2 = insertelement <3 x i32> poison, i32 %1, i64 0 + +; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#WorkgroupId]] +; CHECK: %[[#load1:]] = OpCompositeExtract %[[#int]] %[[#load]] 1 + %3 = call i32 @llvm.spv.group.id(i32 1) + +; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load1]] %[[#tempvar]] 1 + %4 = insertelement <3 x i32> %2, i32 %3, i64 1 + +; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#WorkgroupId]] +; CHECK: %[[#load2:]] = OpCompositeExtract %[[#int]] %[[#load]] 2 + %5 = call i32 @llvm.spv.group.id(i32 2) + +; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load2]] %[[#tempvar]] 2 + %6 = insertelement <3 x i32> %4, i32 %5, i64 2 + + call spir_func void @group_id_user(<3 x i32> %6) + ret void +} + +; Function Attrs: nounwind willreturn memory(none) +declare i32 @llvm.spv.group.id(i32) #3 + +attributes #1 = { convergent noinline norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { nounwind willreturn memory(none) } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll index 2e0eb8c429ac..b1625c07111e 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll @@ -15,7 +15,7 @@ entry: ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec3_float_16]]
; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec3_float_16]]
; CHECK: %[[#]] = OpExtInst %[[#vec3_float_16]] %[[#op_ext_glsl]] Cross %[[#arg0]] %[[#arg1]]
- %hlsl.cross = call <3 x half> @llvm.spv.cross.v4f16(<3 x half> %a, <3 x half> %b)
+ %hlsl.cross = call <3 x half> @llvm.spv.cross.v3f16(<3 x half> %a, <3 x half> %b)
ret <3 x half> %hlsl.cross
}
@@ -25,9 +25,9 @@ entry: ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec3_float_32]]
; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec3_float_32]]
; CHECK: %[[#]] = OpExtInst %[[#vec3_float_32]] %[[#op_ext_glsl]] Cross %[[#arg0]] %[[#arg1]]
- %hlsl.cross = call <3 x float> @llvm.spv.cross.v4f32(<3 x float> %a, <3 x float> %b)
+ %hlsl.cross = call <3 x float> @llvm.spv.cross.v3f32(<3 x float> %a, <3 x float> %b)
ret <3 x float> %hlsl.cross
}
-declare <3 x half> @llvm.spv.cross.v4f16(<3 x half>, <3 x half>)
-declare <3 x float> @llvm.spv.cross.v4f32(<3 x float>, <3 x float>)
+declare <3 x half> @llvm.spv.cross.v3f16(<3 x half>, <3 x half>)
+declare <3 x float> @llvm.spv.cross.v3f32(<3 x float>, <3 x float>)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/distance.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/distance.ll new file mode 100644 index 000000000000..85a24a0127ae --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/distance.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; Make sure SPIRV operation function calls for distance are lowered correctly.
+
+; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
+
+define noundef half @distance_half4(<4 x half> noundef %a, <4 x half> noundef %b) {
+entry:
+ ; CHECK: %[[#]] = OpFunction %[[#float_16]] None %[[#]]
+ ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] Distance %[[#arg0]] %[[#arg1]]
+ %spv.distance = call half @llvm.spv.distance.f16(<4 x half> %a, <4 x half> %b)
+ ret half %spv.distance
+}
+
+define noundef float @distance_float4(<4 x float> noundef %a, <4 x float> noundef %b) {
+entry:
+ ; CHECK: %[[#]] = OpFunction %[[#float_32]] None %[[#]]
+ ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
+ ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] Distance %[[#arg0]] %[[#arg1]]
+ %spv.distance = call float @llvm.spv.distance.f32(<4 x float> %a, <4 x float> %b)
+ ret float %spv.distance
+}
+
+declare half @llvm.spv.distance.f16(<4 x half>, <4 x half>)
+declare float @llvm.spv.distance.f32(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll index b4a9d8e0664b..1ac862b79a3f 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll @@ -11,19 +11,21 @@ define noundef half @length_half4(<4 x half> noundef %a) {
entry:
- ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
+ ; CHECK: %[[#]] = OpFunction %[[#float_16]] None %[[#]]
+ ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] Length %[[#arg0]]
- %hlsl.length = call half @llvm.spv.length.v4f16(<4 x half> %a)
+ %hlsl.length = call half @llvm.spv.length.f16(<4 x half> %a)
ret half %hlsl.length
}
define noundef float @length_float4(<4 x float> noundef %a) {
entry:
- ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
+ ; CHECK: %[[#]] = OpFunction %[[#float_32]] None %[[#]]
+ ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] Length %[[#arg0]]
- %hlsl.length = call float @llvm.spv.length.v4f32(<4 x float> %a)
+ %hlsl.length = call float @llvm.spv.length.f32(<4 x float> %a)
ret float %hlsl.length
}
-declare half @llvm.spv.length.v4f16(<4 x half>)
-declare float @llvm.spv.length.v4f32(<4 x float>)
+declare half @llvm.spv.length.f16(<4 x half>)
+declare float @llvm.spv.length.f32(<4 x float>)
diff --git a/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll b/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll index 8f14eba21b63..49aaa45afed1 100644 --- a/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll +++ b/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll @@ -25,9 +25,7 @@ ; CHECK-SPIRV-DAG: [[v4uint:%[a-z0-9_]+]] = OpTypeVector [[uint]] 4 ; CHECK-SPIRV-DAG: [[vecstruct:%[a-z0-9_]+]] = OpTypeStruct [[v4uint]] [[v4uint]] ; CHECK-SPIRV-DAG: [[_ptr_Function_vecstruct:%[a-z0-9_]+]] = OpTypePointer Function [[vecstruct]] -; CHECK-SPIRV-DAG: [[struct_anon:%[a-z0-9_.]+]] = OpTypeStruct [[uint]] [[uint]] -; CHECK-SPIRV-DAG: [[_ptr_Function_struct_anon:%[a-z0-9_]+]] = OpTypePointer Function [[struct_anon]] -; CHECK-SPIRV-DAG: [[_ptr_Generic_struct_anon:%[a-z0-9_]+]] = OpTypePointer Generic [[struct_anon]] +; CHECK-SPIRV-DAG: [[_ptr_Generic_i32struct:%[a-z0-9_]+]] = OpTypePointer Generic [[i32struct]] define spir_func void @test_builtin_iaddcarrycc(i8 %a, i8 %b) { entry: @@ -116,9 +114,9 @@ define spir_func void @test_builtin_iaddcarry_anon(i32 %a, i32 %b) { ; CHECK-SPIRV: [[a_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[b_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[entry_4:%[a-z0-9_]+]] = OpLabel -; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_struct_anon]] Function -; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_struct_anon]] [[var_59]] -; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpIAddCarry [[struct_anon]] [[a_4]] [[b_4]] +; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_i32struct]] Function +; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_i32struct]] [[var_59]] +; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpIAddCarry [[i32struct]] [[a_4]] [[b_4]] ; CHECK-SPIRV: OpStore [[var_61]] [[var_62]] declare void @_Z17__spirv_IAddCarryIiiE4anonIT_T0_ES1_S2_(ptr addrspace(4) sret(%struct.anon) align 4, i32, i32) diff --git a/llvm/test/CodeGen/SPIRV/image-unoptimized.ll b/llvm/test/CodeGen/SPIRV/image-unoptimized.ll index 0ce9c73ab103..d7d5b1d6b756 100644 --- a/llvm/test/CodeGen/SPIRV/image-unoptimized.ll +++ b/llvm/test/CodeGen/SPIRV/image-unoptimized.ll @@ -1,7 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s -; CHECK: %[[#TypeImage:]] = OpTypeImage -; CHECK: %[[#TypeSampler:]] = OpTypeSampler +; CHECK-DAG: %[[#TypeImage:]] = OpTypeImage +; CHECK-DAG: %[[#TypeSampler:]] = OpTypeSampler ; CHECK-DAG: %[[#TypeImagePtr:]] = OpTypePointer {{.*}} %[[#TypeImage]] ; CHECK-DAG: %[[#TypeSamplerPtr:]] = OpTypePointer {{.*}} %[[#TypeSampler]] diff --git a/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll b/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll index 08b4d2a1fa8e..ca842d2f9557 100644 --- a/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll +++ b/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll @@ -23,9 +23,7 @@ ; CHECK-SPIRV-DAG: [[v4uint:%[a-z0-9_]+]] = OpTypeVector [[uint]] 4 ; CHECK-SPIRV-DAG: [[vecstruct:%[a-z0-9_]+]] = OpTypeStruct [[v4uint]] [[v4uint]] ; CHECK-SPIRV-DAG: [[_ptr_Function_vecstruct:%[a-z0-9_]+]] = OpTypePointer Function [[vecstruct]] -; CHECK-SPIRV-DAG: [[struct_anon:%[a-z0-9_.]+]] = OpTypeStruct [[uint]] [[uint]] -; CHECK-SPIRV-DAG: [[_ptr_Function_struct_anon:%[a-z0-9_]+]] = OpTypePointer Function [[struct_anon]] -; CHECK-SPIRV-DAG: [[_ptr_Generic_struct_anon:%[a-z0-9_]+]] = OpTypePointer Generic [[struct_anon]] +; CHECK-SPIRV-DAG: [[_ptr_Generic_i32struct:%[a-z0-9_]+]] = OpTypePointer Generic [[i32struct]] define spir_func void @test_builtin_isubborrowcc(i8 %a, i8 %b) { entry: @@ -114,9 +112,9 @@ define spir_func void @test_builtin_isubborrow_anon(i32 %a, i32 %b) { ; CHECK-SPIRV: [[a_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[b_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[entry_4:%[a-z0-9_]+]] = OpLabel -; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_struct_anon]] Function -; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_struct_anon]] [[var_59]] -; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpISubBorrow [[struct_anon]] [[a_4]] [[b_4]] +; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_i32struct]] Function +; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_i32struct]] [[var_59]] +; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpISubBorrow [[i32struct]] [[a_4]] [[b_4]] ; CHECK-SPIRV: OpStore [[var_61]] [[var_62]] declare void @_Z18__spirv_ISubBorrowIiiE4anonIT_T0_ES1_S2_(ptr addrspace(4) sret(%struct.anon) align 4, i32, i32) diff --git a/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll b/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll index 0dc86233f8e1..61d06fe2752e 100644 --- a/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll +++ b/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll @@ -3,9 +3,9 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-SPIRV: %[[#Int:]] = OpTypeInt 32 0 -; CHECK-SPIRV: %[[#C0:]] = OpConstant %[[#Int]] 0 -; CHECK-SPIRV: %[[#C1:]] = OpConstant %[[#Int]] 1 +; CHECK-SPIRV-DAG: %[[#Int:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#C0:]] = OpConstant %[[#Int]] 0 +; CHECK-SPIRV-DAG: %[[#C1:]] = OpConstant %[[#Int]] 1 ; CHECK-SPIRV: OpSelect %[[#Int]] %[[#]] %[[#C1]] %[[#C0]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll index 2d5b30978aa2..25b530461012 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll @@ -1,21 +1,21 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_32:]] "spirv.llvm_fshl_i32" -; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_16:]] "spirv.llvm_fshl_i16" -; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_VEC_INT_16:]] "spirv.llvm_fshl_v2i16" -; CHECK-SPIRV: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHL_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_FSHL_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHL_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] -; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_32:]] = OpConstant %[[#TYPE_INT_32]] 8 -; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_16:]] = OpConstant %[[#TYPE_INT_16]] 8 -; CHECK-SPIRV: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] -; CHECK-SPIRV-DAG: %[[#CONST_TYPE_SIZE_32:]] = OpConstant %[[#TYPE_INT_32]] 32 +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHL_FUNC_32:]] "spirv.llvm_fshl_i32" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHL_FUNC_16:]] "spirv.llvm_fshl_i16" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHL_FUNC_VEC_INT_16:]] "spirv.llvm_fshl_v2i16" +; CHECK-SPIRV-DAG: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHL_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHL_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHL_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_32:]] = OpConstant %[[#TYPE_INT_32]] 8 +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_16:]] = OpConstant %[[#TYPE_INT_16]] 8 +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] +; CHECK-SPIRV-DAG: %[[#CONST_TYPE_SIZE_32:]] = OpConstant %[[#TYPE_INT_32]] 32 ; CHECK-SPIRV: %[[#]] = OpFunction %[[#TYPE_INT_32]] {{.*}} %[[#TYPE_ORIG_FUNC_32]] ; CHECK-SPIRV: %[[#X:]] = OpFunctionParameter %[[#TYPE_INT_32]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll index 4cf5ca53a411..55fb2d9079e1 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll @@ -1,20 +1,20 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_32:]] "spirv.llvm_fshr_i32" -; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_16:]] "spirv.llvm_fshr_i16" -; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_VEC_INT_16:]] "spirv.llvm_fshr_v2i16" -; CHECK-SPIRV: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHR_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_FSHR_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHR_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHR_FUNC_32:]] "spirv.llvm_fshr_i32" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHR_FUNC_16:]] "spirv.llvm_fshr_i16" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHR_FUNC_VEC_INT_16:]] "spirv.llvm_fshr_v2i16" +; CHECK-SPIRV-DAG: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHR_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHR_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHR_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] ; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_32:]] = OpConstant %[[#TYPE_INT_32]] 8 ; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_16:]] = OpConstant %[[#TYPE_INT_16]] 8 -; CHECK-SPIRV: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] ; CHECK-SPIRV-DAG: %[[#CONST_TYPE_SIZE_32:]] = OpConstant %[[#TYPE_INT_32]] 32 ; CHECK-SPIRV: %[[#]] = OpFunction %[[#TYPE_INT_32]] {{.*}} %[[#TYPE_ORIG_FUNC_32]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll index e7a986980f25..d5e70ae9e7aa 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll @@ -12,17 +12,17 @@ ; CHECK-DAG: %[[#Int8Ptr:]] = OpTypePointer Generic %[[#Int8]] ; CHECK-DAG: %[[#Const4:]] = OpConstant %[[#Int32]] 4 -; CHECK: %[[#Int8x4:]] = OpTypeArray %[[#Int8]] %[[#Const4]] +; CHECK-DAG: %[[#Int8x4:]] = OpTypeArray %[[#Int8]] %[[#Const4]] ; CHECK-DAG: %[[#Const12:]] = OpConstant %[[#Int32]] 12 -; CHECK: %[[#Int8x12:]] = OpTypeArray %[[#Int8]] %[[#Const12]] +; CHECK-DAG: %[[#Int8x12:]] = OpTypeArray %[[#Int8]] %[[#Const12]] ; CHECK-DAG: %[[#Const21:]] = OpConstant %[[#Int8]] 21 ; CHECK-DAG: %[[#False:]] = OpConstantFalse %[[#]] ; CHECK-DAG: %[[#ConstComp:]] = OpConstantComposite %[[#Int8x4]] %[[#Const21]] %[[#Const21]] %[[#Const21]] %[[#Const21]] ; CHECK-DAG: %[[#ConstNull:]] = OpConstantNull %[[#Int8x12]] -; CHECK: %[[#VarComp:]] = OpVariable %[[#]] UniformConstant %[[#ConstComp]] -; CHECK: %[[#VarNull:]] = OpVariable %[[#]] UniformConstant %[[#ConstNull]] +; CHECK-DAG: %[[#VarComp:]] = OpVariable %[[#]] UniformConstant %[[#ConstComp]] +; CHECK-DAG: %[[#VarNull:]] = OpVariable %[[#]] UniformConstant %[[#ConstNull]] ; CHECK-DAG: %[[#Int8PtrConst:]] = OpTypePointer UniformConstant %[[#Int8]] ; CHECK: OpCopyMemorySized %[[#Target:]] %[[#Source:]] %[[#Const12]] Aligned 4 diff --git a/llvm/test/CodeGen/SPIRV/logical-access-chain.ll b/llvm/test/CodeGen/SPIRV/logical-access-chain.ll index 39f6d33712ef..d56678ecfc2c 100644 --- a/llvm/test/CodeGen/SPIRV/logical-access-chain.ll +++ b/llvm/test/CodeGen/SPIRV/logical-access-chain.ll @@ -1,10 +1,10 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; CHECK: [[uint:%[0-9]+]] = OpTypeInt 32 0 -; CHECK: [[uint2:%[0-9]+]] = OpTypeVector [[uint]] 2 -; CHECK: [[uint_1:%[0-9]+]] = OpConstant [[uint]] 1 -; CHECK: [[ptr_uint:%[0-9]+]] = OpTypePointer Function [[uint]] -; CHECK: [[ptr_uint2:%[0-9]+]] = OpTypePointer Function [[uint2]] +; CHECK-DAG: [[uint:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[uint2:%[0-9]+]] = OpTypeVector [[uint]] 2 +; CHECK-DAG: [[uint_1:%[0-9]+]] = OpConstant [[uint]] 1 +; CHECK-DAG: [[ptr_uint:%[0-9]+]] = OpTypePointer Function [[uint]] +; CHECK-DAG: [[ptr_uint2:%[0-9]+]] = OpTypePointer Function [[uint2]] define void @main() #1 { entry: diff --git a/llvm/test/CodeGen/SPIRV/opencl/degrees.ll b/llvm/test/CodeGen/SPIRV/opencl/degrees.ll index 88f97835fe71..b8d4f52a2879 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/degrees.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/degrees.ll @@ -3,7 +3,7 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "OpenCL.std" +; CHECK-DAG: %[[#op_ext_ocl:]] = OpExtInstImport "OpenCL.std" ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 @@ -20,7 +20,7 @@ declare <4 x half> @llvm.spv.degrees.v4f16(<4 x half>) define noundef float @degrees_float(float noundef %a) { entry: ; CHECK: %[[#float_32_arg:]] = OpFunctionParameter %[[#float_32]] -; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] degrees %[[#float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_ocl]] degrees %[[#float_32_arg]] %elt.degrees = call float @llvm.spv.degrees.f32(float %a) ret float %elt.degrees } @@ -28,7 +28,7 @@ entry: define noundef half @degrees_half(half noundef %a) { entry: ; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]] -; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] degrees %[[#float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_ocl]] degrees %[[#float_16_arg]] %elt.degrees = call half @llvm.spv.degrees.f16(half %a) ret half %elt.degrees } @@ -36,7 +36,7 @@ entry: define noundef <4 x float> @degrees_float_vector(<4 x float> noundef %a) { entry: ; CHECK: %[[#vec4_float_32_arg:]] = OpFunctionParameter %[[#vec4_float_32]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] degrees %[[#vec4_float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_ocl]] degrees %[[#vec4_float_32_arg]] %elt.degrees = call <4 x float> @llvm.spv.degrees.v4f32(<4 x float> %a) ret <4 x float> %elt.degrees } @@ -44,7 +44,7 @@ entry: define noundef <4 x half> @degrees_half_vector(<4 x half> noundef %a) { entry: ; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] degrees %[[#vec4_float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_ocl]] degrees %[[#vec4_float_16_arg]] %elt.degrees = call <4 x half> @llvm.spv.degrees.v4f16(<4 x half> %a) ret <4 x half> %elt.degrees } diff --git a/llvm/test/CodeGen/SPIRV/opencl/distance.ll b/llvm/test/CodeGen/SPIRV/opencl/distance.ll new file mode 100644 index 000000000000..ac18804c00c9 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/opencl/distance.ll @@ -0,0 +1,34 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#op_ext_cl:]] = OpExtInstImport "OpenCL.std" + +; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 +; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4 +; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4 + +define noundef half @distance_half4(<4 x half> noundef %a, <4 x half> noundef %b) { +entry: + ; CHECK: %[[#]] = OpFunction %[[#float_16]] None %[[#]] + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec4_float_16]] + ; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_cl]] distance %[[#arg0]] %[[#arg1]] + %spv.distance = call half @llvm.spv.distance.f16(<4 x half> %a, <4 x half> %b) + ret half %spv.distance +} + +define noundef float @distance_float4(<4 x float> noundef %a, <4 x float> noundef %b) { +entry: + ; CHECK: %[[#]] = OpFunction %[[#float_32]] None %[[#]] + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec4_float_32]] + ; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_cl]] distance %[[#arg0]] %[[#arg1]] + %spv.distance = call float @llvm.spv.distance.f32(<4 x float> %a, <4 x float> %b) + ret float %spv.distance +} + +declare half @llvm.spv.distance.f16(<4 x half>, <4 x half>) +declare float @llvm.spv.distance.f32(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/SPIRV/opencl/radians.ll b/llvm/test/CodeGen/SPIRV/opencl/radians.ll index f7bb8d5226cd..5b4f26a13a4c 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/radians.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/radians.ll @@ -3,7 +3,7 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "OpenCL.std" +; CHECK-DAG: %[[#op_ext_ocl:]] = OpExtInstImport "OpenCL.std" ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 @@ -20,7 +20,7 @@ declare <4 x half> @llvm.spv.radians.v4f16(<4 x half>) define noundef float @radians_float(float noundef %a) { entry: ; CHECK: %[[#float_32_arg:]] = OpFunctionParameter %[[#float_32]] -; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] radians %[[#float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_ocl]] radians %[[#float_32_arg]] %elt.radians = call float @llvm.spv.radians.f32(float %a) ret float %elt.radians } @@ -28,7 +28,7 @@ entry: define noundef half @radians_half(half noundef %a) { entry: ; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]] -; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] radians %[[#float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_ocl]] radians %[[#float_16_arg]] %elt.radians = call half @llvm.spv.radians.f16(half %a) ret half %elt.radians } @@ -36,7 +36,7 @@ entry: define noundef <4 x float> @radians_float_vector(<4 x float> noundef %a) { entry: ; CHECK: %[[#vec4_float_32_arg:]] = OpFunctionParameter %[[#vec4_float_32]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] radians %[[#vec4_float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_ocl]] radians %[[#vec4_float_32_arg]] %elt.radians = call <4 x float> @llvm.spv.radians.v4f32(<4 x float> %a) ret <4 x float> %elt.radians } @@ -44,7 +44,7 @@ entry: define noundef <4 x half> @radians_half_vector(<4 x half> noundef %a) { entry: ; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] radians %[[#vec4_float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_ocl]] radians %[[#vec4_float_16_arg]] %elt.radians = call <4 x half> @llvm.spv.radians.v4f16(<4 x half> %a) ret <4 x half> %elt.radians } diff --git a/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll b/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll index 99e2c3e6d396..dee16da7e099 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll @@ -5,10 +5,8 @@ ; CHECK-DAG: %[[Struct:.*]] = OpTypeStruct %[[Array]] ; CHECK-DAG: %[[Zero:.*]] = OpTypeInt 64 0 ; CHECK-DAG: %[[Null:.*]] = OpConstantNull %[[Zero]] -; CHECK-DAG: %[[R1:.*]] = OpConstantComposite %[[Array]] %[[Null]] -; CHECK-DAG: %[[#]] = OpConstantComposite %[[Struct]] %[[R1]] -; CHECK-DAG: %[[R2:.*]] = OpConstantComposite %[[Array]] %[[Null]] -; CHECK-DAG: %[[#]] = OpConstantComposite %[[Struct]] %[[R2]] +; CHECK-DAG: %[[R:.*]] = OpConstantComposite %[[Array]] %[[Null]] +; CHECK-DAG: %[[#]] = OpConstantComposite %[[Struct]] %[[R]] @G1 = addrspace(1) constant { [1 x ptr addrspace(4)] } { [1 x ptr addrspace(4)] [ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4))] } @G2 = addrspace(1) constant { [1 x ptr addrspace(4)] } { [1 x ptr addrspace(4)] [ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4))] } diff --git a/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll b/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll index 03ecf5e8d839..59a24231769c 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll @@ -1,12 +1,12 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK: %[[TyInt64:.*]] = OpTypeInt 64 0 -; CHECK: %[[TyInt64Ptr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt64]] -; CHECK: %[[TyStruct:.*]] = OpTypeStruct %[[TyInt64Ptr]] %[[TyInt64Ptr]] -; CHECK: %[[ConstStruct:.*]] = OpConstantComposite %[[TyStruct]] %[[ConstField:.*]] %[[ConstField]] -; CHECK: %[[TyStructPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyStruct]] -; CHECK: OpVariable %[[TyStructPtr]] {{[a-zA-Z]+}} %[[ConstStruct]] +; CHECK-DAG: %[[TyInt64:.*]] = OpTypeInt 64 0 +; CHECK-DAG: %[[TyInt64Ptr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt64]] +; CHECK-DAG: %[[TyStruct:.*]] = OpTypeStruct %[[TyInt64Ptr]] %[[TyInt64Ptr]] +; CHECK-DAG: %[[ConstStruct:.*]] = OpConstantComposite %[[TyStruct]] %[[ConstField:.*]] %[[ConstField]] +; CHECK-DAG: %[[TyStructPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyStruct]] +; CHECK-DAG: OpVariable %[[TyStructPtr]] {{[a-zA-Z]+}} %[[ConstStruct]] @a = addrspace(1) constant i64 42 @struct = addrspace(1) global {ptr addrspace(1), ptr addrspace(1)} { ptr addrspace(1) @a, ptr addrspace(1) @a } diff --git a/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll b/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll index e4c7bdb9e9c8..8a90e40e8881 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll @@ -24,12 +24,10 @@ ; CHECK-SPIRV: OpName %[[#sample_kernel_float:]] "sample_kernel_float" ; CHECK-SPIRV: OpName %[[#sample_kernel_int:]] "sample_kernel_int" -; CHECK-SPIRV: %[[#TypeSampler:]] = OpTypeSampler +; CHECK-SPIRV-DAG: %[[#TypeSampler:]] = OpTypeSampler ; CHECK-SPIRV-DAG: %[[#SampledImageTy:]] = OpTypeSampledImage ; CHECK-SPIRV-DAG: %[[#ConstSampler1:]] = OpConstantSampler %[[#TypeSampler]] None 0 Linear ; CHECK-SPIRV-DAG: %[[#ConstSampler2:]] = OpConstantSampler %[[#TypeSampler]] Repeat 0 Nearest -; CHECK-SPIRV-DAG: %[[#ConstSampler3:]] = OpConstantSampler %[[#TypeSampler]] None 0 Linear -; CHECK-SPIRV-DAG: %[[#ConstSampler4:]] = OpConstantSampler %[[#TypeSampler]] Repeat 0 Nearest ; CHECK-SPIRV: %[[#sample_kernel_float]] = OpFunction %{{.*}} ; CHECK-SPIRV: %[[#InputImage:]] = OpFunctionParameter %{{.*}} @@ -65,13 +63,13 @@ declare spir_func target("spirv.Sampler") @__translate_sampler_initializer(i32) ; CHECK-SPIRV: %[[#InputImage:]] = OpFunctionParameter %{{.*}} ; CHECK-SPIRV: %[[#argSampl:]] = OpFunctionParameter %[[#TypeSampler]] -; CHECK-SPIRV: %[[#SampledImage4:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler3]] +; CHECK-SPIRV: %[[#SampledImage4:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler1]] ; CHECK-SPIRV: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#SampledImage4]] ; CHECK-SPIRV: %[[#SampledImage5:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#argSampl]] ; CHECK-SPIRV: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#SampledImage5]] -; CHECK-SPIRV: %[[#SampledImage6:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler4]] +; CHECK-SPIRV: %[[#SampledImage6:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler2]] ; CHECK-SPIRV: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#SampledImage6]] define dso_local spir_kernel void @sample_kernel_int(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) %input, <2 x float> noundef %coords, <4 x i32> addrspace(1)* nocapture noundef writeonly %results, target("spirv.Sampler") %argSampl) local_unnamed_addr { diff --git a/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll b/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll index 8b326e265502..55f1125706f6 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll @@ -39,7 +39,7 @@ ; CHECK-SPIRV-DAG: %[[#SAMP:]] = OpTypeSampler ; CHECK-SPIRV-DAG: %[[#SAMPIMG:]] = OpTypeSampledImage %[[#IMG2D_RD]] -; CHECK-SPIRV: %[[#SAMP_CONST:]] = OpConstantSampler %[[#SAMP]] None 0 Linear +; CHECK-SPIRV-DAG: %[[#SAMP_CONST:]] = OpConstantSampler %[[#SAMP]] None 0 Linear ; CHECK-SPIRV: %[[#]] = OpFunctionParameter %[[#PIPE_RD]] ; CHECK-SPIRV: %[[#]] = OpFunctionParameter %[[#PIPE_WR]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll index 74dbaab63e03..5810d9c59ee3 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll @@ -14,19 +14,19 @@ ; CHECK-SPIRV-DAG: %[[#twelve:]] = OpConstant %[[#i32]] 12 ; CHECK-SPIRV-DAG: %[[#const_i32x3_ptr:]] = OpTypePointer UniformConstant %[[#i32x3]] -; CHECK-SPIRV: %[[#test_arr2:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] -; CHECK-SPIRV: %[[#test_arr:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] +; CHECK-SPIRV-DAG: %[[#test_arr1:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] +; CHECK-SPIRV-DAG: %[[#test_arr2:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] ; CHECK-SPIRV-DAG: %[[#i32x3_ptr:]] = OpTypePointer Function %[[#i32x3]] -; CHECK-SPIRV: %[[#arr:]] = OpVariable %[[#i32x3_ptr]] Function +; CHECK-SPIRV: %[[#arr1:]] = OpVariable %[[#i32x3_ptr]] Function ; CHECK-SPIRV: %[[#arr2:]] = OpVariable %[[#i32x3_ptr]] Function -; CHECK-SPIRV-32: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#twelve]] Aligned 4 +; CHECK-SPIRV-32: OpCopyMemorySized %[[#arr1]] %[[#test_arr1]] %[[#twelve]] Aligned 4 ; CHECK-SPIRV-32: OpCopyMemorySized %[[#arr2]] %[[#test_arr2]] %[[#twelve]] Aligned 4 ; CHECK-SPIRV-64: %[[#twelvezext1:]] = OpUConvert %[[#i64:]] %[[#twelve:]] -; CHECK-SPIRV-64: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#twelvezext1]] Aligned 4 +; CHECK-SPIRV-64: OpCopyMemorySized %[[#arr1]] %[[#test_arr1]] %[[#twelvezext1]] Aligned 4 ; CHECK-SPIRV-64: %[[#twelvezext2:]] = OpUConvert %[[#i64:]] %[[#twelve:]] ; CHECK-SPIRV-64: OpCopyMemorySized %[[#arr2]] %[[#test_arr2]] %[[#twelvezext2]] Aligned 4 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll index adf73fe153de..62b09f6fe685 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll @@ -329,12 +329,12 @@ ; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64 ; CHECK-SPIRV-DAG: %[[#false:]] = OpConstantFalse %[[#bool]] +; CHECK-SPIRV-DAG: %[[#int_32:]] = OpConstant %[[#int]] 32 ; CHECK-SPIRV-DAG: %[[#ScopeSubgroup:]] = OpConstant %[[#int]] 3 ; CHECK-SPIRV-DAG: %[[#char_0:]] = OpConstant %[[#char]] 0 ; CHECK-SPIRV-DAG: %[[#char_10:]] = OpConstant %[[#char]] 10 ; CHECK-SPIRV-DAG: %[[#short_0:]] = OpConstant %[[#short]] 0 ; CHECK-SPIRV-DAG: %[[#int_0:]] = OpConstant %[[#int]] 0 -; CHECK-SPIRV-DAG: %[[#int_32:]] = OpConstant %[[#int]] 32 ; CHECK-SPIRV-DAG: %[[#long_0:]] = OpConstantNull %[[#long]] ; CHECK-SPIRV-DAG: %[[#half_0:]] = OpConstant %[[#half]] 0 ; CHECK-SPIRV-DAG: %[[#float_0:]] = OpConstant %[[#float]] 0 diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll index f72334bd7752..90bac50507c0 100644 --- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll +++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll @@ -4,10 +4,10 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0 -; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123 -; CHECK: %[[TyPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt]] -; CHECK: %[[VarId:.*]] = OpVariable %[[TyPtr]] {{[a-zA-Z]+}} %[[ConstInt]] +; CHECK-DAG: %[[TyInt:.*]] = OpTypeInt 8 0 +; CHECK-DAG: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123 +; CHECK-DAG: %[[TyPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt]] +; CHECK-DAG: %[[VarId:.*]] = OpVariable %[[TyPtr]] {{[a-zA-Z]+}} %[[ConstInt]] @0 = addrspace(1) global i8 123 diff --git a/llvm/test/CodeGen/Thumb2/bf16-instructions.ll b/llvm/test/CodeGen/Thumb2/bf16-instructions.ll index 5de7afca25b8..786e35517fd7 100644 --- a/llvm/test/CodeGen/Thumb2/bf16-instructions.ll +++ b/llvm/test/CodeGen/Thumb2/bf16-instructions.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP -; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabihf -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP +; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabihf -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP,CHECK-FPNO64 +; RUN: llc < %s -mtriple thumbv8.1m.main-none-eabihf -mattr=+fullfp16,+fp64 | FileCheck %s --check-prefixes=CHECK,CHECK-FP,CHECK-FP64 define bfloat @test_fadd(bfloat %a, bfloat %b) { ; CHECK-NOFP-LABEL: test_fadd: @@ -259,9 +260,8 @@ define void @test_truncstore64(double %a, ptr %b) { ; CHECK-FP-NEXT: .save {r4, lr} ; CHECK-FP-NEXT: push {r4, lr} ; CHECK-FP-NEXT: mov r4, r0 -; CHECK-FP-NEXT: vmov r0, r1, d0 -; CHECK-FP-NEXT: bl __aeabi_d2f -; CHECK-FP-NEXT: lsrs r0, r0, #16 +; CHECK-FP-NEXT: bl __truncdfbf2 +; CHECK-FP-NEXT: vmov r0, s0 ; CHECK-FP-NEXT: strh r0, [r4] ; CHECK-FP-NEXT: pop {r4, pc} %r = fptrunc double %a to bfloat @@ -312,15 +312,23 @@ define double @test_loadext64(ptr %a) { ; CHECK-NOFP-NEXT: bl __aeabi_f2d ; CHECK-NOFP-NEXT: pop {r7, pc} ; -; CHECK-FP-LABEL: test_loadext64: -; CHECK-FP: @ %bb.0: -; CHECK-FP-NEXT: .save {r7, lr} -; CHECK-FP-NEXT: push {r7, lr} -; CHECK-FP-NEXT: ldrh r0, [r0] -; CHECK-FP-NEXT: lsls r0, r0, #16 -; CHECK-FP-NEXT: bl __aeabi_f2d -; CHECK-FP-NEXT: vmov d0, r0, r1 -; CHECK-FP-NEXT: pop {r7, pc} +; CHECK-FPNO64-LABEL: test_loadext64: +; CHECK-FPNO64: @ %bb.0: +; CHECK-FPNO64-NEXT: .save {r7, lr} +; CHECK-FPNO64-NEXT: push {r7, lr} +; CHECK-FPNO64-NEXT: ldrh r0, [r0] +; CHECK-FPNO64-NEXT: lsls r0, r0, #16 +; CHECK-FPNO64-NEXT: bl __aeabi_f2d +; CHECK-FPNO64-NEXT: vmov d0, r0, r1 +; CHECK-FPNO64-NEXT: pop {r7, pc} +; +; CHECK-FP64-LABEL: test_loadext64: +; CHECK-FP64: @ %bb.0: +; CHECK-FP64-NEXT: ldrh r0, [r0] +; CHECK-FP64-NEXT: lsls r0, r0, #16 +; CHECK-FP64-NEXT: vmov s0, r0 +; CHECK-FP64-NEXT: vcvt.f64.f32 d0, s0 +; CHECK-FP64-NEXT: bx lr %r = load bfloat, ptr %a %d = fpext bfloat %r to double ret double %d @@ -1374,10 +1382,7 @@ define bfloat @test_fptrunc_double(double %a) { ; CHECK-FP: @ %bb.0: ; CHECK-FP-NEXT: .save {r7, lr} ; CHECK-FP-NEXT: push {r7, lr} -; CHECK-FP-NEXT: vmov r0, r1, d0 -; CHECK-FP-NEXT: bl __aeabi_d2f -; CHECK-FP-NEXT: lsrs r0, r0, #16 -; CHECK-FP-NEXT: vmov.f16 s0, r0 +; CHECK-FP-NEXT: bl __truncdfbf2 ; CHECK-FP-NEXT: vmov.f16 r0, s0 ; CHECK-FP-NEXT: vmov s0, r0 ; CHECK-FP-NEXT: pop {r7, pc} @@ -1410,15 +1415,23 @@ define double @test_fpext_double(bfloat %a) { ; CHECK-NOFP-NEXT: bl __aeabi_f2d ; CHECK-NOFP-NEXT: pop {r7, pc} ; -; CHECK-FP-LABEL: test_fpext_double: -; CHECK-FP: @ %bb.0: -; CHECK-FP-NEXT: .save {r7, lr} -; CHECK-FP-NEXT: push {r7, lr} -; CHECK-FP-NEXT: vmov r0, s0 -; CHECK-FP-NEXT: lsls r0, r0, #16 -; CHECK-FP-NEXT: bl __aeabi_f2d -; CHECK-FP-NEXT: vmov d0, r0, r1 -; CHECK-FP-NEXT: pop {r7, pc} +; CHECK-FPNO64-LABEL: test_fpext_double: +; CHECK-FPNO64: @ %bb.0: +; CHECK-FPNO64-NEXT: .save {r7, lr} +; CHECK-FPNO64-NEXT: push {r7, lr} +; CHECK-FPNO64-NEXT: vmov r0, s0 +; CHECK-FPNO64-NEXT: lsls r0, r0, #16 +; CHECK-FPNO64-NEXT: bl __aeabi_f2d +; CHECK-FPNO64-NEXT: vmov d0, r0, r1 +; CHECK-FPNO64-NEXT: pop {r7, pc} +; +; CHECK-FP64-LABEL: test_fpext_double: +; CHECK-FP64: @ %bb.0: +; CHECK-FP64-NEXT: vmov r0, s0 +; CHECK-FP64-NEXT: lsls r0, r0, #16 +; CHECK-FP64-NEXT: vmov s0, r0 +; CHECK-FP64-NEXT: vcvt.f64.f32 d0, s0 +; CHECK-FP64-NEXT: bx lr %r = fpext bfloat %a to double ret double %r } diff --git a/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll b/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll index 67fd59ed4c26..ed3dcad227bc 100644 --- a/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll +++ b/llvm/test/CodeGen/X86/2011-06-03-x87chain.ll @@ -30,9 +30,9 @@ entry: ret float %conv } -define void @PR17495() { +define void @PR17495(i1 %arg) { entry: - br i1 undef, label %while.end, label %while.body + br i1 %arg, label %while.end, label %while.body while.body: ; preds = %while.body, %entry %x.1.copyload = load i24, ptr undef, align 1 diff --git a/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll b/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll index 22bf4581c6b4..49de5091f0e5 100644 --- a/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll +++ b/llvm/test/CodeGen/X86/2020_12_02_decrementing_loop.ll @@ -165,7 +165,7 @@ failure: ; preds = %backedge unreachable } -define void @test_04() { +define void @test_04(i32 %arg) { ; CHECK-LABEL: test_04: ; CHECK: ## %bb.0: ## %bb ; CHECK-NEXT: ud2 @@ -175,7 +175,7 @@ bb: bb1: ; preds = %bb10, %bb %tmp = phi i64 [ 1, %bb ], [ %tmp2, %bb10 ] %tmp2 = add nuw nsw i64 %tmp, 1 - br i1 undef, label %bb21, label %bb7 + br i1 poison, label %bb21, label %bb7 bb7: ; preds = %bb1 %tmp8 = add nsw i64 %tmp, -1 @@ -187,7 +187,7 @@ bb10: ; preds = %bb16 br label %bb1 bb11: ; preds = %bb16, %bb7 - switch i32 undef, label %bb19 [ + switch i32 %arg, label %bb19 [ i32 0, label %bb17 i32 1, label %bb16 i32 2, label %bb15 @@ -205,7 +205,7 @@ bb15: ; preds = %bb11 unreachable bb16: ; preds = %bb11 - br i1 undef, label %bb10, label %bb11 + br i1 poison, label %bb10, label %bb11 bb17: ; preds = %bb11 unreachable diff --git a/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll b/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll index 86874b14b361..faa119cd037f 100644 --- a/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-combine-undef.ll @@ -5,13 +5,13 @@ define void @undef_2phi(ptr%buf) { ; CHECK-LABEL: @undef_2phi( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) -; CHECK-NEXT: br i1 undef, label [[L2]], label [[L3:%.*]] +; CHECK-NEXT: br i1 poison, label [[L2]], label [[L3:%.*]] ; CHECK: l2: ; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ] -; CHECK-NEXT: br i1 undef, label [[L3]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 poison, label [[L3]], label [[EXIT:%.*]] ; CHECK: l3: ; CHECK-NEXT: [[TMP2:%.*]] = phi x86_amx [ [[TMP1]], [[L2]] ], [ [[T1]], [[L1]] ] ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP2]]) @@ -20,16 +20,16 @@ define void @undef_2phi(ptr%buf) { ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 poison, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %l3 + br i1 poison, label %l2, label %l3 l2: - %t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ] - br i1 undef, label %l3, label %exit + %t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ] + br i1 poison, label %l3, label %exit l3: %t4 = phi <256 x i32> [ %t3, %l2], [ %t2, %l1 ] @@ -45,10 +45,10 @@ define void @foo_undef(ptr%buf) { ; CHECK-LABEL: @foo_undef( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) -; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]] ; CHECK: l2: ; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ] ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]]) @@ -57,15 +57,15 @@ define void @foo_undef(ptr%buf) { ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 poison, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %exit + br i1 poison, label %l2, label %exit l2: - %t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ] + %t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ] %t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3) call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr %buf, i64 1024, x86_amx %t4) br label %exit @@ -78,10 +78,10 @@ define void @foo_zero(ptr%buf) { ; CHECK-LABEL: @foo_zero( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) -; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]] ; CHECK: l2: ; CHECK-NEXT: [[TMP1:%.*]] = phi x86_amx [ [[TMP0]], [[ENTRY:%.*]] ], [ [[T1]], [[L1]] ] ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP1]]) @@ -90,12 +90,12 @@ define void @foo_zero(ptr%buf) { ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 poison, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %exit + br i1 poison, label %l2, label %exit l2: %t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ] @@ -112,14 +112,14 @@ define void @foo_vrow(ptr%buf, i16 %row) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64 ; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64 -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 [[ROW:%.*]], i16 32) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 32, ptr [[TMP1]], i64 32, x86_amx [[T1]]) ; CHECK-NEXT: [[TMP3:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024 -; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]] ; CHECK: l2: -; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP3]], [[L1]] ] +; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP3]], [[L1]] ] ; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024 ; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 [[ROW]], i16 32, ptr [[TMP0]], i64 32) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 [[ROW]], i16 32, ptr [[BUF:%.*]], i64 1024, x86_amx [[TMP5]]) @@ -128,15 +128,15 @@ define void @foo_vrow(ptr%buf, i16 %row) { ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 poison, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 %row, i16 32) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %exit + br i1 poison, label %l2, label %exit l2: - %t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ] + %t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ] %t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3) call void @llvm.x86.tilestored64.internal(i16 %row, i16 32, ptr %buf, i64 1024, x86_amx %t4) br label %exit @@ -150,13 +150,13 @@ define void @foo_vcol(ptr%buf, i16 %col) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64 ; CHECK-NEXT: [[TMP1:%.*]] = alloca <256 x i32>, align 64 -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 [[COL:%.*]]) ; CHECK-NEXT: [[TMP3:%.*]] = sext i16 [[COL]] to i64 ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 [[COL]], ptr [[TMP1]], i64 [[TMP3]], x86_amx [[T1]]) ; CHECK-NEXT: [[TMP4:%.*]] = load <256 x i32>, ptr [[TMP1]], align 1024 -; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]] ; CHECK: l2: ; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ zeroinitializer, [[ENTRY:%.*]] ], [ [[TMP4]], [[L1]] ] ; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[TMP0]], align 1024 @@ -168,12 +168,12 @@ define void @foo_vcol(ptr%buf, i16 %col) { ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 poison, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 %col) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %exit + br i1 poison, label %l2, label %exit l2: %t3 = phi <256 x i32> [ zeroinitializer, %entry ], [ %t2, %l1 ] @@ -189,29 +189,29 @@ define void @noshape(ptr%buf) { ; CHECK-LABEL: @noshape( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64 -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]]) ; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024 -; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]] ; CHECK: l2: -; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ] +; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ] ; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[BUF:%.*]], align 1024 ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 poison, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %exit + br i1 poison, label %l2, label %exit l2: - %t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ] + %t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ] %t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3) %t5 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t4) store <256 x i32> %t5, ptr %buf @@ -225,14 +225,14 @@ define void @noshape2(ptr%buf) { ; CHECK-LABEL: @noshape2( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64 -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 poison, label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]]) ; CHECK-NEXT: [[TMP2:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024 -; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 poison, label [[L2]], label [[EXIT:%.*]] ; CHECK: l2: -; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ] +; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ poison, [[ENTRY:%.*]] ], [ [[TMP2]], [[L1]] ] ; CHECK-NEXT: [[T6:%.*]] = call <256 x i32> @llvm.abs.v256i32(<256 x i32> [[T3]], i1 true) ; CHECK-NEXT: store <256 x i32> [[T6]], ptr [[BUF:%.*]], align 1024 ; CHECK-NEXT: br label [[EXIT]] @@ -240,15 +240,15 @@ define void @noshape2(ptr%buf) { ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 poison, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %exit + br i1 poison, label %l2, label %exit l2: - %t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ] + %t3 = phi <256 x i32> [ poison, %entry ], [ %t2, %l1 ] %t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3) %t5 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t4) %t6 = call <256 x i32> @llvm.abs.v256i32(<256 x i32> %t5, i1 1) diff --git a/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll b/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll index b2eb5fd915b9..b70668f7a3de 100644 --- a/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll +++ b/llvm/test/CodeGen/X86/AMX/lat-combine-amx-bitcast.ll @@ -18,14 +18,14 @@ wrapper_entry: ; Cases where amxcast can be combined across bb ; %5 and %6 is combined together since %goodphi's incoming is phi or amxcast -define void @combine_amx_cast_and_phi() { +define void @combine_amx_cast_and_phi(i1 %arg) { ; CHECK-LABEL: @combine_amx_cast_and_phi( ; CHECK-NEXT: wrapper_entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64 ; CHECK-NEXT: [[TMP1:%.*]] = alloca <616 x i8>, align 64 ; CHECK-NEXT: [[TMP2:%.*]] = alloca <110 x i32>, align 64 ; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] ; CHECK: for.body.i.lr.ph.i: ; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP2]], align 512 ; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP2]], i64 40) @@ -43,7 +43,7 @@ define void @combine_amx_cast_and_phi() { wrapper_entry: %0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) %tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0) - br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i + br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i for.body.i.lr.ph.i: ; preds = %wrapper_entry %1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef) @@ -62,7 +62,7 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, ; Cases where amxcast can't be combined across bb ; %5 and %6 is not combined together since %evilphi's incoming is not phi or amxcast -define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) { +define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp, i1 %arg) { ; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi( ; CHECK-NEXT: wrapper_entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64 @@ -71,7 +71,7 @@ define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) { ; CHECK-NEXT: [[TMP3:%.*]] = alloca <616 x i8>, align 64 ; CHECK-NEXT: [[TMP4:%.*]] = alloca <110 x i32>, align 64 ; CHECK-NEXT: [[TMP5:%.*]] = add <110 x i32> [[TMP:%.*]], [[TMP]] -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] ; CHECK: for.body.i.lr.ph.i: ; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP4]], align 512 ; CHECK-NEXT: [[TMP7:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP4]], i64 40) @@ -92,7 +92,7 @@ define void @fail_to_combine_amx_cast_and_phi(<110 x i32> %tmp) { ; wrapper_entry: %0 = add <110 x i32> %tmp, %tmp - br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i + br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i for.body.i.lr.ph.i: ; preds = %wrapper_entry %1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef) @@ -111,7 +111,7 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, ; Cases where amxcast can't be combined across bb ; %5 and %6 is not combined together since %evilphi's user aka %evilphi2 is not inside phi web. -define void @fail_to_combine_amx_cast_and_phi2() { +define void @fail_to_combine_amx_cast_and_phi2(i1 %arg) { ; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi2( ; CHECK-NEXT: wrapper_entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64 @@ -123,7 +123,7 @@ define void @fail_to_combine_amx_cast_and_phi2() { ; CHECK-NEXT: [[TMP6:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP5]], i64 40, x86_amx [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = load <110 x i32>, ptr [[TMP5]], align 512 -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] ; CHECK: for.body.i.lr.ph.i: ; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP4]], align 512 ; CHECK-NEXT: [[TMP10:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP4]], i64 40) @@ -134,13 +134,13 @@ define void @fail_to_combine_amx_cast_and_phi2() { ; CHECK-NEXT: [[TMP15:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx [[TMP10]], x86_amx [[TMP12]], x86_amx [[TMP14]]) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP1]], i64 40, x86_amx [[TMP15]]) ; CHECK-NEXT: [[TMP17:%.*]] = load <110 x i32>, ptr [[TMP1]], align 512 -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 [[ARG]], label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]] ; CHECK: for.cond.cleanup.i.i: ; CHECK-NEXT: [[GOODPHI:%.*]] = phi <110 x i32> [ [[TMP8]], [[WRAPPER_ENTRY:%.*]] ], [ [[TMP17]], [[FOR_BODY_I_LR_PH_I]] ] ; CHECK-NEXT: store <110 x i32> [[GOODPHI]], ptr [[TMP0]], align 512 ; CHECK-NEXT: [[TMP19:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP0]], i64 40) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP19]]) -; CHECK-NEXT: br i1 undef, label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]] +; CHECK-NEXT: br i1 [[ARG]], label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]] ; CHECK: exit: ; CHECK-NEXT: [[EVILPHI2:%.*]] = phi <110 x i32> [ [[GOODPHI]], [[FOR_COND_CLEANUP_I_I]] ], [ [[TMP17]], [[FOR_BODY_I_LR_PH_I]] ] ; CHECK-NEXT: store <110 x i32> [[EVILPHI2]], ptr undef, align 512 @@ -149,7 +149,7 @@ define void @fail_to_combine_amx_cast_and_phi2() { wrapper_entry: %0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) %tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0) - br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i + br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i for.body.i.lr.ph.i: ; preds = %wrapper_entry %1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef) @@ -157,27 +157,27 @@ for.body.i.lr.ph.i: ; preds = %wrapper_entry %3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef) %4 = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx %1, x86_amx %2, x86_amx %3) %5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4) - br i1 undef, label %for.cond.cleanup.i.i, label %exit + br i1 %arg, label %for.cond.cleanup.i.i, label %exit for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, %wrapper_entry %goodphi = phi <110 x i32> [ %tmp, %wrapper_entry ], [ %5, %for.body.i.lr.ph.i ] %6 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %goodphi) call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %6) - br i1 undef, label %exit, label %for.body.i.lr.ph.i + br i1 %arg, label %exit, label %for.body.i.lr.ph.i exit: %evilphi2 = phi <110 x i32> [ %goodphi, %for.cond.cleanup.i.i ], [ %5, %for.body.i.lr.ph.i ] store <110 x i32> %evilphi2, ptr undef, align 512 ret void } -define void @fail_to_combine_amx_cast_and_phi_due_to_const_value() { +define void @fail_to_combine_amx_cast_and_phi_due_to_const_value(i1 %arg) { ; CHECK-LABEL: @fail_to_combine_amx_cast_and_phi_due_to_const_value( ; CHECK-NEXT: wrapper_entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64 ; CHECK-NEXT: [[TMP1:%.*]] = alloca <616 x i8>, align 64 ; CHECK-NEXT: [[TMP2:%.*]] = alloca <110 x i32>, align 64 ; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 11, i16 40) -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] ; CHECK: for.body.i.lr.ph.i: ; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP2]], align 512 ; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP2]], i64 40) @@ -193,7 +193,7 @@ define void @fail_to_combine_amx_cast_and_phi_due_to_const_value() { ; CHECK-NEXT: ret void ; wrapper_entry: - br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i + br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i for.body.i.lr.ph.i: ; preds = %wrapper_entry %0 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef) @@ -213,14 +213,14 @@ for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, ; Cases where amxcast can be combined across bb ; When optimizeAMXCastFromPhi process %6 and %goodphi, %goodphi2 is outside the phi-web, so the optimization stop ; When optimizeAMXCastFromPhi process %7 and %goodphi2, the optimization continue. -define void @combine_amx_cast_and_multiple_phi() { +define void @combine_amx_cast_and_multiple_phi(i1 %arg) { ; CHECK-LABEL: @combine_amx_cast_and_multiple_phi( ; CHECK-NEXT: wrapper_entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64 ; CHECK-NEXT: [[TMP1:%.*]] = alloca <616 x i8>, align 64 ; CHECK-NEXT: [[TMP2:%.*]] = alloca <110 x i32>, align 64 ; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] ; CHECK: for.body.i.lr.ph.i: ; CHECK-NEXT: store <110 x i32> undef, ptr [[TMP2]], align 512 ; CHECK-NEXT: [[TMP5:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr [[TMP2]], i64 40) @@ -229,11 +229,11 @@ define void @combine_amx_cast_and_multiple_phi() { ; CHECK-NEXT: store <560 x i8> undef, ptr [[TMP0]], align 1024 ; CHECK-NEXT: [[TMP9:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 14, i16 40, ptr [[TMP0]], i64 40) ; CHECK-NEXT: [[TMP10:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx [[TMP5]], x86_amx [[TMP7]], x86_amx [[TMP9]]) -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 [[ARG]], label [[FOR_COND_CLEANUP_I_I]], label [[EXIT:%.*]] ; CHECK: for.cond.cleanup.i.i: ; CHECK-NEXT: [[TMP11:%.*]] = phi x86_amx [ [[TMP3]], [[WRAPPER_ENTRY:%.*]] ], [ [[TMP10]], [[FOR_BODY_I_LR_PH_I]] ] ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP11]]) -; CHECK-NEXT: br i1 undef, label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]] +; CHECK-NEXT: br i1 [[ARG]], label [[EXIT]], label [[FOR_BODY_I_LR_PH_I]] ; CHECK: exit: ; CHECK-NEXT: [[TMP12:%.*]] = phi x86_amx [ [[TMP11]], [[FOR_COND_CLEANUP_I_I]] ], [ [[TMP10]], [[FOR_BODY_I_LR_PH_I]] ] ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP12]]) @@ -242,7 +242,7 @@ define void @combine_amx_cast_and_multiple_phi() { wrapper_entry: %0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) %tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0) - br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i + br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i for.body.i.lr.ph.i: ; preds = %wrapper_entry %1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> undef) @@ -250,13 +250,13 @@ for.body.i.lr.ph.i: ; preds = %wrapper_entry %3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef) %4 = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx %1, x86_amx %2, x86_amx %3) %5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4) - br i1 undef, label %for.cond.cleanup.i.i, label %exit + br i1 %arg, label %for.cond.cleanup.i.i, label %exit for.cond.cleanup.i.i: ; preds = %for.body.i.lr.ph.i, %wrapper_entry %goodphi = phi <110 x i32> [ %tmp, %wrapper_entry ], [ %5, %for.body.i.lr.ph.i ] %6 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %goodphi) call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %6) - br i1 undef, label %exit, label %for.body.i.lr.ph.i + br i1 %arg, label %exit, label %for.body.i.lr.ph.i exit: %evilphi2 = phi <110 x i32> [ %goodphi, %for.cond.cleanup.i.i ], [ %5, %for.body.i.lr.ph.i ] %7 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %evilphi2) @@ -265,7 +265,7 @@ exit: } ; Currently we are not able to delete DeadPHICycle, later we will handle with them -define void @combine_amx_cast_and_phi_in_a_circle() { +define void @combine_amx_cast_and_phi_in_a_circle(i1 %arg) { ; CHECK-LABEL: @combine_amx_cast_and_phi_in_a_circle( ; CHECK-NEXT: wrapper_entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <110 x i32>, align 64 @@ -284,7 +284,7 @@ define void @combine_amx_cast_and_phi_in_a_circle() { ; CHECK-NEXT: [[TMP11:%.*]] = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx [[TMP6]], x86_amx [[TMP8]], x86_amx [[TMP10]]) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr [[TMP0]], i64 40, x86_amx [[TMP11]]) ; CHECK-NEXT: [[TMP13:%.*]] = load <110 x i32>, ptr [[TMP0]], align 512 -; CHECK-NEXT: br i1 undef, label [[BB2:%.*]], label [[BB3:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[BB2:%.*]], label [[BB3:%.*]] ; CHECK: bb2: ; CHECK-NEXT: [[TMP14:%.*]] = phi x86_amx [ [[TMP15:%.*]], [[BB3]] ], [ [[TMP11]], [[BB1]] ] ; CHECK-NEXT: [[GOODPHI:%.*]] = phi <110 x i32> [ [[EVILPHI2:%.*]], [[BB3]] ], [ [[TMP13]], [[BB1]] ] @@ -294,7 +294,7 @@ define void @combine_amx_cast_and_phi_in_a_circle() { ; CHECK-NEXT: [[TMP15]] = phi x86_amx [ [[TMP14]], [[BB2]] ], [ [[TMP11]], [[BB1]] ] ; CHECK-NEXT: [[EVILPHI2]] = phi <110 x i32> [ [[GOODPHI]], [[BB2]] ], [ [[TMP13]], [[BB1]] ] ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP15]]) -; CHECK-NEXT: br i1 undef, label [[BB2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 [[ARG]], label [[BB2]], label [[EXIT:%.*]] ; CHECK: exit: ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx [[TMP15]]) ; CHECK-NEXT: ret void @@ -310,7 +310,7 @@ bb1: ; preds = %wrapper_entry %3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef) %4 = call x86_amx @llvm.x86.tdpbssd.internal(i16 11, i16 40, i16 56, x86_amx %1, x86_amx %2, x86_amx %3) %5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4) - br i1 undef, label %bb2, label %bb3 + br i1 %arg, label %bb2, label %bb3 bb2: ; preds = %bb1, %wrapper_entry %goodphi = phi <110 x i32> [ %evilphi2, %bb3], [ %5, %bb1 ] @@ -321,19 +321,19 @@ bb3: %evilphi2 = phi <110 x i32> [ %goodphi, %bb2 ], [ %5, %bb1 ] %7 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %evilphi2) call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %7) - br i1 undef, label %bb2, label %exit + br i1 %arg, label %bb2, label %exit exit: %8 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %evilphi2) call void @llvm.x86.tilestored64.internal(i16 11, i16 40, ptr undef, i64 undef, x86_amx %8) ret void } -define void @eliminate_unused_phi_and_cast() { +define void @eliminate_unused_phi_and_cast(i1 %arg) { ; CHECK-LABEL: @eliminate_unused_phi_and_cast( ; CHECK-NEXT: wrapper_entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <560 x i8>, align 64 ; CHECK-NEXT: [[TMP1:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) -; CHECK-NEXT: br i1 undef, label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[FOR_COND_CLEANUP_I_I:%.*]], label [[FOR_BODY_I_LR_PH_I:%.*]] ; CHECK: for.body.i.lr.ph.i: ; CHECK-NEXT: [[TMP2:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 56, ptr undef, i64 undef) ; CHECK-NEXT: [[TMP3:%.*]] = call x86_amx @llvm.x86.tileloadd64.internal(i16 14, i16 40, ptr undef, i64 undef) @@ -349,7 +349,7 @@ define void @eliminate_unused_phi_and_cast() { wrapper_entry: %0 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 40, ptr undef, i64 undef) %tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0) - br i1 undef, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i + br i1 %arg, label %for.cond.cleanup.i.i, label %for.body.i.lr.ph.i for.body.i.lr.ph.i: ; preds = %wrapper_entry %1 = call x86_amx @llvm.x86.tileloadd64.internal(i16 11, i16 56, ptr undef, i64 undef) diff --git a/llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll b/llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll index 391727d54a03..3a5b424540ff 100644 --- a/llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll +++ b/llvm/test/CodeGen/X86/AMX/lat-transform-amx-bitcast.ll @@ -317,16 +317,16 @@ define dso_local void @__tile_stored(ptr %0, i64 %1, ptr nocapture readonly byva ret void } -define void @dead_code(ptr%buf) { +define void @dead_code(ptr%buf, i1 %arg) { ; CHECK-LABEL: @dead_code( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = alloca <256 x i32>, align 64 -; CHECK-NEXT: br i1 undef, label [[L1:%.*]], label [[L2:%.*]] +; CHECK-NEXT: br i1 [[ARG:%.*]], label [[L1:%.*]], label [[L2:%.*]] ; CHECK: l1: ; CHECK-NEXT: [[T1:%.*]] = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) ; CHECK-NEXT: call void @llvm.x86.tilestored64.internal(i16 8, i16 32, ptr [[TMP0]], i64 32, x86_amx [[T1]]) ; CHECK-NEXT: [[TMP1:%.*]] = load <256 x i32>, ptr [[TMP0]], align 1024 -; CHECK-NEXT: br i1 undef, label [[L2]], label [[EXIT:%.*]] +; CHECK-NEXT: br i1 [[ARG]], label [[L2]], label [[EXIT:%.*]] ; CHECK: l2: ; CHECK-NEXT: [[T3:%.*]] = phi <256 x i32> [ undef, [[ENTRY:%.*]] ], [ [[TMP1]], [[L1]] ] ; CHECK-NEXT: store <256 x i32> [[T3]], ptr [[BUF:%.*]], align 1024 @@ -335,12 +335,12 @@ define void @dead_code(ptr%buf) { ; CHECK-NEXT: ret void ; entry: - br i1 undef, label %l1, label %l2 + br i1 %arg, label %l1, label %l2 l1: %t1 = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 32) %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1) - br i1 undef, label %l2, label %exit + br i1 %arg, label %l2, label %exit l2: %t3 = phi <256 x i32> [ undef, %entry ], [ %t2, %l1 ] diff --git a/llvm/test/CodeGen/X86/StackColoring.ll b/llvm/test/CodeGen/X86/StackColoring.ll index 389d024dafd1..db3e7dcdfe2d 100644 --- a/llvm/test/CodeGen/X86/StackColoring.ll +++ b/llvm/test/CodeGen/X86/StackColoring.ll @@ -135,7 +135,7 @@ entry: %t3 = call i32 @foo(i32 %in, ptr %a3) %t4 = call i32 @foo(i32 %in, ptr %a3) call void @llvm.lifetime.end.p0(i64 -1, ptr %a3) - br i1 undef, label %bb2, label %bb3 + br i1 poison, label %bb2, label %bb3 bb2: call void @llvm.lifetime.start.p0(i64 -1, ptr %a4) %t11 = call i32 @foo(i32 %in, ptr %a4) diff --git a/llvm/test/CodeGen/X86/asm-label.ll b/llvm/test/CodeGen/X86/asm-label.ll index 05c37db532f8..2d3e7b624d35 100644 --- a/llvm/test/CodeGen/X86/asm-label.ll +++ b/llvm/test/CodeGen/X86/asm-label.ll @@ -12,15 +12,15 @@ ; SAVETEMP: jne {{.*}} <.LBB0_1> ; SAVETEMP-LABEL: <.LBB0_1>: -define void @foo() { +define void @foo(i1 %arg, i32 %arg2) { entry: - br i1 undef, label %land.lhs.true, label %if.end11 + br i1 %arg, label %land.lhs.true, label %if.end11 land.lhs.true: ; preds = %entry - br i1 undef, label %if.then, label %if.end11 + br i1 %arg, label %if.then, label %if.end11 if.then: ; preds = %land.lhs.true - br i1 undef, label %if.then9, label %if.end + br i1 %arg, label %if.then9, label %if.end if.then9: ; preds = %if.then br label %cleanup @@ -29,7 +29,7 @@ if.end: ; preds = %if.then br label %cleanup cleanup: ; preds = %if.end, %if.then9 - switch i32 undef, label %default [ + switch i32 %arg2, label %default [ i32 0, label %cleanup.cont i32 1, label %if.end11 ] diff --git a/llvm/test/CodeGen/X86/avx-select.ll b/llvm/test/CodeGen/X86/avx-select.ll index 7a33daf18be8..1b688c8cf9cc 100644 --- a/llvm/test/CodeGen/X86/avx-select.ll +++ b/llvm/test/CodeGen/X86/avx-select.ll @@ -84,7 +84,7 @@ head: %isneg = icmp slt <4 x i32> %v3, zeroinitializer %or0 = select <4 x i1> %isneg, <4 x i32> <i32 26146, i32 -1257, i32 -2, i32 -3052>, <4 x i32> <i32 -24947, i32 7802, i32 29242, i32 15858> %or1 = shufflevector <4 x i32> %or0, <4 x i32> <i32 29361, i32 -16094, i32 -3080, i32 -26286>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> - br i1 undef, label %exit, label %head + br i1 poison, label %exit, label %head exit: store <8 x i32> %or1, ptr addrspace(1) undef, align 32 diff --git a/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll b/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll new file mode 100644 index 000000000000..d7ad7b048c6d --- /dev/null +++ b/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll @@ -0,0 +1,85 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64 + +; VCVTTPD2DQS +define <8 x i32> @test_signed_v8i32_v8f64(<8 x double> %f) nounwind { +; CHECK-LABEL: test_signed_v8i32_v8f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2dqs %zmm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i32> @llvm.fptosi.sat.v8i32.v8f64(<8 x double> %f) + ret <8 x i32> %x +} + +; VCVTTPD2QQS +define <8 x i64> @test_signed_v8i64_v8f64(<8 x double> %f) nounwind { +; CHECK-LABEL: test_signed_v8i64_v8f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2qqs %zmm0, %zmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f64(<8 x double> %f) + ret <8 x i64> %x +} + +; VCVTTPD2UDQS +define <8 x i32> @test_unsigned_v8i32_v8f64(<8 x double> %f) nounwind { +; CHECK-LABEL: test_unsigned_v8i32_v8f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2udqs %zmm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i32> @llvm.fptoui.sat.v8i32.v8f64(<8 x double> %f) + ret <8 x i32> %x +} + +; VCVTTPD2UQQS +define <8 x i64> @test_unsigned_v8i64_v8f64(<8 x double> %f) nounwind { +; CHECK-LABEL: test_unsigned_v8i64_v8f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2uqqs %zmm0, %zmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f64(<8 x double> %f) + ret <8 x i64> %x +} + +; VCVTTPS2DQS +define <16 x i32> @test_signed_v16i32_v16f32(<16 x float> %f) nounwind { +; CHECK-LABEL: test_signed_v16i32_v16f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2dqs %zmm0, %zmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <16 x i32> @llvm.fptosi.sat.v16i32.v16f32(<16 x float> %f) + ret <16 x i32> %x +} + +; VCVTTPS2UDQS +define <16 x i32> @test_unsigned_v16i32_v16f32(<16 x float> %f) nounwind { +; CHECK-LABEL: test_unsigned_v16i32_v16f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2udqs %zmm0, %zmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <16 x i32> @llvm.fptoui.sat.v16i32.v16f32(<16 x float> %f) + ret <16 x i32> %x +} +; VCVTTPS2QQS +define <8 x i64> @test_signed_v8i64_v8f32(<8 x float> %f) nounwind { +; CHECK-LABEL: test_signed_v8i64_v8f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2qqs %ymm0, %zmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %f) + ret <8 x i64> %x +} + +; VCVTTPS2UQQS +define <8 x i64> @test_unsigned_v8i64_v8f32(<8 x float> %f) nounwind { +; CHECK-LABEL: test_unsigned_v8i64_v8f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2uqqs %ymm0, %zmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %f) + ret <8 x i64> %x +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; X64: {{.*}} +; X86: {{.*}} diff --git a/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll b/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll index 494e4bc8e068..a2f167e94cc2 100644 --- a/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll +++ b/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X86 -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X64 ; ; 32-bit float to signed integer @@ -112,3 +112,157 @@ define i64 @test_signed_i64_f64(double %f) nounwind { %x = call i64 @llvm.fptosi.sat.i64.f64(double %f) ret i64 %x } + +; VCVTTPD2DQS +define <2 x i32> @test_signed_v2i32_v2f64(<2 x double> %d) nounwind { +; CHECK-LABEL: test_signed_v2i32_v2f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2dqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %d) + ret <2 x i32> %x +} + +define <4 x i32> @test_signed_v4i32_v4f64(<4 x double> %f) nounwind { +; CHECK-LABEL: test_signed_v4i32_v4f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2dqs %ymm0, %xmm0 +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %f) + ret <4 x i32> %x +} + +; VCVTTPD2QQS +define <2 x i64> @test_signed_v2i64_v2f64(<2 x double> %f) nounwind { +; CHECK-LABEL: test_signed_v2i64_v2f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2qqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double> %f) + ret <2 x i64> %x +} + +define <4 x i64> @test_signed_v4i64_v4f64(<4 x double> %f) nounwind { +; CHECK-LABEL: test_signed_v4i64_v4f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2qqs %ymm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f64(<4 x double> %f) + ret <4 x i64> %x +} + +; VCVTTPD2UDQS +define <2 x i32> @test_unsigned_v2i32_v2f64(<2 x double> %d) nounwind { +; CHECK-LABEL: test_unsigned_v2i32_v2f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2udqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %d) + ret <2 x i32> %x +} + +define <4 x i32> @test_unsigned_v4i32_v4f64(<4 x double> %f) nounwind { +; CHECK-LABEL: test_unsigned_v4i32_v4f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2udqs %ymm0, %xmm0 +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %f) + ret <4 x i32> %x +} + +; VCVTTPD2UQQS +define <2 x i64> @test_unsigned_v2i64_v2f64(<2 x double> %f) nounwind { +; CHECK-LABEL: test_unsigned_v2i64_v2f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2uqqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f64(<2 x double> %f) + ret <2 x i64> %x +} + +define <4 x i64> @test_unsigned_v4i64_v4f64(<4 x double> %f) nounwind { +; CHECK-LABEL: test_unsigned_v4i64_v4f64: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttpd2uqqs %ymm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f64(<4 x double> %f) + ret <4 x i64> %x +} + +; VCVTTPS2DQS +define <4 x i32> @test_signed_v4i32_v4f32(<4 x float> %f) nounwind { +; CHECK-LABEL: test_signed_v4i32_v4f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2dqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %f) + ret <4 x i32> %x +} + +define <8 x i32> @test_signed_v8i32_v8f32(<8 x float> %f) nounwind { +; CHECK-LABEL: test_signed_v8i32_v8f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2dqs %ymm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i32> @llvm.fptosi.sat.v8i32.v8f32(<8 x float> %f) + ret <8 x i32> %x +} + +; VCVTTPS2UDQS +define <4 x i32> @test_unsigned_v4i32_v4f32(<4 x float> %f) nounwind { +; CHECK-LABEL: test_unsigned_v4i32_v4f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2udqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %f) + ret <4 x i32> %x +} + +define <8 x i32> @test_unsigned_v8i32_v8f32(<8 x float> %f) nounwind { +; CHECK-LABEL: test_unsigned_v8i32_v8f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2udqs %ymm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float> %f) + ret <8 x i32> %x +} + +; VCVTTPS2QQS +define <2 x i64> @test_signed_v2i64_v2f32(<2 x float> %f) nounwind { +; CHECK-LABEL: test_signed_v2i64_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2qqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float> %f) + ret <2 x i64> %x +} + +define <4 x i64> @test_signed_v4i64_v4f32(<4 x float> %f) nounwind { +; CHECK-LABEL: test_signed_v4i64_v4f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2qqs %xmm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f32(<4 x float> %f) + ret <4 x i64> %x +} + +; VCVTTPS2UQQS +define <2 x i64> @test_unsigned_v2i64_v2f32(<2 x float> %f) nounwind { +; CHECK-LABEL: test_unsigned_v2i64_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2uqqs %xmm0, %xmm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float> %f) + ret <2 x i64> %x +} + +define <4 x i64> @test_unsigned_v4i64_v4f32(<4 x float> %f) nounwind { +; CHECK-LABEL: test_unsigned_v4i64_v4f32: +; CHECK: # %bb.0: +; CHECK-NEXT: vcvttps2uqqs %xmm0, %ymm0 +; CHECK-NEXT: ret{{[l|q]}} + %x = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f32(<4 x float> %f) + ret <4 x i64> %x +} diff --git a/llvm/test/CodeGen/X86/avx512-i1test.ll b/llvm/test/CodeGen/X86/avx512-i1test.ll index 3cd733181599..d8683df5cbf7 100644 --- a/llvm/test/CodeGen/X86/avx512-i1test.ll +++ b/llvm/test/CodeGen/X86/avx512-i1test.ll @@ -21,20 +21,20 @@ define void @func() { ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jmp .LBB0_2 bb1: - br i1 undef, label %L_10, label %L_10 + br i1 poison, label %L_10, label %L_10 L_10: ; preds = %bb1, %bb1 - br i1 undef, label %L_30, label %bb56 + br i1 poison, label %L_30, label %bb56 bb56: ; preds = %L_10 br label %bb33 bb33: ; preds = %bb51, %bb56 %r111 = load i64, ptr undef, align 8 - br i1 undef, label %bb51, label %bb35 + br i1 poison, label %bb51, label %bb35 bb35: ; preds = %bb33 - br i1 undef, label %L_19, label %bb37 + br i1 poison, label %L_19, label %bb37 bb37: ; preds = %bb35 %r128 = and i64 %r111, 576460752303423488 @@ -43,7 +43,7 @@ bb37: ; preds = %bb35 L_19: ; preds = %bb37, %bb35 %"$V_S25.0" = phi i1 [ %phitmp, %bb37 ], [ true, %bb35 ] - br i1 undef, label %bb51, label %bb42 + br i1 poison, label %bb51, label %bb42 bb42: ; preds = %L_19 %r136 = select i1 %"$V_S25.0", ptr undef, ptr undef diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll index 675293410dfe..136913141305 100644 --- a/llvm/test/CodeGen/X86/block-placement.ll +++ b/llvm/test/CodeGen/X86/block-placement.ll @@ -312,7 +312,7 @@ exit: ret i32 %sum } -define void @unnatural_cfg1() { +define void @unnatural_cfg1(i1 %arg) { ; Test that we can handle a loop with an inner unnatural loop at the end of ; a function. This is a gross CFG reduced out of the single source GCC. ; CHECK-LABEL: unnatural_cfg1 @@ -327,7 +327,7 @@ loop.header: br label %loop.body1 loop.body1: - br i1 undef, label %loop.body3, label %loop.body2 + br i1 %arg, label %loop.body3, label %loop.body2 loop.body2: %ptr = load ptr, ptr undef, align 4 @@ -341,14 +341,14 @@ loop.body3: br i1 %comp, label %loop.body4, label %loop.body5 loop.body4: - br i1 undef, label %loop.header, label %loop.body5 + br i1 %arg, label %loop.header, label %loop.body5 loop.body5: %ptr2 = load ptr, ptr undef, align 4 br label %loop.body3 } -define void @unnatural_cfg2(ptr %p0, i32 %a0) { +define void @unnatural_cfg2(ptr %p0, i32 %a0, i1 %arg) { ; Test that we can handle a loop with a nested natural loop *and* an unnatural ; loop. This was reduced from a crash on block placement when run over ; single-source GCC. @@ -372,10 +372,10 @@ loop.header: loop.body1: %val0 = load ptr, ptr undef, align 4 - br i1 undef, label %loop.body2, label %loop.inner1.begin + br i1 %arg, label %loop.body2, label %loop.inner1.begin loop.body2: - br i1 undef, label %loop.body4, label %loop.body3 + br i1 %arg, label %loop.body4, label %loop.body3 loop.body3: %ptr1 = getelementptr inbounds i32, ptr %val0, i32 0 @@ -467,7 +467,7 @@ exit: ret i32 %merge } -define void @fpcmp_unanalyzable_branch(i1 %cond, double %a0) { +define void @fpcmp_unanalyzable_branch(i1 %cond, double %a0, i1 %arg) { ; This function's CFG contains an once-unanalyzable branch (une on floating ; points). As now it becomes analyzable, we should get best layout in which each ; edge in 'entry' -> 'entry.if.then_crit_edge' -> 'if.then' -> 'if.end' is @@ -493,7 +493,7 @@ entry.if.then_crit_edge: br label %if.then lor.lhs.false: - br i1 undef, label %if.end, label %exit + br i1 %arg, label %if.end, label %exit exit: %cmp.i = fcmp une double 0.000000e+00, %a0 @@ -516,7 +516,7 @@ declare i32 @f() declare i32 @g() declare i32 @h(i32 %x) -define i32 @test_global_cfg_break_profitability() { +define i32 @test_global_cfg_break_profitability(i1 %arg) { ; Check that our metrics for the profitability of a CFG break are global rather ; than local. A successor may be very hot, but if the current block isn't, it ; doesn't matter. Within this test the 'then' block is slightly warmer than the @@ -530,7 +530,7 @@ define i32 @test_global_cfg_break_profitability() { ; CHECK: ret entry: - br i1 undef, label %then, label %else, !prof !2 + br i1 %arg, label %then, label %else, !prof !2 then: %then.result = call i32 @f() @@ -600,7 +600,7 @@ cleanup: unreachable } -define void @test_unnatural_cfg_backwards_inner_loop() { +define void @test_unnatural_cfg_backwards_inner_loop(i1 %arg) { ; Test that when we encounter an unnatural CFG structure after having formed ; a chain for an inner loop which happened to be laid out backwards we don't ; attempt to merge onto the wrong end of the inner loop just because we find it @@ -612,7 +612,7 @@ define void @test_unnatural_cfg_backwards_inner_loop() { ; CHECK: %loop3 entry: - br i1 undef, label %loop2a, label %body + br i1 %arg, label %loop2a, label %body body: br label %loop2a @@ -692,7 +692,7 @@ exit: ret void } -define void @unanalyzable_branch_to_free_block(float %x) { +define void @unanalyzable_branch_to_free_block(float %x, i1 %arg) { ; Ensure that we can handle unanalyzable branches where the destination block ; gets selected as the best free block in the CFG. ; @@ -704,7 +704,7 @@ define void @unanalyzable_branch_to_free_block(float %x) { ; CHECK: %exit entry: - br i1 undef, label %a, label %b + br i1 %arg, label %a, label %b a: call i32 @f() diff --git a/llvm/test/CodeGen/X86/clobber_frame_ptr.ll b/llvm/test/CodeGen/X86/clobber_frame_ptr.ll index f6b38839d13c..e7ffc4752715 100644 --- a/llvm/test/CodeGen/X86/clobber_frame_ptr.ll +++ b/llvm/test/CodeGen/X86/clobber_frame_ptr.ll @@ -173,7 +173,7 @@ define ghccc void @test5() { ; CHECK-NEXT: .cfi_def_cfa %rsp, 8 ; CHECK-NEXT: jmp tail@PLT # TAILCALL entry: - br i1 undef, label %then, label %else + br i1 poison, label %then, label %else then: store i64 0, ptr undef @@ -186,4 +186,3 @@ else: exit: ret void } - diff --git a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll index c611e89f2786..f3070cd55903 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll +++ b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' %s -o - | FileCheck %s ; This file tests the different cases what are involved when codegen prepare ; tries to get sign/zero extension out of the way of addressing mode. @@ -9,14 +10,17 @@ target triple = "x86_64-apple-macosx" ; Check that we correctly promote both operands of the promotable add. -; CHECK-LABEL: @twoArgsPromotion -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64 -; CHECK: [[ARG2SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg2 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], [[ARG2SEXT]] -; CHECK: inttoptr i64 [[PROMOTED]] to ptr -; CHECK: ret define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) { - %add = add nsw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @twoArgsPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i32 [[ARG1]] to i64 +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i32 [[ARG2]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], [[PROMOTED2]] +; CHECK-NEXT: [[BASE:%.*]] = inttoptr i64 [[ADD]] to ptr +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[BASE]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, %arg2 %sextadd = sext i32 %add to i64 %base = inttoptr i64 %sextadd to ptr %res = load i8, ptr %base @@ -28,11 +32,16 @@ define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) { ; Otherwise, we will increase the number of instruction executed. ; (This is a heuristic of course, because the new sext could have been ; merged with something else.) -; CHECK-LABEL: @twoArgsNoPromotion -; CHECK: add nsw i32 %arg1, %arg2 -; CHECK: ret define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, ptr %base) { - %add = add nsw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @twoArgsNoPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i32 [[ADD]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, %arg2 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -41,11 +50,16 @@ define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, ptr %base) { ; Check that we do not promote when the related instruction does not have ; the nsw flag. -; CHECK-LABEL: @noPromotion -; CHECK-NOT: add i64 -; CHECK: ret define i8 @noPromotion(i32 %arg1, i32 %arg2, ptr %base) { - %add = add i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @noPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i32 [[ADD]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add i32 %arg1, %arg2 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -53,13 +67,16 @@ define i8 @noPromotion(i32 %arg1, i32 %arg2, ptr %base) { } ; Check that we correctly promote constant arguments. -; CHECK-LABEL: @oneArgPromotion -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotion(i32 %arg1, ptr %base) { - %add = add nsw i32 %arg1, 1 +; CHECK-LABEL: define i8 @oneArgPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i32 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, 1 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -67,14 +84,17 @@ define i8 @oneArgPromotion(i32 %arg1, ptr %base) { } ; Check that we are able to merge a sign extension with a zero extension. -; CHECK-LABEL: @oneArgPromotionZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionZExt(i8 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionZExt( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %zext = zext i8 %arg1 to i32 - %add = add nsw i32 %zext, 1 + %add = add nsw i32 %zext, 1 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -88,11 +108,14 @@ define i8 @oneArgPromotionZExt(i8 %arg1, ptr %base) { ; more thing in the addressing mode. Therefore the modification is ; rolled back. ; Still, this test case exercises the desired code path. -; CHECK-LABEL: @oneArgPromotionCstZExt -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 0, 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionCstZExt(ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionCstZExt( +; CHECK-SAME: ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 0, 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %cst = zext i16 undef to i32 %add = add nsw i32 %cst, 1 %sextadd = sext i32 %add to i64 @@ -103,15 +126,18 @@ define i8 @oneArgPromotionCstZExt(ptr %base) { ; Check that we do not promote truncate when we cannot determine the ; bits that are dropped. -; CHECK-LABEL: @oneArgPromotionBlockTrunc1 -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 %arg1 to i8 -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockTrunc1( +; CHECK-SAME: i32 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %trunc = trunc i32 %arg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -120,17 +146,20 @@ define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, ptr %base) { ; Check that we do not promote truncate when we cannot determine all the ; bits that are dropped. -; CHECK-LABEL: @oneArgPromotionBlockTrunc2 -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i16 %arg1 to i32 -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8 -; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockTrunc2( +; CHECK-SAME: i16 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i16 [[ARG1]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEXTARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i16 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -139,15 +168,18 @@ define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, ptr %base) { ; Check that we are able to promote truncate when we know all the bits ; that are dropped. -; CHECK-LABEL: @oneArgPromotionPassTruncKeepSExt -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionPassTruncKeepSExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i1 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -156,17 +188,19 @@ define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, ptr %base) { ; On X86 truncate are free. Check that we are able to promote the add ; to be used as addressing mode and that we insert a truncate for the other -; use. -; CHECK-LABEL: @oneArgPromotionTruncInsert -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8 -; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, ptr [[GEP]] -; CHECK: add i8 [[LOAD]], [[TRUNC]] -; CHECK: ret +; use. define i8 @oneArgPromotionTruncInsert(i8 %arg1, ptr %base) { - %add = add nsw i8 %arg1, 1 +; CHECK-LABEL: define i8 @oneArgPromotionTruncInsert( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[PROMOTED:%.*]] = trunc i64 [[ADD]] to i8 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[FINALRES:%.*]] = add i8 [[RES]], [[PROMOTED]] +; CHECK-NEXT: ret i8 [[FINALRES]] +; + %add = add nsw i8 %arg1, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -175,15 +209,20 @@ define i8 @oneArgPromotionTruncInsert(i8 %arg1, ptr %base) { } ; Cannot sext from a larger type than the promoted type. -; CHECK-LABEL: @oneArgPromotionLargerType -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i128 %arg1 to i8 -; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionLargerType(i128 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionLargerType( +; CHECK-SAME: i128 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i128 [[ARG1]] to i8 +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[PROMOTED:%.*]] = trunc i64 [[ADD]] to i8 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[FINALRES:%.*]] = add i8 [[RES]], [[PROMOTED]] +; CHECK-NEXT: ret i8 [[FINALRES]] +; %trunc = trunc i128 %arg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -194,18 +233,20 @@ define i8 @oneArgPromotionLargerType(i128 %arg1, ptr %base) { ; Use same inserted trunc ; On X86 truncate are free. Check that we are able to promote the add ; to be used as addressing mode and that we insert a truncate for -; *all* the other uses. -; CHECK-LABEL: @oneArgPromotionTruncInsertSeveralUse -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8 -; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, ptr [[GEP]] -; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = add i8 [[LOAD]], [[TRUNC]] -; CHECK: add i8 [[ADDRES]], [[TRUNC]] -; CHECK: ret +; *all* the other uses. define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, ptr %base) { - %add = add nsw i8 %arg1, 1 +; CHECK-LABEL: define i8 @oneArgPromotionTruncInsertSeveralUse( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[PROMOTED:%.*]] = trunc i64 [[ADD]] to i8 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ALMOSTFINALRES:%.*]] = add i8 [[RES]], [[PROMOTED]] +; CHECK-NEXT: [[FINALRES:%.*]] = add i8 [[ALMOSTFINALRES]], [[PROMOTED]] +; CHECK-NEXT: ret i8 [[FINALRES]] +; + %add = add nsw i8 %arg1, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -216,16 +257,18 @@ define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, ptr %base) { ; Check that the promoted instruction is used for all uses of the original ; sign extension. -; CHECK-LABEL: @oneArgPromotionSExtSeveralUse -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, ptr [[GEP]] -; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = zext i8 [[LOAD]] to i64 -; CHECK: add i64 [[ADDRES]], [[PROMOTED]] -; CHECK: ret define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, ptr %base) { - %add = add nsw i8 %arg1, 1 +; CHECK-LABEL: define i64 @oneArgPromotionSExtSeveralUse( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ALMOSTFINALRES:%.*]] = zext i8 [[RES]] to i64 +; CHECK-NEXT: [[FINALRES:%.*]] = add i64 [[ALMOSTFINALRES]], [[ADD]] +; CHECK-NEXT: ret i64 [[FINALRES]] +; + %add = add nsw i8 %arg1, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -249,16 +292,19 @@ define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, ptr %base) { ; - Setting the operands of the promoted instruction with the promoted values. ; - Moving instruction around (mainly sext when promoting instruction). ; Each type of those promotions has to be undo at least once during this -; specific test. -; CHECK-LABEL: @twoArgsPromotionNest -; CHECK: [[ORIG:%[a-zA-Z_0-9-]+]] = add nsw i32 %arg1, %arg2 -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ORIG]], [[ORIG]] -; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[SEXT]] -; CHECK: ret +; specific test. define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, ptr %base) { +; CHECK-LABEL: define i8 @twoArgsPromotionNest( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTABLEADD1:%.*]] = add nsw i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[PROMOTABLEADD2:%.*]] = add nsw i32 [[PROMOTABLEADD1]], [[PROMOTABLEADD1]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i32 [[PROMOTABLEADD2]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %promotableadd1 = add nsw i32 %arg1, %arg2 - %promotableadd2 = add nsw i32 %promotableadd1, %promotableadd1 + %promotableadd2 = add nsw i32 %promotableadd1, %promotableadd1 %sextadd = sext i32 %promotableadd2 to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -270,18 +316,21 @@ define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, ptr %base) { ; The matcher first promotes the add, removes the trunc and promotes ; the sext of arg1. ; Then, the matcher cannot use an addressing mode r + r + r, thus it -; rolls back. -; CHECK-LABEL: @twoArgsNoPromotionRemove -; CHECK: [[SEXTARG1:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i32 -; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[SEXTARG1]] to i8 -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[TRUNC]], %arg2 -; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i64 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[SEXT]] -; CHECK: ret +; rolls back. define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, ptr %base) { +; CHECK-LABEL: define i8 @twoArgsNoPromotionRemove( +; CHECK-SAME: i1 [[ARG1:%.*]], i8 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i1 [[ARG1]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEXTARG1]] to i8 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[TRUNC]], [[ARG2]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i8 [[ADD]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nsw i8 %trunc, %arg2 + %add = add nsw i8 %trunc, %arg2 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -301,29 +350,40 @@ define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, ptr %base) { ; Check that we did not promote anything in the final matching. ; ; <rdar://problem/16020230> -; CHECK-LABEL: @checkProfitability -; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64 -; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg2 to i64 -; CHECK: [[SHL:%[a-zA-Z_0-9-]+]] = shl nsw i32 %arg1, 1 -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2 -; CHECK: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64 ; BB then -; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to ptr -; CHECK: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr [[BASE1]], i64 48 -; CHECK: load i32, ptr [[FULL1]] ; BB else -; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to ptr -; CHECK: [[FULL2:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr [[BASE2]], i64 48 -; CHECK: load i32, ptr [[FULL2]] -; CHECK: ret define i32 @checkProfitability(i32 %arg1, i32 %arg2, i1 %test) { +; CHECK-LABEL: define i32 @checkProfitability( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], i1 [[TEST:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[ARG1]], 1 +; CHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[SHL]], [[ARG2]] +; CHECK-NEXT: [[SEXTIDX1:%.*]] = sext i32 [[ADD1]] to i64 +; CHECK-NEXT: br i1 [[TEST]], label %[[THEN:.*]], label %[[ELSE:.*]] +; CHECK: [[THEN]]: +; CHECK-NEXT: [[SUNKADDR:%.*]] = inttoptr i64 [[SEXTIDX1]] to ptr +; CHECK-NEXT: [[SUNKADDR13:%.*]] = getelementptr i8, ptr [[SUNKADDR]], i64 48 +; CHECK-NEXT: [[RES1:%.*]] = load i32, ptr [[SUNKADDR13]], align 4 +; CHECK-NEXT: br label %[[END:.*]] +; CHECK: [[ELSE]]: +; CHECK-NEXT: [[SUNKADDR17:%.*]] = inttoptr i64 [[SEXTIDX1]] to ptr +; CHECK-NEXT: [[SUNKADDR18:%.*]] = getelementptr i8, ptr [[SUNKADDR17]], i64 48 +; CHECK-NEXT: [[RES2:%.*]] = load i32, ptr [[SUNKADDR18]], align 4 +; CHECK-NEXT: br label %[[END]] +; CHECK: [[END]]: +; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[RES1]], %[[THEN]] ], [ [[RES2]], %[[ELSE]] ] +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[SEXTIDX1]] to i32 +; CHECK-NEXT: [[RES:%.*]] = add i32 [[TMP]], [[TMP1]] +; CHECK-NEXT: [[ADDR:%.*]] = inttoptr i32 [[RES]] to ptr +; CHECK-NEXT: [[FINAL:%.*]] = load i32, ptr [[ADDR]], align 4 +; CHECK-NEXT: ret i32 [[FINAL]] +; %shl = shl nsw i32 %arg1, 1 %add1 = add nsw i32 %shl, %arg2 %sextidx1 = sext i32 %add1 to i64 %tmpptr = inttoptr i64 %sextidx1 to ptr %arrayidx1 = getelementptr i32, ptr %tmpptr, i64 12 br i1 %test, label %then, label %else -then: +then: %res1 = load i32, ptr %arrayidx1 br label %end else: @@ -346,15 +406,47 @@ end: ; We used to crash on this function because we did not return the right ; promoted instruction for %conv.i. ; Make sure we generate the right code now. -; CHECK-LABEL: @fn3 ; %conv.i is used twice and only one of its use is being promoted. ; Use it at the starting point for the matching. -; CHECK: %conv.i = zext i16 [[PLAIN_OPND:%[.a-zA-Z_0-9-]+]] to i32 -; CHECK-NEXT: [[PROMOTED_CONV:%[.a-zA-Z_0-9-]+]] = zext i16 [[PLAIN_OPND]] to i64 -; CHECK-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr %P, i64 [[PROMOTED_CONV]] -; CHECK-NEXT: [[ADDR:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr [[ADD]], i64 7 -; CHECK-NEXT: load i8, ptr [[ADDR]], align 1 define signext i16 @fn3(ptr nocapture readonly %P) { +; CHECK-LABEL: define signext i16 @fn3( +; CHECK-SAME: ptr nocapture readonly [[P:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br label %[[WHILE_BODY_I_I:.*]] +; CHECK: [[WHILE_BODY_I_I]]: +; CHECK-NEXT: [[SRC_ADDR_0_I_I:%.*]] = phi i16 [ 0, %[[ENTRY]] ], [ [[INC_I_I:%.*]], %[[WHILE_BODY_I_I]] ] +; CHECK-NEXT: [[INC_I_I]] = add i16 [[SRC_ADDR_0_I_I]], 1 +; CHECK-NEXT: [[IDXPROM_I_I:%.*]] = sext i16 [[SRC_ADDR_0_I_I]] to i64 +; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[IDXPROM_I_I]] +; CHECK-NEXT: [[SUNKADDR2:%.*]] = getelementptr inbounds i8, ptr [[SUNKADDR]], i64 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SUNKADDR2]], align 1 +; CHECK-NEXT: [[CONV2_I_I:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[AND_I_I:%.*]] = and i32 [[CONV2_I_I]], 15 +; CHECK-NEXT: store i32 [[AND_I_I]], ptr @a, align 4 +; CHECK-NEXT: [[TOBOOL_I_I:%.*]] = icmp eq i32 [[AND_I_I]], 0 +; CHECK-NEXT: br i1 [[TOBOOL_I_I]], label %[[WHILE_BODY_I_I]], label %[[FN1_EXIT_I:.*]] +; CHECK: [[FN1_EXIT_I]]: +; CHECK-NEXT: [[CONV_I:%.*]] = zext i16 [[INC_I_I]] to i32 +; CHECK-NEXT: [[PROMOTED4:%.*]] = zext i16 [[INC_I_I]] to i64 +; CHECK-NEXT: [[SUNKADDR5:%.*]] = getelementptr i8, ptr [[P]], i64 [[PROMOTED4]] +; CHECK-NEXT: [[SUNKADDR6:%.*]] = getelementptr i8, ptr [[SUNKADDR5]], i64 7 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[SUNKADDR6]], align 1 +; CHECK-NEXT: [[CONV2_I:%.*]] = sext i8 [[TMP2]] to i16 +; CHECK-NEXT: store i16 [[CONV2_I]], ptr @b, align 2 +; CHECK-NEXT: [[SUB4_I:%.*]] = sub nsw i32 0, [[CONV_I]] +; CHECK-NEXT: [[CONV5_I:%.*]] = zext i16 [[CONV2_I]] to i32 +; CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt i32 [[CONV5_I]], [[SUB4_I]] +; CHECK-NEXT: br i1 [[CMP_I]], label %[[IF_THEN_I:.*]], label %[[FN2_EXIT:.*]] +; CHECK: [[IF_THEN_I]]: +; CHECK-NEXT: [[END_I:%.*]] = getelementptr inbounds [[STRUCT_DNS_PACKET:%.*]], ptr [[P]], i64 0, i32 1 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[END_I]], align 4 +; CHECK-NEXT: [[SUB7_I:%.*]] = add i32 [[TMP3]], 65535 +; CHECK-NEXT: [[CONV8_I:%.*]] = trunc i32 [[SUB7_I]] to i16 +; CHECK-NEXT: br label %[[FN2_EXIT]] +; CHECK: [[FN2_EXIT]]: +; CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i16 [ [[CONV8_I]], %[[IF_THEN_I]] ], [ undef, %[[FN1_EXIT_I]] ] +; CHECK-NEXT: ret i16 [[RETVAL_0_I]] +; entry: %tmp = getelementptr inbounds %struct.dns_packet, ptr %P, i64 0, i32 2 br label %while.body.i.i @@ -399,13 +491,16 @@ fn2.exit: ; preds = %if.then.i, %fn1.exi ; Check that we do not promote an extension if the non-wrapping flag does not ; match the kind of the extension. -; CHECK-LABEL: @noPromotionFlag -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 %arg1, %arg2 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = zext i32 [[ADD]] to i64 -; CHECK: inttoptr i64 [[PROMOTED]] to ptr -; CHECK: ret define i8 @noPromotionFlag(i32 %arg1, i32 %arg2) { - %add = add nsw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @noPromotionFlag( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[ZEXTADD:%.*]] = zext i32 [[ADD]] to i64 +; CHECK-NEXT: [[BASE:%.*]] = inttoptr i64 [[ZEXTADD]] to ptr +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[BASE]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, %arg2 %zextadd = zext i32 %add to i64 %base = inttoptr i64 %zextadd to ptr %res = load i8, ptr %base @@ -413,14 +508,17 @@ define i8 @noPromotionFlag(i32 %arg1, i32 %arg2) { } ; Check that we correctly promote both operands of the promotable add with zext. -; CHECK-LABEL: @twoArgsPromotionZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i32 %arg1 to i64 -; CHECK: [[ARG2ZEXT:%[a-zA-Z_0-9-]+]] = zext i32 %arg2 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], [[ARG2ZEXT]] -; CHECK: inttoptr i64 [[PROMOTED]] to ptr -; CHECK: ret define i8 @twoArgsPromotionZExt(i32 %arg1, i32 %arg2) { - %add = add nuw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @twoArgsPromotionZExt( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i32 [[ARG1]] to i64 +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i32 [[ARG2]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], [[PROMOTED2]] +; CHECK-NEXT: [[BASE:%.*]] = inttoptr i64 [[ADD]] to ptr +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[BASE]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nuw i32 %arg1, %arg2 %zextadd = zext i32 %add to i64 %base = inttoptr i64 %zextadd to ptr %res = load i8, ptr %base @@ -428,13 +526,16 @@ define i8 @twoArgsPromotionZExt(i32 %arg1, i32 %arg2) { } ; Check that we correctly promote constant arguments. -; CHECK-LABEL: @oneArgPromotionNegativeCstZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 255 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionNegativeCstZExt(i8 %arg1, ptr %base) { - %add = add nuw i8 %arg1, -1 +; CHECK-LABEL: define i8 @oneArgPromotionNegativeCstZExt( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], 255 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nuw i8 %arg1, -1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -442,14 +543,17 @@ define i8 @oneArgPromotionNegativeCstZExt(i8 %arg1, ptr %base) { } ; Check that we are able to merge two zero extensions. -; CHECK-LABEL: @oneArgPromotionZExtZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionZExtZExt(i8 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionZExtZExt( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %zext = zext i8 %arg1 to i32 - %add = add nuw i32 %zext, 1 + %add = add nuw i32 %zext, 1 %zextadd = zext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -458,17 +562,20 @@ define i8 @oneArgPromotionZExtZExt(i8 %arg1, ptr %base) { ; Check that we do not promote truncate when the dropped bits ; are of a different kind. -; CHECK-LABEL: @oneArgPromotionBlockTruncZExt -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i32 -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8 -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockTruncZExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockTruncZExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i1 [[ARG1]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEXTARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nuw i8 %trunc, 1 + %add = add nuw i8 %trunc, 1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -477,15 +584,18 @@ define i8 @oneArgPromotionBlockTruncZExt(i1 %arg1, ptr %base) { ; Check that we are able to promote truncate when we know all the bits ; that are dropped. -; CHECK-LABEL: @oneArgPromotionPassTruncZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i1 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionPassTruncZExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionPassTruncZExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i1 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = zext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nuw i8 %trunc, 1 + %add = add nuw i8 %trunc, 1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -493,15 +603,18 @@ define i8 @oneArgPromotionPassTruncZExt(i1 %arg1, ptr %base) { } ; Check that we do not promote sext with zext. -; CHECK-LABEL: @oneArgPromotionBlockSExtZExt -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i8 -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[ARG1SEXT]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockSExtZExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockSExtZExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i1 [[ARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i8 [[SEXTARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i8 - %add = add nuw i8 %sextarg1, 1 + %add = add nuw i8 %sextarg1, 1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx diff --git a/llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir b/llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir index aceb344d8b76..13f3f3ad4187 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir +++ b/llvm/test/CodeGen/X86/codegen-prepare-replacephi.mir @@ -6,7 +6,7 @@ # "Replacement PHI node is already replaced." --- | - define void @f1() { + define void @f1(i1 %arg) { entry: %arrayidx = getelementptr inbounds [2 x i16], ptr undef, i16 0, i16 2 br label %for.cond @@ -30,10 +30,10 @@ %5 = phi ptr [ %4, %for.body ], [ %5, %if.then5 ], [ undef, %for.cond2 ] %6 = phi ptr [ %3, %for.body ], [ %6, %if.then5 ], [ undef, %for.cond2 ] %7 = phi ptr [ %2, %for.body ], [ %6, %if.then5 ], [ undef, %for.cond2 ] - br i1 undef, label %for.cond2, label %if.then5 + br i1 %arg, label %for.cond2, label %if.then5 if.then5: - br i1 undef, label %cleanup, label %for.cond2 + br i1 %arg, label %cleanup, label %for.cond2 cleanup: br i1 true, label %for.cond, label %for.body diff --git a/llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir b/llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir index 6159aa8a42e2..e93e04bfd443 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir +++ b/llvm/test/CodeGen/X86/codegen-prepare-replacephi2.mir @@ -7,7 +7,7 @@ --- | - define void @f1() { + define void @f1(i1 %arg) { entry: %arrayidx = getelementptr inbounds [2 x i16], ptr undef, i16 0, i16 2 br label %for.cond @@ -24,7 +24,7 @@ %2 = phi ptr [ %1, %for.cond ], [ %12, %cleanup ] %3 = phi ptr [ %0, %for.cond ], [ %11, %cleanup ] %4 = phi ptr [ %0, %for.cond ], [ %10, %cleanup ] - br i1 undef, label %for.cond2.preheader, label %if.then + br i1 %arg, label %for.cond2.preheader, label %if.then for.cond2.preheader: br label %for.cond2 @@ -37,7 +37,7 @@ %5 = phi ptr [ %8, %for.inc ], [ %4, %for.cond2.preheader ] %6 = phi ptr [ %9, %for.inc ], [ %3, %for.cond2.preheader ] %7 = phi ptr [ %9, %for.inc ], [ %2, %for.cond2.preheader ] - br i1 undef, label %for.inc, label %if.then5 + br i1 %arg, label %for.inc, label %if.then5 if.then5: br i1 true, label %cleanup.loopexit, label %if.end diff --git a/llvm/test/CodeGen/X86/combine-concatvectors.ll b/llvm/test/CodeGen/X86/combine-concatvectors.ll index 230afd146193..7237b02ca6b6 100644 --- a/llvm/test/CodeGen/X86/combine-concatvectors.ll +++ b/llvm/test/CodeGen/X86/combine-concatvectors.ll @@ -72,7 +72,7 @@ alloca_0: br label %loop.4942 loop.4942: ; preds = %loop.4942, %alloca_0 - br i1 undef, label %loop.4942, label %ifmerge.1298 + br i1 poison, label %loop.4942, label %ifmerge.1298 ifmerge.1298: ; preds = %loop.4942 %gepload4638 = load float, ptr getelementptr inbounds ([49216 x i8], ptr @qa_, i64 0, i64 28324), align 4 diff --git a/llvm/test/CodeGen/X86/crash.ll b/llvm/test/CodeGen/X86/crash.ll index 16e3bb6e50ae..2f49a60a26f4 100644 --- a/llvm/test/CodeGen/X86/crash.ll +++ b/llvm/test/CodeGen/X86/crash.ll @@ -115,9 +115,9 @@ do.body92: ; preds = %if.then66 ; Crash during XOR optimization. ; <rdar://problem/7869290> -define void @test7() nounwind ssp { +define void @test7(i1 %arg) nounwind ssp { entry: - br i1 undef, label %bb14, label %bb67 + br i1 %arg, label %bb14, label %bb67 bb14: %tmp0 = trunc i16 undef to i1 @@ -157,14 +157,14 @@ entry: ; shift of and. %struct.S0 = type { i8, [2 x i8], i8 } -define void @func_59(i32 %p_63) noreturn nounwind { +define void @func_59(i32 %p_63, i1 %arg) noreturn nounwind { entry: br label %for.body for.body: ; preds = %for.inc44, %entry %p_63.addr.1 = phi i32 [ %p_63, %entry ], [ 0, %for.inc44 ] %l_74.0 = phi i32 [ 0, %entry ], [ %add46, %for.inc44 ] - br i1 undef, label %for.inc44, label %bb.nph81 + br i1 %arg, label %for.inc44, label %bb.nph81 bb.nph81: ; preds = %for.body %tmp98 = add i32 %p_63.addr.1, 0 @@ -237,7 +237,7 @@ declare i64 @llvm.objectsize.i64.p0(ptr, i1) nounwind readnone %t20 = type { i32, i32 } %t21 = type { ptr } -define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 { +define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE(i1 %arg) ssp align 2 { bb: %tmp = load ptr, ptr undef, align 4 %tmp3 = getelementptr inbounds %t9, ptr %tmp, i32 0, i32 0, i32 0, i32 0, i32 1 @@ -246,7 +246,7 @@ bb: bb4: ; preds = %bb37, %bb %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ] %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ] - br i1 undef, label %bb34, label %bb7 + br i1 %arg, label %bb34, label %bb7 bb7: ; preds = %bb4 %tmp8 = load i32, ptr undef, align 4 @@ -292,7 +292,7 @@ bb33: ; preds = %bb29 unreachable bb34: ; preds = %bb4 - br i1 undef, label %bb36, label %bb35 + br i1 %arg, label %bb36, label %bb35 bb35: ; preds = %bb34 store ptr null, ptr %tmp3, align 4 @@ -319,7 +319,7 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind ; PR10463 ; Spilling a virtual register with <undef> uses. -define void @autogen_239_1000() { +define void @autogen_239_1000(i1 %arg) { BB: %Shuff = shufflevector <8 x double> undef, <8 x double> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef> br label %CF @@ -327,14 +327,14 @@ BB: CF: %B16 = frem <8 x double> zeroinitializer, %Shuff %E19 = extractelement <8 x double> %Shuff, i32 5 - br i1 undef, label %CF, label %CF75 + br i1 %arg, label %CF, label %CF75 CF75: - br i1 undef, label %CF75, label %CF76 + br i1 %arg, label %CF75, label %CF76 CF76: store double %E19, ptr undef - br i1 undef, label %CF76, label %CF77 + br i1 %arg, label %CF76, label %CF77 CF77: %B55 = fmul <8 x double> %B16, undef @@ -396,24 +396,24 @@ if.end: ; InstrEmitter::EmitSubregNode() may steal virtual registers from already ; emitted blocks when isCoalescableExtInstr points out the opportunity. ; Make sure kill flags are cleared on the newly global virtual register. -define i64 @ov_read(ptr %vf, ptr nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, ptr %bitstream) nounwind uwtable ssp { +define i64 @ov_read(ptr %vf, ptr nocapture %buffer, i32 %length, i32 %bigendianp, i32 %word, i32 %sgned, ptr %bitstream, i1 %arg) nounwind uwtable ssp { entry: - br i1 undef, label %return, label %while.body.preheader + br i1 %arg, label %return, label %while.body.preheader while.body.preheader: ; preds = %entry - br i1 undef, label %if.then3, label %if.end7 + br i1 %arg, label %if.then3, label %if.end7 if.then3: ; preds = %while.body.preheader %0 = load i32, ptr undef, align 4 - br i1 undef, label %land.lhs.true.i255, label %if.end7 + br i1 %arg, label %land.lhs.true.i255, label %if.end7 land.lhs.true.i255: ; preds = %if.then3 - br i1 undef, label %if.then.i256, label %if.end7 + br i1 %arg, label %if.then.i256, label %if.end7 if.then.i256: ; preds = %land.lhs.true.i255 %sub.i = sub i32 0, %0 %conv = sext i32 %sub.i to i64 - br i1 undef, label %if.end7, label %while.end + br i1 %arg, label %if.end7, label %while.end if.end7: ; preds = %if.then.i256, %land.lhs.true.i255, %if.then3, %while.body.preheader unreachable @@ -486,12 +486,12 @@ declare void @fn3(...) ; When coalescing %1 and %2, the IMPLICIT_DEF instruction should be ; erased along with its value number. ; -define void @rdar12474033() nounwind ssp { +define void @rdar12474033(i1 %arg, i32 %arg2, i32 %arg3, i32 %arg4) nounwind ssp { bb: - br i1 undef, label %bb21, label %bb1 + br i1 %arg, label %bb21, label %bb1 bb1: ; preds = %bb - switch i32 undef, label %bb10 [ + switch i32 %arg2, label %bb10 [ i32 4, label %bb2 i32 1, label %bb9 i32 5, label %bb3 @@ -503,7 +503,7 @@ bb2: ; preds = %bb1 unreachable bb3: ; preds = %bb1, %bb1 - br i1 undef, label %bb4, label %bb5 + br i1 %arg, label %bb4, label %bb5 bb4: ; preds = %bb3 unreachable @@ -521,7 +521,7 @@ bb9: ; preds = %bb1, %bb1 bb10: ; preds = %bb5, %bb1 %tmp11 = phi i128 [ undef, %bb1 ], [ %tmp6, %bb5 ] %tmp12 = phi i128 [ 0, %bb1 ], [ %tmp8, %bb5 ] - switch i32 undef, label %bb21 [ + switch i32 %arg3, label %bb21 [ i32 2, label %bb18 i32 3, label %bb13 i32 5, label %bb16 @@ -530,7 +530,7 @@ bb10: ; preds = %bb5, %bb1 ] bb13: ; preds = %bb10 - br i1 undef, label %bb15, label %bb14 + br i1 %arg, label %bb15, label %bb14 bb14: ; preds = %bb13 br label %bb21 @@ -554,7 +554,7 @@ bb21: ; preds = %bb18, %bb14, %bb10, %tmp23 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp19, %bb18 ] store <4 x float> %tmp23, ptr undef, align 16 store <4 x float> %tmp22, ptr undef, align 16 - switch i32 undef, label %bb29 [ + switch i32 %arg4, label %bb29 [ i32 5, label %bb27 i32 1, label %bb24 i32 2, label %bb25 diff --git a/llvm/test/CodeGen/X86/domain-reassignment-test.ll b/llvm/test/CodeGen/X86/domain-reassignment-test.ll index af7aca67c8fa..77c1ef256cf0 100644 --- a/llvm/test/CodeGen/X86/domain-reassignment-test.ll +++ b/llvm/test/CodeGen/X86/domain-reassignment-test.ll @@ -3,7 +3,7 @@ ; Check that the X86 domain reassignment pass doesn't introduce an illegal ; test instruction. See PR37396 -define void @japi1_foo2_34617() { +define void @japi1_foo2_34617(i1 %arg) { pass2: br label %if5 @@ -27,7 +27,7 @@ if5: %tmp120 = and i1 %tmp118, %tmp119 %tmp121 = zext i1 %tmp120 to i8 %tmp122 = and i8 %b.055, %tmp121 - br i1 undef, label %L174, label %if5 + br i1 %arg, label %L174, label %if5 L188: unreachable diff --git a/llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll b/llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll index 8d8d4fa699aa..4a5cddb30e03 100644 --- a/llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll +++ b/llvm/test/CodeGen/X86/fast-isel-cmp-branch.ll @@ -5,9 +5,9 @@ ; The machine verifier will catch and complain about this case. ; CHECK-LABEL: baz ; CHECK: retq -define void @baz() { +define void @baz(i1 %arg) { entry: - br i1 undef, label %exit, label %exit + br i1 %arg, label %exit, label %exit exit: ret void diff --git a/llvm/test/CodeGen/X86/fminimum-fmaximum.ll b/llvm/test/CodeGen/X86/fminimum-fmaximum.ll index c6da0c5ca479..1dcce5336895 100644 --- a/llvm/test/CodeGen/X86/fminimum-fmaximum.ll +++ b/llvm/test/CodeGen/X86/fminimum-fmaximum.ll @@ -3,6 +3,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX,AVX512,AVX512DQ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=AVX10_2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86 declare float @llvm.maximum.f32(float, float) @@ -73,6 +74,11 @@ define float @test_fmaximum(float %x, float %y) nounwind { ; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $1, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -110,6 +116,11 @@ define <4 x float> @test_fmaximum_scalarize(<4 x float> %x, <4 x float> %y) "no- ; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_scalarize: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $1, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_scalarize: ; X86: # %bb.0: ; X86-NEXT: vmaxps %xmm1, %xmm0, %xmm0 @@ -129,6 +140,11 @@ define float @test_fmaximum_nan0(float %x, float %y) { ; AVX-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_nan0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_nan0: ; X86: # %bb.0: ; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} @@ -148,6 +164,11 @@ define float @test_fmaximum_nan1(float %x, float %y) { ; AVX-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_nan1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_nan1: ; X86: # %bb.0: ; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} @@ -215,6 +236,13 @@ define float @test_fmaximum_nnan(float %x, float %y) nounwind { ; AVX512DQ-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; AVX512DQ-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_nnan: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vaddss %xmm1, %xmm0, %xmm2 +; AVX10_2-NEXT: vsubss %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: vminmaxss $1, %xmm0, %xmm2 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_nnan: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -272,6 +300,12 @@ define double @test_fmaximum_zero0(double %x, double %y) nounwind { ; AVX512-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_zero0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm0, %xmm0, %xmm0 +; AVX10_2-NEXT: vminmaxsd $1, %xmm0, %xmm1 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_zero0: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -323,6 +357,12 @@ define double @test_fmaximum_zero1(double %x, double %y) nounwind { ; AVX512-NEXT: vmovapd %xmm1, %xmm0 ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_zero1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxsd $1, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_zero1: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -354,6 +394,11 @@ define double @test_fmaximum_zero2(double %x, double %y) { ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_zero2: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_zero2: ; X86: # %bb.0: ; X86-NEXT: fldz @@ -390,6 +435,11 @@ define float @test_fmaximum_nsz(float %x, float %y) "no-signed-zeros-fp-math"="t ; AVX512-NEXT: vmovaps %xmm1, %xmm0 ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_nsz: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $1, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_nsz: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -474,6 +524,12 @@ define float @test_fmaximum_combine_cmps(float %x, float %y) nounwind { ; AVX512DQ-NEXT: vmaxss %xmm2, %xmm0, %xmm0 ; AVX512DQ-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_combine_cmps: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxss $1, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_combine_cmps: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -562,6 +618,11 @@ define float @test_fminimum(float %x, float %y) nounwind { ; AVX512-NEXT: vmovaps %xmm1, %xmm0 ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $0, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -599,6 +660,11 @@ define <2 x double> @test_fminimum_scalarize(<2 x double> %x, <2 x double> %y) " ; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_scalarize: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxpd $0, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_scalarize: ; X86: # %bb.0: ; X86-NEXT: vminpd %xmm1, %xmm0, %xmm0 @@ -618,6 +684,11 @@ define float @test_fminimum_nan0(float %x, float %y) { ; AVX-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_nan0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_nan0: ; X86: # %bb.0: ; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} @@ -637,6 +708,11 @@ define float @test_fminimum_nan1(float %x, float %y) { ; AVX-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_nan1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovss {{.*#+}} xmm0 = [NaN,0.0E+0,0.0E+0,0.0E+0] +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_nan1: ; X86: # %bb.0: ; X86-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} @@ -695,6 +771,11 @@ define double @test_fminimum_nnan(double %x, double %y) "no-nans-fp-math"="true" ; AVX512DQ-NEXT: vminsd %xmm2, %xmm1, %xmm0 ; AVX512DQ-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_nnan: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxsd $0, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_nnan: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -749,6 +830,11 @@ define double @test_fminimum_zero0(double %x, double %y) nounwind { ; AVX512-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_zero0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxsd $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_zero0: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -796,6 +882,11 @@ define double @test_fminimum_zero1(double %x, double %y) nounwind { ; AVX512-NEXT: vmovapd %xmm1, %xmm0 ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_zero1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxsd $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_zero1: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -826,6 +917,11 @@ define double @test_fminimum_zero2(double %x, double %y) { ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_zero2: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_zero2: ; X86: # %bb.0: ; X86-NEXT: fldz @@ -863,6 +959,11 @@ define float @test_fminimum_nsz(float %x, float %y) nounwind { ; AVX512-NEXT: vmovaps %xmm1, %xmm0 ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_nsz: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $0, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_nsz: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -948,6 +1049,12 @@ define float @test_fminimum_combine_cmps(float %x, float %y) nounwind { ; AVX512DQ-NEXT: vminss %xmm2, %xmm0, %xmm0 ; AVX512DQ-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_combine_cmps: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxss $0, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_combine_cmps: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -1009,6 +1116,11 @@ define <2 x double> @test_fminimum_vector(<2 x double> %x, <2 x double> %y) { ; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_vector: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxpd $0, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_vector: ; X86: # %bb.0: ; X86-NEXT: vblendvpd %xmm0, %xmm0, %xmm1, %xmm2 @@ -1032,6 +1144,11 @@ define <4 x float> @test_fmaximum_vector(<4 x float> %x, <4 x float> %y) "no-nan ; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_vector: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $1, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_vector: ; X86: # %bb.0: ; X86-NEXT: vmaxps %xmm1, %xmm0, %xmm0 @@ -1054,6 +1171,12 @@ define <2 x double> @test_fminimum_vector_zero(<2 x double> %x) { ; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_vector_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxpd $0, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_vector_zero: ; X86: # %bb.0: ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -1077,6 +1200,11 @@ define <4 x float> @test_fmaximum_vector_signed_zero(<4 x float> %x) { ; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_vector_signed_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_vector_signed_zero: ; X86: # %bb.0: ; X86-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] @@ -1102,6 +1230,13 @@ define <2 x double> @test_fminimum_vector_partially_zero(<2 x double> %x) { ; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_vector_partially_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX10_2-NEXT: vminmaxpd $0, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_vector_partially_zero: ; X86: # %bb.0: ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -1149,6 +1284,13 @@ define <2 x double> @test_fminimum_vector_different_zeros(<2 x double> %x) { ; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_vector_different_zeros: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX10_2-NEXT: vminmaxpd $0, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_vector_different_zeros: ; X86: # %bb.0: ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -1177,6 +1319,11 @@ define <4 x float> @test_fmaximum_vector_non_zero(<4 x float> %x) { ; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_vector_non_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_vector_non_zero: ; X86: # %bb.0: ; X86-NEXT: vmovaps {{.*#+}} xmm1 = [5.0E+0,4.0E+0,3.0E+0,2.0E+0] @@ -1206,6 +1353,13 @@ define <2 x double> @test_fminimum_vector_nan(<2 x double> %x) { ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_vector_nan: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX10_2-NEXT: vminmaxpd $0, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_vector_nan: ; X86: # %bb.0: ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -1232,6 +1386,12 @@ define <2 x double> @test_fminimum_vector_zero_first(<2 x double> %x) { ; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_vector_zero_first: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxpd $0, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_vector_zero_first: ; X86: # %bb.0: ; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 @@ -1260,6 +1420,11 @@ define <2 x double> @test_fminimum_vector_signed_zero(<2 x double> %x) { ; AVX-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fminimum_vector_signed_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxpd $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fminimum_vector_signed_zero: ; X86: # %bb.0: ; X86-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm1 @@ -1284,6 +1449,11 @@ define <4 x float> @test_fmaximum_vector_signed_zero_first(<4 x float> %x) { ; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_vector_signed_zero_first: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_vector_signed_zero_first: ; X86: # %bb.0: ; X86-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] @@ -1314,6 +1484,12 @@ define <4 x float> @test_fmaximum_vector_zero(<4 x float> %x) { ; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 ; AVX-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_vector_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxps $1, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_vector_zero: ; X86: # %bb.0: ; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -1369,6 +1545,12 @@ define <4 x float> @test_fmaximum_v4f32_splat(<4 x float> %x, float %y) { ; AVX512-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_v4f32_splat: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vbroadcastss %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxps $1, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_v4f32_splat: ; X86: # %bb.0: ; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm1 @@ -1803,6 +1985,11 @@ define <4 x half> @test_fmaximum_v4f16(<4 x half> %x, <4 x half> %y) nounwind { ; AVX512-NEXT: popq %rbp ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_v4f16: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxph $1, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_v4f16: ; X86: # %bb.0: ; X86-NEXT: subl $164, %esp @@ -2330,6 +2517,11 @@ define <4 x bfloat> @test_fmaximum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) { ; AVX512-NEXT: .cfi_def_cfa_offset 8 ; AVX512-NEXT: retq ; +; AVX10_2-LABEL: test_fmaximum_v4bf16: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxnepbf16 $1, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; ; X86-LABEL: test_fmaximum_v4bf16: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp diff --git a/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll b/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll new file mode 100644 index 000000000000..2e9e8e62b356 --- /dev/null +++ b/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll @@ -0,0 +1,2765 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX,AVX512,AVX512DQ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=AVX10_2 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86 + +declare float @llvm.maximumnum.f32(float, float) +declare double @llvm.maximumnum.f64(double, double) +declare float @llvm.minimumnum.f32(float, float) +declare double @llvm.minimumnum.f64(double, double) +declare <2 x double> @llvm.minimumnum.v2f64(<2 x double>, <2 x double>) +declare <4 x float> @llvm.maximumnum.v4f32(<4 x float>, <4 x float>) +declare <4 x half> @llvm.maximumnum.v4f16(<4 x half>, <4 x half>) +declare <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat>, <4 x bfloat>) + +; +; fmaximumnum +; + +define float @test_fmaximumnum(float %x, float %y) nounwind { +; SSE2-LABEL: test_fmaximumnum: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: js .LBB0_2 +; SSE2-NEXT: # %bb.1: +; SSE2-NEXT: movdqa %xmm1, %xmm3 +; SSE2-NEXT: .LBB0_2: +; SSE2-NEXT: movdqa %xmm3, %xmm0 +; SSE2-NEXT: cmpordss %xmm3, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm4 +; SSE2-NEXT: andps %xmm3, %xmm4 +; SSE2-NEXT: js .LBB0_4 +; SSE2-NEXT: # %bb.3: +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: .LBB0_4: +; SSE2-NEXT: maxss %xmm1, %xmm3 +; SSE2-NEXT: andnps %xmm3, %xmm0 +; SSE2-NEXT: orps %xmm4, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB0_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vmovdqa %xmm0, %xmm2 +; AVX1-NEXT: jmp .LBB0_3 +; AVX1-NEXT: .LBB0_1: +; AVX1-NEXT: vmovdqa %xmm1, %xmm2 +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: .LBB0_3: +; AVX1-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX1-NEXT: vcmpordss %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fmaximumnum: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: testl %eax, %eax +; AVX512-NEXT: sets %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovdqa %xmm0, %xmm2 +; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: vcmpordss %xmm1, %xmm1, %k1 +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $17, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero +; X86-NEXT: vmovd %xmm2, %eax +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB0_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovdqa %xmm2, %xmm1 +; X86-NEXT: jmp .LBB0_3 +; X86-NEXT: .LBB0_1: +; X86-NEXT: vmovdqa %xmm0, %xmm1 +; X86-NEXT: vmovdqa %xmm2, %xmm0 +; X86-NEXT: .LBB0_3: +; X86-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl + %1 = tail call float @llvm.maximumnum.f32(float %x, float %y) + ret float %1 +} + +define <4 x float> @test_fmaximumnum_scalarize(<4 x float> %x, <4 x float> %y) "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" { +; SSE2-LABEL: test_fmaximumnum_scalarize: +; SSE2: # %bb.0: +; SSE2-NEXT: maxps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_scalarize: +; AVX: # %bb.0: +; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_scalarize: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $17, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_scalarize: +; X86: # %bb.0: +; X86-NEXT: vmaxps %xmm1, %xmm0, %xmm0 +; X86-NEXT: retl + %r = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %x, <4 x float> %y) + ret <4 x float> %r +} + +define float @test_fmaximumnum_nan0(float %x, float %y) { +; SSE2-LABEL: test_fmaximumnum_nan0: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_nan0: +; AVX: # %bb.0: +; AVX-NEXT: vmovaps %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_nan0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovaps %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_nan0: +; X86: # %bb.0: +; X86-NEXT: flds {{[0-9]+}}(%esp) +; X86-NEXT: retl + %1 = tail call float @llvm.maximumnum.f32(float 0x7fff000000000000, float %y) + ret float %1 +} + +define float @test_fmaximumnum_nan1(float %x, float %y) { +; SSE2-LABEL: test_fmaximumnum_nan1: +; SSE2: # %bb.0: +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_nan1: +; AVX: # %bb.0: +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_nan1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_nan1: +; X86: # %bb.0: +; X86-NEXT: flds {{[0-9]+}}(%esp) +; X86-NEXT: retl + %1 = tail call float @llvm.maximumnum.f32(float %x, float 0x7fff000000000000) + ret float %1 +} + +define float @test_fmaximumnum_nnan(float %x, float %y) nounwind { +; SSE2-LABEL: test_fmaximumnum_nnan: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps %xmm0, %xmm2 +; SSE2-NEXT: addss %xmm1, %xmm2 +; SSE2-NEXT: subss %xmm1, %xmm0 +; SSE2-NEXT: movd %xmm2, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: js .LBB4_1 +; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: maxss %xmm2, %xmm0 +; SSE2-NEXT: retq +; SSE2-NEXT: .LBB4_1: +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: maxss %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_nnan: +; AVX1: # %bb.0: +; AVX1-NEXT: vaddss %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vsubss %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vmovd %xmm2, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB4_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vmaxss %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: retq +; AVX1-NEXT: .LBB4_1: +; AVX1-NEXT: vmovaps %xmm0, %xmm1 +; AVX1-NEXT: vmaxss %xmm1, %xmm2, %xmm0 +; AVX1-NEXT: retq +; +; AVX512F-LABEL: test_fmaximumnum_nnan: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vaddss %xmm1, %xmm0, %xmm2 +; AVX512F-NEXT: vsubss %xmm1, %xmm0, %xmm0 +; AVX512F-NEXT: vmovd %xmm2, %eax +; AVX512F-NEXT: testl %eax, %eax +; AVX512F-NEXT: sets %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovaps %xmm2, %xmm1 +; AVX512F-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512F-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1} +; AVX512F-NEXT: vmaxss %xmm1, %xmm0, %xmm0 +; AVX512F-NEXT: retq +; +; AVX512DQ-LABEL: test_fmaximumnum_nnan: +; AVX512DQ: # %bb.0: +; AVX512DQ-NEXT: vaddss %xmm1, %xmm0, %xmm2 +; AVX512DQ-NEXT: vsubss %xmm1, %xmm0, %xmm0 +; AVX512DQ-NEXT: vfpclassss $3, %xmm0, %k0 # k0 = isQuietNaN(xmm0) | isPositiveZero(xmm0) +; AVX512DQ-NEXT: kmovw %k0, %k1 +; AVX512DQ-NEXT: vmovaps %xmm2, %xmm1 +; AVX512DQ-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512DQ-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1} +; AVX512DQ-NEXT: vmaxss %xmm1, %xmm0, %xmm0 +; AVX512DQ-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_nnan: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vaddss %xmm1, %xmm0, %xmm2 +; AVX10_2-NEXT: vsubss %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: vminmaxss $17, %xmm0, %xmm2 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_nnan: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero +; X86-NEXT: vaddss %xmm0, %xmm2, %xmm1 +; X86-NEXT: vsubss %xmm0, %xmm2, %xmm0 +; X86-NEXT: vmovd %xmm1, %eax +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB4_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovaps %xmm1, %xmm2 +; X86-NEXT: jmp .LBB4_3 +; X86-NEXT: .LBB4_1: +; X86-NEXT: vmovaps %xmm0, %xmm2 +; X86-NEXT: vmovaps %xmm1, %xmm0 +; X86-NEXT: .LBB4_3: +; X86-NEXT: vmaxss %xmm2, %xmm0, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl + %1 = fadd nnan float %x, %y + %2 = fsub nnan float %x, %y + %3 = tail call float @llvm.maximumnum.f32(float %1, float %2) + ret float %3 +} + +define double @test_fmaximumnum_zero0(double %x, double %y) nounwind { +; SSE2-LABEL: test_fmaximumnum_zero0: +; SSE2: # %bb.0: +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: cmpordsd %xmm1, %xmm0 +; SSE2-NEXT: movapd %xmm0, %xmm2 +; SSE2-NEXT: andpd %xmm1, %xmm2 +; SSE2-NEXT: xorpd %xmm3, %xmm3 +; SSE2-NEXT: maxsd %xmm3, %xmm1 +; SSE2-NEXT: andnpd %xmm1, %xmm0 +; SSE2-NEXT: orpd %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_zero0: +; AVX1: # %bb.0: +; AVX1-NEXT: vxorpd %xmm0, %xmm0, %xmm0 +; AVX1-NEXT: vmaxsd %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vcmpordsd %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fmaximumnum_zero0: +; AVX512: # %bb.0: +; AVX512-NEXT: vxorpd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmaxsd %xmm0, %xmm1, %xmm0 +; AVX512-NEXT: vcmpordsd %xmm1, %xmm1, %k1 +; AVX512-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_zero0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm0, %xmm0, %xmm0 +; AVX10_2-NEXT: vminmaxsd $17, %xmm0, %xmm1 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_zero0: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vmaxsd %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordsd %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovlpd %xmm0, (%esp) +; X86-NEXT: fldl (%esp) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl + %1 = tail call double @llvm.maximumnum.f64(double 0.0, double %y) + ret double %1 +} + +define double @test_fmaximumnum_zero1(double %x, double %y) nounwind { +; SSE2-LABEL: test_fmaximumnum_zero1: +; SSE2: # %bb.0: +; SSE2-NEXT: movapd %xmm0, %xmm1 +; SSE2-NEXT: cmpordsd %xmm0, %xmm1 +; SSE2-NEXT: movapd %xmm1, %xmm2 +; SSE2-NEXT: andpd %xmm0, %xmm2 +; SSE2-NEXT: xorpd %xmm3, %xmm3 +; SSE2-NEXT: maxsd %xmm3, %xmm0 +; SSE2-NEXT: andnpd %xmm0, %xmm1 +; SSE2-NEXT: orpd %xmm2, %xmm1 +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_zero1: +; AVX1: # %bb.0: +; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX1-NEXT: vmaxsd %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordsd %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fmaximumnum_zero1: +; AVX512: # %bb.0: +; AVX512-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vcmpordsd %xmm0, %xmm0, %k1 +; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmovapd %xmm1, %xmm0 +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_zero1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxsd $17, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_zero1: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vmaxsd %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordsd %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovlpd %xmm0, (%esp) +; X86-NEXT: fldl (%esp) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl + %1 = tail call double @llvm.maximumnum.f64(double %x, double 0.0) + ret double %1 +} + +define double @test_fmaximumnum_zero2(double %x, double %y) { +; SSE2-LABEL: test_fmaximumnum_zero2: +; SSE2: # %bb.0: +; SSE2-NEXT: xorps %xmm0, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_zero2: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_zero2: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_zero2: +; X86: # %bb.0: +; X86-NEXT: fldz +; X86-NEXT: retl + %1 = tail call double @llvm.maximumnum.f64(double 0.0, double -0.0) + ret double %1 +} + +define float @test_fmaximumnum_nsz(float %x, float %y) "no-signed-zeros-fp-math"="true" nounwind { +; SSE2-LABEL: test_fmaximumnum_nsz: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps %xmm0, %xmm2 +; SSE2-NEXT: cmpordss %xmm0, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm3 +; SSE2-NEXT: andps %xmm0, %xmm3 +; SSE2-NEXT: maxss %xmm1, %xmm0 +; SSE2-NEXT: andnps %xmm0, %xmm2 +; SSE2-NEXT: orps %xmm3, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_nsz: +; AVX1: # %bb.0: +; AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fmaximumnum_nsz: +; AVX512: # %bb.0: +; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vcmpordss %xmm0, %xmm0, %k1 +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmovaps %xmm1, %xmm0 +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_nsz: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $17, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_nsz: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm1 +; X86-NEXT: vmaxss {{[0-9]+}}(%esp), %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl + %1 = tail call float @llvm.maximumnum.f32(float %x, float %y) + ret float %1 +} + +define float @test_fmaximumnum_combine_cmps(float %x, float %y) nounwind { +; SSE2-LABEL: test_fmaximumnum_combine_cmps: +; SSE2: # %bb.0: +; SSE2-NEXT: divss %xmm0, %xmm1 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movaps %xmm0, %xmm3 +; SSE2-NEXT: js .LBB9_2 +; SSE2-NEXT: # %bb.1: +; SSE2-NEXT: movaps %xmm1, %xmm3 +; SSE2-NEXT: .LBB9_2: +; SSE2-NEXT: movaps %xmm3, %xmm2 +; SSE2-NEXT: cmpordss %xmm3, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm4 +; SSE2-NEXT: andps %xmm3, %xmm4 +; SSE2-NEXT: js .LBB9_4 +; SSE2-NEXT: # %bb.3: +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: .LBB9_4: +; SSE2-NEXT: maxss %xmm1, %xmm3 +; SSE2-NEXT: andnps %xmm3, %xmm2 +; SSE2-NEXT: orps %xmm4, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_combine_cmps: +; AVX1: # %bb.0: +; AVX1-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB9_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vmovaps %xmm0, %xmm2 +; AVX1-NEXT: jmp .LBB9_3 +; AVX1-NEXT: .LBB9_1: +; AVX1-NEXT: vmovaps %xmm1, %xmm2 +; AVX1-NEXT: vmovaps %xmm0, %xmm1 +; AVX1-NEXT: .LBB9_3: +; AVX1-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX1-NEXT: vcmpordss %xmm1, %xmm1, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX512F-LABEL: test_fmaximumnum_combine_cmps: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX512F-NEXT: vmovd %xmm0, %eax +; AVX512F-NEXT: testl %eax, %eax +; AVX512F-NEXT: sets %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovaps %xmm0, %xmm2 +; AVX512F-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} +; AVX512F-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512F-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX512F-NEXT: vcmpordss %xmm1, %xmm1, %k1 +; AVX512F-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512F-NEXT: retq +; +; AVX512DQ-LABEL: test_fmaximumnum_combine_cmps: +; AVX512DQ: # %bb.0: +; AVX512DQ-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX512DQ-NEXT: vfpclassss $3, %xmm0, %k0 # k0 = isQuietNaN(xmm0) | isPositiveZero(xmm0) +; AVX512DQ-NEXT: kmovw %k0, %k1 +; AVX512DQ-NEXT: vmovaps %xmm1, %xmm2 +; AVX512DQ-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k1} +; AVX512DQ-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512DQ-NEXT: vmaxss %xmm2, %xmm0, %xmm0 +; AVX512DQ-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_combine_cmps: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxss $17, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_combine_cmps: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vdivss %xmm1, %xmm0, %xmm0 +; X86-NEXT: vmovd %xmm1, %eax +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB9_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovaps %xmm1, %xmm2 +; X86-NEXT: jmp .LBB9_3 +; X86-NEXT: .LBB9_1: +; X86-NEXT: vmovaps %xmm0, %xmm2 +; X86-NEXT: vmovaps %xmm1, %xmm0 +; X86-NEXT: .LBB9_3: +; X86-NEXT: vmaxss %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl + %1 = fdiv nnan float %y, %x + %2 = tail call float @llvm.maximumnum.f32(float %x, float %1) + ret float %2 +} + +; +; fminimumnum +; + +define float @test_fminimumnum(float %x, float %y) nounwind { +; SSE2-LABEL: test_fminimumnum: +; SSE2: # %bb.0: +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movdqa %xmm1, %xmm3 +; SSE2-NEXT: js .LBB10_2 +; SSE2-NEXT: # %bb.1: +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: .LBB10_2: +; SSE2-NEXT: movdqa %xmm3, %xmm2 +; SSE2-NEXT: cmpordss %xmm3, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm4 +; SSE2-NEXT: andps %xmm3, %xmm4 +; SSE2-NEXT: js .LBB10_4 +; SSE2-NEXT: # %bb.3: +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: .LBB10_4: +; SSE2-NEXT: minss %xmm0, %xmm3 +; SSE2-NEXT: andnps %xmm3, %xmm2 +; SSE2-NEXT: orps %xmm4, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fminimumnum: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB10_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vmovdqa %xmm1, %xmm2 +; AVX1-NEXT: jmp .LBB10_3 +; AVX1-NEXT: .LBB10_1: +; AVX1-NEXT: vmovdqa %xmm0, %xmm2 +; AVX1-NEXT: vmovdqa %xmm1, %xmm0 +; AVX1-NEXT: .LBB10_3: +; AVX1-NEXT: vminss %xmm2, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fminimumnum: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: testl %eax, %eax +; AVX512-NEXT: sets %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovaps %xmm1, %xmm2 +; AVX512-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vminss %xmm2, %xmm0, %xmm1 +; AVX512-NEXT: vcmpordss %xmm0, %xmm0, %k1 +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmovaps %xmm1, %xmm0 +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $16, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vmovd %xmm0, %eax +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB10_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovdqa %xmm1, %xmm2 +; X86-NEXT: jmp .LBB10_3 +; X86-NEXT: .LBB10_1: +; X86-NEXT: vmovdqa %xmm0, %xmm2 +; X86-NEXT: vmovdqa %xmm1, %xmm0 +; X86-NEXT: .LBB10_3: +; X86-NEXT: vminss %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl + %1 = tail call float @llvm.minimumnum.f32(float %x, float %y) + ret float %1 +} + +define <2 x double> @test_fminimumnum_scalarize(<2 x double> %x, <2 x double> %y) "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" { +; SSE2-LABEL: test_fminimumnum_scalarize: +; SSE2: # %bb.0: +; SSE2-NEXT: minpd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_scalarize: +; AVX: # %bb.0: +; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_scalarize: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxpd $16, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_scalarize: +; X86: # %bb.0: +; X86-NEXT: vminpd %xmm1, %xmm0, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> %y) + ret <2 x double> %r +} + +define float @test_fminimumnum_nan0(float %x, float %y) { +; SSE2-LABEL: test_fminimumnum_nan0: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_nan0: +; AVX: # %bb.0: +; AVX-NEXT: vmovaps %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_nan0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovaps %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_nan0: +; X86: # %bb.0: +; X86-NEXT: flds {{[0-9]+}}(%esp) +; X86-NEXT: retl + %1 = tail call float @llvm.minimumnum.f32(float 0x7fff000000000000, float %y) + ret float %1 +} + +define float @test_fminimumnum_nan1(float %x, float %y) { +; SSE2-LABEL: test_fminimumnum_nan1: +; SSE2: # %bb.0: +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_nan1: +; AVX: # %bb.0: +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_nan1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_nan1: +; X86: # %bb.0: +; X86-NEXT: flds {{[0-9]+}}(%esp) +; X86-NEXT: retl + %1 = tail call float @llvm.minimumnum.f32(float %x, float 0x7fff000000000000) + ret float %1 +} + +define double @test_fminimumnum_nnan(double %x, double %y) "no-nans-fp-math"="true" nounwind { +; SSE2-LABEL: test_fminimumnum_nnan: +; SSE2: # %bb.0: +; SSE2-NEXT: movq %xmm0, %rax +; SSE2-NEXT: testq %rax, %rax +; SSE2-NEXT: js .LBB14_1 +; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: minsd %xmm1, %xmm0 +; SSE2-NEXT: retq +; SSE2-NEXT: .LBB14_1: +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: minsd %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fminimumnum_nnan: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovq %xmm0, %rax +; AVX1-NEXT: testq %rax, %rax +; AVX1-NEXT: js .LBB14_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vminsd %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; AVX1-NEXT: .LBB14_1: +; AVX1-NEXT: vmovdqa %xmm0, %xmm2 +; AVX1-NEXT: vminsd %xmm2, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX512F-LABEL: test_fminimumnum_nnan: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovq %xmm0, %rax +; AVX512F-NEXT: testq %rax, %rax +; AVX512F-NEXT: sets %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovapd %xmm1, %xmm2 +; AVX512F-NEXT: vmovsd %xmm0, %xmm2, %xmm2 {%k1} +; AVX512F-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} +; AVX512F-NEXT: vminsd %xmm2, %xmm0, %xmm0 +; AVX512F-NEXT: retq +; +; AVX512DQ-LABEL: test_fminimumnum_nnan: +; AVX512DQ: # %bb.0: +; AVX512DQ-NEXT: vfpclasssd $5, %xmm1, %k0 # k0 = isQuietNaN(xmm1) | isNegativeZero(xmm1) +; AVX512DQ-NEXT: kmovw %k0, %k1 +; AVX512DQ-NEXT: vmovapd %xmm0, %xmm2 +; AVX512DQ-NEXT: vmovsd %xmm1, %xmm2, %xmm2 {%k1} +; AVX512DQ-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1} +; AVX512DQ-NEXT: vminsd %xmm2, %xmm1, %xmm0 +; AVX512DQ-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_nnan: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxsd $16, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_nnan: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vextractps $1, %xmm0, %eax +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB14_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovapd %xmm1, %xmm2 +; X86-NEXT: jmp .LBB14_3 +; X86-NEXT: .LBB14_1: +; X86-NEXT: vmovapd %xmm0, %xmm2 +; X86-NEXT: vmovapd %xmm1, %xmm0 +; X86-NEXT: .LBB14_3: +; X86-NEXT: vminsd %xmm2, %xmm0, %xmm0 +; X86-NEXT: vmovsd %xmm0, (%esp) +; X86-NEXT: fldl (%esp) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl + %1 = tail call double @llvm.minimumnum.f64(double %x, double %y) + ret double %1 +} + +define double @test_fminimumnum_zero0(double %x, double %y) nounwind { +; SSE2-LABEL: test_fminimumnum_zero0: +; SSE2: # %bb.0: +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: cmpordsd %xmm1, %xmm0 +; SSE2-NEXT: movapd %xmm0, %xmm2 +; SSE2-NEXT: andpd %xmm1, %xmm2 +; SSE2-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE2-NEXT: andnpd %xmm1, %xmm0 +; SSE2-NEXT: orpd %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fminimumnum_zero0: +; AVX1: # %bb.0: +; AVX1-NEXT: vcmpordsd %xmm1, %xmm1, %xmm0 +; AVX1-NEXT: vminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 +; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fminimumnum_zero0: +; AVX512: # %bb.0: +; AVX512-NEXT: vcmpordsd %xmm1, %xmm1, %k1 +; AVX512-NEXT: vminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0 +; AVX512-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_zero0: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxsd $16, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_zero0: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vcmpordsd %xmm0, %xmm0, %xmm1 +; X86-NEXT: vminsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm2 +; X86-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0 +; X86-NEXT: vmovlpd %xmm0, (%esp) +; X86-NEXT: fldl (%esp) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl + %1 = tail call double @llvm.minimumnum.f64(double -0.0, double %y) + ret double %1 +} + +define double @test_fminimumnum_zero1(double %x, double %y) nounwind { +; SSE2-LABEL: test_fminimumnum_zero1: +; SSE2: # %bb.0: +; SSE2-NEXT: movapd %xmm0, %xmm1 +; SSE2-NEXT: cmpordsd %xmm0, %xmm1 +; SSE2-NEXT: movapd %xmm1, %xmm2 +; SSE2-NEXT: andpd %xmm0, %xmm2 +; SSE2-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE2-NEXT: andnpd %xmm0, %xmm1 +; SSE2-NEXT: orpd %xmm2, %xmm1 +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fminimumnum_zero1: +; AVX1: # %bb.0: +; AVX1-NEXT: vcmpordsd %xmm0, %xmm0, %xmm1 +; AVX1-NEXT: vminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 +; AVX1-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fminimumnum_zero1: +; AVX512: # %bb.0: +; AVX512-NEXT: vcmpordsd %xmm0, %xmm0, %k1 +; AVX512-NEXT: vminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vmovsd %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmovapd %xmm1, %xmm0 +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_zero1: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxsd $16, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_zero1: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vcmpordsd %xmm0, %xmm0, %xmm1 +; X86-NEXT: vminsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm2 +; X86-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0 +; X86-NEXT: vmovlpd %xmm0, (%esp) +; X86-NEXT: fldl (%esp) +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl + %1 = tail call double @llvm.minimumnum.f64(double %x, double -0.0) + ret double %1 +} + +define double @test_fminimumnum_zero2(double %x, double %y) { +; SSE2-LABEL: test_fminimumnum_zero2: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_zero2: +; AVX: # %bb.0: +; AVX-NEXT: vmovsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_zero2: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vmovsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_zero2: +; X86: # %bb.0: +; X86-NEXT: fldz +; X86-NEXT: fchs +; X86-NEXT: retl + %1 = tail call double @llvm.minimumnum.f64(double -0.0, double 0.0) + ret double %1 +} + +define float @test_fminimumnum_nsz(float %x, float %y) nounwind { +; SSE2-LABEL: test_fminimumnum_nsz: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps %xmm0, %xmm2 +; SSE2-NEXT: cmpordss %xmm0, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm3 +; SSE2-NEXT: andps %xmm0, %xmm3 +; SSE2-NEXT: minss %xmm1, %xmm0 +; SSE2-NEXT: andnps %xmm0, %xmm2 +; SSE2-NEXT: orps %xmm3, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fminimumnum_nsz: +; AVX1: # %bb.0: +; AVX1-NEXT: vminss %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fminimumnum_nsz: +; AVX512: # %bb.0: +; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vcmpordss %xmm0, %xmm0, %k1 +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmovaps %xmm1, %xmm0 +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_nsz: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxss $16, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_nsz: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm1 +; X86-NEXT: vminss {{[0-9]+}}(%esp), %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl + %1 = tail call nsz float @llvm.minimumnum.f32(float %x, float %y) + ret float %1 +} + +define float @test_fminimumnum_combine_cmps(float %x, float %y) nounwind { +; SSE2-LABEL: test_fminimumnum_combine_cmps: +; SSE2: # %bb.0: +; SSE2-NEXT: divss %xmm0, %xmm1 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movaps %xmm1, %xmm3 +; SSE2-NEXT: js .LBB19_2 +; SSE2-NEXT: # %bb.1: +; SSE2-NEXT: movaps %xmm0, %xmm3 +; SSE2-NEXT: .LBB19_2: +; SSE2-NEXT: movaps %xmm3, %xmm2 +; SSE2-NEXT: cmpordss %xmm3, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm4 +; SSE2-NEXT: andps %xmm3, %xmm4 +; SSE2-NEXT: js .LBB19_4 +; SSE2-NEXT: # %bb.3: +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: .LBB19_4: +; SSE2-NEXT: minss %xmm0, %xmm3 +; SSE2-NEXT: andnps %xmm3, %xmm2 +; SSE2-NEXT: orps %xmm4, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fminimumnum_combine_cmps: +; AVX1: # %bb.0: +; AVX1-NEXT: vdivss %xmm0, %xmm1, %xmm2 +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB19_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vmovaps %xmm2, %xmm1 +; AVX1-NEXT: jmp .LBB19_3 +; AVX1-NEXT: .LBB19_1: +; AVX1-NEXT: vmovaps %xmm0, %xmm1 +; AVX1-NEXT: vmovaps %xmm2, %xmm0 +; AVX1-NEXT: .LBB19_3: +; AVX1-NEXT: vminss %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX512F-LABEL: test_fminimumnum_combine_cmps: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX512F-NEXT: vmovd %xmm0, %eax +; AVX512F-NEXT: testl %eax, %eax +; AVX512F-NEXT: sets %al +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovaps %xmm1, %xmm2 +; AVX512F-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k1} +; AVX512F-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512F-NEXT: vminss %xmm2, %xmm0, %xmm1 +; AVX512F-NEXT: vcmpordss %xmm0, %xmm0, %k1 +; AVX512F-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512F-NEXT: vmovaps %xmm1, %xmm0 +; AVX512F-NEXT: retq +; +; AVX512DQ-LABEL: test_fminimumnum_combine_cmps: +; AVX512DQ: # %bb.0: +; AVX512DQ-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX512DQ-NEXT: vfpclassss $5, %xmm0, %k0 # k0 = isQuietNaN(xmm0) | isNegativeZero(xmm0) +; AVX512DQ-NEXT: kmovw %k0, %k1 +; AVX512DQ-NEXT: vmovaps %xmm1, %xmm2 +; AVX512DQ-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k1} +; AVX512DQ-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512DQ-NEXT: vminss %xmm2, %xmm0, %xmm0 +; AVX512DQ-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_combine_cmps: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vdivss %xmm0, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxss $16, %xmm1, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_combine_cmps: +; X86: # %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X86-NEXT: vdivss %xmm0, %xmm1, %xmm2 +; X86-NEXT: vmovd %xmm0, %eax +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB19_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovaps %xmm2, %xmm1 +; X86-NEXT: jmp .LBB19_3 +; X86-NEXT: .LBB19_1: +; X86-NEXT: vmovaps %xmm0, %xmm1 +; X86-NEXT: vmovaps %xmm2, %xmm0 +; X86-NEXT: .LBB19_3: +; X86-NEXT: vminss %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl + %1 = fdiv nnan float %y, %x + %2 = tail call float @llvm.minimumnum.f32(float %x, float %1) + ret float %2 +} + +define <2 x double> @test_fminimumnum_vector(<2 x double> %x, <2 x double> %y) { +; SSE2-LABEL: test_fminimumnum_vector: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps %xmm0, %xmm2 +; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[3,3] +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm2 +; SSE2-NEXT: pandn %xmm1, %xmm2 +; SSE2-NEXT: movdqa %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: pand %xmm1, %xmm3 +; SSE2-NEXT: por %xmm4, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm1 +; SSE2-NEXT: minpd %xmm0, %xmm1 +; SSE2-NEXT: movdqa %xmm3, %xmm0 +; SSE2-NEXT: cmpordpd %xmm3, %xmm0 +; SSE2-NEXT: andpd %xmm0, %xmm3 +; SSE2-NEXT: andnpd %xmm1, %xmm0 +; SSE2-NEXT: orpd %xmm3, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_vector: +; AVX: # %bb.0: +; AVX-NEXT: vblendvpd %xmm0, %xmm0, %xmm1, %xmm2 +; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vminpd %xmm2, %xmm0, %xmm1 +; AVX-NEXT: vcmpordpd %xmm0, %xmm0, %xmm2 +; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_vector: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxpd $16, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_vector: +; X86: # %bb.0: +; X86-NEXT: vblendvpd %xmm0, %xmm0, %xmm1, %xmm2 +; X86-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm0 +; X86-NEXT: vminpd %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordpd %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> %y) + ret <2 x double> %r +} + +define <4 x float> @test_fmaximumnum_vector(<4 x float> %x, <4 x float> %y) "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" { +; SSE2-LABEL: test_fmaximumnum_vector: +; SSE2: # %bb.0: +; SSE2-NEXT: maxps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_vector: +; AVX: # %bb.0: +; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_vector: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $17, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_vector: +; X86: # %bb.0: +; X86-NEXT: vmaxps %xmm1, %xmm0, %xmm0 +; X86-NEXT: retl + %r = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %x, <4 x float> %y) + ret <4 x float> %r +} + +define <2 x double> @test_fminimumnum_vector_zero(<2 x double> %x) { +; SSE2-LABEL: test_fminimumnum_vector_zero: +; SSE2: # %bb.0: +; SSE2-NEXT: xorpd %xmm1, %xmm1 +; SSE2-NEXT: minpd %xmm0, %xmm1 +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_vector_zero: +; AVX: # %bb.0: +; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_vector_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxpd $16, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_vector_zero: +; X86: # %bb.0: +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vminpd %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> <double 0., double 0.>) + ret <2 x double> %r +} + +define <4 x float> @test_fmaximumnum_vector_signed_zero(<4 x float> %x) { +; SSE2-LABEL: test_fmaximumnum_vector_signed_zero: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] +; SSE2-NEXT: maxps %xmm0, %xmm1 +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_vector_signed_zero: +; AVX: # %bb.0: +; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] +; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_vector_signed_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $17, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_vector_signed_zero: +; X86: # %bb.0: +; X86-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] +; X86-NEXT: vmaxps %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %x, <4 x float> <float -0., float -0., float -0., float -0.>) + ret <4 x float> %r +} + +define <2 x double> @test_fminimumnum_vector_partially_zero(<2 x double> %x) { +; SSE2-LABEL: test_fminimumnum_vector_partially_zero: +; SSE2: # %bb.0: +; SSE2-NEXT: xorpd %xmm1, %xmm1 +; SSE2-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; SSE2-NEXT: minpd %xmm0, %xmm1 +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_vector_partially_zero: +; AVX: # %bb.0: +; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_vector_partially_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX10_2-NEXT: vminmaxpd $16, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_vector_partially_zero: +; X86: # %bb.0: +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; X86-NEXT: vminpd %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> <double 0., double 5.>) + ret <2 x double> %r +} + +define <2 x double> @test_fminimumnum_vector_different_zeros(<2 x double> %x) { +; SSE2-LABEL: test_fminimumnum_vector_different_zeros: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] +; SSE2-NEXT: xorps %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtd %xmm1, %xmm3 +; SSE2-NEXT: movhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] +; SSE2-NEXT: movdqa %xmm3, %xmm1 +; SSE2-NEXT: pandn %xmm2, %xmm1 +; SSE2-NEXT: movaps %xmm0, %xmm4 +; SSE2-NEXT: andps %xmm3, %xmm4 +; SSE2-NEXT: orps %xmm1, %xmm4 +; SSE2-NEXT: pand %xmm0, %xmm2 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: por %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm1 +; SSE2-NEXT: minpd %xmm4, %xmm1 +; SSE2-NEXT: movdqa %xmm3, %xmm0 +; SSE2-NEXT: cmpordpd %xmm3, %xmm0 +; SSE2-NEXT: andpd %xmm0, %xmm3 +; SSE2-NEXT: andnpd %xmm1, %xmm0 +; SSE2-NEXT: orpd %xmm3, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_vector_different_zeros: +; AVX: # %bb.0: +; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX-NEXT: vblendvpd %xmm0, %xmm0, %xmm1, %xmm2 +; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vminpd %xmm2, %xmm0, %xmm1 +; AVX-NEXT: vcmpordpd %xmm0, %xmm0, %xmm2 +; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_vector_different_zeros: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX10_2-NEXT: vminmaxpd $16, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_vector_different_zeros: +; X86: # %bb.0: +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; X86-NEXT: vblendvpd %xmm0, %xmm0, %xmm1, %xmm2 +; X86-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm0 +; X86-NEXT: vminpd %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordpd %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> <double 0., double -0.>) + ret <2 x double> %r +} + +define <4 x float> @test_fmaximumnum_vector_non_zero(<4 x float> %x) { +; SSE2-LABEL: test_fmaximumnum_vector_non_zero: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps {{.*#+}} xmm1 = [5.0E+0,4.0E+0,3.0E+0,2.0E+0] +; SSE2-NEXT: maxps %xmm0, %xmm1 +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_vector_non_zero: +; AVX: # %bb.0: +; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [5.0E+0,4.0E+0,3.0E+0,2.0E+0] +; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_vector_non_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $17, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_vector_non_zero: +; X86: # %bb.0: +; X86-NEXT: vmovaps {{.*#+}} xmm1 = [5.0E+0,4.0E+0,3.0E+0,2.0E+0] +; X86-NEXT: vmaxps %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %x, <4 x float> <float 5., float 4., float 3., float 2.>) + ret <4 x float> %r +} + +define <2 x double> @test_fminimumnum_vector_nan(<2 x double> %x) { +; SSE2-LABEL: test_fminimumnum_vector_nan: +; SSE2: # %bb.0: +; SSE2-NEXT: xorpd %xmm2, %xmm2 +; SSE2-NEXT: xorpd %xmm1, %xmm1 +; SSE2-NEXT: movhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; SSE2-NEXT: minpd %xmm0, %xmm1 +; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1] +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_vector_nan: +; AVX: # %bb.0: +; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vmovhpd {{.*#+}} xmm2 = xmm1[0],mem[0] +; AVX-NEXT: vminpd %xmm0, %xmm2, %xmm0 +; AVX-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_vector_nan: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; AVX10_2-NEXT: vminmaxpd $16, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_vector_nan: +; X86: # %bb.0: +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0] +; X86-NEXT: vminpd %xmm0, %xmm1, %xmm0 +; X86-NEXT: vcmpordpd %xmm1, %xmm1, %xmm2 +; X86-NEXT: vblendvpd %xmm2, %xmm1, %xmm0, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> <double 0., double 0x7fff000000000000>) + ret <2 x double> %r +} + +define <2 x double> @test_fminimumnum_vector_zero_first(<2 x double> %x) { +; SSE2-LABEL: test_fminimumnum_vector_zero_first: +; SSE2: # %bb.0: +; SSE2-NEXT: xorpd %xmm1, %xmm1 +; SSE2-NEXT: minpd %xmm0, %xmm1 +; SSE2-NEXT: movapd %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_vector_zero_first: +; AVX: # %bb.0: +; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_vector_zero_first: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxpd $16, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_vector_zero_first: +; X86: # %bb.0: +; X86-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; X86-NEXT: vminpd %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> <double 0., double 0.>, <2 x double> %x) + ret <2 x double> %r +} + +define <2 x double> @test_fminimumnum_vector_signed_zero(<2 x double> %x) { +; SSE2-LABEL: test_fminimumnum_vector_signed_zero: +; SSE2: # %bb.0: +; SSE2-NEXT: movapd %xmm0, %xmm1 +; SSE2-NEXT: minpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE2-NEXT: movapd %xmm0, %xmm2 +; SSE2-NEXT: cmpordpd %xmm0, %xmm2 +; SSE2-NEXT: andpd %xmm2, %xmm0 +; SSE2-NEXT: andnpd %xmm1, %xmm2 +; SSE2-NEXT: orpd %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fminimumnum_vector_signed_zero: +; AVX: # %bb.0: +; AVX-NEXT: vcmpordpd %xmm0, %xmm0, %xmm1 +; AVX-NEXT: vminpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 +; AVX-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fminimumnum_vector_signed_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxpd $16, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fminimumnum_vector_signed_zero: +; X86: # %bb.0: +; X86-NEXT: vcmpordpd %xmm0, %xmm0, %xmm1 +; X86-NEXT: vminpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm2 +; X86-NEXT: vblendvpd %xmm1, %xmm0, %xmm2, %xmm0 +; X86-NEXT: retl + %r = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %x, <2 x double> <double -0., double -0.>) + ret <2 x double> %r +} + +define <4 x float> @test_fmaximumnum_vector_signed_zero_first(<4 x float> %x) { +; SSE2-LABEL: test_fmaximumnum_vector_signed_zero_first: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] +; SSE2-NEXT: maxps %xmm0, %xmm1 +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_vector_signed_zero_first: +; AVX: # %bb.0: +; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] +; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_vector_signed_zero_first: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxps $17, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_vector_signed_zero_first: +; X86: # %bb.0: +; X86-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] +; X86-NEXT: vmaxps %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> <float -0., float -0., float -0., float -0.>, <4 x float> %x) + ret <4 x float> %r +} + +define <4 x float> @test_fmaximumnum_vector_zero(<4 x float> %x) { +; SSE2-LABEL: test_fmaximumnum_vector_zero: +; SSE2: # %bb.0: +; SSE2-NEXT: xorps %xmm1, %xmm1 +; SSE2-NEXT: movaps %xmm0, %xmm2 +; SSE2-NEXT: maxps %xmm1, %xmm2 +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: cmpordps %xmm0, %xmm1 +; SSE2-NEXT: andps %xmm1, %xmm0 +; SSE2-NEXT: andnps %xmm2, %xmm1 +; SSE2-NEXT: orps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; AVX-LABEL: test_fmaximumnum_vector_zero: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm1 +; AVX-NEXT: vcmpordps %xmm0, %xmm0, %xmm2 +; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_vector_zero: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxps $17, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_vector_zero: +; X86: # %bb.0: +; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X86-NEXT: vmaxps %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordps %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %r = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %x, <4 x float> <float 0., float 0., float 0., float 0.>) + ret <4 x float> %r +} + +; PR77805: Check that signed zeroes are handled correctly in this case (FIXME) +define <4 x float> @test_fmaximumnum_v4f32_splat(<4 x float> %x, float %y) { +; SSE2-LABEL: test_fmaximumnum_v4f32_splat: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0] +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm3 +; SSE2-NEXT: pandn %xmm0, %xmm3 +; SSE2-NEXT: movaps %xmm1, %xmm4 +; SSE2-NEXT: andps %xmm2, %xmm4 +; SSE2-NEXT: orps %xmm3, %xmm4 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: andnps %xmm1, %xmm2 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: maxps %xmm4, %xmm1 +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: cmpordps %xmm0, %xmm2 +; SSE2-NEXT: andps %xmm2, %xmm0 +; SSE2-NEXT: andnps %xmm1, %xmm2 +; SSE2-NEXT: orps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_v4f32_splat: +; AVX1: # %bb.0: +; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0,0,0] +; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm0, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vmaxps %xmm2, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordps %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fmaximumnum_v4f32_splat: +; AVX512: # %bb.0: +; AVX512-NEXT: vbroadcastss %xmm1, %xmm1 +; AVX512-NEXT: vblendvps %xmm0, %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vblendvps %xmm0, %xmm0, %xmm1, %xmm0 +; AVX512-NEXT: vmaxps %xmm2, %xmm0, %xmm1 +; AVX512-NEXT: vcmpordps %xmm0, %xmm0, %xmm2 +; AVX512-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_v4f32_splat: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vbroadcastss %xmm1, %xmm1 +; AVX10_2-NEXT: vminmaxps $17, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_v4f32_splat: +; X86: # %bb.0: +; X86-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm1 +; X86-NEXT: vblendvps %xmm0, %xmm1, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm0, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmaxps %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordps %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: retl + %splatinsert = insertelement <4 x float> poison, float %y, i64 0 + %vec = shufflevector <4 x float> %splatinsert, <4 x float> poison, <4 x i32> zeroinitializer + %r = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %x, <4 x float> %vec) readnone + ret <4 x float> %r +} + +define <4 x half> @test_fmaximumnum_v4f16(<4 x half> %x, <4 x half> %y) nounwind { +; SSE2-LABEL: test_fmaximumnum_v4f16: +; SSE2: # %bb.0: +; SSE2-NEXT: subq $104, %rsp +; SSE2-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: psrld $16, %xmm0 +; SSE2-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: psrld $16, %xmm0 +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movd {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 4-byte Folded Reload +; SSE2-NEXT: # xmm4 = mem[0],zero,zero,zero +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: js .LBB33_2 +; SSE2-NEXT: # %bb.1: +; SSE2-NEXT: movdqa %xmm4, %xmm2 +; SSE2-NEXT: .LBB33_2: +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: cmpordss %xmm2, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm3 +; SSE2-NEXT: andps %xmm2, %xmm3 +; SSE2-NEXT: js .LBB33_4 +; SSE2-NEXT: # %bb.3: +; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: .LBB33_4: +; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] +; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload +; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] +; SSE2-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: maxss %xmm4, %xmm2 +; SSE2-NEXT: andnps %xmm2, %xmm0 +; SSE2-NEXT: orps %xmm3, %xmm0 +; SSE2-NEXT: callq __truncsfhf2@PLT +; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movd {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 4-byte Folded Reload +; SSE2-NEXT: # xmm4 = mem[0],zero,zero,zero +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: js .LBB33_6 +; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: movdqa %xmm4, %xmm2 +; SSE2-NEXT: .LBB33_6: +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: cmpordss %xmm2, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm3 +; SSE2-NEXT: andps %xmm2, %xmm3 +; SSE2-NEXT: js .LBB33_8 +; SSE2-NEXT: # %bb.7: +; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: .LBB33_8: +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; SSE2-NEXT: psrlq $48, %xmm1 +; SSE2-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: movdqa (%rsp), %xmm1 # 16-byte Reload +; SSE2-NEXT: psrlq $48, %xmm1 +; SSE2-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill +; SSE2-NEXT: maxss %xmm4, %xmm2 +; SSE2-NEXT: andnps %xmm2, %xmm0 +; SSE2-NEXT: orps %xmm3, %xmm0 +; SSE2-NEXT: callq __truncsfhf2@PLT +; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movd {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 4-byte Folded Reload +; SSE2-NEXT: # xmm4 = mem[0],zero,zero,zero +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: js .LBB33_10 +; SSE2-NEXT: # %bb.9: +; SSE2-NEXT: movdqa %xmm4, %xmm2 +; SSE2-NEXT: .LBB33_10: +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: cmpordss %xmm2, %xmm1 +; SSE2-NEXT: movaps %xmm1, %xmm3 +; SSE2-NEXT: andps %xmm2, %xmm3 +; SSE2-NEXT: js .LBB33_12 +; SSE2-NEXT: # %bb.11: +; SSE2-NEXT: movdqa %xmm0, %xmm4 +; SSE2-NEXT: .LBB33_12: +; SSE2-NEXT: maxss %xmm4, %xmm2 +; SSE2-NEXT: andnps %xmm2, %xmm1 +; SSE2-NEXT: orps %xmm3, %xmm1 +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: callq __truncsfhf2@PLT +; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movss %xmm0, (%rsp) # 4-byte Spill +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; SSE2-NEXT: callq __extendhfsf2@PLT +; SSE2-NEXT: movd (%rsp), %xmm4 # 4-byte Folded Reload +; SSE2-NEXT: # xmm4 = mem[0],zero,zero,zero +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: movd %xmm0, %eax +; SSE2-NEXT: testl %eax, %eax +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: js .LBB33_14 +; SSE2-NEXT: # %bb.13: +; SSE2-NEXT: movdqa %xmm4, %xmm2 +; SSE2-NEXT: .LBB33_14: +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: cmpordss %xmm2, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm3 +; SSE2-NEXT: andps %xmm2, %xmm3 +; SSE2-NEXT: js .LBB33_16 +; SSE2-NEXT: # %bb.15: +; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: .LBB33_16: +; SSE2-NEXT: maxss %xmm4, %xmm2 +; SSE2-NEXT: andnps %xmm2, %xmm0 +; SSE2-NEXT: orps %xmm3, %xmm0 +; SSE2-NEXT: callq __truncsfhf2@PLT +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; SSE2-NEXT: punpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload +; SSE2-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: addq $104, %rsp +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_v4f16: +; AVX1: # %bb.0: +; AVX1-NEXT: subq $120, %rsp +; AVX1-NEXT: vmovaps %xmm0, %xmm2 +; AVX1-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX1-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] +; AVX1-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vpsrld $16, %xmm2, %xmm0 +; AVX1-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovaps %xmm1, (%rsp) # 16-byte Spill +; AVX1-NEXT: vpsrld $16, %xmm1, %xmm0 +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB33_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload +; AVX1-NEXT: jmp .LBB33_3 +; AVX1-NEXT: .LBB33_1: +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX1-NEXT: vmovdqa %xmm0, %xmm2 +; AVX1-NEXT: .LBB33_3: +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX1-NEXT: vpsrlq $48, %xmm0, %xmm0 +; AVX1-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload +; AVX1-NEXT: vpsrlq $48, %xmm0, %xmm0 +; AVX1-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmaxss %xmm1, %xmm2, %xmm0 +; AVX1-NEXT: vcmpordss %xmm2, %xmm2, %xmm1 +; AVX1-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: callq __truncsfhf2@PLT +; AVX1-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB33_4 +; AVX1-NEXT: # %bb.5: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa (%rsp), %xmm2 # 16-byte Reload +; AVX1-NEXT: jmp .LBB33_6 +; AVX1-NEXT: .LBB33_4: +; AVX1-NEXT: vmovdqa (%rsp), %xmm1 # 16-byte Reload +; AVX1-NEXT: vmovdqa %xmm0, %xmm2 +; AVX1-NEXT: .LBB33_6: +; AVX1-NEXT: vmaxss %xmm1, %xmm2, %xmm0 +; AVX1-NEXT: vcmpordss %xmm2, %xmm2, %xmm1 +; AVX1-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: callq __truncsfhf2@PLT +; AVX1-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB33_7 +; AVX1-NEXT: # %bb.8: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa (%rsp), %xmm2 # 16-byte Reload +; AVX1-NEXT: jmp .LBB33_9 +; AVX1-NEXT: .LBB33_7: +; AVX1-NEXT: vmovdqa (%rsp), %xmm1 # 16-byte Reload +; AVX1-NEXT: vmovdqa %xmm0, %xmm2 +; AVX1-NEXT: .LBB33_9: +; AVX1-NEXT: vmaxss %xmm1, %xmm2, %xmm0 +; AVX1-NEXT: vcmpordss %xmm2, %xmm2, %xmm1 +; AVX1-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: callq __truncsfhf2@PLT +; AVX1-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill +; AVX1-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX1-NEXT: callq __extendhfsf2@PLT +; AVX1-NEXT: vmovd %xmm0, %eax +; AVX1-NEXT: testl %eax, %eax +; AVX1-NEXT: js .LBB33_10 +; AVX1-NEXT: # %bb.11: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload +; AVX1-NEXT: jmp .LBB33_12 +; AVX1-NEXT: .LBB33_10: +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX1-NEXT: vmovdqa %xmm0, %xmm2 +; AVX1-NEXT: .LBB33_12: +; AVX1-NEXT: vmaxss %xmm1, %xmm2, %xmm0 +; AVX1-NEXT: vcmpordss %xmm2, %xmm2, %xmm1 +; AVX1-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: callq __truncsfhf2@PLT +; AVX1-NEXT: vmovdqa (%rsp), %xmm1 # 16-byte Reload +; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX1-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload +; AVX1-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] +; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero +; AVX1-NEXT: addq $120, %rsp +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fmaximumnum_v4f16: +; AVX512: # %bb.0: +; AVX512-NEXT: subq $88, %rsp +; AVX512-NEXT: vmovdqa %xmm1, %xmm4 +; AVX512-NEXT: vmovdqa %xmm0, %xmm6 +; AVX512-NEXT: vpsrldq {{.*#+}} xmm0 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm0 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vpsrldq {{.*#+}} xmm2 = xmm6[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm2 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm1 +; AVX512-NEXT: vmovaps %xmm1, (%rsp) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm2 +; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm2 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: movzwl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax +; AVX512-NEXT: vmovd %eax, %xmm2 +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm9 +; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 +; AVX512-NEXT: vxorps %xmm10, %xmm10, %xmm10 +; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm10[1,2,3] +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0 +; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm4[3,3,3,3] +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm2 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm6[3,3,3,3] +; AVX512-NEXT: vcvtph2ps %xmm3, %xmm3 +; AVX512-NEXT: vucomiss %xmm3, %xmm3 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm2, %xmm3, %xmm3 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm1 +; AVX512-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm3 +; AVX512-NEXT: vmovss %xmm3, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm1 +; AVX512-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm3 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm3, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm2 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 +; AVX512-NEXT: vmulss %xmm2, %xmm9, %xmm2 +; AVX512-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0],xmm10[1,2,3] +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm1 +; AVX512-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vmovd %xmm1, %eax +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] +; AVX512-NEXT: vpsrldq {{.*#+}} xmm0 = xmm4[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm0 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vpsrldq {{.*#+}} xmm3 = xmm6[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm3, %xmm3 +; AVX512-NEXT: vucomiss %xmm3, %xmm3 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm1 +; AVX512-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm5 +; AVX512-NEXT: vmovss %xmm5, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm3 +; AVX512-NEXT: vucomiss %xmm3, %xmm5 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm5, %xmm3, %xmm3 {%k1} +; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm4[1,0] +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm0 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vshufpd {{.*#+}} xmm5 = xmm6[1,0] +; AVX512-NEXT: vcvtph2ps %xmm5, %xmm5 +; AVX512-NEXT: vucomiss %xmm5, %xmm5 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm0, %xmm5, %xmm5 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm5, %xmm15 +; AVX512-NEXT: vcvtph2ps %xmm15, %xmm5 +; AVX512-NEXT: vmovss %xmm5, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm5 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm5, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm3 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm3, %xmm3 +; AVX512-NEXT: vmulss %xmm3, %xmm9, %xmm3 +; AVX512-NEXT: vblendps {{.*#+}} xmm3 = xmm3[0],xmm10[1,2,3] +; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm1 +; AVX512-NEXT: vmovdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vmovd %xmm1, %eax +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 +; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm10[1,2,3] +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vmovd %xmm0, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm3 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX512-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vpshuflw {{.*#+}} xmm0 = xmm4[3,3,3,3,4,5,6,7] +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm0 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vpshuflw {{.*#+}} xmm2 = xmm6[3,3,3,3,4,5,6,7] +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm2 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm11 +; AVX512-NEXT: vcvtph2ps %xmm11, %xmm3 +; AVX512-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm3 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm3, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm4[1,1,3,3] +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm0 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovshdup {{.*#+}} xmm3 = xmm6[1,1,3,3] +; AVX512-NEXT: vcvtph2ps %xmm3, %xmm3 +; AVX512-NEXT: vucomiss %xmm3, %xmm3 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm0, %xmm3, %xmm3 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm3, %xmm7 +; AVX512-NEXT: vcvtph2ps %xmm7, %xmm3 +; AVX512-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm12 +; AVX512-NEXT: vcvtph2ps %xmm12, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm3 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm3, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm2 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 +; AVX512-NEXT: vmulss %xmm2, %xmm9, %xmm2 +; AVX512-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0],xmm10[1,2,3] +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm14 +; AVX512-NEXT: vmovd %xmm14, %eax +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 +; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm10[1,2,3] +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm13 +; AVX512-NEXT: vmovd %xmm13, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] +; AVX512-NEXT: vcvtph2ps %xmm4, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm0 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vcvtph2ps %xmm6, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm2 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm3 +; AVX512-NEXT: vcvtph2ps %xmm3, %xmm1 +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm8 +; AVX512-NEXT: vcvtph2ps %xmm8, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vpshuflw {{.*#+}} xmm1 = xmm4[1,1,1,1,4,5,6,7] +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm1 +; AVX512-NEXT: vucomiss %xmm1, %xmm1 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vpshuflw {{.*#+}} xmm4 = xmm6[1,1,1,1,4,5,6,7] +; AVX512-NEXT: vcvtph2ps %xmm4, %xmm4 +; AVX512-NEXT: vucomiss %xmm4, %xmm4 +; AVX512-NEXT: setp %al +; AVX512-NEXT: kmovw %eax, %k2 +; AVX512-NEXT: vmovss %xmm1, %xmm4, %xmm4 {%k2} +; AVX512-NEXT: vcvtps2ph $4, %xmm4, %xmm4 +; AVX512-NEXT: vcvtph2ps %xmm4, %xmm6 +; AVX512-NEXT: vmovss %xmm6, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm1, %xmm1 +; AVX512-NEXT: vcvtph2ps %xmm1, %xmm0 +; AVX512-NEXT: vucomiss %xmm0, %xmm6 +; AVX512-NEXT: seta %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: vmovss %xmm6, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm2 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm2, %xmm2 +; AVX512-NEXT: vmulss %xmm2, %xmm9, %xmm2 +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512-NEXT: vcvtph2ps %xmm0, %xmm0 +; AVX512-NEXT: vmulss %xmm0, %xmm9, %xmm0 +; AVX512-NEXT: vblendps {{.*#+}} xmm2 = xmm2[0],xmm10[1,2,3] +; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm10[1,2,3] +; AVX512-NEXT: vcvtps2ph $4, %xmm2, %xmm9 +; AVX512-NEXT: vmovd %xmm9, %eax +; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm10 +; AVX512-NEXT: vmovd %xmm10, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] +; AVX512-NEXT: vpunpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm6 # 16-byte Folded Reload +; AVX512-NEXT: # xmm6 = xmm0[0],mem[0] +; AVX512-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm0, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm2, %eax +; AVX512-NEXT: vmovd %xmm15, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm2 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm5 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm2[0],xmm5[1],xmm2[1],xmm5[2],xmm2[2],xmm5[3],xmm2[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; AVX512-NEXT: vmovd %xmm11, %eax +; AVX512-NEXT: vmovd %xmm7, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm2 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm5 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm2[0],xmm5[1],xmm2[1],xmm5[2],xmm2[2],xmm5[3],xmm2[3] +; AVX512-NEXT: vmovd %xmm3, %eax +; AVX512-NEXT: vmovd %xmm4, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm3 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm4 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] +; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] +; AVX512-NEXT: vpxor %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpcmpeqw %xmm0, %xmm2, %xmm3 +; AVX512-NEXT: vpblendvb %xmm3, %xmm2, %xmm6, %xmm2 +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm3, %eax +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm3, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm3 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm4 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm4, %eax +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm4, %ecx +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm4 +; AVX512-NEXT: vpinsrw $0, %ecx, %xmm0, %xmm5 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] +; AVX512-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload +; AVX512-NEXT: vmovd %xmm4, %eax +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm4 +; AVX512-NEXT: vmovd %xmm12, %eax +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm5 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3] +; AVX512-NEXT: vmovd %xmm8, %eax +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm5 +; AVX512-NEXT: vmovd %xmm1, %eax +; AVX512-NEXT: vpinsrw $0, %eax, %xmm0, %xmm1 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3] +; AVX512-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1] +; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] +; AVX512-NEXT: vpcmpeqw %xmm0, %xmm1, %xmm0 +; AVX512-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0 +; AVX512-NEXT: vcvtph2ps %xmm10, %xmm1 +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: movl $65535, %ecx # imm = 0xFFFF +; AVX512-NEXT: movl $0, %edx +; AVX512-NEXT: cmovel %ecx, %edx +; AVX512-NEXT: vcvtph2ps %xmm9, %xmm1 +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: movl $0, %esi +; AVX512-NEXT: cmovel %ecx, %esi +; AVX512-NEXT: vcvtph2ps %xmm13, %xmm1 +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: movl $0, %edi +; AVX512-NEXT: cmovel %ecx, %edi +; AVX512-NEXT: vcvtph2ps %xmm14, %xmm1 +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: movl $0, %r8d +; AVX512-NEXT: cmovel %ecx, %r8d +; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: movl $0, %r9d +; AVX512-NEXT: cmovel %ecx, %r9d +; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: movl $0, %r10d +; AVX512-NEXT: cmovel %ecx, %r10d +; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: movl $0, %r11d +; AVX512-NEXT: cmovel %ecx, %r11d +; AVX512-NEXT: vcvtph2ps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload +; AVX512-NEXT: vucomiss %xmm2, %xmm1 +; AVX512-NEXT: vmovd %esi, %xmm1 +; AVX512-NEXT: vpinsrw $1, %edx, %xmm1, %xmm1 +; AVX512-NEXT: vpinsrw $2, %edi, %xmm1, %xmm1 +; AVX512-NEXT: vpinsrw $3, %r8d, %xmm1, %xmm1 +; AVX512-NEXT: vpinsrw $4, %r9d, %xmm1, %xmm1 +; AVX512-NEXT: vpinsrw $5, %r10d, %xmm1, %xmm1 +; AVX512-NEXT: vpinsrw $6, %r11d, %xmm1, %xmm1 +; AVX512-NEXT: cmovel %ecx, %eax +; AVX512-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1 +; AVX512-NEXT: vpblendvb %xmm1, %xmm0, %xmm6, %xmm0 +; AVX512-NEXT: addq $88, %rsp +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_v4f16: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxph $17, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_v4f16: +; X86: # %bb.0: +; X86-NEXT: subl $164, %esp +; X86-NEXT: vmovdqa %xmm0, %xmm2 +; X86-NEXT: vmovdqu %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vpsrlq $48, %xmm0, %xmm0 +; X86-NEXT: vmovdqu %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovshdup {{.*#+}} xmm0 = xmm2[1,1,3,3] +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovshdup {{.*#+}} xmm0 = xmm1[1,1,3,3] +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vpsrlq $48, %xmm1, %xmm0 +; X86-NEXT: vmovdqu %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vpsrld $16, %xmm2, %xmm0 +; X86-NEXT: vmovdqu %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vpsrld $16, %xmm1, %xmm0 +; X86-NEXT: vmovdqu %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vpextrw $0, %xmm1, (%esp) +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vpextrw $0, %xmm0, (%esp) +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vpextrw $0, %xmm0, (%esp) +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vpextrw $0, %xmm0, (%esp) +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero +; X86-NEXT: vmovd %xmm2, %eax +; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB33_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovdqa %xmm2, %xmm1 +; X86-NEXT: jmp .LBB33_3 +; X86-NEXT: .LBB33_1: +; X86-NEXT: vmovdqa %xmm0, %xmm1 +; X86-NEXT: vmovdqa %xmm2, %xmm0 +; X86-NEXT: .LBB33_3: +; X86-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X86-NEXT: vmovd %xmm1, %eax +; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB33_4 +; X86-NEXT: # %bb.5: +; X86-NEXT: vmovdqa %xmm1, %xmm2 +; X86-NEXT: jmp .LBB33_6 +; X86-NEXT: .LBB33_4: +; X86-NEXT: vmovdqa %xmm0, %xmm2 +; X86-NEXT: vmovdqa %xmm1, %xmm0 +; X86-NEXT: .LBB33_6: +; X86-NEXT: vmaxss %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: calll __truncsfhf2 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: calll __truncsfhf2 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vpextrw $0, %xmm0, (%esp) +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vpextrw $0, %xmm0, (%esp) +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vpextrw $0, %xmm0, (%esp) +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vpextrw $0, %xmm0, (%esp) +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X86-NEXT: vmovd %xmm1, %eax +; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB33_7 +; X86-NEXT: # %bb.8: +; X86-NEXT: vmovdqa %xmm1, %xmm2 +; X86-NEXT: jmp .LBB33_9 +; X86-NEXT: .LBB33_7: +; X86-NEXT: vmovdqa %xmm0, %xmm2 +; X86-NEXT: vmovdqa %xmm1, %xmm0 +; X86-NEXT: .LBB33_9: +; X86-NEXT: vmaxss %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: calll __extendhfsf2 +; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload +; X86-NEXT: fstps {{[0-9]+}}(%esp) +; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero +; X86-NEXT: vmovd %xmm1, %eax +; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: testl %eax, %eax +; X86-NEXT: js .LBB33_10 +; X86-NEXT: # %bb.11: +; X86-NEXT: vmovdqa %xmm1, %xmm2 +; X86-NEXT: jmp .LBB33_12 +; X86-NEXT: .LBB33_10: +; X86-NEXT: vmovdqa %xmm0, %xmm2 +; X86-NEXT: vmovdqa %xmm1, %xmm0 +; X86-NEXT: .LBB33_12: +; X86-NEXT: vmaxss %xmm2, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: calll __truncsfhf2 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vmovd %xmm0, (%esp) +; X86-NEXT: calll __truncsfhf2 +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 # 16-byte Reload +; X86-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 # 16-byte Reload +; X86-NEXT: vpunpcklwd {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload +; X86-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] +; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero +; X86-NEXT: addl $164, %esp +; X86-NEXT: retl + %r = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %x, <4 x half> %y) + ret <4 x half> %r +} + +define <4 x bfloat> @test_fmaximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) nounwind { +; SSE2-LABEL: test_fmaximumnum_v4bf16: +; SSE2: # %bb.0: +; SSE2-NEXT: pushq %rbp +; SSE2-NEXT: pushq %r15 +; SSE2-NEXT: pushq %r14 +; SSE2-NEXT: pushq %rbx +; SSE2-NEXT: subq $56, %rsp +; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: movdqa %xmm0, %xmm5 +; SSE2-NEXT: pextrw $0, %xmm1, %r14d +; SSE2-NEXT: pextrw $0, %xmm0, %r15d +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: psrld $16, %xmm0 +; SSE2-NEXT: pextrw $0, %xmm0, %eax +; SSE2-NEXT: movdqa %xmm5, %xmm0 +; SSE2-NEXT: psrld $16, %xmm0 +; SSE2-NEXT: pextrw $0, %xmm0, %ecx +; SSE2-NEXT: shll $16, %ecx +; SSE2-NEXT: movd %ecx, %xmm3 +; SSE2-NEXT: shll $16, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: testl %ecx, %ecx +; SSE2-NEXT: movdqa %xmm3, %xmm1 +; SSE2-NEXT: js .LBB34_2 +; SSE2-NEXT: # %bb.1: +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: .LBB34_2: +; SSE2-NEXT: movdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1,1,1] +; SSE2-NEXT: movdqa %xmm5, (%rsp) # 16-byte Spill +; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,1,1,1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: cmpordss %xmm1, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm6 +; SSE2-NEXT: andps %xmm1, %xmm6 +; SSE2-NEXT: js .LBB34_4 +; SSE2-NEXT: # %bb.3: +; SSE2-NEXT: movdqa %xmm3, %xmm2 +; SSE2-NEXT: .LBB34_4: +; SSE2-NEXT: pextrw $0, %xmm4, %ebp +; SSE2-NEXT: pextrw $0, %xmm5, %ebx +; SSE2-NEXT: maxss %xmm2, %xmm1 +; SSE2-NEXT: andnps %xmm1, %xmm0 +; SSE2-NEXT: orps %xmm6, %xmm0 +; SSE2-NEXT: callq __truncsfbf2@PLT +; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: shll $16, %r15d +; SSE2-NEXT: movd %r15d, %xmm3 +; SSE2-NEXT: shll $16, %r14d +; SSE2-NEXT: movd %r14d, %xmm2 +; SSE2-NEXT: testl %r15d, %r15d +; SSE2-NEXT: movdqa %xmm3, %xmm1 +; SSE2-NEXT: js .LBB34_6 +; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: movdqa %xmm2, %xmm1 +; SSE2-NEXT: .LBB34_6: +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload +; SSE2-NEXT: psrlq $48, %xmm5 +; SSE2-NEXT: movdqa (%rsp), %xmm6 # 16-byte Reload +; SSE2-NEXT: psrlq $48, %xmm6 +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: cmpordss %xmm1, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm4 +; SSE2-NEXT: andps %xmm1, %xmm4 +; SSE2-NEXT: js .LBB34_8 +; SSE2-NEXT: # %bb.7: +; SSE2-NEXT: movdqa %xmm3, %xmm2 +; SSE2-NEXT: .LBB34_8: +; SSE2-NEXT: pextrw $0, %xmm5, %r15d +; SSE2-NEXT: pextrw $0, %xmm6, %r14d +; SSE2-NEXT: maxss %xmm2, %xmm1 +; SSE2-NEXT: andnps %xmm1, %xmm0 +; SSE2-NEXT: orps %xmm4, %xmm0 +; SSE2-NEXT: callq __truncsfbf2@PLT +; SSE2-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; SSE2-NEXT: shll $16, %ebx +; SSE2-NEXT: movd %ebx, %xmm1 +; SSE2-NEXT: shll $16, %ebp +; SSE2-NEXT: movd %ebp, %xmm3 +; SSE2-NEXT: testl %ebx, %ebx +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: js .LBB34_10 +; SSE2-NEXT: # %bb.9: +; SSE2-NEXT: movdqa %xmm3, %xmm2 +; SSE2-NEXT: .LBB34_10: +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: cmpordss %xmm2, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm4 +; SSE2-NEXT: andps %xmm2, %xmm4 +; SSE2-NEXT: js .LBB34_12 +; SSE2-NEXT: # %bb.11: +; SSE2-NEXT: movdqa %xmm1, %xmm3 +; SSE2-NEXT: .LBB34_12: +; SSE2-NEXT: maxss %xmm3, %xmm2 +; SSE2-NEXT: andnps %xmm2, %xmm0 +; SSE2-NEXT: orps %xmm4, %xmm0 +; SSE2-NEXT: callq __truncsfbf2@PLT +; SSE2-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill +; SSE2-NEXT: shll $16, %r14d +; SSE2-NEXT: movd %r14d, %xmm1 +; SSE2-NEXT: shll $16, %r15d +; SSE2-NEXT: movd %r15d, %xmm3 +; SSE2-NEXT: testl %r14d, %r14d +; SSE2-NEXT: movdqa %xmm1, %xmm2 +; SSE2-NEXT: js .LBB34_14 +; SSE2-NEXT: # %bb.13: +; SSE2-NEXT: movdqa %xmm3, %xmm2 +; SSE2-NEXT: .LBB34_14: +; SSE2-NEXT: movdqa %xmm2, %xmm0 +; SSE2-NEXT: cmpordss %xmm2, %xmm0 +; SSE2-NEXT: movaps %xmm0, %xmm4 +; SSE2-NEXT: andps %xmm2, %xmm4 +; SSE2-NEXT: js .LBB34_16 +; SSE2-NEXT: # %bb.15: +; SSE2-NEXT: movdqa %xmm1, %xmm3 +; SSE2-NEXT: .LBB34_16: +; SSE2-NEXT: maxss %xmm3, %xmm2 +; SSE2-NEXT: andnps %xmm2, %xmm0 +; SSE2-NEXT: orps %xmm4, %xmm0 +; SSE2-NEXT: callq __truncsfbf2@PLT +; SSE2-NEXT: movdqa (%rsp), %xmm1 # 16-byte Reload +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; SSE2-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; SSE2-NEXT: punpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload +; SSE2-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: addq $56, %rsp +; SSE2-NEXT: popq %rbx +; SSE2-NEXT: popq %r14 +; SSE2-NEXT: popq %r15 +; SSE2-NEXT: popq %rbp +; SSE2-NEXT: retq +; +; AVX1-LABEL: test_fmaximumnum_v4bf16: +; AVX1: # %bb.0: +; AVX1-NEXT: pushq %rbp +; AVX1-NEXT: pushq %r15 +; AVX1-NEXT: pushq %r14 +; AVX1-NEXT: pushq %r13 +; AVX1-NEXT: pushq %r12 +; AVX1-NEXT: pushq %rbx +; AVX1-NEXT: subq $56, %rsp +; AVX1-NEXT: vpsrlq $48, %xmm0, %xmm2 +; AVX1-NEXT: vpsrlq $48, %xmm1, %xmm3 +; AVX1-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] +; AVX1-NEXT: vpextrw $0, %xmm4, %ebx +; AVX1-NEXT: vmovshdup {{.*#+}} xmm4 = xmm1[1,1,3,3] +; AVX1-NEXT: vpextrw $0, %xmm4, %ebp +; AVX1-NEXT: vpextrw $0, %xmm0, %r12d +; AVX1-NEXT: vpextrw $0, %xmm1, %r13d +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0 +; AVX1-NEXT: vpextrw $0, %xmm0, %eax +; AVX1-NEXT: vpsrld $16, %xmm1, %xmm0 +; AVX1-NEXT: vpextrw $0, %xmm0, %ecx +; AVX1-NEXT: shll $16, %ecx +; AVX1-NEXT: vmovd %ecx, %xmm0 +; AVX1-NEXT: shll $16, %eax +; AVX1-NEXT: vmovd %eax, %xmm4 +; AVX1-NEXT: js .LBB34_1 +; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: vmovdqa %xmm4, %xmm1 +; AVX1-NEXT: jmp .LBB34_3 +; AVX1-NEXT: .LBB34_1: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa %xmm4, %xmm0 +; AVX1-NEXT: .LBB34_3: +; AVX1-NEXT: vpextrw $0, %xmm2, %r14d +; AVX1-NEXT: vpextrw $0, %xmm3, %r15d +; AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: callq __truncsfbf2@PLT +; AVX1-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: shll $16, %r13d +; AVX1-NEXT: vmovd %r13d, %xmm0 +; AVX1-NEXT: shll $16, %r12d +; AVX1-NEXT: vmovd %r12d, %xmm2 +; AVX1-NEXT: js .LBB34_4 +; AVX1-NEXT: # %bb.5: +; AVX1-NEXT: vmovdqa %xmm2, %xmm1 +; AVX1-NEXT: jmp .LBB34_6 +; AVX1-NEXT: .LBB34_4: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa %xmm2, %xmm0 +; AVX1-NEXT: .LBB34_6: +; AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: callq __truncsfbf2@PLT +; AVX1-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX1-NEXT: shll $16, %ebp +; AVX1-NEXT: vmovd %ebp, %xmm0 +; AVX1-NEXT: shll $16, %ebx +; AVX1-NEXT: vmovd %ebx, %xmm2 +; AVX1-NEXT: js .LBB34_7 +; AVX1-NEXT: # %bb.8: +; AVX1-NEXT: vmovdqa %xmm2, %xmm1 +; AVX1-NEXT: jmp .LBB34_9 +; AVX1-NEXT: .LBB34_7: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa %xmm2, %xmm0 +; AVX1-NEXT: .LBB34_9: +; AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: callq __truncsfbf2@PLT +; AVX1-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill +; AVX1-NEXT: shll $16, %r15d +; AVX1-NEXT: vmovd %r15d, %xmm0 +; AVX1-NEXT: shll $16, %r14d +; AVX1-NEXT: vmovd %r14d, %xmm2 +; AVX1-NEXT: js .LBB34_10 +; AVX1-NEXT: # %bb.11: +; AVX1-NEXT: vmovdqa %xmm2, %xmm1 +; AVX1-NEXT: jmp .LBB34_12 +; AVX1-NEXT: .LBB34_10: +; AVX1-NEXT: vmovdqa %xmm0, %xmm1 +; AVX1-NEXT: vmovdqa %xmm2, %xmm0 +; AVX1-NEXT: .LBB34_12: +; AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: callq __truncsfbf2@PLT +; AVX1-NEXT: vmovdqa (%rsp), %xmm1 # 16-byte Reload +; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX1-NEXT: vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload +; AVX1-NEXT: vpunpcklwd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload +; AVX1-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] +; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero +; AVX1-NEXT: addq $56, %rsp +; AVX1-NEXT: popq %rbx +; AVX1-NEXT: popq %r12 +; AVX1-NEXT: popq %r13 +; AVX1-NEXT: popq %r14 +; AVX1-NEXT: popq %r15 +; AVX1-NEXT: popq %rbp +; AVX1-NEXT: retq +; +; AVX512-LABEL: test_fmaximumnum_v4bf16: +; AVX512: # %bb.0: +; AVX512-NEXT: pushq %rbp +; AVX512-NEXT: pushq %r15 +; AVX512-NEXT: pushq %r14 +; AVX512-NEXT: pushq %r13 +; AVX512-NEXT: pushq %r12 +; AVX512-NEXT: pushq %rbx +; AVX512-NEXT: pushq %rax +; AVX512-NEXT: vmovq %xmm1, %r13 +; AVX512-NEXT: movq %r13, %rbx +; AVX512-NEXT: shrq $32, %rbx +; AVX512-NEXT: vmovq %xmm0, %rbp +; AVX512-NEXT: movq %rbp, %r14 +; AVX512-NEXT: shrq $32, %r14 +; AVX512-NEXT: movq %r13, %r15 +; AVX512-NEXT: shrq $48, %r15 +; AVX512-NEXT: movq %rbp, %r12 +; AVX512-NEXT: shrq $48, %r12 +; AVX512-NEXT: movl %ebp, %eax +; AVX512-NEXT: andl $-65536, %eax # imm = 0xFFFF0000 +; AVX512-NEXT: sets %cl +; AVX512-NEXT: kmovw %ecx, %k1 +; AVX512-NEXT: movl %r13d, %ecx +; AVX512-NEXT: andl $-65536, %ecx # imm = 0xFFFF0000 +; AVX512-NEXT: vmovd %ecx, %xmm1 +; AVX512-NEXT: vmovd %eax, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, %xmm2 +; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: vcmpordss %xmm1, %xmm1, %k1 +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: callq __truncsfbf2@PLT +; AVX512-NEXT: vpextrw $0, %xmm0, {{[0-9]+}}(%rsp) +; AVX512-NEXT: shll $16, %ebp +; AVX512-NEXT: sets %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: shll $16, %r13d +; AVX512-NEXT: vmovd %r13d, %xmm1 +; AVX512-NEXT: vmovd %ebp, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, %xmm2 +; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: vcmpordss %xmm1, %xmm1, %k1 +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: callq __truncsfbf2@PLT +; AVX512-NEXT: vpextrw $0, %xmm0, (%rsp) +; AVX512-NEXT: shll $16, %r12d +; AVX512-NEXT: sets %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: shll $16, %r15d +; AVX512-NEXT: vmovd %r15d, %xmm1 +; AVX512-NEXT: vmovd %r12d, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, %xmm2 +; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: vcmpordss %xmm1, %xmm1, %k1 +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: callq __truncsfbf2@PLT +; AVX512-NEXT: vpextrw $0, %xmm0, {{[0-9]+}}(%rsp) +; AVX512-NEXT: shll $16, %r14d +; AVX512-NEXT: sets %al +; AVX512-NEXT: kmovw %eax, %k1 +; AVX512-NEXT: shll $16, %ebx +; AVX512-NEXT: vmovd %ebx, %xmm1 +; AVX512-NEXT: vmovd %r14d, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, %xmm2 +; AVX512-NEXT: vmovss %xmm1, %xmm2, %xmm2 {%k1} +; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} +; AVX512-NEXT: vmaxss %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: vcmpordss %xmm1, %xmm1, %k1 +; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1} +; AVX512-NEXT: callq __truncsfbf2@PLT +; AVX512-NEXT: vpextrw $0, %xmm0, {{[0-9]+}}(%rsp) +; AVX512-NEXT: vmovaps (%rsp), %xmm0 +; AVX512-NEXT: addq $8, %rsp +; AVX512-NEXT: popq %rbx +; AVX512-NEXT: popq %r12 +; AVX512-NEXT: popq %r13 +; AVX512-NEXT: popq %r14 +; AVX512-NEXT: popq %r15 +; AVX512-NEXT: popq %rbp +; AVX512-NEXT: retq +; +; AVX10_2-LABEL: test_fmaximumnum_v4bf16: +; AVX10_2: # %bb.0: +; AVX10_2-NEXT: vminmaxnepbf16 $17, %xmm1, %xmm0, %xmm0 +; AVX10_2-NEXT: retq +; +; X86-LABEL: test_fmaximumnum_v4bf16: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $68, %esp +; X86-NEXT: vpsrlq $48, %xmm0, %xmm2 +; X86-NEXT: vpsrlq $48, %xmm1, %xmm3 +; X86-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] +; X86-NEXT: vpextrw $0, %xmm4, %esi +; X86-NEXT: vmovshdup {{.*#+}} xmm4 = xmm1[1,1,3,3] +; X86-NEXT: vpextrw $0, %xmm4, %ebx +; X86-NEXT: vpextrw $0, %xmm0, %eax +; X86-NEXT: vpextrw $0, %xmm1, %ecx +; X86-NEXT: vpsrld $16, %xmm0, %xmm0 +; X86-NEXT: vpextrw $0, %xmm0, %edx +; X86-NEXT: vpsrld $16, %xmm1, %xmm0 +; X86-NEXT: vpextrw $0, %xmm0, %edi +; X86-NEXT: shll $16, %edi +; X86-NEXT: vmovd %edi, %xmm0 +; X86-NEXT: shll $16, %edx +; X86-NEXT: vmovd %edx, %xmm4 +; X86-NEXT: js .LBB34_1 +; X86-NEXT: # %bb.2: +; X86-NEXT: vmovdqa %xmm4, %xmm1 +; X86-NEXT: jmp .LBB34_3 +; X86-NEXT: .LBB34_1: +; X86-NEXT: vmovdqa %xmm0, %xmm1 +; X86-NEXT: vmovdqa %xmm4, %xmm0 +; X86-NEXT: .LBB34_3: +; X86-NEXT: vpextrw $0, %xmm2, %edi +; X86-NEXT: vpextrw $0, %xmm3, %ebp +; X86-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: shll $16, %ecx +; X86-NEXT: vmovd %ecx, %xmm0 +; X86-NEXT: shll $16, %eax +; X86-NEXT: vmovd %eax, %xmm2 +; X86-NEXT: js .LBB34_4 +; X86-NEXT: # %bb.5: +; X86-NEXT: vmovdqa %xmm2, %xmm1 +; X86-NEXT: jmp .LBB34_6 +; X86-NEXT: .LBB34_4: +; X86-NEXT: vmovdqa %xmm0, %xmm1 +; X86-NEXT: vmovdqa %xmm2, %xmm0 +; X86-NEXT: .LBB34_6: +; X86-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: calll __truncsfbf2 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: shll $16, %ebx +; X86-NEXT: vmovd %ebx, %xmm0 +; X86-NEXT: shll $16, %esi +; X86-NEXT: vmovd %esi, %xmm2 +; X86-NEXT: js .LBB34_7 +; X86-NEXT: # %bb.8: +; X86-NEXT: vmovdqa %xmm2, %xmm1 +; X86-NEXT: jmp .LBB34_9 +; X86-NEXT: .LBB34_7: +; X86-NEXT: vmovdqa %xmm0, %xmm1 +; X86-NEXT: vmovdqa %xmm2, %xmm0 +; X86-NEXT: .LBB34_9: +; X86-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: calll __truncsfbf2 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vmovss %xmm0, (%esp) +; X86-NEXT: shll $16, %ebp +; X86-NEXT: vmovd %ebp, %xmm0 +; X86-NEXT: shll $16, %edi +; X86-NEXT: vmovd %edi, %xmm2 +; X86-NEXT: js .LBB34_10 +; X86-NEXT: # %bb.11: +; X86-NEXT: vmovdqa %xmm2, %xmm1 +; X86-NEXT: jmp .LBB34_12 +; X86-NEXT: .LBB34_10: +; X86-NEXT: vmovdqa %xmm0, %xmm1 +; X86-NEXT: vmovdqa %xmm2, %xmm0 +; X86-NEXT: .LBB34_12: +; X86-NEXT: vmaxss %xmm1, %xmm0, %xmm1 +; X86-NEXT: vcmpordss %xmm0, %xmm0, %xmm2 +; X86-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: calll __truncsfbf2 +; X86-NEXT: vmovups %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload +; X86-NEXT: vmovd %xmm0, (%esp) +; X86-NEXT: calll __truncsfbf2 +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 # 16-byte Reload +; X86-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; X86-NEXT: vmovdqu {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 # 16-byte Reload +; X86-NEXT: vpunpcklwd {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 16-byte Folded Reload +; X86-NEXT: # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] +; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],zero,zero +; X86-NEXT: addl $68, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: popl %ebp +; X86-NEXT: retl + %r = call <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) + ret <4 x bfloat> %r +} diff --git a/llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll b/llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll index 95432380ced7..55d9ea90682d 100644 --- a/llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll +++ b/llvm/test/CodeGen/X86/fold-vector-shuffle-crash.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 -define void @autogen_SD13708(i32) { +define void @autogen_SD13708(i32, i1 %arg) { BB: %Shuff7 = shufflevector <8 x i32> zeroinitializer, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 10, i32 12, i32 14, i32 undef, i32 2, i32 4, i32 undef> br label %CF @@ -8,11 +8,11 @@ BB: CF: %Tr = trunc <8 x i64> zeroinitializer to <8 x i32> %Shuff20 = shufflevector <8 x i32> %Shuff7, <8 x i32> %Tr, <8 x i32> <i32 13, i32 15, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 11> - br i1 undef, label %CF, label %CF247 + br i1 %arg, label %CF, label %CF247 CF247: %I171 = insertelement <8 x i32> %Shuff20, i32 %0, i32 0 - br i1 undef, label %CF, label %CF247 + br i1 %arg, label %CF, label %CF247 } define void @autogen_SD13800(ptr, ptr, ptr, i32, i64, i8) { diff --git a/llvm/test/CodeGen/X86/hoist-spill.ll b/llvm/test/CodeGen/X86/hoist-spill.ll index d11b6666442b..b51609c313b0 100644 --- a/llvm/test/CodeGen/X86/hoist-spill.ll +++ b/llvm/test/CodeGen/X86/hoist-spill.ll @@ -14,7 +14,7 @@ target triple = "x86_64-unknown-linux-gnu" @d = external global ptr, align 8 ; Function Attrs: norecurse noreturn nounwind uwtable -define void @fn1(i32 %p1, i32 %p2, i64 %p3) { +define void @fn1(i32 %p1, i32 %p2, i64 %p3, i1 %arg) { entry: %tmp = load ptr, ptr @d, align 8 %tmp1 = load ptr, ptr @a, align 8 @@ -54,10 +54,10 @@ for.cond4.preheader: ; preds = %for.body, %for.cond br i1 %cmp528, label %for.inc14, label %for.body6.preheader for.body6.preheader: ; preds = %for.cond4.preheader - br i1 undef, label %for.body6, label %min.iters.checked + br i1 %arg, label %for.body6, label %min.iters.checked min.iters.checked: ; preds = %for.body6.preheader - br i1 undef, label %for.body6, label %vector.memcheck + br i1 %arg, label %for.body6, label %vector.memcheck vector.memcheck: ; preds = %min.iters.checked %bound1 = icmp ule ptr undef, %scevgep41 @@ -85,10 +85,10 @@ vector.body: ; preds = %vector.body, %vecto %tmp16 = getelementptr inbounds i32, ptr %tmp1, i64 %offset.idx.1 store <4 x i32> %wide.load.1, ptr %tmp16, align 4 %index.next.3 = add i64 %index, 32 - br i1 undef, label %middle.block, label %vector.body + br i1 %arg, label %middle.block, label %vector.body middle.block: ; preds = %vector.body, %vector.body.preheader.split - br i1 undef, label %for.inc14, label %for.body6 + br i1 %arg, label %for.inc14, label %for.body6 for.body.preheader: ; preds = %for.cond br label %for.body @@ -98,7 +98,7 @@ for.body: ; preds = %for.body, %for.body %add = add nsw i32 %k.127, 1 %tmp18 = load i32, ptr undef, align 4 store i32 %tmp18, ptr @b, align 4 - br i1 undef, label %for.body, label %for.cond4.preheader + br i1 %arg, label %for.body, label %for.cond4.preheader for.body6: ; preds = %for.body6, %middle.block, %vector.memcheck, %min.iters.checked, %for.body6.preheader %indvars.iv32 = phi i64 [ undef, %for.body6 ], [ %tmp12, %vector.memcheck ], [ %tmp12, %min.iters.checked ], [ %tmp12, %for.body6.preheader ], [ undef, %middle.block ] diff --git a/llvm/test/CodeGen/X86/implicit-null-checks.mir b/llvm/test/CodeGen/X86/implicit-null-checks.mir index 0077906b6018..c98019c09a1e 100644 --- a/llvm/test/CodeGen/X86/implicit-null-checks.mir +++ b/llvm/test/CodeGen/X86/implicit-null-checks.mir @@ -5,15 +5,15 @@ target triple = "x86_64-apple-macosx" ;; Positive test - define i32 @imp_null_check_with_bitwise_op_0(ptr %x, i32 %val) { + define i32 @imp_null_check_with_bitwise_op_0(ptr %x, i32 %val, i1 %arg) { entry: - br i1 undef, label %is_null, label %not_null, !make.implicit !0 + br i1 %arg, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 not_null: - br i1 undef, label %ret_100, label %ret_200 + br i1 %arg, label %ret_100, label %ret_200 ret_100: ret i32 100 @@ -24,15 +24,15 @@ ;; Negative test. The regalloc is such that we cannot hoist the ;; instruction materializing 2200000 into $eax - define i32 @imp_null_check_with_bitwise_op_1(ptr %x, i32 %val, ptr %ptr) { + define i32 @imp_null_check_with_bitwise_op_1(ptr %x, i32 %val, ptr %ptr, i1 %arg) { entry: - br i1 undef, label %is_null, label %not_null, !make.implicit !0 + br i1 %arg, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 undef not_null: - br i1 undef, label %ret_100, label %ret_200 + br i1 %arg, label %ret_100, label %ret_200 ret_100: ret i32 100 @@ -43,15 +43,15 @@ ;; Negative test: IR is identical to ;; @imp_null_check_with_bitwise_op_0 but MIR differs. - define i32 @imp_null_check_with_bitwise_op_2(ptr %x, i32 %val) { + define i32 @imp_null_check_with_bitwise_op_2(ptr %x, i32 %val, i1 %arg) { entry: - br i1 undef, label %is_null, label %not_null, !make.implicit !0 + br i1 %arg, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 not_null: - br i1 undef, label %ret_100, label %ret_200 + br i1 %arg, label %ret_100, label %ret_200 ret_100: ret i32 100 @@ -62,15 +62,15 @@ ;; Negative test: IR is identical to ;; @imp_null_check_with_bitwise_op_0 but MIR differs. - define i32 @imp_null_check_with_bitwise_op_3(ptr %x, i32 %val) { + define i32 @imp_null_check_with_bitwise_op_3(ptr %x, i32 %val, i1 %arg) { entry: - br i1 undef, label %is_null, label %not_null, !make.implicit !0 + br i1 %arg, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 not_null: - br i1 undef, label %ret_100, label %ret_200 + br i1 %arg, label %ret_100, label %ret_200 ret_100: ret i32 100 @@ -80,15 +80,15 @@ } ;; Positive test - define i32 @imp_null_check_with_bitwise_op_4(ptr %x, i32 %val) { + define i32 @imp_null_check_with_bitwise_op_4(ptr %x, i32 %val, i1 %arg) { entry: - br i1 undef, label %is_null, label %not_null, !make.implicit !0 + br i1 %arg, label %is_null, label %not_null, !make.implicit !0 is_null: ret i32 42 not_null: - br i1 undef, label %ret_100, label %ret_200 + br i1 %arg, label %ret_100, label %ret_200 ret_100: ret i32 100 diff --git a/llvm/test/CodeGen/X86/interval-update-remat.ll b/llvm/test/CodeGen/X86/interval-update-remat.ll index 44d3db3a2972..91fde2ba018b 100644 --- a/llvm/test/CodeGen/X86/interval-update-remat.ll +++ b/llvm/test/CodeGen/X86/interval-update-remat.ll @@ -17,13 +17,13 @@ target triple = "i386-unknown-linux-gnu" @f = external global i16, align 2 @.str = external unnamed_addr constant [12 x i8], align 1 -define void @fn1() { +define void @fn1(i1 %arg) { entry: %tmp = load i64, ptr @b, align 8 %or = or i64 0, 3299921317 %and = and i64 %or, %tmp %tmp1 = load i32, ptr @d, align 4 - br i1 undef, label %lor.rhs, label %lor.end + br i1 %arg, label %lor.rhs, label %lor.end lor.rhs: ; preds = %entry %tobool3 = icmp ne i8 undef, 0 @@ -32,7 +32,7 @@ lor.rhs: ; preds = %entry lor.end: ; preds = %lor.rhs, %entry %lor.ext = zext i1 undef to i32 %tmp2 = load i64, ptr @e, align 8 - br i1 undef, label %lor.rhs5, label %lor.end7 + br i1 %arg, label %lor.rhs5, label %lor.end7 lor.rhs5: ; preds = %lor.end br label %lor.end7 diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll index 9eaa65442a72..6dc0427b02f3 100644 --- a/llvm/test/CodeGen/X86/jump_sign.ll +++ b/llvm/test/CodeGen/X86/jump_sign.ll @@ -249,16 +249,16 @@ define void @func_o() nounwind uwtable { ; CHECK-NEXT: .LBB12_7: # %if.else.i97 entry: %0 = load i16, ptr undef, align 2 - br i1 undef, label %if.then.i, label %if.end.i + br i1 poison, label %if.then.i, label %if.end.i if.then.i: ; preds = %entry unreachable if.end.i: ; preds = %entry - br i1 undef, label %sw.bb, label %sw.default + br i1 poison, label %sw.bb, label %sw.default sw.bb: ; preds = %if.end.i - br i1 undef, label %if.then44, label %if.end29 + br i1 poison, label %if.then44, label %if.end29 if.end29: ; preds = %sw.bb %1 = urem i16 %0, 10 @@ -267,7 +267,7 @@ if.end29: ; preds = %sw.bb br i1 %cmp25, label %if.then44, label %sw.default sw.default: ; preds = %if.end29, %if.end.i - br i1 undef, label %if.then.i96, label %if.else.i97 + br i1 poison, label %if.then.i96, label %if.else.i97 if.then.i96: ; preds = %sw.default unreachable @@ -277,7 +277,7 @@ if.else.i97: ; preds = %sw.default if.then44: ; preds = %if.end29, %sw.bb %aModeRefSel.1.ph = phi i16 [ %., %if.end29 ], [ 3, %sw.bb ] - br i1 undef, label %if.then.i103, label %if.else.i104 + br i1 poison, label %if.then.i103, label %if.else.i104 if.then.i103: ; preds = %if.then44 unreachable @@ -420,4 +420,3 @@ if.end: } !1 = !{!"branch_weights", i32 2, i32 1} - diff --git a/llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll b/llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll index a00433391f15..9cd755119e7a 100644 --- a/llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll +++ b/llvm/test/CodeGen/X86/loop-strength-reduce-crash.ll @@ -7,7 +7,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.12.0" -define void @foo() { +define void @foo(i1 %arg) { entry: br label %for @@ -17,7 +17,7 @@ for: store i32 %next, ptr undef, align 4 %add = add i64 %0, 9223372036854775807 %inc = add nsw i32 %next, 1 - br i1 undef, label %exit, label %for + br i1 %arg, label %exit, label %for exit: store i64 %add, ptr undef diff --git a/llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll b/llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll index 552999fdba65..cf434419bb97 100644 --- a/llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll +++ b/llvm/test/CodeGen/X86/lsr-crash-empty-uses.ll @@ -3,7 +3,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" target triple = "x86_64-unknown-linux-gnu" ; CHECK-LABEL: @hoge -define void @hoge() { +define void @hoge(i1 %arg) { bb: %tmp = sext i32 undef to i64 %tmp3 = sub nsw i64 0, %tmp @@ -21,7 +21,7 @@ bb7: ; preds = %bb7, %bb4 br i1 true, label %bb11, label %bb7 bb11: ; preds = %bb7 - br i1 undef, label %bb20, label %bb12 + br i1 %arg, label %bb20, label %bb12 bb12: ; preds = %bb11 br label %bb13 diff --git a/llvm/test/CodeGen/X86/lsr-delayed-fold.ll b/llvm/test/CodeGen/X86/lsr-delayed-fold.ll index efa9331cfcc4..a35015d09a4f 100644 --- a/llvm/test/CodeGen/X86/lsr-delayed-fold.ll +++ b/llvm/test/CodeGen/X86/lsr-delayed-fold.ll @@ -30,7 +30,7 @@ bb24: ; preds = %bb21, %bb11 ; ScalarEvolution should be able to correctly expand the crazy addrec here. ; PR6914 -define void @int323() nounwind { +define void @int323(i1 %arg) nounwind { entry: br label %for.cond @@ -38,7 +38,7 @@ for.cond: ; preds = %lbl_264, %for.inc, %g_263.tmp.1 = phi i8 [ undef, %entry ], [ %g_263.tmp.1, %for.cond ] %p_95.addr.0 = phi i8 [ 0, %entry ], [ %add, %for.cond ] %add = add i8 %p_95.addr.0, 1 ; <i8> [#uses=1] - br i1 undef, label %for.cond, label %lbl_264 + br i1 %arg, label %for.cond, label %lbl_264 lbl_264: ; preds = %if.end, %lbl_264.preheader %g_263.tmp.0 = phi i8 [ %g_263.tmp.1, %for.cond ] ; <i8> [#uses=1] @@ -56,13 +56,13 @@ lbl_264: ; preds = %if.end, %lbl_264.pr %struct.Bu = type { i32, i32, i32 } -define void @_Z3fooP2Bui(ptr nocapture %bu) { +define void @_Z3fooP2Bui(ptr nocapture %bu, i1 %arg) { entry: br label %for.body for.body: ; preds = %for.inc131, %entry %indvar = phi i64 [ %indvar.next, %for.inc131 ], [ 0, %entry ] ; <i64> [#uses=3] - br i1 undef, label %for.inc131, label %lor.lhs.false + br i1 %arg, label %for.inc131, label %lor.lhs.false lor.lhs.false: ; preds = %for.body %tmp15 = add i64 %indvar, 1 ; <i64> [#uses=1] @@ -123,11 +123,11 @@ for.body123: ; preds = %for.body123, %lor.l %add129 = add i32 %mul, %j.03 ; <i32> [#uses=1] tail call void undef(i32 %add129) %inc = add nsw i32 %j.03, 1 ; <i32> [#uses=1] - br i1 undef, label %for.inc131, label %for.body123 + br i1 %arg, label %for.inc131, label %for.body123 for.inc131: ; preds = %for.body123, %for.body %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1] - br i1 undef, label %for.end134, label %for.body + br i1 %arg, label %for.end134, label %for.body for.end134: ; preds = %for.inc131 ret void @@ -138,14 +138,14 @@ for.end134: ; preds = %for.inc131 ; require insert point adjustment. ; PR7306 -define fastcc i32 @GetOptimum() nounwind { +define fastcc i32 @GetOptimum(i1 %arg) nounwind { bb: br label %bb1 bb1: ; preds = %bb1, %bb %t = phi i32 [ 0, %bb ], [ %t2, %bb1 ] ; <i32> [#uses=1] %t2 = add i32 %t, undef ; <i32> [#uses=3] - br i1 undef, label %bb1, label %bb3 + br i1 %arg, label %bb1, label %bb3 bb3: ; preds = %bb1 %t4 = add i32 undef, -1 ; <i32> [#uses=1] @@ -155,13 +155,13 @@ bb5: ; preds = %bb16, %bb3 %t6 = phi i32 [ %t17, %bb16 ], [ 0, %bb3 ] ; <i32> [#uses=3] %t7 = add i32 undef, %t6 ; <i32> [#uses=2] %t8 = add i32 %t4, %t6 ; <i32> [#uses=1] - br i1 undef, label %bb9, label %bb10 + br i1 %arg, label %bb9, label %bb10 bb9: ; preds = %bb5 br label %bb10 bb10: ; preds = %bb9, %bb5 - br i1 undef, label %bb11, label %bb16 + br i1 %arg, label %bb11, label %bb16 bb11: ; preds = %bb10 %t12 = icmp ugt i32 %t7, %t2 ; <i1> [#uses=1] diff --git a/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll b/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll index 5828f06bf1c3..41eae3ca03c2 100644 --- a/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll +++ b/llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll @@ -52,7 +52,7 @@ define void @PR24199(i32 %a0) { entry: %i = alloca %struct.A, align 8 %tobool = icmp ne i32 %a0, 0 - br i1 undef, label %if.end, label %if.then + br i1 poison, label %if.end, label %if.then if.then: br label %if.end @@ -96,5 +96,3 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) !4 = !DIExpression() !5 = !DILocalVariable(name: "this", arg: 1, scope: !3, flags: DIFlagArtificial | DIFlagObjectPointer) !6 = !DILocation(line: 0, scope: !3) - - diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll index ee5fd78c6437..62935f7e372b 100644 --- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll @@ -193,13 +193,13 @@ define i32 @length4(ptr %X, ptr %Y) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl (%ecx), %ecx -; X86-NEXT: movl (%eax), %edx +; X86-NEXT: movl (%eax), %eax ; X86-NEXT: bswapl %ecx -; X86-NEXT: bswapl %edx -; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: bswapl %eax +; X86-NEXT: cmpl %eax, %ecx ; X86-NEXT: seta %al -; X86-NEXT: sbbl $0, %eax +; X86-NEXT: sbbb $0, %al +; X86-NEXT: movsbl %al, %eax ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 4) nounwind ret i32 %m diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll index a46f9ed3d379..9bbd335a903b 100644 --- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll +++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll @@ -179,14 +179,14 @@ define i1 @length3_eq(ptr %X, ptr %Y) nounwind { define i32 @length4(ptr %X, ptr %Y) nounwind { ; X64-LABEL: length4: ; X64: # %bb.0: -; X64-NEXT: movl (%rdi), %ecx -; X64-NEXT: movl (%rsi), %edx +; X64-NEXT: movl (%rdi), %eax +; X64-NEXT: movl (%rsi), %ecx +; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx -; X64-NEXT: bswapl %edx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %edx, %ecx +; X64-NEXT: cmpl %ecx, %eax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind ret i32 %m @@ -391,14 +391,14 @@ define i1 @length7_lt(ptr %X, ptr %Y) nounwind { define i32 @length8(ptr %X, ptr %Y) nounwind { ; X64-LABEL: length8: ; X64: # %bb.0: -; X64-NEXT: movq (%rdi), %rcx -; X64-NEXT: movq (%rsi), %rdx +; X64-NEXT: movq (%rdi), %rax +; X64-NEXT: movq (%rsi), %rcx +; X64-NEXT: bswapq %rax ; X64-NEXT: bswapq %rcx -; X64-NEXT: bswapq %rdx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpq %rdx, %rcx +; X64-NEXT: cmpq %rcx, %rax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 8) nounwind ret i32 %m diff --git a/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll b/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll index 4a9643c0f4fc..3a16ab656b11 100644 --- a/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll @@ -122,13 +122,13 @@ define i32 @length4(ptr %X, ptr %Y) nounwind optsize { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl (%ecx), %ecx -; X86-NEXT: movl (%eax), %edx +; X86-NEXT: movl (%eax), %eax ; X86-NEXT: bswapl %ecx -; X86-NEXT: bswapl %edx -; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: bswapl %eax +; X86-NEXT: cmpl %eax, %ecx ; X86-NEXT: seta %al -; X86-NEXT: sbbl $0, %eax +; X86-NEXT: sbbb $0, %al +; X86-NEXT: movsbl %al, %eax ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 4) nounwind ret i32 %m diff --git a/llvm/test/CodeGen/X86/memcmp-optsize.ll b/llvm/test/CodeGen/X86/memcmp-optsize.ll index 4e27301436c3..0f817b2c727c 100644 --- a/llvm/test/CodeGen/X86/memcmp-optsize.ll +++ b/llvm/test/CodeGen/X86/memcmp-optsize.ll @@ -107,14 +107,14 @@ define i1 @length3_eq(ptr %X, ptr %Y) nounwind optsize { define i32 @length4(ptr %X, ptr %Y) nounwind optsize { ; X64-LABEL: length4: ; X64: # %bb.0: -; X64-NEXT: movl (%rdi), %ecx -; X64-NEXT: movl (%rsi), %edx +; X64-NEXT: movl (%rdi), %eax +; X64-NEXT: movl (%rsi), %ecx +; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx -; X64-NEXT: bswapl %edx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %edx, %ecx +; X64-NEXT: cmpl %ecx, %eax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind ret i32 %m @@ -186,14 +186,14 @@ define i1 @length5_eq(ptr %X, ptr %Y) nounwind optsize { define i32 @length8(ptr %X, ptr %Y) nounwind optsize { ; X64-LABEL: length8: ; X64: # %bb.0: -; X64-NEXT: movq (%rdi), %rcx -; X64-NEXT: movq (%rsi), %rdx +; X64-NEXT: movq (%rdi), %rax +; X64-NEXT: movq (%rsi), %rcx +; X64-NEXT: bswapq %rax ; X64-NEXT: bswapq %rcx -; X64-NEXT: bswapq %rdx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpq %rdx, %rcx +; X64-NEXT: cmpq %rcx, %rax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 8) nounwind ret i32 %m diff --git a/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll b/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll index bdb50f5b60c4..35fd373536bd 100644 --- a/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll @@ -122,13 +122,13 @@ define i32 @length4(ptr %X, ptr %Y) nounwind !prof !14 { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl (%ecx), %ecx -; X86-NEXT: movl (%eax), %edx +; X86-NEXT: movl (%eax), %eax ; X86-NEXT: bswapl %ecx -; X86-NEXT: bswapl %edx -; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: bswapl %eax +; X86-NEXT: cmpl %eax, %ecx ; X86-NEXT: seta %al -; X86-NEXT: sbbl $0, %eax +; X86-NEXT: sbbb $0, %al +; X86-NEXT: movsbl %al, %eax ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 4) nounwind ret i32 %m diff --git a/llvm/test/CodeGen/X86/memcmp-pgso.ll b/llvm/test/CodeGen/X86/memcmp-pgso.ll index 9347e5422022..f63885292318 100644 --- a/llvm/test/CodeGen/X86/memcmp-pgso.ll +++ b/llvm/test/CodeGen/X86/memcmp-pgso.ll @@ -107,14 +107,14 @@ define i1 @length3_eq(ptr %X, ptr %Y) nounwind !prof !14 { define i32 @length4(ptr %X, ptr %Y) nounwind !prof !14 { ; X64-LABEL: length4: ; X64: # %bb.0: -; X64-NEXT: movl (%rdi), %ecx -; X64-NEXT: movl (%rsi), %edx +; X64-NEXT: movl (%rdi), %eax +; X64-NEXT: movl (%rsi), %ecx +; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx -; X64-NEXT: bswapl %edx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %edx, %ecx +; X64-NEXT: cmpl %ecx, %eax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind ret i32 %m @@ -186,14 +186,14 @@ define i1 @length5_eq(ptr %X, ptr %Y) nounwind !prof !14 { define i32 @length8(ptr %X, ptr %Y) nounwind !prof !14 { ; X64-LABEL: length8: ; X64: # %bb.0: -; X64-NEXT: movq (%rdi), %rcx -; X64-NEXT: movq (%rsi), %rdx +; X64-NEXT: movq (%rdi), %rax +; X64-NEXT: movq (%rsi), %rcx +; X64-NEXT: bswapq %rax ; X64-NEXT: bswapq %rcx -; X64-NEXT: bswapq %rdx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpq %rdx, %rcx +; X64-NEXT: cmpq %rcx, %rax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 8) nounwind ret i32 %m diff --git a/llvm/test/CodeGen/X86/memcmp-x32.ll b/llvm/test/CodeGen/X86/memcmp-x32.ll index ad9f2a30d75b..4a3f5a608e58 100644 --- a/llvm/test/CodeGen/X86/memcmp-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-x32.ll @@ -221,13 +221,13 @@ define i32 @length4(ptr %X, ptr %Y) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl (%ecx), %ecx -; X86-NEXT: movl (%eax), %edx +; X86-NEXT: movl (%eax), %eax ; X86-NEXT: bswapl %ecx -; X86-NEXT: bswapl %edx -; X86-NEXT: xorl %eax, %eax -; X86-NEXT: cmpl %edx, %ecx +; X86-NEXT: bswapl %eax +; X86-NEXT: cmpl %eax, %ecx ; X86-NEXT: seta %al -; X86-NEXT: sbbl $0, %eax +; X86-NEXT: sbbb $0, %al +; X86-NEXT: movsbl %al, %eax ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 4) nounwind ret i32 %m diff --git a/llvm/test/CodeGen/X86/memcmp.ll b/llvm/test/CodeGen/X86/memcmp.ll index 8fe1a581cd9c..bb089e5ddda8 100644 --- a/llvm/test/CodeGen/X86/memcmp.ll +++ b/llvm/test/CodeGen/X86/memcmp.ll @@ -205,14 +205,14 @@ define i1 @length3_eq(ptr %X, ptr %Y) nounwind { define i32 @length4(ptr %X, ptr %Y) nounwind { ; X64-LABEL: length4: ; X64: # %bb.0: -; X64-NEXT: movl (%rdi), %ecx -; X64-NEXT: movl (%rsi), %edx +; X64-NEXT: movl (%rdi), %eax +; X64-NEXT: movl (%rsi), %ecx +; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx -; X64-NEXT: bswapl %edx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpl %edx, %ecx +; X64-NEXT: cmpl %ecx, %eax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind ret i32 %m @@ -260,6 +260,36 @@ define i1 @length4_gt(ptr %X, ptr %Y) nounwind { ret i1 %c } +define i1 @length4_le(ptr %X, ptr %Y) nounwind { +; X64-LABEL: length4_le: +; X64: # %bb.0: +; X64-NEXT: movl (%rdi), %eax +; X64-NEXT: movl (%rsi), %ecx +; X64-NEXT: bswapl %eax +; X64-NEXT: bswapl %ecx +; X64-NEXT: cmpl %ecx, %eax +; X64-NEXT: setbe %al +; X64-NEXT: retq + %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind + %c = icmp slt i32 %m, 1 + ret i1 %c +} + +define i1 @length4_ge(ptr %X, ptr %Y) nounwind { +; X64-LABEL: length4_ge: +; X64: # %bb.0: +; X64-NEXT: movl (%rdi), %eax +; X64-NEXT: movl (%rsi), %ecx +; X64-NEXT: bswapl %eax +; X64-NEXT: bswapl %ecx +; X64-NEXT: cmpl %ecx, %eax +; X64-NEXT: setae %al +; X64-NEXT: retq + %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 4) nounwind + %c = icmp sgt i32 %m, -1 + ret i1 %c +} + define i1 @length4_eq_const(ptr %X) nounwind { ; X64-LABEL: length4_eq_const: ; X64: # %bb.0: @@ -279,13 +309,13 @@ define i32 @length5(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %ecx ; X64-NEXT: bswapl %edx ; X64-NEXT: cmpl %edx, %ecx -; X64-NEXT: jne .LBB18_3 +; X64-NEXT: jne .LBB20_3 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB18_3: # %res_block +; X64-NEXT: .LBB20_3: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl %edx, %ecx ; X64-NEXT: sbbl %eax, %eax @@ -319,7 +349,7 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %ecx ; X64-NEXT: bswapl %edx ; X64-NEXT: cmpl %edx, %ecx -; X64-NEXT: jne .LBB20_3 +; X64-NEXT: jne .LBB22_3 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx @@ -327,7 +357,7 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: shrl $31, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq -; X64-NEXT: .LBB20_3: # %res_block +; X64-NEXT: .LBB22_3: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl %edx, %ecx ; X64-NEXT: sbbl %eax, %eax @@ -348,7 +378,7 @@ define i32 @length7(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %ecx ; X64-NEXT: bswapl %edx ; X64-NEXT: cmpl %edx, %ecx -; X64-NEXT: jne .LBB21_2 +; X64-NEXT: jne .LBB23_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movl 3(%rdi), %ecx ; X64-NEXT: movl 3(%rsi), %edx @@ -356,13 +386,13 @@ define i32 @length7(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %edx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl %edx, %ecx -; X64-NEXT: je .LBB21_3 -; X64-NEXT: .LBB21_2: # %res_block +; X64-NEXT: je .LBB23_3 +; X64-NEXT: .LBB23_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl %edx, %ecx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB21_3: # %endblock +; X64-NEXT: .LBB23_3: # %endblock ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 7) nounwind ret i32 %m @@ -376,7 +406,7 @@ define i1 @length7_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %ecx ; X64-NEXT: bswapl %edx ; X64-NEXT: cmpl %edx, %ecx -; X64-NEXT: jne .LBB22_2 +; X64-NEXT: jne .LBB24_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movl 3(%rdi), %ecx ; X64-NEXT: movl 3(%rsi), %edx @@ -384,13 +414,13 @@ define i1 @length7_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %edx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl %edx, %ecx -; X64-NEXT: je .LBB22_3 -; X64-NEXT: .LBB22_2: # %res_block +; X64-NEXT: je .LBB24_3 +; X64-NEXT: .LBB24_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl %edx, %ecx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB22_3: # %endblock +; X64-NEXT: .LBB24_3: # %endblock ; X64-NEXT: shrl $31, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -417,14 +447,14 @@ define i1 @length7_eq(ptr %X, ptr %Y) nounwind { define i32 @length8(ptr %X, ptr %Y) nounwind { ; X64-LABEL: length8: ; X64: # %bb.0: -; X64-NEXT: movq (%rdi), %rcx -; X64-NEXT: movq (%rsi), %rdx +; X64-NEXT: movq (%rdi), %rax +; X64-NEXT: movq (%rsi), %rcx +; X64-NEXT: bswapq %rax ; X64-NEXT: bswapq %rcx -; X64-NEXT: bswapq %rdx -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: cmpq %rdx, %rcx +; X64-NEXT: cmpq %rcx, %rax ; X64-NEXT: seta %al -; X64-NEXT: sbbl $0, %eax +; X64-NEXT: sbbb $0, %al +; X64-NEXT: movsbl %al, %eax ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 8) nounwind ret i32 %m @@ -524,7 +554,7 @@ define i32 @length12(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapq %rcx ; X64-NEXT: bswapq %rdx ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: jne .LBB31_2 +; X64-NEXT: jne .LBB33_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movl 8(%rdi), %ecx ; X64-NEXT: movl 8(%rsi), %edx @@ -532,13 +562,13 @@ define i32 @length12(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %edx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: je .LBB31_3 -; X64-NEXT: .LBB31_2: # %res_block +; X64-NEXT: je .LBB33_3 +; X64-NEXT: .LBB33_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB31_3: # %endblock +; X64-NEXT: .LBB33_3: # %endblock ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 12) nounwind ret i32 %m @@ -582,7 +612,7 @@ define i32 @length15(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapq %rcx ; X64-NEXT: bswapq %rdx ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: jne .LBB34_2 +; X64-NEXT: jne .LBB36_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movq 7(%rdi), %rcx ; X64-NEXT: movq 7(%rsi), %rdx @@ -590,13 +620,13 @@ define i32 @length15(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapq %rdx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: je .LBB34_3 -; X64-NEXT: .LBB34_2: # %res_block +; X64-NEXT: je .LBB36_3 +; X64-NEXT: .LBB36_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB34_3: # %endblock +; X64-NEXT: .LBB36_3: # %endblock ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 15) nounwind ret i32 %m @@ -610,7 +640,7 @@ define i1 @length15_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapq %rcx ; X64-NEXT: bswapq %rdx ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: jne .LBB35_2 +; X64-NEXT: jne .LBB37_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movq 7(%rdi), %rcx ; X64-NEXT: movq 7(%rsi), %rdx @@ -618,13 +648,13 @@ define i1 @length15_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapq %rdx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: je .LBB35_3 -; X64-NEXT: .LBB35_2: # %res_block +; X64-NEXT: je .LBB37_3 +; X64-NEXT: .LBB37_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB35_3: # %endblock +; X64-NEXT: .LBB37_3: # %endblock ; X64-NEXT: shrl $31, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -640,20 +670,20 @@ define i32 @length15_const(ptr %X, ptr %Y) nounwind { ; X64-NEXT: movq (%rdi), %rdx ; X64-NEXT: bswapq %rdx ; X64-NEXT: cmpq %rcx, %rdx -; X64-NEXT: jne .LBB36_2 +; X64-NEXT: jne .LBB38_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movabsq $4051322327650219061, %rcx # imm = 0x3839303132333435 ; X64-NEXT: movq 7(%rdi), %rdx ; X64-NEXT: bswapq %rdx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rcx, %rdx -; X64-NEXT: je .LBB36_3 -; X64-NEXT: .LBB36_2: # %res_block +; X64-NEXT: je .LBB38_3 +; X64-NEXT: .LBB38_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rcx, %rdx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB36_3: # %endblock +; X64-NEXT: .LBB38_3: # %endblock ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr getelementptr inbounds ([513 x i8], ptr @.str, i32 0, i32 1), i64 15) nounwind ret i32 %m @@ -681,20 +711,20 @@ define i1 @length15_gt_const(ptr %X, ptr %Y) nounwind { ; X64-NEXT: movq (%rdi), %rcx ; X64-NEXT: bswapq %rcx ; X64-NEXT: cmpq %rax, %rcx -; X64-NEXT: jne .LBB38_2 +; X64-NEXT: jne .LBB40_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movabsq $4051322327650219061, %rax # imm = 0x3839303132333435 ; X64-NEXT: movq 7(%rdi), %rcx ; X64-NEXT: bswapq %rcx ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: cmpq %rax, %rcx -; X64-NEXT: je .LBB38_3 -; X64-NEXT: .LBB38_2: # %res_block +; X64-NEXT: je .LBB40_3 +; X64-NEXT: .LBB40_2: # %res_block ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: cmpq %rax, %rcx ; X64-NEXT: sbbl %edx, %edx ; X64-NEXT: orl $1, %edx -; X64-NEXT: .LBB38_3: # %endblock +; X64-NEXT: .LBB40_3: # %endblock ; X64-NEXT: testl %edx, %edx ; X64-NEXT: setg %al ; X64-NEXT: retq @@ -713,7 +743,7 @@ define i32 @length16(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapq %rcx ; X64-NEXT: bswapq %rdx ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: jne .LBB39_2 +; X64-NEXT: jne .LBB41_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movq 8(%rdi), %rcx ; X64-NEXT: movq 8(%rsi), %rdx @@ -721,13 +751,13 @@ define i32 @length16(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapq %rdx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: je .LBB39_3 -; X64-NEXT: .LBB39_2: # %res_block +; X64-NEXT: je .LBB41_3 +; X64-NEXT: .LBB41_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB39_3: # %endblock +; X64-NEXT: .LBB41_3: # %endblock ; X64-NEXT: retq %m = tail call i32 @memcmp(ptr %X, ptr %Y, i64 16) nounwind ret i32 %m @@ -783,7 +813,7 @@ define i1 @length16_lt(ptr %x, ptr %y) nounwind { ; X64-NEXT: bswapq %rcx ; X64-NEXT: bswapq %rdx ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: jne .LBB41_2 +; X64-NEXT: jne .LBB43_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movq 8(%rdi), %rcx ; X64-NEXT: movq 8(%rsi), %rdx @@ -791,13 +821,13 @@ define i1 @length16_lt(ptr %x, ptr %y) nounwind { ; X64-NEXT: bswapq %rdx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx -; X64-NEXT: je .LBB41_3 -; X64-NEXT: .LBB41_2: # %res_block +; X64-NEXT: je .LBB43_3 +; X64-NEXT: .LBB43_2: # %res_block ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpq %rdx, %rcx ; X64-NEXT: sbbl %eax, %eax ; X64-NEXT: orl $1, %eax -; X64-NEXT: .LBB41_3: # %endblock +; X64-NEXT: .LBB43_3: # %endblock ; X64-NEXT: shrl $31, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -814,7 +844,7 @@ define i1 @length16_gt(ptr %x, ptr %y) nounwind { ; X64-NEXT: bswapq %rax ; X64-NEXT: bswapq %rcx ; X64-NEXT: cmpq %rcx, %rax -; X64-NEXT: jne .LBB42_2 +; X64-NEXT: jne .LBB44_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movq 8(%rdi), %rax ; X64-NEXT: movq 8(%rsi), %rcx @@ -822,13 +852,13 @@ define i1 @length16_gt(ptr %x, ptr %y) nounwind { ; X64-NEXT: bswapq %rcx ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: cmpq %rcx, %rax -; X64-NEXT: je .LBB42_3 -; X64-NEXT: .LBB42_2: # %res_block +; X64-NEXT: je .LBB44_3 +; X64-NEXT: .LBB44_2: # %res_block ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: cmpq %rcx, %rax ; X64-NEXT: sbbl %edx, %edx ; X64-NEXT: orl $1, %edx -; X64-NEXT: .LBB42_3: # %endblock +; X64-NEXT: .LBB44_3: # %endblock ; X64-NEXT: testl %edx, %edx ; X64-NEXT: setg %al ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll b/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll index a10fbc10bf28..3dba5eb15d67 100644 --- a/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll +++ b/llvm/test/CodeGen/X86/merge-vector-stores-scale-idx-crash.ll @@ -21,10 +21,10 @@ define void @testfn(ptr nocapture %p) { ; CHECK-LABEL: testfn_scalar ; CHECK: retq -define void @testfn_scalar(ptr nocapture %j) local_unnamed_addr #0 align 2 { +define void @testfn_scalar(ptr nocapture %j, i1 %arg) local_unnamed_addr #0 align 2 { entry: %0 = bitcast i64 undef to <2 x float> - br i1 undef, label %if.end, label %if.then + br i1 %arg, label %if.end, label %if.then if.then: ; preds = %entry unreachable diff --git a/llvm/test/CodeGen/X86/mingw-refptr.ll b/llvm/test/CodeGen/X86/mingw-refptr.ll index 73f1a9880913..82a90aba3865 100644 --- a/llvm/test/CodeGen/X86/mingw-refptr.ll +++ b/llvm/test/CodeGen/X86/mingw-refptr.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-w64-mingw32 | FileCheck %s -check-prefix=CHECK-X64 +; RUN: llc < %s -mtriple=x86_64-pc-cygwin | FileCheck %s -check-prefix=CHECK-X64 ; RUN: llc < %s -mtriple=i686-w64-mingw32 | FileCheck %s -check-prefix=CHECK-X86 ; RUN: llc < %s -mtriple=i686-w64-mingw32-none-elf | FileCheck %s -check-prefix=CHECK-X86-ELF diff --git a/llvm/test/CodeGen/X86/misched-crash.ll b/llvm/test/CodeGen/X86/misched-crash.ll index 98818d9a102f..a421faba95f7 100644 --- a/llvm/test/CodeGen/X86/misched-crash.ll +++ b/llvm/test/CodeGen/X86/misched-crash.ll @@ -4,7 +4,7 @@ target triple = "x86_64-apple-macosx10" ; This function contains a cmp instruction with two users. ; Hoisting the last use requires trimming the EFLAGS live range to the second. -define void @rdar13353090(ptr %plane, i64 %_x1, i64 %_x2) { +define void @rdar13353090(ptr %plane, i64 %_x1, i64 %_x2, i1 %arg) { entry: %cmp = icmp ult i64 %_x1, %_x2 %cond = select i1 %cmp, i64 %_x1, i64 %_x2 @@ -33,7 +33,7 @@ for.body34.i: ; preds = %for.inc39.i, %if.th for.inc39.i: ; preds = %for.body34.i %inc41.i = add i64 %index.178.i, 1 - br i1 undef, label %return, label %for.body34.i + br i1 %arg, label %return, label %for.body34.i return: ; preds = %for.inc39.i, %for.body34.i, %land.lhs.true21, %entry ret void diff --git a/llvm/test/CodeGen/X86/pr10475.ll b/llvm/test/CodeGen/X86/pr10475.ll index 4dd5aab499ca..4275dc262c37 100644 --- a/llvm/test/CodeGen/X86/pr10475.ll +++ b/llvm/test/CodeGen/X86/pr10475.ll @@ -2,19 +2,19 @@ ; No check in a crash test -define void @autogen_262380_1000() { +define void @autogen_262380_1000(i1 %arg) { BB: br label %CF79 CF79: ; preds = %CF79, %BB - br i1 undef, label %CF79, label %CF84.critedge.critedge + br i1 %arg, label %CF79, label %CF84.critedge.critedge CF84.critedge.critedge: ; preds = %CF79 %L35 = load <8 x i32>, ptr undef br label %CF85 CF85: ; preds = %CF85, %CF84.critedge.critedge - br i1 undef, label %CF85, label %CF86 + br i1 %arg, label %CF85, label %CF86 CF86: ; preds = %CF86, %CF85 %B61 = sub <8 x i32> %L35, zeroinitializer @@ -23,7 +23,7 @@ CF86: ; preds = %CF86, %CF85 br i1 %E73, label %CF86, label %CF87 CF87: ; preds = %CF87, %CF86 - br i1 undef, label %CF87, label %CF88 + br i1 %arg, label %CF87, label %CF88 CF88: ; preds = %CF87 ret void diff --git a/llvm/test/CodeGen/X86/pr107423.ll b/llvm/test/CodeGen/X86/pr107423.ll new file mode 100644 index 000000000000..d5119d45f97c --- /dev/null +++ b/llvm/test/CodeGen/X86/pr107423.ll @@ -0,0 +1,74 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s + +define void @PR107423(<64 x i8> %arg, ptr %p0) { +; CHECK-LABEL: PR107423: +; CHECK: # %bb.0: +; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2 +; CHECK-NEXT: vpsllw $8, %xmm2, %xmm2 +; CHECK-NEXT: vpsllw $8, %xmm1, %xmm3 +; CHECK-NEXT: vpaddb %xmm2, %xmm3, %xmm3 +; CHECK-NEXT: vpaddb %xmm0, %xmm2, %xmm2 +; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm4 +; CHECK-NEXT: vpaddb %xmm1, %xmm4, %xmm1 +; CHECK-NEXT: vpaddb %xmm4, %xmm0, %xmm4 +; CHECK-NEXT: vpsllw $8, %xmm4, %xmm4 +; CHECK-NEXT: vpaddb %xmm3, %xmm4, %xmm3 +; CHECK-NEXT: vpsllw $8, %xmm1, %xmm1 +; CHECK-NEXT: vpaddb %xmm2, %xmm1, %xmm1 +; CHECK-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; CHECK-NEXT: vpor %xmm3, %xmm2, %xmm2 +; CHECK-NEXT: vpsllw $8, %xmm0, %xmm0 +; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vmovdqu %xmm0, 16(%rdi) +; CHECK-NEXT: vmovdqu %xmm2, (%rdi) +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq + %i3 = bitcast <64 x i8> %arg to <32 x i16> + %i4 = shufflevector <32 x i16> %i3, <32 x i16> poison, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %i5 = shl <8 x i16> %i4, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %i6 = bitcast <8 x i16> %i5 to <16 x i8> + %i7 = shufflevector <64 x i8> %arg, <64 x i8> poison, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47> + %i8 = shufflevector <64 x i8> %arg, <64 x i8> poison, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i9 = shufflevector <64 x i8> %i7, <64 x i8> %i8, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> + %i10 = shufflevector <16 x i8> %i6, <16 x i8> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i11 = shufflevector <64 x i8> %i10, <64 x i8> %i9, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> + %i12 = bitcast <64 x i8> %i11 to <32 x i16> + %i13 = shl <32 x i16> %i12, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %i14 = bitcast <32 x i16> %i13 to <64 x i8> + %i15 = shufflevector <64 x i8> %i14, <64 x i8> poison, <16 x i32> <i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> + %i16 = shufflevector <64 x i8> %i11, <64 x i8> poison, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47> + %i17 = shufflevector <16 x i8> %i6, <16 x i8> poison, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i18 = shufflevector <64 x i8> %i16, <64 x i8> %i17, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> + %i19 = shufflevector <16 x i8> %i15, <16 x i8> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i20 = shufflevector <64 x i8> %i19, <64 x i8> %i18, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> + %i21 = add <64 x i8> %i20, %i11 + %i22 = bitcast <64 x i8> %i21 to <32 x i16> + %i23 = shl <32 x i16> %i22, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %i24 = bitcast <32 x i16> %i23 to <64 x i8> + %i25 = shufflevector <64 x i8> %i24, <64 x i8> poison, <16 x i32> <i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> + %i26 = bitcast <32 x i16> %i23 to <64 x i8> + %i28 = shufflevector <64 x i8> %i26, <64 x i8> poison, <16 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47> + %i32 = shufflevector <64 x i8> %i21, <64 x i8> poison, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %i33 = shufflevector <16 x i8> %i25, <16 x i8> poison, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i34 = shufflevector <64 x i8> %i32, <64 x i8> %i33, <64 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63> + %i35 = shufflevector <16 x i8> %i28, <16 x i8> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i36 = shufflevector <64 x i8> %i35, <64 x i8> %i34, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> + %i37 = add <64 x i8> %i36, %i21 + %i38 = bitcast <64 x i8> %i37 to <32 x i16> + %i39 = shufflevector <32 x i16> %i38, <32 x i16> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %i40 = shl <8 x i16> %i39, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %i41 = bitcast <8 x i16> %i40 to <16 x i8> + %i42 = shufflevector <16 x i8> %i41, <16 x i8> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i43 = shufflevector <64 x i8> %i42, <64 x i8> %i37, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 80, i32 81, i32 82, i32 83, i32 84, i32 85, i32 86, i32 87, i32 88, i32 89, i32 90, i32 91, i32 92, i32 93, i32 94, i32 95, i32 96, i32 97, i32 98, i32 99, i32 100, i32 101, i32 102, i32 103, i32 104, i32 105, i32 106, i32 107, i32 108, i32 109, i32 110, i32 111, i32 112, i32 113, i32 114, i32 115, i32 116, i32 117, i32 118, i32 119, i32 120, i32 121, i32 122, i32 123, i32 124, i32 125, i32 126, i32 127> + %i44 = bitcast <64 x i8> %i43 to <32 x i16> + %i45 = shufflevector <32 x i16> %i44, <32 x i16> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %i46 = shl <8 x i16> %i45, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %i47 = bitcast <8 x i16> %i46 to <16 x i8> + %i48 = shufflevector <16 x i8> %i47, <16 x i8> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> + %i49 = shufflevector <64 x i8> %i43, <64 x i8> %i48, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 64, i32 65, i32 66, i32 67, i32 68, i32 69, i32 70, i32 71, i32 72, i32 73, i32 74, i32 75, i32 76, i32 77, i32 78, i32 79> + %i50 = shufflevector <64 x i8> %i37, <64 x i8> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %i51 = add <32 x i8> %i49, %i50 + store <32 x i8> %i51, ptr %p0, align 1 + ret void +} diff --git a/llvm/test/CodeGen/X86/pr11998.ll b/llvm/test/CodeGen/X86/pr11998.ll index caaf2710fba8..4b93c20e7c23 100644 --- a/llvm/test/CodeGen/X86/pr11998.ll +++ b/llvm/test/CodeGen/X86/pr11998.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -mcpu=corei7-avx -mtriple=x86_64-- -mattr=+avx -define void @autogen_51367_5000(i8) { +define void @autogen_51367_5000(i8, i1 %arg) { BB: %B = srem i8 55, %0 %B9 = shl i8 %B, %B br label %CF CF: ; preds = %CF, %BB - br i1 undef, label %CF, label %CF403 + br i1 %arg, label %CF, label %CF403 CF403: ; preds = %CF403, %CF %S44 = icmp eq i8 %B9, %0 diff --git a/llvm/test/CodeGen/X86/pr32108.ll b/llvm/test/CodeGen/X86/pr32108.ll index 32f8a7657a3f..a50b9a676ae2 100644 --- a/llvm/test/CodeGen/X86/pr32108.ll +++ b/llvm/test/CodeGen/X86/pr32108.ll @@ -13,7 +13,7 @@ BB: br label %CF243 CF243: ; preds = %CF243, %BB - br i1 undef, label %CF243, label %CF257 + br i1 poison, label %CF243, label %CF257 CF257: ; preds = %CF243 %Shuff144 = shufflevector <4 x i1> undef, <4 x i1> %Cmp45, <4 x i32> <i32 undef, i32 undef, i32 5, i32 undef> diff --git a/llvm/test/CodeGen/X86/pr50254.ll b/llvm/test/CodeGen/X86/pr50254.ll index 01d261a3fd4b..95b7ae5e3e02 100644 --- a/llvm/test/CodeGen/X86/pr50254.ll +++ b/llvm/test/CodeGen/X86/pr50254.ll @@ -37,7 +37,7 @@ entry: br label %for.body for.body: ; preds = %entry - br i1 undef, label %for.end, label %for.body.1 + br i1 poison, label %for.end, label %for.body.1 for.end: ; preds = %for.body store i16 %xor1, ptr @d.e, align 4 diff --git a/llvm/test/CodeGen/X86/pr57673.ll b/llvm/test/CodeGen/X86/pr57673.ll index 4ca8ae91f9e6..779978b90349 100644 --- a/llvm/test/CodeGen/X86/pr57673.ll +++ b/llvm/test/CodeGen/X86/pr57673.ll @@ -100,7 +100,7 @@ bb_entry: br label %bb_8 bb_8: ; preds = %bb_last, %bb_entry - br i1 undef, label %bb_last, label %bb_mid + br i1 poison, label %bb_last, label %bb_mid bb_mid: ; preds = %bb_8 %i4 = getelementptr inbounds %t10, ptr %i1, i64 0, i32 1, i64 32 diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll index beb42f55b709..47e5079e9c36 100644 --- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll +++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll @@ -331,13 +331,13 @@ if.end: ] if.then4: - br i1 undef, label %SyTime.exit, label %if.then.i + br i1 poison, label %SyTime.exit, label %if.then.i if.then.i: unreachable SyTime.exit: - br i1 undef, label %SyTime.exit2681, label %if.then.i2673 + br i1 poison, label %SyTime.exit2681, label %if.then.i2673 if.then.i2673: unreachable @@ -349,7 +349,7 @@ land.lhs.true14: unreachable if.end25: - br i1 undef, label %SyTime.exit2720, label %if.then.i2712 + br i1 poison, label %SyTime.exit2720, label %if.then.i2712 if.then.i2712: unreachable @@ -406,7 +406,7 @@ do.end: %mul167 = shl i32 %rep.6, 2 %rep.8 = select i1 %cmp164, i32 %mul167, i32 %rep.6 %..ch.19 = select i1 false, i32 2, i32 0 - br i1 undef, label %while.body200, label %while.end1465 + br i1 poison, label %while.body200, label %while.end1465 while.body200: %dec3386.in = phi i32 [ %dec3386, %while.cond197.backedge ], [ %rep.8, %do.end ] @@ -444,7 +444,7 @@ while.cond1037.preheader: br i1 %cmp10393273, label %if.end1070, label %land.rhs1041 while.cond635.preheader: - br i1 undef, label %for.body643.us, label %while.cond661 + br i1 poison, label %for.body643.us, label %while.cond661 for.body643.us: br label %for.body643.us @@ -488,7 +488,7 @@ land.rhs485: br i1 %isascii.i.i27763151, label %cond.true.i.i2780, label %cond.false.i.i2782 cond.true.i.i2780: - br i1 undef, label %land.lhs.true490, label %lor.rhs500 + br i1 poison, label %land.lhs.true490, label %lor.rhs500 cond.false.i.i2782: unreachable @@ -499,10 +499,10 @@ land.lhs.true490: lor.rhs500: ; Make sure spill is hoisted to a cold preheader in outside loop. %call3.i.i2792 = call i32 @__maskrune(i32 undef, i64 256) - br i1 undef, label %land.lhs.true504, label %do.body479.backedge + br i1 poison, label %land.lhs.true504, label %do.body479.backedge land.lhs.true504: - br i1 undef, label %do.body479.backedge, label %if.end517 + br i1 poison, label %do.body479.backedge, label %if.end517 do.body479.backedge: %incdec.ptr480 = getelementptr i8, ptr %incdec.ptr4803316, i64 1 @@ -531,10 +531,10 @@ for.cond534: br i1 %cmp536, label %for.cond542.preheader, label %for.cond534 for.cond542.preheader: - br i1 undef, label %for.body545, label %for.end552 + br i1 poison, label %for.body545, label %for.end552 for.body545: - br i1 undef, label %for.end552, label %for.body545 + br i1 poison, label %for.end552, label %for.body545 for.end552: %s.2.lcssa = phi ptr [ undef, %for.cond542.preheader ], [ %q.4, %for.body545 ] @@ -554,7 +554,7 @@ while.cond864: br label %while.cond864 sw.bb956: - br i1 undef, label %if.then959, label %while.cond197.backedge + br i1 poison, label %if.then959, label %while.cond197.backedge if.then959: br label %while.cond962 @@ -600,7 +600,7 @@ while.end1465: ] for.cond1480.preheader: - br i1 undef, label %for.body1606.lr.ph, label %for.end1609 + br i1 poison, label %for.body1606.lr.ph, label %for.end1609 if.then1477: %p.1.lcssa3539 = phi ptr [ null, %while.end1465 ], [ null, %while.end1465 ], [ null, %while.end1465 ], [ null, %while.end1465 ], [ %line, %while.body200 ] @@ -614,7 +614,7 @@ for.body1606.lr.ph: br label %for.end1609 for.end1609: - br i1 undef, label %for.cond1659.preheader, label %land.lhs.true1614 + br i1 poison, label %for.cond1659.preheader, label %land.lhs.true1614 land.lhs.true1614: br label %for.cond1659.preheader @@ -631,13 +631,13 @@ while.body1703.lr.ph: unreachable while.cond1683.preheader: - br i1 undef, label %while.body1691, label %while.end1693 + br i1 poison, label %while.body1691, label %while.end1693 while.body1679: %oldc.43406 = phi i32 [ %inc, %syEchoch.exit3070 ], [ %oldc.1.lcssa, %for.body1664.lr.ph ] %3 = load ptr, ptr %echo.i3101, align 8, !tbaa !6 %call.i3062 = call i32 @fileno(ptr %3) - br i1 undef, label %if.then.i3069, label %syEchoch.exit3070 + br i1 poison, label %if.then.i3069, label %syEchoch.exit3070 if.then.i3069: br label %syEchoch.exit3070 diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll index c9edd3f3e904..cd3d48110772 100644 --- a/llvm/test/CodeGen/X86/shift-combine.ll +++ b/llvm/test/CodeGen/X86/shift-combine.ll @@ -408,7 +408,7 @@ define dso_local void @PR42880(i32 %t0) { %x = ptrtoint ptr %add.ptr.i94 to i32 %sub2 = sub i32 %x, 0 %div = sdiv exact i32 %sub2, 24 - br i1 undef, label %if, label %then + br i1 poison, label %if, label %then then: %t1 = xor i32 %div, -1 diff --git a/llvm/test/CodeGen/X86/shuffle-combine-crash.ll b/llvm/test/CodeGen/X86/shuffle-combine-crash.ll index e10e3dd1cd92..962b833ad9a1 100644 --- a/llvm/test/CodeGen/X86/shuffle-combine-crash.ll +++ b/llvm/test/CodeGen/X86/shuffle-combine-crash.ll @@ -28,7 +28,7 @@ define void @sample_test() { ; CHECK-NEXT: movd %xmm0, (%rax) ; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: retq - br i1 undef, label %5, label %1 + br i1 poison, label %5, label %1 ; <label>:1 ; preds = %0 %2 = load <4 x i8>, ptr undef @@ -40,4 +40,3 @@ define void @sample_test() { ; <label>:5 ; preds = %1, %0 ret void } - diff --git a/llvm/test/CodeGen/X86/stackmap.ll b/llvm/test/CodeGen/X86/stackmap.ll index 33180a7db893..72406aaa4efa 100644 --- a/llvm/test/CodeGen/X86/stackmap.ll +++ b/llvm/test/CodeGen/X86/stackmap.ll @@ -379,23 +379,23 @@ entry: ; CHECK-NEXT: .short 6 ; CHECK-NEXT: .short 0 ; CHECK-NEXT: .long -define void @spillSubReg(i64 %arg) #0 { +define void @spillSubReg(i64 %arg, i1 %arg2) #0 { bb: - br i1 undef, label %bb1, label %bb2 + br i1 %arg2, label %bb1, label %bb2 bb1: unreachable bb2: %tmp = load i64, ptr inttoptr (i64 140685446136880 to ptr) - br i1 undef, label %bb16, label %bb17 + br i1 %arg2, label %bb16, label %bb17 bb16: unreachable bb17: %tmp32 = trunc i64 %tmp to i32 - br i1 undef, label %bb60, label %bb61 + br i1 %arg2, label %bb60, label %bb61 bb60: tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind diff --git a/llvm/test/CodeGen/X86/swifterror.ll b/llvm/test/CodeGen/X86/swifterror.ll index 1489b0295e93..77b1ac094cea 100644 --- a/llvm/test/CodeGen/X86/swifterror.ll +++ b/llvm/test/CodeGen/X86/swifterror.ll @@ -1014,7 +1014,7 @@ define void @swifterror_isel(ptr) { ; CHECK-i386-NEXT: retl entry: %swifterror = alloca swifterror ptr, align 8 - br i1 undef, label %5, label %1 + br i1 poison, label %5, label %1 %2 = phi i16 [ %4, %1 ], [ undef, %entry ] %3 = call i1 undef(i16 %2, ptr swiftself %0, ptr nocapture swifterror %swifterror) diff --git a/llvm/test/CodeGen/X86/switch.ll b/llvm/test/CodeGen/X86/switch.ll index 629ba48fcae6..c75819c2fd2c 100644 --- a/llvm/test/CodeGen/X86/switch.ll +++ b/llvm/test/CodeGen/X86/switch.ll @@ -2563,7 +2563,7 @@ define i32 @pr27135(i32 %i) { ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: retq entry: - br i1 undef, label %sw, label %end + br i1 poison, label %sw, label %end sw: switch i32 %i, label %end [ i32 99, label %sw.bb diff --git a/llvm/test/CodeGen/X86/tail-merge-unreachable.ll b/llvm/test/CodeGen/X86/tail-merge-unreachable.ll index ce5613f52309..9afdabd4ce13 100644 --- a/llvm/test/CodeGen/X86/tail-merge-unreachable.ll +++ b/llvm/test/CodeGen/X86/tail-merge-unreachable.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -verify-machineinstrs | FileCheck %s -define i32 @tail_merge_unreachable(i32 %i) { +define i32 @tail_merge_unreachable(i32 %i, i1 %arg) { entry: - br i1 undef, label %sw, label %end + br i1 %arg, label %sw, label %end sw: switch i32 %i, label %end [ i32 99, label %sw.bb diff --git a/llvm/test/CodeGen/X86/uint_to_half.ll b/llvm/test/CodeGen/X86/uint_to_half.ll new file mode 100644 index 000000000000..b62a07eec1ce --- /dev/null +++ b/llvm/test/CodeGen/X86/uint_to_half.ll @@ -0,0 +1,198 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx,+f16c | FileCheck %s -check-prefixes=AVX1 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+f16c | FileCheck %s -check-prefixes=AVX2 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl | FileCheck %s -check-prefixes=AVX512 + +define <8 x half> @test_uitofp_v8i32_v8f16(<8 x i32> %a) { +; AVX1-LABEL: test_uitofp_v8i32_v8f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 +; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_uitofp_v8i32_v8f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_uitofp_v8i32_v8f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %ymm0, %ymm0 +; AVX512-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %vec = uitofp <8 x i32> %a to <8 x half> + ret <8 x half> %vec +} + +define <8 x half> @test_strict_uitofp_v8i32_v8f16(<8 x i32> %a) { +; AVX1-LABEL: test_strict_uitofp_v8i32_v8f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 +; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_strict_uitofp_v8i32_v8f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_strict_uitofp_v8i32_v8f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %ymm0, %ymm0 +; AVX512-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %vec = tail call <8 x half> @llvm.experimental.constrained.uitofp.f16.i32(<8 x i32> %a, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret <8 x half> %vec +} + +define <16 x half> @test_uitofp_v16i32_v16f16(<16 x i32> %a) { +; AVX1-LABEL: test_uitofp_v16i32_v16f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpsrld $16, %xmm3, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4] +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm4 = [65535,65535,65535,65535,65535,65535,65535,65535] +; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm2, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vpsrld $16, %xmm1, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vpsrld $16, %xmm5, %xmm5 +; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vandps %ymm4, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX1-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_uitofp_v16i32_v16f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm3 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm4 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7],ymm0[8],ymm4[9],ymm0[10],ymm4[11],ymm0[12],ymm4[13],ymm0[14],ymm4[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm5 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm5, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0],ymm2[1],ymm1[2],ymm2[3],ymm1[4],ymm2[5],ymm1[6],ymm2[7],ymm1[8],ymm2[9],ymm1[10],ymm2[11],ymm1[12],ymm2[13],ymm1[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm4[1],ymm1[2],ymm4[3],ymm1[4],ymm4[5],ymm1[6],ymm4[7],ymm1[8],ymm4[9],ymm1[10],ymm4[11],ymm1[12],ymm4[13],ymm1[14],ymm4[15] +; AVX2-NEXT: vsubps %ymm5, %ymm1, %ymm1 +; AVX2-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_uitofp_v16i32_v16f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %zmm0, %zmm0 +; AVX512-NEXT: vcvtps2ph $4, %zmm0, %ymm0 +; AVX512-NEXT: retq + %vec = uitofp <16 x i32> %a to <16 x half> + ret <16 x half> %vec +} + +define <16 x half> @test_strict_uitofp_v16i32_v16f16(<16 x i32> %a) { +; AVX1-LABEL: test_strict_uitofp_v16i32_v16f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpsrld $16, %xmm3, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4] +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm4 = [65535,65535,65535,65535,65535,65535,65535,65535] +; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm2, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vpsrld $16, %xmm1, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vpsrld $16, %xmm5, %xmm5 +; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vandps %ymm4, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX1-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_strict_uitofp_v16i32_v16f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm3 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm4 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7],ymm0[8],ymm4[9],ymm0[10],ymm4[11],ymm0[12],ymm4[13],ymm0[14],ymm4[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm5 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm5, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0],ymm2[1],ymm1[2],ymm2[3],ymm1[4],ymm2[5],ymm1[6],ymm2[7],ymm1[8],ymm2[9],ymm1[10],ymm2[11],ymm1[12],ymm2[13],ymm1[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm4[1],ymm1[2],ymm4[3],ymm1[4],ymm4[5],ymm1[6],ymm4[7],ymm1[8],ymm4[9],ymm1[10],ymm4[11],ymm1[12],ymm4[13],ymm1[14],ymm4[15] +; AVX2-NEXT: vsubps %ymm5, %ymm1, %ymm1 +; AVX2-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_strict_uitofp_v16i32_v16f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %zmm0, %zmm0 +; AVX512-NEXT: vcvtps2ph $4, %zmm0, %ymm0 +; AVX512-NEXT: retq + %vec = tail call <16 x half> @llvm.experimental.constrained.uitofp.f16.i32(<16 x i32> %a, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret <16 x half> %vec +} diff --git a/llvm/test/CodeGen/X86/unreachable-loop-sinking.ll b/llvm/test/CodeGen/X86/unreachable-loop-sinking.ll index d784425d76d3..b09e2024db78 100644 --- a/llvm/test/CodeGen/X86/unreachable-loop-sinking.ll +++ b/llvm/test/CodeGen/X86/unreachable-loop-sinking.ll @@ -7,9 +7,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" -define double @fn1(ptr %arg, i64 %arg1) { +define double @fn1(ptr %arg, i64 %arg1, i1 %arg2) { Entry: - br i1 undef, label %Body, label %Exit + br i1 %arg2, label %Body, label %Exit Exit: ; preds = %Brancher7, %Entry ret double undef diff --git a/llvm/test/CodeGen/X86/update-terminator.mir b/llvm/test/CodeGen/X86/update-terminator.mir index d26f79750771..ff5df9ad8885 100644 --- a/llvm/test/CodeGen/X86/update-terminator.mir +++ b/llvm/test/CodeGen/X86/update-terminator.mir @@ -10,14 +10,14 @@ declare void @dummy3() ; Function Attrs: nounwind - define void @f2() { - br i1 undef, label %bb1, label %bb3 + define void @f2(i1 %arg) { + br i1 %arg, label %bb1, label %bb3 bb1: call void @dummy1() call void @dummy1() call void @dummy1() - br i1 undef, label %bb2, label %bb2 + br i1 %arg, label %bb2, label %bb2 bb2: call void @dummy2() diff --git a/llvm/test/CodeGen/X86/vec_saddo.ll b/llvm/test/CodeGen/X86/vec_saddo.ll index 460c5fe11f82..78dd2cf783ef 100644 --- a/llvm/test/CodeGen/X86/vec_saddo.ll +++ b/llvm/test/CodeGen/X86/vec_saddo.ll @@ -517,7 +517,7 @@ define <16 x i32> @saddo_v16i32(<16 x i32> %a0, <16 x i32> %a1, ptr %p2) nounwin ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm1 ; AVX512-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; AVX512-NEXT: kxorw %k1, %k0, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa64 %zmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i32>, <16 x i1>} @llvm.sadd.with.overflow.v16i32(<16 x i32> %a0, <16 x i32> %a1) @@ -647,7 +647,7 @@ define <16 x i32> @saddo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind { ; AVX512-NEXT: vpaddsb %xmm1, %xmm0, %xmm2 ; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm1 ; AVX512-NEXT: vpcmpneqb %xmm2, %xmm1, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa %xmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i8>, <16 x i1>} @llvm.sadd.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) @@ -993,7 +993,7 @@ define <4 x i32> @saddo_v4i24(<4 x i24> %a0, <4 x i24> %a1, ptr %p2) nounwind { ; AVX512-NEXT: vpslld $8, %xmm1, %xmm0 ; AVX512-NEXT: vpsrad $8, %xmm0, %xmm0 ; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq {{.*#+}} xmm0 = ~xmm0 ; AVX512-NEXT: vpextrd $3, %xmm1, %eax ; AVX512-NEXT: movw %ax, 9(%rdi) ; AVX512-NEXT: vpextrd $2, %xmm1, %ecx diff --git a/llvm/test/CodeGen/X86/vec_ssubo.ll b/llvm/test/CodeGen/X86/vec_ssubo.ll index d06993da6365..746c09e5e70d 100644 --- a/llvm/test/CodeGen/X86/vec_ssubo.ll +++ b/llvm/test/CodeGen/X86/vec_ssubo.ll @@ -522,7 +522,7 @@ define <16 x i32> @ssubo_v16i32(<16 x i32> %a0, <16 x i32> %a1, ptr %p2) nounwin ; AVX512-NEXT: vpsubd %zmm1, %zmm0, %zmm1 ; AVX512-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; AVX512-NEXT: kxorw %k1, %k0, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa64 %zmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i32>, <16 x i1>} @llvm.ssub.with.overflow.v16i32(<16 x i32> %a0, <16 x i32> %a1) @@ -652,7 +652,7 @@ define <16 x i32> @ssubo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind { ; AVX512-NEXT: vpsubsb %xmm1, %xmm0, %xmm2 ; AVX512-NEXT: vpsubb %xmm1, %xmm0, %xmm1 ; AVX512-NEXT: vpcmpneqb %xmm2, %xmm1, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa %xmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i8>, <16 x i1>} @llvm.ssub.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) @@ -1010,7 +1010,7 @@ define <4 x i32> @ssubo_v4i24(<4 x i24> %a0, <4 x i24> %a1, ptr %p2) nounwind { ; AVX512-NEXT: vpslld $8, %xmm1, %xmm0 ; AVX512-NEXT: vpsrad $8, %xmm0, %xmm0 ; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq {{.*#+}} xmm0 = ~xmm0 ; AVX512-NEXT: vpextrd $3, %xmm1, %eax ; AVX512-NEXT: movw %ax, 9(%rdi) ; AVX512-NEXT: vpextrd $2, %xmm1, %ecx diff --git a/llvm/test/CodeGen/X86/vec_uaddo.ll b/llvm/test/CodeGen/X86/vec_uaddo.ll index bac118095331..be7888cd76a6 100644 --- a/llvm/test/CodeGen/X86/vec_uaddo.ll +++ b/llvm/test/CodeGen/X86/vec_uaddo.ll @@ -604,7 +604,7 @@ define <16 x i32> @uaddo_v16i32(<16 x i32> %a0, <16 x i32> %a1, ptr %p2) nounwin ; AVX512: # %bb.0: ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm1 ; AVX512-NEXT: vpcmpltud %zmm0, %zmm1, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa64 %zmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i32>, <16 x i1>} @llvm.uadd.with.overflow.v16i32(<16 x i32> %a0, <16 x i32> %a1) @@ -730,7 +730,7 @@ define <16 x i32> @uaddo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind { ; AVX512: # %bb.0: ; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm1 ; AVX512-NEXT: vpcmpltub %xmm0, %xmm1, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa %xmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i8>, <16 x i1>} @llvm.uadd.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) @@ -1046,7 +1046,7 @@ define <4 x i32> @uaddo_v4i24(<4 x i24> %a0, <4 x i24> %a1, ptr %p2) nounwind { ; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm1 ; AVX512-NEXT: vpand %xmm2, %xmm1, %xmm0 ; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq {{.*#+}} xmm0 = ~xmm0 ; AVX512-NEXT: vpextrd $3, %xmm1, %eax ; AVX512-NEXT: movw %ax, 9(%rdi) ; AVX512-NEXT: vpextrd $2, %xmm1, %ecx diff --git a/llvm/test/CodeGen/X86/vec_usubo.ll b/llvm/test/CodeGen/X86/vec_usubo.ll index ab75ada72f25..ceb1ad13bc15 100644 --- a/llvm/test/CodeGen/X86/vec_usubo.ll +++ b/llvm/test/CodeGen/X86/vec_usubo.ll @@ -647,7 +647,7 @@ define <16 x i32> @usubo_v16i32(<16 x i32> %a0, <16 x i32> %a1, ptr %p2) nounwin ; AVX512: # %bb.0: ; AVX512-NEXT: vpsubd %zmm1, %zmm0, %zmm1 ; AVX512-NEXT: vpcmpnleud %zmm0, %zmm1, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa64 %zmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i32>, <16 x i1>} @llvm.usub.with.overflow.v16i32(<16 x i32> %a0, <16 x i32> %a1) @@ -773,7 +773,7 @@ define <16 x i32> @usubo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind { ; AVX512: # %bb.0: ; AVX512-NEXT: vpsubb %xmm1, %xmm0, %xmm1 ; AVX512-NEXT: vpcmpnleub %xmm0, %xmm1, %k1 -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 ; AVX512-NEXT: vmovdqa %xmm1, (%rdi) ; AVX512-NEXT: retq %t = call {<16 x i8>, <16 x i1>} @llvm.usub.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) @@ -1093,7 +1093,7 @@ define <4 x i32> @usubo_v4i24(<4 x i24> %a0, <4 x i24> %a1, ptr %p2) nounwind { ; AVX512-NEXT: vpsubd %xmm1, %xmm0, %xmm1 ; AVX512-NEXT: vpand %xmm2, %xmm1, %xmm0 ; AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq {{.*#+}} xmm0 = ~xmm0 ; AVX512-NEXT: vpextrd $3, %xmm1, %eax ; AVX512-NEXT: movw %ax, 9(%rdi) ; AVX512-NEXT: vpextrd $2, %xmm1, %ecx diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll index 4f42d5c65528..15e287d66754 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll @@ -4129,6 +4129,62 @@ define <32 x i8> @shuffle_v32i8_56_zz_zz_zz_57_zz_zz_zz_58_zz_zz_zz__zz_59_zz_zz ret <32 x i8> %shuffle } +; PR121823 +define <32 x i8> @shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz(<32 x i8> %a) { +; AVX1-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[1,9,0,3] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,9,0,3,11,2,5,13,4,7,15,6],zero,zero,zero,zero +; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[11,2,5,13,4,7,15,6],zero,zero,zero,zero,zero,zero,zero,zero +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX2: # %bb.0: +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,9,0,3,11,2,5,13,4,7,15,6,u,u,u,u,17,25,16,19,27,18,21,29,20,23,31,22,u,u,u,u] +; AVX2-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,2,4,5,6,0,0] +; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; AVX2-NEXT: retq +; +; AVX512VLBW-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX512VLBW: # %bb.0: +; AVX512VLBW-NEXT: vpshufb {{.*#+}} ymm1 = ymm0[1,9,0,3,11,2,5,13,4,7,15,6,u,u,u,u,17,25,16,19,27,18,21,29,20,23,31,22,u,u,u,u] +; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512VLBW-NEXT: vpmovsxbd {{.*#+}} ymm0 = [0,1,2,4,5,6,14,15] +; AVX512VLBW-NEXT: vpermi2d %ymm2, %ymm1, %ymm0 +; AVX512VLBW-NEXT: retq +; +; AVX512VLVBMI-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX512VLVBMI: # %bb.0: +; AVX512VLVBMI-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VLVBMI-NEXT: vmovdqa {{.*#+}} ymm2 = [1,9,0,3,11,2,5,13,4,7,15,6,17,25,16,19,27,18,21,29,20,23,31,22,56,57,58,59,60,61,62,63] +; AVX512VLVBMI-NEXT: vpermt2b %ymm1, %ymm2, %ymm0 +; AVX512VLVBMI-NEXT: retq +; +; XOPAVX1-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; XOPAVX1: # %bb.0: +; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; XOPAVX1-NEXT: vpperm {{.*#+}} xmm0 = xmm0[1,9,0,3,11,2,5,13,4,7,15,6],xmm1[1,9,0,3] +; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[11,2,5,13,4,7,15,6],zero,zero,zero,zero,zero,zero,zero,zero +; XOPAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; XOPAVX1-NEXT: retq +; +; XOPAVX2-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; XOPAVX2: # %bb.0: +; XOPAVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,9,0,3,11,2,5,13,4,7,15,6,u,u,u,u,17,25,16,19,27,18,21,29,20,23,31,22,u,u,u,u] +; XOPAVX2-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,2,4,5,6,0,0] +; XOPAVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0 +; XOPAVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; XOPAVX2-NEXT: retq + %r = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 9, i32 0, i32 3, i32 11, i32 2, i32 5, i32 13, i32 4, i32 7, i32 15, i32 6, i32 17, i32 25, i32 16, i32 19, i32 27, i32 18, i32 21, i32 29, i32 20, i32 23, i32 31, i32 22, i32 32, i32 32, i32 32, i32 32, i32 48, i32 48, i32 48, i32 48> + ret <32 x i8> %r +} + define <32 x i8> @shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30(<32 x i8> %a, <32 x i8> %b) { ; AVX1-LABEL: shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30: ; AVX1: # %bb.0: diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll index f0b70ae26b1f..4125d7878371 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll @@ -190,7 +190,7 @@ define i64 @PR55050() { entry: %i275 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> undef, <16 x i8> zeroinitializer) %i277 = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> undef, <16 x i8> zeroinitializer) - br i1 undef, label %exit, label %if + br i1 poison, label %exit, label %if if: %i298 = bitcast <2 x i64> %i275 to <4 x i32> diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll index fe7459ea45e1..928f29b7b188 100644 --- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll @@ -868,7 +868,7 @@ define void @infiniteloop() { ; DISABLE-NEXT: popq %rbp ; DISABLE-NEXT: retq entry: - br i1 undef, label %if.then, label %if.end + br i1 poison, label %if.then, label %if.end if.then: %ptr = alloca i32, i32 4 @@ -983,7 +983,7 @@ define void @infiniteloop2() { ; DISABLE-NEXT: popq %rbp ; DISABLE-NEXT: retq entry: - br i1 undef, label %if.then, label %if.end + br i1 poison, label %if.then, label %if.end if.then: %ptr = alloca i32, i32 4 @@ -994,7 +994,7 @@ for.body: ; preds = %for.body, %entry %call = tail call i32 asm "movl $$1, $0", "=r,~{ebx}"() %add = add nsw i32 %call, %sum.03 store i32 %add, ptr %ptr - br i1 undef, label %body1, label %body2 + br i1 poison, label %body1, label %body2 body1: tail call void asm sideeffect "nop", "~{ebx}"() @@ -1074,10 +1074,10 @@ define void @infiniteloop3() { ; DISABLE-NEXT: LBB12_7: ## %end ; DISABLE-NEXT: retq entry: - br i1 undef, label %loop2a, label %body + br i1 poison, label %loop2a, label %body body: ; preds = %entry - br i1 undef, label %loop2a, label %end + br i1 poison, label %loop2a, label %end loop1: ; preds = %loop2a, %loop2b %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ] |