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-rw-r--r--llvm/test/CodeGen/WebAssembly/exception-legacy.ll52
-rw-r--r--llvm/test/CodeGen/WebAssembly/half-precision.ll36
-rw-r--r--llvm/test/CodeGen/WebAssembly/libcalls.ll69
-rw-r--r--llvm/test/CodeGen/WebAssembly/simd-unsupported.ll16
-rw-r--r--llvm/test/CodeGen/WebAssembly/target-features-attrs.ll84
-rw-r--r--llvm/test/CodeGen/WebAssembly/target-features-cpus.ll48
-rw-r--r--llvm/test/CodeGen/WebAssembly/target-features.ll116
7 files changed, 272 insertions, 149 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/exception-legacy.ll b/llvm/test/CodeGen/WebAssembly/exception-legacy.ll
index dfa33f95f37b..3537baa42516 100644
--- a/llvm/test/CodeGen/WebAssembly/exception-legacy.ll
+++ b/llvm/test/CodeGen/WebAssembly/exception-legacy.ll
@@ -350,8 +350,60 @@ ehcleanupret: ; preds = %catch.start, %ehcle
cleanupret from %0 unwind to caller
}
+; Regression test for the bug that 'rethrow' was not treated correctly as a
+; terminator in isel.
+define void @test_rethrow_terminator() personality ptr @__gxx_wasm_personality_v0 {
+entry:
+ invoke void @foo()
+ to label %try.cont unwind label %catch.dispatch
+
+catch.dispatch: ; preds = %entry
+ %0 = catchswitch within none [label %catch.start] unwind label %ehcleanup
+
+catch.start: ; preds = %catch.dispatch
+ %1 = catchpad within %0 [ptr @_ZTIi]
+ %2 = call ptr @llvm.wasm.get.exception(token %1)
+ %3 = call i32 @llvm.wasm.get.ehselector(token %1)
+ %4 = call i32 @llvm.eh.typeid.for.p0(ptr @_ZTIi)
+ %matches = icmp eq i32 %3, %4
+ br i1 %matches, label %catch, label %rethrow
+
+catch: ; preds = %catch.start
+ %5 = call ptr @__cxa_begin_catch(ptr %2) [ "funclet"(token %1) ]
+ %6 = load i32, ptr %5, align 4
+ call void @__cxa_end_catch() [ "funclet"(token %1) ]
+ catchret from %1 to label %try.cont
+
+rethrow: ; preds = %catch.start
+ invoke void @llvm.wasm.rethrow() #1 [ "funclet"(token %1) ]
+ to label %unreachable unwind label %ehcleanup
+
+try.cont: ; preds = %entry, %catch
+ ret void
+
+ehcleanup: ; preds = %rethrow, %catch.dispatch
+ ; 'rethrow' BB is this BB's predecessor, and its
+ ; 'invoke void @llvm.wasm.rethrow()' is lowered down to a 'RETHROW' in Wasm
+ ; MIR. And this 'phi' creates 'CONST_I32' instruction in the predecessor
+ ; 'rethrow' BB. If 'RETHROW' is not treated correctly as a terminator, it can
+ ; create a BB like
+ ; bb.3.rethrow:
+ ; RETHROW 0
+ ; %0 = CONST_I32 20
+ ; BR ...
+ %tmp = phi i32 [ 10, %catch.dispatch ], [ 20, %rethrow ]
+ %7 = cleanuppad within none []
+ call void @take_i32(i32 %tmp) [ "funclet"(token %7) ]
+ cleanupret from %7 unwind to caller
+
+unreachable: ; preds = %rethrow
+ unreachable
+}
+
+
declare void @foo()
declare void @bar(ptr)
+declare void @take_i32(i32)
declare i32 @__gxx_wasm_personality_v0(...)
; Function Attrs: noreturn
declare void @llvm.wasm.throw(i32, ptr) #1
diff --git a/llvm/test/CodeGen/WebAssembly/half-precision.ll b/llvm/test/CodeGen/WebAssembly/half-precision.ll
index 0f0a15909151..fa78f5f9591d 100644
--- a/llvm/test/CodeGen/WebAssembly/half-precision.ll
+++ b/llvm/test/CodeGen/WebAssembly/half-precision.ll
@@ -246,3 +246,39 @@ define <8 x half> @nearest_v8f16_via_roundeven(<8 x half> %a) {
%v = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %a)
ret <8 x half> %v
}
+
+define <8 x half> @convert_s_v8f16(<8 x i16> %x) {
+; CHECK-LABEL: convert_s_v8f16:
+; CHECK: .functype convert_s_v8f16 (v128) -> (v128)
+; CHECK-NEXT: f16x8.convert_i16x8_s $push0=, $0
+; CHECK-NEXT: return $pop[[R]]{{$}}
+ %a = sitofp <8 x i16> %x to <8 x half>
+ ret <8 x half> %a
+}
+
+define <8 x half> @convert_u_v8f16(<8 x i16> %x) {
+; CHECK-LABEL: convert_u_v8f16:
+; CHECK: .functype convert_u_v8f16 (v128) -> (v128)
+; CHECK-NEXT: f16x8.convert_i16x8_u $push0=, $0
+; CHECK-NEXT: return $pop[[R]]{{$}}
+ %a = uitofp <8 x i16> %x to <8 x half>
+ ret <8 x half> %a
+}
+
+define <8 x i16> @trunc_sat_s_v8i16(<8 x half> %x) {
+; CHECK-LABEL: trunc_sat_s_v8i16:
+; CHECK: .functype trunc_sat_s_v8i16 (v128) -> (v128)
+; CHECK-NEXT: i16x8.trunc_sat_f16x8_s $push0=, $0
+; CHECK-NEXT: return $pop[[R]]{{$}}
+ %a = fptosi <8 x half> %x to <8 x i16>
+ ret <8 x i16> %a
+}
+
+define <8 x i16> @trunc_sat_u_v8i16(<8 x half> %x) {
+; CHECK-LABEL: trunc_sat_u_v8i16:
+; CHECK: .functype trunc_sat_u_v8i16 (v128) -> (v128)
+; CHECK-NEXT: i16x8.trunc_sat_f16x8_u $push0=, $0
+; CHECK-NEXT: return $pop[[R]]{{$}}
+ %a = fptoui <8 x half> %x to <8 x i16>
+ ret <8 x i16> %a
+}
diff --git a/llvm/test/CodeGen/WebAssembly/libcalls.ll b/llvm/test/CodeGen/WebAssembly/libcalls.ll
index 4f57c347a1a3..70f000664d38 100644
--- a/llvm/test/CodeGen/WebAssembly/libcalls.ll
+++ b/llvm/test/CodeGen/WebAssembly/libcalls.ll
@@ -12,6 +12,7 @@ declare fp128 @llvm.nearbyint.f128(fp128)
declare fp128 @llvm.pow.f128(fp128, fp128)
declare fp128 @llvm.powi.f128.i32(fp128, i32)
+declare double @llvm.tan.f64(double)
declare double @llvm.cos.f64(double)
declare double @llvm.log10.f64(double)
declare double @llvm.pow.f64(double, double)
@@ -240,42 +241,44 @@ define double @f64libcalls(double %x, double %y, i32 %z) {
; CHECK: .functype f64libcalls (f64, f64, i32) -> (f64)
; CHECK-NEXT: .local i32
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: global.get $push11=, __stack_pointer
-; CHECK-NEXT: i32.const $push12=, 16
-; CHECK-NEXT: i32.sub $push18=, $pop11, $pop12
-; CHECK-NEXT: local.tee $push17=, 3, $pop18
-; CHECK-NEXT: global.set __stack_pointer, $pop17
-; CHECK-NEXT: local.get $push22=, 0
-; CHECK-NEXT: local.get $push19=, 0
-; CHECK-NEXT: call $push0=, cos, $pop19
-; CHECK-NEXT: call $push1=, log10, $pop0
-; CHECK-NEXT: local.get $push20=, 1
-; CHECK-NEXT: call $push2=, pow, $pop1, $pop20
-; CHECK-NEXT: local.get $push21=, 2
-; CHECK-NEXT: call $push3=, __powidf2, $pop2, $pop21
-; CHECK-NEXT: call $push4=, log, $pop3
-; CHECK-NEXT: call $push5=, exp, $pop4
-; CHECK-NEXT: call $push6=, exp10, $pop5
-; CHECK-NEXT: call $push7=, cbrt, $pop6
-; CHECK-NEXT: call $push8=, lround, $pop7
-; CHECK-NEXT: call $push9=, ldexp, $pop22, $pop8
-; CHECK-NEXT: local.get $push23=, 3
-; CHECK-NEXT: i32.const $push15=, 12
-; CHECK-NEXT: i32.add $push16=, $pop23, $pop15
-; CHECK-NEXT: call $push24=, frexp, $pop9, $pop16
-; CHECK-NEXT: local.set 0, $pop24
-; CHECK-NEXT: local.get $push25=, 3
-; CHECK-NEXT: i32.load $push10=, 12($pop25)
-; CHECK-NEXT: call escape_value, $pop10
-; CHECK-NEXT: local.get $push26=, 3
+; CHECK-NEXT: global.get $push12=, __stack_pointer
; CHECK-NEXT: i32.const $push13=, 16
-; CHECK-NEXT: i32.add $push14=, $pop26, $pop13
-; CHECK-NEXT: global.set __stack_pointer, $pop14
-; CHECK-NEXT: local.get $push27=, 0
-; CHECK-NEXT: return $pop27
+; CHECK-NEXT: i32.sub $push19=, $pop12, $pop13
+; CHECK-NEXT: local.tee $push18=, 3, $pop19
+; CHECK-NEXT: global.set __stack_pointer, $pop18
+; CHECK-NEXT: local.get $push23=, 0
+; CHECK-NEXT: local.get $push20=, 0
+; CHECK-NEXT: call $push0=, tan, $pop20
+; CHECK-NEXT: call $push1=, cos, $pop0
+; CHECK-NEXT: call $push2=, log10, $pop1
+; CHECK-NEXT: local.get $push21=, 1
+; CHECK-NEXT: call $push3=, pow, $pop2, $pop21
+; CHECK-NEXT: local.get $push22=, 2
+; CHECK-NEXT: call $push4=, __powidf2, $pop3, $pop22
+; CHECK-NEXT: call $push5=, log, $pop4
+; CHECK-NEXT: call $push6=, exp, $pop5
+; CHECK-NEXT: call $push7=, exp10, $pop6
+; CHECK-NEXT: call $push8=, cbrt, $pop7
+; CHECK-NEXT: call $push9=, lround, $pop8
+; CHECK-NEXT: call $push10=, ldexp, $pop23, $pop9
+; CHECK-NEXT: local.get $push24=, 3
+; CHECK-NEXT: i32.const $push16=, 12
+; CHECK-NEXT: i32.add $push17=, $pop24, $pop16
+; CHECK-NEXT: call $push25=, frexp, $pop10, $pop17
+; CHECK-NEXT: local.set 0, $pop25
+; CHECK-NEXT: local.get $push26=, 3
+; CHECK-NEXT: i32.load $push11=, 12($pop26)
+; CHECK-NEXT: call escape_value, $pop11
+; CHECK-NEXT: local.get $push27=, 3
+; CHECK-NEXT: i32.const $push14=, 16
+; CHECK-NEXT: i32.add $push15=, $pop27, $pop14
+; CHECK-NEXT: global.set __stack_pointer, $pop15
+; CHECK-NEXT: local.get $push28=, 0
+; CHECK-NEXT: return $pop28
- %a = call double @llvm.cos.f64(double %x)
+ %k = call double @llvm.tan.f64(double %x)
+ %a = call double @llvm.cos.f64(double %k)
%b = call double @llvm.log10.f64(double %a)
%c = call double @llvm.pow.f64(double %b, double %y)
%d = call double @llvm.powi.f64.i32(double %c, i32 %z)
diff --git a/llvm/test/CodeGen/WebAssembly/simd-unsupported.ll b/llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
index d214a3af5a15..1d6e073271ef 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-unsupported.ll
@@ -377,6 +377,14 @@ define <4 x float> @cos_v4f32(<4 x float> %x) {
ret <4 x float> %v
}
+; CHECK-LABEL: tan_v4f32:
+; CHECK: call $push[[L:[0-9]+]]=, tanf
+declare <4 x float> @llvm.tan.v4f32(<4 x float>)
+define <4 x float> @tan_v4f32(<4 x float> %x) {
+ %v = call <4 x float> @llvm.tan.v4f32(<4 x float> %x)
+ ret <4 x float> %v
+}
+
; CHECK-LABEL: powi_v4f32:
; CHECK: call $push[[L:[0-9]+]]=, __powisf2
declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32)
@@ -469,6 +477,14 @@ define <2 x double> @cos_v2f64(<2 x double> %x) {
ret <2 x double> %v
}
+; CHECK-LABEL: tan_v2f64:
+; CHECK: call $push[[L:[0-9]+]]=, tan
+declare <2 x double> @llvm.tan.v2f64(<2 x double>)
+define <2 x double> @tan_v2f64(<2 x double> %x) {
+ %v = call <2 x double> @llvm.tan.v2f64(<2 x double> %x)
+ ret <2 x double> %v
+}
+
; CHECK-LABEL: powi_v2f64:
; CHECK: call $push[[L:[0-9]+]]=, __powidf2
declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32)
diff --git a/llvm/test/CodeGen/WebAssembly/target-features-attrs.ll b/llvm/test/CodeGen/WebAssembly/target-features-attrs.ll
new file mode 100644
index 000000000000..25dee51ac8c3
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/target-features-attrs.ll
@@ -0,0 +1,84 @@
+; RUN: llc -mcpu=mvp < %s | FileCheck %s
+; RUN: llc -mcpu=mvp -mattr=+simd128 < %s | FileCheck %s --check-prefixes SIMD128
+
+; Test that codegen emits target features from the command line or
+; function attributes correctly and that features are enabled for the
+; entire module if they are enabled for any function in the module.
+
+target triple = "wasm32-unknown-unknown"
+
+define void @fn_atomics(ptr %p1, float %f2) #0 {
+ %a = atomicrmw min ptr undef, i32 42 seq_cst
+ %v = fptoui float %f2 to i32
+ store i32 %v, ptr %p1
+ ret void
+}
+
+define void @fn_nontrapping_fptoint(ptr %p1, float %f2) #1 {
+ %a = atomicrmw min ptr undef, i32 42 seq_cst
+ %v = fptoui float %f2 to i32
+ store i32 %v, ptr %p1
+ ret void
+}
+
+define void @fn_reference_types() #2 {
+ ret void
+}
+
+attributes #0 = { "target-features"="+atomics" }
+attributes #1 = { "target-features"="+nontrapping-fptoint" }
+attributes #2 = { "target-features"="+reference-types" }
+
+; CHECK-LABEL: fn_atomics:
+
+; Expanded atomicrmw min
+; CHECK: loop
+; CHECK: i32.atomic.rmw.cmpxchg
+; CHECK: end_loop
+
+; nontrapping fptoint
+; CHECK: i32.trunc_sat_f32_u
+; CHECK: i32.store
+
+; `fn_nontrapping_fptoint` should be the same as `fn_atomics`
+; CHECK-LABEL: fn_nontrapping_fptoint:
+
+; Expanded atomicrmw min
+; CHECK: loop
+; CHECK: i32.atomic.rmw.cmpxchg
+; CHECK: end_loop
+
+; nontrapping fptoint
+; CHECK: i32.trunc_sat_f32_u
+; CHECK: i32.store
+
+; Features in function attributes:
+; +atomics, +nontrapping-fptoint, +reference-types
+; CHECK-LABEL: .custom_section.target_features,"",@
+; CHECK-NEXT: .int8 3
+; CHECK-NEXT: .int8 43
+; CHECK-NEXT: .int8 7
+; CHECK-NEXT: .ascii "atomics"
+; CHECK-NEXT: .int8 43
+; CHECK-NEXT: .int8 19
+; CHECK-NEXT: .ascii "nontrapping-fptoint"
+; CHECK-NEXT: .int8 43
+; CHECK-NEXT: .int8 15
+; CHECK-NEXT: .ascii "reference-types"
+
+; Features in function attributes + features specified by -mattr= option:
+; +atomics, +nontrapping-fptoint, +reference-types, +simd128
+; SIMD128-LABEL: .custom_section.target_features,"",@
+; SIMD128-NEXT: .int8 4
+; SIMD128-NEXT: .int8 43
+; SIMD128-NEXT: .int8 7
+; SIMD128-NEXT: .ascii "atomics"
+; SIMD128-NEXT: .int8 43
+; SIMD128-NEXT: .int8 19
+; SIMD128-NEXT: .ascii "nontrapping-fptoint"
+; SIMD128-NEXT: .int8 43
+; SIMD128-NEXT: .int8 15
+; SIMD128-NEXT: .ascii "reference-types"
+; SIMD128-NEXT: .int8 43
+; SIMD128-NEXT: .int8 7
+; SIMD128-NEXT: .ascii "simd128"
diff --git a/llvm/test/CodeGen/WebAssembly/target-features-cpus.ll b/llvm/test/CodeGen/WebAssembly/target-features-cpus.ll
new file mode 100644
index 000000000000..d368271682a9
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/target-features-cpus.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -mcpu=mvp | FileCheck %s --check-prefixes MVP
+; RUN: llc < %s -mcpu=generic | FileCheck %s --check-prefixes GENERIC
+; RUN: llc < %s | FileCheck %s --check-prefixes GENERIC
+; RUN: llc < %s -mcpu=bleeding-edge | FileCheck %s --check-prefixes BLEEDING-EDGE
+
+; Test that the target features section contains the correct set of features
+; depending on -mcpu= options.
+
+target triple = "wasm32-unknown-unknown"
+
+; mvp: should not contain the target features section
+; MVP-NOT: .custom_section.target_features,"",@
+
+; generic: +mutable-globals, +sign-ext
+; GENERIC-LABEL: .custom_section.target_features,"",@
+; GENERIC-NEXT: .int8 2
+; GENERIC-NEXT: .int8 43
+; GENERIC-NEXT: .int8 15
+; GENERIC-NEXT: .ascii "mutable-globals"
+; GENERIC-NEXT: .int8 43
+; GENERIC-NEXT: .int8 8
+; GENERIC-NEXT: .ascii "sign-ext"
+
+; bleeding-edge: +atomics, +bulk-memory, +mutable-globals, +nontrapping-fptoint,
+; +sign-ext, +simd128, +tail-call
+; BLEEDING-EDGE-LABEL: .section .custom_section.target_features,"",@
+; BLEEDING-EDGE-NEXT: .int8 7
+; BLEEDING-EDGE-NEXT: .int8 43
+; BLEEDING-EDGE-NEXT: .int8 7
+; BLEEDING-EDGE-NEXT: .ascii "atomics"
+; BLEEDING-EDGE-NEXT: .int8 43
+; BLEEDING-EDGE-NEXT: .int8 11
+; BLEEDING-EDGE-NEXT: .ascii "bulk-memory"
+; BLEEDING-EDGE-NEXT: .int8 43
+; BLEEDING-EDGE-NEXT: .int8 15
+; BLEEDING-EDGE-NEXT: .ascii "mutable-globals"
+; BLEEDING-EDGE-NEXT: .int8 43
+; BLEEDING-EDGE-NEXT: .int8 19
+; BLEEDING-EDGE-NEXT: .ascii "nontrapping-fptoint"
+; BLEEDING-EDGE-NEXT: .int8 43
+; BLEEDING-EDGE-NEXT: .int8 8
+; BLEEDING-EDGE-NEXT: .ascii "sign-ext"
+; BLEEDING-EDGE-NEXT: .int8 43
+; BLEEDING-EDGE-NEXT: .int8 7
+; BLEEDING-EDGE-NEXT: .ascii "simd128"
+; BLEEDING-EDGE-NEXT: .int8 43
+; BLEEDING-EDGE-NEXT: .int8 9
+; BLEEDING-EDGE-NEXT: .ascii "tail-call"
diff --git a/llvm/test/CodeGen/WebAssembly/target-features.ll b/llvm/test/CodeGen/WebAssembly/target-features.ll
deleted file mode 100644
index 953a4ac9b41d..000000000000
--- a/llvm/test/CodeGen/WebAssembly/target-features.ll
+++ /dev/null
@@ -1,116 +0,0 @@
-; RUN: llc < %s | FileCheck %s --check-prefixes CHECK,ATTRS
-; RUN: llc < %s -mcpu=mvp -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -mcpu=bleeding-edge | FileCheck %s --check-prefixes CHECK,BLEEDING-EDGE
-
-; Test that codegen emits target features from the command line or
-; function attributes correctly and that features are enabled for the
-; entire module if they are enabled for any function in the module.
-
-target triple = "wasm32-unknown-unknown"
-
-define void @fn_atomics(ptr %p1, float %f2) #0 {
- %a = atomicrmw min ptr undef, i32 42 seq_cst
- %v = fptoui float %f2 to i32
- store i32 %v, ptr %p1
- ret void
-}
-
-define void @fn_nontrapping_fptoint(ptr %p1, float %f2) #1 {
- %a = atomicrmw min ptr undef, i32 42 seq_cst
- %v = fptoui float %f2 to i32
- store i32 %v, ptr %p1
- ret void
-}
-
-define void @fn_reference_types() #2 {
- ret void
-}
-
-attributes #0 = { "target-features"="+atomics" }
-attributes #1 = { "target-features"="+nontrapping-fptoint" }
-attributes #2 = { "target-features"="+reference-types" }
-
-; CHECK-LABEL: fn_atomics:
-
-; Expanded atomicrmw min
-; ATTRS: loop
-; CHECK: i32.atomic.rmw.cmpxchg
-; ATTRS: end_loop
-
-; nontrapping fptoint
-; CHECK: i32.trunc_sat_f32_u
-; ATTRS: i32.store
-
-; `fn_nontrapping_fptoint` should be the same as `fn_atomics`
-; CHECK-LABEL: fn_nontrapping_fptoint:
-
-; Expanded atomicrmw min
-; ATTRS: loop
-; CHECK: i32.atomic.rmw.cmpxchg
-; ATTRS: end_loop
-
-; nontrapping fptoint
-; CHECK: i32.trunc_sat_f32_u
-; ATTRS: i32.store
-
-; CHECK-LABEL: .custom_section.target_features,"",@
-
-; +atomics, +reference-types, +mutable-globals
-; ATTRS-NEXT: .int8 5
-; ATTRS-NEXT: .int8 43
-; ATTRS-NEXT: .int8 7
-; ATTRS-NEXT: .ascii "atomics"
-; ATTRS-NEXT: .int8 43
-; ATTRS-NEXT: .int8 15
-; ATTRS-NEXT: .ascii "mutable-globals"
-; ATTRS-NEXT: .int8 43
-; ATTRS-NEXT: .int8 19
-; ATTRS-NEXT: .ascii "nontrapping-fptoint"
-; ATTRS-NEXT: .int8 43
-; ATTRS-NEXT: .int8 15
-; ATTRS-NEXT: .ascii "reference-types"
-; ATTRS-NEXT: .int8 43
-; ATTRS-NEXT: .int8 8
-
-; +atomics, +nontrapping-fptoint, +reference-types, +simd128
-; SIMD128-NEXT: .int8 4
-; SIMD128-NEXT: .int8 43
-; SIMD128-NEXT: .int8 7
-; SIMD128-NEXT: .ascii "atomics"
-; SIMD128-NEXT: .int8 43
-; SIMD128-NEXT: .int8 19
-; SIMD128-NEXT: .ascii "nontrapping-fptoint"
-; SIMD128-NEXT: .int8 43
-; SIMD128-NEXT: .int8 15
-; SIMD128-NEXT: .ascii "reference-types"
-; SIMD128-NEXT: .int8 43
-; SIMD128-NEXT: .int8 7
-; SIMD128-NEXT: .ascii "simd128"
-
-; +atomics, +bulk-memory, +mutable-globals, +nontrapping-fptoint,
-; +reference-types, +sign-ext, +simd128, +tail-call
-; BLEEDING-EDGE-NEXT: .int8 8
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 7
-; BLEEDING-EDGE-NEXT: .ascii "atomics"
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 11
-; BLEEDING-EDGE-NEXT: .ascii "bulk-memory"
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 15
-; BLEEDING-EDGE-NEXT: .ascii "mutable-globals"
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 19
-; BLEEDING-EDGE-NEXT: .ascii "nontrapping-fptoint"
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 15
-; BLEEDING-EDGE-NEXT: .ascii "reference-types"
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 8
-; BLEEDING-EDGE-NEXT: .ascii "sign-ext"
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 7
-; BLEEDING-EDGE-NEXT: .ascii "simd128"
-; BLEEDING-EDGE-NEXT: .int8 43
-; BLEEDING-EDGE-NEXT: .int8 9
-; BLEEDING-EDGE-NEXT: .ascii "tail-call"
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 15:48:12 +0000