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-rw-r--r--llvm/test/CodeGen/SystemZ/builtin-longjmp.ll49
-rw-r--r--llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll156
-rw-r--r--llvm/test/CodeGen/SystemZ/builtin-setjmp-spills.ll254
-rw-r--r--llvm/test/CodeGen/SystemZ/builtin-setjmp.ll124
-rw-r--r--llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir9
-rw-r--r--llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir43
-rw-r--r--llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir100
-rw-r--r--llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir87
-rw-r--r--llvm/test/CodeGen/SystemZ/stackmap-args.ll22
9 files changed, 725 insertions, 119 deletions
diff --git a/llvm/test/CodeGen/SystemZ/builtin-longjmp.ll b/llvm/test/CodeGen/SystemZ/builtin-longjmp.ll
new file mode 100644
index 000000000000..c1d3dc54b2fd
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/builtin-longjmp.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test longjmp load from jmp_buf.
+; Frame pointer from Slot 1.
+; Jump address from Slot 2.
+; Backchain Value from Slot 3.
+; Stack Pointer from Slot 4.
+; Literal Pool Pointer from Slot 5.
+
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu | FileCheck %s
+
+@buf = global [20 x ptr] zeroinitializer, align 8
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: lgrl %r1, buf@GOT
+; CHECK-NEXT: lg %r2, 8(%r1)
+; CHECK-NEXT: lg %r11, 0(%r1)
+; CHECK-NEXT: lg %r13, 32(%r1)
+; CHECK-NEXT: lg %r15, 24(%r1)
+; CHECK-NEXT: br %r2
+entry:
+ tail call void @llvm.eh.sjlj.longjmp(ptr nonnull @buf)
+ unreachable
+}
+
+define void @bar() "backchain" {
+; CHECK-LABEL: bar:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: lgrl %r1, buf@GOT
+; CHECK-NEXT: lg %r2, 8(%r1)
+; CHECK-NEXT: lg %r11, 0(%r1)
+; CHECK-NEXT: lg %r13, 32(%r1)
+; CHECK-NEXT: lg %r3, 16(%r1)
+; CHECK-NEXT: lg %r15, 24(%r1)
+; CHECK-NEXT: stg %r3, 0(%r15)
+; CHECK-NEXT: br %r2
+entry:
+ tail call void @llvm.eh.sjlj.longjmp(ptr nonnull @buf)
+ unreachable
+}
diff --git a/llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll b/llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll
new file mode 100644
index 000000000000..f714599f9a8f
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/builtin-setjmp-alloca.ll
@@ -0,0 +1,156 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test setjmp store to jmp_buf when frame pointer is used and saved
+; because of variable size alloca.
+; Frame Pointer is stored in slot 1.
+; Return address in slot 2.
+; Backchain value is stored in slot 3 for -mbackchain option.
+; Stack Pointer in slot 4.
+; Clobber %r6-%r15, %f8-%f15.
+
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare i32 @llvm.eh.sjlj.setjmp(ptr)
+@buf = global [20 x ptr] zeroinitializer, align 8
+
+define signext i32 @foo() "frame-pointer"="all" {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -240
+; CHECK-NEXT: .cfi_def_cfa_offset 400
+; CHECK-NEXT: lgr %r11, %r15
+; CHECK-NEXT: .cfi_def_cfa_register %r11
+; CHECK-NEXT: std %f8, 232(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f9, 224(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f10, 216(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f11, 208(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f12, 200(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f13, 192(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f14, 184(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f15, 176(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: .cfi_offset %f10, -184
+; CHECK-NEXT: .cfi_offset %f11, -192
+; CHECK-NEXT: .cfi_offset %f12, -200
+; CHECK-NEXT: .cfi_offset %f13, -208
+; CHECK-NEXT: .cfi_offset %f14, -216
+; CHECK-NEXT: .cfi_offset %f15, -224
+; CHECK-NEXT: la %r0, 160(%r11)
+; CHECK-NEXT: lgrl %r1, buf@GOT
+; CHECK-NEXT: stg %r0, 168(%r11)
+; CHECK-NEXT: mvhi 160(%r11), 10
+; CHECK-NEXT: larl %r0, .LBB0_1
+; CHECK-NEXT: stg %r0, 8(%r1)
+; CHECK-NEXT: stg %r11, 0(%r1)
+; CHECK-NEXT: stg %r15, 24(%r1)
+; CHECK-NEXT: .LBB0_1: # Block address taken
+; CHECK-NEXT: # %entry
+; CHECK-NEXT: .LBB0_2: # %entry
+; CHECK-NEXT: lg %r1, 168(%r11)
+; CHECK-NEXT: lgf %r2, 0(%r1)
+; CHECK-NEXT: ld %f8, 232(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f9, 224(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f10, 216(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f11, 208(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f12, 200(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f13, 192(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f14, 184(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f15, 176(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: lmg %r6, %r15, 288(%r11)
+; CHECK-NEXT: br %r14
+entry:
+ %val = alloca ptr, align 8
+ %0 = alloca i8, i64 4, align 8
+ store ptr %0, ptr %val, align 8
+ %1 = load ptr, ptr %val, align 8
+ store volatile i32 10, ptr %1, align 4
+ %2 = call i32 @llvm.eh.sjlj.setjmp(ptr @buf)
+ %3 = load ptr, ptr %val, align 8
+ %4 = load volatile i32, ptr %3, align 4
+ ret i32 %4
+}
+
+define signext i32 @foo1() "backchain" "frame-pointer"="all" {
+; CHECK-LABEL: foo1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: lgr %r1, %r15
+; CHECK-NEXT: aghi %r15, -240
+; CHECK-NEXT: .cfi_def_cfa_offset 400
+; CHECK-NEXT: stg %r1, 0(%r15)
+; CHECK-NEXT: lgr %r11, %r15
+; CHECK-NEXT: .cfi_def_cfa_register %r11
+; CHECK-NEXT: std %f8, 232(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f9, 224(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f10, 216(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f11, 208(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f12, 200(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f13, 192(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f14, 184(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: std %f15, 176(%r11) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: .cfi_offset %f10, -184
+; CHECK-NEXT: .cfi_offset %f11, -192
+; CHECK-NEXT: .cfi_offset %f12, -200
+; CHECK-NEXT: .cfi_offset %f13, -208
+; CHECK-NEXT: .cfi_offset %f14, -216
+; CHECK-NEXT: .cfi_offset %f15, -224
+; CHECK-NEXT: la %r0, 160(%r11)
+; CHECK-NEXT: lgrl %r1, buf@GOT
+; CHECK-NEXT: stg %r0, 168(%r11)
+; CHECK-NEXT: mvhi 160(%r11), 10
+; CHECK-NEXT: larl %r0, .LBB1_1
+; CHECK-NEXT: stg %r0, 8(%r1)
+; CHECK-NEXT: stg %r11, 0(%r1)
+; CHECK-NEXT: stg %r15, 24(%r1)
+; CHECK-NEXT: lg %r0, 0(%r15)
+; CHECK-NEXT: stg %r0, 16(%r1)
+; CHECK-NEXT: .LBB1_1: # Block address taken
+; CHECK-NEXT: # %entry
+; CHECK-NEXT: .LBB1_2: # %entry
+; CHECK-NEXT: lg %r1, 168(%r11)
+; CHECK-NEXT: lgf %r2, 0(%r1)
+; CHECK-NEXT: ld %f8, 232(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f9, 224(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f10, 216(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f11, 208(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f12, 200(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f13, 192(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f14, 184(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f15, 176(%r11) # 8-byte Folded Reload
+; CHECK-NEXT: lmg %r6, %r15, 288(%r11)
+; CHECK-NEXT: br %r14
+entry:
+ %val = alloca ptr, align 8
+ %0 = alloca i8, i64 4, align 8
+ store ptr %0, ptr %val, align 8
+ %1 = load ptr, ptr %val, align 8
+ store volatile i32 10, ptr %1, align 4
+ %2 = call i32 @llvm.eh.sjlj.setjmp(ptr @buf)
+ %3 = load ptr, ptr %val, align 8
+ %4 = load volatile i32, ptr %3, align 4
+ ret i32 %4
+}
+
diff --git a/llvm/test/CodeGen/SystemZ/builtin-setjmp-spills.ll b/llvm/test/CodeGen/SystemZ/builtin-setjmp-spills.ll
new file mode 100644
index 000000000000..65657ec9f182
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/builtin-setjmp-spills.ll
@@ -0,0 +1,254 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Simulate register pressure around setjmp call and check all virtual registers
+; are saved to stack before setjmp call and restored from stack after the call.
+; And these registers are not live across the setjmp call.
+; setjmp storing to jmp_buf.
+; Return address in slot 2.
+; Stack Pointer in slot 4.
+; Clobber %r6-%r15, %f8-%f15.
+
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare i32 @llvm.eh.sjlj.setjmp(ptr)
+
+@t = global i32 0, align 4
+@s = global i32 0, align 4
+@r = global i32 0, align 4
+@q = global i32 0, align 4
+@p = global i32 0, align 4
+@o = global i32 0, align 4
+@n = global i32 0, align 4
+@m = global i32 0, align 4
+@l = global i32 0, align 4
+@k = global i32 0, align 4
+@j = global i32 0, align 4
+@i = global i32 0, align 4
+@h = global i32 0, align 4
+@g = global i32 0, align 4
+@f = global i32 0, align 4
+@e = global i32 0, align 4
+@d = global i32 0, align 4
+@c = global i32 0, align 4
+@b = global i32 0, align 4
+@a = global i32 0, align 4
+@buf = global [10 x ptr] zeroinitializer, align 8
+
+define signext i32 @func() {
+; CHECK-LABEL: func:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -384
+; CHECK-NEXT: .cfi_def_cfa_offset 544
+; CHECK-NEXT: std %f8, 376(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f9, 368(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f10, 360(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f11, 352(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f12, 344(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f13, 336(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f14, 328(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f15, 320(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: .cfi_offset %f10, -184
+; CHECK-NEXT: .cfi_offset %f11, -192
+; CHECK-NEXT: .cfi_offset %f12, -200
+; CHECK-NEXT: .cfi_offset %f13, -208
+; CHECK-NEXT: .cfi_offset %f14, -216
+; CHECK-NEXT: .cfi_offset %f15, -224
+; CHECK-NEXT: lgrl %r1, t@GOT
+; CHECK-NEXT: lgrl %r2, s@GOT
+; CHECK-NEXT: stg %r1, 312(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r1), 1
+; CHECK-NEXT: lgrl %r1, r@GOT
+; CHECK-NEXT: lgrl %r3, q@GOT
+; CHECK-NEXT: stg %r2, 304(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r2), 1
+; CHECK-NEXT: lgrl %r2, p@GOT
+; CHECK-NEXT: stg %r1, 296(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r1), 1
+; CHECK-NEXT: stg %r3, 288(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r3), 1
+; CHECK-NEXT: lgrl %r1, o@GOT
+; CHECK-NEXT: stg %r2, 280(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r2), 1
+; CHECK-NEXT: lgrl %r2, n@GOT
+; CHECK-NEXT: lgrl %r3, m@GOT
+; CHECK-NEXT: stg %r1, 272(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r1), 1
+; CHECK-NEXT: lgrl %r1, l@GOT
+; CHECK-NEXT: stg %r2, 264(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r2), 1
+; CHECK-NEXT: stg %r3, 256(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r3), 1
+; CHECK-NEXT: lgrl %r2, k@GOT
+; CHECK-NEXT: stg %r1, 248(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r1), 1
+; CHECK-NEXT: lgrl %r1, j@GOT
+; CHECK-NEXT: lgrl %r3, i@GOT
+; CHECK-NEXT: stg %r2, 240(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r2), 1
+; CHECK-NEXT: lgrl %r2, h@GOT
+; CHECK-NEXT: stg %r1, 232(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r1), 1
+; CHECK-NEXT: stg %r3, 224(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r3), 1
+; CHECK-NEXT: lgrl %r1, g@GOT
+; CHECK-NEXT: stg %r2, 216(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r2), 1
+; CHECK-NEXT: lgrl %r2, f@GOT
+; CHECK-NEXT: lgrl %r3, e@GOT
+; CHECK-NEXT: stg %r1, 208(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r1), 1
+; CHECK-NEXT: lgrl %r1, d@GOT
+; CHECK-NEXT: stg %r2, 200(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r2), 1
+; CHECK-NEXT: stg %r3, 192(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r3), 1
+; CHECK-NEXT: lgrl %r2, c@GOT
+; CHECK-NEXT: stg %r1, 184(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r1), 1
+; CHECK-NEXT: lgrl %r3, b@GOT
+; CHECK-NEXT: lgrl %r4, a@GOT
+; CHECK-NEXT: stg %r2, 176(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r2), 1
+; CHECK-NEXT: lgrl %r1, buf@GOT
+; CHECK-NEXT: stg %r3, 168(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r3), 1
+; CHECK-NEXT: stg %r4, 160(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: mvhi 0(%r4), 1
+; CHECK-NEXT: larl %r0, .LBB0_2
+; CHECK-NEXT: stg %r0, 8(%r1)
+; CHECK-NEXT: stg %r15, 24(%r1)
+; CHECK-NEXT: .LBB0_1: # %entry
+; CHECK-NEXT: lhi %r0, 0
+; CHECK-NEXT: j .LBB0_3
+; CHECK-NEXT: .LBB0_2: # Block address taken
+; CHECK-NEXT: # %entry
+; CHECK-NEXT: lhi %r0, 1
+; CHECK-NEXT: .LBB0_3: # %entry
+; CHECK-NEXT: lg %r1, 160(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 168(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 176(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 184(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 192(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 200(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 208(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 216(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 224(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 232(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 240(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 248(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 256(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 264(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 272(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 280(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 288(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 296(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 304(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lg %r1, 312(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: a %r0, 0(%r1)
+; CHECK-NEXT: lgfr %r2, %r0
+; CHECK-NEXT: ld %f8, 376(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f9, 368(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f10, 360(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f11, 352(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f12, 344(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f13, 336(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f14, 328(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f15, 320(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: lmg %r6, %r15, 432(%r15)
+; CHECK-NEXT: br %r14
+entry:
+ store i32 1, ptr @t, align 4
+ store i32 1, ptr @s, align 4
+ store i32 1, ptr @r, align 4
+ store i32 1, ptr @q, align 4
+ store i32 1, ptr @p, align 4
+ store i32 1, ptr @o, align 4
+ store i32 1, ptr @n, align 4
+ store i32 1, ptr @m, align 4
+ store i32 1, ptr @l, align 4
+ store i32 1, ptr @k, align 4
+ store i32 1, ptr @j, align 4
+ store i32 1, ptr @i, align 4
+ store i32 1, ptr @h, align 4
+ store i32 1, ptr @g, align 4
+ store i32 1, ptr @f, align 4
+ store i32 1, ptr @e, align 4
+ store i32 1, ptr @d, align 4
+ store i32 1, ptr @c, align 4
+ store i32 1, ptr @b, align 4
+ store i32 1, ptr @a, align 4
+ %0 = tail call i32 @llvm.eh.sjlj.setjmp(ptr nonnull @buf)
+ %1 = load i32, ptr @a, align 4
+ %2 = load i32, ptr @b, align 4
+ %3 = load i32, ptr @c, align 4
+ %4 = load i32, ptr @d, align 4
+ %5 = load i32, ptr @e, align 4
+ %6 = load i32, ptr @f, align 4
+ %7 = load i32, ptr @g, align 4
+ %8 = load i32, ptr @h, align 4
+ %9 = load i32, ptr @i, align 4
+ %10 = load i32, ptr @j, align 4
+ %11 = load i32, ptr @k, align 4
+ %12 = load i32, ptr @l, align 4
+ %13 = load i32, ptr @m, align 4
+ %14 = load i32, ptr @n, align 4
+ %15 = load i32, ptr @o, align 4
+ %16 = load i32, ptr @p, align 4
+ %17 = load i32, ptr @q, align 4
+ %18 = load i32, ptr @r, align 4
+ %19 = load i32, ptr @s, align 4
+ %20 = load i32, ptr @t, align 4
+ %add = add i32 %1, %0
+ %add1 = add i32 %add, %2
+ %add2 = add i32 %add1, %3
+ %add3 = add i32 %add2, %4
+ %add4 = add i32 %add3, %5
+ %add5 = add i32 %add4, %6
+ %add6 = add i32 %add5, %7
+ %add7 = add i32 %add6, %8
+ %add8 = add i32 %add7, %9
+ %add9 = add i32 %add8, %10
+ %add10 = add i32 %add9, %11
+ %add11 = add i32 %add10, %12
+ %add12 = add i32 %add11, %13
+ %add13 = add i32 %add12, %14
+ %add14 = add i32 %add13, %15
+ %add15 = add i32 %add14, %16
+ %add16 = add i32 %add15, %17
+ %add17 = add i32 %add16, %18
+ %add18 = add i32 %add17, %19
+ %add19 = add i32 %add18, %20
+ ret i32 %add19
+}
+
diff --git a/llvm/test/CodeGen/SystemZ/builtin-setjmp.ll b/llvm/test/CodeGen/SystemZ/builtin-setjmp.ll
new file mode 100644
index 000000000000..cfeba5a051ad
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/builtin-setjmp.ll
@@ -0,0 +1,124 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; Test setjmp store jmp_buf
+; Return address in slot 2.
+; Backchain value is stored in slot 3 for -mbackchain option.
+; Stack Pointer in slot 4.
+; Clobber %r6-%r15, %f8-%f15.
+
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare i32 @llvm.eh.sjlj.setjmp(ptr)
+@buf = global [20 x ptr] zeroinitializer, align 8
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: aghi %r15, -64
+; CHECK-NEXT: .cfi_def_cfa_offset 224
+; CHECK-NEXT: std %f8, 56(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f9, 48(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f10, 40(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f11, 32(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f12, 24(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f13, 16(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f14, 8(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f15, 0(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: .cfi_offset %f10, -184
+; CHECK-NEXT: .cfi_offset %f11, -192
+; CHECK-NEXT: .cfi_offset %f12, -200
+; CHECK-NEXT: .cfi_offset %f13, -208
+; CHECK-NEXT: .cfi_offset %f14, -216
+; CHECK-NEXT: .cfi_offset %f15, -224
+; CHECK-NEXT: lgrl %r1, buf@GOT
+; CHECK-NEXT: larl %r0, .LBB0_1
+; CHECK-NEXT: stg %r0, 8(%r1)
+; CHECK-NEXT: stg %r15, 24(%r1)
+; CHECK-NEXT: .LBB0_1: # Block address taken
+; CHECK-NEXT: # %entry
+; CHECK-NEXT: .LBB0_2: # %entry
+; CHECK-NEXT: ld %f8, 56(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f9, 48(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f10, 40(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f11, 32(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f12, 24(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f13, 16(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f14, 8(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f15, 0(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: lmg %r6, %r15, 112(%r15)
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 @llvm.eh.sjlj.setjmp(ptr nonnull @buf)
+ ret void
+}
+
+define void @foo1() "backchain" {
+; CHECK-LABEL: foo1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
+; CHECK-NEXT: .cfi_offset %r6, -112
+; CHECK-NEXT: .cfi_offset %r7, -104
+; CHECK-NEXT: .cfi_offset %r8, -96
+; CHECK-NEXT: .cfi_offset %r9, -88
+; CHECK-NEXT: .cfi_offset %r10, -80
+; CHECK-NEXT: .cfi_offset %r11, -72
+; CHECK-NEXT: .cfi_offset %r12, -64
+; CHECK-NEXT: .cfi_offset %r13, -56
+; CHECK-NEXT: .cfi_offset %r14, -48
+; CHECK-NEXT: .cfi_offset %r15, -40
+; CHECK-NEXT: lgr %r1, %r15
+; CHECK-NEXT: aghi %r15, -64
+; CHECK-NEXT: .cfi_def_cfa_offset 224
+; CHECK-NEXT: stg %r1, 0(%r15)
+; CHECK-NEXT: std %f8, 56(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f9, 48(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f10, 40(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f11, 32(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f12, 24(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f13, 16(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f14, 8(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: std %f15, 0(%r15) # 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset %f8, -168
+; CHECK-NEXT: .cfi_offset %f9, -176
+; CHECK-NEXT: .cfi_offset %f10, -184
+; CHECK-NEXT: .cfi_offset %f11, -192
+; CHECK-NEXT: .cfi_offset %f12, -200
+; CHECK-NEXT: .cfi_offset %f13, -208
+; CHECK-NEXT: .cfi_offset %f14, -216
+; CHECK-NEXT: .cfi_offset %f15, -224
+; CHECK-NEXT: lgrl %r1, buf@GOT
+; CHECK-NEXT: larl %r0, .LBB1_1
+; CHECK-NEXT: stg %r0, 8(%r1)
+; CHECK-NEXT: stg %r15, 24(%r1)
+; CHECK-NEXT: lg %r0, 0(%r15)
+; CHECK-NEXT: stg %r0, 16(%r1)
+; CHECK-NEXT: .LBB1_1: # Block address taken
+; CHECK-NEXT: # %entry
+; CHECK-NEXT: .LBB1_2: # %entry
+; CHECK-NEXT: ld %f8, 56(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f9, 48(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f10, 40(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f11, 32(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f12, 24(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f13, 16(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f14, 8(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: ld %f15, 0(%r15) # 8-byte Folded Reload
+; CHECK-NEXT: lmg %r6, %r15, 112(%r15)
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 @llvm.eh.sjlj.setjmp(ptr nonnull @buf)
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
index f7b58f04fd7b..e3207df79944 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
@@ -29,13 +29,12 @@ tracksRegLiveness: true
body: |
bb.0:
- ; CHECK-LABEL
; CHECK-LABEL: name: main
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 25
- ; CHECK: CHIMux [[LGHI]].subreg_l32, 0, implicit-def $cc
- ; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 25
- ; CHECK: undef [[LGHI1]].subreg_l32:gr64bit = MSFI [[LGHI1]].subreg_l32, -117440512
- ; CHECK: Return implicit [[LGHI1]].subreg_l32
+ ; CHECK-NEXT: CHIMux [[LGHI]].subreg_l32, 0, implicit-def $cc
+ ; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 25
+ ; CHECK-NEXT: undef [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = MSFI [[LGHI1]].subreg_l32, -117440512
+ ; CHECK-NEXT: Return implicit [[LGHI1]].subreg_l32
%0:gr64bit = LGHI 25
%1:gr32bit = COPY %0.subreg_l32
%1:gr32bit = MSFI %1, -117440512
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
index bf5855010bf9..c805d31aa11c 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
@@ -25,12 +25,12 @@ body: |
; CHECK-LABEL: name: main
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43
- ; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
- ; CHECK: [[LGHI1]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
- ; CHECK: [[LGHI1]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
- ; CHECK: undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
- ; CHECK: [[DLGR:%[0-9]+]]:gr128bit = DLGR [[DLGR]], [[LGHI]]
- ; CHECK: Return implicit [[DLGR]]
+ ; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
+ ; CHECK-NEXT: undef [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
+ ; CHECK-NEXT: [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
+ ; CHECK-NEXT: undef [[LGFI:%[0-9]+]].subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
+ ; CHECK-NEXT: [[LGFI:%[0-9]+]]:gr128bit = DLGR [[LGFI]], [[LGHI]]
+ ; CHECK-NEXT: Return implicit [[LGFI]]
%0:gr64bit = LGHI 43
%1:gr32bit = COPY %0.subreg_l32
%1:gr32bit = MSR %1, %1
@@ -55,20 +55,23 @@ liveins: []
body: |
; CHECK-LABEL: name: segfault
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0
- ; CHECK: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
- ; CHECK: $r2d = LGHI 123
- ; CHECK: $r3d = LGHI 0
- ; CHECK: $r4d = LGHI 0
- ; CHECK: $r5d = COPY [[LGFR]]
- ; CHECK: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
- ; CHECK: ADJCALLSTACKUP 0, 0
- ; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
- ; CHECK: J %bb.1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0
+ ; CHECK-NEXT: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
+ ; CHECK-NEXT: $r2d = LGHI 123
+ ; CHECK-NEXT: $r3d = LGHI 0
+ ; CHECK-NEXT: $r4d = LGHI 0
+ ; CHECK-NEXT: $r5d = COPY [[LGFR]]
+ ; CHECK-NEXT: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
+ ; CHECK-NEXT: J %bb.1
bb.0:
successors: %bb.1(0x80000000)
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
index b1a0a309e1e2..cd8f14b28844 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
@@ -15,56 +15,70 @@
# only partial defined before being fully copied.
#
# PR40215.
+
+
+# The coalescer should have been able to swap the operands of
+# the OR, hence eliminating the copy of %20 and %18.
+# This is also visible here because the ROSBG operand was LHS
+# before the coalescer, now it is RHS.
---
name: main
alignment: 16
tracksRegLiveness: true
-machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: main
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI -30
- ; CHECK: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
- ; CHECK: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
- ; CHECK: undef %20.subreg_l32:gr64bit = IMPLICIT_DEF
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
- ; CHECK: CHIMux [[LHIMux]], 0, implicit-def $cc
- ; CHECK: BRC 14, 6, %bb.3, implicit killed $cc
- ; CHECK: J %bb.4
- ; CHECK: bb.2:
- ; CHECK: successors:
- ; CHECK: STMux %20.subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
- ; CHECK: bb.3:
- ; CHECK: successors:
- ; CHECK: bb.4:
- ; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000)
- ; CHECK: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg
- ; CHECK: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg
- ; CHECK: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg
- ; CHECK: [[OGR:%[0-9]+]]:gr64bit = OGR [[OGR]], [[LAY]], implicit-def dead $cc
- ; CHECK: undef %19.subreg_l32:gr64bit = AHIMuxK [[LGHI]].subreg_l32, 19843, implicit-def dead $cc
- ; CHECK: [[ROSBG:%[0-9]+]]:gr64bit = ROSBG [[ROSBG]], [[OGR]], 32, 63, 0, implicit-def dead $cc
- ; The coalescer should have been able to swap the operands of
- ; the OR, hence eliminating the copy of %20 and %18.
- ; This is also visible here because the ROSBG operand was LHS
- ; before the coalescer, now it is RHS.
- ; CHECK: %20.subreg_l32:gr64bit = OR %20.subreg_l32, [[ROSBG]].subreg_l32, implicit-def dead $cc
- ; CHECK: [[ROSBG1:%[0-9]+]]:gr64bit = ROSBG [[ROSBG1]], [[LAY1]], 32, 63, 0, implicit-def dead $cc
- ; CHECK: CHIMux [[LHIMux1]], 0, implicit-def $cc
- ; CHECK: BRC 14, 6, %bb.6, implicit killed $cc
- ; CHECK: J %bb.5
- ; CHECK: bb.5:
- ; CHECK: successors: %bb.6(0x80000000)
- ; CHECK: bb.6:
- ; CHECK: successors: %bb.2(0x00000001), %bb.7(0x7fffffff)
- ; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 6, $noreg
- ; CHECK: CGHI [[LGHI]], 0, implicit-def $cc
- ; CHECK: BRC 14, 8, %bb.2, implicit killed $cc
- ; CHECK: bb.7:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: J %bb.1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = LGHI -30
+ ; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
+ ; CHECK-NEXT: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
+ ; CHECK-NEXT: undef [[DEF:%[0-9]+]].subreg_l32:gr64bit = IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: CHIMux [[LHIMux]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.3, implicit killed $cc
+ ; CHECK-NEXT: J %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STMux [[DEF]].subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.5(0x30000000), %bb.6(0x50000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg
+ ; CHECK-NEXT: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg
+ ; CHECK-NEXT: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg
+ ; CHECK-NEXT: [[LAY2:%[0-9]+]]:gr64bit = OGR [[LAY2]], [[LAY]], implicit-def dead $cc
+ ; CHECK-NEXT: undef [[AHIMuxK:%[0-9]+]].subreg_l32:gr64bit = AHIMuxK [[LGHI]].subreg_l32, 19843, implicit-def dead $cc
+ ; CHECK-NEXT: [[AHIMuxK:%[0-9]+]]:gr64bit = ROSBG [[AHIMuxK]], [[LAY2]], 32, 63, 0, implicit-def dead $cc
+ ; CHECK-NEXT: [[DEF:%[0-9]+]].subreg_l32:gr64bit = OR [[DEF]].subreg_l32, [[AHIMuxK]].subreg_l32, implicit-def dead $cc
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64bit = ROSBG [[DEF]], [[LAY1]], 32, 63, 0, implicit-def dead $cc
+ ; CHECK-NEXT: CHIMux [[LHIMux1]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.6, implicit killed $cc
+ ; CHECK-NEXT: J %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6:
+ ; CHECK-NEXT: successors: %bb.2(0x00000001), %bb.7(0x7fffffff)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = nuw nsw LA [[LGHI]], 6, $noreg
+ ; CHECK-NEXT: CGHI [[LGHI]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 8, %bb.2, implicit killed $cc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J %bb.1
bb.0:
%6:gr64bit = LGHI -30
%8:grx32bit = LHIMux 1
diff --git a/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir b/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
index eb1fd4e9c148..3ee857b7b1b1 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
@@ -1,55 +1,38 @@
-# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -start-before=livevars %s -o /dev/null 2>&1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=livevars -stop-after=register-coalescer %s -o - | FileCheck %s
# Test that coalesing of an empty live range (undef) does not cause failure.
---- |
- define dso_local void @fun(ptr %src, ptr %dst) #0 {
- %1 = sdiv i64 poison, poison
- %2 = load i32, ptr %src, align 4
- br i1 poison, label %6, label %3
-
- 3: ; preds = %0
- %4 = trunc i64 %1 to i32
- %5 = udiv i32 %4, %2
- br label %6
-
- 6: ; preds = %3, %0
- %7 = phi i32 [ %5, %3 ], [ 1, %0 ]
- store i32 %7, ptr %dst, align 4
- ret void
- }
-
-...
---
name: fun
-alignment: 16
tracksRegLiveness: true
-registers:
- - { id: 0, class: gr64bit }
- - { id: 1, class: gr32bit }
- - { id: 2, class: grx32bit }
- - { id: 3, class: grx32bit }
- - { id: 4, class: addr64bit }
- - { id: 5, class: addr64bit }
- - { id: 6, class: grx32bit }
- - { id: 7, class: grx32bit }
- - { id: 8, class: grx32bit }
- - { id: 9, class: gr64bit }
- - { id: 10, class: gr64bit }
- - { id: 11, class: gr128bit }
- - { id: 12, class: gr128bit }
- - { id: 13, class: gr128bit }
- - { id: 14, class: gr128bit }
- - { id: 15, class: gr64bit }
-liveins:
- - { reg: '$r2d', virtual-reg: '%4' }
- - { reg: '$r3d', virtual-reg: '%5' }
-frameInfo:
- maxAlignment: 1
-machineFunctionInfo: {}
body: |
- bb.0 (%ir-block.0):
+ ; CHECK-LABEL: name: fun
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $r2d, $r3d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:addr64bit = COPY $r3d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY $r2d
+ ; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
+ ; CHECK-NEXT: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
+ ; CHECK-NEXT: CHIMux [[LHIMux1]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.2, implicit killed $cc
+ ; CHECK-NEXT: J %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LMux:%[0-9]+]]:gr32bit = LMux [[COPY1]], 0, $noreg :: (load (s32))
+ ; CHECK-NEXT: undef [[LLILL:%[0-9]+]].subreg_h64:gr128bit = LLILL 0
+ ; CHECK-NEXT: [[LLILL:%[0-9]+]]:gr128bit = DLR [[LLILL]], [[LMux]]
+ ; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = COPY [[LLILL]].subreg_ll32
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: STMux [[LHIMux]], [[COPY]], 0, $noreg :: (store (s32))
+ ; CHECK-NEXT: Return
+ bb.0:
liveins: $r2d, $r3d
-
+
%5:addr64bit = COPY $r3d
%4:addr64bit = COPY $r2d
%6:grx32bit = LHIMux 1
@@ -57,18 +40,20 @@ body: |
CHIMux killed %7, 0, implicit-def $cc
BRC 14, 6, %bb.2, implicit $cc
J %bb.1
-
- bb.1 (%ir-block.3):
- %1:gr32bit = LMux %4, 0, $noreg :: (load (s32) from %ir.src)
+
+ bb.1:
+ %1:gr32bit = LMux %4, 0, $noreg :: (load (s32))
%15:gr64bit = LLILL 0
%14:gr128bit = INSERT_SUBREG undef %13:gr128bit, %15, %subreg.subreg_h64
%11:gr128bit = INSERT_SUBREG %14, undef %9:gr64bit, %subreg.subreg_l64
%12:gr128bit = DLR %11, %1
%2:grx32bit = COPY %12.subreg_ll32
-
- bb.2 (%ir-block.6):
+
+ bb.2:
%3:grx32bit = PHI %6, %bb.0, %2, %bb.1
- STMux %3, %5, 0, $noreg :: (store (s32) into %ir.dst)
+ STMux %3, %5, 0, $noreg :: (store (s32))
Return
...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/SystemZ/stackmap-args.ll b/llvm/test/CodeGen/SystemZ/stackmap-args.ll
new file mode 100644
index 000000000000..4c52a33c1e64
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/stackmap-args.ll
@@ -0,0 +1,22 @@
+; RUN: not llc -mtriple=s390x-linux-gnu < %s 2>&1 | FileCheck %s
+; Tests error when we pass non-immediate parameters to @llvm.experiment.stackmap
+
+define void @first_arg() {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+ ; First operand should be immediate
+ %id = add i64 0, 0
+ call void (i64, i32, ...) @llvm.experimental.stackmap(i64 %id, i32 0)
+ ret void
+}
+
+define void @second_arg() {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+ ; Second operand should be immediate
+ %numShadowByte = add i32 0, 0
+ call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 %numShadowByte)
+ ret void
+}
+
+declare void @llvm.experimental.stackmap(i64, i32, ...)
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-27 06:08:27 +0000