diff options
Diffstat (limited to 'llvm/test/CodeGen/SPIRV')
52 files changed, 562 insertions, 109 deletions
diff --git a/llvm/test/CodeGen/SPIRV/branching/if-merging.ll b/llvm/test/CodeGen/SPIRV/branching/if-merging.ll index eb8ca515c582..18fbe417addf 100644 --- a/llvm/test/CodeGen/SPIRV/branching/if-merging.ll +++ b/llvm/test/CodeGen/SPIRV/branching/if-merging.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ;; NOTE: This does not check for structured control-flow operations. diff --git a/llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll b/llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll index f978c44888e0..b664a65a5829 100644 --- a/llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll +++ b/llvm/test/CodeGen/SPIRV/branching/if-non-merging.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; CHECK-DAG: [[I32:%.+]] = OpTypeInt 32 ; CHECK-DAG: [[BOOL:%.+]] = OpTypeBool diff --git a/llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll b/llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll index 9981e0d86eaa..25c2c8627de4 100644 --- a/llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll +++ b/llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpFunction diff --git a/llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll b/llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll index 06ab469e7007..432fbe0a2297 100644 --- a/llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll +++ b/llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + define i4 @getConstantI4() { ret i4 2 ; i4 => OpTypeInt 8 } diff --git a/llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll b/llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll index 090fe1578a36..6073b0c2b927 100644 --- a/llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll +++ b/llvm/test/CodeGen/SPIRV/debug-info/debug-type-basic.ll @@ -1,6 +1,3 @@ -; Issue #118011 -; XFAIL: * - ; RUN: llc --verify-machineinstrs --spv-emit-nonsemantic-debug-info --spirv-ext=+SPV_KHR_non_semantic_info --print-after=spirv-nonsemantic-debug-info -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-MIR ; RUN: llc --verify-machineinstrs --spv-emit-nonsemantic-debug-info --spirv-ext=+SPV_KHR_non_semantic_info -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: llc --verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_non_semantic_info %s -o - | FileCheck %s --check-prefix=CHECK-OPTION @@ -14,33 +11,33 @@ ; CHECK-MIR-DAG: [[str_bool:%[0-9]+\:id\(s32\)]] = OpString 1819242338, 0 ; CHECK-MIR-DAG: [[size_8bits:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 8 ; CHECK-MIR-DAG: [[encoding_boolean:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 2 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_bool]], [[size_8bits]], [[encoding_boolean]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_bool]], [[size_8bits]], [[encoding_boolean]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_int:%[0-9]+\:id\(s32\)]] = OpString 7630441 ; CHECK-MIR-DAG: [[size_32bits:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 32 ; CHECK-MIR-DAG: [[encoding_signed:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 4 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_int]], [[size_32bits]], [[encoding_signed]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_int]], [[size_32bits]], [[encoding_signed]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_short:%[0-9]+\:id\(s32\)]] = OpString 1919903859, 116 ; CHECK-MIR-DAG: [[size_16bits:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 16 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_short]], [[size_16bits]], [[encoding_signed]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_short]], [[size_16bits]], [[encoding_signed]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_char:%[0-9]+\:id\(s32\)]] = OpString 1918986339, 0 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_char]], [[size_8bits]], [[encoding_signedchar]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_char]], [[size_8bits]], [[encoding_signedchar]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_long:%[0-9]+\:id\(s32\)]] = OpString 1735290732, 0 ; CHECK-MIR-DAG: [[size_64bits:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 64 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_long]], [[size_64bits]], [[encoding_signed]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_long]], [[size_64bits]], [[encoding_signed]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_uint:%[0-9]+\:id\(s32\)]] = OpString 1769172597, 1684368999, 1953392928, 0 ; CHECK-MIR-DAG: [[encoding_unsigned:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 6 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_uint]], [[size_32bits]], [[encoding_unsigned]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_uint]], [[size_32bits]], [[encoding_unsigned]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_ushort:%[0-9]+\:id\(s32\)]] = OpString 1769172597, 1684368999, 1869116192, 29810 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_ushort]], [[size_16bits]], [[encoding_unsigned]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_ushort]], [[size_16bits]], [[encoding_unsigned]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_uchar:%[0-9]+\:id\(s32\)]] = OpString 1769172597, 1684368999, 1634231072, 114 ; CHECK-MIR-DAG: [[encoding_unsignedchar:%[0-9]+\:iid\(s32\)]] = OpConstantI [[type_i32]], 7 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_uchar]], [[size_8bits]], [[encoding_unsignedchar]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_uchar]], [[size_8bits]], [[encoding_unsignedchar]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_ulong:%[0-9]+\:id\(s32\)]] = OpString 1769172597, 1684368999, 1852795936, 103 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_ulong]], [[size_64bits]], [[encoding_unsigned]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_ulong]], [[size_64bits]], [[encoding_unsigned]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_float:%[0-9]+\:id\(s32\)]] = OpString 1634692198, 116 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_float]], [[size_32bits]], [[encoding_float]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_float]], [[size_32bits]], [[encoding_float]], [[flag_zero]] ; CHECK-MIR-DAG: [[str_double:%[0-9]+\:id\(s32\)]] = OpString 1651863396, 25964 -; CHECK-MIR: OpExtInst [[type_void]], 3, 2, [[str_double]], [[size_64bits]], [[encoding_float]], [[flag_zero]] +; CHECK-MIR-DAG: OpExtInst [[type_void]], 3, 2, [[str_double]], [[size_64bits]], [[encoding_float]], [[flag_zero]] ; CHECK-SPIRV: [[ext_inst_non_semantic:%[0-9]+]] = OpExtInstImport "NonSemantic.Shader.DebugInfo.100" ; CHECK-SPIRV-DAG: [[str_bool:%[0-9]+]] = OpString "bool" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll new file mode 100644 index 000000000000..dca777a150a5 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_empty.ll @@ -0,0 +1,18 @@ +; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_float_controls2 + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_float_controls,+SPV_INTEL_float_controls2 %s -o - | FileCheck %s +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_float_controls,+SPV_INTEL_float_controls2 %s -o - -filetype=obj | spirv-val %} + +; CHECK-NOT: {{ExecutionMode.*(DenormPreserve|DenormFlushToZero|SignedZeroInfNanPreserve|RoundingModeRTE|RoundingModeRTZ|RoundingModeRTPINTEL|RoundingModeRTNINTEL|FloatingPointModeALTINTEL|FloatingPointModeIEEEINTEL)}} +define dso_local dllexport spir_kernel void @k_no_fc(i32 %ibuf, i32 %obuf) local_unnamed_addr #16 { +entry: + ret void +} + +attributes #16 = { noinline norecurse nounwind readnone "VCMain" "VCFunction" "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 8.0.1"} diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll new file mode 100644 index 000000000000..5de154053da8 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_float_controls2/exec_mode_float_control_intel.ll @@ -0,0 +1,74 @@ +; Adapted from https://github.com/KhronosGroup/SPIRV-LLVM-Translator/tree/main/test/extensions/INTEL/SPV_INTEL_float_controls2 + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_float_controls2 %s -o - | FileCheck %s +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_float_controls2 %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: Capability RoundToInfinityINTEL +; CHECK-DAG: Capability FloatingPointModeINTEL +; CHECK: Extension "SPV_INTEL_float_controls2" + +define dso_local dllexport spir_kernel void @k_float_controls_0(i32 %ibuf, i32 %obuf) { +entry: + ret void +} + +define dso_local dllexport spir_kernel void @k_float_controls_1(i32 %ibuf, i32 %obuf) { +entry: + ret void +} + +define dso_local dllexport spir_kernel void @k_float_controls_2(i32 %ibuf, i32 %obuf) { +entry: + ret void +} + +define dso_local dllexport spir_kernel void @k_float_controls_3(i32 %ibuf, i32 %obuf) { +entry: + ret void +} + +!llvm.module.flags = !{!12} +!llvm.ident = !{!13} +!spirv.EntryPoint = !{} +!spirv.ExecutionMode = !{!15, !16, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26} + +; CHECK-DAG: OpEntryPoint Kernel %[[#KERNEL0:]] "k_float_controls_0" +; CHECK-DAG: OpEntryPoint Kernel %[[#KERNEL1:]] "k_float_controls_1" +; CHECK-DAG: OpEntryPoint Kernel %[[#KERNEL2:]] "k_float_controls_2" +; CHECK-DAG: OpEntryPoint Kernel %[[#KERNEL3:]] "k_float_controls_3" +!0 = !{ptr @k_float_controls_0, !"k_float_controls_0", !1, i32 0, !2, !3, !4, i32 0, i32 0} +!1 = !{i32 2, i32 2} +!2 = !{i32 32, i32 36} +!3 = !{i32 0, i32 0} +!4 = !{!"", !""} +!12 = !{i32 1, !"wchar_size", i32 4} +!13 = !{!"clang version 8.0.1"} +!14 = !{i32 1, i32 0} + +; CHECK-DAG: OpExecutionMode %[[#KERNEL0]] RoundingModeRTPINTEL 64 +!15 = !{ptr @k_float_controls_0, i32 5620, i32 64} +; CHECK-DAG: OpExecutionMode %[[#KERNEL0]] RoundingModeRTPINTEL 32 +!16 = !{ptr @k_float_controls_0, i32 5620, i32 32} +; CHECK-DAG: OpExecutionMode %[[#KERNEL0]] RoundingModeRTPINTEL 16 +!17 = !{ptr @k_float_controls_0, i32 5620, i32 16} + +; CHECK-DAG: OpExecutionMode %[[#KERNEL1]] RoundingModeRTNINTEL 64 +!18 = !{ptr @k_float_controls_1, i32 5621, i32 64} +; CHECK-DAG: OpExecutionMode %[[#KERNEL1]] RoundingModeRTNINTEL 32 +!19 = !{ptr @k_float_controls_1, i32 5621, i32 32} +; CHECK-DAG: OpExecutionMode %[[#KERNEL1]] RoundingModeRTNINTEL 16 +!20 = !{ptr @k_float_controls_1, i32 5621, i32 16} + +; CHECK-DAG: OpExecutionMode %[[#KERNEL2]] FloatingPointModeALTINTEL 64 +!21 = !{ptr @k_float_controls_2, i32 5622, i32 64} +; CHECK-DAG: OpExecutionMode %[[#KERNEL2]] FloatingPointModeALTINTEL 32 +!22 = !{ptr @k_float_controls_2, i32 5622, i32 32} +; CHECK-DAG: OpExecutionMode %[[#KERNEL2]] FloatingPointModeALTINTEL 16 +!23 = !{ptr @k_float_controls_2, i32 5622, i32 16} + +; CHECK-DAG: OpExecutionMode %[[#KERNEL3]] FloatingPointModeIEEEINTEL 64 +!24 = !{ptr @k_float_controls_3, i32 5623, i32 64} +; CHECK-DAG: OpExecutionMode %[[#KERNEL3]] FloatingPointModeIEEEINTEL 32 +!25 = !{ptr @k_float_controls_3, i32 5623, i32 32} +; CHECK-DAG: OpExecutionMode %[[#KERNEL3]] FloatingPointModeIEEEINTEL 16 +!26 = !{ptr @k_float_controls_3, i32 5623, i32 16} diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll index d5a8fb3e7baa..368c5d4a3298 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll @@ -1,6 +1,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-DAG: OpName %[[I9:.*]] "_ZN13BaseIncrement9incrementEPi" ; CHECK-DAG: OpName %[[I29:.*]] "_ZN12IncrementBy29incrementEPi" ; CHECK-DAG: OpName %[[I49:.*]] "_ZN12IncrementBy49incrementEPi" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll index 6aeb29df9f7b..75ad382f05ff 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll @@ -1,6 +1,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-DAG: OpCapability FunctionPointersINTEL ; CHECK-DAG: OpCapability Int64 ; CHECK: OpExtension "SPV_INTEL_function_pointers" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll index b238b07bbc04..d38de216c223 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll @@ -5,6 +5,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - --spirv-ext=+SPV_INTEL_function_pointers | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; Running with -verify-machineinstrs would lead to "Reading virtual register without a def" ; error, because OpConstantFunctionPointerINTEL forward-refers to a function definition. diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll index 13667f44389e..457b3a14fd8f 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_sub_groups.ll @@ -77,9 +77,6 @@ ; CHECK-SPIRV-LABEL: Return -target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" -target triple = "spir64" - %opencl.image2d_ro_t = type opaque %opencl.image2d_wo_t = type opaque diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_subgroup_local_block_io.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_subgroup_local_block_io.ll new file mode 100644 index 000000000000..8274c917bbe2 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_subgroups/cl_intel_subgroup_local_block_io.ll @@ -0,0 +1,156 @@ +; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_subgroups/cl_intel_sub_groups.ll + +;Source: +;void __kernel test(float2 x, uint c, +; read_only image2d_t image_in, +; write_only image2d_t image_out, +; int2 coord, +; __local uint* p, +; __local ushort* sp, +; __local uchar* cp, +; __local ulong* lp) { +; +; uint2 ui2 = intel_sub_group_block_read2(image_in, coord); +; intel_sub_group_block_write2(image_out, coord, ui2); +; ui2 = intel_sub_group_block_read2(p); +; intel_sub_group_block_write2(p, ui2); +; +; ushort2 us2 = intel_sub_group_block_read_us2(image_in, coord); +; intel_sub_group_block_write_us2(image_out, coord, us2); +; us2 = intel_sub_group_block_read_us2(sp); +; intel_sub_group_block_write_us2(sp, us2); +; +; uchar2 uc2 = intel_sub_group_block_read_uc2(image_in, coord); +; intel_sub_group_block_write_uc2(image_out, coord, uc2); +; uc2 = intel_sub_group_block_read_uc2(cp); +; intel_sub_group_block_write_uc2(cp, uc2); +; +; ulong2 ul2 = intel_sub_group_block_read_ul2(image_in, coord); +; intel_sub_group_block_write_ul2(image_out, coord, ul2); +; ul2 = intel_sub_group_block_read_ul2(lp); +; intel_sub_group_block_write_ul2(lp, ul2); +;} + +; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_subgroups %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_subgroups %s -o - -filetype=obj | spirv-val %} + +; CHECK-ERROR: LLVM ERROR: intel_sub_group_block_read2: the builtin requires the following SPIR-V extension: SPV_INTEL_subgroups + +; CHECK-DAG: Capability SubgroupBufferBlockIOINTEL +; CHECK-DAG: Capability SubgroupImageBlockIOINTEL +; CHECK: Extension "SPV_INTEL_subgroups" + +; CHECK-SPIRV-LABEL: Function +; CHECK-SPIRV-LABEL: Label + +; CHECK: SubgroupImageBlockReadINTEL +; CHECK: SubgroupImageBlockWriteINTEL +; CHECK: SubgroupBlockReadINTEL +; CHECK: SubgroupBlockWriteINTEL + +; CHECK: SubgroupImageBlockReadINTEL +; CHECK: SubgroupImageBlockWriteINTEL +; CHECK: SubgroupBlockReadINTEL +; CHECK: SubgroupBlockWriteINTEL + +; CHECK: SubgroupImageBlockReadINTEL +; CHECK: SubgroupImageBlockWriteINTEL +; CHECK: SubgroupBlockReadINTEL +; CHECK: SubgroupBlockWriteINTEL + +; CHECK: SubgroupImageBlockReadINTEL +; CHECK: SubgroupImageBlockWriteINTEL +; CHECK: SubgroupBlockReadINTEL +; CHECK: SubgroupBlockWriteINTEL + +; CHECK-SPIRV-LABEL: Return + +%opencl.image2d_ro_t = type opaque +%opencl.image2d_wo_t = type opaque + +; Function Attrs: convergent nounwind +define spir_kernel void @test(<2 x float> %x, i32 %c, ptr addrspace(3) %image_in, ptr addrspace(3) %image_out, <2 x i32> %coord, ptr addrspace(3) %p, ptr addrspace(3) %sp, ptr addrspace(3) %cp, ptr addrspace(3) %lp) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 !kernel_arg_name !6 { +entry: + %call4 = tail call spir_func <2 x i32> @_Z27intel_sub_group_block_read214ocl_image2d_roDv2_i(ptr addrspace(3) %image_in, <2 x i32> %coord) + tail call spir_func void @_Z28intel_sub_group_block_write214ocl_image2d_woDv2_iDv2_j(ptr addrspace(3) %image_out, <2 x i32> %coord, <2 x i32> %call4) + %call5 = tail call spir_func <2 x i32> @_Z27intel_sub_group_block_read2PU3AS1Kj(ptr addrspace(3) %p) + tail call spir_func void @_Z28intel_sub_group_block_write2PU3AS1jDv2_j(ptr addrspace(3) %p, <2 x i32> %call5) + + %call6 = tail call spir_func <2 x i16> @_Z30intel_sub_group_block_read_us214ocl_image2d_roDv2_i(ptr addrspace(3) %image_in, <2 x i32> %coord) + tail call spir_func void @_Z31intel_sub_group_block_write_us214ocl_image2d_woDv2_iDv2_t(ptr addrspace(3) %image_out, <2 x i32> %coord, <2 x i16> %call6) + %call7 = tail call spir_func <2 x i16> @_Z30intel_sub_group_block_read_us2PU3AS1Kt(ptr addrspace(3) %sp) + tail call spir_func void @_Z31intel_sub_group_block_write_us2PU3AS1tDv2_t(ptr addrspace(3) %sp, <2 x i16> %call7) + + %call8 = tail call spir_func <2 x i8> @_Z30intel_sub_group_block_read_uc214ocl_image2d_roDv2_i(ptr addrspace(3) %image_in, <2 x i32> %coord) + tail call spir_func void @_Z31intel_sub_group_block_write_uc214ocl_image2d_woDv2_iDv2_h(ptr addrspace(3) %image_out, <2 x i32> %coord, <2 x i8> %call8) + %call9 = tail call spir_func <2 x i8> @_Z30intel_sub_group_block_read_uc2PU3AS1Kh(ptr addrspace(3) %cp) + tail call spir_func void @_Z31intel_sub_group_block_write_uc2PU3AS1hDv2_h(ptr addrspace(3) %cp, <2 x i8> %call9) + + %call10 = tail call spir_func <2 x i64> @_Z30intel_sub_group_block_read_ul214ocl_image2d_roDv2_i(ptr addrspace(3) %image_in, <2 x i32> %coord) + tail call spir_func void @_Z31intel_sub_group_block_write_ul214ocl_image2d_woDv2_iDv2_m(ptr addrspace(3) %image_out, <2 x i32> %coord, <2 x i64> %call10) + %call11 = tail call spir_func <2 x i64> @_Z30intel_sub_group_block_read_ul2PU3AS1Km(ptr addrspace(3) %lp) + tail call spir_func void @_Z31intel_sub_group_block_write_ul2PU3AS1mDv2_m(ptr addrspace(3) %lp, <2 x i64> %call11) + + ret void +} + +; Function Attrs: convergent +declare spir_func <2 x i32> @_Z27intel_sub_group_block_read214ocl_image2d_roDv2_i(ptr addrspace(3), <2 x i32>) + +; Function Attrs: convergent +declare spir_func void @_Z28intel_sub_group_block_write214ocl_image2d_woDv2_iDv2_j(ptr addrspace(3), <2 x i32>, <2 x i32>) + +; Function Attrs: convergent +declare spir_func <2 x i32> @_Z27intel_sub_group_block_read2PU3AS1Kj(ptr addrspace(3)) + +; Function Attrs: convergent +declare spir_func void @_Z28intel_sub_group_block_write2PU3AS1jDv2_j(ptr addrspace(3), <2 x i32>) + +; Function Attrs: convergent +declare spir_func <2 x i16> @_Z30intel_sub_group_block_read_us214ocl_image2d_roDv2_i(ptr addrspace(3), <2 x i32>) + +; Function Attrs: convergent +declare spir_func void @_Z31intel_sub_group_block_write_us214ocl_image2d_woDv2_iDv2_t(ptr addrspace(3), <2 x i32>, <2 x i16>) + +; Function Attrs: convergent +declare spir_func <2 x i16> @_Z30intel_sub_group_block_read_us2PU3AS1Kt(ptr addrspace(3)) + +; Function Attrs: convergent +declare spir_func void @_Z31intel_sub_group_block_write_us2PU3AS1tDv2_t(ptr addrspace(3), <2 x i16>) + +; Function Attrs: convergent +declare spir_func <2 x i8> @_Z30intel_sub_group_block_read_uc214ocl_image2d_roDv2_i(ptr addrspace(3), <2 x i32>) + +; Function Attrs: convergent +declare spir_func void @_Z31intel_sub_group_block_write_uc214ocl_image2d_woDv2_iDv2_h(ptr addrspace(3), <2 x i32>, <2 x i8>) + +; Function Attrs: convergent +declare spir_func <2 x i8> @_Z30intel_sub_group_block_read_uc2PU3AS1Kh(ptr addrspace(3)) + +; Function Attrs: convergent +declare spir_func void @_Z31intel_sub_group_block_write_uc2PU3AS1hDv2_h(ptr addrspace(3), <2 x i8>) + +; Function Attrs: convergent +declare spir_func <2 x i64> @_Z30intel_sub_group_block_read_ul214ocl_image2d_roDv2_i(ptr addrspace(3), <2 x i32>) + +; Function Attrs: convergent +declare spir_func void @_Z31intel_sub_group_block_write_ul214ocl_image2d_woDv2_iDv2_m(ptr addrspace(3), <2 x i32>, <2 x i64>) + +; Function Attrs: convergent +declare spir_func <2 x i64> @_Z30intel_sub_group_block_read_ul2PU3AS1Km(ptr addrspace(3)) + +; Function Attrs: convergent +declare spir_func void @_Z31intel_sub_group_block_write_ul2PU3AS1mDv2_m(ptr addrspace(3), <2 x i64>) + +!opencl.ocl.version = !{!0} +!opencl.spir.version = !{!0} + +!0 = !{i32 1, i32 2} +!1 = !{i32 0, i32 0, i32 1, i32 1, i32 0, i32 1, i32 1, i32 1, i32 1} +!2 = !{!"none", !"none", !"read_only", !"write_only", !"none", !"none", !"none", !"none", !"none"} +!3 = !{!"float2", !"uint", !"image2d_t", !"image2d_t", !"int2", !"uint*", !"ushort*", !"uchar*", !"ulong*"} +!4 = !{!"float __attribute__((ext_vector_type(2)))", !"uint", !"image2d_t", !"image2d_t", !"int __attribute__((ext_vector_type(2)))", !"uint*", !"ushort*", !"uchar*", !"ulong*"} +!5 = !{!"", !"", !"", !"", !"", !"", !"", !"", !""} +!6 = !{!"x", !"c", !"image_in", !"image_out", !"coord", !"p", !"sp", !"cp", !"lp"} diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll index e290c1eaeaba..45e71d44fbf6 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll @@ -2,6 +2,9 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_cooperative_matrix %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_cooperative_matrix %s -o - -filetype=obj | spirv-val %} +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-ERROR: LLVM ERROR: OpTypeCooperativeMatrixKHR type requires the following SPIR-V extension: SPV_KHR_cooperative_matrix ; CHECK: OpCapability CooperativeMatrixKHR diff --git a/llvm/test/CodeGen/SPIRV/half_no_extension.ll b/llvm/test/CodeGen/SPIRV/half_no_extension.ll index a5b0ec9c92d2..63cecbc7399a 100644 --- a/llvm/test/CodeGen/SPIRV/half_no_extension.ll +++ b/llvm/test/CodeGen/SPIRV/half_no_extension.ll @@ -5,10 +5,11 @@ ;; vstorea_half4_rtp( data, 0, f ); ;; } -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-SPIRV: OpCapability Float16Buffer -; CHECK-SPIRV-NOT: OpCapability Float16 +; CHECK-DAG: OpCapability Float16Buffer +; CHECK-DAG: OpCapability Float16 define spir_kernel void @test(<4 x float> addrspace(1)* %p, half addrspace(1)* %f) { entry: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupThreadID.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupThreadID.ll new file mode 100644 index 000000000000..a88debf97fa7 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_GroupThreadID.ll @@ -0,0 +1,76 @@ +; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; This file generated from the following command: +; clang -cc1 -triple spirv-vulkan-library -x hlsl -emit-llvm -disable-llvm-passes -finclude-default-header - -o - <<EOF +; [shader("compute")] +; [numthreads(1,1,1)] +; void main(uint3 ID : SV_GroupThreadID) {} +; EOF + +; CHECK-DAG: %[[#int:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#v3int:]] = OpTypeVector %[[#int]] 3 +; CHECK-DAG: %[[#ptr_Input_v3int:]] = OpTypePointer Input %[[#v3int]] +; CHECK-DAG: %[[#tempvar:]] = OpUndef %[[#v3int]] +; CHECK-DAG: %[[#LocalInvocationId:]] = OpVariable %[[#ptr_Input_v3int]] Input + +; CHECK-DAG: OpEntryPoint GLCompute {{.*}} %[[#LocalInvocationId]] +; CHECK-DAG: OpName %[[#LocalInvocationId]] "__spirv_BuiltInLocalInvocationId" +; CHECK-DAG: OpDecorate %[[#LocalInvocationId]] LinkageAttributes "__spirv_BuiltInLocalInvocationId" Import +; CHECK-DAG: OpDecorate %[[#LocalInvocationId]] BuiltIn LocalInvocationId + +; ModuleID = '-' +source_filename = "-" +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spirv-unknown-vulkan-library" + +; Function Attrs: noinline norecurse nounwind optnone +define internal spir_func void @main(<3 x i32> noundef %ID) #0 { +entry: + %ID.addr = alloca <3 x i32>, align 16 + store <3 x i32> %ID, ptr %ID.addr, align 16 + ret void +} + +; Function Attrs: norecurse +define void @main.1() #1 { +entry: + +; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#LocalInvocationId]] +; CHECK: %[[#load0:]] = OpCompositeExtract %[[#int]] %[[#load]] 0 + %0 = call i32 @llvm.spv.thread.id.in.group(i32 0) + +; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load0]] %[[#tempvar]] 0 + %1 = insertelement <3 x i32> poison, i32 %0, i64 0 + +; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#LocalInvocationId]] +; CHECK: %[[#load1:]] = OpCompositeExtract %[[#int]] %[[#load]] 1 + %2 = call i32 @llvm.spv.thread.id.in.group(i32 1) + +; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load1]] %[[#tempvar]] 1 + %3 = insertelement <3 x i32> %1, i32 %2, i64 1 + +; CHECK: %[[#load:]] = OpLoad %[[#v3int]] %[[#LocalInvocationId]] +; CHECK: %[[#load2:]] = OpCompositeExtract %[[#int]] %[[#load]] 2 + %4 = call i32 @llvm.spv.thread.id.in.group(i32 2) + +; CHECK: %[[#tempvar:]] = OpCompositeInsert %[[#v3int]] %[[#load2]] %[[#tempvar]] 2 + %5 = insertelement <3 x i32> %3, i32 %4, i64 2 + + call void @main(<3 x i32> %5) + ret void +} + +; Function Attrs: nounwind willreturn memory(none) +declare i32 @llvm.spv.thread.id.in.group(i32) #2 + +attributes #0 = { noinline norecurse nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #2 = { nounwind willreturn memory(none) } + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{!"clang version 19.0.0git (git@github.com:llvm/llvm-project.git 91600507765679e92434ec7c5edb883bf01f847f)"} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllTrue.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllTrue.ll new file mode 100644 index 000000000000..d030353ad93b --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllTrue.ll @@ -0,0 +1,21 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#bool:]] = OpTypeBool +; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3 +; CHECK-DAG: OpCapability GroupNonUniformVote + +; CHECK-LABEL: Begin function test_wave_all +define i1 @test_wave_all(i1 %p1) #0 { +entry: +; CHECK: %[[#param:]] = OpFunctionParameter %[[#bool]] +; CHECK: %{{.+}} = OpGroupNonUniformAll %[[#bool]] %[[#scope]] %[[#param]] + %0 = call token @llvm.experimental.convergence.entry() + %ret = call i1 @llvm.spv.wave.all(i1 %p1) [ "convergencectrl"(token %0) ] + ret i1 %ret +} + +declare i1 @llvm.spv.wave.all(i1) #0 + +attributes #0 = { convergent } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll index c2749d13c214..58252fe297f3 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferLoad.ll @@ -19,11 +19,11 @@ define void @RWBufferLoad_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: OpImageRead [[v4_int]] [[buffer]] [[zero]] - %data0 = call <4 x i32> @llvm.spv.typedBufferLoad( + %data0 = call <4 x i32> @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0) ret void @@ -34,12 +34,12 @@ define void @RWBufferLoad_Vec4_I32() #0 { define void @RWBufferLoad_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[V:%[0-9]+]] = OpImageRead [[v4_int]] [[buffer]] [[zero]] ; CHECK: OpCompositeExtract [[int]] [[V]] 0 - %data1 = call i32 @llvm.spv.typedBufferLoad( + %data1 = call i32 @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer1, i32 0) ret void @@ -50,14 +50,14 @@ define void @RWBufferLoad_I32() #0 { define void @RWBufferLoad_Vec2_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[V:%[0-9]+]] = OpImageRead [[v4_int]] [[buffer]] [[zero]] ; CHECK: [[e0:%[0-9]+]] = OpCompositeExtract [[int]] [[V]] 0 ; CHECK: [[e1:%[0-9]+]] = OpCompositeExtract [[int]] [[V]] 1 ; CHECK: OpCompositeConstruct [[v2_int]] [[e0]] [[e1]] - %data0 = call <2 x i32> @llvm.spv.typedBufferLoad( + %data0 = call <2 x i32> @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0) ret void diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll index afcc0ed0a455..b0ffa01ccdd4 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/BufferStore.ll @@ -22,13 +22,13 @@ declare <4 x i32> @get_data() #1 define void @RWBufferStore_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_i32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_i32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[data:%[0-9]+]] = OpFunctionCall %data = call <4 x i32> @get_data() ; CHECK: OpImageWrite [[buffer]] [[zero]] [[data]] - call void @llvm.spv.typedBufferStore(target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0, <4 x i32> %data) + call void @llvm.spv.resource.store.typedbuffer(target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) %buffer0, i32 0, <4 x i32> %data) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll index 7a21a6c4bf7e..97a7252eb067 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll @@ -26,13 +26,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[CombindedType]] [[ac]] %buffer0 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[CombindedType]] [[ac]] %buffer1 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll index b821f5bdfa13..6c5c126e4462 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll @@ -33,13 +33,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0:%[0-9]+]] = OpLoad [[CombindedType]] [[ac0]] %buffer0 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[CombindedType]] [[ac1]] %buffer1 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll index c925be1f8216..2a52dd1817f0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll @@ -25,13 +25,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll index bb2e7549fd3b..6dae79c5b385 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_6_2_0_0_2_0( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll index 69b1ac9078ff..efd89c5977f9 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } @@ -51,13 +51,13 @@ define void @DifferentArraySizesAreDifferentVariables() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[OtherVar]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 5, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll index 7d1865aca673..6d93051ce3f0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll index 3ca6788f0e48..fd276e9ef4a9 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll @@ -24,13 +24,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[SamplerType]] [[ac]] %buffer0 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[SamplerType]] [[ac]] %buffer1 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll index 0917d4751f45..3e59d66febf0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll @@ -31,13 +31,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[SamplerType]] [[ac0]] %buffer0 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[SamplerType]] [[ac1]] %buffer1 = call target("spirv.Sampler") - @llvm.spv.handle.fromBinding.tspirv.Image( + @llvm.spv.resource.handlefrombinding.tspirv.Image( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll index b264227771c3..52cc2275bc7a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/ScalarResourceType.ll @@ -20,13 +20,13 @@ define void @RWBufferLoad() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; Make sure we use the same variable with multiple loads. ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ret void } @@ -38,7 +38,7 @@ define void @UseDifferentGlobalVar() #0 { ; different types. ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeFloat]] [[FloatBufferVar]] %buffer0 = call target("spirv.Image", float, 5, 2, 0, 0, 2, 3) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_3( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_3( i32 16, i32 7, i32 1, i32 0, i1 false) ret void } @@ -50,7 +50,7 @@ define void @ReuseGlobalVarFromFirstFunction() #0 { ; same in case one function calls the other. ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll index 1922e6638832..082a5c832f1c 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll @@ -25,13 +25,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll index 231e1cf7567a..d6419492bb95 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_0_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll index 454ba1f47db0..31fdcb362eb7 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll @@ -25,13 +25,13 @@ define void @void() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll index a579aaa1eed6..a5608979025f 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll index 98c4ff7a965d..131a6b38d393 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll @@ -25,13 +25,13 @@ define void @main() #0 { ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 false) ; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 false) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll index da523f215046..cfb3eb5f5207 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll @@ -32,13 +32,13 @@ define void @main() #0 { ; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] ; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 0, i1 true) ; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] ; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_1_24( i32 3, i32 4, i32 3, i32 1, i1 true) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll index 7f9c6f7da285..4ec8605f6813 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferLoad.ll @@ -17,11 +17,11 @@ define void @RWBufferLoad_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_0( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: OpImageRead [[v4_int]] [[buffer]] [[zero]] - %data0 = call <4 x i32> @llvm.spv.typedBufferLoad( + %data0 = call <4 x i32> @llvm.spv.resource.load.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) %buffer0, i32 0) ret void diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll index 4d26f5025681..4c6f9bfd97ed 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UnknownBufferStore.ll @@ -20,13 +20,13 @@ declare <4 x i32> @get_data() #1 define void @RWBufferLoad_Vec4_I32() #0 { ; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) - @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_0( + @llvm.spv.resource.handlefrombinding.tspirv.Image_f32_5_2_0_0_2_0( i32 16, i32 7, i32 1, i32 0, i1 false) ; CHECK: [[data:%[0-9]+]] = OpFunctionCall %data = call <4 x i32> @get_data() ; CHECK: OpImageWrite [[buffer]] [[ten]] [[data]] - call void @llvm.spv.typedBufferStore( + call void @llvm.spv.resource.store.typedbuffer( target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) %buffer0, i32 10, <4 x i32> %data) ret void diff --git a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll index 640dc273dfa6..6a4b4f593bf3 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/integer-casts.ll @@ -14,6 +14,12 @@ ; CHECK-DAG: OpName [[ZEXT8_16:%.*]] "u8tou16" ; CHECK-DAG: OpName [[ZEXT16_32:%.*]] "u16tou32" +; CHECK-DAG: OpName %[[#R17:]] "r17" +; CHECK-DAG: OpName %[[#R18:]] "r18" +; CHECK-DAG: OpName %[[#R19:]] "r19" +; CHECK-DAG: OpName %[[#R20:]] "r20" +; CHECK-DAG: OpName %[[#R21:]] "r21" + ; CHECK-DAG: OpName [[TRUNC32_16v4:%.*]] "i32toi16v4" ; CHECK-DAG: OpName [[TRUNC32_8v4:%.*]] "i32toi8v4" ; CHECK-DAG: OpName [[TRUNC16_8v4:%.*]] "i16toi8v4" @@ -24,12 +30,19 @@ ; CHECK-DAG: OpName [[ZEXT8_16v4:%.*]] "u8tou16v4" ; CHECK-DAG: OpName [[ZEXT16_32v4:%.*]] "u16tou32v4" +; CHECK-DAG: OpDecorate %[[#R17]] FPRoundingMode RTZ +; CHECK-DAG: OpDecorate %[[#R18]] FPRoundingMode RTE +; CHECK-DAG: OpDecorate %[[#R19]] FPRoundingMode RTP +; CHECK-DAG: OpDecorate %[[#R20]] FPRoundingMode RTN +; CHECK-DAG: OpDecorate %[[#R21]] SaturatedConversion + ; CHECK-DAG: [[F32:%.*]] = OpTypeFloat 32 ; CHECK-DAG: [[F16:%.*]] = OpTypeFloat 16 ; CHECK-DAG: [[U64:%.*]] = OpTypeInt 64 0 ; CHECK-DAG: [[U32:%.*]] = OpTypeInt 32 0 ; CHECK-DAG: [[U16:%.*]] = OpTypeInt 16 0 ; CHECK-DAG: [[U8:%.*]] = OpTypeInt 8 0 +; CHECK-DAG: [[F32v2:%.*]] = OpTypeVector [[F32]] 2 ; CHECK-DAG: [[U32v4:%.*]] = OpTypeVector [[U32]] 4 ; CHECK-DAG: [[U16v4:%.*]] = OpTypeVector [[U16]] 4 ; CHECK-DAG: [[U8v4:%.*]] = OpTypeVector [[U8]] 4 @@ -254,6 +267,11 @@ define <4 x i32> @u16tou32v4(<4 x i16> %a) { ; CHECK: %[[#]] = OpSConvert [[U32v4]] %[[#]] ; CHECK: %[[#]] = OpConvertUToF [[F32]] %[[#]] ; CHECK: %[[#]] = OpConvertUToF [[F32]] %[[#]] +; CHECK: %[[#R17]] = OpFConvert [[F32v2]] %[[#]] +; CHECK: %[[#R18]] = OpFConvert [[F32v2]] %[[#]] +; CHECK: %[[#R19]] = OpFConvert [[F32v2]] %[[#]] +; CHECK: %[[#R20]] = OpFConvert [[F32v2]] %[[#]] +; CHECK: %[[#R21]] = OpConvertFToU [[U8]] %[[#]] ; CHECK: OpFunctionEnd define dso_local spir_kernel void @test_wrappers(ptr addrspace(4) %arg, i64 %arg_ptr, <4 x i8> %arg_v2) { %r1 = call spir_func i32 @__spirv_ConvertFToU(float 0.000000e+00) @@ -272,6 +290,11 @@ define dso_local spir_kernel void @test_wrappers(ptr addrspace(4) %arg, i64 %arg %r14 = call spir_func <4 x i32> @_Z22__spirv_SConvert_Rint2Dv2_a(<4 x i8> %arg_v2) %r15 = call spir_func float @_Z30__spirv_ConvertUToF_Rfloat_rtz(i64 %arg_ptr) %r16 = call spir_func float @__spirv_ConvertUToF_Rfloat_rtz(i64 %arg_ptr) + %r17 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtzDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>) + %r18 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rteDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>) + %r19 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtpDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>) + %r20 = call spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtnDv2_DF16_(<2 x half> noundef <half 0xH409A, half 0xH439A>) + %r21 = call spir_func i8 @_Z30__spirv_ConvertFToU_Ruchar_satf(float noundef 42.0) ret void } @@ -291,3 +314,8 @@ declare dso_local spir_func <4 x i32> @_Z22__spirv_UConvert_Rint2Dv2_a(<4 x i8>) declare dso_local spir_func <4 x i32> @_Z22__spirv_SConvert_Rint2Dv2_a(<4 x i8>) declare dso_local spir_func float @_Z30__spirv_ConvertUToF_Rfloat_rtz(i64) declare dso_local spir_func float @__spirv_ConvertUToF_Rfloat_rtz(i64) +declare dso_local spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtzDv2_DF16_(<2 x half> noundef) +declare dso_local spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rteDv2_DF16_(<2 x half> noundef) +declare dso_local spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtpDv2_DF16_(<2 x half> noundef) +declare dso_local spir_func <2 x float> @_Z28__spirv_FConvert_Rfloat2_rtnDv2_DF16_(<2 x half> noundef) +declare dso_local spir_func i8 @_Z30__spirv_ConvertFToU_Ruchar_satf(float) diff --git a/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll b/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll index e22e02f76d01..9c35d4ee9b1c 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-DAG: OpName [[SHFv4:%.+]] "shuffle_v4" ; CHECK-DAG: OpName [[INSv4:%.+]] "insert_v4" ; CHECK-DAG: OpName [[EXTv4:%.+]] "extract_v4" diff --git a/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll b/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll index 0c25d8a67aca..0dc86233f8e1 100644 --- a/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll +++ b/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll @@ -1,6 +1,6 @@ ; This test case ensures that cleaning of temporary constants doesn't purge tracked ones. -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: %[[#Int:]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll new file mode 100644 index 000000000000..11bedfa605f9 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/constrained-arithmetic.ll @@ -0,0 +1,44 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: OpName %[[#r1:]] "r1" +; CHECK-DAG: OpName %[[#r2:]] "r2" +; CHECK-DAG: OpName %[[#r3:]] "r3" +; CHECK-DAG: OpName %[[#r4:]] "r4" +; CHECK-DAG: OpName %[[#r5:]] "r5" +; CHECK-DAG: OpName %[[#r6:]] "r6" + +; CHECK-NOT: OpDecorate %[[#r5]] FPRoundingMode +; CHECK-NOT: OpDecorate %[[#r6]] FPRoundingMode + +; CHECK-DAG: OpDecorate %[[#r1]] FPRoundingMode RTE +; CHECK-DAG: OpDecorate %[[#r2]] FPRoundingMode RTZ +; CHECK-DAG: OpDecorate %[[#r4]] FPRoundingMode RTN +; CHECK-DAG: OpDecorate %[[#r3]] FPRoundingMode RTP + +; CHECK: OpFAdd %[[#]] %[[#]] +; CHECK: OpFDiv %[[#]] %[[#]] +; CHECK: OpFSub %[[#]] %[[#]] +; CHECK: OpFMul %[[#]] %[[#]] +; CHECK: OpExtInst %[[#]] %[[#]] fma %[[#]] %[[#]] %[[#]] +; CHECK: OpFRem + +; Function Attrs: norecurse nounwind strictfp +define dso_local spir_kernel void @test(float %a, i32 %in, i32 %ui) { +entry: + %r1 = tail call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.tonearest", metadata !"fpexcept.strict") + %r2 = tail call float @llvm.experimental.constrained.fdiv.f32(float %a, float %a, metadata !"round.towardzero", metadata !"fpexcept.strict") + %r3 = tail call float @llvm.experimental.constrained.fsub.f32(float %a, float %a, metadata !"round.upward", metadata !"fpexcept.strict") + %r4 = tail call float @llvm.experimental.constrained.fmul.f32(float %a, float %a, metadata !"round.downward", metadata !"fpexcept.strict") + %r5 = tail call float @llvm.experimental.constrained.fma.f32(float %a, float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") + %r6 = tail call float @llvm.experimental.constrained.frem.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret void +} + +declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) +declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) +declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata) +declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) +declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata) +declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) +declare float @llvm.experimental.constrained.frem.f32(float, float, metadata, metadata) diff --git a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll index 592de33d4d39..1a1b6c484e74 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll @@ -1,9 +1,14 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; This test only intends to check the vloadn builtin name resolution. -; The calls to the OpenCL builtins are not valid and will not pass SPIR-V validation. +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#IMPORT:]] = OpExtInstImport "OpenCL.std" +; CHECK-DAG: OpName %[[#CALL1:]] "call1" +; CHECK-DAG: OpName %[[#CALL2:]] "call2" +; CHECK-DAG: OpName %[[#CALL3:]] "call3" +; CHECK-DAG: OpName %[[#CALL4:]] "call4" +; CHECK-DAG: OpName %[[#CALL5:]] "call5" + ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#INT16:]] = OpTypeInt 16 0 ; CHECK-DAG: %[[#INT32:]] = OpTypeInt 32 0 @@ -23,20 +28,20 @@ ; CHECK: %[[#OFFSET:]] = OpFunctionParameter %[[#INT64]] define spir_kernel void @test_fn(i64 %offset, ptr addrspace(1) %address) { -; CHECK: %[[#CASTorPARAMofPTRI8:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT8]]{{.*}} -; CHECK: %[[#]] = OpExtInst %[[#VINT8]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI8]] 2 +; CHECK-DAG: %[[#CASTorPARAMofPTRI8:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT8]]{{.*}} +; CHECK-DAG: %[[#CALL1]] = OpExtInst %[[#VINT8]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI8]] 2 %call1 = call spir_func <2 x i8> @_Z6vload2mPU3AS1Kc(i64 %offset, ptr addrspace(1) %address) -; CHECK: %[[#CASTorPARAMofPTRI16:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT16]]{{.*}} -; CHECK: %[[#]] = OpExtInst %[[#VINT16]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI16]] 2 +; CHECK-DAG: %[[#CASTorPARAMofPTRI16:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT16]]{{.*}} +; CHECK-DAG: %[[#CALL2]] = OpExtInst %[[#VINT16]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI16]] 2 %call2 = call spir_func <2 x i16> @_Z6vload2mPU3AS1Ks(i64 %offset, ptr addrspace(1) %address) -; CHECK: %[[#CASTorPARAMofPTRI32:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT32]]{{.*}} -; CHECK: %[[#]] = OpExtInst %[[#VINT32]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI32]] 2 +; CHECK-DAG: %[[#CASTorPARAMofPTRI32:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT32]]{{.*}} +; CHECK-DAG: %[[#CALL3]] = OpExtInst %[[#VINT32]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI32]] 2 %call3 = call spir_func <2 x i32> @_Z6vload2mPU3AS1Ki(i64 %offset, ptr addrspace(1) %address) -; CHECK: %[[#CASTorPARAMofPTRI64:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT64]]{{.*}} -; CHECK: %[[#]] = OpExtInst %[[#VINT64]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI64]] 2 +; CHECK-DAG: %[[#CASTorPARAMofPTRI64:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRINT64]]{{.*}} +; CHECK-DAG: %[[#CALL4]] = OpExtInst %[[#VINT64]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRI64]] 2 %call4 = call spir_func <2 x i64> @_Z6vload2mPU3AS1Kl(i64 %offset, ptr addrspace(1) %address) -; CHECK: %[[#CASTorPARAMofPTRFLOAT:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRFLOAT]]{{.*}} -; CHECK: %[[#]] = OpExtInst %[[#VFLOAT]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRFLOAT]] 2 +; CHECK-DAG: %[[#CASTorPARAMofPTRFLOAT:]] = {{OpBitcast|OpFunctionParameter}}{{.*}}%[[#PTRFLOAT]]{{.*}} +; CHECK-DAG: %[[#CALL5]] = OpExtInst %[[#VFLOAT]] %[[#IMPORT]] vloadn %[[#OFFSET]] %[[#CASTorPARAMofPTRFLOAT]] 2 %call5 = call spir_func <2 x float> @_Z6vload2mPU3AS1Kf(i64 %offset, ptr addrspace(1) %address) ret void } diff --git a/llvm/test/CodeGen/SPIRV/phi-insert-point.ll b/llvm/test/CodeGen/SPIRV/phi-insert-point.ll index 41cc514f4dba..70d121cdf4b3 100644 --- a/llvm/test/CodeGen/SPIRV/phi-insert-point.ll +++ b/llvm/test/CodeGen/SPIRV/phi-insert-point.ll @@ -2,7 +2,7 @@ ; operand are inserted at the correct positions, and don't break rules of ; instruction domination and PHI nodes grouping at top of basic block. -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpName %[[#Foo:]] "foo" diff --git a/llvm/test/CodeGen/SPIRV/phi-ptrcast-dominate.ll b/llvm/test/CodeGen/SPIRV/phi-ptrcast-dominate.ll index 102eb76356fe..bc090ce55fbe 100644 --- a/llvm/test/CodeGen/SPIRV/phi-ptrcast-dominate.ll +++ b/llvm/test/CodeGen/SPIRV/phi-ptrcast-dominate.ll @@ -3,7 +3,7 @@ ; positions, and don't break rules of instruction domination and PHI nodes ; grouping at top of basic block. -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/phi-spvintrinsic-dominate.ll b/llvm/test/CodeGen/SPIRV/phi-spvintrinsic-dominate.ll index 471ab03ed89f..45831ce97263 100644 --- a/llvm/test/CodeGen/SPIRV/phi-spvintrinsic-dominate.ll +++ b/llvm/test/CodeGen/SPIRV/phi-spvintrinsic-dominate.ll @@ -3,7 +3,7 @@ ; positions, and don't break rules of instruction domination and PHI nodes ; grouping at top of basic block. -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpFunction diff --git a/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll b/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll index 485da19fd6da..d897ccd02ed9 100644 --- a/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll +++ b/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK: OpDecorate %[[#SpecConst:]] SpecId 0 ; CHECK: %[[#SpecConst]] = OpSpecConstant %[[#]] 70 ; CHECK: %[[#]] = OpPhi %[[#]] %[[#]] %[[#]] %[[#SpecConst]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll index fe71ce862dfc..481bad9a26b7 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll @@ -7,6 +7,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_KHR_bit_instructions -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_KHR_bit_instructions -o - -filetype=obj | spirv-val %} +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-SPIRV: OpCapability BitInstructions ; CHECK-SPIRV: OpExtension "SPV_KHR_bit_instructions" ; CHECK-SPIRV: %[[#CharTy:]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll index 1840ad5411f4..9d6a5e0dc0d3 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll @@ -7,6 +7,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_KHR_bit_instructions -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_KHR_bit_instructions -o - -filetype=obj | spirv-val %} +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-SPIRV: OpCapability BitInstructions ; CHECK-SPIRV: OpExtension "SPV_KHR_bit_instructions" ; CHECK-SPIRV: %[[#CharTy:]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpConstantSampler.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpConstantSampler.ll index 7e0d13490fcf..0169cc8b8fd8 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpConstantSampler.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpConstantSampler.ll @@ -12,8 +12,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; CHECK-SPIRV: %[[#SamplerID0:]] = OpConstantSampler %[[#]] Repeat 1 Nearest -; CHECK-SPIRV: %[[#SamplerID1:]] = OpConstantSampler %[[#]] None 0 Nearest +; CHECK-SPIRV-DAG: %[[#SamplerID0:]] = OpConstantSampler %[[#]] Repeat 1 Nearest +; CHECK-SPIRV-DAG: %[[#SamplerID1:]] = OpConstantSampler %[[#]] None 0 Nearest ; CHECK-SPIRV: %[[#]] = OpSampledImage %[[#]] %[[#]] %[[#SamplerID0]] ; CHECK-SPIRV: %[[#]] = OpSampledImage %[[#]] %[[#]] %[[#SamplerID1]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll index d2d5483ed361..11b613b956e0 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-SPIRV-DAG: %[[#]] = OpGroupAsyncCopy %[[#]] %[[#Scope:]] ; CHECK-SPIRV-DAG: %[[#Scope]] = OpConstant %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpPhi_ArgumentsPlaceholders.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpPhi_ArgumentsPlaceholders.ll index ee5596ed38b1..63b517c80549 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpPhi_ArgumentsPlaceholders.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpPhi_ArgumentsPlaceholders.ll @@ -14,7 +14,6 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; XFAIL: * %struct.Node = type { %struct.Node.0 addrspace(1)* } %struct.Node.0 = type opaque diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll index c770ab7f8fb5..03731b6d6756 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll @@ -1,5 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-SPIRV: OpName %[[#vec:]] "vec" ; CHECK-SPIRV: OpName %[[#index:]] "index" ; CHECK-SPIRV: OpName %[[#res:]] "res" diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll index e512f909cfd0..c8691c32710a 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll @@ -13,14 +13,33 @@ ; CHECK-DAG: %[[#TyChar:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#TyV4:]] = OpTypeVector %[[#TyChar]] 4 ; CHECK-DAG: %[[#TyStructV4:]] = OpTypeStruct %[[#TyV4]] -; CHECK-DAG: %[[#TyPtrSV4_W:]] = OpTypePointer Workgroup %[[#TyStructV4]] ; CHECK-DAG: %[[#TyPtrSV4_CW:]] = OpTypePointer CrossWorkgroup %[[#TyStructV4]] ; CHECK-DAG: %[[#TyPtrV4_W:]] = OpTypePointer Workgroup %[[#TyV4]] ; CHECK-DAG: %[[#TyPtrV4_CW:]] = OpTypePointer CrossWorkgroup %[[#TyV4]] +; CHECK-DAG: %[[#TyHalf:]] = OpTypeFloat 16 +; CHECK-DAG: %[[#TyHalfV2:]] = OpTypeVector %[[#TyHalf]] 2 +; CHECK-DAG: %[[#TyHalfV2_W:]] = OpTypePointer Workgroup %[[#TyHalfV2]] +; CHECK-DAG: %[[#TyHalfV2_CW:]] = OpTypePointer CrossWorkgroup %[[#TyHalfV2]] ; Check correct translation of __spirv_GroupAsyncCopy and target("spirv.Event") zeroinitializer ; CHECK: OpFunction +; CHECK: %[[#HalfA1:]] = OpFunctionParameter %[[#TyHalfV2_W:]] +; CHECK: %[[#HalfA2:]] = OpFunctionParameter %[[#TyHalfV2_CW:]] +; CHECK: OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#HalfA1]] %[[#HalfA2]] %[[#]] %[[#]] %[[#ConstEvent]] +; CHECK: OpFunctionEnd + +%StructEvent = type { target("spirv.Event") } + +define spir_kernel void @test_half(ptr addrspace(3) %_arg1, ptr addrspace(1) %_arg2) { +entry: + %r = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_mm9ocl_event(i32 2, ptr addrspace(3) %_arg1, ptr addrspace(1) %_arg2, i64 16, i64 10, target("spirv.Event") zeroinitializer) + ret void +} + +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_mm9ocl_event(i32 noundef, ptr addrspace(3) noundef, ptr addrspace(1) noundef, i64 noundef, i64 noundef, target("spirv.Event")) + +; CHECK: OpFunction ; CHECK: OpFunctionParameter ; CHECK: %[[#Src:]] = OpFunctionParameter ; CHECK: OpVariable %[[#TyStructPtr]] Function @@ -30,8 +49,6 @@ ; CHECK: OpStore %[[#EventVar]] %[[#CopyRes]] ; CHECK: OpFunctionEnd -%StructEvent = type { target("spirv.Event") } - define spir_kernel void @foo(ptr addrspace(1) %_arg_out_ptr, ptr addrspace(3) %_arg_local_acc) { entry: %var = alloca %StructEvent @@ -50,33 +67,17 @@ declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU ; and %_arg_Local and %_arg are source/destination arguments in OpGroupAsyncCopy ; CHECK: OpFunction -; CHECK: %[[#BarArg1:]] = OpFunctionParameter %[[#TyPtrSV4_W]] +; CHECK: %[[#BarArg1:]] = OpFunctionParameter %[[#TyPtrV4_W]] ; CHECK: %[[#BarArg2:]] = OpFunctionParameter %[[#TyPtrSV4_CW]] ; CHECK: %[[#EventVarBar:]] = OpVariable %[[#TyStructPtr]] Function ; CHECK: %[[#EventVarBarCasted2:]] = OpBitcast %[[#TyEventPtr]] %[[#EventVarBar]] -; CHECK: %[[#SrcBar:]] = OpInBoundsPtrAccessChain %[[#TyPtrSV4_CW]] %[[#BarArg2]] %[[#]] -; CHECK-DAG: %[[#BarArg1Casted:]] = OpBitcast %[[#TyPtrV4_W]] %[[#BarArg1]] -; CHECK-DAG: %[[#SrcBarCasted:]] = OpBitcast %[[#TyPtrV4_CW]] %[[#SrcBar]] -; CHECK: %[[#ResBar:]] = OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#BarArg1Casted]] %[[#SrcBarCasted]] %[[#]] %[[#]] %[[#ConstEvent]] +; CHECK: %[[#ResBar:]] = OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#BarArg1]] %[[#]] %[[#]] %[[#]] %[[#ConstEvent]] ; CHECK: %[[#EventVarBarCasted:]] = OpBitcast %[[#TyEventPtr]] %[[#EventVarBar]] ; CHECK: OpStore %[[#EventVarBarCasted]] %[[#ResBar]] ; CHECK: %[[#EventVarBarGen:]] = OpPtrCastToGeneric %[[#TyEventPtrGen]] %[[#EventVarBarCasted2]] ; CHECK: OpGroupWaitEvents %[[#]] %[[#]] %[[#EventVarBarGen]] ; CHECK: OpFunctionEnd -; CHECK2: OpFunction -; CHECK2: %[[#BarArg1:]] = OpFunctionParameter %[[#TyPtrSV4_W]] -; CHECK2: %[[#BarArg2:]] = OpFunctionParameter %[[#TyPtrSV4_CW]] -; CHECK2: %[[#EventVarBar:]] = OpVariable %[[#TyEventPtr]] Function -; CHECK2: %[[#SrcBar:]] = OpInBoundsPtrAccessChain %[[#TyPtrSV4_CW]] %[[#BarArg2]] %[[#]] -; CHECK2-DAG: %[[#BarArg1Casted:]] = OpBitcast %[[#TyPtrV4_W]] %[[#BarArg1]] -; CHECK2-DAG: %[[#SrcBarCasted:]] = OpBitcast %[[#TyPtrV4_CW]] %[[#SrcBar]] -; CHECK2: %[[#ResBar:]] = OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#BarArg1Casted]] %[[#SrcBarCasted]] %[[#]] %[[#]] %[[#ConstEvent]] -; CHECK2: OpStore %[[#EventVarBar]] %[[#ResBar]] -; CHECK2: %[[#EventVarBarGen:]] = OpPtrCastToGeneric %[[#TyEventPtrGen]] %[[#EventVarBar]] -; CHECK2: OpGroupWaitEvents %[[#]] %[[#]] %[[#EventVarBarGen]] -; CHECK2: OpFunctionEnd - %Vec4 = type { <4 x i8> } define spir_kernel void @bar(ptr addrspace(3) %_arg_Local, ptr addrspace(1) readonly %_arg) { diff --git a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll index 437e161864ec..79c2824c3dde 100644 --- a/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll +++ b/llvm/test/CodeGen/SPIRV/trunc-nonstd-bitwidth.ll @@ -8,6 +8,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s --spirv-ext=+SPV_INTEL_arbitrary_precision_integers -o - | FileCheck %s --check-prefixes=CHECK,CHECK-EXT +; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled +; XFAIL: expensive_checks + ; CHECK-DAG: OpName %[[#Struct:]] "struct" ; CHECK-DAG: OpName %[[#Arg:]] "arg" ; CHECK-DAG: OpName %[[#QArg:]] "qarg" |