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-rw-r--r--llvm/test/CodeGen/RISCV/combine-storetomstore.ll100
-rw-r--r--llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll33
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll78
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll236
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll108
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll28
-rw-r--r--llvm/test/CodeGen/RISCV/select-optimize-multiple.ll72
-rw-r--r--llvm/test/CodeGen/RISCV/sextw-removal.ll40
-rw-r--r--llvm/test/CodeGen/RISCV/simplify-condbr.ll16
9 files changed, 346 insertions, 365 deletions
diff --git a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
index c7d1f76e73cf..65c3eb64d978 100644
--- a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
@@ -73,37 +73,33 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> %
; RISCV-NEXT: vmerge.vim v11, v10, 1, v0
; RISCV-NEXT: vslidedown.vi v11, v11, 1
; RISCV-NEXT: vmv.x.s a3, v11
-; RISCV-NEXT: andi a3, a3, 1
-; RISCV-NEXT: bnez a3, .LBB4_4
+; RISCV-NEXT: andi a4, a3, 1
+; RISCV-NEXT: addi a3, a0, 24
+; RISCV-NEXT: bnez a4, .LBB4_4
; RISCV-NEXT: # %bb.3:
; RISCV-NEXT: addi a3, a1, 6
-; RISCV-NEXT: j .LBB4_5
; RISCV-NEXT: .LBB4_4:
-; RISCV-NEXT: addi a3, a0, 24
-; RISCV-NEXT: .LBB4_5:
; RISCV-NEXT: vmv1r.v v0, v9
; RISCV-NEXT: vmerge.vim v9, v10, 1, v0
; RISCV-NEXT: vslidedown.vi v9, v9, 1
; RISCV-NEXT: vmv.x.s a4, v9
; RISCV-NEXT: andi a4, a4, 1
-; RISCV-NEXT: bnez a4, .LBB4_7
-; RISCV-NEXT: # %bb.6:
-; RISCV-NEXT: addi a5, a1, 2
-; RISCV-NEXT: j .LBB4_8
-; RISCV-NEXT: .LBB4_7:
; RISCV-NEXT: addi a5, a0, 8
-; RISCV-NEXT: .LBB4_8:
+; RISCV-NEXT: bnez a4, .LBB4_6
+; RISCV-NEXT: # %bb.5:
+; RISCV-NEXT: addi a5, a1, 2
+; RISCV-NEXT: .LBB4_6:
; RISCV-NEXT: lh a4, 0(a2)
; RISCV-NEXT: lh a2, 0(a3)
; RISCV-NEXT: lh a3, 0(a5)
; RISCV-NEXT: vfirst.m a5, v8
-; RISCV-NEXT: beqz a5, .LBB4_10
-; RISCV-NEXT: # %bb.9:
+; RISCV-NEXT: beqz a5, .LBB4_8
+; RISCV-NEXT: # %bb.7:
; RISCV-NEXT: addi a0, a1, 4
-; RISCV-NEXT: j .LBB4_11
-; RISCV-NEXT: .LBB4_10:
+; RISCV-NEXT: j .LBB4_9
+; RISCV-NEXT: .LBB4_8:
; RISCV-NEXT: addi a0, a0, 16
-; RISCV-NEXT: .LBB4_11:
+; RISCV-NEXT: .LBB4_9:
; RISCV-NEXT: lh a0, 0(a0)
; RISCV-NEXT: sh a4, 0(a1)
; RISCV-NEXT: sh a3, 2(a1)
@@ -219,14 +215,12 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: vmerge.vim v13, v12, 1, v0
; RISCV-NEXT: vslidedown.vi v13, v13, 1
; RISCV-NEXT: vmv.x.s a3, v13
-; RISCV-NEXT: andi a3, a3, 1
-; RISCV-NEXT: bnez a3, .LBB11_4
+; RISCV-NEXT: andi a4, a3, 1
+; RISCV-NEXT: addi a3, a0, 56
+; RISCV-NEXT: bnez a4, .LBB11_4
; RISCV-NEXT: # %bb.3:
; RISCV-NEXT: addi a3, a1, 14
-; RISCV-NEXT: j .LBB11_5
; RISCV-NEXT: .LBB11_4:
-; RISCV-NEXT: addi a3, a0, 56
-; RISCV-NEXT: .LBB11_5:
; RISCV-NEXT: vmv1r.v v0, v8
; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RISCV-NEXT: vmerge.vim v10, v10, 1, v0
@@ -238,50 +232,40 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: vmerge.vim v13, v12, 1, v0
; RISCV-NEXT: vslidedown.vi v13, v13, 1
; RISCV-NEXT: vmv.x.s a4, v13
-; RISCV-NEXT: andi a4, a4, 1
-; RISCV-NEXT: bnez a4, .LBB11_8
-; RISCV-NEXT: # %bb.6:
+; RISCV-NEXT: andi a5, a4, 1
+; RISCV-NEXT: addi a4, a0, 24
+; RISCV-NEXT: bnez a5, .LBB11_6
+; RISCV-NEXT: # %bb.5:
; RISCV-NEXT: addi a4, a1, 6
-; RISCV-NEXT: vfirst.m a5, v11
-; RISCV-NEXT: bnez a5, .LBB11_9
-; RISCV-NEXT: .LBB11_7:
+; RISCV-NEXT: .LBB11_6:
+; RISCV-NEXT: vfirst.m a6, v11
; RISCV-NEXT: addi a5, a0, 32
-; RISCV-NEXT: j .LBB11_10
-; RISCV-NEXT: .LBB11_8:
-; RISCV-NEXT: addi a4, a0, 24
-; RISCV-NEXT: vfirst.m a5, v11
-; RISCV-NEXT: beqz a5, .LBB11_7
-; RISCV-NEXT: .LBB11_9:
+; RISCV-NEXT: beqz a6, .LBB11_8
+; RISCV-NEXT: # %bb.7:
; RISCV-NEXT: addi a5, a1, 8
-; RISCV-NEXT: .LBB11_10:
+; RISCV-NEXT: .LBB11_8:
; RISCV-NEXT: vmv1r.v v0, v11
; RISCV-NEXT: vmerge.vim v11, v12, 1, v0
; RISCV-NEXT: vslidedown.vi v11, v11, 1
; RISCV-NEXT: vmv.x.s a6, v11
-; RISCV-NEXT: andi a6, a6, 1
-; RISCV-NEXT: bnez a6, .LBB11_14
-; RISCV-NEXT: # %bb.11:
+; RISCV-NEXT: andi a7, a6, 1
+; RISCV-NEXT: addi a6, a0, 40
+; RISCV-NEXT: bnez a7, .LBB11_10
+; RISCV-NEXT: # %bb.9:
; RISCV-NEXT: addi a6, a1, 10
-; RISCV-NEXT: vfirst.m a7, v9
-; RISCV-NEXT: bnez a7, .LBB11_15
-; RISCV-NEXT: .LBB11_12:
+; RISCV-NEXT: .LBB11_10:
+; RISCV-NEXT: vfirst.m t0, v9
; RISCV-NEXT: addi a7, a0, 48
-; RISCV-NEXT: vfirst.m t0, v10
-; RISCV-NEXT: bnez t0, .LBB11_16
-; RISCV-NEXT: .LBB11_13:
-; RISCV-NEXT: addi t1, a0, 16
-; RISCV-NEXT: j .LBB11_17
-; RISCV-NEXT: .LBB11_14:
-; RISCV-NEXT: addi a6, a0, 40
-; RISCV-NEXT: vfirst.m a7, v9
-; RISCV-NEXT: beqz a7, .LBB11_12
-; RISCV-NEXT: .LBB11_15:
+; RISCV-NEXT: beqz t0, .LBB11_12
+; RISCV-NEXT: # %bb.11:
; RISCV-NEXT: addi a7, a1, 12
+; RISCV-NEXT: .LBB11_12:
; RISCV-NEXT: vfirst.m t0, v10
-; RISCV-NEXT: beqz t0, .LBB11_13
-; RISCV-NEXT: .LBB11_16:
+; RISCV-NEXT: addi t1, a0, 16
+; RISCV-NEXT: beqz t0, .LBB11_14
+; RISCV-NEXT: # %bb.13:
; RISCV-NEXT: addi t1, a1, 4
-; RISCV-NEXT: .LBB11_17:
+; RISCV-NEXT: .LBB11_14:
; RISCV-NEXT: vmv1r.v v0, v8
; RISCV-NEXT: lh t0, 0(a2)
; RISCV-NEXT: lh a2, 0(a3)
@@ -294,13 +278,13 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: vslidedown.vi v8, v8, 1
; RISCV-NEXT: vmv.x.s t1, v8
; RISCV-NEXT: andi t1, t1, 1
-; RISCV-NEXT: bnez t1, .LBB11_19
-; RISCV-NEXT: # %bb.18:
+; RISCV-NEXT: bnez t1, .LBB11_16
+; RISCV-NEXT: # %bb.15:
; RISCV-NEXT: addi a0, a1, 2
-; RISCV-NEXT: j .LBB11_20
-; RISCV-NEXT: .LBB11_19:
+; RISCV-NEXT: j .LBB11_17
+; RISCV-NEXT: .LBB11_16:
; RISCV-NEXT: addi a0, a0, 8
-; RISCV-NEXT: .LBB11_20:
+; RISCV-NEXT: .LBB11_17:
; RISCV-NEXT: lh a0, 0(a0)
; RISCV-NEXT: sh t0, 0(a1)
; RISCV-NEXT: sh a0, 2(a1)
diff --git a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
index 6136c321c08c..252ecd33ca47 100644
--- a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
@@ -48,38 +48,35 @@ for.body: ; preds = %for.body.preheader,
define void @test2(ptr nocapture noundef %a, i32 noundef signext %n) {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: blez a1, .LBB1_7
+; CHECK-NEXT: blez a1, .LBB1_6
; CHECK-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-NEXT: li a3, 1
-; CHECK-NEXT: andi a2, a1, 1
-; CHECK-NEXT: bne a1, a3, .LBB1_3
-; CHECK-NEXT: # %bb.2:
-; CHECK-NEXT: li a3, 0
-; CHECK-NEXT: j .LBB1_5
-; CHECK-NEXT: .LBB1_3: # %for.body.preheader.new
-; CHECK-NEXT: li a3, 0
+; CHECK-NEXT: li a4, 1
+; CHECK-NEXT: andi a3, a1, 1
+; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: beq a1, a4, .LBB1_4
+; CHECK-NEXT: # %bb.2: # %for.body.preheader.new
; CHECK-NEXT: andi a1, a1, -2
; CHECK-NEXT: addi a4, a0, 4
-; CHECK-NEXT: .LBB1_4: # %for.body
+; CHECK-NEXT: .LBB1_3: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a5, -4(a4)
; CHECK-NEXT: lw a6, 0(a4)
-; CHECK-NEXT: addi a3, a3, 2
+; CHECK-NEXT: addi a2, a2, 2
; CHECK-NEXT: addi a5, a5, 4
; CHECK-NEXT: addi a6, a6, 4
; CHECK-NEXT: sw a5, -4(a4)
; CHECK-NEXT: sw a6, 0(a4)
; CHECK-NEXT: addi a4, a4, 8
-; CHECK-NEXT: bne a1, a3, .LBB1_4
-; CHECK-NEXT: .LBB1_5: # %for.cond.cleanup.loopexit.unr-lcssa
-; CHECK-NEXT: beqz a2, .LBB1_7
-; CHECK-NEXT: # %bb.6: # %for.body.epil
-; CHECK-NEXT: slli a3, a3, 2
-; CHECK-NEXT: add a0, a0, a3
+; CHECK-NEXT: bne a1, a2, .LBB1_3
+; CHECK-NEXT: .LBB1_4: # %for.cond.cleanup.loopexit.unr-lcssa
+; CHECK-NEXT: beqz a3, .LBB1_6
+; CHECK-NEXT: # %bb.5: # %for.body.epil
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: addi a1, a1, 4
; CHECK-NEXT: sw a1, 0(a0)
-; CHECK-NEXT: .LBB1_7: # %for.cond.cleanup
+; CHECK-NEXT: .LBB1_6: # %for.cond.cleanup
; CHECK-NEXT: ret
entry:
%cmp3 = icmp sgt i32 %n, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
index 31fa5d025156..a3374c5c34b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
@@ -88,8 +88,8 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
; NO-SINK: # %bb.0: # %entry
; NO-SINK-NEXT: csrr a5, vlenb
; NO-SINK-NEXT: srli a3, a5, 1
-; NO-SINK-NEXT: li a2, 1024
-; NO-SINK-NEXT: bgeu a2, a3, .LBB1_2
+; NO-SINK-NEXT: li a4, 1024
+; NO-SINK-NEXT: bgeu a4, a3, .LBB1_2
; NO-SINK-NEXT: # %bb.1:
; NO-SINK-NEXT: li a2, 0
; NO-SINK-NEXT: j .LBB1_5
@@ -131,8 +131,8 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
; SINK: # %bb.0: # %entry
; SINK-NEXT: csrr a5, vlenb
; SINK-NEXT: srli a3, a5, 1
-; SINK-NEXT: li a2, 1024
-; SINK-NEXT: bgeu a2, a3, .LBB1_2
+; SINK-NEXT: li a4, 1024
+; SINK-NEXT: bgeu a4, a3, .LBB1_2
; SINK-NEXT: # %bb.1:
; SINK-NEXT: li a2, 0
; SINK-NEXT: j .LBB1_5
@@ -173,8 +173,8 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
; DEFAULT: # %bb.0: # %entry
; DEFAULT-NEXT: csrr a5, vlenb
; DEFAULT-NEXT: srli a3, a5, 1
-; DEFAULT-NEXT: li a2, 1024
-; DEFAULT-NEXT: bgeu a2, a3, .LBB1_2
+; DEFAULT-NEXT: li a4, 1024
+; DEFAULT-NEXT: bgeu a4, a3, .LBB1_2
; DEFAULT-NEXT: # %bb.1:
; DEFAULT-NEXT: li a2, 0
; DEFAULT-NEXT: j .LBB1_5
@@ -406,33 +406,33 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; NO-SINK-LABEL: sink_splat_fadd_scalable:
; NO-SINK: # %bb.0: # %entry
-; NO-SINK-NEXT: csrr a1, vlenb
-; NO-SINK-NEXT: srli a3, a1, 2
-; NO-SINK-NEXT: li a2, 1024
-; NO-SINK-NEXT: bgeu a2, a3, .LBB4_2
+; NO-SINK-NEXT: csrr a2, vlenb
+; NO-SINK-NEXT: srli a3, a2, 2
+; NO-SINK-NEXT: li a4, 1024
+; NO-SINK-NEXT: bgeu a4, a3, .LBB4_2
; NO-SINK-NEXT: # %bb.1:
-; NO-SINK-NEXT: li a2, 0
+; NO-SINK-NEXT: li a1, 0
; NO-SINK-NEXT: j .LBB4_5
; NO-SINK-NEXT: .LBB4_2: # %vector.ph
-; NO-SINK-NEXT: addi a2, a3, -1
-; NO-SINK-NEXT: andi a4, a2, 1024
-; NO-SINK-NEXT: xori a2, a4, 1024
+; NO-SINK-NEXT: addi a1, a3, -1
+; NO-SINK-NEXT: andi a4, a1, 1024
+; NO-SINK-NEXT: xori a1, a4, 1024
; NO-SINK-NEXT: vsetvli a5, zero, e32, m1, ta, ma
; NO-SINK-NEXT: vfmv.v.f v8, fa0
; NO-SINK-NEXT: mv a5, a0
-; NO-SINK-NEXT: mv a6, a2
+; NO-SINK-NEXT: mv a6, a1
; NO-SINK-NEXT: .LBB4_3: # %vector.body
; NO-SINK-NEXT: # =>This Inner Loop Header: Depth=1
; NO-SINK-NEXT: vl1re32.v v9, (a5)
; NO-SINK-NEXT: sub a6, a6, a3
; NO-SINK-NEXT: vfadd.vv v9, v9, v8
; NO-SINK-NEXT: vs1r.v v9, (a5)
-; NO-SINK-NEXT: add a5, a5, a1
+; NO-SINK-NEXT: add a5, a5, a2
; NO-SINK-NEXT: bnez a6, .LBB4_3
; NO-SINK-NEXT: # %bb.4: # %middle.block
; NO-SINK-NEXT: beqz a4, .LBB4_7
; NO-SINK-NEXT: .LBB4_5: # %for.body.preheader
-; NO-SINK-NEXT: slli a1, a2, 2
+; NO-SINK-NEXT: slli a1, a1, 2
; NO-SINK-NEXT: lui a2, 1
; NO-SINK-NEXT: add a1, a0, a1
; NO-SINK-NEXT: add a0, a0, a2
@@ -448,19 +448,19 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
;
; SINK-LABEL: sink_splat_fadd_scalable:
; SINK: # %bb.0: # %entry
-; SINK-NEXT: csrr a1, vlenb
-; SINK-NEXT: srli a3, a1, 2
-; SINK-NEXT: li a2, 1024
-; SINK-NEXT: bgeu a2, a3, .LBB4_2
+; SINK-NEXT: csrr a2, vlenb
+; SINK-NEXT: srli a3, a2, 2
+; SINK-NEXT: li a4, 1024
+; SINK-NEXT: bgeu a4, a3, .LBB4_2
; SINK-NEXT: # %bb.1:
-; SINK-NEXT: li a2, 0
+; SINK-NEXT: li a1, 0
; SINK-NEXT: j .LBB4_5
; SINK-NEXT: .LBB4_2: # %vector.ph
-; SINK-NEXT: addi a2, a3, -1
-; SINK-NEXT: andi a4, a2, 1024
-; SINK-NEXT: xori a2, a4, 1024
+; SINK-NEXT: addi a1, a3, -1
+; SINK-NEXT: andi a4, a1, 1024
+; SINK-NEXT: xori a1, a4, 1024
; SINK-NEXT: mv a5, a0
-; SINK-NEXT: mv a6, a2
+; SINK-NEXT: mv a6, a1
; SINK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; SINK-NEXT: .LBB4_3: # %vector.body
; SINK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -468,12 +468,12 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; SINK-NEXT: sub a6, a6, a3
; SINK-NEXT: vfadd.vf v8, v8, fa0
; SINK-NEXT: vs1r.v v8, (a5)
-; SINK-NEXT: add a5, a5, a1
+; SINK-NEXT: add a5, a5, a2
; SINK-NEXT: bnez a6, .LBB4_3
; SINK-NEXT: # %bb.4: # %middle.block
; SINK-NEXT: beqz a4, .LBB4_7
; SINK-NEXT: .LBB4_5: # %for.body.preheader
-; SINK-NEXT: slli a1, a2, 2
+; SINK-NEXT: slli a1, a1, 2
; SINK-NEXT: lui a2, 1
; SINK-NEXT: add a1, a0, a1
; SINK-NEXT: add a0, a0, a2
@@ -489,19 +489,19 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
;
; DEFAULT-LABEL: sink_splat_fadd_scalable:
; DEFAULT: # %bb.0: # %entry
-; DEFAULT-NEXT: csrr a1, vlenb
-; DEFAULT-NEXT: srli a3, a1, 2
-; DEFAULT-NEXT: li a2, 1024
-; DEFAULT-NEXT: bgeu a2, a3, .LBB4_2
+; DEFAULT-NEXT: csrr a2, vlenb
+; DEFAULT-NEXT: srli a3, a2, 2
+; DEFAULT-NEXT: li a4, 1024
+; DEFAULT-NEXT: bgeu a4, a3, .LBB4_2
; DEFAULT-NEXT: # %bb.1:
-; DEFAULT-NEXT: li a2, 0
+; DEFAULT-NEXT: li a1, 0
; DEFAULT-NEXT: j .LBB4_5
; DEFAULT-NEXT: .LBB4_2: # %vector.ph
-; DEFAULT-NEXT: addi a2, a3, -1
-; DEFAULT-NEXT: andi a4, a2, 1024
-; DEFAULT-NEXT: xori a2, a4, 1024
+; DEFAULT-NEXT: addi a1, a3, -1
+; DEFAULT-NEXT: andi a4, a1, 1024
+; DEFAULT-NEXT: xori a1, a4, 1024
; DEFAULT-NEXT: mv a5, a0
-; DEFAULT-NEXT: mv a6, a2
+; DEFAULT-NEXT: mv a6, a1
; DEFAULT-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; DEFAULT-NEXT: .LBB4_3: # %vector.body
; DEFAULT-NEXT: # =>This Inner Loop Header: Depth=1
@@ -509,12 +509,12 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; DEFAULT-NEXT: sub a6, a6, a3
; DEFAULT-NEXT: vfadd.vf v8, v8, fa0
; DEFAULT-NEXT: vs1r.v v8, (a5)
-; DEFAULT-NEXT: add a5, a5, a1
+; DEFAULT-NEXT: add a5, a5, a2
; DEFAULT-NEXT: bnez a6, .LBB4_3
; DEFAULT-NEXT: # %bb.4: # %middle.block
; DEFAULT-NEXT: beqz a4, .LBB4_7
; DEFAULT-NEXT: .LBB4_5: # %for.body.preheader
-; DEFAULT-NEXT: slli a1, a2, 2
+; DEFAULT-NEXT: slli a1, a1, 2
; DEFAULT-NEXT: lui a2, 1
; DEFAULT-NEXT: add a1, a0, a1
; DEFAULT-NEXT: add a0, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index 02825b2bda48..287050c06b90 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -245,8 +245,8 @@ define void @sink_splat_mul_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB7_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB7_5
@@ -336,8 +336,8 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB8_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB8_5
@@ -427,8 +427,8 @@ define void @sink_splat_sub_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB9_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB9_5
@@ -518,8 +518,8 @@ define void @sink_splat_rsub_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB10_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB10_5
@@ -609,8 +609,8 @@ define void @sink_splat_and_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB11_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB11_5
@@ -700,8 +700,8 @@ define void @sink_splat_or_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB12_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB12_5
@@ -791,8 +791,8 @@ define void @sink_splat_xor_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB13_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB13_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB13_5
@@ -984,8 +984,8 @@ define void @sink_splat_shl_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB17_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB17_5
@@ -1075,8 +1075,8 @@ define void @sink_splat_lshr_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB18_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB18_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB18_5
@@ -1166,8 +1166,8 @@ define void @sink_splat_ashr_scalable(ptr nocapture %a) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: srli a2, a4, 1
-; CHECK-NEXT: li a1, 1024
-; CHECK-NEXT: bgeu a1, a2, .LBB19_2
+; CHECK-NEXT: li a3, 1024
+; CHECK-NEXT: bgeu a3, a2, .LBB19_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB19_5
@@ -1457,19 +1457,19 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_fmul_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fmul_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB26_2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB26_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB26_5
; CHECK-NEXT: .LBB26_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB26_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1477,12 +1477,12 @@ define void @sink_splat_fmul_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB26_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB26_7
; CHECK-NEXT: .LBB26_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1547,19 +1547,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fdiv_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB27_2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB27_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB27_5
; CHECK-NEXT: .LBB27_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB27_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1567,12 +1567,12 @@ define void @sink_splat_fdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB27_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB27_7
; CHECK-NEXT: .LBB27_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1637,19 +1637,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_frdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_frdiv_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB28_2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB28_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB28_5
; CHECK-NEXT: .LBB28_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB28_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1657,12 +1657,12 @@ define void @sink_splat_frdiv_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB28_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB28_7
; CHECK-NEXT: .LBB28_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1727,19 +1727,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fadd_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB29_2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB29_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB29_5
; CHECK-NEXT: .LBB29_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB29_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1747,12 +1747,12 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB29_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB29_7
; CHECK-NEXT: .LBB29_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1817,19 +1817,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fsub_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fsub_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB30_2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB30_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB30_5
; CHECK-NEXT: .LBB30_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB30_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1837,12 +1837,12 @@ define void @sink_splat_fsub_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB30_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB30_7
; CHECK-NEXT: .LBB30_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -1907,19 +1907,19 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_frsub_scalable(ptr nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_frsub_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a3, a1, 2
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB31_2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB31_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB31_5
; CHECK-NEXT: .LBB31_2: # %vector.ph
-; CHECK-NEXT: addi a2, a3, -1
-; CHECK-NEXT: andi a4, a2, 1024
-; CHECK-NEXT: xori a2, a4, 1024
+; CHECK-NEXT: addi a1, a3, -1
+; CHECK-NEXT: andi a4, a1, 1024
+; CHECK-NEXT: xori a1, a4, 1024
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB31_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@@ -1927,12 +1927,12 @@ define void @sink_splat_frsub_scalable(ptr nocapture %a, float %x) {
; CHECK-NEXT: sub a6, a6, a3
; CHECK-NEXT: vfrsub.vf v8, v8, fa0
; CHECK-NEXT: vs1r.v v8, (a5)
-; CHECK-NEXT: add a5, a5, a1
+; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: bnez a6, .LBB31_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a4, .LBB31_7
; CHECK-NEXT: .LBB31_5: # %for.body.preheader
-; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: add a0, a0, a2
@@ -2073,35 +2073,35 @@ for.cond.cleanup: ; preds = %vector.body
define void @sink_splat_fma_scalable(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, float %x) {
; CHECK-LABEL: sink_splat_fma_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a4, a2, 2
-; CHECK-NEXT: li a3, 1024
-; CHECK-NEXT: bgeu a3, a4, .LBB34_2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: srli a4, a3, 2
+; CHECK-NEXT: li a5, 1024
+; CHECK-NEXT: bgeu a5, a4, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a3, 0
+; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB34_5
; CHECK-NEXT: .LBB34_2: # %vector.ph
-; CHECK-NEXT: addi a3, a4, -1
-; CHECK-NEXT: andi a5, a3, 1024
-; CHECK-NEXT: xori a3, a5, 1024
+; CHECK-NEXT: addi a2, a4, -1
+; CHECK-NEXT: andi a5, a2, 1024
+; CHECK-NEXT: xori a2, a5, 1024
; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: mv a7, a1
-; CHECK-NEXT: mv t0, a3
+; CHECK-NEXT: mv t0, a2
; CHECK-NEXT: vsetvli t1, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB34_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vl1re32.v v9, (a7)
; CHECK-NEXT: sub t0, t0, a4
-; CHECK-NEXT: add a7, a7, a2
+; CHECK-NEXT: add a7, a7, a3
; CHECK-NEXT: vfmacc.vf v9, fa0, v8
; CHECK-NEXT: vs1r.v v9, (a6)
-; CHECK-NEXT: add a6, a6, a2
+; CHECK-NEXT: add a6, a6, a3
; CHECK-NEXT: bnez t0, .LBB34_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a5, .LBB34_7
; CHECK-NEXT: .LBB34_5: # %for.body.preheader
-; CHECK-NEXT: slli a2, a3, 2
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: lui a3, 1
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: add a2, a1, a2
@@ -2173,35 +2173,35 @@ for.body: ; preds = %for.body.preheader,
define void @sink_splat_fma_commute_scalable(ptr noalias nocapture %a, ptr noalias nocapture readonly %b, float %x) {
; CHECK-LABEL: sink_splat_fma_commute_scalable:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a4, a2, 2
-; CHECK-NEXT: li a3, 1024
-; CHECK-NEXT: bgeu a3, a4, .LBB35_2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: srli a4, a3, 2
+; CHECK-NEXT: li a5, 1024
+; CHECK-NEXT: bgeu a5, a4, .LBB35_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: li a3, 0
+; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB35_5
; CHECK-NEXT: .LBB35_2: # %vector.ph
-; CHECK-NEXT: addi a3, a4, -1
-; CHECK-NEXT: andi a5, a3, 1024
-; CHECK-NEXT: xori a3, a5, 1024
+; CHECK-NEXT: addi a2, a4, -1
+; CHECK-NEXT: andi a5, a2, 1024
+; CHECK-NEXT: xori a2, a5, 1024
; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: mv a7, a1
-; CHECK-NEXT: mv t0, a3
+; CHECK-NEXT: mv t0, a2
; CHECK-NEXT: vsetvli t1, zero, e32, m1, ta, ma
; CHECK-NEXT: .LBB35_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vl1re32.v v9, (a7)
; CHECK-NEXT: sub t0, t0, a4
-; CHECK-NEXT: add a7, a7, a2
+; CHECK-NEXT: add a7, a7, a3
; CHECK-NEXT: vfmacc.vf v9, fa0, v8
; CHECK-NEXT: vs1r.v v9, (a6)
-; CHECK-NEXT: add a6, a6, a2
+; CHECK-NEXT: add a6, a6, a3
; CHECK-NEXT: bnez t0, .LBB35_3
; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a5, .LBB35_7
; CHECK-NEXT: .LBB35_5: # %for.body.preheader
-; CHECK-NEXT: slli a2, a3, 2
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: lui a3, 1
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: add a2, a1, a2
@@ -2488,8 +2488,8 @@ define void @sink_splat_udiv_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB42_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB42_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB42_5
@@ -2579,8 +2579,8 @@ define void @sink_splat_sdiv_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB43_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB43_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB43_5
@@ -2670,8 +2670,8 @@ define void @sink_splat_urem_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB44_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB44_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB44_5
@@ -2761,8 +2761,8 @@ define void @sink_splat_srem_scalable(ptr nocapture %a, i32 signext %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a3, a5, 1
-; CHECK-NEXT: li a2, 1024
-; CHECK-NEXT: bgeu a2, a3, .LBB45_2
+; CHECK-NEXT: li a4, 1024
+; CHECK-NEXT: bgeu a4, a3, .LBB45_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB45_5
diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
index f295bd8d74df..cb101f99e932 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
@@ -2240,19 +2240,19 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-RV32-LABEL: vand_vx_loop_hoisted_not:
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT: csrr a4, vlenb
-; CHECK-RV32-NEXT: srli a2, a4, 3
-; CHECK-RV32-NEXT: li a3, 64
+; CHECK-RV32-NEXT: srli a3, a4, 3
+; CHECK-RV32-NEXT: li a5, 64
; CHECK-RV32-NEXT: not a1, a1
-; CHECK-RV32-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-RV32-NEXT: bgeu a5, a3, .LBB98_2
; CHECK-RV32-NEXT: # %bb.1:
-; CHECK-RV32-NEXT: li a3, 0
; CHECK-RV32-NEXT: li a2, 0
+; CHECK-RV32-NEXT: li a3, 0
; CHECK-RV32-NEXT: j .LBB98_5
; CHECK-RV32-NEXT: .LBB98_2: # %vector.ph
-; CHECK-RV32-NEXT: li a2, 0
+; CHECK-RV32-NEXT: li a3, 0
; CHECK-RV32-NEXT: srli a4, a4, 1
-; CHECK-RV32-NEXT: neg a3, a4
-; CHECK-RV32-NEXT: andi a3, a3, 256
+; CHECK-RV32-NEXT: neg a2, a4
+; CHECK-RV32-NEXT: andi a2, a2, 256
; CHECK-RV32-NEXT: li a6, 0
; CHECK-RV32-NEXT: li a5, 0
; CHECK-RV32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2264,25 +2264,25 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-RV32-NEXT: vl2re32.v v8, (a7)
; CHECK-RV32-NEXT: sltu a6, t0, a6
; CHECK-RV32-NEXT: add a5, a5, a6
-; CHECK-RV32-NEXT: xor a6, t0, a3
+; CHECK-RV32-NEXT: xor a6, t0, a2
; CHECK-RV32-NEXT: vand.vx v8, v8, a1
; CHECK-RV32-NEXT: or t1, a6, a5
; CHECK-RV32-NEXT: vs2r.v v8, (a7)
; CHECK-RV32-NEXT: mv a6, t0
; CHECK-RV32-NEXT: bnez t1, .LBB98_3
; CHECK-RV32-NEXT: # %bb.4: # %middle.block
-; CHECK-RV32-NEXT: bnez a3, .LBB98_6
+; CHECK-RV32-NEXT: bnez a2, .LBB98_6
; CHECK-RV32-NEXT: .LBB98_5: # %for.body
; CHECK-RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-RV32-NEXT: slli a4, a3, 2
-; CHECK-RV32-NEXT: addi a3, a3, 1
+; CHECK-RV32-NEXT: slli a4, a2, 2
+; CHECK-RV32-NEXT: addi a2, a2, 1
; CHECK-RV32-NEXT: add a4, a0, a4
; CHECK-RV32-NEXT: lw a5, 0(a4)
-; CHECK-RV32-NEXT: seqz a6, a3
-; CHECK-RV32-NEXT: add a2, a2, a6
-; CHECK-RV32-NEXT: xori a6, a3, 256
+; CHECK-RV32-NEXT: seqz a6, a2
+; CHECK-RV32-NEXT: add a3, a3, a6
+; CHECK-RV32-NEXT: xori a6, a2, 256
; CHECK-RV32-NEXT: and a5, a5, a1
-; CHECK-RV32-NEXT: or a6, a6, a2
+; CHECK-RV32-NEXT: or a6, a6, a3
; CHECK-RV32-NEXT: sw a5, 0(a4)
; CHECK-RV32-NEXT: bnez a6, .LBB98_5
; CHECK-RV32-NEXT: .LBB98_6: # %for.cond.cleanup
@@ -2291,10 +2291,10 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-RV64-LABEL: vand_vx_loop_hoisted_not:
; CHECK-RV64: # %bb.0: # %entry
; CHECK-RV64-NEXT: csrr a4, vlenb
-; CHECK-RV64-NEXT: srli a2, a4, 3
-; CHECK-RV64-NEXT: li a3, 64
+; CHECK-RV64-NEXT: srli a3, a4, 3
+; CHECK-RV64-NEXT: li a5, 64
; CHECK-RV64-NEXT: not a1, a1
-; CHECK-RV64-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-RV64-NEXT: bgeu a5, a3, .LBB98_2
; CHECK-RV64-NEXT: # %bb.1:
; CHECK-RV64-NEXT: li a2, 0
; CHECK-RV64-NEXT: j .LBB98_5
@@ -2333,18 +2333,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-NOZBB32-LABEL: vand_vx_loop_hoisted_not:
; CHECK-ZVKB-NOZBB32: # %bb.0: # %entry
; CHECK-ZVKB-NOZBB32-NEXT: csrr a4, vlenb
-; CHECK-ZVKB-NOZBB32-NEXT: srli a2, a4, 3
-; CHECK-ZVKB-NOZBB32-NEXT: li a3, 64
-; CHECK-ZVKB-NOZBB32-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-ZVKB-NOZBB32-NEXT: srli a3, a4, 3
+; CHECK-ZVKB-NOZBB32-NEXT: li a5, 64
+; CHECK-ZVKB-NOZBB32-NEXT: bgeu a5, a3, .LBB98_2
; CHECK-ZVKB-NOZBB32-NEXT: # %bb.1:
-; CHECK-ZVKB-NOZBB32-NEXT: li a3, 0
; CHECK-ZVKB-NOZBB32-NEXT: li a2, 0
+; CHECK-ZVKB-NOZBB32-NEXT: li a3, 0
; CHECK-ZVKB-NOZBB32-NEXT: j .LBB98_5
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_2: # %vector.ph
-; CHECK-ZVKB-NOZBB32-NEXT: li a2, 0
+; CHECK-ZVKB-NOZBB32-NEXT: li a3, 0
; CHECK-ZVKB-NOZBB32-NEXT: srli a4, a4, 1
-; CHECK-ZVKB-NOZBB32-NEXT: neg a3, a4
-; CHECK-ZVKB-NOZBB32-NEXT: andi a3, a3, 256
+; CHECK-ZVKB-NOZBB32-NEXT: neg a2, a4
+; CHECK-ZVKB-NOZBB32-NEXT: andi a2, a2, 256
; CHECK-ZVKB-NOZBB32-NEXT: li a6, 0
; CHECK-ZVKB-NOZBB32-NEXT: li a5, 0
; CHECK-ZVKB-NOZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2356,27 +2356,27 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-NOZBB32-NEXT: vl2re32.v v8, (a7)
; CHECK-ZVKB-NOZBB32-NEXT: sltu a6, t0, a6
; CHECK-ZVKB-NOZBB32-NEXT: add a5, a5, a6
-; CHECK-ZVKB-NOZBB32-NEXT: xor a6, t0, a3
+; CHECK-ZVKB-NOZBB32-NEXT: xor a6, t0, a2
; CHECK-ZVKB-NOZBB32-NEXT: vandn.vx v8, v8, a1
; CHECK-ZVKB-NOZBB32-NEXT: or t1, a6, a5
; CHECK-ZVKB-NOZBB32-NEXT: vs2r.v v8, (a7)
; CHECK-ZVKB-NOZBB32-NEXT: mv a6, t0
; CHECK-ZVKB-NOZBB32-NEXT: bnez t1, .LBB98_3
; CHECK-ZVKB-NOZBB32-NEXT: # %bb.4: # %middle.block
-; CHECK-ZVKB-NOZBB32-NEXT: bnez a3, .LBB98_7
+; CHECK-ZVKB-NOZBB32-NEXT: bnez a2, .LBB98_7
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_5: # %for.body.preheader
; CHECK-ZVKB-NOZBB32-NEXT: not a1, a1
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_6: # %for.body
; CHECK-ZVKB-NOZBB32-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-ZVKB-NOZBB32-NEXT: slli a4, a3, 2
-; CHECK-ZVKB-NOZBB32-NEXT: addi a3, a3, 1
+; CHECK-ZVKB-NOZBB32-NEXT: slli a4, a2, 2
+; CHECK-ZVKB-NOZBB32-NEXT: addi a2, a2, 1
; CHECK-ZVKB-NOZBB32-NEXT: add a4, a0, a4
; CHECK-ZVKB-NOZBB32-NEXT: lw a5, 0(a4)
-; CHECK-ZVKB-NOZBB32-NEXT: seqz a6, a3
-; CHECK-ZVKB-NOZBB32-NEXT: add a2, a2, a6
-; CHECK-ZVKB-NOZBB32-NEXT: xori a6, a3, 256
+; CHECK-ZVKB-NOZBB32-NEXT: seqz a6, a2
+; CHECK-ZVKB-NOZBB32-NEXT: add a3, a3, a6
+; CHECK-ZVKB-NOZBB32-NEXT: xori a6, a2, 256
; CHECK-ZVKB-NOZBB32-NEXT: and a5, a5, a1
-; CHECK-ZVKB-NOZBB32-NEXT: or a6, a6, a2
+; CHECK-ZVKB-NOZBB32-NEXT: or a6, a6, a3
; CHECK-ZVKB-NOZBB32-NEXT: sw a5, 0(a4)
; CHECK-ZVKB-NOZBB32-NEXT: bnez a6, .LBB98_6
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_7: # %for.cond.cleanup
@@ -2385,9 +2385,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-NOZBB64-LABEL: vand_vx_loop_hoisted_not:
; CHECK-ZVKB-NOZBB64: # %bb.0: # %entry
; CHECK-ZVKB-NOZBB64-NEXT: csrr a4, vlenb
-; CHECK-ZVKB-NOZBB64-NEXT: srli a2, a4, 3
-; CHECK-ZVKB-NOZBB64-NEXT: li a3, 64
-; CHECK-ZVKB-NOZBB64-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-ZVKB-NOZBB64-NEXT: srli a3, a4, 3
+; CHECK-ZVKB-NOZBB64-NEXT: li a5, 64
+; CHECK-ZVKB-NOZBB64-NEXT: bgeu a5, a3, .LBB98_2
; CHECK-ZVKB-NOZBB64-NEXT: # %bb.1:
; CHECK-ZVKB-NOZBB64-NEXT: li a2, 0
; CHECK-ZVKB-NOZBB64-NEXT: j .LBB98_5
@@ -2427,18 +2427,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-ZBB32-LABEL: vand_vx_loop_hoisted_not:
; CHECK-ZVKB-ZBB32: # %bb.0: # %entry
; CHECK-ZVKB-ZBB32-NEXT: csrr a4, vlenb
-; CHECK-ZVKB-ZBB32-NEXT: srli a2, a4, 3
-; CHECK-ZVKB-ZBB32-NEXT: li a3, 64
-; CHECK-ZVKB-ZBB32-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-ZVKB-ZBB32-NEXT: srli a3, a4, 3
+; CHECK-ZVKB-ZBB32-NEXT: li a5, 64
+; CHECK-ZVKB-ZBB32-NEXT: bgeu a5, a3, .LBB98_2
; CHECK-ZVKB-ZBB32-NEXT: # %bb.1:
-; CHECK-ZVKB-ZBB32-NEXT: li a3, 0
; CHECK-ZVKB-ZBB32-NEXT: li a2, 0
+; CHECK-ZVKB-ZBB32-NEXT: li a3, 0
; CHECK-ZVKB-ZBB32-NEXT: j .LBB98_5
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_2: # %vector.ph
-; CHECK-ZVKB-ZBB32-NEXT: li a2, 0
+; CHECK-ZVKB-ZBB32-NEXT: li a3, 0
; CHECK-ZVKB-ZBB32-NEXT: srli a4, a4, 1
-; CHECK-ZVKB-ZBB32-NEXT: neg a3, a4
-; CHECK-ZVKB-ZBB32-NEXT: andi a3, a3, 256
+; CHECK-ZVKB-ZBB32-NEXT: neg a2, a4
+; CHECK-ZVKB-ZBB32-NEXT: andi a2, a2, 256
; CHECK-ZVKB-ZBB32-NEXT: li a6, 0
; CHECK-ZVKB-ZBB32-NEXT: li a5, 0
; CHECK-ZVKB-ZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2450,25 +2450,25 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-ZBB32-NEXT: vl2re32.v v8, (a7)
; CHECK-ZVKB-ZBB32-NEXT: sltu a6, t0, a6
; CHECK-ZVKB-ZBB32-NEXT: add a5, a5, a6
-; CHECK-ZVKB-ZBB32-NEXT: xor a6, t0, a3
+; CHECK-ZVKB-ZBB32-NEXT: xor a6, t0, a2
; CHECK-ZVKB-ZBB32-NEXT: vandn.vx v8, v8, a1
; CHECK-ZVKB-ZBB32-NEXT: or t1, a6, a5
; CHECK-ZVKB-ZBB32-NEXT: vs2r.v v8, (a7)
; CHECK-ZVKB-ZBB32-NEXT: mv a6, t0
; CHECK-ZVKB-ZBB32-NEXT: bnez t1, .LBB98_3
; CHECK-ZVKB-ZBB32-NEXT: # %bb.4: # %middle.block
-; CHECK-ZVKB-ZBB32-NEXT: bnez a3, .LBB98_6
+; CHECK-ZVKB-ZBB32-NEXT: bnez a2, .LBB98_6
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_5: # %for.body
; CHECK-ZVKB-ZBB32-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-ZVKB-ZBB32-NEXT: slli a4, a3, 2
-; CHECK-ZVKB-ZBB32-NEXT: addi a3, a3, 1
+; CHECK-ZVKB-ZBB32-NEXT: slli a4, a2, 2
+; CHECK-ZVKB-ZBB32-NEXT: addi a2, a2, 1
; CHECK-ZVKB-ZBB32-NEXT: add a4, a0, a4
; CHECK-ZVKB-ZBB32-NEXT: lw a5, 0(a4)
-; CHECK-ZVKB-ZBB32-NEXT: seqz a6, a3
-; CHECK-ZVKB-ZBB32-NEXT: add a2, a2, a6
-; CHECK-ZVKB-ZBB32-NEXT: xori a6, a3, 256
+; CHECK-ZVKB-ZBB32-NEXT: seqz a6, a2
+; CHECK-ZVKB-ZBB32-NEXT: add a3, a3, a6
+; CHECK-ZVKB-ZBB32-NEXT: xori a6, a2, 256
; CHECK-ZVKB-ZBB32-NEXT: andn a5, a5, a1
-; CHECK-ZVKB-ZBB32-NEXT: or a6, a6, a2
+; CHECK-ZVKB-ZBB32-NEXT: or a6, a6, a3
; CHECK-ZVKB-ZBB32-NEXT: sw a5, 0(a4)
; CHECK-ZVKB-ZBB32-NEXT: bnez a6, .LBB98_5
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_6: # %for.cond.cleanup
@@ -2477,9 +2477,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-ZBB64-LABEL: vand_vx_loop_hoisted_not:
; CHECK-ZVKB-ZBB64: # %bb.0: # %entry
; CHECK-ZVKB-ZBB64-NEXT: csrr a4, vlenb
-; CHECK-ZVKB-ZBB64-NEXT: srli a2, a4, 3
-; CHECK-ZVKB-ZBB64-NEXT: li a3, 64
-; CHECK-ZVKB-ZBB64-NEXT: bgeu a3, a2, .LBB98_2
+; CHECK-ZVKB-ZBB64-NEXT: srli a3, a4, 3
+; CHECK-ZVKB-ZBB64-NEXT: li a5, 64
+; CHECK-ZVKB-ZBB64-NEXT: bgeu a5, a3, .LBB98_2
; CHECK-ZVKB-ZBB64-NEXT: # %bb.1:
; CHECK-ZVKB-ZBB64-NEXT: li a2, 0
; CHECK-ZVKB-ZBB64-NEXT: j .LBB98_5
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
index 7990dfc0880a..9a0f27b50d41 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
@@ -86,14 +86,14 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV32-NEXT: # Child Loop BB0_15 Depth 2
; RV32-NEXT: beqz t1, .LBB0_12
; RV32-NEXT: # %bb.11: # in Loop: Header=BB0_10 Depth=1
-; RV32-NEXT: li t4, 0
; RV32-NEXT: li t3, 0
+; RV32-NEXT: li t4, 0
; RV32-NEXT: j .LBB0_15
; RV32-NEXT: .LBB0_12: # %vector.ph
; RV32-NEXT: # in Loop: Header=BB0_10 Depth=1
-; RV32-NEXT: li t3, 0
-; RV32-NEXT: neg t4, t2
-; RV32-NEXT: and t4, t4, a6
+; RV32-NEXT: li t4, 0
+; RV32-NEXT: neg t3, t2
+; RV32-NEXT: and t3, t3, a6
; RV32-NEXT: li t6, 0
; RV32-NEXT: li t5, 0
; RV32-NEXT: vsetvli s0, zero, e8, m2, ta, ma
@@ -108,7 +108,7 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV32-NEXT: add s1, t6, t2
; RV32-NEXT: sltu t6, s1, t6
; RV32-NEXT: add t5, t5, t6
-; RV32-NEXT: xor t6, s1, t4
+; RV32-NEXT: xor t6, s1, t3
; RV32-NEXT: vaaddu.vv v8, v8, v10
; RV32-NEXT: or s2, t6, t5
; RV32-NEXT: vs2r.v v8, (s0)
@@ -116,23 +116,23 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV32-NEXT: bnez s2, .LBB0_13
; RV32-NEXT: # %bb.14: # %middle.block
; RV32-NEXT: # in Loop: Header=BB0_10 Depth=1
-; RV32-NEXT: beq t4, a6, .LBB0_9
+; RV32-NEXT: beq t3, a6, .LBB0_9
; RV32-NEXT: .LBB0_15: # %for.body4.us
; RV32-NEXT: # Parent Loop BB0_10 Depth=1
; RV32-NEXT: # => This Inner Loop Header: Depth=2
-; RV32-NEXT: add t5, a2, t4
-; RV32-NEXT: add t6, a4, t4
-; RV32-NEXT: add s0, a0, t4
+; RV32-NEXT: add t5, a2, t3
+; RV32-NEXT: add t6, a4, t3
+; RV32-NEXT: add s0, a0, t3
; RV32-NEXT: lbu t5, 0(t5)
; RV32-NEXT: lbu t6, 0(t6)
-; RV32-NEXT: addi t4, t4, 1
-; RV32-NEXT: seqz s1, t4
-; RV32-NEXT: add t3, t3, s1
+; RV32-NEXT: addi t3, t3, 1
+; RV32-NEXT: seqz s1, t3
+; RV32-NEXT: add t4, t4, s1
; RV32-NEXT: add t5, t5, t6
-; RV32-NEXT: xor t6, t4, a6
+; RV32-NEXT: xor t6, t3, a6
; RV32-NEXT: addi t5, t5, 1
; RV32-NEXT: srli t5, t5, 1
-; RV32-NEXT: or t6, t6, t3
+; RV32-NEXT: or t6, t6, t4
; RV32-NEXT: sb t5, 0(s0)
; RV32-NEXT: bnez t6, .LBB0_15
; RV32-NEXT: j .LBB0_9
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
index 4066f62afad0..141b814d941f 100644
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -42,33 +42,35 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind {
; RV32I-NEXT: xori a1, a1, 123
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: mv a2, a3
-; RV32I-NEXT: beqz a1, .LBB1_2
+; RV32I-NEXT: bnez a1, .LBB1_6
; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: mv a2, a4
+; RV32I-NEXT: addi a5, a3, 4
+; RV32I-NEXT: bnez a1, .LBB1_7
; RV32I-NEXT: .LBB1_2: # %entry
-; RV32I-NEXT: beqz a1, .LBB1_5
-; RV32I-NEXT: # %bb.3: # %entry
-; RV32I-NEXT: addi a5, a4, 4
-; RV32I-NEXT: bnez a1, .LBB1_6
-; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: addi a6, a3, 8
-; RV32I-NEXT: j .LBB1_7
-; RV32I-NEXT: .LBB1_5:
-; RV32I-NEXT: addi a5, a3, 4
; RV32I-NEXT: beqz a1, .LBB1_4
-; RV32I-NEXT: .LBB1_6: # %entry
+; RV32I-NEXT: .LBB1_3: # %entry
; RV32I-NEXT: addi a6, a4, 8
-; RV32I-NEXT: .LBB1_7: # %entry
+; RV32I-NEXT: .LBB1_4: # %entry
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a5, 0(a5)
; RV32I-NEXT: lw a6, 0(a6)
-; RV32I-NEXT: beqz a1, .LBB1_9
-; RV32I-NEXT: # %bb.8: # %entry
+; RV32I-NEXT: beqz a1, .LBB1_8
+; RV32I-NEXT: # %bb.5: # %entry
; RV32I-NEXT: addi a3, a4, 12
-; RV32I-NEXT: j .LBB1_10
-; RV32I-NEXT: .LBB1_9:
+; RV32I-NEXT: j .LBB1_9
+; RV32I-NEXT: .LBB1_6: # %entry
+; RV32I-NEXT: mv a2, a4
+; RV32I-NEXT: addi a5, a3, 4
+; RV32I-NEXT: beqz a1, .LBB1_2
+; RV32I-NEXT: .LBB1_7: # %entry
+; RV32I-NEXT: addi a5, a4, 4
+; RV32I-NEXT: addi a6, a3, 8
+; RV32I-NEXT: bnez a1, .LBB1_3
+; RV32I-NEXT: j .LBB1_4
+; RV32I-NEXT: .LBB1_8:
; RV32I-NEXT: addi a3, a3, 12
-; RV32I-NEXT: .LBB1_10: # %entry
+; RV32I-NEXT: .LBB1_9: # %entry
; RV32I-NEXT: lw a1, 0(a3)
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
@@ -125,33 +127,35 @@ define i128 @cmov128(i1 %a, i128 %b, i128 %c) nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: mv a4, a2
-; RV32I-NEXT: bnez a1, .LBB3_2
+; RV32I-NEXT: beqz a1, .LBB3_6
; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: mv a4, a3
+; RV32I-NEXT: addi a5, a2, 4
+; RV32I-NEXT: beqz a1, .LBB3_7
; RV32I-NEXT: .LBB3_2: # %entry
-; RV32I-NEXT: bnez a1, .LBB3_5
-; RV32I-NEXT: # %bb.3: # %entry
-; RV32I-NEXT: addi a5, a3, 4
-; RV32I-NEXT: beqz a1, .LBB3_6
-; RV32I-NEXT: .LBB3_4:
; RV32I-NEXT: addi a6, a2, 8
-; RV32I-NEXT: j .LBB3_7
-; RV32I-NEXT: .LBB3_5:
-; RV32I-NEXT: addi a5, a2, 4
; RV32I-NEXT: bnez a1, .LBB3_4
-; RV32I-NEXT: .LBB3_6: # %entry
+; RV32I-NEXT: .LBB3_3: # %entry
; RV32I-NEXT: addi a6, a3, 8
-; RV32I-NEXT: .LBB3_7: # %entry
+; RV32I-NEXT: .LBB3_4: # %entry
; RV32I-NEXT: lw a4, 0(a4)
; RV32I-NEXT: lw a5, 0(a5)
; RV32I-NEXT: lw a6, 0(a6)
-; RV32I-NEXT: bnez a1, .LBB3_9
-; RV32I-NEXT: # %bb.8: # %entry
+; RV32I-NEXT: bnez a1, .LBB3_8
+; RV32I-NEXT: # %bb.5: # %entry
; RV32I-NEXT: addi a2, a3, 12
-; RV32I-NEXT: j .LBB3_10
-; RV32I-NEXT: .LBB3_9:
+; RV32I-NEXT: j .LBB3_9
+; RV32I-NEXT: .LBB3_6: # %entry
+; RV32I-NEXT: mv a4, a3
+; RV32I-NEXT: addi a5, a2, 4
+; RV32I-NEXT: bnez a1, .LBB3_2
+; RV32I-NEXT: .LBB3_7: # %entry
+; RV32I-NEXT: addi a5, a3, 4
+; RV32I-NEXT: addi a6, a2, 8
+; RV32I-NEXT: beqz a1, .LBB3_3
+; RV32I-NEXT: j .LBB3_4
+; RV32I-NEXT: .LBB3_8:
; RV32I-NEXT: addi a2, a2, 12
-; RV32I-NEXT: .LBB3_10: # %entry
+; RV32I-NEXT: .LBB3_9: # %entry
; RV32I-NEXT: lw a1, 0(a2)
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index b155feab9b4d..40663912b72d 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -1032,19 +1032,17 @@ bb7: ; preds = %bb2
define signext i32 @bug(i32 signext %x) {
; CHECK-LABEL: bug:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: beqz a0, .LBB18_5
+; CHECK-NEXT: beqz a0, .LBB18_4
; CHECK-NEXT: # %bb.1: # %if.end
-; CHECK-NEXT: srliw a1, a0, 16
-; CHECK-NEXT: seqz a2, a1
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: sllw a0, a0, a2
-; CHECK-NEXT: beqz a1, .LBB18_3
+; CHECK-NEXT: srliw a2, a0, 16
+; CHECK-NEXT: seqz a1, a2
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: li a1, 16
+; CHECK-NEXT: beqz a2, .LBB18_3
; CHECK-NEXT: # %bb.2: # %if.end
; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: j .LBB18_4
-; CHECK-NEXT: .LBB18_3:
-; CHECK-NEXT: li a1, 16
-; CHECK-NEXT: .LBB18_4: # %if.end
+; CHECK-NEXT: .LBB18_3: # %if.end
; CHECK-NEXT: srliw a2, a0, 24
; CHECK-NEXT: seqz a2, a2
; CHECK-NEXT: slli a3, a2, 3
@@ -1069,24 +1067,22 @@ define signext i32 @bug(i32 signext %x) {
; CHECK-NEXT: not a0, a0
; CHECK-NEXT: srli a0, a0, 31
; CHECK-NEXT: addw a0, a1, a0
-; CHECK-NEXT: .LBB18_5: # %cleanup
+; CHECK-NEXT: .LBB18_4: # %cleanup
; CHECK-NEXT: ret
;
; NOREMOVAL-LABEL: bug:
; NOREMOVAL: # %bb.0: # %entry
-; NOREMOVAL-NEXT: beqz a0, .LBB18_5
+; NOREMOVAL-NEXT: beqz a0, .LBB18_4
; NOREMOVAL-NEXT: # %bb.1: # %if.end
-; NOREMOVAL-NEXT: srliw a1, a0, 16
-; NOREMOVAL-NEXT: seqz a2, a1
-; NOREMOVAL-NEXT: slli a2, a2, 4
-; NOREMOVAL-NEXT: sllw a0, a0, a2
-; NOREMOVAL-NEXT: beqz a1, .LBB18_3
+; NOREMOVAL-NEXT: srliw a2, a0, 16
+; NOREMOVAL-NEXT: seqz a1, a2
+; NOREMOVAL-NEXT: slli a1, a1, 4
+; NOREMOVAL-NEXT: sllw a0, a0, a1
+; NOREMOVAL-NEXT: li a1, 16
+; NOREMOVAL-NEXT: beqz a2, .LBB18_3
; NOREMOVAL-NEXT: # %bb.2: # %if.end
; NOREMOVAL-NEXT: li a1, 32
-; NOREMOVAL-NEXT: j .LBB18_4
-; NOREMOVAL-NEXT: .LBB18_3:
-; NOREMOVAL-NEXT: li a1, 16
-; NOREMOVAL-NEXT: .LBB18_4: # %if.end
+; NOREMOVAL-NEXT: .LBB18_3: # %if.end
; NOREMOVAL-NEXT: srliw a2, a0, 24
; NOREMOVAL-NEXT: seqz a2, a2
; NOREMOVAL-NEXT: slli a3, a2, 3
@@ -1111,7 +1107,7 @@ define signext i32 @bug(i32 signext %x) {
; NOREMOVAL-NEXT: not a0, a0
; NOREMOVAL-NEXT: srli a0, a0, 31
; NOREMOVAL-NEXT: addw a0, a1, a0
-; NOREMOVAL-NEXT: .LBB18_5: # %cleanup
+; NOREMOVAL-NEXT: .LBB18_4: # %cleanup
; NOREMOVAL-NEXT: ret
entry:
%tobool.not = icmp eq i32 %x, 0
diff --git a/llvm/test/CodeGen/RISCV/simplify-condbr.ll b/llvm/test/CodeGen/RISCV/simplify-condbr.ll
index 6dabd7d93cbc..4e3940fd2fb5 100644
--- a/llvm/test/CodeGen/RISCV/simplify-condbr.ll
+++ b/llvm/test/CodeGen/RISCV/simplify-condbr.ll
@@ -112,21 +112,21 @@ if.end1497: ; preds = %if.else1492, %sw.ep
define ptr @Perl_pp_refassign(ptr %PL_stack_sp, i1 %tobool.not, i1 %tobool3.not, i1 %cond1) nounwind {
; CHECK-LABEL: Perl_pp_refassign:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: andi a1, a1, 1
-; CHECK-NEXT: beqz a1, .LBB1_3
+; CHECK-NEXT: andi a3, a1, 1
+; CHECK-NEXT: beqz a3, .LBB1_3
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0
-; CHECK-NEXT: andi a2, a2, 1
-; CHECK-NEXT: bnez a2, .LBB1_4
+; CHECK-NEXT: andi a3, a2, 1
+; CHECK-NEXT: bnez a3, .LBB1_4
; CHECK-NEXT: .LBB1_2: # %cond.true4
; CHECK-NEXT: ld a0, 0(a0)
-; CHECK-NEXT: snez a0, a0
-; CHECK-NEXT: bnez a0, .LBB1_5
+; CHECK-NEXT: snez a2, a0
+; CHECK-NEXT: bnez a2, .LBB1_5
; CHECK-NEXT: j .LBB1_6
; CHECK-NEXT: .LBB1_3: # %cond.true
; CHECK-NEXT: ld a1, 0(a0)
-; CHECK-NEXT: andi a2, a2, 1
-; CHECK-NEXT: beqz a2, .LBB1_2
+; CHECK-NEXT: andi a3, a2, 1
+; CHECK-NEXT: beqz a3, .LBB1_2
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: j .LBB1_6
; CHECK-NEXT: .LBB1_5: # %sw.bb85
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:46:10 +0000