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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vwmul.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vwmul.ll60
1 files changed, 30 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul.ll
index 3c8b6c8c4b56..c1dad7f66214 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmul.ll
@@ -19,7 +19,7 @@ define <vscale x 1 x i16> @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen %2)
@@ -67,7 +67,7 @@ define <vscale x 2 x i16> @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen %2)
@@ -115,7 +115,7 @@ define <vscale x 4 x i16> @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen %2)
@@ -164,7 +164,7 @@ define <vscale x 8 x i16> @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen %2)
@@ -213,7 +213,7 @@ define <vscale x 16 x i16> @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen %2)
@@ -262,7 +262,7 @@ define <vscale x 32 x i16> @intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen %2)
@@ -310,7 +310,7 @@ define <vscale x 1 x i32> @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen %2)
@@ -358,7 +358,7 @@ define <vscale x 2 x i32> @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen %2)
@@ -407,7 +407,7 @@ define <vscale x 4 x i32> @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen %2)
@@ -456,7 +456,7 @@ define <vscale x 8 x i32> @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen %2)
@@ -505,7 +505,7 @@ define <vscale x 16 x i32> @intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16(<vscal
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen %2)
@@ -553,7 +553,7 @@ define <vscale x 1 x i64> @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen %2)
@@ -602,7 +602,7 @@ define <vscale x 2 x i64> @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2)
@@ -651,7 +651,7 @@ define <vscale x 4 x i64> @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen %2)
@@ -700,7 +700,7 @@ define <vscale x 8 x i64> @intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen %2)
@@ -748,7 +748,7 @@ define <vscale x 1 x i16> @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i8> %0,
i8 %1,
iXLen %2)
@@ -796,7 +796,7 @@ define <vscale x 2 x i16> @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i8> %0,
i8 %1,
iXLen %2)
@@ -844,7 +844,7 @@ define <vscale x 4 x i16> @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i8> %0,
i8 %1,
iXLen %2)
@@ -892,7 +892,7 @@ define <vscale x 8 x i16> @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i8> %0,
i8 %1,
iXLen %2)
@@ -940,7 +940,7 @@ define <vscale x 16 x i16> @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8(<vscale x 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i8> %0,
i8 %1,
iXLen %2)
@@ -988,7 +988,7 @@ define <vscale x 32 x i16> @intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8(<vscale x 32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i8> %0,
i8 %1,
iXLen %2)
@@ -1036,7 +1036,7 @@ define <vscale x 1 x i32> @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i16> %0,
i16 %1,
iXLen %2)
@@ -1084,7 +1084,7 @@ define <vscale x 2 x i32> @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i16> %0,
i16 %1,
iXLen %2)
@@ -1132,7 +1132,7 @@ define <vscale x 4 x i32> @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i16> %0,
i16 %1,
iXLen %2)
@@ -1180,7 +1180,7 @@ define <vscale x 8 x i32> @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i16> %0,
i16 %1,
iXLen %2)
@@ -1228,7 +1228,7 @@ define <vscale x 16 x i32> @intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i16> %0,
i16 %1,
iXLen %2)
@@ -1276,7 +1276,7 @@ define <vscale x 1 x i64> @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i32> %0,
i32 %1,
iXLen %2)
@@ -1324,7 +1324,7 @@ define <vscale x 2 x i64> @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i32> %0,
i32 %1,
iXLen %2)
@@ -1372,7 +1372,7 @@ define <vscale x 4 x i64> @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i32> %0,
i32 %1,
iXLen %2)
@@ -1420,7 +1420,7 @@ define <vscale x 8 x i64> @intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i32> %0,
i32 %1,
iXLen %2)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:55:05 +0000