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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vsmul.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vsmul.ll88
1 files changed, 44 insertions, 44 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul.ll
index 8592f01cdfbb..0b56a54f08a8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsmul.ll
@@ -23,7 +23,7 @@ define <vscale x 1 x i8> @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen 0, iXLen %2)
@@ -71,7 +71,7 @@ define <vscale x 2 x i8> @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen 0, iXLen %2)
@@ -119,7 +119,7 @@ define <vscale x 4 x i8> @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen 0, iXLen %2)
@@ -167,7 +167,7 @@ define <vscale x 8 x i8> @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen 0, iXLen %2)
@@ -215,7 +215,7 @@ define <vscale x 16 x i8> @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen 0, iXLen %2)
@@ -263,7 +263,7 @@ define <vscale x 32 x i8> @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsmul.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen 0, iXLen %2)
@@ -311,7 +311,7 @@ define <vscale x 64 x i8> @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsmul.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
iXLen 0, iXLen %2)
@@ -360,7 +360,7 @@ define <vscale x 1 x i16> @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsmul.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen 0, iXLen %2)
@@ -408,7 +408,7 @@ define <vscale x 2 x i16> @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsmul.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen 0, iXLen %2)
@@ -456,7 +456,7 @@ define <vscale x 4 x i16> @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsmul.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen 0, iXLen %2)
@@ -504,7 +504,7 @@ define <vscale x 8 x i16> @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsmul.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen 0, iXLen %2)
@@ -552,7 +552,7 @@ define <vscale x 16 x i16> @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16(<vscal
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsmul.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen 0, iXLen %2)
@@ -600,7 +600,7 @@ define <vscale x 32 x i16> @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16(<vscal
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsmul.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
iXLen 0, iXLen %2)
@@ -649,7 +649,7 @@ define <vscale x 1 x i32> @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsmul.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen 0, iXLen %2)
@@ -697,7 +697,7 @@ define <vscale x 2 x i32> @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsmul.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen 0, iXLen %2)
@@ -745,7 +745,7 @@ define <vscale x 4 x i32> @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen 0, iXLen %2)
@@ -793,7 +793,7 @@ define <vscale x 8 x i32> @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsmul.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen 0, iXLen %2)
@@ -841,7 +841,7 @@ define <vscale x 16 x i32> @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32(<vscal
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsmul.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
iXLen 0, iXLen %2)
@@ -890,7 +890,7 @@ define <vscale x 1 x i64> @intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
iXLen 0, iXLen %2)
@@ -938,7 +938,7 @@ define <vscale x 2 x i64> @intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
iXLen 0, iXLen %2)
@@ -986,7 +986,7 @@ define <vscale x 4 x i64> @intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
iXLen 0, iXLen %2)
@@ -1034,7 +1034,7 @@ define <vscale x 8 x i64> @intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
iXLen 0, iXLen %2)
@@ -1083,7 +1083,7 @@ define <vscale x 1 x i8> @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
i8 %1,
iXLen 0, iXLen %2)
@@ -1131,7 +1131,7 @@ define <vscale x 2 x i8> @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
i8 %1,
iXLen 0, iXLen %2)
@@ -1179,7 +1179,7 @@ define <vscale x 4 x i8> @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
i8 %1,
iXLen 0, iXLen %2)
@@ -1227,7 +1227,7 @@ define <vscale x 8 x i8> @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
i8 %1,
iXLen 0, iXLen %2)
@@ -1275,7 +1275,7 @@ define <vscale x 16 x i8> @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
i8 %1,
iXLen 0, iXLen %2)
@@ -1323,7 +1323,7 @@ define <vscale x 32 x i8> @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsmul.nxv32i8.i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
i8 %1,
iXLen 0, iXLen %2)
@@ -1371,7 +1371,7 @@ define <vscale x 64 x i8> @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsmul.nxv64i8.i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
i8 %1,
iXLen 0, iXLen %2)
@@ -1419,7 +1419,7 @@ define <vscale x 1 x i16> @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsmul.nxv1i16.i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
i16 %1,
iXLen 0, iXLen %2)
@@ -1467,7 +1467,7 @@ define <vscale x 2 x i16> @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsmul.nxv2i16.i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
i16 %1,
iXLen 0, iXLen %2)
@@ -1515,7 +1515,7 @@ define <vscale x 4 x i16> @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsmul.nxv4i16.i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
i16 %1,
iXLen 0, iXLen %2)
@@ -1563,7 +1563,7 @@ define <vscale x 8 x i16> @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsmul.nxv8i16.i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
i16 %1,
iXLen 0, iXLen %2)
@@ -1611,7 +1611,7 @@ define <vscale x 16 x i16> @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsmul.nxv16i16.i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
i16 %1,
iXLen 0, iXLen %2)
@@ -1659,7 +1659,7 @@ define <vscale x 32 x i16> @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16(<vscale x 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsmul.nxv32i16.i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
i16 %1,
iXLen 0, iXLen %2)
@@ -1707,7 +1707,7 @@ define <vscale x 1 x i32> @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsmul.nxv1i32.i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
i32 %1,
iXLen 0, iXLen %2)
@@ -1755,7 +1755,7 @@ define <vscale x 2 x i32> @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsmul.nxv2i32.i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
i32 %1,
iXLen 0, iXLen %2)
@@ -1803,7 +1803,7 @@ define <vscale x 4 x i32> @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
i32 %1,
iXLen 0, iXLen %2)
@@ -1851,7 +1851,7 @@ define <vscale x 8 x i32> @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsmul.nxv8i32.i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
i32 %1,
iXLen 0, iXLen %2)
@@ -1899,7 +1899,7 @@ define <vscale x 16 x i32> @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsmul.nxv16i32.i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
i32 %1,
iXLen 0, iXLen %2)
@@ -1960,7 +1960,7 @@ define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 %1,
iXLen 0, iXLen %2)
@@ -2034,7 +2034,7 @@ define <vscale x 2 x i64> @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
i64 %1,
iXLen 0, iXLen %2)
@@ -2108,7 +2108,7 @@ define <vscale x 4 x i64> @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
i64 %1,
iXLen 0, iXLen %2)
@@ -2182,7 +2182,7 @@ define <vscale x 8 x i64> @intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
i64 %1,
iXLen 0, iXLen %2)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:55:07 +0000