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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vrsub.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vrsub.ll88
1 files changed, 44 insertions, 44 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub.ll
index 19d6afbd0e57..bab0e8fa0bff 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrsub.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrsub.ll
@@ -18,7 +18,7 @@ define <vscale x 1 x i8> @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
i8 %1,
iXLen %2)
@@ -64,7 +64,7 @@ define <vscale x 2 x i8> @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
i8 %1,
iXLen %2)
@@ -110,7 +110,7 @@ define <vscale x 4 x i8> @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
i8 %1,
iXLen %2)
@@ -156,7 +156,7 @@ define <vscale x 8 x i8> @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
i8 %1,
iXLen %2)
@@ -202,7 +202,7 @@ define <vscale x 16 x i8> @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
i8 %1,
iXLen %2)
@@ -248,7 +248,7 @@ define <vscale x 32 x i8> @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
i8 %1,
iXLen %2)
@@ -294,7 +294,7 @@ define <vscale x 64 x i8> @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
i8 %1,
iXLen %2)
@@ -340,7 +340,7 @@ define <vscale x 1 x i16> @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
i16 %1,
iXLen %2)
@@ -386,7 +386,7 @@ define <vscale x 2 x i16> @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
i16 %1,
iXLen %2)
@@ -432,7 +432,7 @@ define <vscale x 4 x i16> @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
i16 %1,
iXLen %2)
@@ -478,7 +478,7 @@ define <vscale x 8 x i16> @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
i16 %1,
iXLen %2)
@@ -524,7 +524,7 @@ define <vscale x 16 x i16> @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
i16 %1,
iXLen %2)
@@ -570,7 +570,7 @@ define <vscale x 32 x i16> @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16(<vscale x 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
i16 %1,
iXLen %2)
@@ -616,7 +616,7 @@ define <vscale x 1 x i32> @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
i32 %1,
iXLen %2)
@@ -662,7 +662,7 @@ define <vscale x 2 x i32> @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
i32 %1,
iXLen %2)
@@ -708,7 +708,7 @@ define <vscale x 4 x i32> @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
i32 %1,
iXLen %2)
@@ -754,7 +754,7 @@ define <vscale x 8 x i32> @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
i32 %1,
iXLen %2)
@@ -800,7 +800,7 @@ define <vscale x 16 x i32> @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
i32 %1,
iXLen %2)
@@ -858,7 +858,7 @@ define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 %1,
iXLen %2)
@@ -928,7 +928,7 @@ define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
i64 %1,
iXLen %2)
@@ -998,7 +998,7 @@ define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
i64 %1,
iXLen %2)
@@ -1068,7 +1068,7 @@ define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x
; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
i64 %1,
iXLen %2)
@@ -1120,7 +1120,7 @@ define <vscale x 1 x i8> @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
i8 9,
iXLen %1)
@@ -1153,7 +1153,7 @@ define <vscale x 2 x i8> @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
i8 9,
iXLen %1)
@@ -1186,7 +1186,7 @@ define <vscale x 4 x i8> @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
i8 9,
iXLen %1)
@@ -1219,7 +1219,7 @@ define <vscale x 8 x i8> @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
i8 9,
iXLen %1)
@@ -1252,7 +1252,7 @@ define <vscale x 16 x i8> @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
i8 9,
iXLen %1)
@@ -1285,7 +1285,7 @@ define <vscale x 32 x i8> @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
i8 9,
iXLen %1)
@@ -1318,7 +1318,7 @@ define <vscale x 64 x i8> @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
i8 9,
iXLen %1)
@@ -1351,7 +1351,7 @@ define <vscale x 1 x i16> @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
i16 9,
iXLen %1)
@@ -1384,7 +1384,7 @@ define <vscale x 2 x i16> @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
i16 9,
iXLen %1)
@@ -1417,7 +1417,7 @@ define <vscale x 4 x i16> @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
i16 9,
iXLen %1)
@@ -1450,7 +1450,7 @@ define <vscale x 8 x i16> @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
i16 9,
iXLen %1)
@@ -1483,7 +1483,7 @@ define <vscale x 16 x i16> @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
i16 9,
iXLen %1)
@@ -1516,7 +1516,7 @@ define <vscale x 32 x i16> @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16(<vscale x 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
i16 9,
iXLen %1)
@@ -1549,7 +1549,7 @@ define <vscale x 1 x i32> @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
i32 9,
iXLen %1)
@@ -1582,7 +1582,7 @@ define <vscale x 2 x i32> @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
i32 9,
iXLen %1)
@@ -1615,7 +1615,7 @@ define <vscale x 4 x i32> @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
i32 9,
iXLen %1)
@@ -1648,7 +1648,7 @@ define <vscale x 8 x i32> @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
i32 9,
iXLen %1)
@@ -1681,7 +1681,7 @@ define <vscale x 16 x i32> @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
i32 9,
iXLen %1)
@@ -1714,7 +1714,7 @@ define <vscale x 1 x i64> @intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 9,
iXLen %1)
@@ -1747,7 +1747,7 @@ define <vscale x 2 x i64> @intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
i64 9,
iXLen %1)
@@ -1780,7 +1780,7 @@ define <vscale x 4 x i64> @intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
i64 9,
iXLen %1)
@@ -1813,7 +1813,7 @@ define <vscale x 8 x i64> @intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
i64 9,
iXLen %1)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:55:03 +0000