summaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/RISCV/rvv/vror.ll
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vror.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vror.ll132
1 files changed, 66 insertions, 66 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vror.ll b/llvm/test/CodeGen/RISCV/rvv/vror.ll
index 1e8fa86119b6..4e5734310dae 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vror.ll
@@ -18,7 +18,7 @@ define <vscale x 1 x i8> @intrinsic_vror_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0,
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen %2)
@@ -65,7 +65,7 @@ define <vscale x 2 x i8> @intrinsic_vror_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0,
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen %2)
@@ -112,7 +112,7 @@ define <vscale x 4 x i8> @intrinsic_vror_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0,
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen %2)
@@ -159,7 +159,7 @@ define <vscale x 8 x i8> @intrinsic_vror_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0,
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen %2)
@@ -206,7 +206,7 @@ define <vscale x 16 x i8> @intrinsic_vror_vv_nxv16i8_nxv16i8(<vscale x 16 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen %2)
@@ -253,7 +253,7 @@ define <vscale x 32 x i8> @intrinsic_vror_vv_nxv32i8_nxv32i8(<vscale x 32 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vror.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen %2)
@@ -300,7 +300,7 @@ define <vscale x 64 x i8> @intrinsic_vror_vv_nxv64i8_nxv64i8(<vscale x 64 x i8>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vror.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
iXLen %2)
@@ -348,7 +348,7 @@ define <vscale x 1 x i16> @intrinsic_vror_vv_nxv1i16_nxv1i16(<vscale x 1 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vror.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen %2)
@@ -395,7 +395,7 @@ define <vscale x 2 x i16> @intrinsic_vror_vv_nxv2i16_nxv2i16(<vscale x 2 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vror.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen %2)
@@ -442,7 +442,7 @@ define <vscale x 4 x i16> @intrinsic_vror_vv_nxv4i16_nxv4i16(<vscale x 4 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vror.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen %2)
@@ -489,7 +489,7 @@ define <vscale x 8 x i16> @intrinsic_vror_vv_nxv8i16_nxv8i16(<vscale x 8 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vror.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen %2)
@@ -536,7 +536,7 @@ define <vscale x 16 x i16> @intrinsic_vror_vv_nxv16i16_nxv16i16(<vscale x 16 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vror.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen %2)
@@ -583,7 +583,7 @@ define <vscale x 32 x i16> @intrinsic_vror_vv_nxv32i16_nxv32i16(<vscale x 32 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vror.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
iXLen %2)
@@ -631,7 +631,7 @@ define <vscale x 1 x i32> @intrinsic_vror_vv_nxv1i32_nxv1i32(<vscale x 1 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vror.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen %2)
@@ -678,7 +678,7 @@ define <vscale x 2 x i32> @intrinsic_vror_vv_nxv2i32_nxv2i32(<vscale x 2 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vror.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2)
@@ -725,7 +725,7 @@ define <vscale x 4 x i32> @intrinsic_vror_vv_nxv4i32_nxv4i32(<vscale x 4 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen %2)
@@ -772,7 +772,7 @@ define <vscale x 8 x i32> @intrinsic_vror_vv_nxv8i32_nxv8i32(<vscale x 8 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vror.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen %2)
@@ -819,7 +819,7 @@ define <vscale x 16 x i32> @intrinsic_vror_vv_nxv16i32_nxv16i32(<vscale x 16 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vror.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
iXLen %2)
@@ -867,7 +867,7 @@ define <vscale x 1 x i64> @intrinsic_vror_vv_nxv1i64_nxv1i64(<vscale x 1 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vror.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
iXLen %2)
@@ -914,7 +914,7 @@ define <vscale x 2 x i64> @intrinsic_vror_vv_nxv2i64_nxv2i64(<vscale x 2 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vror.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
iXLen %2)
@@ -961,7 +961,7 @@ define <vscale x 4 x i64> @intrinsic_vror_vv_nxv4i64_nxv4i64(<vscale x 4 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vror.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
iXLen %2)
@@ -1008,7 +1008,7 @@ define <vscale x 8 x i64> @intrinsic_vror_vv_nxv8i64_nxv8i64(<vscale x 8 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vror.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
iXLen %2)
@@ -1056,7 +1056,7 @@ define <vscale x 1 x i8> @intrinsic_vror_vx_nxv1i8(<vscale x 1 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
iXLen %1,
iXLen %2)
@@ -1103,7 +1103,7 @@ define <vscale x 2 x i8> @intrinsic_vror_vx_nxv2i8(<vscale x 2 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
iXLen %1,
iXLen %2)
@@ -1150,7 +1150,7 @@ define <vscale x 4 x i8> @intrinsic_vror_vx_nxv4i8(<vscale x 4 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
iXLen %1,
iXLen %2)
@@ -1197,7 +1197,7 @@ define <vscale x 8 x i8> @intrinsic_vror_vx_nxv8i8(<vscale x 8 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
iXLen %1,
iXLen %2)
@@ -1244,7 +1244,7 @@ define <vscale x 16 x i8> @intrinsic_vror_vx_nxv16i8(<vscale x 16 x i8> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
iXLen %1,
iXLen %2)
@@ -1291,7 +1291,7 @@ define <vscale x 32 x i8> @intrinsic_vror_vx_nxv32i8(<vscale x 32 x i8> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vror.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
iXLen %1,
iXLen %2)
@@ -1338,7 +1338,7 @@ define <vscale x 64 x i8> @intrinsic_vror_vx_nxv64i8(<vscale x 64 x i8> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vror.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
iXLen %1,
iXLen %2)
@@ -1385,7 +1385,7 @@ define <vscale x 1 x i16> @intrinsic_vror_vx_nxv1i16(<vscale x 1 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vror.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
iXLen %1,
iXLen %2)
@@ -1432,7 +1432,7 @@ define <vscale x 2 x i16> @intrinsic_vror_vx_nxv2i16(<vscale x 2 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vror.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
iXLen %1,
iXLen %2)
@@ -1479,7 +1479,7 @@ define <vscale x 4 x i16> @intrinsic_vror_vx_nxv4i16(<vscale x 4 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vror.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
iXLen %1,
iXLen %2)
@@ -1526,7 +1526,7 @@ define <vscale x 8 x i16> @intrinsic_vror_vx_nxv8i16(<vscale x 8 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vror.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
iXLen %1,
iXLen %2)
@@ -1573,7 +1573,7 @@ define <vscale x 16 x i16> @intrinsic_vror_vx_nxv16i16(<vscale x 16 x i16> %0, i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vror.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
iXLen %1,
iXLen %2)
@@ -1620,7 +1620,7 @@ define <vscale x 32 x i16> @intrinsic_vror_vx_nxv32i16(<vscale x 32 x i16> %0, i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vror.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
iXLen %1,
iXLen %2)
@@ -1667,7 +1667,7 @@ define <vscale x 1 x i32> @intrinsic_vror_vx_nxv1i32(<vscale x 1 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vror.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1714,7 +1714,7 @@ define <vscale x 2 x i32> @intrinsic_vror_vx_nxv2i32(<vscale x 2 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vror.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1761,7 +1761,7 @@ define <vscale x 4 x i32> @intrinsic_vror_vx_nxv4i32(<vscale x 4 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1808,7 +1808,7 @@ define <vscale x 8 x i32> @intrinsic_vror_vx_nxv8i32(<vscale x 8 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vror.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1855,7 +1855,7 @@ define <vscale x 16 x i32> @intrinsic_vror_vx_nxv16i32(<vscale x 16 x i32> %0, i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vror.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1902,7 +1902,7 @@ define <vscale x 1 x i64> @intrinsic_vror_vx_nxv1i64(<vscale x 1 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vror.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
iXLen %1,
iXLen %2)
@@ -1949,7 +1949,7 @@ define <vscale x 2 x i64> @intrinsic_vror_vx_nxv2i64(<vscale x 2 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vror.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
iXLen %1,
iXLen %2)
@@ -1996,7 +1996,7 @@ define <vscale x 4 x i64> @intrinsic_vror_vx_nxv4i64(<vscale x 4 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vror.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
iXLen %1,
iXLen %2)
@@ -2043,7 +2043,7 @@ define <vscale x 8 x i64> @intrinsic_vror_vx_nxv8i64(<vscale x 8 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vror.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
iXLen %1,
iXLen %2)
@@ -2084,7 +2084,7 @@ define <vscale x 1 x i8> @intrinsic_vror_vi_nxv1i8(<vscale x 1 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vror.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
iXLen 2,
iXLen %1)
@@ -2117,7 +2117,7 @@ define <vscale x 2 x i8> @intrinsic_vror_vi_nxv2i8(<vscale x 2 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vror.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
iXLen 2,
iXLen %1)
@@ -2150,7 +2150,7 @@ define <vscale x 4 x i8> @intrinsic_vror_vi_nxv4i8(<vscale x 4 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vror.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
iXLen 2,
iXLen %1)
@@ -2183,7 +2183,7 @@ define <vscale x 8 x i8> @intrinsic_vror_vi_nxv8i8(<vscale x 8 x i8> %0, iXLen %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vror.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
iXLen 2,
iXLen %1)
@@ -2216,7 +2216,7 @@ define <vscale x 16 x i8> @intrinsic_vror_vi_nxv16i8(<vscale x 16 x i8> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vror.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
iXLen 2,
iXLen %1)
@@ -2249,7 +2249,7 @@ define <vscale x 32 x i8> @intrinsic_vror_vi_nxv32i8(<vscale x 32 x i8> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vror.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
iXLen 2,
iXLen %1)
@@ -2282,7 +2282,7 @@ define <vscale x 64 x i8> @intrinsic_vror_vi_nxv64i8(<vscale x 64 x i8> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vror.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
iXLen 2,
iXLen %1)
@@ -2315,7 +2315,7 @@ define <vscale x 1 x i16> @intrinsic_vror_vi_nxv1i16(<vscale x 1 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vror.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
iXLen 2,
iXLen %1)
@@ -2348,7 +2348,7 @@ define <vscale x 2 x i16> @intrinsic_vror_vi_nxv2i16(<vscale x 2 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vror.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
iXLen 2,
iXLen %1)
@@ -2381,7 +2381,7 @@ define <vscale x 4 x i16> @intrinsic_vror_vi_nxv4i16(<vscale x 4 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vror.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
iXLen 2,
iXLen %1)
@@ -2414,7 +2414,7 @@ define <vscale x 8 x i16> @intrinsic_vror_vi_nxv8i16(<vscale x 8 x i16> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vror.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
iXLen 2,
iXLen %1)
@@ -2447,7 +2447,7 @@ define <vscale x 16 x i16> @intrinsic_vror_vi_nxv16i16(<vscale x 16 x i16> %0, i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vror.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
iXLen 2,
iXLen %1)
@@ -2480,7 +2480,7 @@ define <vscale x 32 x i16> @intrinsic_vror_vi_nxv32i16(<vscale x 32 x i16> %0, i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vror.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
iXLen 2,
iXLen %1)
@@ -2513,7 +2513,7 @@ define <vscale x 1 x i32> @intrinsic_vror_vi_nxv1i32(<vscale x 1 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vror.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
iXLen 2,
iXLen %1)
@@ -2546,7 +2546,7 @@ define <vscale x 2 x i32> @intrinsic_vror_vi_nxv2i32(<vscale x 2 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vror.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
iXLen 2,
iXLen %1)
@@ -2579,7 +2579,7 @@ define <vscale x 4 x i32> @intrinsic_vror_vi_nxv4i32(<vscale x 4 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vror.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
iXLen 2,
iXLen %1)
@@ -2612,7 +2612,7 @@ define <vscale x 8 x i32> @intrinsic_vror_vi_nxv8i32(<vscale x 8 x i32> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vror.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
iXLen 2,
iXLen %1)
@@ -2645,7 +2645,7 @@ define <vscale x 16 x i32> @intrinsic_vror_vi_nxv16i32(<vscale x 16 x i32> %0, i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vror.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
iXLen 2,
iXLen %1)
@@ -2678,7 +2678,7 @@ define <vscale x 1 x i64> @intrinsic_vror_vi_nxv1i64(<vscale x 1 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vror.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
iXLen 2,
iXLen %1)
@@ -2711,7 +2711,7 @@ define <vscale x 2 x i64> @intrinsic_vror_vi_nxv2i64(<vscale x 2 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vror.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
iXLen 2,
iXLen %1)
@@ -2744,7 +2744,7 @@ define <vscale x 4 x i64> @intrinsic_vror_vi_nxv4i64(<vscale x 4 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vror.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
iXLen 2,
iXLen %1)
@@ -2777,7 +2777,7 @@ define <vscale x 8 x i64> @intrinsic_vror_vi_nxv8i64(<vscale x 8 x i64> %0, iXLe
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vror.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
iXLen 2,
iXLen %1)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 16:44:08 +0000