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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vnsra.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vnsra.ll90
1 files changed, 45 insertions, 45 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra.ll
index ed4ec10d8946..78c31d340347 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnsra.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra.ll
@@ -18,7 +18,7 @@ define <vscale x 1 x i8> @intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i16> %0,
<vscale x 1 x i8> %1,
iXLen %2)
@@ -65,7 +65,7 @@ define <vscale x 2 x i8> @intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i16> %0,
<vscale x 2 x i8> %1,
iXLen %2)
@@ -112,7 +112,7 @@ define <vscale x 4 x i8> @intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i16> %0,
<vscale x 4 x i8> %1,
iXLen %2)
@@ -160,7 +160,7 @@ define <vscale x 8 x i8> @intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i16> %0,
<vscale x 8 x i8> %1,
iXLen %2)
@@ -208,7 +208,7 @@ define <vscale x 16 x i8> @intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i16> %0,
<vscale x 16 x i8> %1,
iXLen %2)
@@ -256,7 +256,7 @@ define <vscale x 32 x i8> @intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i16> %0,
<vscale x 32 x i8> %1,
iXLen %2)
@@ -303,7 +303,7 @@ define <vscale x 1 x i16> @intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i32> %0,
<vscale x 1 x i16> %1,
iXLen %2)
@@ -350,7 +350,7 @@ define <vscale x 2 x i16> @intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i16> %1,
iXLen %2)
@@ -398,7 +398,7 @@ define <vscale x 4 x i16> @intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i32> %0,
<vscale x 4 x i16> %1,
iXLen %2)
@@ -446,7 +446,7 @@ define <vscale x 8 x i16> @intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i32> %0,
<vscale x 8 x i16> %1,
iXLen %2)
@@ -494,7 +494,7 @@ define <vscale x 16 x i16> @intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16(<vscal
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i32> %0,
<vscale x 16 x i16> %1,
iXLen %2)
@@ -541,7 +541,7 @@ define <vscale x 1 x i32> @intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i64> %0,
<vscale x 1 x i32> %1,
iXLen %2)
@@ -589,7 +589,7 @@ define <vscale x 2 x i32> @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i64> %0,
<vscale x 2 x i32> %1,
iXLen %2)
@@ -637,7 +637,7 @@ define <vscale x 4 x i32> @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i64> %0,
<vscale x 4 x i32> %1,
iXLen %2)
@@ -685,7 +685,7 @@ define <vscale x 8 x i32> @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i64> %0,
<vscale x 8 x i32> %1,
iXLen %2)
@@ -732,7 +732,7 @@ define <vscale x 1 x i8> @intrinsic_vnsra_vx_nxv1i8_nxv1i16(<vscale x 1 x i16> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i16> %0,
iXLen %1,
iXLen %2)
@@ -779,7 +779,7 @@ define <vscale x 2 x i8> @intrinsic_vnsra_vx_nxv2i8_nxv2i16(<vscale x 2 x i16> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i16> %0,
iXLen %1,
iXLen %2)
@@ -826,7 +826,7 @@ define <vscale x 4 x i8> @intrinsic_vnsra_vx_nxv4i8_nxv4i16(<vscale x 4 x i16> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i16> %0,
iXLen %1,
iXLen %2)
@@ -874,7 +874,7 @@ define <vscale x 8 x i8> @intrinsic_vnsra_vx_nxv8i8_nxv8i16(<vscale x 8 x i16> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i16> %0,
iXLen %1,
iXLen %2)
@@ -922,7 +922,7 @@ define <vscale x 16 x i8> @intrinsic_vnsra_vx_nxv16i8_nxv16i16(<vscale x 16 x i1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i16> %0,
iXLen %1,
iXLen %2)
@@ -970,7 +970,7 @@ define <vscale x 32 x i8> @intrinsic_vnsra_vx_nxv32i8_nxv32i16(<vscale x 32 x i1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i16> %0,
iXLen %1,
iXLen %2)
@@ -1017,7 +1017,7 @@ define <vscale x 1 x i16> @intrinsic_vnsra_vx_nxv1i16_nxv1i32(<vscale x 1 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1064,7 +1064,7 @@ define <vscale x 2 x i16> @intrinsic_vnsra_vx_nxv2i16_nxv2i32(<vscale x 2 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1112,7 +1112,7 @@ define <vscale x 4 x i16> @intrinsic_vnsra_vx_nxv4i16_nxv4i32(<vscale x 4 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1160,7 +1160,7 @@ define <vscale x 8 x i16> @intrinsic_vnsra_vx_nxv8i16_nxv8i32(<vscale x 8 x i32>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1208,7 +1208,7 @@ define <vscale x 16 x i16> @intrinsic_vnsra_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i32> %0,
iXLen %1,
iXLen %2)
@@ -1255,7 +1255,7 @@ define <vscale x 1 x i32> @intrinsic_vnsra_vx_nxv1i32_nxv1i64(<vscale x 1 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i64> %0,
iXLen %1,
iXLen %2)
@@ -1303,7 +1303,7 @@ define <vscale x 2 x i32> @intrinsic_vnsra_vx_nxv2i32_nxv2i64(<vscale x 2 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i64> %0,
iXLen %1,
iXLen %2)
@@ -1351,7 +1351,7 @@ define <vscale x 4 x i32> @intrinsic_vnsra_vx_nxv4i32_nxv4i64(<vscale x 4 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i64> %0,
iXLen %1,
iXLen %2)
@@ -1399,7 +1399,7 @@ define <vscale x 8 x i32> @intrinsic_vnsra_vx_nxv8i32_nxv8i64(<vscale x 8 x i64>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i64> %0,
iXLen %1,
iXLen %2)
@@ -1440,7 +1440,7 @@ define <vscale x 1 x i8> @intrinsic_vnsra_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i16> %0,
iXLen 9,
iXLen %1)
@@ -1473,7 +1473,7 @@ define <vscale x 2 x i8> @intrinsic_vnsra_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnsra.nxv2i8.nxv2i16(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i16> %0,
iXLen 9,
iXLen %1)
@@ -1506,7 +1506,7 @@ define <vscale x 4 x i8> @intrinsic_vnsra_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnsra.nxv4i8.nxv4i16(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i16> %0,
iXLen 9,
iXLen %1)
@@ -1540,7 +1540,7 @@ define <vscale x 8 x i8> @intrinsic_vnsra_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnsra.nxv8i8.nxv8i16(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i16> %0,
iXLen 9,
iXLen %1)
@@ -1574,7 +1574,7 @@ define <vscale x 16 x i8> @intrinsic_vnsra_vi_nxv16i8_nxv16i16_i8(<vscale x 16 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnsra.nxv16i8.nxv16i16(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i16> %0,
iXLen 9,
iXLen %1)
@@ -1608,7 +1608,7 @@ define <vscale x 32 x i8> @intrinsic_vnsra_vi_nxv32i8_nxv32i16_i8(<vscale x 32 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnsra.nxv32i8.nxv32i16(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i16> %0,
iXLen 9,
iXLen %1)
@@ -1641,7 +1641,7 @@ define <vscale x 1 x i16> @intrinsic_vnsra_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnsra.nxv1i16.nxv1i32(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i32> %0,
iXLen 9,
iXLen %1)
@@ -1674,7 +1674,7 @@ define <vscale x 2 x i16> @intrinsic_vnsra_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnsra.nxv2i16.nxv2i32(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i32> %0,
iXLen 9,
iXLen %1)
@@ -1708,7 +1708,7 @@ define <vscale x 4 x i16> @intrinsic_vnsra_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnsra.nxv4i16.nxv4i32(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i32> %0,
iXLen 9,
iXLen %1)
@@ -1742,7 +1742,7 @@ define <vscale x 8 x i16> @intrinsic_vnsra_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnsra.nxv8i16.nxv8i32(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i32> %0,
iXLen 9,
iXLen %1)
@@ -1776,7 +1776,7 @@ define <vscale x 16 x i16> @intrinsic_vnsra_vi_nxv16i16_nxv16i32_i16(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnsra.nxv16i16.nxv16i32(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i32> %0,
iXLen 9,
iXLen %1)
@@ -1809,7 +1809,7 @@ define <vscale x 1 x i32> @intrinsic_vnsra_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnsra.nxv1i32.nxv1i64(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i64> %0,
iXLen 9,
iXLen %1)
@@ -1843,7 +1843,7 @@ define <vscale x 2 x i32> @intrinsic_vnsra_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnsra.nxv2i32.nxv2i64(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i64> %0,
iXLen 9,
iXLen %1)
@@ -1877,7 +1877,7 @@ define <vscale x 4 x i32> @intrinsic_vnsra_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnsra.nxv4i32.nxv4i64(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i64> %0,
iXLen 9,
iXLen %1)
@@ -1911,7 +1911,7 @@ define <vscale x 8 x i32> @intrinsic_vnsra_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnsra.nxv8i32.nxv8i64(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i64> %0,
iXLen 9,
iXLen %1)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:54:58 +0000