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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vnclip.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vnclip.ll90
1 files changed, 45 insertions, 45 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip.ll
index 8902b1a28f8c..1c389f522e84 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vnclip.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vnclip.ll
@@ -19,7 +19,7 @@ define <vscale x 1 x i8> @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i16> %0,
<vscale x 1 x i8> %1,
iXLen 0, iXLen %2)
@@ -67,7 +67,7 @@ define <vscale x 2 x i8> @intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i16> %0,
<vscale x 2 x i8> %1,
iXLen 0, iXLen %2)
@@ -115,7 +115,7 @@ define <vscale x 4 x i8> @intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i16> %0,
<vscale x 4 x i8> %1,
iXLen 0, iXLen %2)
@@ -164,7 +164,7 @@ define <vscale x 8 x i8> @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i16> %0,
<vscale x 8 x i8> %1,
iXLen 0, iXLen %2)
@@ -213,7 +213,7 @@ define <vscale x 16 x i8> @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i16> %0,
<vscale x 16 x i8> %1,
iXLen 0, iXLen %2)
@@ -262,7 +262,7 @@ define <vscale x 32 x i8> @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i16> %0,
<vscale x 32 x i8> %1,
iXLen 0, iXLen %2)
@@ -310,7 +310,7 @@ define <vscale x 1 x i16> @intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i32> %0,
<vscale x 1 x i16> %1,
iXLen 0, iXLen %2)
@@ -358,7 +358,7 @@ define <vscale x 2 x i16> @intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i16> %1,
iXLen 0, iXLen %2)
@@ -407,7 +407,7 @@ define <vscale x 4 x i16> @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i32> %0,
<vscale x 4 x i16> %1,
iXLen 0, iXLen %2)
@@ -456,7 +456,7 @@ define <vscale x 8 x i16> @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i32> %0,
<vscale x 8 x i16> %1,
iXLen 0, iXLen %2)
@@ -505,7 +505,7 @@ define <vscale x 16 x i16> @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16(<vsca
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i32> %0,
<vscale x 16 x i16> %1,
iXLen 0, iXLen %2)
@@ -553,7 +553,7 @@ define <vscale x 1 x i32> @intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i64> %0,
<vscale x 1 x i32> %1,
iXLen 0, iXLen %2)
@@ -602,7 +602,7 @@ define <vscale x 2 x i32> @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i64> %0,
<vscale x 2 x i32> %1,
iXLen 0, iXLen %2)
@@ -651,7 +651,7 @@ define <vscale x 4 x i32> @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i64> %0,
<vscale x 4 x i32> %1,
iXLen 0, iXLen %2)
@@ -700,7 +700,7 @@ define <vscale x 8 x i32> @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i64> %0,
<vscale x 8 x i32> %1,
iXLen 0, iXLen %2)
@@ -747,7 +747,7 @@ define <vscale x 1 x i8> @intrinsic_vnclip_vx_nxv1i8_nxv1i16(<vscale x 1 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i16> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -794,7 +794,7 @@ define <vscale x 2 x i8> @intrinsic_vnclip_vx_nxv2i8_nxv2i16(<vscale x 2 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i16> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -841,7 +841,7 @@ define <vscale x 4 x i8> @intrinsic_vnclip_vx_nxv4i8_nxv4i16(<vscale x 4 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i16> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -889,7 +889,7 @@ define <vscale x 8 x i8> @intrinsic_vnclip_vx_nxv8i8_nxv8i16(<vscale x 8 x i16>
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i16> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -937,7 +937,7 @@ define <vscale x 16 x i8> @intrinsic_vnclip_vx_nxv16i8_nxv16i16(<vscale x 16 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i16> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -985,7 +985,7 @@ define <vscale x 32 x i8> @intrinsic_vnclip_vx_nxv32i8_nxv32i16(<vscale x 32 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i16> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1032,7 +1032,7 @@ define <vscale x 1 x i16> @intrinsic_vnclip_vx_nxv1i16_nxv1i32(<vscale x 1 x i32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i32> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1079,7 +1079,7 @@ define <vscale x 2 x i16> @intrinsic_vnclip_vx_nxv2i16_nxv2i32(<vscale x 2 x i32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i32> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1127,7 +1127,7 @@ define <vscale x 4 x i16> @intrinsic_vnclip_vx_nxv4i16_nxv4i32(<vscale x 4 x i32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i32> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1175,7 +1175,7 @@ define <vscale x 8 x i16> @intrinsic_vnclip_vx_nxv8i16_nxv8i32(<vscale x 8 x i32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i32> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1223,7 +1223,7 @@ define <vscale x 16 x i16> @intrinsic_vnclip_vx_nxv16i16_nxv16i32(<vscale x 16 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i32> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1270,7 +1270,7 @@ define <vscale x 1 x i32> @intrinsic_vnclip_vx_nxv1i32_nxv1i64(<vscale x 1 x i64
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i64> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1318,7 +1318,7 @@ define <vscale x 2 x i32> @intrinsic_vnclip_vx_nxv2i32_nxv2i64(<vscale x 2 x i64
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i64> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1366,7 +1366,7 @@ define <vscale x 4 x i32> @intrinsic_vnclip_vx_nxv4i32_nxv4i64(<vscale x 4 x i64
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i64> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1414,7 +1414,7 @@ define <vscale x 8 x i32> @intrinsic_vnclip_vx_nxv8i32_nxv8i64(<vscale x 8 x i64
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i64> %0,
iXLen %1,
iXLen 0, iXLen %2)
@@ -1456,7 +1456,7 @@ define <vscale x 1 x i8> @intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8(<vscale x 1 x i1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i16> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1491,7 +1491,7 @@ define <vscale x 2 x i8> @intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8(<vscale x 2 x i1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vnclip.nxv2i8.nxv2i16(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i16> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1526,7 +1526,7 @@ define <vscale x 4 x i8> @intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8(<vscale x 4 x i1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vnclip.nxv4i8.nxv4i16(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i16> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1562,7 +1562,7 @@ define <vscale x 8 x i8> @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8(<vscale x 8 x i1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vnclip.nxv8i8.nxv8i16(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i16> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1598,7 +1598,7 @@ define <vscale x 16 x i8> @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8(<vscale x 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vnclip.nxv16i8.nxv16i16(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i16> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1634,7 +1634,7 @@ define <vscale x 32 x i8> @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8(<vscale x 32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vnclip.nxv32i8.nxv32i16(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i16> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1669,7 +1669,7 @@ define <vscale x 1 x i16> @intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vnclip.nxv1i16.nxv1i32(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i32> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1704,7 +1704,7 @@ define <vscale x 2 x i16> @intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i32> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1740,7 +1740,7 @@ define <vscale x 4 x i16> @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vnclip.nxv4i16.nxv4i32(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i32> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1776,7 +1776,7 @@ define <vscale x 8 x i16> @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vnclip.nxv8i16.nxv8i32(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i32> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1812,7 +1812,7 @@ define <vscale x 16 x i16> @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vnclip.nxv16i16.nxv16i32(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i32> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1847,7 +1847,7 @@ define <vscale x 1 x i32> @intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32(<vscale x 1 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vnclip.nxv1i32.nxv1i64(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i64> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1883,7 +1883,7 @@ define <vscale x 2 x i32> @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32(<vscale x 2 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vnclip.nxv2i32.nxv2i64(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i64> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1919,7 +1919,7 @@ define <vscale x 4 x i32> @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32(<vscale x 4 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vnclip.nxv4i32.nxv4i64(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i64> %0,
iXLen 9,
iXLen 0, iXLen %1)
@@ -1955,7 +1955,7 @@ define <vscale x 8 x i32> @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32(<vscale x 8 x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vnclip.nxv8i32.nxv8i64(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i64> %0,
iXLen 9,
iXLen 0, iXLen %1)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:54:49 +0000