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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll88
1 files changed, 44 insertions, 44 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
index 79bdd30291c0..472cd6ec07e2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll
@@ -17,7 +17,7 @@ define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, iXLen %1) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
i8 %0,
iXLen %1)
@@ -37,7 +37,7 @@ define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, iXLen %1) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
i8 %0,
iXLen %1)
@@ -57,7 +57,7 @@ define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, iXLen %1) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
i8 %0,
iXLen %1)
@@ -77,7 +77,7 @@ define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, iXLen %1) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
i8 %0,
iXLen %1)
@@ -97,7 +97,7 @@ define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, iXLen %1) nounwind
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
i8 %0,
iXLen %1)
@@ -117,7 +117,7 @@ define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, iXLen %1) nounwind
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
i8 %0,
iXLen %1)
@@ -137,7 +137,7 @@ define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, iXLen %1) nounwind
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
i8 %0,
iXLen %1)
@@ -157,7 +157,7 @@ define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
i16 %0,
iXLen %1)
@@ -177,7 +177,7 @@ define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
i16 %0,
iXLen %1)
@@ -197,7 +197,7 @@ define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
i16 %0,
iXLen %1)
@@ -217,7 +217,7 @@ define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
i16 %0,
iXLen %1)
@@ -237,7 +237,7 @@ define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, iXLen %1) nounw
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
i16 %0,
iXLen %1)
@@ -257,7 +257,7 @@ define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, iXLen %1) nounw
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
i16 %0,
iXLen %1)
@@ -277,7 +277,7 @@ define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
i32 %0,
iXLen %1)
@@ -297,7 +297,7 @@ define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
i32 %0,
iXLen %1)
@@ -317,7 +317,7 @@ define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
i32 %0,
iXLen %1)
@@ -337,7 +337,7 @@ define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, iXLen %1) nounwin
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
i32 %0,
iXLen %1)
@@ -357,7 +357,7 @@ define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, iXLen %1) nounw
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
i32 %0,
iXLen %1)
@@ -388,7 +388,7 @@ define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, iXLen %1) nounwin
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
i64 %0,
iXLen %1)
@@ -419,7 +419,7 @@ define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, iXLen %1) nounwin
; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
i64 %0,
iXLen %1)
@@ -450,7 +450,7 @@ define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, iXLen %1) nounwin
; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
i64 %0,
iXLen %1)
@@ -481,7 +481,7 @@ define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, iXLen %1) nounwin
; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
i64 %0,
iXLen %1)
@@ -496,7 +496,7 @@ define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
i8 9,
iXLen %0)
@@ -511,7 +511,7 @@ define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
i8 9,
iXLen %0)
@@ -526,7 +526,7 @@ define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
i8 9,
iXLen %0)
@@ -541,7 +541,7 @@ define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
i8 9,
iXLen %0)
@@ -556,7 +556,7 @@ define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
i8 9,
iXLen %0)
@@ -571,7 +571,7 @@ define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
i8 9,
iXLen %0)
@@ -586,7 +586,7 @@ define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
i8 9,
iXLen %0)
@@ -601,7 +601,7 @@ define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
i16 9,
iXLen %0)
@@ -616,7 +616,7 @@ define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
i16 9,
iXLen %0)
@@ -631,7 +631,7 @@ define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
i16 9,
iXLen %0)
@@ -646,7 +646,7 @@ define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
i16 9,
iXLen %0)
@@ -661,7 +661,7 @@ define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
i16 9,
iXLen %0)
@@ -676,7 +676,7 @@ define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
i16 9,
iXLen %0)
@@ -691,7 +691,7 @@ define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
i32 9,
iXLen %0)
@@ -706,7 +706,7 @@ define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
i32 9,
iXLen %0)
@@ -721,7 +721,7 @@ define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
i32 9,
iXLen %0)
@@ -736,7 +736,7 @@ define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
i32 9,
iXLen %0)
@@ -751,7 +751,7 @@ define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
i32 9,
iXLen %0)
@@ -766,7 +766,7 @@ define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
i64 9,
iXLen %0)
@@ -781,7 +781,7 @@ define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
i64 9,
iXLen %0)
@@ -796,7 +796,7 @@ define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
i64 9,
iXLen %0)
@@ -811,7 +811,7 @@ define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64(iXLen %0) nounwind {
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
i64 9,
iXLen %0)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:55:17 +0000