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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll88
1 files changed, 44 insertions, 44 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
index 03c4f3fa1de8..5a785d8a678b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
@@ -24,7 +24,7 @@ define <vscale x 1 x i8> @intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen %2)
@@ -70,7 +70,7 @@ define <vscale x 2 x i8> @intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen %2)
@@ -116,7 +116,7 @@ define <vscale x 4 x i8> @intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen %2)
@@ -162,7 +162,7 @@ define <vscale x 8 x i8> @intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen %2)
@@ -208,7 +208,7 @@ define <vscale x 16 x i8> @intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen %2)
@@ -254,7 +254,7 @@ define <vscale x 32 x i8> @intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen %2)
@@ -300,7 +300,7 @@ define <vscale x 64 x i8> @intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
iXLen %2)
@@ -347,7 +347,7 @@ define <vscale x 1 x i16> @intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen %2)
@@ -393,7 +393,7 @@ define <vscale x 2 x i16> @intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen %2)
@@ -439,7 +439,7 @@ define <vscale x 4 x i16> @intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen %2)
@@ -485,7 +485,7 @@ define <vscale x 8 x i16> @intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen %2)
@@ -531,7 +531,7 @@ define <vscale x 16 x i16> @intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16(<vsc
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen %2)
@@ -577,7 +577,7 @@ define <vscale x 32 x i16> @intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16(<vsc
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
iXLen %2)
@@ -624,7 +624,7 @@ define <vscale x 1 x i32> @intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen %2)
@@ -670,7 +670,7 @@ define <vscale x 2 x i32> @intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2)
@@ -716,7 +716,7 @@ define <vscale x 4 x i32> @intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen %2)
@@ -762,7 +762,7 @@ define <vscale x 8 x i32> @intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen %2)
@@ -808,7 +808,7 @@ define <vscale x 16 x i32> @intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32(<vsc
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
iXLen %2)
@@ -855,7 +855,7 @@ define <vscale x 1 x i64> @intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
iXLen %2)
@@ -901,7 +901,7 @@ define <vscale x 2 x i64> @intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
iXLen %2)
@@ -947,7 +947,7 @@ define <vscale x 4 x i64> @intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
iXLen %2)
@@ -993,7 +993,7 @@ define <vscale x 8 x i64> @intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
iXLen %2)
@@ -1040,7 +1040,7 @@ define <vscale x 1 x i8> @intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
i8 %1,
iXLen %2)
@@ -1086,7 +1086,7 @@ define <vscale x 2 x i8> @intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmulhsu.nxv2i8.i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
i8 %1,
iXLen %2)
@@ -1132,7 +1132,7 @@ define <vscale x 4 x i8> @intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmulhsu.nxv4i8.i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
i8 %1,
iXLen %2)
@@ -1178,7 +1178,7 @@ define <vscale x 8 x i8> @intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmulhsu.nxv8i8.i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
i8 %1,
iXLen %2)
@@ -1224,7 +1224,7 @@ define <vscale x 16 x i8> @intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8(<vscale x 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmulhsu.nxv16i8.i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
i8 %1,
iXLen %2)
@@ -1270,7 +1270,7 @@ define <vscale x 32 x i8> @intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8(<vscale x 32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmulhsu.nxv32i8.i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
i8 %1,
iXLen %2)
@@ -1316,7 +1316,7 @@ define <vscale x 64 x i8> @intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8(<vscale x 64
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmulhsu.nxv64i8.i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
i8 %1,
iXLen %2)
@@ -1362,7 +1362,7 @@ define <vscale x 1 x i16> @intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmulhsu.nxv1i16.i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
i16 %1,
iXLen %2)
@@ -1408,7 +1408,7 @@ define <vscale x 2 x i16> @intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmulhsu.nxv2i16.i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
i16 %1,
iXLen %2)
@@ -1454,7 +1454,7 @@ define <vscale x 4 x i16> @intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmulhsu.nxv4i16.i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
i16 %1,
iXLen %2)
@@ -1500,7 +1500,7 @@ define <vscale x 8 x i16> @intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmulhsu.nxv8i16.i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
i16 %1,
iXLen %2)
@@ -1546,7 +1546,7 @@ define <vscale x 16 x i16> @intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmulhsu.nxv16i16.i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
i16 %1,
iXLen %2)
@@ -1592,7 +1592,7 @@ define <vscale x 32 x i16> @intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmulhsu.nxv32i16.i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
i16 %1,
iXLen %2)
@@ -1638,7 +1638,7 @@ define <vscale x 1 x i32> @intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmulhsu.nxv1i32.i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
i32 %1,
iXLen %2)
@@ -1684,7 +1684,7 @@ define <vscale x 2 x i32> @intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmulhsu.nxv2i32.i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
i32 %1,
iXLen %2)
@@ -1730,7 +1730,7 @@ define <vscale x 4 x i32> @intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmulhsu.nxv4i32.i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
i32 %1,
iXLen %2)
@@ -1776,7 +1776,7 @@ define <vscale x 8 x i32> @intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmulhsu.nxv8i32.i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
i32 %1,
iXLen %2)
@@ -1822,7 +1822,7 @@ define <vscale x 16 x i32> @intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32(<vscale x
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmulhsu.nxv16i32.i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
i32 %1,
iXLen %2)
@@ -1880,7 +1880,7 @@ define <vscale x 1 x i64> @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64(<vscale x 1
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmulhsu.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 %1,
iXLen %2)
@@ -1950,7 +1950,7 @@ define <vscale x 2 x i64> @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64(<vscale x 2
; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmulhsu.nxv2i64.i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
i64 %1,
iXLen %2)
@@ -2020,7 +2020,7 @@ define <vscale x 4 x i64> @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64(<vscale x 4
; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmulhsu.nxv4i64.i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
i64 %1,
iXLen %2)
@@ -2090,7 +2090,7 @@ define <vscale x 8 x i64> @intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64(<vscale x 8
; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmulhsu.nxv8i64.i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
i64 %1,
iXLen %2)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:55:06 +0000