diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vloxei.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vloxei.ll | 222 |
1 files changed, 111 insertions, 111 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei.ll index 03b4268975d4..be9faa8867a7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vloxei.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxei.ll @@ -19,7 +19,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i32( - <vscale x 1 x i8> undef, + <vscale x 1 x i8> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -67,7 +67,7 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i32( - <vscale x 2 x i8> undef, + <vscale x 2 x i8> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -115,7 +115,7 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i32( - <vscale x 4 x i8> undef, + <vscale x 4 x i8> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -163,7 +163,7 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i32( - <vscale x 8 x i8> undef, + <vscale x 8 x i8> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -211,7 +211,7 @@ define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i32( - <vscale x 16 x i8> undef, + <vscale x 16 x i8> poison, ptr %0, <vscale x 16 x i32> %1, iXLen %2) @@ -259,7 +259,7 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i32( - <vscale x 1 x i16> undef, + <vscale x 1 x i16> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -307,7 +307,7 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i32( - <vscale x 2 x i16> undef, + <vscale x 2 x i16> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -355,7 +355,7 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i32( - <vscale x 4 x i16> undef, + <vscale x 4 x i16> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -403,7 +403,7 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i32( - <vscale x 8 x i16> undef, + <vscale x 8 x i16> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -451,7 +451,7 @@ define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32(ptr %0 ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i32( - <vscale x 16 x i16> undef, + <vscale x 16 x i16> poison, ptr %0, <vscale x 16 x i32> %1, iXLen %2) @@ -498,7 +498,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32( - <vscale x 1 x i32> undef, + <vscale x 1 x i32> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -545,7 +545,7 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i32( - <vscale x 2 x i32> undef, + <vscale x 2 x i32> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -592,7 +592,7 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i32( - <vscale x 4 x i32> undef, + <vscale x 4 x i32> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -639,7 +639,7 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i32( - <vscale x 8 x i32> undef, + <vscale x 8 x i32> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -686,7 +686,7 @@ define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32(ptr %0 ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i32( - <vscale x 16 x i32> undef, + <vscale x 16 x i32> poison, ptr %0, <vscale x 16 x i32> %1, iXLen %2) @@ -734,7 +734,7 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32( - <vscale x 1 x i64> undef, + <vscale x 1 x i64> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -782,7 +782,7 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i32( - <vscale x 2 x i64> undef, + <vscale x 2 x i64> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -830,7 +830,7 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i32( - <vscale x 4 x i64> undef, + <vscale x 4 x i64> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -878,7 +878,7 @@ define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i32( - <vscale x 8 x i64> undef, + <vscale x 8 x i64> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -926,7 +926,7 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32( - <vscale x 1 x half> undef, + <vscale x 1 x half> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -974,7 +974,7 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32( - <vscale x 2 x half> undef, + <vscale x 2 x half> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -1022,7 +1022,7 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32( - <vscale x 4 x half> undef, + <vscale x 4 x half> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -1070,7 +1070,7 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32( - <vscale x 8 x half> undef, + <vscale x 8 x half> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -1118,7 +1118,7 @@ define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32( - <vscale x 16 x half> undef, + <vscale x 16 x half> poison, ptr %0, <vscale x 16 x i32> %1, iXLen %2) @@ -1165,7 +1165,7 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32( - <vscale x 1 x float> undef, + <vscale x 1 x float> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -1212,7 +1212,7 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i32( - <vscale x 2 x float> undef, + <vscale x 2 x float> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -1259,7 +1259,7 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i32( - <vscale x 4 x float> undef, + <vscale x 4 x float> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -1306,7 +1306,7 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i32( - <vscale x 8 x float> undef, + <vscale x 8 x float> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -1353,7 +1353,7 @@ define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32(ptr ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i32( - <vscale x 16 x float> undef, + <vscale x 16 x float> poison, ptr %0, <vscale x 16 x i32> %1, iXLen %2) @@ -1401,7 +1401,7 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i32( - <vscale x 1 x double> undef, + <vscale x 1 x double> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -1449,7 +1449,7 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i32( - <vscale x 2 x double> undef, + <vscale x 2 x double> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -1497,7 +1497,7 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i32( - <vscale x 4 x double> undef, + <vscale x 4 x double> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -1545,7 +1545,7 @@ define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i32( - <vscale x 8 x double> undef, + <vscale x 8 x double> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -1593,7 +1593,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i16( - <vscale x 1 x i8> undef, + <vscale x 1 x i8> poison, ptr %0, <vscale x 1 x i16> %1, iXLen %2) @@ -1641,7 +1641,7 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i16( - <vscale x 2 x i8> undef, + <vscale x 2 x i8> poison, ptr %0, <vscale x 2 x i16> %1, iXLen %2) @@ -1689,7 +1689,7 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i16( - <vscale x 4 x i8> undef, + <vscale x 4 x i8> poison, ptr %0, <vscale x 4 x i16> %1, iXLen %2) @@ -1737,7 +1737,7 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16(ptr %0, <vsca ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i16( - <vscale x 8 x i8> undef, + <vscale x 8 x i8> poison, ptr %0, <vscale x 8 x i16> %1, iXLen %2) @@ -1785,7 +1785,7 @@ define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i16( - <vscale x 16 x i8> undef, + <vscale x 16 x i8> poison, ptr %0, <vscale x 16 x i16> %1, iXLen %2) @@ -1833,7 +1833,7 @@ define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i16( - <vscale x 32 x i8> undef, + <vscale x 32 x i8> poison, ptr %0, <vscale x 32 x i16> %1, iXLen %2) @@ -1880,7 +1880,7 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i16( - <vscale x 1 x i16> undef, + <vscale x 1 x i16> poison, ptr %0, <vscale x 1 x i16> %1, iXLen %2) @@ -1927,7 +1927,7 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i16( - <vscale x 2 x i16> undef, + <vscale x 2 x i16> poison, ptr %0, <vscale x 2 x i16> %1, iXLen %2) @@ -1974,7 +1974,7 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i16( - <vscale x 4 x i16> undef, + <vscale x 4 x i16> poison, ptr %0, <vscale x 4 x i16> %1, iXLen %2) @@ -2021,7 +2021,7 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i16( - <vscale x 8 x i16> undef, + <vscale x 8 x i16> poison, ptr %0, <vscale x 8 x i16> %1, iXLen %2) @@ -2068,7 +2068,7 @@ define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16(ptr %0 ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i16( - <vscale x 16 x i16> undef, + <vscale x 16 x i16> poison, ptr %0, <vscale x 16 x i16> %1, iXLen %2) @@ -2115,7 +2115,7 @@ define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16(ptr %0 ; CHECK-NEXT: ret entry: %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i16( - <vscale x 32 x i16> undef, + <vscale x 32 x i16> poison, ptr %0, <vscale x 32 x i16> %1, iXLen %2) @@ -2163,7 +2163,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16( - <vscale x 1 x i32> undef, + <vscale x 1 x i32> poison, ptr %0, <vscale x 1 x i16> %1, iXLen %2) @@ -2211,7 +2211,7 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i16( - <vscale x 2 x i32> undef, + <vscale x 2 x i32> poison, ptr %0, <vscale x 2 x i16> %1, iXLen %2) @@ -2259,7 +2259,7 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i16( - <vscale x 4 x i32> undef, + <vscale x 4 x i32> poison, ptr %0, <vscale x 4 x i16> %1, iXLen %2) @@ -2307,7 +2307,7 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i16( - <vscale x 8 x i32> undef, + <vscale x 8 x i32> poison, ptr %0, <vscale x 8 x i16> %1, iXLen %2) @@ -2355,7 +2355,7 @@ define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16(ptr %0 ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i16( - <vscale x 16 x i32> undef, + <vscale x 16 x i32> poison, ptr %0, <vscale x 16 x i16> %1, iXLen %2) @@ -2403,7 +2403,7 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i16( - <vscale x 1 x i64> undef, + <vscale x 1 x i64> poison, ptr %0, <vscale x 1 x i16> %1, iXLen %2) @@ -2451,7 +2451,7 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i16( - <vscale x 2 x i64> undef, + <vscale x 2 x i64> poison, ptr %0, <vscale x 2 x i16> %1, iXLen %2) @@ -2499,7 +2499,7 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i16( - <vscale x 4 x i64> undef, + <vscale x 4 x i64> poison, ptr %0, <vscale x 4 x i16> %1, iXLen %2) @@ -2547,7 +2547,7 @@ define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i16( - <vscale x 8 x i64> undef, + <vscale x 8 x i64> poison, ptr %0, <vscale x 8 x i16> %1, iXLen %2) @@ -2594,7 +2594,7 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16( - <vscale x 1 x half> undef, + <vscale x 1 x half> poison, ptr %0, <vscale x 1 x i16> %1, iXLen %2) @@ -2641,7 +2641,7 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16( - <vscale x 2 x half> undef, + <vscale x 2 x half> poison, ptr %0, <vscale x 2 x i16> %1, iXLen %2) @@ -2688,7 +2688,7 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16( - <vscale x 4 x half> undef, + <vscale x 4 x half> poison, ptr %0, <vscale x 4 x i16> %1, iXLen %2) @@ -2735,7 +2735,7 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16( - <vscale x 8 x half> undef, + <vscale x 8 x half> poison, ptr %0, <vscale x 8 x i16> %1, iXLen %2) @@ -2782,7 +2782,7 @@ define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16( - <vscale x 16 x half> undef, + <vscale x 16 x half> poison, ptr %0, <vscale x 16 x i16> %1, iXLen %2) @@ -2829,7 +2829,7 @@ define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16( - <vscale x 32 x half> undef, + <vscale x 32 x half> poison, ptr %0, <vscale x 32 x i16> %1, iXLen %2) @@ -2877,7 +2877,7 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16( - <vscale x 1 x float> undef, + <vscale x 1 x float> poison, ptr %0, <vscale x 1 x i16> %1, iXLen %2) @@ -2925,7 +2925,7 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i16( - <vscale x 2 x float> undef, + <vscale x 2 x float> poison, ptr %0, <vscale x 2 x i16> %1, iXLen %2) @@ -2973,7 +2973,7 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i16( - <vscale x 4 x float> undef, + <vscale x 4 x float> poison, ptr %0, <vscale x 4 x i16> %1, iXLen %2) @@ -3021,7 +3021,7 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i16( - <vscale x 8 x float> undef, + <vscale x 8 x float> poison, ptr %0, <vscale x 8 x i16> %1, iXLen %2) @@ -3069,7 +3069,7 @@ define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16(ptr ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i16( - <vscale x 16 x float> undef, + <vscale x 16 x float> poison, ptr %0, <vscale x 16 x i16> %1, iXLen %2) @@ -3117,7 +3117,7 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i16( - <vscale x 1 x double> undef, + <vscale x 1 x double> poison, ptr %0, <vscale x 1 x i16> %1, iXLen %2) @@ -3165,7 +3165,7 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i16( - <vscale x 2 x double> undef, + <vscale x 2 x double> poison, ptr %0, <vscale x 2 x i16> %1, iXLen %2) @@ -3213,7 +3213,7 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i16( - <vscale x 4 x double> undef, + <vscale x 4 x double> poison, ptr %0, <vscale x 4 x i16> %1, iXLen %2) @@ -3261,7 +3261,7 @@ define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i16( - <vscale x 8 x double> undef, + <vscale x 8 x double> poison, ptr %0, <vscale x 8 x i16> %1, iXLen %2) @@ -3308,7 +3308,7 @@ define <vscale x 1 x i8> @intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8(ptr %0, <vscal ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8.nxv1i8( - <vscale x 1 x i8> undef, + <vscale x 1 x i8> poison, ptr %0, <vscale x 1 x i8> %1, iXLen %2) @@ -3355,7 +3355,7 @@ define <vscale x 2 x i8> @intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8(ptr %0, <vscal ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i8> @llvm.riscv.vloxei.nxv2i8.nxv2i8( - <vscale x 2 x i8> undef, + <vscale x 2 x i8> poison, ptr %0, <vscale x 2 x i8> %1, iXLen %2) @@ -3402,7 +3402,7 @@ define <vscale x 4 x i8> @intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8(ptr %0, <vscal ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i8> @llvm.riscv.vloxei.nxv4i8.nxv4i8( - <vscale x 4 x i8> undef, + <vscale x 4 x i8> poison, ptr %0, <vscale x 4 x i8> %1, iXLen %2) @@ -3449,7 +3449,7 @@ define <vscale x 8 x i8> @intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8(ptr %0, <vscal ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i8> @llvm.riscv.vloxei.nxv8i8.nxv8i8( - <vscale x 8 x i8> undef, + <vscale x 8 x i8> poison, ptr %0, <vscale x 8 x i8> %1, iXLen %2) @@ -3496,7 +3496,7 @@ define <vscale x 16 x i8> @intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i8> @llvm.riscv.vloxei.nxv16i8.nxv16i8( - <vscale x 16 x i8> undef, + <vscale x 16 x i8> poison, ptr %0, <vscale x 16 x i8> %1, iXLen %2) @@ -3543,7 +3543,7 @@ define <vscale x 32 x i8> @intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 32 x i8> @llvm.riscv.vloxei.nxv32i8.nxv32i8( - <vscale x 32 x i8> undef, + <vscale x 32 x i8> poison, ptr %0, <vscale x 32 x i8> %1, iXLen %2) @@ -3590,7 +3590,7 @@ define <vscale x 64 x i8> @intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 64 x i8> @llvm.riscv.vloxei.nxv64i8.nxv64i8( - <vscale x 64 x i8> undef, + <vscale x 64 x i8> poison, ptr %0, <vscale x 64 x i8> %1, iXLen %2) @@ -3638,7 +3638,7 @@ define <vscale x 1 x i16> @intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i16> @llvm.riscv.vloxei.nxv1i16.nxv1i8( - <vscale x 1 x i16> undef, + <vscale x 1 x i16> poison, ptr %0, <vscale x 1 x i8> %1, iXLen %2) @@ -3686,7 +3686,7 @@ define <vscale x 2 x i16> @intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i16> @llvm.riscv.vloxei.nxv2i16.nxv2i8( - <vscale x 2 x i16> undef, + <vscale x 2 x i16> poison, ptr %0, <vscale x 2 x i8> %1, iXLen %2) @@ -3734,7 +3734,7 @@ define <vscale x 4 x i16> @intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i16> @llvm.riscv.vloxei.nxv4i16.nxv4i8( - <vscale x 4 x i16> undef, + <vscale x 4 x i16> poison, ptr %0, <vscale x 4 x i8> %1, iXLen %2) @@ -3782,7 +3782,7 @@ define <vscale x 8 x i16> @intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i16> @llvm.riscv.vloxei.nxv8i16.nxv8i8( - <vscale x 8 x i16> undef, + <vscale x 8 x i16> poison, ptr %0, <vscale x 8 x i8> %1, iXLen %2) @@ -3830,7 +3830,7 @@ define <vscale x 16 x i16> @intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i16> @llvm.riscv.vloxei.nxv16i16.nxv16i8( - <vscale x 16 x i16> undef, + <vscale x 16 x i16> poison, ptr %0, <vscale x 16 x i8> %1, iXLen %2) @@ -3878,7 +3878,7 @@ define <vscale x 32 x i16> @intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 32 x i16> @llvm.riscv.vloxei.nxv32i16.nxv32i8( - <vscale x 32 x i16> undef, + <vscale x 32 x i16> poison, ptr %0, <vscale x 32 x i8> %1, iXLen %2) @@ -3926,7 +3926,7 @@ define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i8( - <vscale x 1 x i32> undef, + <vscale x 1 x i32> poison, ptr %0, <vscale x 1 x i8> %1, iXLen %2) @@ -3974,7 +3974,7 @@ define <vscale x 2 x i32> @intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i32> @llvm.riscv.vloxei.nxv2i32.nxv2i8( - <vscale x 2 x i32> undef, + <vscale x 2 x i32> poison, ptr %0, <vscale x 2 x i8> %1, iXLen %2) @@ -4022,7 +4022,7 @@ define <vscale x 4 x i32> @intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i32> @llvm.riscv.vloxei.nxv4i32.nxv4i8( - <vscale x 4 x i32> undef, + <vscale x 4 x i32> poison, ptr %0, <vscale x 4 x i8> %1, iXLen %2) @@ -4070,7 +4070,7 @@ define <vscale x 8 x i32> @intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i32> @llvm.riscv.vloxei.nxv8i32.nxv8i8( - <vscale x 8 x i32> undef, + <vscale x 8 x i32> poison, ptr %0, <vscale x 8 x i8> %1, iXLen %2) @@ -4118,7 +4118,7 @@ define <vscale x 16 x i32> @intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x i32> @llvm.riscv.vloxei.nxv16i32.nxv16i8( - <vscale x 16 x i32> undef, + <vscale x 16 x i32> poison, ptr %0, <vscale x 16 x i8> %1, iXLen %2) @@ -4166,7 +4166,7 @@ define <vscale x 1 x i64> @intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i8( - <vscale x 1 x i64> undef, + <vscale x 1 x i64> poison, ptr %0, <vscale x 1 x i8> %1, iXLen %2) @@ -4214,7 +4214,7 @@ define <vscale x 2 x i64> @intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x i64> @llvm.riscv.vloxei.nxv2i64.nxv2i8( - <vscale x 2 x i64> undef, + <vscale x 2 x i64> poison, ptr %0, <vscale x 2 x i8> %1, iXLen %2) @@ -4262,7 +4262,7 @@ define <vscale x 4 x i64> @intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x i64> @llvm.riscv.vloxei.nxv4i64.nxv4i8( - <vscale x 4 x i64> undef, + <vscale x 4 x i64> poison, ptr %0, <vscale x 4 x i8> %1, iXLen %2) @@ -4310,7 +4310,7 @@ define <vscale x 8 x i64> @intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8(ptr %0, <vs ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x i64> @llvm.riscv.vloxei.nxv8i64.nxv8i8( - <vscale x 8 x i64> undef, + <vscale x 8 x i64> poison, ptr %0, <vscale x 8 x i8> %1, iXLen %2) @@ -4358,7 +4358,7 @@ define <vscale x 1 x half> @intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8( - <vscale x 1 x half> undef, + <vscale x 1 x half> poison, ptr %0, <vscale x 1 x i8> %1, iXLen %2) @@ -4406,7 +4406,7 @@ define <vscale x 2 x half> @intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8( - <vscale x 2 x half> undef, + <vscale x 2 x half> poison, ptr %0, <vscale x 2 x i8> %1, iXLen %2) @@ -4454,7 +4454,7 @@ define <vscale x 4 x half> @intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8( - <vscale x 4 x half> undef, + <vscale x 4 x half> poison, ptr %0, <vscale x 4 x i8> %1, iXLen %2) @@ -4502,7 +4502,7 @@ define <vscale x 8 x half> @intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8(ptr %0, <v ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8( - <vscale x 8 x half> undef, + <vscale x 8 x half> poison, ptr %0, <vscale x 8 x i8> %1, iXLen %2) @@ -4550,7 +4550,7 @@ define <vscale x 16 x half> @intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8(ptr %0 ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8( - <vscale x 16 x half> undef, + <vscale x 16 x half> poison, ptr %0, <vscale x 16 x i8> %1, iXLen %2) @@ -4598,7 +4598,7 @@ define <vscale x 32 x half> @intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8(ptr %0 ; CHECK-NEXT: ret entry: %a = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8( - <vscale x 32 x half> undef, + <vscale x 32 x half> poison, ptr %0, <vscale x 32 x i8> %1, iXLen %2) @@ -4646,7 +4646,7 @@ define <vscale x 1 x bfloat> @intrinsic_vloxei_v_nxv1bf16_nxv1bf16_nxv1i32(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x bfloat> @llvm.riscv.vloxei.nxv1bf16.nxv1i32( - <vscale x 1 x bfloat> undef, + <vscale x 1 x bfloat> poison, ptr %0, <vscale x 1 x i32> %1, iXLen %2) @@ -4694,7 +4694,7 @@ define <vscale x 2 x bfloat> @intrinsic_vloxei_v_nxv2bf16_nxv2bf16_nxv2i32(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x bfloat> @llvm.riscv.vloxei.nxv2bf16.nxv2i32( - <vscale x 2 x bfloat> undef, + <vscale x 2 x bfloat> poison, ptr %0, <vscale x 2 x i32> %1, iXLen %2) @@ -4742,7 +4742,7 @@ define <vscale x 4 x bfloat> @intrinsic_vloxei_v_nxv4bf16_nxv4bf16_nxv4i32(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x bfloat> @llvm.riscv.vloxei.nxv4bf16.nxv4i32( - <vscale x 4 x bfloat> undef, + <vscale x 4 x bfloat> poison, ptr %0, <vscale x 4 x i32> %1, iXLen %2) @@ -4790,7 +4790,7 @@ define <vscale x 8 x bfloat> @intrinsic_vloxei_v_nxv8bf16_nxv8bf16_nxv8i32(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x bfloat> @llvm.riscv.vloxei.nxv8bf16.nxv8i32( - <vscale x 8 x bfloat> undef, + <vscale x 8 x bfloat> poison, ptr %0, <vscale x 8 x i32> %1, iXLen %2) @@ -4838,7 +4838,7 @@ define <vscale x 16 x bfloat> @intrinsic_vloxei_v_nxv16bf16_nxv16bf16_nxv16i32(p ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x bfloat> @llvm.riscv.vloxei.nxv16bf16.nxv16i32( - <vscale x 16 x bfloat> undef, + <vscale x 16 x bfloat> poison, ptr %0, <vscale x 16 x i32> %1, iXLen %2) @@ -4886,7 +4886,7 @@ define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i8( - <vscale x 1 x float> undef, + <vscale x 1 x float> poison, ptr %0, <vscale x 1 x i8> %1, iXLen %2) @@ -4934,7 +4934,7 @@ define <vscale x 2 x float> @intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x float> @llvm.riscv.vloxei.nxv2f32.nxv2i8( - <vscale x 2 x float> undef, + <vscale x 2 x float> poison, ptr %0, <vscale x 2 x i8> %1, iXLen %2) @@ -4982,7 +4982,7 @@ define <vscale x 4 x float> @intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x float> @llvm.riscv.vloxei.nxv4f32.nxv4i8( - <vscale x 4 x float> undef, + <vscale x 4 x float> poison, ptr %0, <vscale x 4 x i8> %1, iXLen %2) @@ -5030,7 +5030,7 @@ define <vscale x 8 x float> @intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8(ptr %0, < ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x float> @llvm.riscv.vloxei.nxv8f32.nxv8i8( - <vscale x 8 x float> undef, + <vscale x 8 x float> poison, ptr %0, <vscale x 8 x i8> %1, iXLen %2) @@ -5078,7 +5078,7 @@ define <vscale x 16 x float> @intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8(ptr % ; CHECK-NEXT: ret entry: %a = call <vscale x 16 x float> @llvm.riscv.vloxei.nxv16f32.nxv16i8( - <vscale x 16 x float> undef, + <vscale x 16 x float> poison, ptr %0, <vscale x 16 x i8> %1, iXLen %2) @@ -5126,7 +5126,7 @@ define <vscale x 1 x double> @intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 1 x double> @llvm.riscv.vloxei.nxv1f64.nxv1i8( - <vscale x 1 x double> undef, + <vscale x 1 x double> poison, ptr %0, <vscale x 1 x i8> %1, iXLen %2) @@ -5174,7 +5174,7 @@ define <vscale x 2 x double> @intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 2 x double> @llvm.riscv.vloxei.nxv2f64.nxv2i8( - <vscale x 2 x double> undef, + <vscale x 2 x double> poison, ptr %0, <vscale x 2 x i8> %1, iXLen %2) @@ -5222,7 +5222,7 @@ define <vscale x 4 x double> @intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 4 x double> @llvm.riscv.vloxei.nxv4f64.nxv4i8( - <vscale x 4 x double> undef, + <vscale x 4 x double> poison, ptr %0, <vscale x 4 x i8> %1, iXLen %2) @@ -5270,7 +5270,7 @@ define <vscale x 8 x double> @intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8(ptr %0, ; CHECK-NEXT: ret entry: %a = call <vscale x 8 x double> @llvm.riscv.vloxei.nxv8f64.nxv8i8( - <vscale x 8 x double> undef, + <vscale x 8 x double> poison, ptr %0, <vscale x 8 x i8> %1, iXLen %2) |