diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vl-opt.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vl-opt.ll | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll index cd282c265ae4..20608cd6bed8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.ll @@ -198,3 +198,43 @@ define void @fadd_fcmp_select_copy(<vscale x 4 x float> %v, <vscale x 4 x i1> %c call void @llvm.riscv.vsm(<vscale x 4 x i1> %select, ptr %p, iXLen %vl) ret void } + +define <vscale x 8 x i32> @vcompress_cmp(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, iXLen %vl) { +; CHECK-LABEL: vcompress_cmp: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; CHECK-NEXT: vmseq.vv v20, v8, v12 +; CHECK-NEXT: vcompress.vm v8, v16, v20 +; CHECK-NEXT: ret + %cmp = icmp eq <vscale x 8 x i32> %a, %b + %compress = call <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> %c, <vscale x 8 x i1> %cmp, iXLen %vl) + ret <vscale x 8 x i32> %compress +} + +define <vscale x 8 x i32> @vcompress_add(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i1> %c, iXLen %vl) { +; CHECK-LABEL: vcompress_add: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; CHECK-NEXT: vadd.vv v12, v8, v12 +; CHECK-NEXT: vcompress.vm v8, v12, v0 +; CHECK-NEXT: ret + %add = add <vscale x 8 x i32> %a, %b + %compress = call <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(<vscale x 8 x i32> poison, <vscale x 8 x i32> %add, <vscale x 8 x i1> %c, iXLen %vl) + ret <vscale x 8 x i32> %compress +} + +; Make sure we peek through INSERT_SUBREG of tuple registers. +define void @segmented_store_insert_subreg(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, ptr %p, iXLen %vl) { +; CHECK-LABEL: segmented_store_insert_subreg: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma +; CHECK-NEXT: vfadd.vv v10, v8, v10 +; CHECK-NEXT: vsseg3e32.v v8, (a0) +; CHECK-NEXT: ret + %fadd = fadd <vscale x 4 x float> %v0, %v1 + %t0 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.tuple.insert(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) poison, <vscale x 4 x float> %v0, i32 0) + %t1 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.tuple.insert(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %t0, <vscale x 4 x float> %fadd, i32 1) + %t2 = call target("riscv.vector.tuple", <vscale x 16 x i8>, 3) @llvm.riscv.tuple.insert(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %t1, <vscale x 4 x float> %v2, i32 2) + call void @llvm.riscv.vsseg3(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %t2, ptr %p, iXLen %vl, iXLen 5) + ret void +} |
