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Diffstat (limited to 'llvm/test/CodeGen/RISCV/rvv/vadd.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vadd.ll136
1 files changed, 68 insertions, 68 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd.ll b/llvm/test/CodeGen/RISCV/rvv/vadd.ll
index 6c8cab848402..bdc62a974f09 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd.ll
@@ -18,7 +18,7 @@ define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
iXLen %2)
@@ -64,7 +64,7 @@ define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
iXLen %2)
@@ -110,7 +110,7 @@ define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
iXLen %2)
@@ -156,7 +156,7 @@ define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
iXLen %2)
@@ -202,7 +202,7 @@ define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
iXLen %2)
@@ -248,7 +248,7 @@ define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
iXLen %2)
@@ -294,7 +294,7 @@ define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 6
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
iXLen %2)
@@ -341,7 +341,7 @@ define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
iXLen %2)
@@ -387,7 +387,7 @@ define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
iXLen %2)
@@ -433,7 +433,7 @@ define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
iXLen %2)
@@ -479,7 +479,7 @@ define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
iXLen %2)
@@ -525,7 +525,7 @@ define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
iXLen %2)
@@ -571,7 +571,7 @@ define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
iXLen %2)
@@ -618,7 +618,7 @@ define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
iXLen %2)
@@ -664,7 +664,7 @@ define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
iXLen %2)
@@ -710,7 +710,7 @@ define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
iXLen %2)
@@ -756,7 +756,7 @@ define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
iXLen %2)
@@ -802,7 +802,7 @@ define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
iXLen %2)
@@ -849,7 +849,7 @@ define <vscale x 1 x i64> @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
iXLen %2)
@@ -895,7 +895,7 @@ define <vscale x 2 x i64> @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
iXLen %2)
@@ -941,7 +941,7 @@ define <vscale x 4 x i64> @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
iXLen %2)
@@ -987,7 +987,7 @@ define <vscale x 8 x i64> @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
iXLen %2)
@@ -1034,7 +1034,7 @@ define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
i8 %1,
iXLen %2)
@@ -1080,7 +1080,7 @@ define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
i8 %1,
iXLen %2)
@@ -1126,7 +1126,7 @@ define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
i8 %1,
iXLen %2)
@@ -1172,7 +1172,7 @@ define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
i8 %1,
iXLen %2)
@@ -1218,7 +1218,7 @@ define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
i8 %1,
iXLen %2)
@@ -1264,7 +1264,7 @@ define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
i8 %1,
iXLen %2)
@@ -1310,7 +1310,7 @@ define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
i8 %1,
iXLen %2)
@@ -1356,7 +1356,7 @@ define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
i16 %1,
iXLen %2)
@@ -1402,7 +1402,7 @@ define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
i16 %1,
iXLen %2)
@@ -1448,7 +1448,7 @@ define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
i16 %1,
iXLen %2)
@@ -1494,7 +1494,7 @@ define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
i16 %1,
iXLen %2)
@@ -1540,7 +1540,7 @@ define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
i16 %1,
iXLen %2)
@@ -1586,7 +1586,7 @@ define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
i16 %1,
iXLen %2)
@@ -1632,7 +1632,7 @@ define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
i32 %1,
iXLen %2)
@@ -1678,7 +1678,7 @@ define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
i32 %1,
iXLen %2)
@@ -1724,7 +1724,7 @@ define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
i32 %1,
iXLen %2)
@@ -1770,7 +1770,7 @@ define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
i32 %1,
iXLen %2)
@@ -1816,7 +1816,7 @@ define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
i32 %1,
iXLen %2)
@@ -1874,7 +1874,7 @@ define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 %1,
iXLen %2)
@@ -1898,7 +1898,7 @@ define <vscale x 1 x i64> @intrinsic_vadd_vx_sext_nxv1i64_nxv1i64_i64(<vscale x
entry:
%ext = sext i32 %1 to i64
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 %ext,
iXLen %2)
@@ -1917,7 +1917,7 @@ entry:
%load = load i32, ptr %1
%ext = sext i32 %load to i64
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 %ext,
iXLen %2)
@@ -1987,7 +1987,7 @@ define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; RV64-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
i64 %1,
iXLen %2)
@@ -2057,7 +2057,7 @@ define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; RV64-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
i64 %1,
iXLen %2)
@@ -2127,7 +2127,7 @@ define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i
; RV64-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
i64 %1,
iXLen %2)
@@ -2179,7 +2179,7 @@ define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(
- <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> poison,
<vscale x 1 x i8> %0,
i8 9,
iXLen %1)
@@ -2212,7 +2212,7 @@ define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(
- <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> poison,
<vscale x 2 x i8> %0,
i8 9,
iXLen %1)
@@ -2245,7 +2245,7 @@ define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(
- <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> poison,
<vscale x 4 x i8> %0,
i8 9,
iXLen %1)
@@ -2278,7 +2278,7 @@ define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(
- <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> poison,
<vscale x 8 x i8> %0,
i8 9,
iXLen %1)
@@ -2311,7 +2311,7 @@ define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(
- <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> poison,
<vscale x 16 x i8> %0,
i8 9,
iXLen %1)
@@ -2344,7 +2344,7 @@ define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(
- <vscale x 32 x i8> undef,
+ <vscale x 32 x i8> poison,
<vscale x 32 x i8> %0,
i8 9,
iXLen %1)
@@ -2377,7 +2377,7 @@ define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(
- <vscale x 64 x i8> undef,
+ <vscale x 64 x i8> poison,
<vscale x 64 x i8> %0,
i8 -9,
iXLen %1)
@@ -2410,7 +2410,7 @@ define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(
- <vscale x 1 x i16> undef,
+ <vscale x 1 x i16> poison,
<vscale x 1 x i16> %0,
i16 9,
iXLen %1)
@@ -2443,7 +2443,7 @@ define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(
- <vscale x 2 x i16> undef,
+ <vscale x 2 x i16> poison,
<vscale x 2 x i16> %0,
i16 9,
iXLen %1)
@@ -2476,7 +2476,7 @@ define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(
- <vscale x 4 x i16> undef,
+ <vscale x 4 x i16> poison,
<vscale x 4 x i16> %0,
i16 9,
iXLen %1)
@@ -2509,7 +2509,7 @@ define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(
- <vscale x 8 x i16> undef,
+ <vscale x 8 x i16> poison,
<vscale x 8 x i16> %0,
i16 9,
iXLen %1)
@@ -2542,7 +2542,7 @@ define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(
- <vscale x 16 x i16> undef,
+ <vscale x 16 x i16> poison,
<vscale x 16 x i16> %0,
i16 9,
iXLen %1)
@@ -2575,7 +2575,7 @@ define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(
- <vscale x 32 x i16> undef,
+ <vscale x 32 x i16> poison,
<vscale x 32 x i16> %0,
i16 9,
iXLen %1)
@@ -2608,7 +2608,7 @@ define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(
- <vscale x 1 x i32> undef,
+ <vscale x 1 x i32> poison,
<vscale x 1 x i32> %0,
i32 9,
iXLen %1)
@@ -2641,7 +2641,7 @@ define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(
- <vscale x 2 x i32> undef,
+ <vscale x 2 x i32> poison,
<vscale x 2 x i32> %0,
i32 9,
iXLen %1)
@@ -2674,7 +2674,7 @@ define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(
- <vscale x 4 x i32> undef,
+ <vscale x 4 x i32> poison,
<vscale x 4 x i32> %0,
i32 9,
iXLen %1)
@@ -2707,7 +2707,7 @@ define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(
- <vscale x 8 x i32> undef,
+ <vscale x 8 x i32> poison,
<vscale x 8 x i32> %0,
i32 9,
iXLen %1)
@@ -2740,7 +2740,7 @@ define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(
- <vscale x 16 x i32> undef,
+ <vscale x 16 x i32> poison,
<vscale x 16 x i32> %0,
i32 9,
iXLen %1)
@@ -2773,7 +2773,7 @@ define <vscale x 1 x i64> @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(
- <vscale x 1 x i64> undef,
+ <vscale x 1 x i64> poison,
<vscale x 1 x i64> %0,
i64 9,
iXLen %1)
@@ -2806,7 +2806,7 @@ define <vscale x 2 x i64> @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(
- <vscale x 2 x i64> undef,
+ <vscale x 2 x i64> poison,
<vscale x 2 x i64> %0,
i64 9,
iXLen %1)
@@ -2839,7 +2839,7 @@ define <vscale x 4 x i64> @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(
- <vscale x 4 x i64> undef,
+ <vscale x 4 x i64> poison,
<vscale x 4 x i64> %0,
i64 9,
iXLen %1)
@@ -2872,7 +2872,7 @@ define <vscale x 8 x i64> @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(
- <vscale x 8 x i64> undef,
+ <vscale x 8 x i64> poison,
<vscale x 8 x i64> %0,
i64 9,
iXLen %1)
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:52:54 +0000