1 files changed, 40 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll b/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
index b3c22a5322cb..b23f4f581200 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
@@ -220,3 +220,43 @@ define signext i32 @test14(ptr %0, ptr %1, i64 %2) {
   %12 = add i32 %9, %11
   ret i32 %12
 }
+
+; Test that we can propagate sign bits through sraw. We should use an slli
+; instead of slliw.
+define signext i32 @test15(i32 signext %x, i32 signext %y) {
+; RV64I-LABEL: test15:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 1
+; RV64I-NEXT:    sraw a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 1
+; RV64I-NEXT:    ret
+  %a = ashr i32 %x, 1
+  %b = ashr i32 %a, %y
+  %c = shl i32 %b, 1
+  ret i32 %c
+}
+
+define signext i32 @test16(i32 signext %x, i32 signext %y) {
+; RV64I-LABEL: test16:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    ori a2, a0, 192
+; RV64I-NEXT:    srli a3, a0, 8
+; RV64I-NEXT:    lui a4, 16
+; RV64I-NEXT:    srliw a0, a0, 24
+; RV64I-NEXT:    addi a4, a4, -256
+; RV64I-NEXT:    and a3, a3, a4
+; RV64I-NEXT:    and a4, a2, a4
+; RV64I-NEXT:    or a0, a3, a0
+; RV64I-NEXT:    slli a4, a4, 8
+; RV64I-NEXT:    slli a2, a2, 24
+; RV64I-NEXT:    or a2, a2, a4
+; RV64I-NEXT:    or a0, a2, a0
+; RV64I-NEXT:    sraw a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 1
+; RV64I-NEXT:    ret
+  %a = or i32 %x, 192
+  %d = call i32 @llvm.bswap.i32(i32 %a)
+  %b = ashr i32 %d, %y
+  %c = shl i32 %b, 1
+  ret i32 %c
+}