diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/llvm.frexp.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/llvm.frexp.ll | 468 |
1 files changed, 234 insertions, 234 deletions
diff --git a/llvm/test/CodeGen/RISCV/llvm.frexp.ll b/llvm/test/CodeGen/RISCV/llvm.frexp.ll index 2c9d640e03a6..e85a7118f5ff 100644 --- a/llvm/test/CodeGen/RISCV/llvm.frexp.ll +++ b/llvm/test/CodeGen/RISCV/llvm.frexp.ll @@ -568,18 +568,18 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV32IFD-NEXT: addi a0, sp, 20 ; RV32IFD-NEXT: fmv.s fa0, fs0 ; RV32IFD-NEXT: call frexpf -; RV32IFD-NEXT: lw a0, 20(sp) -; RV32IFD-NEXT: lw a1, 16(sp) -; RV32IFD-NEXT: lw a2, 12(sp) -; RV32IFD-NEXT: lw a3, 8(sp) -; RV32IFD-NEXT: sw a0, 28(s0) -; RV32IFD-NEXT: sw a1, 24(s0) -; RV32IFD-NEXT: sw a2, 20(s0) -; RV32IFD-NEXT: sw a3, 16(s0) -; RV32IFD-NEXT: fsw fa0, 12(s0) -; RV32IFD-NEXT: fsw fs1, 8(s0) -; RV32IFD-NEXT: fsw fs2, 4(s0) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: lw a2, 16(sp) +; RV32IFD-NEXT: lw a3, 20(sp) +; RV32IFD-NEXT: sw a0, 16(s0) +; RV32IFD-NEXT: sw a1, 20(s0) +; RV32IFD-NEXT: sw a2, 24(s0) +; RV32IFD-NEXT: sw a3, 28(s0) ; RV32IFD-NEXT: fsw fs3, 0(s0) +; RV32IFD-NEXT: fsw fs2, 4(s0) +; RV32IFD-NEXT: fsw fs1, 8(s0) +; RV32IFD-NEXT: fsw fa0, 12(s0) ; RV32IFD-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 56(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 48(sp) # 8-byte Folded Reload @@ -616,18 +616,18 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV64IFD-NEXT: addi a0, sp, 24 ; RV64IFD-NEXT: fmv.s fa0, fs0 ; RV64IFD-NEXT: call frexpf -; RV64IFD-NEXT: ld a0, 24(sp) -; RV64IFD-NEXT: ld a1, 16(sp) -; RV64IFD-NEXT: ld a2, 8(sp) -; RV64IFD-NEXT: ld a3, 0(sp) -; RV64IFD-NEXT: sw a0, 28(s0) -; RV64IFD-NEXT: sw a1, 24(s0) -; RV64IFD-NEXT: sw a2, 20(s0) -; RV64IFD-NEXT: sw a3, 16(s0) -; RV64IFD-NEXT: fsw fa0, 12(s0) -; RV64IFD-NEXT: fsw fs1, 8(s0) -; RV64IFD-NEXT: fsw fs2, 4(s0) +; RV64IFD-NEXT: ld a0, 0(sp) +; RV64IFD-NEXT: ld a1, 8(sp) +; RV64IFD-NEXT: ld a2, 16(sp) +; RV64IFD-NEXT: ld a3, 24(sp) +; RV64IFD-NEXT: sw a0, 16(s0) +; RV64IFD-NEXT: sw a1, 20(s0) +; RV64IFD-NEXT: sw a2, 24(s0) +; RV64IFD-NEXT: sw a3, 28(s0) ; RV64IFD-NEXT: fsw fs3, 0(s0) +; RV64IFD-NEXT: fsw fs2, 4(s0) +; RV64IFD-NEXT: fsw fs1, 8(s0) +; RV64IFD-NEXT: fsw fa0, 12(s0) ; RV64IFD-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 56(sp) # 8-byte Folded Reload @@ -666,18 +666,18 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV32IZFINXZDINX-NEXT: addi a1, sp, 20 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call frexpf -; RV32IZFINXZDINX-NEXT: lw a1, 20(sp) -; RV32IZFINXZDINX-NEXT: lw a2, 16(sp) -; RV32IZFINXZDINX-NEXT: lw a3, 12(sp) -; RV32IZFINXZDINX-NEXT: lw a4, 8(sp) -; RV32IZFINXZDINX-NEXT: sw a1, 28(s3) -; RV32IZFINXZDINX-NEXT: sw a2, 24(s3) -; RV32IZFINXZDINX-NEXT: sw a3, 20(s3) -; RV32IZFINXZDINX-NEXT: sw a4, 16(s3) -; RV32IZFINXZDINX-NEXT: sw a0, 12(s3) -; RV32IZFINXZDINX-NEXT: sw s1, 8(s3) -; RV32IZFINXZDINX-NEXT: sw s2, 4(s3) +; RV32IZFINXZDINX-NEXT: lw a1, 8(sp) +; RV32IZFINXZDINX-NEXT: lw a2, 12(sp) +; RV32IZFINXZDINX-NEXT: lw a3, 16(sp) +; RV32IZFINXZDINX-NEXT: lw a4, 20(sp) +; RV32IZFINXZDINX-NEXT: sw a1, 16(s3) +; RV32IZFINXZDINX-NEXT: sw a2, 20(s3) +; RV32IZFINXZDINX-NEXT: sw a3, 24(s3) +; RV32IZFINXZDINX-NEXT: sw a4, 28(s3) ; RV32IZFINXZDINX-NEXT: sw s4, 0(s3) +; RV32IZFINXZDINX-NEXT: sw s2, 4(s3) +; RV32IZFINXZDINX-NEXT: sw s1, 8(s3) +; RV32IZFINXZDINX-NEXT: sw a0, 12(s3) ; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 36(sp) # 4-byte Folded Reload @@ -716,18 +716,18 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV64IZFINXZDINX-NEXT: addi a1, sp, 24 ; RV64IZFINXZDINX-NEXT: mv a0, s0 ; RV64IZFINXZDINX-NEXT: call frexpf -; RV64IZFINXZDINX-NEXT: ld a1, 24(sp) -; RV64IZFINXZDINX-NEXT: ld a2, 16(sp) -; RV64IZFINXZDINX-NEXT: ld a3, 8(sp) -; RV64IZFINXZDINX-NEXT: ld a4, 0(sp) -; RV64IZFINXZDINX-NEXT: sw a1, 28(s3) -; RV64IZFINXZDINX-NEXT: sw a2, 24(s3) -; RV64IZFINXZDINX-NEXT: sw a3, 20(s3) -; RV64IZFINXZDINX-NEXT: sw a4, 16(s3) -; RV64IZFINXZDINX-NEXT: sw a0, 12(s3) -; RV64IZFINXZDINX-NEXT: sw s1, 8(s3) -; RV64IZFINXZDINX-NEXT: sw s2, 4(s3) +; RV64IZFINXZDINX-NEXT: ld a1, 0(sp) +; RV64IZFINXZDINX-NEXT: ld a2, 8(sp) +; RV64IZFINXZDINX-NEXT: ld a3, 16(sp) +; RV64IZFINXZDINX-NEXT: ld a4, 24(sp) +; RV64IZFINXZDINX-NEXT: sw a1, 16(s3) +; RV64IZFINXZDINX-NEXT: sw a2, 20(s3) +; RV64IZFINXZDINX-NEXT: sw a3, 24(s3) +; RV64IZFINXZDINX-NEXT: sw a4, 28(s3) ; RV64IZFINXZDINX-NEXT: sw s4, 0(s3) +; RV64IZFINXZDINX-NEXT: sw s2, 4(s3) +; RV64IZFINXZDINX-NEXT: sw s1, 8(s3) +; RV64IZFINXZDINX-NEXT: sw a0, 12(s3) ; RV64IZFINXZDINX-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s1, 56(sp) # 8-byte Folded Reload @@ -770,14 +770,14 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV32I-NEXT: lw a2, 12(sp) ; RV32I-NEXT: lw a3, 16(sp) ; RV32I-NEXT: lw a4, 20(sp) -; RV32I-NEXT: sw a0, 12(s3) -; RV32I-NEXT: sw s1, 8(s3) -; RV32I-NEXT: sw s0, 4(s3) ; RV32I-NEXT: sw s4, 0(s3) -; RV32I-NEXT: sw a4, 28(s3) -; RV32I-NEXT: sw a3, 24(s3) -; RV32I-NEXT: sw a2, 20(s3) +; RV32I-NEXT: sw s0, 4(s3) +; RV32I-NEXT: sw s1, 8(s3) +; RV32I-NEXT: sw a0, 12(s3) ; RV32I-NEXT: sw a1, 16(s3) +; RV32I-NEXT: sw a2, 20(s3) +; RV32I-NEXT: sw a3, 24(s3) +; RV32I-NEXT: sw a4, 28(s3) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload @@ -820,14 +820,14 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi ; RV64I-NEXT: lw a2, 4(sp) ; RV64I-NEXT: lw a3, 8(sp) ; RV64I-NEXT: lw a4, 12(sp) -; RV64I-NEXT: sw a0, 12(s3) -; RV64I-NEXT: sw s1, 8(s3) -; RV64I-NEXT: sw s0, 4(s3) ; RV64I-NEXT: sw s4, 0(s3) -; RV64I-NEXT: sw a4, 28(s3) -; RV64I-NEXT: sw a3, 24(s3) -; RV64I-NEXT: sw a2, 20(s3) +; RV64I-NEXT: sw s0, 4(s3) +; RV64I-NEXT: sw s1, 8(s3) +; RV64I-NEXT: sw a0, 12(s3) ; RV64I-NEXT: sw a1, 16(s3) +; RV64I-NEXT: sw a2, 20(s3) +; RV64I-NEXT: sw a3, 24(s3) +; RV64I-NEXT: sw a4, 28(s3) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload @@ -868,10 +868,10 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV32IFD-NEXT: addi a0, sp, 20 ; RV32IFD-NEXT: fmv.s fa0, fs0 ; RV32IFD-NEXT: call frexpf -; RV32IFD-NEXT: fsw fa0, 12(s0) -; RV32IFD-NEXT: fsw fs1, 8(s0) -; RV32IFD-NEXT: fsw fs2, 4(s0) ; RV32IFD-NEXT: fsw fs3, 0(s0) +; RV32IFD-NEXT: fsw fs2, 4(s0) +; RV32IFD-NEXT: fsw fs1, 8(s0) +; RV32IFD-NEXT: fsw fa0, 12(s0) ; RV32IFD-NEXT: lw ra, 60(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 56(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 48(sp) # 8-byte Folded Reload @@ -908,10 +908,10 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV64IFD-NEXT: addi a0, sp, 24 ; RV64IFD-NEXT: fmv.s fa0, fs0 ; RV64IFD-NEXT: call frexpf -; RV64IFD-NEXT: fsw fa0, 12(s0) -; RV64IFD-NEXT: fsw fs1, 8(s0) -; RV64IFD-NEXT: fsw fs2, 4(s0) ; RV64IFD-NEXT: fsw fs3, 0(s0) +; RV64IFD-NEXT: fsw fs2, 4(s0) +; RV64IFD-NEXT: fsw fs1, 8(s0) +; RV64IFD-NEXT: fsw fa0, 12(s0) ; RV64IFD-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 56(sp) # 8-byte Folded Reload @@ -950,10 +950,10 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV32IZFINXZDINX-NEXT: addi a1, sp, 20 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call frexpf -; RV32IZFINXZDINX-NEXT: sw a0, 12(s3) -; RV32IZFINXZDINX-NEXT: sw s1, 8(s3) -; RV32IZFINXZDINX-NEXT: sw s2, 4(s3) ; RV32IZFINXZDINX-NEXT: sw s4, 0(s3) +; RV32IZFINXZDINX-NEXT: sw s2, 4(s3) +; RV32IZFINXZDINX-NEXT: sw s1, 8(s3) +; RV32IZFINXZDINX-NEXT: sw a0, 12(s3) ; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 36(sp) # 4-byte Folded Reload @@ -992,10 +992,10 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV64IZFINXZDINX-NEXT: addi a1, sp, 24 ; RV64IZFINXZDINX-NEXT: mv a0, s0 ; RV64IZFINXZDINX-NEXT: call frexpf -; RV64IZFINXZDINX-NEXT: sw a0, 12(s3) -; RV64IZFINXZDINX-NEXT: sw s1, 8(s3) -; RV64IZFINXZDINX-NEXT: sw s2, 4(s3) ; RV64IZFINXZDINX-NEXT: sw s4, 0(s3) +; RV64IZFINXZDINX-NEXT: sw s2, 4(s3) +; RV64IZFINXZDINX-NEXT: sw s1, 8(s3) +; RV64IZFINXZDINX-NEXT: sw a0, 12(s3) ; RV64IZFINXZDINX-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s1, 56(sp) # 8-byte Folded Reload @@ -1034,10 +1034,10 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV32I-NEXT: addi a1, sp, 20 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call frexpf -; RV32I-NEXT: sw a0, 12(s3) -; RV32I-NEXT: sw s1, 8(s3) -; RV32I-NEXT: sw s0, 4(s3) ; RV32I-NEXT: sw s4, 0(s3) +; RV32I-NEXT: sw s0, 4(s3) +; RV32I-NEXT: sw s1, 8(s3) +; RV32I-NEXT: sw a0, 12(s3) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload @@ -1076,10 +1076,10 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi ; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call frexpf -; RV64I-NEXT: sw a0, 12(s3) -; RV64I-NEXT: sw s1, 8(s3) -; RV64I-NEXT: sw s0, 4(s3) ; RV64I-NEXT: sw s4, 0(s3) +; RV64I-NEXT: sw s0, 4(s3) +; RV64I-NEXT: sw s1, 8(s3) +; RV64I-NEXT: sw a0, 12(s3) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload @@ -1117,14 +1117,14 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV32IFD-NEXT: addi a0, sp, 12 ; RV32IFD-NEXT: fmv.s fa0, fs0 ; RV32IFD-NEXT: call frexpf -; RV32IFD-NEXT: lw a0, 12(sp) -; RV32IFD-NEXT: lw a1, 8(sp) -; RV32IFD-NEXT: lw a2, 4(sp) -; RV32IFD-NEXT: lw a3, 0(sp) -; RV32IFD-NEXT: sw a0, 12(s0) -; RV32IFD-NEXT: sw a1, 8(s0) -; RV32IFD-NEXT: sw a2, 4(s0) -; RV32IFD-NEXT: sw a3, 0(s0) +; RV32IFD-NEXT: lw a0, 0(sp) +; RV32IFD-NEXT: lw a1, 4(sp) +; RV32IFD-NEXT: lw a2, 8(sp) +; RV32IFD-NEXT: lw a3, 12(sp) +; RV32IFD-NEXT: sw a0, 0(s0) +; RV32IFD-NEXT: sw a1, 4(s0) +; RV32IFD-NEXT: sw a2, 8(s0) +; RV32IFD-NEXT: sw a3, 12(s0) ; RV32IFD-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 32(sp) # 8-byte Folded Reload @@ -1156,14 +1156,14 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV64IFD-NEXT: addi a0, sp, 32 ; RV64IFD-NEXT: fmv.s fa0, fs0 ; RV64IFD-NEXT: call frexpf -; RV64IFD-NEXT: ld a0, 32(sp) -; RV64IFD-NEXT: ld a1, 24(sp) -; RV64IFD-NEXT: ld a2, 16(sp) -; RV64IFD-NEXT: ld a3, 8(sp) -; RV64IFD-NEXT: sw a0, 12(s0) -; RV64IFD-NEXT: sw a1, 8(s0) -; RV64IFD-NEXT: sw a2, 4(s0) -; RV64IFD-NEXT: sw a3, 0(s0) +; RV64IFD-NEXT: ld a0, 8(sp) +; RV64IFD-NEXT: ld a1, 16(sp) +; RV64IFD-NEXT: ld a2, 24(sp) +; RV64IFD-NEXT: ld a3, 32(sp) +; RV64IFD-NEXT: sw a0, 0(s0) +; RV64IFD-NEXT: sw a1, 4(s0) +; RV64IFD-NEXT: sw a2, 8(s0) +; RV64IFD-NEXT: sw a3, 12(s0) ; RV64IFD-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: fld fs0, 56(sp) # 8-byte Folded Reload @@ -1197,14 +1197,14 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi a1, sp, 24 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call frexpf -; RV32IZFINXZDINX-NEXT: lw a0, 24(sp) -; RV32IZFINXZDINX-NEXT: lw a1, 20(sp) -; RV32IZFINXZDINX-NEXT: lw a2, 16(sp) -; RV32IZFINXZDINX-NEXT: lw a3, 12(sp) -; RV32IZFINXZDINX-NEXT: sw a0, 12(s3) -; RV32IZFINXZDINX-NEXT: sw a1, 8(s3) -; RV32IZFINXZDINX-NEXT: sw a2, 4(s3) -; RV32IZFINXZDINX-NEXT: sw a3, 0(s3) +; RV32IZFINXZDINX-NEXT: lw a0, 12(sp) +; RV32IZFINXZDINX-NEXT: lw a1, 16(sp) +; RV32IZFINXZDINX-NEXT: lw a2, 20(sp) +; RV32IZFINXZDINX-NEXT: lw a3, 24(sp) +; RV32IZFINXZDINX-NEXT: sw a0, 0(s3) +; RV32IZFINXZDINX-NEXT: sw a1, 4(s3) +; RV32IZFINXZDINX-NEXT: sw a2, 8(s3) +; RV32IZFINXZDINX-NEXT: sw a3, 12(s3) ; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 36(sp) # 4-byte Folded Reload @@ -1238,14 +1238,14 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV64IZFINXZDINX-NEXT: addi a1, sp, 32 ; RV64IZFINXZDINX-NEXT: mv a0, s0 ; RV64IZFINXZDINX-NEXT: call frexpf -; RV64IZFINXZDINX-NEXT: ld a0, 32(sp) -; RV64IZFINXZDINX-NEXT: ld a1, 24(sp) -; RV64IZFINXZDINX-NEXT: ld a2, 16(sp) -; RV64IZFINXZDINX-NEXT: ld a3, 8(sp) -; RV64IZFINXZDINX-NEXT: sw a0, 12(s3) -; RV64IZFINXZDINX-NEXT: sw a1, 8(s3) -; RV64IZFINXZDINX-NEXT: sw a2, 4(s3) -; RV64IZFINXZDINX-NEXT: sw a3, 0(s3) +; RV64IZFINXZDINX-NEXT: ld a0, 8(sp) +; RV64IZFINXZDINX-NEXT: ld a1, 16(sp) +; RV64IZFINXZDINX-NEXT: ld a2, 24(sp) +; RV64IZFINXZDINX-NEXT: ld a3, 32(sp) +; RV64IZFINXZDINX-NEXT: sw a0, 0(s3) +; RV64IZFINXZDINX-NEXT: sw a1, 4(s3) +; RV64IZFINXZDINX-NEXT: sw a2, 8(s3) +; RV64IZFINXZDINX-NEXT: sw a3, 12(s3) ; RV64IZFINXZDINX-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s1, 56(sp) # 8-byte Folded Reload @@ -1279,14 +1279,14 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV32I-NEXT: addi a1, sp, 24 ; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: call frexpf -; RV32I-NEXT: lw a0, 24(sp) -; RV32I-NEXT: lw a1, 20(sp) -; RV32I-NEXT: lw a2, 16(sp) -; RV32I-NEXT: lw a3, 12(sp) -; RV32I-NEXT: sw a0, 12(s3) -; RV32I-NEXT: sw a1, 8(s3) -; RV32I-NEXT: sw a2, 4(s3) -; RV32I-NEXT: sw a3, 0(s3) +; RV32I-NEXT: lw a0, 12(sp) +; RV32I-NEXT: lw a1, 16(sp) +; RV32I-NEXT: lw a2, 20(sp) +; RV32I-NEXT: lw a3, 24(sp) +; RV32I-NEXT: sw a0, 0(s3) +; RV32I-NEXT: sw a1, 4(s3) +; RV32I-NEXT: sw a2, 8(s3) +; RV32I-NEXT: sw a3, 12(s3) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload @@ -1320,14 +1320,14 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind { ; RV64I-NEXT: addi a1, sp, 20 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call frexpf -; RV64I-NEXT: lw a0, 20(sp) -; RV64I-NEXT: lw a1, 16(sp) -; RV64I-NEXT: lw a2, 12(sp) -; RV64I-NEXT: lw a3, 8(sp) -; RV64I-NEXT: sw a0, 12(s3) -; RV64I-NEXT: sw a1, 8(s3) -; RV64I-NEXT: sw a2, 4(s3) -; RV64I-NEXT: sw a3, 0(s3) +; RV64I-NEXT: lw a0, 8(sp) +; RV64I-NEXT: lw a1, 12(sp) +; RV64I-NEXT: lw a2, 16(sp) +; RV64I-NEXT: lw a3, 20(sp) +; RV64I-NEXT: sw a0, 0(s3) +; RV64I-NEXT: sw a1, 4(s3) +; RV64I-NEXT: sw a2, 8(s3) +; RV64I-NEXT: sw a3, 12(s3) ; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload @@ -1397,8 +1397,8 @@ define { double, i32 } @test_frexp_f64_i32(double %a) nounwind { ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: call frexp ; RV32I-NEXT: lw a2, 4(sp) -; RV32I-NEXT: sw a1, 4(s0) ; RV32I-NEXT: sw a0, 0(s0) +; RV32I-NEXT: sw a1, 4(s0) ; RV32I-NEXT: sw a2, 8(s0) ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -1580,28 +1580,28 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV32IFD-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: lw a3, 0(a1) -; RV32IFD-NEXT: lw a2, 4(a1) -; RV32IFD-NEXT: lw a4, 8(a1) -; RV32IFD-NEXT: lw a1, 12(a1) +; RV32IFD-NEXT: lw a4, 4(a1) +; RV32IFD-NEXT: lw a5, 8(a1) +; RV32IFD-NEXT: lw a6, 12(a1) ; RV32IFD-NEXT: mv s0, a0 -; RV32IFD-NEXT: sw a1, 12(sp) -; RV32IFD-NEXT: sw a4, 8(sp) -; RV32IFD-NEXT: sw a2, 4(sp) ; RV32IFD-NEXT: addi a0, sp, 16 ; RV32IFD-NEXT: mv a1, sp ; RV32IFD-NEXT: addi a2, sp, 36 ; RV32IFD-NEXT: sw a3, 0(sp) +; RV32IFD-NEXT: sw a4, 4(sp) +; RV32IFD-NEXT: sw a5, 8(sp) +; RV32IFD-NEXT: sw a6, 12(sp) ; RV32IFD-NEXT: call frexpl -; RV32IFD-NEXT: lw a0, 24(sp) -; RV32IFD-NEXT: lw a1, 28(sp) -; RV32IFD-NEXT: lw a2, 16(sp) -; RV32IFD-NEXT: lw a3, 20(sp) -; RV32IFD-NEXT: lw a4, 36(sp) -; RV32IFD-NEXT: sw a1, 12(s0) -; RV32IFD-NEXT: sw a0, 8(s0) -; RV32IFD-NEXT: sw a3, 4(s0) -; RV32IFD-NEXT: sw a2, 0(s0) -; RV32IFD-NEXT: sw a4, 16(s0) +; RV32IFD-NEXT: lw a0, 36(sp) +; RV32IFD-NEXT: lw a1, 16(sp) +; RV32IFD-NEXT: lw a2, 20(sp) +; RV32IFD-NEXT: lw a3, 24(sp) +; RV32IFD-NEXT: lw a4, 28(sp) +; RV32IFD-NEXT: sw a1, 0(s0) +; RV32IFD-NEXT: sw a2, 4(s0) +; RV32IFD-NEXT: sw a3, 8(s0) +; RV32IFD-NEXT: sw a4, 12(s0) +; RV32IFD-NEXT: sw a0, 16(s0) ; RV32IFD-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 48 @@ -1619,8 +1619,8 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV64IFD-NEXT: mv a1, a3 ; RV64IFD-NEXT: call frexpl ; RV64IFD-NEXT: lw a2, 12(sp) -; RV64IFD-NEXT: sd a1, 8(s0) ; RV64IFD-NEXT: sd a0, 0(s0) +; RV64IFD-NEXT: sd a1, 8(s0) ; RV64IFD-NEXT: sw a2, 16(s0) ; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -1633,28 +1633,28 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: lw a3, 0(a1) -; RV32IZFINXZDINX-NEXT: lw a2, 4(a1) -; RV32IZFINXZDINX-NEXT: lw a4, 8(a1) -; RV32IZFINXZDINX-NEXT: lw a1, 12(a1) +; RV32IZFINXZDINX-NEXT: lw a4, 4(a1) +; RV32IZFINXZDINX-NEXT: lw a5, 8(a1) +; RV32IZFINXZDINX-NEXT: lw a6, 12(a1) ; RV32IZFINXZDINX-NEXT: mv s0, a0 -; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) -; RV32IZFINXZDINX-NEXT: sw a4, 8(sp) -; RV32IZFINXZDINX-NEXT: sw a2, 4(sp) ; RV32IZFINXZDINX-NEXT: addi a0, sp, 16 ; RV32IZFINXZDINX-NEXT: mv a1, sp ; RV32IZFINXZDINX-NEXT: addi a2, sp, 36 ; RV32IZFINXZDINX-NEXT: sw a3, 0(sp) +; RV32IZFINXZDINX-NEXT: sw a4, 4(sp) +; RV32IZFINXZDINX-NEXT: sw a5, 8(sp) +; RV32IZFINXZDINX-NEXT: sw a6, 12(sp) ; RV32IZFINXZDINX-NEXT: call frexpl -; RV32IZFINXZDINX-NEXT: lw a0, 24(sp) -; RV32IZFINXZDINX-NEXT: lw a1, 28(sp) -; RV32IZFINXZDINX-NEXT: lw a2, 16(sp) -; RV32IZFINXZDINX-NEXT: lw a3, 20(sp) -; RV32IZFINXZDINX-NEXT: lw a4, 36(sp) -; RV32IZFINXZDINX-NEXT: sw a1, 12(s0) -; RV32IZFINXZDINX-NEXT: sw a0, 8(s0) -; RV32IZFINXZDINX-NEXT: sw a3, 4(s0) -; RV32IZFINXZDINX-NEXT: sw a2, 0(s0) -; RV32IZFINXZDINX-NEXT: sw a4, 16(s0) +; RV32IZFINXZDINX-NEXT: lw a0, 36(sp) +; RV32IZFINXZDINX-NEXT: lw a1, 16(sp) +; RV32IZFINXZDINX-NEXT: lw a2, 20(sp) +; RV32IZFINXZDINX-NEXT: lw a3, 24(sp) +; RV32IZFINXZDINX-NEXT: lw a4, 28(sp) +; RV32IZFINXZDINX-NEXT: sw a1, 0(s0) +; RV32IZFINXZDINX-NEXT: sw a2, 4(s0) +; RV32IZFINXZDINX-NEXT: sw a3, 8(s0) +; RV32IZFINXZDINX-NEXT: sw a4, 12(s0) +; RV32IZFINXZDINX-NEXT: sw a0, 16(s0) ; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 48 @@ -1672,8 +1672,8 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV64IZFINXZDINX-NEXT: mv a1, a3 ; RV64IZFINXZDINX-NEXT: call frexpl ; RV64IZFINXZDINX-NEXT: lw a2, 12(sp) -; RV64IZFINXZDINX-NEXT: sd a1, 8(s0) ; RV64IZFINXZDINX-NEXT: sd a0, 0(s0) +; RV64IZFINXZDINX-NEXT: sd a1, 8(s0) ; RV64IZFINXZDINX-NEXT: sw a2, 16(s0) ; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64IZFINXZDINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -1686,28 +1686,28 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a3, 0(a1) -; RV32I-NEXT: lw a2, 4(a1) -; RV32I-NEXT: lw a4, 8(a1) -; RV32I-NEXT: lw a1, 12(a1) +; RV32I-NEXT: lw a4, 4(a1) +; RV32I-NEXT: lw a5, 8(a1) +; RV32I-NEXT: lw a6, 12(a1) ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: sw a1, 12(sp) -; RV32I-NEXT: sw a4, 8(sp) -; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: addi a0, sp, 16 ; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: addi a2, sp, 36 ; RV32I-NEXT: sw a3, 0(sp) +; RV32I-NEXT: sw a4, 4(sp) +; RV32I-NEXT: sw a5, 8(sp) +; RV32I-NEXT: sw a6, 12(sp) ; RV32I-NEXT: call frexpl -; RV32I-NEXT: lw a0, 24(sp) -; RV32I-NEXT: lw a1, 28(sp) -; RV32I-NEXT: lw a2, 16(sp) -; RV32I-NEXT: lw a3, 20(sp) -; RV32I-NEXT: lw a4, 36(sp) -; RV32I-NEXT: sw a1, 12(s0) -; RV32I-NEXT: sw a0, 8(s0) -; RV32I-NEXT: sw a3, 4(s0) -; RV32I-NEXT: sw a2, 0(s0) -; RV32I-NEXT: sw a4, 16(s0) +; RV32I-NEXT: lw a0, 36(sp) +; RV32I-NEXT: lw a1, 16(sp) +; RV32I-NEXT: lw a2, 20(sp) +; RV32I-NEXT: lw a3, 24(sp) +; RV32I-NEXT: lw a4, 28(sp) +; RV32I-NEXT: sw a1, 0(s0) +; RV32I-NEXT: sw a2, 4(s0) +; RV32I-NEXT: sw a3, 8(s0) +; RV32I-NEXT: sw a4, 12(s0) +; RV32I-NEXT: sw a0, 16(s0) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 48 @@ -1725,8 +1725,8 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind { ; RV64I-NEXT: mv a1, a3 ; RV64I-NEXT: call frexpl ; RV64I-NEXT: lw a2, 12(sp) -; RV64I-NEXT: sd a1, 8(s0) ; RV64I-NEXT: sd a0, 0(s0) +; RV64I-NEXT: sd a1, 8(s0) ; RV64I-NEXT: sw a2, 16(s0) ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -1743,26 +1743,26 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV32IFD-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: lw a3, 0(a1) -; RV32IFD-NEXT: lw a2, 4(a1) -; RV32IFD-NEXT: lw a4, 8(a1) -; RV32IFD-NEXT: lw a1, 12(a1) +; RV32IFD-NEXT: lw a4, 4(a1) +; RV32IFD-NEXT: lw a5, 8(a1) +; RV32IFD-NEXT: lw a6, 12(a1) ; RV32IFD-NEXT: mv s0, a0 -; RV32IFD-NEXT: sw a1, 12(sp) -; RV32IFD-NEXT: sw a4, 8(sp) -; RV32IFD-NEXT: sw a2, 4(sp) ; RV32IFD-NEXT: addi a0, sp, 16 ; RV32IFD-NEXT: mv a1, sp ; RV32IFD-NEXT: addi a2, sp, 36 ; RV32IFD-NEXT: sw a3, 0(sp) +; RV32IFD-NEXT: sw a4, 4(sp) +; RV32IFD-NEXT: sw a5, 8(sp) +; RV32IFD-NEXT: sw a6, 12(sp) ; RV32IFD-NEXT: call frexpl -; RV32IFD-NEXT: lw a0, 28(sp) -; RV32IFD-NEXT: lw a1, 24(sp) -; RV32IFD-NEXT: lw a2, 20(sp) -; RV32IFD-NEXT: lw a3, 16(sp) -; RV32IFD-NEXT: sw a0, 12(s0) -; RV32IFD-NEXT: sw a1, 8(s0) -; RV32IFD-NEXT: sw a2, 4(s0) -; RV32IFD-NEXT: sw a3, 0(s0) +; RV32IFD-NEXT: lw a0, 16(sp) +; RV32IFD-NEXT: lw a1, 20(sp) +; RV32IFD-NEXT: lw a2, 24(sp) +; RV32IFD-NEXT: lw a3, 28(sp) +; RV32IFD-NEXT: sw a0, 0(s0) +; RV32IFD-NEXT: sw a1, 4(s0) +; RV32IFD-NEXT: sw a2, 8(s0) +; RV32IFD-NEXT: sw a3, 12(s0) ; RV32IFD-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 48 @@ -1784,26 +1784,26 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: lw a3, 0(a1) -; RV32IZFINXZDINX-NEXT: lw a2, 4(a1) -; RV32IZFINXZDINX-NEXT: lw a4, 8(a1) -; RV32IZFINXZDINX-NEXT: lw a1, 12(a1) +; RV32IZFINXZDINX-NEXT: lw a4, 4(a1) +; RV32IZFINXZDINX-NEXT: lw a5, 8(a1) +; RV32IZFINXZDINX-NEXT: lw a6, 12(a1) ; RV32IZFINXZDINX-NEXT: mv s0, a0 -; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) -; RV32IZFINXZDINX-NEXT: sw a4, 8(sp) -; RV32IZFINXZDINX-NEXT: sw a2, 4(sp) ; RV32IZFINXZDINX-NEXT: addi a0, sp, 16 ; RV32IZFINXZDINX-NEXT: mv a1, sp ; RV32IZFINXZDINX-NEXT: addi a2, sp, 36 ; RV32IZFINXZDINX-NEXT: sw a3, 0(sp) +; RV32IZFINXZDINX-NEXT: sw a4, 4(sp) +; RV32IZFINXZDINX-NEXT: sw a5, 8(sp) +; RV32IZFINXZDINX-NEXT: sw a6, 12(sp) ; RV32IZFINXZDINX-NEXT: call frexpl -; RV32IZFINXZDINX-NEXT: lw a0, 28(sp) -; RV32IZFINXZDINX-NEXT: lw a1, 24(sp) -; RV32IZFINXZDINX-NEXT: lw a2, 20(sp) -; RV32IZFINXZDINX-NEXT: lw a3, 16(sp) -; RV32IZFINXZDINX-NEXT: sw a0, 12(s0) -; RV32IZFINXZDINX-NEXT: sw a1, 8(s0) -; RV32IZFINXZDINX-NEXT: sw a2, 4(s0) -; RV32IZFINXZDINX-NEXT: sw a3, 0(s0) +; RV32IZFINXZDINX-NEXT: lw a0, 16(sp) +; RV32IZFINXZDINX-NEXT: lw a1, 20(sp) +; RV32IZFINXZDINX-NEXT: lw a2, 24(sp) +; RV32IZFINXZDINX-NEXT: lw a3, 28(sp) +; RV32IZFINXZDINX-NEXT: sw a0, 0(s0) +; RV32IZFINXZDINX-NEXT: sw a1, 4(s0) +; RV32IZFINXZDINX-NEXT: sw a2, 8(s0) +; RV32IZFINXZDINX-NEXT: sw a3, 12(s0) ; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 48 @@ -1825,26 +1825,26 @@ define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind { ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a3, 0(a1) -; RV32I-NEXT: lw a2, 4(a1) -; RV32I-NEXT: lw a4, 8(a1) -; RV32I-NEXT: lw a1, 12(a1) +; RV32I-NEXT: lw a4, 4(a1) +; RV32I-NEXT: lw a5, 8(a1) +; RV32I-NEXT: lw a6, 12(a1) ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: sw a1, 12(sp) -; RV32I-NEXT: sw a4, 8(sp) -; RV32I-NEXT: sw a2, 4(sp) ; RV32I-NEXT: addi a0, sp, 16 ; RV32I-NEXT: mv a1, sp ; RV32I-NEXT: addi a2, sp, 36 ; RV32I-NEXT: sw a3, 0(sp) +; RV32I-NEXT: sw a4, 4(sp) +; RV32I-NEXT: sw a5, 8(sp) +; RV32I-NEXT: sw a6, 12(sp) ; RV32I-NEXT: call frexpl -; RV32I-NEXT: lw a0, 28(sp) -; RV32I-NEXT: lw a1, 24(sp) -; RV32I-NEXT: lw a2, 20(sp) -; RV32I-NEXT: lw a3, 16(sp) -; RV32I-NEXT: sw a0, 12(s0) -; RV32I-NEXT: sw a1, 8(s0) -; RV32I-NEXT: sw a2, 4(s0) -; RV32I-NEXT: sw a3, 0(s0) +; RV32I-NEXT: lw a0, 16(sp) +; RV32I-NEXT: lw a1, 20(sp) +; RV32I-NEXT: lw a2, 24(sp) +; RV32I-NEXT: lw a3, 28(sp) +; RV32I-NEXT: sw a0, 0(s0) +; RV32I-NEXT: sw a1, 4(s0) +; RV32I-NEXT: sw a2, 8(s0) +; RV32I-NEXT: sw a3, 12(s0) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 48 @@ -1870,16 +1870,16 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -48 ; RV32IFD-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: lw a3, 0(a0) -; RV32IFD-NEXT: lw a1, 4(a0) -; RV32IFD-NEXT: lw a2, 8(a0) -; RV32IFD-NEXT: lw a0, 12(a0) -; RV32IFD-NEXT: sw a0, 20(sp) -; RV32IFD-NEXT: sw a2, 16(sp) -; RV32IFD-NEXT: sw a1, 12(sp) +; RV32IFD-NEXT: lw a4, 4(a0) +; RV32IFD-NEXT: lw a5, 8(a0) +; RV32IFD-NEXT: lw a6, 12(a0) ; RV32IFD-NEXT: addi a0, sp, 24 ; RV32IFD-NEXT: addi a1, sp, 8 ; RV32IFD-NEXT: addi a2, sp, 40 ; RV32IFD-NEXT: sw a3, 8(sp) +; RV32IFD-NEXT: sw a4, 12(sp) +; RV32IFD-NEXT: sw a5, 16(sp) +; RV32IFD-NEXT: sw a6, 20(sp) ; RV32IFD-NEXT: call frexpl ; RV32IFD-NEXT: lw a0, 40(sp) ; RV32IFD-NEXT: lw ra, 44(sp) # 4-byte Folded Reload @@ -1902,16 +1902,16 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV32IZFINXZDINX-NEXT: addi sp, sp, -48 ; RV32IZFINXZDINX-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: lw a3, 0(a0) -; RV32IZFINXZDINX-NEXT: lw a1, 4(a0) -; RV32IZFINXZDINX-NEXT: lw a2, 8(a0) -; RV32IZFINXZDINX-NEXT: lw a0, 12(a0) -; RV32IZFINXZDINX-NEXT: sw a0, 20(sp) -; RV32IZFINXZDINX-NEXT: sw a2, 16(sp) -; RV32IZFINXZDINX-NEXT: sw a1, 12(sp) +; RV32IZFINXZDINX-NEXT: lw a4, 4(a0) +; RV32IZFINXZDINX-NEXT: lw a5, 8(a0) +; RV32IZFINXZDINX-NEXT: lw a6, 12(a0) ; RV32IZFINXZDINX-NEXT: addi a0, sp, 24 ; RV32IZFINXZDINX-NEXT: addi a1, sp, 8 ; RV32IZFINXZDINX-NEXT: addi a2, sp, 40 ; RV32IZFINXZDINX-NEXT: sw a3, 8(sp) +; RV32IZFINXZDINX-NEXT: sw a4, 12(sp) +; RV32IZFINXZDINX-NEXT: sw a5, 16(sp) +; RV32IZFINXZDINX-NEXT: sw a6, 20(sp) ; RV32IZFINXZDINX-NEXT: call frexpl ; RV32IZFINXZDINX-NEXT: lw a0, 40(sp) ; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload @@ -1934,16 +1934,16 @@ define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind { ; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a3, 0(a0) -; RV32I-NEXT: lw a1, 4(a0) -; RV32I-NEXT: lw a2, 8(a0) -; RV32I-NEXT: lw a0, 12(a0) -; RV32I-NEXT: sw a0, 20(sp) -; RV32I-NEXT: sw a2, 16(sp) -; RV32I-NEXT: sw a1, 12(sp) +; RV32I-NEXT: lw a4, 4(a0) +; RV32I-NEXT: lw a5, 8(a0) +; RV32I-NEXT: lw a6, 12(a0) ; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a2, sp, 40 ; RV32I-NEXT: sw a3, 8(sp) +; RV32I-NEXT: sw a4, 12(sp) +; RV32I-NEXT: sw a5, 16(sp) +; RV32I-NEXT: sw a6, 20(sp) ; RV32I-NEXT: call frexpl ; RV32I-NEXT: lw a0, 40(sp) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload |