diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/half-convert-strict.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/half-convert-strict.ll | 2541 |
1 files changed, 831 insertions, 1710 deletions
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll index 675e230816f3..a607893a3735 100644 --- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll +++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll @@ -1,52 +1,56 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \ ; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s +; RUN: | FileCheck -check-prefixes=CHECKIZFH,CHECK32-IZFH,RV32IZFH %s ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \ ; RUN: -target-abi lp64f -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s +; RUN: | FileCheck -check-prefixes=CHECKIZFH,CHECK64-IZFH,RV64IZFH %s ; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \ ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s +; RUN: | FileCheck -check-prefixes=CHECKIZHINX,CHECK32-IZHINX,RV32IZHINX %s ; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \ ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s +; RUN: | FileCheck -check-prefixes=CHECKIZHINX,CHECK64-IZHINX,RV64IZHINX %s + ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \ ; RUN: -target-abi ilp32d -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefix=RV32IDZFH %s +; RUN: | FileCheck -check-prefixes=CHECKIDZFH,CHECK32-IZFH %s ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \ ; RUN: -target-abi lp64d -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefix=RV64IDZFH %s +; RUN: | FileCheck -check-prefixes=CHECKIDZFH,CHECK64-IZFH %s ; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs \ ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefix=RV32IZDINXZHINX %s +; RUN: | FileCheck -check-prefixes=CHECKIZDINXZHINX,CHECK32-IZHINX %s ; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs \ ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefix=RV64IZDINXZHINX %s +; RUN: | FileCheck -check-prefixes=CHECKIZDINXZHINX,CHECK64-IZHINX %s + ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \ ; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IFZFHMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIZFHMIN,CHECK32-IZFHMIN,RV32IFZFHMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \ ; RUN: -target-abi lp64f -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IFZFHMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIZFHMIN,CHECK64-IZFHMIN,RV64IFZFHMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \ ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK32-IZHINXMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,CHECK32-IZHINXMIN,RV32IZHINXMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \ ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK64-IZHINXMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,CHECK64-IZHINXMIN,RV64IZHINXMIN %s + ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs \ ; RUN: -target-abi ilp32d -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IDZFHMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIDZFHMIN,CHECK32-IZFHMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs \ ; RUN: -target-abi lp64d -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IDZFHMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIDZFHMIN,CHECK64-IZFHMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \ ; RUN: -target-abi ilp32 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK32-IZDINXZHINXMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIZDINXZHINXMIN,CHECK32-IZHINXMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \ ; RUN: -target-abi lp64 -disable-strictnode-mutation < %s \ -; RUN: | FileCheck -check-prefixes=CHECK64-IZDINXZHINXMIN %s +; RUN: | FileCheck -check-prefixes=CHECKIZDINXZHINXMIN,CHECK64-IZHINXMIN %s + ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs \ ; RUN: -target-abi ilp32d -disable-strictnode-mutation < %s \ ; RUN: | FileCheck -check-prefixes=CHECK32-D %s @@ -56,45 +60,25 @@ ; support rounding mode. define i16 @fcvt_si_h(half %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_si_h: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_si_h: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_si_h: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_si_h: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_si_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_si_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_si_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_si_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_si_h: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: fcvt.w.h a0, fa0, rtz +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_si_h: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: fcvt.l.h a0, fa0, rtz +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_si_h: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: fcvt.w.h a0, a0, rtz +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_si_h: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: fcvt.l.h a0, a0, rtz +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_si_h: ; CHECK32-IZFHMIN: # %bb.0: @@ -120,18 +104,6 @@ define i16 @fcvt_si_h(half %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_si_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_si_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_si_h: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -151,45 +123,25 @@ define i16 @fcvt_si_h(half %a) nounwind strictfp { declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata) define i16 @fcvt_ui_h(half %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_ui_h: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_ui_h: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_ui_h: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_ui_h: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_ui_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_ui_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_ui_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_ui_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_ui_h: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: fcvt.w.h a0, fa0, rtz +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_ui_h: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: fcvt.l.h a0, fa0, rtz +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_ui_h: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: fcvt.w.h a0, a0, rtz +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_ui_h: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: fcvt.l.h a0, a0, rtz +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_ui_h: ; CHECK32-IZFHMIN: # %bb.0: @@ -215,18 +167,6 @@ define i16 @fcvt_ui_h(half %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_ui_h: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -256,61 +196,39 @@ define i32 @fcvt_w_h(half %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.w.h a0, a0, rtz ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_w_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_w_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_w_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_w_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_w_h: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_w_h: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK64-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_w_h: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_w_h: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_w_h: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.w.h a0, fa0, rtz +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_w_h: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_w_h: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_w_h: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_w_h: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIDZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_w_h: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_w_h: ; CHECK32-D: # %bb.0: @@ -341,61 +259,39 @@ define i32 @fcvt_wu_h(half %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_wu_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_wu_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_wu_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_wu_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_wu_h: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_wu_h: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK64-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_wu_h: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.wu.h a0, fa0, rtz +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_wu_h: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_wu_h: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_wu_h: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_wu_h: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIDZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_wu_h: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_wu_h: ; CHECK32-D: # %bb.0: @@ -433,81 +329,51 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) strictfp { ; CHECKIZHINX-NEXT: add a0, a0, a1 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz -; RV32IDZFH-NEXT: seqz a1, a0 -; RV32IDZFH-NEXT: add a0, a0, a1 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_wu_h_multiple_use: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz -; RV64IDZFH-NEXT: seqz a1, a0 -; RV64IDZFH-NEXT: add a0, a0, a1 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_wu_h_multiple_use: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz -; RV32IZDINXZHINX-NEXT: seqz a1, a0 -; RV32IZDINXZHINX-NEXT: add a0, a0, a1 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_wu_h_multiple_use: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz -; RV64IZDINXZHINX-NEXT: seqz a1, a0 -; RV64IZDINXZHINX-NEXT: add a0, a0, a1 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_wu_h_multiple_use: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz -; CHECK32-IZFHMIN-NEXT: seqz a1, a0 -; CHECK32-IZFHMIN-NEXT: add a0, a0, a1 -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_multiple_use: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0 -; CHECK64-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz -; CHECK64-IZFHMIN-NEXT: seqz a1, a0 -; CHECK64-IZFHMIN-NEXT: add a0, a0, a1 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK32-IZHINXMIN-NEXT: seqz a1, a0 -; CHECK32-IZHINXMIN-NEXT: add a0, a0, a1 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK64-IZHINXMIN-NEXT: seqz a1, a0 -; CHECK64-IZHINXMIN-NEXT: add a0, a0, a1 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK32-IZDINXZHINXMIN-NEXT: seqz a1, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: add a0, a0, a1 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz -; CHECK64-IZDINXZHINXMIN-NEXT: seqz a1, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: add a0, a0, a1 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_wu_h_multiple_use: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.wu.h a0, fa0, rtz +; CHECKIDZFH-NEXT: seqz a1, a0 +; CHECKIDZFH-NEXT: add a0, a0, a1 +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_wu_h_multiple_use: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz +; CHECKIZDINXZHINX-NEXT: seqz a1, a0 +; CHECKIZDINXZHINX-NEXT: add a0, a0, a1 +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_wu_h_multiple_use: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz +; CHECKIZFHMIN-NEXT: seqz a1, a0 +; CHECKIZFHMIN-NEXT: add a0, a0, a1 +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_wu_h_multiple_use: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKIZHINXMIN-NEXT: seqz a1, a0 +; CHECKIZHINXMIN-NEXT: add a0, a0, a1 +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_wu_h_multiple_use: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.h fa5, fa0 +; CHECKIDZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz +; CHECKIDZFHMIN-NEXT: seqz a1, a0 +; CHECKIDZFHMIN-NEXT: add a0, a0, a1 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz +; CHECKIZDINXZHINXMIN-NEXT: seqz a1, a0 +; CHECKIZDINXZHINXMIN-NEXT: add a0, a0, a1 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_wu_h_multiple_use: ; CHECK32-D: # %bb.0: @@ -535,61 +401,33 @@ define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) strictfp { } define i64 @fcvt_l_h(half %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_l_h: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __fixhfdi -; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_l_h: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_l_h: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi sp, sp, -16 -; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __fixhfdi -; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_l_h: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_l_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi sp, sp, -16 -; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __fixhfdi -; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 16 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_l_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_l_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 -; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __fixhfdi -; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_l_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_l_h: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi sp, sp, -16 +; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZFH-NEXT: call __fixhfdi +; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZFH-NEXT: addi sp, sp, 16 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_l_h: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: fcvt.l.h a0, fa0, rtz +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_l_h: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi sp, sp, -16 +; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZHINX-NEXT: call __fixhfdi +; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZHINX-NEXT: addi sp, sp, 16 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_l_h: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: fcvt.l.h a0, a0, rtz +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_l_h: ; CHECK32-IZFHMIN: # %bb.0: @@ -621,21 +459,6 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_l_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixhfdi -; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_l_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_l_h: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -655,61 +478,33 @@ define i64 @fcvt_l_h(half %a) nounwind strictfp { declare i64 @llvm.experimental.constrained.fptosi.i64.f16(half, metadata) define i64 @fcvt_lu_h(half %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_lu_h: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __fixunshfdi -; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_lu_h: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_lu_h: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi sp, sp, -16 -; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __fixunshfdi -; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_lu_h: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_lu_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi sp, sp, -16 -; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __fixunshfdi -; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 16 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_lu_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_lu_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 -; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __fixunshfdi -; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_lu_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.lu.h a0, a0, rtz -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_lu_h: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi sp, sp, -16 +; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZFH-NEXT: call __fixunshfdi +; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZFH-NEXT: addi sp, sp, 16 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_lu_h: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: fcvt.lu.h a0, fa0, rtz +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_lu_h: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi sp, sp, -16 +; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZHINX-NEXT: call __fixunshfdi +; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZHINX-NEXT: addi sp, sp, 16 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_lu_h: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: fcvt.lu.h a0, a0, rtz +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_lu_h: ; CHECK32-IZFHMIN: # %bb.0: @@ -741,21 +536,6 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_lu_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __fixunshfdi -; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_lu_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_lu_h: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -775,61 +555,33 @@ define i64 @fcvt_lu_h(half %a) nounwind strictfp { declare i64 @llvm.experimental.constrained.fptoui.i64.f16(half, metadata) define half @fcvt_h_si(i16 %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_h_si: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: slli a0, a0, 16 -; RV32IZFH-NEXT: srai a0, a0, 16 -; RV32IZFH-NEXT: fcvt.h.w fa0, a0 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_si: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: slli a0, a0, 48 -; RV64IZFH-NEXT: srai a0, a0, 48 -; RV64IZFH-NEXT: fcvt.h.w fa0, a0 -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_h_si: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: slli a0, a0, 16 -; RV32IZHINX-NEXT: srai a0, a0, 16 -; RV32IZHINX-NEXT: fcvt.h.w a0, a0 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_si: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: slli a0, a0, 48 -; RV64IZHINX-NEXT: srai a0, a0, 48 -; RV64IZHINX-NEXT: fcvt.h.w a0, a0 -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_h_si: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: slli a0, a0, 16 -; RV32IDZFH-NEXT: srai a0, a0, 16 -; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_si: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: slli a0, a0, 48 -; RV64IDZFH-NEXT: srai a0, a0, 48 -; RV64IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_si: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: slli a0, a0, 16 -; RV32IZDINXZHINX-NEXT: srai a0, a0, 16 -; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_si: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: slli a0, a0, 48 -; RV64IZDINXZHINX-NEXT: srai a0, a0, 48 -; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_h_si: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: slli a0, a0, 16 +; CHECK32-IZFH-NEXT: srai a0, a0, 16 +; CHECK32-IZFH-NEXT: fcvt.h.w fa0, a0 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_h_si: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: slli a0, a0, 48 +; CHECK64-IZFH-NEXT: srai a0, a0, 48 +; CHECK64-IZFH-NEXT: fcvt.h.w fa0, a0 +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_h_si: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: slli a0, a0, 16 +; CHECK32-IZHINX-NEXT: srai a0, a0, 16 +; CHECK32-IZHINX-NEXT: fcvt.h.w a0, a0 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_h_si: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: slli a0, a0, 48 +; CHECK64-IZHINX-NEXT: srai a0, a0, 48 +; CHECK64-IZHINX-NEXT: fcvt.h.w a0, a0 +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_h_si: ; CHECK32-IZFHMIN: # %bb.0: @@ -863,22 +615,6 @@ define half @fcvt_h_si(i16 %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: slli a0, a0, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: srai a0, a0, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 48 -; CHECK64-IZDINXZHINXMIN-NEXT: srai a0, a0, 48 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_h_si: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -910,61 +646,39 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_si_signext: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_si_signext: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_si_signext: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_si_signext: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_h_si_signext: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0 -; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_h_si_signext: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.w fa5, a0 -; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_si_signext: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_si_signext: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_si_signext: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.h.w fa0, a0 +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_h_si_signext: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.h.w a0, a0 +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_h_si_signext: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0 +; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_h_si_signext: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_h_si_signext: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.w fa5, a0 +; CHECKIDZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_si_signext: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_si_signext: ; CHECK32-D: # %bb.0: @@ -984,61 +698,33 @@ define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp { } define half @fcvt_h_ui(i16 %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_h_ui: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: slli a0, a0, 16 -; RV32IZFH-NEXT: srli a0, a0, 16 -; RV32IZFH-NEXT: fcvt.h.wu fa0, a0 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_ui: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: slli a0, a0, 48 -; RV64IZFH-NEXT: srli a0, a0, 48 -; RV64IZFH-NEXT: fcvt.h.wu fa0, a0 -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_h_ui: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: slli a0, a0, 16 -; RV32IZHINX-NEXT: srli a0, a0, 16 -; RV32IZHINX-NEXT: fcvt.h.wu a0, a0 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_ui: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: slli a0, a0, 48 -; RV64IZHINX-NEXT: srli a0, a0, 48 -; RV64IZHINX-NEXT: fcvt.h.wu a0, a0 -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_h_ui: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: slli a0, a0, 16 -; RV32IDZFH-NEXT: srli a0, a0, 16 -; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_ui: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: slli a0, a0, 48 -; RV64IDZFH-NEXT: srli a0, a0, 48 -; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_ui: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: slli a0, a0, 16 -; RV32IZDINXZHINX-NEXT: srli a0, a0, 16 -; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_ui: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: slli a0, a0, 48 -; RV64IZDINXZHINX-NEXT: srli a0, a0, 48 -; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_h_ui: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: slli a0, a0, 16 +; CHECK32-IZFH-NEXT: srli a0, a0, 16 +; CHECK32-IZFH-NEXT: fcvt.h.wu fa0, a0 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_h_ui: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: slli a0, a0, 48 +; CHECK64-IZFH-NEXT: srli a0, a0, 48 +; CHECK64-IZFH-NEXT: fcvt.h.wu fa0, a0 +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_h_ui: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: slli a0, a0, 16 +; CHECK32-IZHINX-NEXT: srli a0, a0, 16 +; CHECK32-IZHINX-NEXT: fcvt.h.wu a0, a0 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_h_ui: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: slli a0, a0, 48 +; CHECK64-IZHINX-NEXT: srli a0, a0, 48 +; CHECK64-IZHINX-NEXT: fcvt.h.wu a0, a0 +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_h_ui: ; CHECK32-IZFHMIN: # %bb.0: @@ -1072,22 +758,6 @@ define half @fcvt_h_ui(i16 %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: slli a0, a0, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: srli a0, a0, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: slli a0, a0, 48 -; CHECK64-IZDINXZHINXMIN-NEXT: srli a0, a0, 48 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_h_ui: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -1119,61 +789,39 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.h.wu a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_ui_zeroext: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_ui_zeroext: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_ui_zeroext: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_ui_zeroext: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_h_ui_zeroext: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0 -; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_h_ui_zeroext: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.wu fa5, a0 -; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_ui_zeroext: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui_zeroext: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_ui_zeroext: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.h.wu fa0, a0 +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_h_ui_zeroext: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.h.wu a0, a0 +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_h_ui_zeroext: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.wu fa5, a0 +; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_h_ui_zeroext: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.wu a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_h_ui_zeroext: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.wu fa5, a0 +; CHECKIDZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_ui_zeroext: ; CHECK32-D: # %bb.0: @@ -1203,61 +851,39 @@ define half @fcvt_h_w(i32 %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_w: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_w: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_w: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_w: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_h_w: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0 -; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_h_w: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.w fa5, a0 -; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_w: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_w: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_w: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.h.w fa0, a0 +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_h_w: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.h.w a0, a0 +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_h_w: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0 +; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_h_w: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_h_w: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.w fa5, a0 +; CHECKIDZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_w: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_w: ; CHECK32-D: # %bb.0: @@ -1290,71 +916,45 @@ define half @fcvt_h_w_load(ptr %p) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.h.w a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_w_load: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: lw a0, 0(a0) -; RV32IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_w_load: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: lw a0, 0(a0) -; RV64IDZFH-NEXT: fcvt.h.w fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_w_load: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: lw a0, 0(a0) -; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_w_load: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: lw a0, 0(a0) -; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_h_w_load: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: lw a0, 0(a0) -; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0 -; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_h_w_load: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: lw a0, 0(a0) -; CHECK64-IZFHMIN-NEXT: fcvt.s.w fa5, a0 -; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_w_load: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_load: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK64-IZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_load: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_load: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_w_load: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: lw a0, 0(a0) +; CHECKIDZFH-NEXT: fcvt.h.w fa0, a0 +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_h_w_load: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: lw a0, 0(a0) +; CHECKIZDINXZHINX-NEXT: fcvt.h.w a0, a0 +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_h_w_load: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: lw a0, 0(a0) +; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0 +; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_h_w_load: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: lw a0, 0(a0) +; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_h_w_load: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: lw a0, 0(a0) +; CHECKIDZFHMIN-NEXT: fcvt.s.w fa5, a0 +; CHECKIDZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_w_load: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: lw a0, 0(a0) +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_w_load: ; CHECK32-D: # %bb.0: @@ -1386,61 +986,39 @@ define half @fcvt_h_wu(i32 %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.h.wu a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_wu: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_wu: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_wu: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_wu: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_h_wu: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0 -; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_h_wu: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.wu fa5, a0 -; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_wu: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.h.wu fa0, a0 +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_h_wu: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.h.wu a0, a0 +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_h_wu: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.wu fa5, a0 +; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_h_wu: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.wu a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_h_wu: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.wu fa5, a0 +; CHECKIDZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_wu: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_wu: ; CHECK32-D: # %bb.0: @@ -1473,71 +1051,45 @@ define half @fcvt_h_wu_load(ptr %p) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.h.wu a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_wu_load: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: lw a0, 0(a0) -; RV32IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_wu_load: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: lw a0, 0(a0) -; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_wu_load: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: lw a0, 0(a0) -; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_wu_load: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: lw a0, 0(a0) -; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a0 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_load: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: lw a0, 0(a0) -; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a0 -; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK32-IZFHMIN-NEXT: ret -; -; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_load: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: lw a0, 0(a0) -; CHECK64-IZFHMIN-NEXT: fcvt.s.wu fa5, a0 -; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa5 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu_load: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_load: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK64-IZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: lw a0, 0(a0) -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_wu_load: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: lw a0, 0(a0) +; CHECKIDZFH-NEXT: fcvt.h.wu fa0, a0 +; CHECKIDZFH-NEXT: ret +; +; CHECKIZDINXZHINX-LABEL: fcvt_h_wu_load: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: lw a0, 0(a0) +; CHECKIZDINXZHINX-NEXT: fcvt.h.wu a0, a0 +; CHECKIZDINXZHINX-NEXT: ret +; +; CHECKIZFHMIN-LABEL: fcvt_h_wu_load: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: lw a0, 0(a0) +; CHECKIZFHMIN-NEXT: fcvt.s.wu fa5, a0 +; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIZFHMIN-NEXT: ret +; +; CHECKIZHINXMIN-LABEL: fcvt_h_wu_load: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: lw a0, 0(a0) +; CHECKIZHINXMIN-NEXT: fcvt.s.wu a0, a0 +; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_h_wu_load: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: lw a0, 0(a0) +; CHECKIDZFHMIN-NEXT: fcvt.s.wu fa5, a0 +; CHECKIDZFHMIN-NEXT: fcvt.h.s fa0, fa5 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_wu_load: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: lw a0, 0(a0) +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_wu_load: ; CHECK32-D: # %bb.0: @@ -1559,61 +1111,33 @@ define half @fcvt_h_wu_load(ptr %p) nounwind strictfp { } define half @fcvt_h_l(i64 %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_h_l: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __floatdihf -; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_l: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.l fa0, a0 -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_h_l: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi sp, sp, -16 -; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __floatdihf -; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_l: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fcvt.h.l a0, a0 -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_h_l: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi sp, sp, -16 -; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __floatdihf -; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 16 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_l: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.l fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_l: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 -; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __floatdihf -; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_l: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.l a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_h_l: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi sp, sp, -16 +; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZFH-NEXT: call __floatdihf +; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZFH-NEXT: addi sp, sp, 16 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_h_l: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: fcvt.h.l fa0, a0 +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_h_l: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi sp, sp, -16 +; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZHINX-NEXT: call __floatdihf +; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZHINX-NEXT: addi sp, sp, 16 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_h_l: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: fcvt.h.l a0, a0 +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_h_l: ; CHECK32-IZFHMIN: # %bb.0: @@ -1645,21 +1169,6 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_l: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __floatdihf -; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_l: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_h_l: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -1679,61 +1188,33 @@ define half @fcvt_h_l(i64 %a) nounwind strictfp { declare half @llvm.experimental.constrained.sitofp.f16.i64(i64, metadata, metadata) define half @fcvt_h_lu(i64 %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_h_lu: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: call __floatundihf -; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_lu: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.lu fa0, a0 -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_h_lu: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi sp, sp, -16 -; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: call __floatundihf -; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_lu: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: fcvt.h.lu a0, a0 -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_h_lu: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi sp, sp, -16 -; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: call __floatundihf -; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 16 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_lu: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_lu: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi sp, sp, -16 -; RV32IZDINXZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: call __floatundihf -; RV32IZDINXZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZDINXZHINX-NEXT: addi sp, sp, 16 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_lu: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.lu a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_h_lu: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi sp, sp, -16 +; CHECK32-IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZFH-NEXT: call __floatundihf +; CHECK32-IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZFH-NEXT: addi sp, sp, 16 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_h_lu: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: fcvt.h.lu fa0, a0 +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_h_lu: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi sp, sp, -16 +; CHECK32-IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; CHECK32-IZHINX-NEXT: call __floatundihf +; CHECK32-IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; CHECK32-IZHINX-NEXT: addi sp, sp, 16 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_h_lu: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: fcvt.h.lu a0, a0 +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_h_lu: ; CHECK32-IZFHMIN: # %bb.0: @@ -1765,21 +1246,6 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_lu: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: call __floatundihf -; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_lu: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_h_lu: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -1809,55 +1275,35 @@ define half @fcvt_h_s(float %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.h.s a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_s: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.s fa0, fa0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_s: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.s fa0, fa0 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_s: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.h.s a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_s: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.s a0, a0 -; RV64IZDINXZHINX-NEXT: ret -; -; CHECK32-IZFHMIN-LABEL: fcvt_h_s: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa0, fa0 -; CHECK32-IZFHMIN-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_s: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.h.s fa0, fa0 +; CHECKIDZFH-NEXT: ret ; -; CHECK64-IZFHMIN-LABEL: fcvt_h_s: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa0, fa0 -; CHECK64-IZFHMIN-NEXT: ret +; CHECKIZDINXZHINX-LABEL: fcvt_h_s: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINX-NEXT: ret ; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_s: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret +; CHECKIZFHMIN-LABEL: fcvt_h_s: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa0 +; CHECKIZFHMIN-NEXT: ret ; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_s: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret +; CHECKIZHINXMIN-LABEL: fcvt_h_s: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_s: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret +; CHECKIDZFHMIN-LABEL: fcvt_h_s: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.h.s fa0, fa0 +; CHECKIDZFHMIN-NEXT: ret ; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_s: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_s: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_s: ; CHECK32-D: # %bb.0: @@ -1887,55 +1333,35 @@ define float @fcvt_s_h(half %a) nounwind strictfp { ; CHECKIZHINX-NEXT: fcvt.s.h a0, a0 ; CHECKIZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_s_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IDZFH-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_s_h: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.s.h fa0, fa0 +; CHECKIDZFH-NEXT: ret ; -; RV64IDZFH-LABEL: fcvt_s_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IDZFH-NEXT: ret +; CHECKIZDINXZHINX-LABEL: fcvt_s_h: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.s.h a0, a0 +; CHECKIZDINXZHINX-NEXT: ret ; -; RV32IZDINXZHINX-LABEL: fcvt_s_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV32IZDINXZHINX-NEXT: ret +; CHECKIZFHMIN-LABEL: fcvt_s_h: +; CHECKIZFHMIN: # %bb.0: +; CHECKIZFHMIN-NEXT: fcvt.s.h fa0, fa0 +; CHECKIZFHMIN-NEXT: ret ; -; RV64IZDINXZHINX-LABEL: fcvt_s_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECKIZHINXMIN-LABEL: fcvt_s_h: +; CHECKIZHINXMIN: # %bb.0: +; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZHINXMIN-NEXT: ret ; -; CHECK32-IZFHMIN-LABEL: fcvt_s_h: -; CHECK32-IZFHMIN: # %bb.0: -; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; CHECK32-IZFHMIN-NEXT: ret +; CHECKIDZFHMIN-LABEL: fcvt_s_h: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.s.h fa0, fa0 +; CHECKIDZFHMIN-NEXT: ret ; -; CHECK64-IZFHMIN-LABEL: fcvt_s_h: -; CHECK64-IZFHMIN: # %bb.0: -; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa0, fa0 -; CHECK64-IZFHMIN-NEXT: ret -; -; CHECK32-IZHINXMIN-LABEL: fcvt_s_h: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_s_h: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZHINXMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_s_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_s_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; CHECKIZDINXZHINXMIN-LABEL: fcvt_s_h: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_s_h: ; CHECK32-D: # %bb.0: @@ -1991,25 +1417,15 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, 16 ; RV64IZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_h_d: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.h.d fa0, fa0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_d: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.h.d fa0, fa0 -; RV64IDZFH-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_h_d: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.h.d fa0, fa0 +; CHECKIDZFH-NEXT: ret ; -; RV32IZDINXZHINX-LABEL: fcvt_h_d: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.h.d a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_d: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.h.d a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECKIZDINXZHINX-LABEL: fcvt_h_d: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.h.d a0, a0 +; CHECKIZDINXZHINX-NEXT: ret ; ; RV32IFZFHMIN-LABEL: fcvt_h_d: ; RV32IFZFHMIN: # %bb.0: @@ -2029,43 +1445,33 @@ define half @fcvt_h_d(double %a) nounwind strictfp { ; RV64IFZFHMIN-NEXT: addi sp, sp, 16 ; RV64IFZFHMIN-NEXT: ret ; -; CHECK32-IZHINXMIN-LABEL: fcvt_h_d: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: call __truncdfhf2 -; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_h_d: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; CHECK64-IZHINXMIN-NEXT: call __truncdfhf2 -; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK64-IZHINXMIN-NEXT: ret -; -; RV32IDZFHMIN-LABEL: fcvt_h_d: -; RV32IDZFHMIN: # %bb.0: -; RV32IDZFHMIN-NEXT: fcvt.h.d fa0, fa0 -; RV32IDZFHMIN-NEXT: ret -; -; RV64IDZFHMIN-LABEL: fcvt_h_d: -; RV64IDZFHMIN: # %bb.0: -; RV64IDZFHMIN-NEXT: fcvt.h.d fa0, fa0 -; RV64IDZFHMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_d: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.d a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_d: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.d a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; RV32IZHINXMIN-LABEL: fcvt_h_d: +; RV32IZHINXMIN: # %bb.0: +; RV32IZHINXMIN-NEXT: addi sp, sp, -16 +; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZHINXMIN-NEXT: call __truncdfhf2 +; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZHINXMIN-NEXT: addi sp, sp, 16 +; RV32IZHINXMIN-NEXT: ret +; +; RV64IZHINXMIN-LABEL: fcvt_h_d: +; RV64IZHINXMIN: # %bb.0: +; RV64IZHINXMIN-NEXT: addi sp, sp, -16 +; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZHINXMIN-NEXT: call __truncdfhf2 +; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZHINXMIN-NEXT: addi sp, sp, 16 +; RV64IZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_h_d: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.h.d fa0, fa0 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_h_d: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.h.d a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_h_d: ; CHECK32-D: # %bb.0: @@ -2125,25 +1531,15 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV64IZHINX-NEXT: addi sp, sp, 16 ; RV64IZHINX-NEXT: ret ; -; RV32IDZFH-LABEL: fcvt_d_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: fcvt.d.h fa0, fa0 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_d_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: fcvt.d.h fa0, fa0 -; RV64IDZFH-NEXT: ret +; CHECKIDZFH-LABEL: fcvt_d_h: +; CHECKIDZFH: # %bb.0: +; CHECKIDZFH-NEXT: fcvt.d.h fa0, fa0 +; CHECKIDZFH-NEXT: ret ; -; RV32IZDINXZHINX-LABEL: fcvt_d_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: fcvt.d.h a0, a0 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_d_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: fcvt.d.h a0, a0 -; RV64IZDINXZHINX-NEXT: ret +; CHECKIZDINXZHINX-LABEL: fcvt_d_h: +; CHECKIZDINXZHINX: # %bb.0: +; CHECKIZDINXZHINX-NEXT: fcvt.d.h a0, a0 +; CHECKIZDINXZHINX-NEXT: ret ; ; RV32IFZFHMIN-LABEL: fcvt_d_h: ; RV32IFZFHMIN: # %bb.0: @@ -2165,45 +1561,35 @@ define double @fcvt_d_h(half %a) nounwind strictfp { ; RV64IFZFHMIN-NEXT: addi sp, sp, 16 ; RV64IFZFHMIN-NEXT: ret ; -; CHECK32-IZHINXMIN-LABEL: fcvt_d_h: -; CHECK32-IZHINXMIN: # %bb.0: -; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK32-IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK32-IZHINXMIN-NEXT: call __extendsfdf2 -; CHECK32-IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK32-IZHINXMIN-NEXT: ret -; -; CHECK64-IZHINXMIN-LABEL: fcvt_d_h: -; CHECK64-IZHINXMIN: # %bb.0: -; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK64-IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZHINXMIN-NEXT: call __extendsfdf2 -; CHECK64-IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK64-IZHINXMIN-NEXT: ret -; -; RV32IDZFHMIN-LABEL: fcvt_d_h: -; RV32IDZFHMIN: # %bb.0: -; RV32IDZFHMIN-NEXT: fcvt.d.h fa0, fa0 -; RV32IDZFHMIN-NEXT: ret -; -; RV64IDZFHMIN-LABEL: fcvt_d_h: -; RV64IDZFHMIN: # %bb.0: -; RV64IDZFHMIN-NEXT: fcvt.d.h fa0, fa0 -; RV64IDZFHMIN-NEXT: ret -; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_d_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.d.h a0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_d_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.d.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: ret +; RV32IZHINXMIN-LABEL: fcvt_d_h: +; RV32IZHINXMIN: # %bb.0: +; RV32IZHINXMIN-NEXT: addi sp, sp, -16 +; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 +; RV32IZHINXMIN-NEXT: call __extendsfdf2 +; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZHINXMIN-NEXT: addi sp, sp, 16 +; RV32IZHINXMIN-NEXT: ret +; +; RV64IZHINXMIN-LABEL: fcvt_d_h: +; RV64IZHINXMIN: # %bb.0: +; RV64IZHINXMIN-NEXT: addi sp, sp, -16 +; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 +; RV64IZHINXMIN-NEXT: call __extendsfdf2 +; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64IZHINXMIN-NEXT: addi sp, sp, 16 +; RV64IZHINXMIN-NEXT: ret +; +; CHECKIDZFHMIN-LABEL: fcvt_d_h: +; CHECKIDZFHMIN: # %bb.0: +; CHECKIDZFHMIN-NEXT: fcvt.d.h fa0, fa0 +; CHECKIDZFHMIN-NEXT: ret +; +; CHECKIZDINXZHINXMIN-LABEL: fcvt_d_h: +; CHECKIZDINXZHINXMIN: # %bb.0: +; CHECKIZDINXZHINXMIN-NEXT: fcvt.d.h a0, a0 +; CHECKIZDINXZHINXMIN-NEXT: ret ; ; CHECK32-D-LABEL: fcvt_d_h: ; CHECK32-D: # %bb.0: @@ -2225,61 +1611,33 @@ declare double @llvm.experimental.constrained.fpext.f64.f16(half, metadata) ; Make sure we select W version of addi on RV64. define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp { -; RV32IZFH-LABEL: fcvt_h_w_demanded_bits: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi a0, a0, 1 -; RV32IZFH-NEXT: fcvt.h.w fa5, a0 -; RV32IZFH-NEXT: fsh fa5, 0(a1) -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_w_demanded_bits: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: addiw a0, a0, 1 -; RV64IZFH-NEXT: fcvt.h.w fa5, a0 -; RV64IZFH-NEXT: fsh fa5, 0(a1) -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_h_w_demanded_bits: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi a0, a0, 1 -; RV32IZHINX-NEXT: fcvt.h.w a2, a0 -; RV32IZHINX-NEXT: sh a2, 0(a1) -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: addiw a0, a0, 1 -; RV64IZHINX-NEXT: fcvt.h.w a2, a0 -; RV64IZHINX-NEXT: sh a2, 0(a1) -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi a0, a0, 1 -; RV32IDZFH-NEXT: fcvt.h.w fa5, a0 -; RV32IDZFH-NEXT: fsh fa5, 0(a1) -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: addiw a0, a0, 1 -; RV64IDZFH-NEXT: fcvt.h.w fa5, a0 -; RV64IDZFH-NEXT: fsh fa5, 0(a1) -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi a0, a0, 1 -; RV32IZDINXZHINX-NEXT: fcvt.h.w a2, a0 -; RV32IZDINXZHINX-NEXT: sh a2, 0(a1) -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: addiw a0, a0, 1 -; RV64IZDINXZHINX-NEXT: fcvt.h.w a2, a0 -; RV64IZDINXZHINX-NEXT: sh a2, 0(a1) -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_h_w_demanded_bits: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi a0, a0, 1 +; CHECK32-IZFH-NEXT: fcvt.h.w fa5, a0 +; CHECK32-IZFH-NEXT: fsh fa5, 0(a1) +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_h_w_demanded_bits: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: addiw a0, a0, 1 +; CHECK64-IZFH-NEXT: fcvt.h.w fa5, a0 +; CHECK64-IZFH-NEXT: fsh fa5, 0(a1) +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_h_w_demanded_bits: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi a0, a0, 1 +; CHECK32-IZHINX-NEXT: fcvt.h.w a2, a0 +; CHECK32-IZHINX-NEXT: sh a2, 0(a1) +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_h_w_demanded_bits: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: addiw a0, a0, 1 +; CHECK64-IZHINX-NEXT: fcvt.h.w a2, a0 +; CHECK64-IZHINX-NEXT: sh a2, 0(a1) +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_h_w_demanded_bits: ; CHECK32-IZFHMIN: # %bb.0: @@ -2313,22 +1671,6 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp { ; CHECK64-IZHINXMIN-NEXT: sh a2, 0(a1) ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi a0, a0, 1 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a2, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2 -; CHECK32-IZDINXZHINXMIN-NEXT: sh a2, 0(a1) -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: addiw a0, a0, 1 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.w a2, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2 -; CHECK64-IZDINXZHINXMIN-NEXT: sh a2, 0(a1) -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_h_w_demanded_bits: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -2363,61 +1705,33 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) strictfp { ; Make sure we select W version of addi on RV64. define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) strictfp { -; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi a0, a0, 1 -; RV32IZFH-NEXT: fcvt.h.wu fa5, a0 -; RV32IZFH-NEXT: fsh fa5, 0(a1) -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: addiw a0, a0, 1 -; RV64IZFH-NEXT: fcvt.h.wu fa5, a0 -; RV64IZFH-NEXT: fsh fa5, 0(a1) -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_h_wu_demanded_bits: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi a0, a0, 1 -; RV32IZHINX-NEXT: fcvt.h.wu a2, a0 -; RV32IZHINX-NEXT: sh a2, 0(a1) -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_wu_demanded_bits: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: addiw a0, a0, 1 -; RV64IZHINX-NEXT: fcvt.h.wu a2, a0 -; RV64IZHINX-NEXT: sh a2, 0(a1) -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi a0, a0, 1 -; RV32IDZFH-NEXT: fcvt.h.wu fa5, a0 -; RV32IDZFH-NEXT: fsh fa5, 0(a1) -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: addiw a0, a0, 1 -; RV64IDZFH-NEXT: fcvt.h.wu fa5, a0 -; RV64IDZFH-NEXT: fsh fa5, 0(a1) -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi a0, a0, 1 -; RV32IZDINXZHINX-NEXT: fcvt.h.wu a2, a0 -; RV32IZDINXZHINX-NEXT: sh a2, 0(a1) -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: addiw a0, a0, 1 -; RV64IZDINXZHINX-NEXT: fcvt.h.wu a2, a0 -; RV64IZDINXZHINX-NEXT: sh a2, 0(a1) -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_h_wu_demanded_bits: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi a0, a0, 1 +; CHECK32-IZFH-NEXT: fcvt.h.wu fa5, a0 +; CHECK32-IZFH-NEXT: fsh fa5, 0(a1) +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_h_wu_demanded_bits: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: addiw a0, a0, 1 +; CHECK64-IZFH-NEXT: fcvt.h.wu fa5, a0 +; CHECK64-IZFH-NEXT: fsh fa5, 0(a1) +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_h_wu_demanded_bits: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi a0, a0, 1 +; CHECK32-IZHINX-NEXT: fcvt.h.wu a2, a0 +; CHECK32-IZHINX-NEXT: sh a2, 0(a1) +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_h_wu_demanded_bits: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: addiw a0, a0, 1 +; CHECK64-IZHINX-NEXT: fcvt.h.wu a2, a0 +; CHECK64-IZHINX-NEXT: sh a2, 0(a1) +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits: ; CHECK32-IZFHMIN: # %bb.0: @@ -2451,22 +1765,6 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) strictfp { ; CHECK64-IZHINXMIN-NEXT: sh a2, 0(a1) ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi a0, a0, 1 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a2, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2 -; CHECK32-IZDINXZHINXMIN-NEXT: sh a2, 0(a1) -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: addiw a0, a0, 1 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.wu a2, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a2, a2 -; CHECK64-IZDINXZHINXMIN-NEXT: sh a2, 0(a1) -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_h_wu_demanded_bits: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -16 @@ -2500,113 +1798,59 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) strictfp { } define half @fcvt_h_q(fp128 %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_h_q: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi sp, sp, -32 -; RV32IZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: lw a1, 0(a0) -; RV32IZFH-NEXT: lw a2, 4(a0) -; RV32IZFH-NEXT: lw a3, 8(a0) -; RV32IZFH-NEXT: lw a4, 12(a0) -; RV32IZFH-NEXT: addi a0, sp, 8 -; RV32IZFH-NEXT: sw a1, 8(sp) -; RV32IZFH-NEXT: sw a2, 12(sp) -; RV32IZFH-NEXT: sw a3, 16(sp) -; RV32IZFH-NEXT: sw a4, 20(sp) -; RV32IZFH-NEXT: call __trunctfhf2 -; RV32IZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 32 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_h_q: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: call __trunctfhf2 -; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IZFH-NEXT: addi sp, sp, 16 -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_h_q: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi sp, sp, -32 -; RV32IZHINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: lw a1, 0(a0) -; RV32IZHINX-NEXT: lw a2, 4(a0) -; RV32IZHINX-NEXT: lw a3, 8(a0) -; RV32IZHINX-NEXT: lw a4, 12(a0) -; RV32IZHINX-NEXT: addi a0, sp, 8 -; RV32IZHINX-NEXT: sw a1, 8(sp) -; RV32IZHINX-NEXT: sw a2, 12(sp) -; RV32IZHINX-NEXT: sw a3, 16(sp) -; RV32IZHINX-NEXT: sw a4, 20(sp) -; RV32IZHINX-NEXT: call __trunctfhf2 -; RV32IZHINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: addi sp, sp, 32 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_h_q: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: addi sp, sp, -16 -; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: call __trunctfhf2 -; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IZHINX-NEXT: addi sp, sp, 16 -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_h_q: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi sp, sp, -32 -; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: lw a1, 0(a0) -; RV32IDZFH-NEXT: lw a2, 4(a0) -; RV32IDZFH-NEXT: lw a3, 8(a0) -; RV32IDZFH-NEXT: lw a4, 12(a0) -; RV32IDZFH-NEXT: addi a0, sp, 8 -; RV32IDZFH-NEXT: sw a1, 8(sp) -; RV32IDZFH-NEXT: sw a2, 12(sp) -; RV32IDZFH-NEXT: sw a3, 16(sp) -; RV32IDZFH-NEXT: sw a4, 20(sp) -; RV32IDZFH-NEXT: call __trunctfhf2 -; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 32 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_h_q: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: addi sp, sp, -16 -; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IDZFH-NEXT: call __trunctfhf2 -; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IDZFH-NEXT: addi sp, sp, 16 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_h_q: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi sp, sp, -32 -; RV32IZDINXZHINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: lw a1, 0(a0) -; RV32IZDINXZHINX-NEXT: lw a2, 4(a0) -; RV32IZDINXZHINX-NEXT: lw a3, 8(a0) -; RV32IZDINXZHINX-NEXT: lw a4, 12(a0) -; RV32IZDINXZHINX-NEXT: addi a0, sp, 8 -; RV32IZDINXZHINX-NEXT: sw a1, 8(sp) -; RV32IZDINXZHINX-NEXT: sw a2, 12(sp) -; RV32IZDINXZHINX-NEXT: sw a3, 16(sp) -; RV32IZDINXZHINX-NEXT: sw a4, 20(sp) -; RV32IZDINXZHINX-NEXT: call __trunctfhf2 -; RV32IZDINXZHINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZDINXZHINX-NEXT: addi sp, sp, 32 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_h_q: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 -; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZDINXZHINX-NEXT: call __trunctfhf2 -; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_h_q: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi sp, sp, -32 +; CHECK32-IZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; CHECK32-IZFH-NEXT: lw a1, 0(a0) +; CHECK32-IZFH-NEXT: lw a2, 4(a0) +; CHECK32-IZFH-NEXT: lw a3, 8(a0) +; CHECK32-IZFH-NEXT: lw a4, 12(a0) +; CHECK32-IZFH-NEXT: addi a0, sp, 8 +; CHECK32-IZFH-NEXT: sw a1, 8(sp) +; CHECK32-IZFH-NEXT: sw a2, 12(sp) +; CHECK32-IZFH-NEXT: sw a3, 16(sp) +; CHECK32-IZFH-NEXT: sw a4, 20(sp) +; CHECK32-IZFH-NEXT: call __trunctfhf2 +; CHECK32-IZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; CHECK32-IZFH-NEXT: addi sp, sp, 32 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_h_q: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: addi sp, sp, -16 +; CHECK64-IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK64-IZFH-NEXT: call __trunctfhf2 +; CHECK64-IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK64-IZFH-NEXT: addi sp, sp, 16 +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_h_q: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi sp, sp, -32 +; CHECK32-IZHINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; CHECK32-IZHINX-NEXT: lw a1, 0(a0) +; CHECK32-IZHINX-NEXT: lw a2, 4(a0) +; CHECK32-IZHINX-NEXT: lw a3, 8(a0) +; CHECK32-IZHINX-NEXT: lw a4, 12(a0) +; CHECK32-IZHINX-NEXT: addi a0, sp, 8 +; CHECK32-IZHINX-NEXT: sw a1, 8(sp) +; CHECK32-IZHINX-NEXT: sw a2, 12(sp) +; CHECK32-IZHINX-NEXT: sw a3, 16(sp) +; CHECK32-IZHINX-NEXT: sw a4, 20(sp) +; CHECK32-IZHINX-NEXT: call __trunctfhf2 +; CHECK32-IZHINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; CHECK32-IZHINX-NEXT: addi sp, sp, 32 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_h_q: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: addi sp, sp, -16 +; CHECK64-IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK64-IZHINX-NEXT: call __trunctfhf2 +; CHECK64-IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK64-IZHINX-NEXT: addi sp, sp, 16 +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_h_q: ; CHECK32-IZFHMIN: # %bb.0: @@ -2662,33 +1906,6 @@ define half @fcvt_h_q(fp128 %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_q: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -32 -; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 0(a0) -; CHECK32-IZDINXZHINXMIN-NEXT: lw a2, 4(a0) -; CHECK32-IZDINXZHINXMIN-NEXT: lw a3, 8(a0) -; CHECK32-IZDINXZHINXMIN-NEXT: lw a4, 12(a0) -; CHECK32-IZDINXZHINXMIN-NEXT: addi a0, sp, 8 -; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 8(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: sw a2, 12(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: sw a3, 16(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: sw a4, 20(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: call __trunctfhf2 -; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 32 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_q: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK64-IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; CHECK64-IZDINXZHINXMIN-NEXT: call __trunctfhf2 -; CHECK64-IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_h_q: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -32 @@ -2715,133 +1932,69 @@ define half @fcvt_h_q(fp128 %a) nounwind strictfp { } define fp128 @fcvt_q_h(half %a) nounwind strictfp { -; RV32IZFH-LABEL: fcvt_q_h: -; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: addi sp, sp, -32 -; RV32IZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: mv s0, a0 -; RV32IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IZFH-NEXT: addi a0, sp, 8 -; RV32IZFH-NEXT: call __extendsftf2 -; RV32IZFH-NEXT: lw a0, 8(sp) -; RV32IZFH-NEXT: lw a1, 12(sp) -; RV32IZFH-NEXT: lw a2, 16(sp) -; RV32IZFH-NEXT: lw a3, 20(sp) -; RV32IZFH-NEXT: sw a0, 0(s0) -; RV32IZFH-NEXT: sw a1, 4(s0) -; RV32IZFH-NEXT: sw a2, 8(s0) -; RV32IZFH-NEXT: sw a3, 12(s0) -; RV32IZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 32 -; RV32IZFH-NEXT: ret -; -; RV64IZFH-LABEL: fcvt_q_h: -; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: addi sp, sp, -16 -; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IZFH-NEXT: call __extendsftf2 -; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IZFH-NEXT: addi sp, sp, 16 -; RV64IZFH-NEXT: ret -; -; RV32IZHINX-LABEL: fcvt_q_h: -; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: addi sp, sp, -32 -; RV32IZHINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IZHINX-NEXT: mv s0, a0 -; RV32IZHINX-NEXT: fcvt.s.h a1, a1 -; RV32IZHINX-NEXT: addi a0, sp, 8 -; RV32IZHINX-NEXT: call __extendsftf2 -; RV32IZHINX-NEXT: lw a0, 8(sp) -; RV32IZHINX-NEXT: lw a1, 12(sp) -; RV32IZHINX-NEXT: lw a2, 16(sp) -; RV32IZHINX-NEXT: lw a3, 20(sp) -; RV32IZHINX-NEXT: sw a0, 0(s0) -; RV32IZHINX-NEXT: sw a1, 4(s0) -; RV32IZHINX-NEXT: sw a2, 8(s0) -; RV32IZHINX-NEXT: sw a3, 12(s0) -; RV32IZHINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IZHINX-NEXT: addi sp, sp, 32 -; RV32IZHINX-NEXT: ret -; -; RV64IZHINX-LABEL: fcvt_q_h: -; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: addi sp, sp, -16 -; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZHINX-NEXT: call __extendsftf2 -; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IZHINX-NEXT: addi sp, sp, 16 -; RV64IZHINX-NEXT: ret -; -; RV32IDZFH-LABEL: fcvt_q_h: -; RV32IDZFH: # %bb.0: -; RV32IDZFH-NEXT: addi sp, sp, -32 -; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: mv s0, a0 -; RV32IDZFH-NEXT: fcvt.s.h fa0, fa0 -; RV32IDZFH-NEXT: addi a0, sp, 8 -; RV32IDZFH-NEXT: call __extendsftf2 -; RV32IDZFH-NEXT: lw a0, 8(sp) -; RV32IDZFH-NEXT: lw a1, 12(sp) -; RV32IDZFH-NEXT: lw a2, 16(sp) -; RV32IDZFH-NEXT: lw a3, 20(sp) -; RV32IDZFH-NEXT: sw a0, 0(s0) -; RV32IDZFH-NEXT: sw a1, 4(s0) -; RV32IDZFH-NEXT: sw a2, 8(s0) -; RV32IDZFH-NEXT: sw a3, 12(s0) -; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 32 -; RV32IDZFH-NEXT: ret -; -; RV64IDZFH-LABEL: fcvt_q_h: -; RV64IDZFH: # %bb.0: -; RV64IDZFH-NEXT: addi sp, sp, -16 -; RV64IDZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IDZFH-NEXT: fcvt.s.h fa0, fa0 -; RV64IDZFH-NEXT: call __extendsftf2 -; RV64IDZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IDZFH-NEXT: addi sp, sp, 16 -; RV64IDZFH-NEXT: ret -; -; RV32IZDINXZHINX-LABEL: fcvt_q_h: -; RV32IZDINXZHINX: # %bb.0: -; RV32IZDINXZHINX-NEXT: addi sp, sp, -32 -; RV32IZDINXZHINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IZDINXZHINX-NEXT: mv s0, a0 -; RV32IZDINXZHINX-NEXT: fcvt.s.h a1, a1 -; RV32IZDINXZHINX-NEXT: addi a0, sp, 8 -; RV32IZDINXZHINX-NEXT: call __extendsftf2 -; RV32IZDINXZHINX-NEXT: lw a0, 8(sp) -; RV32IZDINXZHINX-NEXT: lw a1, 12(sp) -; RV32IZDINXZHINX-NEXT: lw a2, 16(sp) -; RV32IZDINXZHINX-NEXT: lw a3, 20(sp) -; RV32IZDINXZHINX-NEXT: sw a0, 0(s0) -; RV32IZDINXZHINX-NEXT: sw a1, 4(s0) -; RV32IZDINXZHINX-NEXT: sw a2, 8(s0) -; RV32IZDINXZHINX-NEXT: sw a3, 12(s0) -; RV32IZDINXZHINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZDINXZHINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IZDINXZHINX-NEXT: addi sp, sp, 32 -; RV32IZDINXZHINX-NEXT: ret -; -; RV64IZDINXZHINX-LABEL: fcvt_q_h: -; RV64IZDINXZHINX: # %bb.0: -; RV64IZDINXZHINX-NEXT: addi sp, sp, -16 -; RV64IZDINXZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64IZDINXZHINX-NEXT: fcvt.s.h a0, a0 -; RV64IZDINXZHINX-NEXT: call __extendsftf2 -; RV64IZDINXZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64IZDINXZHINX-NEXT: addi sp, sp, 16 -; RV64IZDINXZHINX-NEXT: ret +; CHECK32-IZFH-LABEL: fcvt_q_h: +; CHECK32-IZFH: # %bb.0: +; CHECK32-IZFH-NEXT: addi sp, sp, -32 +; CHECK32-IZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; CHECK32-IZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; CHECK32-IZFH-NEXT: mv s0, a0 +; CHECK32-IZFH-NEXT: fcvt.s.h fa0, fa0 +; CHECK32-IZFH-NEXT: addi a0, sp, 8 +; CHECK32-IZFH-NEXT: call __extendsftf2 +; CHECK32-IZFH-NEXT: lw a0, 8(sp) +; CHECK32-IZFH-NEXT: lw a1, 12(sp) +; CHECK32-IZFH-NEXT: lw a2, 16(sp) +; CHECK32-IZFH-NEXT: lw a3, 20(sp) +; CHECK32-IZFH-NEXT: sw a0, 0(s0) +; CHECK32-IZFH-NEXT: sw a1, 4(s0) +; CHECK32-IZFH-NEXT: sw a2, 8(s0) +; CHECK32-IZFH-NEXT: sw a3, 12(s0) +; CHECK32-IZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; CHECK32-IZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; CHECK32-IZFH-NEXT: addi sp, sp, 32 +; CHECK32-IZFH-NEXT: ret +; +; CHECK64-IZFH-LABEL: fcvt_q_h: +; CHECK64-IZFH: # %bb.0: +; CHECK64-IZFH-NEXT: addi sp, sp, -16 +; CHECK64-IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK64-IZFH-NEXT: fcvt.s.h fa0, fa0 +; CHECK64-IZFH-NEXT: call __extendsftf2 +; CHECK64-IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK64-IZFH-NEXT: addi sp, sp, 16 +; CHECK64-IZFH-NEXT: ret +; +; CHECK32-IZHINX-LABEL: fcvt_q_h: +; CHECK32-IZHINX: # %bb.0: +; CHECK32-IZHINX-NEXT: addi sp, sp, -32 +; CHECK32-IZHINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; CHECK32-IZHINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; CHECK32-IZHINX-NEXT: mv s0, a0 +; CHECK32-IZHINX-NEXT: fcvt.s.h a1, a1 +; CHECK32-IZHINX-NEXT: addi a0, sp, 8 +; CHECK32-IZHINX-NEXT: call __extendsftf2 +; CHECK32-IZHINX-NEXT: lw a0, 8(sp) +; CHECK32-IZHINX-NEXT: lw a1, 12(sp) +; CHECK32-IZHINX-NEXT: lw a2, 16(sp) +; CHECK32-IZHINX-NEXT: lw a3, 20(sp) +; CHECK32-IZHINX-NEXT: sw a0, 0(s0) +; CHECK32-IZHINX-NEXT: sw a1, 4(s0) +; CHECK32-IZHINX-NEXT: sw a2, 8(s0) +; CHECK32-IZHINX-NEXT: sw a3, 12(s0) +; CHECK32-IZHINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; CHECK32-IZHINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; CHECK32-IZHINX-NEXT: addi sp, sp, 32 +; CHECK32-IZHINX-NEXT: ret +; +; CHECK64-IZHINX-LABEL: fcvt_q_h: +; CHECK64-IZHINX: # %bb.0: +; CHECK64-IZHINX-NEXT: addi sp, sp, -16 +; CHECK64-IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK64-IZHINX-NEXT: fcvt.s.h a0, a0 +; CHECK64-IZHINX-NEXT: call __extendsftf2 +; CHECK64-IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK64-IZHINX-NEXT: addi sp, sp, 16 +; CHECK64-IZHINX-NEXT: ret ; ; CHECK32-IZFHMIN-LABEL: fcvt_q_h: ; CHECK32-IZFHMIN: # %bb.0: @@ -2907,38 +2060,6 @@ define fp128 @fcvt_q_h(half %a) nounwind strictfp { ; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16 ; CHECK64-IZHINXMIN-NEXT: ret ; -; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_q_h: -; CHECK32-IZDINXZHINXMIN: # %bb.0: -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -32 -; CHECK32-IZDINXZHINXMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; CHECK32-IZDINXZHINXMIN-NEXT: mv s0, a0 -; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a1, a1 -; CHECK32-IZDINXZHINXMIN-NEXT: addi a0, sp, 8 -; CHECK32-IZDINXZHINXMIN-NEXT: call __extendsftf2 -; CHECK32-IZDINXZHINXMIN-NEXT: lw a0, 8(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: lw a1, 12(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: lw a2, 16(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: lw a3, 20(sp) -; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 0(s0) -; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 4(s0) -; CHECK32-IZDINXZHINXMIN-NEXT: sw a2, 8(s0) -; CHECK32-IZDINXZHINXMIN-NEXT: sw a3, 12(s0) -; CHECK32-IZDINXZHINXMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; CHECK32-IZDINXZHINXMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 32 -; CHECK32-IZDINXZHINXMIN-NEXT: ret -; -; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_q_h: -; CHECK64-IZDINXZHINXMIN: # %bb.0: -; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, -16 -; CHECK64-IZDINXZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 -; CHECK64-IZDINXZHINXMIN-NEXT: call __extendsftf2 -; CHECK64-IZDINXZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, 16 -; CHECK64-IZDINXZHINXMIN-NEXT: ret -; ; CHECK32-D-LABEL: fcvt_q_h: ; CHECK32-D: # %bb.0: ; CHECK32-D-NEXT: addi sp, sp, -32 |