diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips')
513 files changed, 1321 insertions, 1321 deletions
diff --git a/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll b/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll index 5e6092fc7848..d233ef978276 100644 --- a/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll +++ b/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s define i64 @add64(i64 %u, i64 %v) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll b/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll index 7654ef271fcc..51d73a319494 100644 --- a/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll +++ b/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s %struct.sret0 = type { i32, i32, i32 } diff --git a/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll b/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll index 29c8e8446e3d..dcd3adc3c671 100644 --- a/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll +++ b/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=single-float < %s | FileCheck %s define double @dofloat(float %a) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll b/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll index 9a6bbdfb22ff..a748841afe76 100644 --- a/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll +++ b/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=single-float < %s | FileCheck %s define double @int2fp(i32 %a) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll index 8807d750e499..ae9d739e0219 100644 --- a/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll +++ b/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll index 9c547f15c9a6..8fe8ac539a90 100644 --- a/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll +++ b/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -o %t +; RUN: llc < %s -mtriple=mips -o %t ; RUN: grep "c\..*\.s" %t | count 3 ; RUN: grep "bc1[tf]" %t | count 3 diff --git a/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll b/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll index e88e3d3755c4..e962ec6cfb8b 100644 --- a/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll +++ b/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips | grep "b[ne][eq]" | count 1 +; RUN: llc < %s -mtriple=mips | grep "b[ne][eq]" | count 1 ; FIXME: Disabled because branch instructions are generated where ; conditional move instructions are expected. diff --git a/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll b/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll index f152acc9a15d..cfbea9cf6277 100644 --- a/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll +++ b/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -o %t +; RUN: llc < %s -mtriple=mips -o %t ; RUN: grep abs.s %t | count 1 ; RUN: grep neg.s %t | count 1 diff --git a/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll b/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll index 74a3f218379b..4eaf00950074 100644 --- a/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll +++ b/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s %struct.DWstruct = type { i32, i32 } diff --git a/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll b/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll index 7c19c15ca7bb..c3931417a758 100644 --- a/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll +++ b/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll @@ -1,5 +1,5 @@ ; Double return in abicall (default) -; RUN: llc < %s -march=mips +; RUN: llc < %s -mtriple=mips ; PR2615 define double @main(...) { diff --git a/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll b/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll index 2b1713c39f72..18c01065dec9 100644 --- a/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll +++ b/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll @@ -1,4 +1,4 @@ -; DISABLED: llc < %s -march=mips -o %t +; DISABLED: llc < %s -mtriple=mips -o %t ; DISABLED: grep {lui.*32767} %t | count 1 ; DISABLED: grep {ori.*65535} %t | count 1 ; RUN: false diff --git a/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll b/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll index 78a49ffbe444..8fcda34f889a 100644 --- a/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll +++ b/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s define float @A(i32 %u) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll b/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll index 84d92e3189ea..e4c648888cce 100644 --- a/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll +++ b/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s define i32 @twoalloca(i32 %size) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-08-07-CC.ll b/llvm/test/CodeGen/Mips/2008-08-07-CC.ll index 63c25951423a..cc7493759d42 100644 --- a/llvm/test/CodeGen/Mips/2008-08-07-CC.ll +++ b/llvm/test/CodeGen/Mips/2008-08-07-CC.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips +; RUN: llc < %s -mtriple=mips ; Mips must ignore fastcc target datalayout = diff --git a/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll b/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll index 4fa43b6833bd..ff15bdf367df 100644 --- a/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll +++ b/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=single-float < %s | FileCheck %s define float @round2float(double %a) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll b/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll index abd61de5a8d8..e76aef9a1340 100644 --- a/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll +++ b/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s define i32 @A0(i32 %u) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll b/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll index d2e054b17973..ed3938d2b42f 100644 --- a/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll +++ b/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips +; RUN: llc < %s -mtriple=mips ; PR2794 define i32 @main(ptr) nounwind { diff --git a/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll b/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll index d80da658d928..c2a8eb06fbce 100644 --- a/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll +++ b/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=+soft-float < %s +; RUN: llc -mtriple=mips -mattr=+soft-float < %s ; PR2667 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" %struct._Bigint = type { ptr, i32, i32, i32, i32, [1 x i32] } diff --git a/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll b/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll index 6174500d3e0b..05a29ed06bea 100644 --- a/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll +++ b/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s ; CHECK: clz $2, $4 define i32 @t1(i32 %X) nounwind readnone { diff --git a/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll b/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll index dcade3c671db..52112e83be53 100644 --- a/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll +++ b/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s ; CHECK: mul $2, $5, $4 define i32 @mul1(i32 %a, i32 %b) nounwind readnone { diff --git a/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll b/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll index 745d57c8e9a2..9cf5c9a72ea0 100644 --- a/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll +++ b/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s @.str = private unnamed_addr constant [7 x i8] c"hello\0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test b/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test index da20e7ef5224..4d32a7fb9cbb 100644 --- a/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test +++ b/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test @@ -1 +1 @@ -RUN: llc -O0 -march=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll +RUN: llc -O0 -mtriple=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll index 2f0f1a04a558..b5bdf840facf 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @b = global i32 1, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll index b5cf2a2030d2..cb2ff41fa7fb 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ ; RUN: < %s -verify-machineinstrs | FileCheck %s define void @testeq(i32, i32) { diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll index b8973efda179..c3b1584a7e9a 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll @@ -1,39 +1,39 @@ ; Targets where we should not enable FastISel. -; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips2 -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -mtriple=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -mtriple=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mattr=mips16 -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -mtriple=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -mtriple=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -mtriple=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -mtriple=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s ; Valid targets for FastISel. -; RUN: llc -march=mips -mcpu=mips32r0 -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r0 -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL -; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL ; The CHECK prefix is being used by those targets that do not support FastISel. diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll b/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll index f89802d1a11c..b1fc6cf52a37 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \ +; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic \ ; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic \ ; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s @ARR = external global [10 x i32], align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll index effa04738388..fb35864171ae 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ ; RUN: -fast-isel-abort=3 | FileCheck %s -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: -fast-isel-abort=3 | FileCheck %s @sj = global i32 200000, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll index 16cba99ad065..6eccc9f498da 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ +; RUN: not --crash llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 \ ; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s ; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll index b69000fc625e..baac59508236 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \ +; RUN: not --crash llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+soft-float \ ; RUN: -O0 -fast-isel-abort=3 -relocation-model=pic < %s ; Test that FastISel aborts instead of trying to lower arguments for soft-float. diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll index 73e5f714802f..6044e6b6dd90 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s -verify-machineinstrs | FileCheck %s %struct.x = type { i32 } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll index 0aec8d506f77..9156cc6da25e 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: -pass-remarks-missed=isel 2>&1 | FileCheck %s ; CHECK: FastISel missed call: diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll index 95270ff6b272..a60b9673ad8b 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s @f1 = common global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll index fbd5039f20a1..1d4d8ed6d27c 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @f = global float 0x40147E6B80000000, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll index 67b509938c40..57226a94a759 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll index 0a414316fa1b..36a8cbfd558d 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @d = global double 0x40147E6B74DF0446, align 8 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll index 53783c11785f..3cd2f6b43a50 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @c = global i32 4, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll index 37e49c2e8a42..3462f1d2b9d4 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel-elf -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ ; RUN: < %s -verify-machineinstrs | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll index 66c1f4f30c15..31ad7df23a96 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ ; RUN: < %s -verify-machineinstrs | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll index 93865a9b5c12..a5c1cec0ea11 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll @@ -4,9 +4,9 @@ target triple = "mips--linux-gnu" @c2 = common global i8 0, align 1 @c1 = common global i8 0, align 1 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @s2 = common global i16 0, align 2 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll index 2a75b808cb7e..740aa78459a1 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @b2 = global i8 0, align 1 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll index 66b615bad4dc..bc6f2c50a805 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll index 494dcd19a5b8..90db1fde96fe 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s @ub1 = common global i8 0, align 1 @ub2 = common global i8 0, align 1 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll index 8713e7ef1d96..d84a10b2b111 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic ; The test is just to make sure it is able to allocate ; registers for this example. There was an issue with allocating AC0 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll index 617b9bb07dd9..cb71cb426e64 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll index 2ed6117dd733..8f2b8c5ecc7a 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @x = common global [128000 x float] zeroinitializer, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll index cc0fc47d1b87..c37278350785 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ ; RUN: -fast-isel-abort=3 | FileCheck %s -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: -fast-isel-abort=3 | FileCheck %s @sj = global i32 200, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll index c8023e97d593..dcfe84e4d222 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s @i = global i32 75, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll index 923ccaede29d..b49478998a86 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 \ ; RUN: -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 \ ; RUN: -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s @s1 = global i16 -89, align 2 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll index d029ea4973b4..25df91a6fae9 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @abcd = external global i32 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll index 1957453f5506..d1a0574a1982 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @f = common global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll index 2f73d1cb890c..ee174ddbc25d 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ +; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @ijk = external global i32 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll b/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll index f0974d580fe7..0541b8de7f47 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -fast-isel -frame-pointer=all -relocation-model=pic < %s +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -fast-isel -frame-pointer=all -relocation-model=pic < %s ; Test that negative array access don't crash constant synthesis when fast isel ; generates negative offsets. diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir index 3c81427231a3..c3ccc820fc02 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir @@ -209,10 +209,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -242,10 +242,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -275,10 +275,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -308,10 +308,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -341,10 +341,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -374,10 +374,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -407,10 +407,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -440,10 +440,10 @@ body: | ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 - ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] - ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]] - ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ICMP2]], [[ICMP]] + ; MIPS32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]] + ; MIPS32-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] + ; MIPS32-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]] ; MIPS32-NEXT: $v0 = COPY [[SELECT]](s32) ; MIPS32-NEXT: RetRA implicit $v0 %2:_(s32) = COPY $a0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll index 49f2a78683b0..2f8d075bf766 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll @@ -188,8 +188,8 @@ entry: define i1 @sgt_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: sgt_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: slt $2, $7, $5 ; MIPS32-NEXT: sltu $1, $6, $4 +; MIPS32-NEXT: slt $2, $7, $5 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra @@ -202,10 +202,10 @@ entry: define i1 @sge_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: sge_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: slt $1, $5, $7 -; MIPS32-NEXT: xori $2, $1, 1 ; MIPS32-NEXT: sltu $1, $4, $6 ; MIPS32-NEXT: xori $1, $1, 1 +; MIPS32-NEXT: slt $2, $5, $7 +; MIPS32-NEXT: xori $2, $2, 1 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra @@ -218,8 +218,8 @@ entry: define i1 @slt_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: slt_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: slt $2, $5, $7 ; MIPS32-NEXT: sltu $1, $4, $6 +; MIPS32-NEXT: slt $2, $5, $7 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra @@ -232,10 +232,10 @@ entry: define i1 @sle_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: sle_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: slt $1, $7, $5 -; MIPS32-NEXT: xori $2, $1, 1 ; MIPS32-NEXT: sltu $1, $6, $4 ; MIPS32-NEXT: xori $1, $1, 1 +; MIPS32-NEXT: slt $2, $7, $5 +; MIPS32-NEXT: xori $2, $2, 1 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra @@ -248,8 +248,8 @@ entry: define i1 @ugt_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: ugt_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sltu $2, $7, $5 ; MIPS32-NEXT: sltu $1, $6, $4 +; MIPS32-NEXT: sltu $2, $7, $5 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra @@ -262,10 +262,10 @@ entry: define i1 @uge_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: uge_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sltu $1, $5, $7 -; MIPS32-NEXT: xori $2, $1, 1 ; MIPS32-NEXT: sltu $1, $4, $6 ; MIPS32-NEXT: xori $1, $1, 1 +; MIPS32-NEXT: sltu $2, $5, $7 +; MIPS32-NEXT: xori $2, $2, 1 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra @@ -278,8 +278,8 @@ entry: define i1 @ult_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: ult_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sltu $2, $5, $7 ; MIPS32-NEXT: sltu $1, $4, $6 +; MIPS32-NEXT: sltu $2, $5, $7 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra @@ -292,10 +292,10 @@ entry: define i1 @ule_i64(i64 %a, i64 %b) { ; MIPS32-LABEL: ule_i64: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: sltu $1, $7, $5 -; MIPS32-NEXT: xori $2, $1, 1 ; MIPS32-NEXT: sltu $1, $6, $4 ; MIPS32-NEXT: xori $1, $1, 1 +; MIPS32-NEXT: sltu $2, $7, $5 +; MIPS32-NEXT: xori $2, $2, 1 ; MIPS32-NEXT: xor $3, $5, $7 ; MIPS32-NEXT: movz $2, $1, $3 ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/addc.ll b/llvm/test/CodeGen/Mips/addc.ll index 6877b3b633ce..13467ac84c81 100644 --- a/llvm/test/CodeGen/Mips/addc.ll +++ b/llvm/test/CodeGen/Mips/addc.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s -; RUN: llc < %s -march=mips | FileCheck %s +; RUN: llc < %s -mtriple=mipsel | FileCheck %s +; RUN: llc < %s -mtriple=mips | FileCheck %s define void @f(i64 %l, ptr nocapture %p) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/address-selection.ll b/llvm/test/CodeGen/Mips/address-selection.ll index d7b3fc66813c..8b269aeb83b3 100644 --- a/llvm/test/CodeGen/Mips/address-selection.ll +++ b/llvm/test/CodeGen/Mips/address-selection.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips -relocation-model=pic -mattr=+xgot < %s \ +; RUN: llc -mtriple=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot < %s \ ; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MIPS-XGOT -; RUN: llc -march=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -relocation-model=pic -mattr=+xgot,+micromips < %s \ +; RUN: llc -mtriple=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot,+micromips < %s \ ; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MM-XGOT ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Mips/addressing-mode.ll b/llvm/test/CodeGen/Mips/addressing-mode.ll index bd8daf45be2c..9d4363765c96 100644 --- a/llvm/test/CodeGen/Mips/addressing-mode.ll +++ b/llvm/test/CodeGen/Mips/addressing-mode.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll b/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll index c583ff0fdd6c..821904686a43 100644 --- a/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll +++ b/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=M16 -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips3 -target-abi n64 | FileCheck %s -check-prefix=GP64 -; RUN: llc < %s -march=mips -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=GP64 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips -mattr=mips16 | FileCheck %s -check-prefix=M16 +; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips3 -target-abi n64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -mtriple=mips -mcpu=mips64r6 -target-abi n64 | FileCheck %s -check-prefix=GP64 declare void @bar(ptr) diff --git a/llvm/test/CodeGen/Mips/alloca.ll b/llvm/test/CodeGen/Mips/alloca.ll index 1fd6d859954a..e4ac0e46044c 100644 --- a/llvm/test/CodeGen/Mips/alloca.ll +++ b/llvm/test/CodeGen/Mips/alloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s define i32 @twoalloca(i32 %size) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/alloca16.ll b/llvm/test/CodeGen/Mips/alloca16.ll index b6921d59e94c..f074b2d56936 100644 --- a/llvm/test/CodeGen/Mips/alloca16.ll +++ b/llvm/test/CodeGen/Mips/alloca16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 25, align 4 @jjjj = global i32 35, align 4 diff --git a/llvm/test/CodeGen/Mips/and1.ll b/llvm/test/CodeGen/Mips/and1.ll index 7b5380fab2fd..e3577343dbe7 100644 --- a/llvm/test/CodeGen/Mips/and1.ll +++ b/llvm/test/CodeGen/Mips/and1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/llvm/test/CodeGen/Mips/ase_warnings.ll b/llvm/test/CodeGen/Mips/ase_warnings.ll index ede830c72ebe..35103b4012a6 100644 --- a/llvm/test/CodeGen/Mips/ase_warnings.ll +++ b/llvm/test/CodeGen/Mips/ase_warnings.ll @@ -1,61 +1,61 @@ ; Check msa warnings. -; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=MSA_32 -; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+msa < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=MSA_64 -; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r5 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=MSA_32_NO_WARNING -; RUN: llc -march=mips64 -mattr=+mips64r5 -mattr=+msa < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r5 -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=MSA_64_NO_WARNING ; Check dspr2 warnings. -; RUN: llc -march=mips -mattr=+mips32 -mattr=+dspr2 < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32 -mattr=+dspr2 < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSPR2_32 -; RUN: llc -march=mips64 -mattr=+mips64 -mattr=+dspr2 < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64 -mattr=+dspr2 < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSPR2_64 -; RUN: llc -march=mips64 -mattr=+mips64r3 -mattr=+dspr2 < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r3 -mattr=+dspr2 < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSPR2_64_NO_WARNING -; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+dspr2 < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+dspr2 < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSPR2_32_NO_WARNING ; Check dsp warnings. -; RUN: llc -march=mips -mattr=+mips32 -mattr=+dsp < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32 -mattr=+dsp < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSP_32 -; RUN: llc -march=mips64 -mattr=+mips64 -mattr=+dsp < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64 -mattr=+dsp < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSP_64 -; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+dsp < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r5 -mattr=+dsp < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSP_32_NO_WARNING -; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+dsp < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+dsp < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=DSP_64_NO_WARNING ; Check virt warnings. -; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+virt < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+virt < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=VIRT_32 -; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+virt < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+virt < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=VIRT_64 -; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+virt < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r5 -mattr=+virt < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=VIRT_32_NO_WARNING -; RUN: llc -march=mips64 -mattr=+mips64r5 -mattr=+virt < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r5 -mattr=+virt < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=VIRT_64_NO_WARNING ; Check crc warnings. -; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+crc < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+crc < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=CRC_32 -; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+crc < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+crc < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=CRC_64 -; RUN: llc -march=mips -mattr=+mips32r6 -mattr=+crc < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r6 -mattr=+crc < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=CRC_32_NO_WARNING -; RUN: llc -march=mips64 -mattr=+mips64r6 -mattr=+crc < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r6 -mattr=+crc < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=CRC_64_NO_WARNING ; Check ginv warnings. -; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+ginv < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+ginv < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=GINV_32 -; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+ginv < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+ginv < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=GINV_64 -; RUN: llc -march=mips -mattr=+mips32r6 -mattr=+ginv < %s 2>&1 | \ +; RUN: llc -mtriple=mips -mattr=+mips32r6 -mattr=+ginv < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=GINV_32_NO_WARNING -; RUN: llc -march=mips64 -mattr=+mips64r6 -mattr=+ginv < %s 2>&1 | \ +; RUN: llc -mtriple=mips64 -mattr=+mips64r6 -mattr=+ginv < %s 2>&1 | \ ; RUN: FileCheck %s -check-prefix=GINV_64_NO_WARNING ; MSA_32: warning: the 'msa' ASE requires MIPS32 revision 5 or greater diff --git a/llvm/test/CodeGen/Mips/asm-large-immediate.ll b/llvm/test/CodeGen/Mips/asm-large-immediate.ll index c75b9e4ad12b..848be30839a8 100644 --- a/llvm/test/CodeGen/Mips/asm-large-immediate.ll +++ b/llvm/test/CodeGen/Mips/asm-large-immediate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -no-integrated-as < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -no-integrated-as < %s | FileCheck %s define void @test() { entry: diff --git a/llvm/test/CodeGen/Mips/assertzext-trunc.ll b/llvm/test/CodeGen/Mips/assertzext-trunc.ll index 2295727834eb..a6b9c0a2066a 100644 --- a/llvm/test/CodeGen/Mips/assertzext-trunc.ll +++ b/llvm/test/CodeGen/Mips/assertzext-trunc.ll @@ -1,16 +1,16 @@ -; RUN: llc < %s -march=mips64 -mcpu=mips3 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | \ ; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \ ; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \ ; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \ ; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | \ ; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | \ ; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \ ; RUN: FileCheck %s -check-prefixes=ALL,R6 ; Check that we don't emit redundant SLLs for sequences of diff --git a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll index 5273f499cede..f3308c4b6ad1 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 -; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 define i64 @test_max(ptr nocapture %ptr, i64 signext %val) { ; MIPS-LABEL: test_max: diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll index 3d3225509d1a..85bf6d02c7d8 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll @@ -1,17 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 -; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 -; RUN: llc -march=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL -; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 -; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL -; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6 -; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64 -; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6 -; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL -; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6 +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6 +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6 +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL +; RUN: llc -mtriple=mipsel-elf -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64 +; RUN: llc -mtriple=mips64-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL +; RUN: llc -mtriple=mips64el-elf -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6 define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) { ; MIPS-LABEL: test_max_32: diff --git a/llvm/test/CodeGen/Mips/atomicops.ll b/llvm/test/CodeGen/Mips/atomicops.ll index 14e401e1f096..906429b14a18 100644 --- a/llvm/test/CodeGen/Mips/atomicops.ll +++ b/llvm/test/CodeGen/Mips/atomicops.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [8 x i8] c"%d, %d\0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/beqzc.ll b/llvm/test/CodeGen/Mips/beqzc.ll index 11e009bcc79e..28f3f8c144b6 100644 --- a/llvm/test/CodeGen/Mips/beqzc.ll +++ b/llvm/test/CodeGen/Mips/beqzc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/beqzc1.ll b/llvm/test/CodeGen/Mips/beqzc1.ll index ad41ae271bb4..915f34e63ff2 100644 --- a/llvm/test/CodeGen/Mips/beqzc1.ll +++ b/llvm/test/CodeGen/Mips/beqzc1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/biggot.ll b/llvm/test/CodeGen/Mips/biggot.ll index 1080922ade80..50d72b9219c5 100644 --- a/llvm/test/CodeGen/Mips/biggot.ll +++ b/llvm/test/CodeGen/Mips/biggot.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -mattr=+xgot \ +; RUN: llc -mtriple=mipsel -mattr=+xgot \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+xgot \ +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+xgot \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=N64 -; RUN: llc -march=mipsel -mattr=+xgot -fast-isel \ +; RUN: llc -mtriple=mipsel -mattr=+xgot -fast-isel \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+xgot -fast-isel \ +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+xgot -fast-isel \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=N64 @v0 = external global i32 diff --git a/llvm/test/CodeGen/Mips/blockaddr.ll b/llvm/test/CodeGen/Mips/blockaddr.ll index b1ab9a171eb9..92184e7ed6bd 100644 --- a/llvm/test/CodeGen/Mips/blockaddr.ll +++ b/llvm/test/CodeGen/Mips/blockaddr.ll @@ -10,7 +10,7 @@ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64 ; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi n64 \ ; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 \ +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32 -mattr=+mips16 \ ; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-MIPS16 @reg = common global ptr null, align 4 diff --git a/llvm/test/CodeGen/Mips/brconeq.ll b/llvm/test/CodeGen/Mips/brconeq.ll index ba7dc0f8540e..7c23db8d96fc 100644 --- a/llvm/test/CodeGen/Mips/brconeq.ll +++ b/llvm/test/CodeGen/Mips/brconeq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconeqk.ll b/llvm/test/CodeGen/Mips/brconeqk.ll index 4ee2f772ff68..98d8b07bc809 100644 --- a/llvm/test/CodeGen/Mips/brconeqk.ll +++ b/llvm/test/CodeGen/Mips/brconeqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconeqz.ll b/llvm/test/CodeGen/Mips/brconeqz.ll index b8e7d1d12f97..fbc50a7701b3 100644 --- a/llvm/test/CodeGen/Mips/brconeqz.ll +++ b/llvm/test/CodeGen/Mips/brconeqz.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconge.ll b/llvm/test/CodeGen/Mips/brconge.ll index 38e3a7c3706f..4e91f4624aa6 100644 --- a/llvm/test/CodeGen/Mips/brconge.ll +++ b/llvm/test/CodeGen/Mips/brconge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brcongt.ll b/llvm/test/CodeGen/Mips/brcongt.ll index 3231811588fc..1152167f3a8a 100644 --- a/llvm/test/CodeGen/Mips/brcongt.ll +++ b/llvm/test/CodeGen/Mips/brcongt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconle.ll b/llvm/test/CodeGen/Mips/brconle.ll index e0ade5df2377..d68362f253a3 100644 --- a/llvm/test/CodeGen/Mips/brconle.ll +++ b/llvm/test/CodeGen/Mips/brconle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16 @i = global i32 -5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconlt.ll b/llvm/test/CodeGen/Mips/brconlt.ll index f3dbb9607eaf..522db0d9e2da 100644 --- a/llvm/test/CodeGen/Mips/brconlt.ll +++ b/llvm/test/CodeGen/Mips/brconlt.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips-elf -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/brconne.ll b/llvm/test/CodeGen/Mips/brconne.ll index 5c3a0ef34329..e673727def7d 100644 --- a/llvm/test/CodeGen/Mips/brconne.ll +++ b/llvm/test/CodeGen/Mips/brconne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 5, align 4 diff --git a/llvm/test/CodeGen/Mips/brconnek.ll b/llvm/test/CodeGen/Mips/brconnek.ll index 30c32825da52..f963be59c12f 100644 --- a/llvm/test/CodeGen/Mips/brconnek.ll +++ b/llvm/test/CodeGen/Mips/brconnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brconnez.ll b/llvm/test/CodeGen/Mips/brconnez.ll index 5f8b54e9cbb5..15ba7c16cb3d 100644 --- a/llvm/test/CodeGen/Mips/brconnez.ll +++ b/llvm/test/CodeGen/Mips/brconnez.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 0, align 4 @result = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/brind.ll b/llvm/test/CodeGen/Mips/brind.ll index 8f2954fd2b25..1cc7fdd6bef8 100644 --- a/llvm/test/CodeGen/Mips/brind.ll +++ b/llvm/test/CodeGen/Mips/brind.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @main.L = internal unnamed_addr constant [5 x ptr] [ptr blockaddress(@main, %L1), ptr blockaddress(@main, %L2), ptr blockaddress(@main, %L3), ptr blockaddress(@main, %L4), ptr null], align 4 @str = private unnamed_addr constant [2 x i8] c"A\00" diff --git a/llvm/test/CodeGen/Mips/brsize3.ll b/llvm/test/CodeGen/Mips/brsize3.ll index a93de3269510..1aea201af96b 100644 --- a/llvm/test/CodeGen/Mips/brsize3.ll +++ b/llvm/test/CodeGen/Mips/brsize3.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 \ ; RUN: -mattr=+soft-float -mips16-hard-float -relocation-model=pic \ ; RUN: -mips16-constant-islands -verify-machineinstrs < %s | \ ; RUN: FileCheck %s -check-prefix=b-no-short -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 \ ; RUN: -mattr=+soft-float -mips16-hard-float -relocation-model=pic \ ; RUN: -mips16-constant-islands -verify-machineinstrs < %s | \ ; RUN: FileCheck %s -check-prefix=b-long diff --git a/llvm/test/CodeGen/Mips/brsize3a.ll b/llvm/test/CodeGen/Mips/brsize3a.ll index 87f96203047e..de866f210e7b 100644 --- a/llvm/test/CodeGen/Mips/brsize3a.ll +++ b/llvm/test/CodeGen/Mips/brsize3a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-short +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-short ; ModuleID = 'brsize3.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/llvm/test/CodeGen/Mips/brundef.ll b/llvm/test/CodeGen/Mips/brundef.ll index d63b587af039..b353862c6edd 100644 --- a/llvm/test/CodeGen/Mips/brundef.ll +++ b/llvm/test/CodeGen/Mips/brundef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -o /dev/null < %s +; RUN: llc -mtriple=mips -mcpu=mips32 -verify-machineinstrs -o /dev/null < %s ; Confirm that MachineInstr branch simplification preserves ; register operand flags, such as the <undef> flag. diff --git a/llvm/test/CodeGen/Mips/bswap.ll b/llvm/test/CodeGen/Mips/bswap.ll index ace6c3d6021d..fa8cda330ba3 100644 --- a/llvm/test/CodeGen/Mips/bswap.ll +++ b/llvm/test/CodeGen/Mips/bswap.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 \ ; RUN: | FileCheck %s -check-prefix=MIPS32 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: | FileCheck %s -check-prefix=MM -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 \ +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 \ ; RUN: | FileCheck %s -check-prefix=MIPS64 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+mips16 \ +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+mips16 \ ; RUN: | FileCheck %s -check-prefix=MIPS16 define i32 @bswap32(i32 signext %x) nounwind readnone { diff --git a/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll b/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll index 95b9ca8caf02..1c1323b10f0a 100644 --- a/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll +++ b/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL -; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL +; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL @a = external global i32 diff --git a/llvm/test/CodeGen/Mips/call-optimization.ll b/llvm/test/CodeGen/Mips/call-optimization.ll index 89fb970ed817..e48c29115019 100644 --- a/llvm/test/CodeGen/Mips/call-optimization.ll +++ b/llvm/test/CodeGen/Mips/call-optimization.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=O32 -; RUN: llc -march=mipsel -mips-load-target-from-got=false \ +; RUN: llc -mtriple=mipsel -mips-load-target-from-got=false \ ; RUN: -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck %s -check-prefix=O32-LOADTGT @gd1 = common global double 0.000000e+00, align 8 diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll b/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll index f2355049adfa..533f8b6426bc 100644 --- a/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll +++ b/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB -; RUN: llc < %s -march=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL -; RUN: llc < %s -march=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB -; RUN: llc < %s -march=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL +; RUN: llc < %s -mtriple=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB +; RUN: llc < %s -mtriple=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL +; RUN: llc < %s -mtriple=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB +; RUN: llc < %s -mtriple=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL ; #include <stdio.h> ; diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll index 0619ebe48cfe..6f94dce7f8a6 100644 --- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll +++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll @@ -1,4 +1,4 @@ -; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s +; RUN: llc --mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s ; Generated from the C program: ; diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll index db066c047514..485aab499189 100644 --- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll +++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll @@ -1,4 +1,4 @@ -; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s +; RUN: llc --mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s ; Generated from the C program: ; diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll index 3bddbf9d450a..0193a90d6e9c 100644 --- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll +++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll @@ -1,4 +1,4 @@ -; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s +; RUN: llc --mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s ; Generated from the C program: ; diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll index 1a604e7b5e89..741d5e3645ca 100644 --- a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll +++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s +; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s +; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s +; RUN-TODO: llc -mtriple=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN-TODO: llc -mtriple=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s +; RUN-TODO: llc -mtriple=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s +; RUN-TODO: llc -mtriple=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s define void @fpu_clobber() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll index 1c2f9e2be341..e4f5564910c3 100644 --- a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll +++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll @@ -1,13 +1,13 @@ -; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s \ +; RUN: llc -mtriple=mips -mattr=+o32,+fp64,+mips32r2 < %s \ ; RUN: | FileCheck --check-prefix=O32-FP64-INV %s -; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s \ +; RUN: llc -mtriple=mipsel -mattr=+o32,+fp64,+mips32r2 < %s \ ; RUN: | FileCheck --check-prefix=O32-FP64-INV %s -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s +; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s +; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s +; RUN-TODO: llc -mtriple=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s +; RUN-TODO: llc -mtriple=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s define void @fpu_clobber() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved.ll index 8cfd1397ed97..93808fbcad03 100644 --- a/llvm/test/CodeGen/Mips/cconv/callee-saved.ll +++ b/llvm/test/CodeGen/Mips/cconv/callee-saved.ll @@ -1,33 +1,33 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s \ +; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s \ ; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s \ +; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s \ ; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s \ +; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s \ ; RUN-TODO: | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s \ +; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s \ ; RUN-TODO: | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN: llc -march=mips64 -target-abi n32 < %s \ +; RUN: llc -mtriple=mips64 -target-abi n32 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s \ +; RUN: llc -mtriple=mips64el -target-abi n32 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s \ +; RUN: llc -mtriple=mips64 -target-abi n32 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N32-INV %s -; RUN: llc -march=mips64el -target-abi n32 < %s \ +; RUN: llc -mtriple=mips64el -target-abi n32 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N32-INV %s -; RUN: llc -march=mips64 -target-abi n64 < %s \ +; RUN: llc -mtriple=mips64 -target-abi n64 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s \ +; RUN: llc -mtriple=mips64el -target-abi n64 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64 -target-abi n64 < %s \ +; RUN: llc -mtriple=mips64 -target-abi n64 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N64-INV %s -; RUN: llc -march=mips64el -target-abi n64 < %s \ +; RUN: llc -mtriple=mips64el -target-abi n64 < %s \ ; RUN: | FileCheck --check-prefixes=ALL,N64-INV %s ; Test the callee-saved registers are callee-saved as specified by section diff --git a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll index dae4bfc22609..c95fe09de20e 100644 --- a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll +++ b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips-elf < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-elf -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the memory layout for all ABI's and byte orders as specified by section ; 4 of MD00305 (MIPS ABIs Described). diff --git a/llvm/test/CodeGen/Mips/cconv/pr33883.ll b/llvm/test/CodeGen/Mips/cconv/pr33883.ll index 54d7286ab8ff..9fecf09ef3c2 100644 --- a/llvm/test/CodeGen/Mips/cconv/pr33883.ll +++ b/llvm/test/CodeGen/Mips/cconv/pr33883.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s -o /dev/null +; RUN: llc -mtriple=mips -mcpu=mips32 < %s -o /dev/null ; Test that calls to vector intrinsics do not crash SelectionDAGBuilder. diff --git a/llvm/test/CodeGen/Mips/cconv/reserved-space.ll b/llvm/test/CodeGen/Mips/cconv/reserved-space.ll index 0a922345ddf3..490476961626 100644 --- a/llvm/test/CodeGen/Mips/cconv/reserved-space.ll +++ b/llvm/test/CodeGen/Mips/cconv/reserved-space.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test that O32 correctly reserved space for the four arguments, even when ; there aren't any as per section 5 of MD00305 (MIPS ABIs Described). diff --git a/llvm/test/CodeGen/Mips/cconv/roundl-call.ll b/llvm/test/CodeGen/Mips/cconv/roundl-call.ll index 242b4292e528..98bda89546e4 100644 --- a/llvm/test/CodeGen/Mips/cconv/roundl-call.ll +++ b/llvm/test/CodeGen/Mips/cconv/roundl-call.ll @@ -1,22 +1,22 @@ -; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ +; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ ; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ +; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ ; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT -; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ +; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ ; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \ +; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT -; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ +; RUN: llc -mtriple=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT -; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ +; RUN: llc -mtriple=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ ; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT -; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \ +; RUN: llc -mtriple=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \ ; RUN: -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,N64,SOFT-FLOAT -; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \ +; RUN: llc -mtriple=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \ ; RUN: %s -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,N64,SOFT-FLOAT diff --git a/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll b/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll index c957e311b1b3..9cdb8428b484 100644 --- a/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll +++ b/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the stack alignment for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/llvm/test/CodeGen/Mips/cfi_offset.ll b/llvm/test/CodeGen/Mips/cfi_offset.ll index 217adda59468..e55924e2f535 100644 --- a/llvm/test/CodeGen/Mips/cfi_offset.ll +++ b/llvm/test/CodeGen/Mips/cfi_offset.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -mtriple=mips-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -mtriple=mipsel-elf -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL @var = global double 0.0 diff --git a/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll b/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll index cf0fda66ad62..f22848c1c45c 100644 --- a/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll +++ b/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll @@ -1,16 +1,16 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL define i64 @add_i64(i64 %a) { ; GP32-LABEL: add_i64 diff --git a/llvm/test/CodeGen/Mips/check-noat.ll b/llvm/test/CodeGen/Mips/check-noat.ll index cfcd367e87af..1e53eda4d63f 100644 --- a/llvm/test/CodeGen/Mips/check-noat.ll +++ b/llvm/test/CodeGen/Mips/check-noat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s define void @f() nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/ci2.ll b/llvm/test/CodeGen/Mips/ci2.ll index 9546656ebf25..a9497296c8e4 100644 --- a/llvm/test/CodeGen/Mips/ci2.ll +++ b/llvm/test/CodeGen/Mips/ci2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=constisle +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=constisle @i = common global i32 0, align 4 @b = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/cins.ll b/llvm/test/CodeGen/Mips/cins.ll index 4fe25564d1c1..39d80e3bb36a 100644 --- a/llvm/test/CodeGen/Mips/cins.ll +++ b/llvm/test/CodeGen/Mips/cins.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64 -mcpu=octeon -target-abi=n64 < %s -o - | FileCheck %s +; RUN: llc -mtriple=mips64 -mcpu=octeon -target-abi=n64 < %s -o - | FileCheck %s define i64 @cins_zext(i32 signext %n) { entry: diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll index d19c1b1f14c3..bb3c7c27a122 100644 --- a/llvm/test/CodeGen/Mips/cmov.ll +++ b/llvm/test/CodeGen/Mips/cmov.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV -; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV -; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV -; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP -; RUN: llc -march=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV -; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV -; RUN: llc -march=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP +; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -mtriple=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP +; RUN: llc -mtriple=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global ptr null, align 4 diff --git a/llvm/test/CodeGen/Mips/cmplarge.ll b/llvm/test/CodeGen/Mips/cmplarge.ll index a64983dfed02..db7f37a88ac2 100644 --- a/llvm/test/CodeGen/Mips/cmplarge.ll +++ b/llvm/test/CodeGen/Mips/cmplarge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=cmp16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=cmp16 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" target triple = "mipsel--linux-gnu" diff --git a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir index bfdd5cfd8b53..de7286611f95 100644 --- a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir +++ b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips64 -o - %s -run-pass=register-coalescer -verify-coalescing | FileCheck %s +# RUN: llc -mtriple=mips64 -o - %s -run-pass=register-coalescer -verify-coalescing | FileCheck %s --- name: f diff --git a/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll b/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll index 13e30676aa6f..b0eeadfecf6e 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll +++ b/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s -; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s ; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0 diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir index 33e43ad06f12..dfaad3a01bb7 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir +++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s +# RUN: llc -mtriple=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s # Check that MipsHazardSchedule sees through basic blocks with transient instructions. # The mir code in this file isn't representative of the llvm-ir. diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll index c819bf59ace6..5a206f2d8891 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll +++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll @@ -1,7 +1,7 @@ ; Check that -mips-compact-branches={never,optimal,always} is accepted and honoured. -; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER -; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL -; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS define i32 @l(i32 signext %a, i32 signext %b) { entry: diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll b/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll index 1ba80bff8d5a..a808bec149ea 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll +++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll @@ -1,4 +1,4 @@ -; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips64r6 \ +; RUN: llc -relocation-model=pic -mtriple=mipsel -mcpu=mips64r6 \ ; RUN: -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir index a2caf5b67aab..41f59f535a4c 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir +++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s +# RUN: llc -mtriple=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s # Check that empty blocks in the cfg don't cause the mips hazard scheduler to # crash and that the nop is inserted correctly. diff --git a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll index de61515cff9b..99efc5e8e441 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll +++ b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 < %s | FileCheck %s -; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r6 < %s | FileCheck %s +; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r6 < %s | FileCheck %s @boo = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/const1.ll b/llvm/test/CodeGen/Mips/const1.ll index 429107cfdbcd..750912d94f90 100644 --- a/llvm/test/CodeGen/Mips/const1.ll +++ b/llvm/test/CodeGen/Mips/const1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s ; ModuleID = 'const1.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/llvm/test/CodeGen/Mips/const4a.ll b/llvm/test/CodeGen/Mips/const4a.ll index 757629de5da3..245abbfe196c 100644 --- a/llvm/test/CodeGen/Mips/const4a.ll +++ b/llvm/test/CodeGen/Mips/const4a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax ; ModuleID = 'const4.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/llvm/test/CodeGen/Mips/const6.ll b/llvm/test/CodeGen/Mips/const6.ll index 27e8eace4b16..f40eeef3ccb6 100644 --- a/llvm/test/CodeGen/Mips/const6.ll +++ b/llvm/test/CodeGen/Mips/const6.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax ; ModuleID = 'const6.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/llvm/test/CodeGen/Mips/const6a.ll b/llvm/test/CodeGen/Mips/const6a.ll index 5a3f4a1f951e..720edd3a662b 100644 --- a/llvm/test/CodeGen/Mips/const6a.ll +++ b/llvm/test/CodeGen/Mips/const6a.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax1 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax ; ModuleID = 'const6a.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/llvm/test/CodeGen/Mips/constantfp0.ll b/llvm/test/CodeGen/Mips/constantfp0.ll index 191f31d01319..dd0ddca036c3 100644 --- a/llvm/test/CodeGen/Mips/constantfp0.ll +++ b/llvm/test/CodeGen/Mips/constantfp0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s define i32 @branch(double %d) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/constraint-c-err.ll b/llvm/test/CodeGen/Mips/constraint-c-err.ll index 94768f89e992..43229d1d38d9 100644 --- a/llvm/test/CodeGen/Mips/constraint-c-err.ll +++ b/llvm/test/CodeGen/Mips/constraint-c-err.ll @@ -1,5 +1,5 @@ ; Check that invalid type for constraint `c` causes an error message. -; RUN: not llc -march=mips -target-abi o32 < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=mips -target-abi o32 < %s 2>&1 | FileCheck %s define i32 @main() #0 { entry: diff --git a/llvm/test/CodeGen/Mips/constraint-c.ll b/llvm/test/CodeGen/Mips/constraint-c.ll index 31b75b01a5e8..85eda164a1a6 100644 --- a/llvm/test/CodeGen/Mips/constraint-c.ll +++ b/llvm/test/CodeGen/Mips/constraint-c.ll @@ -1,5 +1,5 @@ ; Check handling of the constraint `c`. -; RUN: llc -march=mips -target-abi o32 < %s | FileCheck %s +; RUN: llc -mtriple=mips -target-abi o32 < %s | FileCheck %s define i32 @main() #0 { entry: diff --git a/llvm/test/CodeGen/Mips/constraint-empty.ll b/llvm/test/CodeGen/Mips/constraint-empty.ll index 8541a4fa348e..ff2b9b840852 100644 --- a/llvm/test/CodeGen/Mips/constraint-empty.ll +++ b/llvm/test/CodeGen/Mips/constraint-empty.ll @@ -1,5 +1,5 @@ ; Check that `getRegForInlineAsmConstraint` does not crash on empty Constraint. -; RUN: llc -march=mips64 < %s | FileCheck %s +; RUN: llc -mtriple=mips64 < %s | FileCheck %s define void @foo() { entry: diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll index 264d0486e3b8..9c512bd3ad38 100644 --- a/llvm/test/CodeGen/Mips/countleading.ll +++ b/llvm/test/CodeGen/Mips/countleading.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R6 %s -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefixes=MIPS4 %s +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R6 %s +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck -check-prefixes=MIPS4 %s ; Prefixes: ; ALL - All diff --git a/llvm/test/CodeGen/Mips/cprestore.ll b/llvm/test/CodeGen/Mips/cprestore.ll index bb27c947d998..2bd7591e38ab 100644 --- a/llvm/test/CodeGen/Mips/cprestore.ll +++ b/llvm/test/CodeGen/Mips/cprestore.ll @@ -1,4 +1,4 @@ -; DISABLE: llc -march=mipsel < %s | FileCheck %s +; DISABLE: llc -mtriple=mipsel < %s | FileCheck %s ; RUN: false ; XFAIL: * diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll b/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll index f34c70efa7a8..6a5f65a96095 100644 --- a/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll +++ b/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=ALL,MIPS -; RUN: llc -march=mips < %s -mattr=+micromips | FileCheck %s -check-prefixes=ALL,MM +; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefixes=ALL,MIPS +; RUN: llc -mtriple=mips < %s -mattr=+micromips | FileCheck %s -check-prefixes=ALL,MM ; Test the patterns used for constant materialization. diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll index b29115a4f782..dc8efae68fda 100644 --- a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll +++ b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll b/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll index 78c01d9b7473..0e9075aa1688 100644 --- a/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll +++ b/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32 -; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32 +; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-MIPS64 -; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \ +; RUN: llc -mtriple=mipsel -mcpu=mips64 -target-abi n32 < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-MIPSN32 ; Test that the expansion of ADJCALLSTACKDOWN and ADJCALLSTACKUP generate diff --git a/llvm/test/CodeGen/Mips/ctlz-v.ll b/llvm/test/CodeGen/Mips/ctlz-v.ll index 156c640681b7..280054dac082 100644 --- a/llvm/test/CodeGen/Mips/ctlz-v.ll +++ b/llvm/test/CodeGen/Mips/ctlz-v.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) diff --git a/llvm/test/CodeGen/Mips/ctlz.ll b/llvm/test/CodeGen/Mips/ctlz.ll index efb23f55c2cf..3cc156943f22 100644 --- a/llvm/test/CodeGen/Mips/ctlz.ll +++ b/llvm/test/CodeGen/Mips/ctlz.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static @x = global i32 28912, align 4 @y = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/cttz-v.ll b/llvm/test/CodeGen/Mips/cttz-v.ll index dbcde7f5fe5b..347466086a68 100644 --- a/llvm/test/CodeGen/Mips/cttz-v.ll +++ b/llvm/test/CodeGen/Mips/cttz-v.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) diff --git a/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll b/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll index 8c2ac7a7f2ce..c2376a7b56df 100644 --- a/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll +++ b/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -mcpu=mips32r6 -o /dev/null +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -o /dev/null ; Test that this file is compiled in a reasonable time period. Without the ; optimization level check in findBetterNeighbors, this test demonstrates diff --git a/llvm/test/CodeGen/Mips/delay-slot-kill.ll b/llvm/test/CodeGen/Mips/delay-slot-kill.ll index 57b630303c26..9d51d72721e9 100644 --- a/llvm/test/CodeGen/Mips/delay-slot-kill.ll +++ b/llvm/test/CodeGen/Mips/delay-slot-kill.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s +; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s ; Currently, the following IR assembly generates a KILL instruction between ; the bitwise-and instruction and the return instruction. We verify that the diff --git a/llvm/test/CodeGen/Mips/dext.ll b/llvm/test/CodeGen/Mips/dext.ll index 1794f16b2cd7..b27d67c7da6a 100644 --- a/llvm/test/CodeGen/Mips/dext.ll +++ b/llvm/test/CodeGen/Mips/dext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s define i64 @dext_add_zext(i32 signext %n) { entry: diff --git a/llvm/test/CodeGen/Mips/dins.ll b/llvm/test/CodeGen/Mips/dins.ll index 4deb7455a801..cdb8f419eb2b 100644 --- a/llvm/test/CodeGen/Mips/dins.ll +++ b/llvm/test/CodeGen/Mips/dins.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \ ; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2 -; RUN: llc -O2 -verify-machineinstrs -march=mips -mcpu=mips32r2 < %s -o - \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mcpu=mips32r2 < %s -o - \ ; RUN: | FileCheck %s -check-prefix=MIPS32R2 -; RUN: llc -O2 -verify-machineinstrs -march=mips -mattr=mips16 < %s -o - \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips-elf -mattr=mips16 < %s -o - \ ; RUN: | FileCheck %s -check-prefix=MIPS16 -; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \ +; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64-elf -mcpu=mips64r2 \ ; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32 ; #include <stdint.h> diff --git a/llvm/test/CodeGen/Mips/disable-tail-merge.ll b/llvm/test/CodeGen/Mips/disable-tail-merge.ll index 188b83b68f5d..8e6174c4b3c4 100644 --- a/llvm/test/CodeGen/Mips/disable-tail-merge.ll +++ b/llvm/test/CodeGen/Mips/disable-tail-merge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/div.ll b/llvm/test/CodeGen/Mips/div.ll index 839b2dee6d09..0dd3bb47049a 100644 --- a/llvm/test/CodeGen/Mips/div.ll +++ b/llvm/test/CodeGen/Mips/div.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 100, align 4 @jjjj = global i32 -4, align 4 diff --git a/llvm/test/CodeGen/Mips/div_rem.ll b/llvm/test/CodeGen/Mips/div_rem.ll index c8e22f262fb2..7485ca2df5e8 100644 --- a/llvm/test/CodeGen/Mips/div_rem.ll +++ b/llvm/test/CodeGen/Mips/div_rem.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 -4, align 4 diff --git a/llvm/test/CodeGen/Mips/divrem.ll b/llvm/test/CodeGen/Mips/divrem.ll index b0dd49a06221..a29f2793c081 100644 --- a/llvm/test/CodeGen/Mips/divrem.ll +++ b/llvm/test/CodeGen/Mips/divrem.ll @@ -1,16 +1,16 @@ -; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP -; RUN: llc -march=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP -; RUN: llc -march=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP -; RUN: llc -march=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP -; RUN: llc -march=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP -; RUN: llc -march=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP - -; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK -; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK -; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK +; RUN: llc -mtriple=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP +; RUN: llc -mtriple=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP +; RUN: llc -mtriple=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP +; RUN: llc -mtriple=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP + +; RUN: llc -mtriple=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK +; RUN: llc -mtriple=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK ; FileCheck Prefixes: ; ALL - All targets diff --git a/llvm/test/CodeGen/Mips/divu.ll b/llvm/test/CodeGen/Mips/divu.ll index caa49fd472b3..10348001dd4b 100644 --- a/llvm/test/CodeGen/Mips/divu.ll +++ b/llvm/test/CodeGen/Mips/divu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 100, align 4 @jjjj = global i32 4, align 4 diff --git a/llvm/test/CodeGen/Mips/divu_remu.ll b/llvm/test/CodeGen/Mips/divu_remu.ll index 820633be119b..7a435e922f1a 100644 --- a/llvm/test/CodeGen/Mips/divu_remu.ll +++ b/llvm/test/CodeGen/Mips/divu_remu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 4, align 4 diff --git a/llvm/test/CodeGen/Mips/double2int.ll b/llvm/test/CodeGen/Mips/double2int.ll index f0d8ad28100f..a5ca8b9f46aa 100644 --- a/llvm/test/CodeGen/Mips/double2int.ll +++ b/llvm/test/CodeGen/Mips/double2int.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s define i32 @f1(double %d) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll index a5fe34c1f684..9444fdf32ebd 100644 --- a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll +++ b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=dsp < %s | FileCheck %s ; CHECK-LABEL: select_v2q15_eq_: ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}} diff --git a/llvm/test/CodeGen/Mips/dsp-patterns.ll b/llvm/test/CodeGen/Mips/dsp-patterns.ll index ba6c4d972c56..0f044f968bdb 100644 --- a/llvm/test/CodeGen/Mips/dsp-patterns.ll +++ b/llvm/test/CodeGen/Mips/dsp-patterns.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=R1 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=R1 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2 ; R1-LABEL: test_lbux: ; R1: lbux ${{[0-9]+}} diff --git a/llvm/test/CodeGen/Mips/dsp-r1.ll b/llvm/test/CodeGen/Mips/dsp-r1.ll index 0ec23b9d7fd7..7a661d6c7051 100644 --- a/llvm/test/CodeGen/Mips/dsp-r1.ll +++ b/llvm/test/CodeGen/Mips/dsp-r1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ ; RUN: FileCheck %s define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind { diff --git a/llvm/test/CodeGen/Mips/dsp-r2.ll b/llvm/test/CodeGen/Mips/dsp-r2.ll index 631f9e43c23a..584455cf0c52 100644 --- a/llvm/test/CodeGen/Mips/dsp-r2.ll +++ b/llvm/test/CodeGen/Mips/dsp-r2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=+dspr2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+dspr2 < %s | FileCheck %s define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll b/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll index 2feefcc09879..b1d1f9703fc4 100644 --- a/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll +++ b/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=+dsp < %s +; RUN: llc -mtriple=mipsel -mattr=+dsp < %s @g1 = common global <2 x i8> zeroinitializer, align 2 @g0 = common global <2 x i8> zeroinitializer, align 2 diff --git a/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll b/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll index c201c34f9686..daa0f79af4c3 100644 --- a/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll +++ b/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll @@ -1,24 +1,24 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP32,GP32-M -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP32,GP32-M -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP32,GP32-M -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP32,GP32-MM,GP32-MMR2 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP32,GP32-MM,GP32-MMR6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP64,N64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP64,N64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP64,N64 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -target-abi n32 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP64,N32 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP64,N32 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -target-abi n32 -relocation-model=pic | FileCheck %s \ ; RUN: --check-prefixes=ALL,GP64,N32 ; Check dynamic stack realignment in functions without variable-sized objects. diff --git a/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll b/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll index 2377707b8f72..ce96605572ce 100644 --- a/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll +++ b/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -; RUN: llc -march=mips64el -mcpu=mips4 < %s | \ +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64 < %s | \ +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | \ ; RUN: FileCheck %s -check-prefix=CHECK-MIPS64 declare ptr @llvm.eh.dwarf.cfa(i32) nounwind diff --git a/llvm/test/CodeGen/Mips/eh-return32.ll b/llvm/test/CodeGen/Mips/eh-return32.ll index 983fc6f7788c..0c60c4731095 100644 --- a/llvm/test/CodeGen/Mips/eh-return32.ll +++ b/llvm/test/CodeGen/Mips/eh-return32.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i32(i32, ptr) declare void @foo(...) diff --git a/llvm/test/CodeGen/Mips/eh-return64.ll b/llvm/test/CodeGen/Mips/eh-return64.ll index 9ae2f00d46c1..f5a547a3b608 100644 --- a/llvm/test/CodeGen/Mips/eh-return64.ll +++ b/llvm/test/CodeGen/Mips/eh-return64.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i64(i64, ptr) declare void @foo(...) diff --git a/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll index b1045a08dd3a..3379322f0bf7 100644 --- a/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll +++ b/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -O0 -relocation-model=pic < %s | FileCheck %s ; Check that register scavenging spill slot is close to $fp. target triple="mipsel--" diff --git a/llvm/test/CodeGen/Mips/emit-big-cst.ll b/llvm/test/CodeGen/Mips/emit-big-cst.ll index cd0666cfd3fc..5171e22abab6 100644 --- a/llvm/test/CodeGen/Mips/emit-big-cst.ll +++ b/llvm/test/CodeGen/Mips/emit-big-cst.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=BE -; RUN: llc -march=mipsel < %s | FileCheck %s --check-prefix=LE +; RUN: llc -mtriple=mips-elf < %s | FileCheck %s --check-prefix=BE +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s --check-prefix=LE ; Check assembly printing of odd constants. ; BE-LABEL: bigCst: diff --git a/llvm/test/CodeGen/Mips/ex2.ll b/llvm/test/CodeGen/Mips/ex2.ll index 79aabfcbbfc4..d0fa4058e41e 100644 --- a/llvm/test/CodeGen/Mips/ex2.ll +++ b/llvm/test/CodeGen/Mips/ex2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 @_ZTIPKc = external constant ptr diff --git a/llvm/test/CodeGen/Mips/extins.ll b/llvm/test/CodeGen/Mips/extins.ll index 9989c3c00dc7..e5c66602450e 100644 --- a/llvm/test/CodeGen/Mips/extins.ll +++ b/llvm/test/CodeGen/Mips/extins.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 -; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=16 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -mtriple=mips -mattr=mips16 | FileCheck %s -check-prefix=16 define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/f16abs.ll b/llvm/test/CodeGen/Mips/f16abs.ll index 30ff458f5a46..23bf402bb6dc 100644 --- a/llvm/test/CodeGen/Mips/f16abs.ll +++ b/llvm/test/CodeGen/Mips/f16abs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static @y = global double -1.450000e+00, align 8 @x = common global double 0.000000e+00, align 8 diff --git a/llvm/test/CodeGen/Mips/fastcc.ll b/llvm/test/CodeGen/Mips/fastcc.ll index ccdeedce6d23..e6d12664d83f 100644 --- a/llvm/test/CodeGen/Mips/fastcc.ll +++ b/llvm/test/CodeGen/Mips/fastcc.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=mipsel -relocation-model=pic | FileCheck %s ; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu -relocation-model=pic -mips-tail-calls=1\ ; RUN: | FileCheck %s -check-prefix=CHECK-NACL -; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic -mips-tail-calls=1| FileCheck %s -check-prefix=NOODDSPREG -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic -mips-tail-calls=1 | FileCheck %s -check-prefix=FP64-NOODDSPREG +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic -mips-tail-calls=1| FileCheck %s -check-prefix=NOODDSPREG +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic -mips-tail-calls=1 | FileCheck %s -check-prefix=FP64-NOODDSPREG @gi0 = external global i32 diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll index 34088beb2246..c0b34454d620 100644 --- a/llvm/test/CodeGen/Mips/fcmp.ll +++ b/llvm/test/CodeGen/Mips/fcmp.ll @@ -1,20 +1,20 @@ -; RUN: llc < %s -march=mips -mcpu=mips32 | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32 | \ ; RUN: FileCheck %s -check-prefixes=ALL,32-C -; RUN: llc < %s -march=mips -mcpu=mips32r2 | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | \ ; RUN: FileCheck %s -check-prefixes=ALL,32-C -; RUN: llc < %s -march=mips -mcpu=mips32r6 | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | \ ; RUN: FileCheck %s -check-prefixes=ALL,32-CMP -; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \ ; RUN: FileCheck %s -check-prefixes=ALL,64-C -; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \ ; RUN: FileCheck %s -check-prefixes=ALL,64-C -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \ ; RUN: FileCheck %s -check-prefixes=ALL,64-C -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \ ; RUN: FileCheck %s -check-prefixes=ALL,64-CMP -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32R3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6 define i32 @false_f32(float %a, float %b) nounwind { diff --git a/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll b/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll index 695431a5ab60..ed6b2e08a9b9 100644 --- a/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll +++ b/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips4 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips4 \ ; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64 -; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64 \ ; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64 -; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64r2 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64r2 \ ; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2 declare double @copysign(double, double) nounwind readnone diff --git a/llvm/test/CodeGen/Mips/fcopysign.ll b/llvm/test/CodeGen/Mips/fcopysign.ll index 810d0f958086..7ef9d6376e6d 100644 --- a/llvm/test/CodeGen/Mips/fcopysign.ll +++ b/llvm/test/CodeGen/Mips/fcopysign.ll @@ -1,12 +1,12 @@ -; RUN: llc < %s -verify-machineinstrs -march=mipsel -mcpu=mips32 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mipsel -mcpu=mips32 \ ; RUN: | FileCheck %s -check-prefix=32 -; RUN: llc < %s -verify-machineinstrs -march=mipsel -mcpu=mips32r2 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mipsel -mcpu=mips32r2 \ ; RUN: | FileCheck %s -check-prefix=32R2 -; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips4 -target-abi=n64 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips4 -target-abi=n64 \ ; RUN: | FileCheck %s -check-prefix=64 -; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64 -target-abi=n64 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64 -target-abi=n64 \ ; RUN: | FileCheck %s -check-prefix=64 -; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64r2 -target-abi=n64 \ +; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 \ ; RUN: | FileCheck %s -check-prefix=64R2 define double @func0(double %d0, double %d1) nounwind readnone { diff --git a/llvm/test/CodeGen/Mips/fixdfsf.ll b/llvm/test/CodeGen/Mips/fixdfsf.ll index 07b57f9f9482..e15efe75a60b 100644 --- a/llvm/test/CodeGen/Mips/fixdfsf.ll +++ b/llvm/test/CodeGen/Mips/fixdfsf.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic2 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic1 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic2 @x = common global double 0.000000e+00, align 8 @y = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/fmadd1.ll b/llvm/test/CodeGen/Mips/fmadd1.ll index 4704387bf289..b9380c45ca78 100644 --- a/llvm/test/CodeGen/Mips/fmadd1.ll +++ b/llvm/test/CodeGen/Mips/fmadd1.ll @@ -5,29 +5,29 @@ ; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only ; available when -enable-no-nans-fp-math is given. -; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD ; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated ; when +nomadd attribute is specified. ; Output for mips32 and mips64r6 reused since aforementioned instructions are ; not generated in those cases. -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD define float @FOO0float(float %a, float %b, float %c) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/fp-contract.ll b/llvm/test/CodeGen/Mips/fp-contract.ll index f25e9f5258c7..c43d2a644bb3 100644 --- a/llvm/test/CodeGen/Mips/fp-contract.ll +++ b/llvm/test/CodeGen/Mips/fp-contract.ll @@ -1,11 +1,11 @@ ; Test that the compiled does not fuse fmul and fadd into fmadd when no -fp-contract=fast ; option is set (the same applies for fmul, fsub and fmsub). -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \ +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -fp-contract=off < %s \ +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -fp-contract=off < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -fp-contract=fast < %s \ +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -fp-contract=fast < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-FAST declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/Mips/fp-indexed-ls.ll b/llvm/test/CodeGen/Mips/fp-indexed-ls.ll index 48052b6e8614..8e20c8229847 100644 --- a/llvm/test/CodeGen/Mips/fp-indexed-ls.ll +++ b/llvm/test/CodeGen/Mips/fp-indexed-ls.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R1 -; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2 -; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R6 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6 +; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R1 +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2 +; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R6 +; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6 ; Check that [ls][dwu]xc1 are not emitted for nacl. ; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL diff --git a/llvm/test/CodeGen/Mips/fp-spill-reload.ll b/llvm/test/CodeGen/Mips/fp-spill-reload.ll index 21a7ed040f0f..8a01ec873264 100644 --- a/llvm/test/CodeGen/Mips/fp-spill-reload.ll +++ b/llvm/test/CodeGen/Mips/fp-spill-reload.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s ; check that $fp is not reserved. define void @foo0(ptr nocapture %b) nounwind { diff --git a/llvm/test/CodeGen/Mips/fp16instrinsmc.ll b/llvm/test/CodeGen/Mips/fp16instrinsmc.ll index 168b042f4d4a..6c29c0872051 100644 --- a/llvm/test/CodeGen/Mips/fp16instrinsmc.ll +++ b/llvm/test/CodeGen/Mips/fp16instrinsmc.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask @x = global float 1.500000e+00, align 4 @xn = global float -1.900000e+01, align 4 diff --git a/llvm/test/CodeGen/Mips/fp16mix.ll b/llvm/test/CodeGen/Mips/fp16mix.ll index d97759422cf9..07fc6a67f11d 100644 --- a/llvm/test/CodeGen/Mips/fp16mix.ll +++ b/llvm/test/CodeGen/Mips/fp16mix.ll @@ -1,8 +1,8 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=10 -mips-os16 < %s | FileCheck %s -check-prefix=fmask1 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static -mips32-function-mask=10 -mips-os16 < %s | FileCheck %s -check-prefix=fmask1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=01 -mips-os16 < %s | FileCheck %s -check-prefix=fmask2 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static -mips32-function-mask=01 -mips-os16 < %s | FileCheck %s -check-prefix=fmask2 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=10. -mips-os16 < %s | FileCheck %s -check-prefix=fmask1nr +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static -mips32-function-mask=10. -mips-os16 < %s | FileCheck %s -check-prefix=fmask1nr ; Function Attrs: nounwind optsize readnone define void @foo1() { diff --git a/llvm/test/CodeGen/Mips/fp64a.ll b/llvm/test/CodeGen/Mips/fp64a.ll index 317afd7003bb..392a4f6e4a2d 100644 --- a/llvm/test/CodeGen/Mips/fp64a.ll +++ b/llvm/test/CodeGen/Mips/fp64a.ll @@ -7,16 +7,16 @@ ; We don't test MIPS32r1 since support for 64-bit coprocessors (such as a 64-bit ; FPU) on a 32-bit architecture was added in MIPS32r2. -; RUN: not llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A - -; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A -; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A -; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A -; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A +; RUN: not llc -mtriple=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A + +; RUN: llc -mtriple=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A +; RUN: not llc -mtriple=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A +; RUN: llc -mtriple=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A +; RUN: not llc -mtriple=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A ; 32R1-FP64: LLVM ERROR: FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater. ; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI. diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll index 251c5392575b..7193a426ab0d 100644 --- a/llvm/test/CodeGen/Mips/fpbr.ll +++ b/llvm/test/CodeGen/Mips/fpbr.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define void @func0(float %f2, float %f3) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/fpnotneeded.ll b/llvm/test/CodeGen/Mips/fpnotneeded.ll index d21bd53e949d..761ef3032fc4 100644 --- a/llvm/test/CodeGen/Mips/fpnotneeded.ll +++ b/llvm/test/CodeGen/Mips/fpnotneeded.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-os16 | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32 -relocation-model=static -O3 < %s -mips-os16 | FileCheck %s -check-prefix=32 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -relocation-model=static -O3 -mips16-constant-islands < %s -mips-os16 | FileCheck %s -check-prefix=cisle +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32 -relocation-model=static -O3 -mips16-constant-islands < %s -mips-os16 | FileCheck %s -check-prefix=cisle @i = global i32 1, align 4 @f = global float 1.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/fpxx.ll b/llvm/test/CodeGen/Mips/fpxx.ll index 6fdb95efe8ec..a12aa7406356 100644 --- a/llvm/test/CodeGen/Mips/fpxx.ll +++ b/llvm/test/CodeGen/Mips/fpxx.ll @@ -1,20 +1,20 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32-NOFPXX -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32-FPXX +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32-NOFPXX +; RUN: llc -mtriple=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32-FPXX -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32R2-NOFPXX -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32R2-NOFPXX +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX -; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX -; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX +; RUN: llc -mtriple=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX +; RUN: not llc -mtriple=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX -; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX -; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX +; RUN: llc -mtriple=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX +; RUN: not llc -mtriple=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX +; RUN-TODO: llc -mtriple=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX +; RUN-TODO: llc -mtriple=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,64-O32-NOFPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,64-O32-FPXX +; RUN-TODO: llc -mtriple=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,64-O32-NOFPXX +; RUN-TODO: llc -mtriple=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,64-O32-FPXX declare double @dbl(); diff --git a/llvm/test/CodeGen/Mips/frame-address-err.ll b/llvm/test/CodeGen/Mips/frame-address-err.ll index 45f20ac8119c..9b75d3c66e27 100644 --- a/llvm/test/CodeGen/Mips/frame-address-err.ll +++ b/llvm/test/CodeGen/Mips/frame-address-err.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=mips < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=mips < %s 2>&1 | FileCheck %s declare ptr @llvm.frameaddress(i32) nounwind readnone diff --git a/llvm/test/CodeGen/Mips/frame-address.ll b/llvm/test/CodeGen/Mips/frame-address.ll index 685d1fe1f465..8f73cb33c4b6 100644 --- a/llvm/test/CodeGen/Mips/frame-address.ll +++ b/llvm/test/CodeGen/Mips/frame-address.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf < %s | FileCheck %s declare ptr @llvm.frameaddress(i32) nounwind readnone diff --git a/llvm/test/CodeGen/Mips/frem.ll b/llvm/test/CodeGen/Mips/frem.ll index be222b2d9172..556ca6c2e7e7 100644 --- a/llvm/test/CodeGen/Mips/frem.ll +++ b/llvm/test/CodeGen/Mips/frem.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel +; RUN: llc < %s -mtriple=mipsel define float @fmods(float %x, float %y) { entry: diff --git a/llvm/test/CodeGen/Mips/funnel-shift-rot.ll b/llvm/test/CodeGen/Mips/funnel-shift-rot.ll index ee187678949e..1fc2f5d309b5 100644 --- a/llvm/test/CodeGen/Mips/funnel-shift-rot.ll +++ b/llvm/test/CodeGen/Mips/funnel-shift-rot.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=mips-linux-gnu -march=mips -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-BE -; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-LE +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-BE +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-LE declare i8 @llvm.fshl.i8(i8, i8, i8) declare i16 @llvm.fshl.i16(i16, i16, i16) diff --git a/llvm/test/CodeGen/Mips/funnel-shift.ll b/llvm/test/CodeGen/Mips/funnel-shift.ll index bda2b477b52f..99e0d47441a0 100644 --- a/llvm/test/CodeGen/Mips/funnel-shift.ll +++ b/llvm/test/CodeGen/Mips/funnel-shift.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=mips-linux-gnu -march=mips -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-BE -; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-LE +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-BE +; RUN: llc < %s -mtriple=mipsel-linux-gnu -mcpu=mips32 | FileCheck %s --check-prefixes=CHECK,CHECK-LE declare i8 @llvm.fshl.i8(i8, i8, i8) declare i16 @llvm.fshl.i16(i16, i16, i16) diff --git a/llvm/test/CodeGen/Mips/global-pointer-reg.ll b/llvm/test/CodeGen/Mips/global-pointer-reg.ll index 3cb2aaed4766..a616fa3ec2fa 100644 --- a/llvm/test/CodeGen/Mips/global-pointer-reg.ll +++ b/llvm/test/CodeGen/Mips/global-pointer-reg.ll @@ -1,4 +1,4 @@ -; DISABLED: llc < %s -march=mipsel -mips-fix-global-base-reg=false | FileCheck %s +; DISABLED: llc < %s -mtriple=mipsel -mips-fix-global-base-reg=false | FileCheck %s ; RUN: false ; XFAIL: * diff --git a/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll b/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll index 35cebdf302b5..ae6627a8c768 100644 --- a/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll +++ b/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -disable-mips-delay-filler -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s @g = external global i32 diff --git a/llvm/test/CodeGen/Mips/helloworld.ll b/llvm/test/CodeGen/Mips/helloworld.ll index 152f8533fc36..ba010aafef1c 100644 --- a/llvm/test/CodeGen/Mips/helloworld.ll +++ b/llvm/test/CodeGen/Mips/helloworld.ll @@ -1,11 +1,11 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST2 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST2 ; -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR32 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR32 @.str = private unnamed_addr constant [13 x i8] c"hello world\0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/hf16_1.ll b/llvm/test/CodeGen/Mips/hf16_1.ll index 327f04f64859..611e53f4fd2f 100644 --- a/llvm/test/CodeGen/Mips/hf16_1.ll +++ b/llvm/test/CodeGen/Mips/hf16_1.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=1 -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=2 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=1 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=2 @x = common global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/hf16call32.ll b/llvm/test/CodeGen/Mips/hf16call32.ll index 881ad12d65a2..e187b76744b8 100644 --- a/llvm/test/CodeGen/Mips/hf16call32.ll +++ b/llvm/test/CodeGen/Mips/hf16call32.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel @x = common global float 0.000000e+00, align 4 @y = common global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/hf16call32_body.ll b/llvm/test/CodeGen/Mips/hf16call32_body.ll index 88cc02a9f795..ea83f776bd40 100644 --- a/llvm/test/CodeGen/Mips/hf16call32_body.ll +++ b/llvm/test/CodeGen/Mips/hf16call32_body.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel @x = external global float @xd = external global double diff --git a/llvm/test/CodeGen/Mips/hf1_body.ll b/llvm/test/CodeGen/Mips/hf1_body.ll index c3dea6789621..ec452e02757d 100644 --- a/llvm/test/CodeGen/Mips/hf1_body.ll +++ b/llvm/test/CodeGen/Mips/hf1_body.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 \ ; RUN: -relocation-model=pic -no-integrated-as < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,GAS ; The integrated assembler expands assembly macros before printing. -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 \ ; RUN: -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,IAS diff --git a/llvm/test/CodeGen/Mips/hfptrcall.ll b/llvm/test/CodeGen/Mips/hfptrcall.ll index b4749058ba76..920c6945c25c 100644 --- a/llvm/test/CodeGen/Mips/hfptrcall.ll +++ b/llvm/test/CodeGen/Mips/hfptrcall.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picel +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picel @ptrsv = global ptr @sv, align 4 @ptrdv = global ptr @dv, align 4 diff --git a/llvm/test/CodeGen/Mips/i32k.ll b/llvm/test/CodeGen/Mips/i32k.ll index 130a467433fc..681bdeebc06d 100644 --- a/llvm/test/CodeGen/Mips/i32k.ll +++ b/llvm/test/CodeGen/Mips/i32k.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -mips16-constant-islands=false -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic -mips16-constant-islands=false -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/i64arg.ll b/llvm/test/CodeGen/Mips/i64arg.ll index ec26cdc6776c..2af16f7d23f3 100644 --- a/llvm/test/CodeGen/Mips/i64arg.ll +++ b/llvm/test/CodeGen/Mips/i64arg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s +; RUN: llc -mtriple=mips -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/imm.ll b/llvm/test/CodeGen/Mips/imm.ll index eea391e8707e..bf62df699282 100644 --- a/llvm/test/CodeGen/Mips/imm.ll +++ b/llvm/test/CodeGen/Mips/imm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s define i32 @foo0() nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll b/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll index 759e84b02007..cb01e605e9a1 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s ; Check for the emission of appropriate assembler directives before and ; after the inline assembly code. diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll index aa75a1d0a9bc..f04e64889e00 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s @data = global [8193 x i32] zeroinitializer diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll index f3431aa4c825..fb075c268626 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT -; RUN: llc -march=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT +; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT +; RUN: llc -mtriple=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT @data = global [8193 x i32] zeroinitializer diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll index b05f586b1351..6071469e82bd 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6 -; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6 +; RUN: llc -mtriple=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \ ; RUN: < %s | FileCheck %s --check-prefixes=ALL,R6 -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6 -; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6 +; RUN: llc -mtriple=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \ ; RUN: < %s | FileCheck %s --check-prefixes=ALL,PRER6 diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll index c09108dc0744..48b754f3a6ca 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll @@ -2,7 +2,7 @@ ;This is a negative test. The constant value given for the constraint ;is greater than 16 bits. ; -; RUN: not llc -march=mipsel < %s 2> %t +; RUN: not llc -mtriple=mipsel < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll index 2b24b0f82c57..1239263287f3 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll @@ -2,7 +2,7 @@ ;This is a negative test. The constant value given for the constraint (J) ;is non-zero (3). ; -; RUN: not llc -march=mipsel < %s 2> %t +; RUN: not llc -mtriple=mipsel < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll index 3baf437324ac..13a41e8dc04e 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll @@ -2,7 +2,7 @@ ;This is a negative test. The constant value given for the constraint (K) ;is greater than 16 bits (0x00100000). ; -; RUN: not llc -march=mipsel < %s 2> %t +; RUN: not llc -mtriple=mipsel < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll index 5edb3e24674e..75b42e8c93a0 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll @@ -2,7 +2,7 @@ ;This is a negative test. The constant value given for the constraint (L) ;is non-zero in the lower 16 bits (0x00100003). ; -; RUN: not llc -march=mipsel < %s 2> %t +; RUN: not llc -mtriple=mipsel < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll index eaa540acdafa..84121ad8ddd4 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll @@ -3,7 +3,7 @@ ;immediate in the range of -65535 to -1 (inclusive). ;Our example uses the positive value 3. ; -; RUN: not llc -march=mipsel < %s 2> %t +; RUN: not llc -mtriple=mipsel < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll index 56afbaaa9cd6..e4b760955a65 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll @@ -3,7 +3,7 @@ ;signed 15 bit immediate (+- 16383). ;Our example uses the positive value 16384. ; -; RUN: not llc -march=mipsel < %s 2> %t +; RUN: not llc -mtriple=mipsel < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll index 0a55cb55e5f2..c240e3457e48 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll @@ -3,7 +3,7 @@ ; A constant in the range of 1 to 655535 inclusive. ; Our example uses the positive value 655536. ; -; RUN: not llc -march=mipsel < %s 2> %t +; RUN: not llc -mtriple=mipsel < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll index a2a863671d40..27be7815c19f 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s @data = global [8193 x i32] zeroinitializer diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll index 295b93b6f182..9ec7f8196cd2 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mips -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips -relocation-model=pic < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,EB %s -; RUN: llc -march=mipsel -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s \ ; RUN: | FileCheck --check-prefixes=CHECK,EL %s ; Simple memory diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll index 550446deb581..356c5f41f527 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s @data = global [8193 x i32] zeroinitializer diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll index 4d3a288875fa..19dd3d6b39a6 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll @@ -1,7 +1,7 @@ ; Positive test for inline register constraints ; -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck %s define i32 @main() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll index ae0504980cc2..661c0cb717f7 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll @@ -4,7 +4,7 @@ ; The target is 64 bit. ; ; -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint.ll index 164d28f733e4..fbbe50b133b2 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraint.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraint.ll @@ -1,6 +1,6 @@ -; RUN: llc -no-integrated-as -march=mipsel < %s | \ +; RUN: llc -no-integrated-as -mtriple=mipsel < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,GAS -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS +; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS define void @constraint_I() nounwind { ; First I with short diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll index 705570f808ce..6366972e2b49 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips64 < %s | FileCheck %s --check-prefix=MIPS64 +; RUN: llc -mtriple=mips < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mips64 < %s | FileCheck %s --check-prefix=MIPS64 define dso_local void @read_double(ptr nocapture noundef readonly %0) local_unnamed_addr #0 { ; MIPS32-LABEL: read_double: diff --git a/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll b/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll index e94b608d047e..3bf1a26641cf 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll @@ -1,7 +1,7 @@ ; Negative test for the 'm' operand code. This operand code is applicable ; for an immediate whic is exact power of 2. -; RUN: not llc -march=mips < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=mips < %s 2>&1 | FileCheck %s define i32 @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll index 88e56a89cd7b..db9edb2974f9 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -1,14 +1,14 @@ ; Positive test for inline register constraints ; -; RUN: llc -no-integrated-as -march=mipsel -relocation-model=pic < %s | \ +; RUN: llc -no-integrated-as -mtriple=mipsel -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefixes=ALL,LE32,GAS %s -; RUN: llc -no-integrated-as -march=mips -relocation-model=pic < %s | \ +; RUN: llc -no-integrated-as -mtriple=mips -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefixes=ALL,BE32,GAS %s ; IAS might not print in the same way since it parses the assembly. -; RUN: llc -march=mipsel -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefixes=ALL,LE32,IAS %s -; RUN: llc -march=mips -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefixes=ALL,BE32,IAS %s %union.u_tag = type { i64 } diff --git a/llvm/test/CodeGen/Mips/ins.ll b/llvm/test/CodeGen/Mips/ins.ll index 615dc8f3d6ac..06e493bcd759 100644 --- a/llvm/test/CodeGen/Mips/ins.ll +++ b/llvm/test/CodeGen/Mips/ins.ll @@ -1,6 +1,6 @@ ; RUN: llc -O3 -mcpu=mips32r2 -mtriple=mipsel-linux-gnu < %s -o - \ ; RUN: | FileCheck %s --check-prefixes=MIPS32R2 -; RUN: llc -O3 -mcpu=mips64r2 -march=mips64el < %s \ +; RUN: llc -O3 -mcpu=mips64r2 -mtriple=mips64el < %s \ ; RUN: | FileCheck %s --check-prefixes=MIPS64R2 define i32 @or_and_shl(i32 %a, i32 %b) { diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir index 02dd9085c31e..1574eeb11a3d 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir index 97cb085eac50..2e750aade31a 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir index e76af1be9493..9a0e9a37282c 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir index 264968382447..e3862d7d242e 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir index fc24a2756c6a..74522e991d97 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir index 7001221bb0db..f69f20fcfb7e 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir index b9e3b8c169e4..52e5b6d0f692 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir index 6663b96494ab..75c1c1e44c6c 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK-NOT: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir index 8407a7a836f7..b001b42c2cf3 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir index d72837850cfb..c881d65898ee 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir index 71d4242c948c..b074b8782194 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir index 35848a936e5c..c9a3410aef67 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir index a00d3cf715a7..0ae16d1d43d6 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir index 0bbbdd232245..fe622e12e7fe 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir index c1f5f044bdee..2ae4dc7c9f2b 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir index 9f9953a85565..34c509a016fc 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir index 12e999d5d488..7ce2c9509f9e 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir index f204a3373f76..9e185cb943f2 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir index c7b16fd50ab0..da42bac7140c 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir index ce2abeb3cdcf..1762d8942aee 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir index 57737ea60283..42158f63872c 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir index 1e48f1e8a236..72d6d690429e 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir index c72e6f5a3be3..c2464d3d94c2 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir index 92319bd3ff8a..050e909933ef 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/int-to-float-conversion.ll b/llvm/test/CodeGen/Mips/int-to-float-conversion.ll index 6444d1fe8556..84bc6a253595 100644 --- a/llvm/test/CodeGen/Mips/int-to-float-conversion.ll +++ b/llvm/test/CodeGen/Mips/int-to-float-conversion.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global ptr null, align 4 diff --git a/llvm/test/CodeGen/Mips/internalfunc.ll b/llvm/test/CodeGen/Mips/internalfunc.ll index 7db46f54da53..34bf5d03d8f9 100644 --- a/llvm/test/CodeGen/Mips/internalfunc.ll +++ b/llvm/test/CodeGen/Mips/internalfunc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=mipsel -relocation-model=pic | FileCheck %s @caller.sf1 = internal unnamed_addr global ptr null, align 4 @gf1 = external global ptr diff --git a/llvm/test/CodeGen/Mips/jumptable_labels.ll b/llvm/test/CodeGen/Mips/jumptable_labels.ll index 8ae22be9dd23..075b57e08d35 100644 --- a/llvm/test/CodeGen/Mips/jumptable_labels.ll +++ b/llvm/test/CodeGen/Mips/jumptable_labels.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mips64 -target-abi=n32 < %s | FileCheck %s -check-prefix=N32 -; RUN: llc -march=mips64 < %s | FileCheck %s -check-prefix=N64 +; RUN: llc -mtriple=mips-elf < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -mtriple=mips64-elf -target-abi=n32 < %s | FileCheck %s -check-prefix=N32 +; RUN: llc -mtriple=mips64-elf < %s | FileCheck %s -check-prefix=N64 ; We only use the '$' prefix on O32. The others use the ELF convention. ; O32: $JTI0_0 diff --git a/llvm/test/CodeGen/Mips/l3mc.ll b/llvm/test/CodeGen/Mips/l3mc.ll index b45208256628..440da3abb53f 100644 --- a/llvm/test/CodeGen/Mips/l3mc.ll +++ b/llvm/test/CodeGen/Mips/l3mc.ll @@ -1,22 +1,22 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfsi +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfsi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdidf +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdidf -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdisf +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdisf -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundidf +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundidf -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixsfdi +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixsfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfdi +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixdfdi +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixdfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfsi +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfsi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfdi +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundisf +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundisf @ll1 = global i64 0, align 8 @ll2 = global i64 0, align 8 diff --git a/llvm/test/CodeGen/Mips/largeimm1.ll b/llvm/test/CodeGen/Mips/largeimm1.ll index adef511a4aad..5d1987941363 100644 --- a/llvm/test/CodeGen/Mips/largeimm1.ll +++ b/llvm/test/CodeGen/Mips/largeimm1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s define void @f() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/largeimmprinting.ll b/llvm/test/CodeGen/Mips/largeimmprinting.ll index eed9e12eac8b..efa0aa63abf6 100644 --- a/llvm/test/CodeGen/Mips/largeimmprinting.ll +++ b/llvm/test/CodeGen/Mips/largeimmprinting.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=64 %struct.S1 = type { [65536 x i8] } diff --git a/llvm/test/CodeGen/Mips/lazy-binding.ll b/llvm/test/CodeGen/Mips/lazy-binding.ll index 4f5c71effe69..e9860acb91bb 100644 --- a/llvm/test/CodeGen/Mips/lazy-binding.ll +++ b/llvm/test/CodeGen/Mips/lazy-binding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s ; CHECK-LABEL: foo6: ; CHECK: %while.body diff --git a/llvm/test/CodeGen/Mips/lb1.ll b/llvm/test/CodeGen/Mips/lb1.ll index caff4c7fa33a..7d93a9076d3c 100644 --- a/llvm/test/CodeGen/Mips/lb1.ll +++ b/llvm/test/CodeGen/Mips/lb1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @c = global i8 -1, align 1 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/lbu1.ll b/llvm/test/CodeGen/Mips/lbu1.ll index 13fe20af1aef..c492c0d4784d 100644 --- a/llvm/test/CodeGen/Mips/lbu1.ll +++ b/llvm/test/CodeGen/Mips/lbu1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @c = global i8 97, align 1 @.str = private unnamed_addr constant [5 x i8] c"%c \0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/lcb2.ll b/llvm/test/CodeGen/Mips/lcb2.ll index 7f9e71d5efec..036de382b621 100644 --- a/llvm/test/CodeGen/Mips/lcb2.ll +++ b/llvm/test/CodeGen/Mips/lcb2.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcb +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcb -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcbn +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcbn @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/lcb3c.ll b/llvm/test/CodeGen/Mips/lcb3c.ll index 386059f144dd..40912f3701f3 100644 --- a/llvm/test/CodeGen/Mips/lcb3c.ll +++ b/llvm/test/CodeGen/Mips/lcb3c.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -O0 < %s | FileCheck %s -check-prefix=lcb +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -O0 < %s | FileCheck %s -check-prefix=lcb @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/lcb4a.ll b/llvm/test/CodeGen/Mips/lcb4a.ll index 87089a779558..a0258b15e84a 100644 --- a/llvm/test/CodeGen/Mips/lcb4a.ll +++ b/llvm/test/CodeGen/Mips/lcb4a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/lcb5.ll b/llvm/test/CodeGen/Mips/lcb5.ll index bb059f1ee845..22baebac3e93 100644 --- a/llvm/test/CodeGen/Mips/lcb5.ll +++ b/llvm/test/CodeGen/Mips/lcb5.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/lh1.ll b/llvm/test/CodeGen/Mips/lh1.ll index 4ec8d928cd06..5d4facc38ce6 100644 --- a/llvm/test/CodeGen/Mips/lh1.ll +++ b/llvm/test/CodeGen/Mips/lh1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @s = global i16 -1, align 2 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/lhu1.ll b/llvm/test/CodeGen/Mips/lhu1.ll index 1d438b6093de..561e8461552f 100644 --- a/llvm/test/CodeGen/Mips/lhu1.ll +++ b/llvm/test/CodeGen/Mips/lhu1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @s = global i16 255, align 2 diff --git a/llvm/test/CodeGen/Mips/llcarry.ll b/llvm/test/CodeGen/Mips/llcarry.ll index 4bba047ba1f0..45e4cbd2a597 100644 --- a/llvm/test/CodeGen/Mips/llcarry.ll +++ b/llvm/test/CodeGen/Mips/llcarry.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i64 4294967295, align 8 @j = global i64 15, align 8 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/abs.ll b/llvm/test/CodeGen/Mips/llvm-ir/abs.ll index c0812977e3a1..e4dde185b48b 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/abs.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/abs.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 define float @abs_s(float %a) { ; MIPS32: {{(ori|ins)}} diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll index 84c4bf677f94..f6b3b96aaa0c 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,PRE4 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR3,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll b/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll index bddbdc667bd6..71a9ca80b95f 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL ; Address spaces 1-255 are software defined. define ptr @cast(ptr %arg) { diff --git a/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll index 33a86bbc5dee..7b56deae3c09 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 define double @add_d(double %a, double %b) { ; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll b/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll index 2e03ee9868a9..3a1a9bee56c2 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll @@ -1,6 +1,6 @@ -; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s | \ +; RUN: llc -asm-show-inst -mtriple=mipsel -mcpu=mips32r6 < %s | \ ; RUN: FileCheck %s -check-prefix=CHK32 -; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s | \ +; RUN: llc -asm-show-inst -mtriple=mips64el -mcpu=mips64r6 < %s | \ ; RUN: FileCheck %s -check-prefix=CHK64 @a = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll index a649234342dd..a4a2f920a7d7 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst \ +; RUN: llc -mtriple=mips -mcpu=mips32r2 -asm-show-inst \ ; RUN: < %s | FileCheck %s --check-prefix=MIPS32R2 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst \ +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst \ ; RUN: < %s | FileCheck %s --check-prefix=MIPS32FP64 -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst \ +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst \ ; RUN: < %s | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \ +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \ ; RUN: < %s | FileCheck %s --check-prefix=MMFP64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst \ +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst \ ; RUN: < %s | FileCheck %s --check-prefix=MMR6 define double @mthc1(i64 %a) { diff --git a/llvm/test/CodeGen/Mips/llvm-ir/call.ll b/llvm/test/CodeGen/Mips/llvm-ir/call.ll index a259bdd04c2e..a962e1763618 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/call.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/call.ll @@ -1,29 +1,29 @@ ; Test the 'call' instruction and the tailcall variant. -; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C -; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C -; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,R6C -; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C -; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C -; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C -; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C -; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C +; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -mtriple=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,R6C +; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C +; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C +; RUN: llc -mtriple=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C declare void @extern_void_void() declare i32 @extern_i32_void() diff --git a/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll index 04368f202fa5..0901c8cbfda7 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 +; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 ; TODO: Test for cvt_w_d is missing, could not generate instruction diff --git a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll index 4f926cbee0b2..290491a13d77 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL +; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL ; This test triggered a bug in the vector splitting where the type legalizer ; attempted to extract the element with by storing the vector, then reading diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll index aebeac9e5bd2..c9490e59a623 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -1,16 +1,16 @@ ; Test all important variants of the unconditional 'br' instruction. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C +; RUN: llc -mtriple=mips64-elf -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 define i32 @br(ptr %addr) { ; ALL-LABEL: br: diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll b/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll index 4e434617d39e..f38aa78dd587 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s @us = global i16 0, align 2 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll b/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll index f401b0a1d6c9..16c09003298c 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ +; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,M64 -; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,M64 define i8 @load_i8(ptr %ptr) { diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll index 19955e4f9bbd..00b91d1413cf 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll @@ -1,30 +1,30 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=ALL,64R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=MM32,MM32R3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=MM32,MM32R6 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { diff --git a/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll b/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll index 918cda6b38c2..34c7720ecbe0 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll @@ -1,20 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s --check-prefix=MIPS32R1 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s --check-prefix=MIPS32R2 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s --check-prefix=MIPS32R2 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s --check-prefix=MIPS32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s --check-prefix=MIPS64R1 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s --check-prefix=MIPS64R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R2-ABS2K8 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s --check-prefix=MIPS64R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R6-ABS2K8 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s --check-prefix=MM -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008 | FileCheck %s --check-prefix=MM-ABS2K8 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008,+fp64 | FileCheck %s --check-prefix=MM-ABS2K8 -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips,+fp64 | FileCheck %s --check-prefix=MM -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s --check-prefix=MMR6 +; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s --check-prefix=MIPS32R1 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s --check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s --check-prefix=MIPS32R2 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s --check-prefix=MIPS32R6 +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s --check-prefix=MIPS64R1 +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s --check-prefix=MIPS64R2 +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R2-ABS2K8 +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R6-ABS2K8 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s --check-prefix=MM +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008 | FileCheck %s --check-prefix=MM-ABS2K8 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008,+fp64 | FileCheck %s --check-prefix=MM-ABS2K8 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips,+fp64 | FileCheck %s --check-prefix=MM +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s --check-prefix=MMR6 ; Test that the instruction selection for the case of `abs.s` and `abs.d` ; matches the expected behaviour. In the default case with NaNs and no "abs2008" diff --git a/llvm/test/CodeGen/Mips/llvm-ir/not.ll b/llvm/test/CodeGen/Mips/llvm-ir/not.ll index 03ba8e562ef0..58ed0e66d5e2 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/not.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/not.ll @@ -1,30 +1,30 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,GP64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32 define signext i1 @not_i1(i1 signext %a) { diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll index 7b3778437066..550ee0395ab7 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll @@ -7,23 +7,23 @@ ; affects it and it's undesirable to repeat the non-pointer returns for each ; relocation model. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -mtriple=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -mtriple=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C +; RUN: llc -mtriple=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -mtriple=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 ; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled ; as mthc1 has unmodeled side effects. This is an artifact of our backend. ; Force the delay slot filler off to check that the sequence jr $ra; nop is ; turned into jic 0, $ra. -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C define void @ret_void() { ; ALL-LABEL: ret_void: diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll index 8bf83c5c18ce..20a06139a02b 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,M2,M2-M3 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL,SEL-32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,M3,M2-M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=ALL,CMOV,CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64-elf -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,SEL,SEL-64 -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM32R3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32R6 define signext i1 @tst_select_i1_i1(i1 signext %s, diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll b/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll index 05776886dd94..f4b86257b5b7 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64 +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6 define float @sqrt_fn(float %value) #0 { entry: diff --git a/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll b/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll index 09713805c101..b9ffbff0c6bc 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ +; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,M64 -; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,M64 define void @store_i8(ptr %ptr, i8 signext %v) { diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll index 51dcccefc84d..b465e24d47a0 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll @@ -1,32 +1,32 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s \ ; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM,PRE4 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP32,NOT-MM -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP32,NOT-MM -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP32,NOT-MM -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP32,NOT-MM -; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefixes=MM32,MMR3 -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=MM32,MMR6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \ ; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \ ; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \ ; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll index 3c3110341df2..0b7e51cbf7dc 100644 --- a/llvm/test/CodeGen/Mips/load-store-left-right.ll +++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll @@ -1,18 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s -; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s -; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s -; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s -; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s -; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s -; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s %struct.SLL = type { i64 } %struct.SI = type { i32 } diff --git a/llvm/test/CodeGen/Mips/long-call-attr.ll b/llvm/test/CodeGen/Mips/long-call-attr.ll index beda290a9725..1c25a36cf123 100644 --- a/llvm/test/CodeGen/Mips/long-call-attr.ll +++ b/llvm/test/CodeGen/Mips/long-call-attr.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \ +; RUN: llc -mtriple=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \ ; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=O32 %s -; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \ +; RUN: llc -mtriple=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \ ; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=O32 %s -; RUN: llc -march=mips64 -target-abi n64 --mattr=+long-calls,+noabicalls < %s \ +; RUN: llc -mtriple=mips64 -target-abi n64 --mattr=+long-calls,+noabicalls < %s \ ; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=N64 %s -; RUN: llc -march=mips64 -target-abi n64 --mattr=-long-calls,+noabicalls < %s \ +; RUN: llc -mtriple=mips64 -target-abi n64 --mattr=-long-calls,+noabicalls < %s \ ; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=N64 %s declare void @far() #0 diff --git a/llvm/test/CodeGen/Mips/long-call-mcount.ll b/llvm/test/CodeGen/Mips/long-call-mcount.ll index 40d3b74ee579..2e90a47ad0f0 100644 --- a/llvm/test/CodeGen/Mips/long-call-mcount.ll +++ b/llvm/test/CodeGen/Mips/long-call-mcount.ll @@ -1,7 +1,7 @@ ; Check call to mcount in case of long/short call options. -; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \ +; RUN: llc -mtriple=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \ ; RUN: -mips-jalr-reloc=false | FileCheck -check-prefixes=CHECK,LONG %s -; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \ +; RUN: llc -mtriple=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \ ; RUN: -mips-jalr-reloc=false | FileCheck -check-prefixes=CHECK,SHORT %s define void @foo() { diff --git a/llvm/test/CodeGen/Mips/long-calls.ll b/llvm/test/CodeGen/Mips/long-calls.ll index 99fce03cd005..5ee1ee1ed575 100644 --- a/llvm/test/CodeGen/Mips/long-calls.ll +++ b/llvm/test/CodeGen/Mips/long-calls.ll @@ -1,19 +1,19 @@ -; RUN: llc -march=mips -mattr=-long-calls %s -o - \ +; RUN: llc -mtriple=mips -mattr=-long-calls %s -o - \ ; RUN: | FileCheck -check-prefix=OFF %s -; RUN: llc -march=mips -mattr=+long-calls,+noabicalls %s -o - \ +; RUN: llc -mtriple=mips -mattr=+long-calls,+noabicalls %s -o - \ ; RUN: | FileCheck -check-prefix=ON32 %s -; RUN: llc -march=mips -mattr=+long-calls,-noabicalls %s -o - \ +; RUN: llc -mtriple=mips -mattr=+long-calls,-noabicalls %s -o - \ ; RUN: | FileCheck -check-prefix=OFF %s -; RUN: llc -march=mips64 -target-abi n32 -mattr=-long-calls %s -o - \ +; RUN: llc -mtriple=mips64 -target-abi n32 -mattr=-long-calls %s -o - \ ; RUN: | FileCheck -check-prefix=OFF %s -; RUN: llc -march=mips64 -target-abi n32 -mattr=+long-calls,+noabicalls %s -o - \ +; RUN: llc -mtriple=mips64 -target-abi n32 -mattr=+long-calls,+noabicalls %s -o - \ ; RUN: | FileCheck -check-prefix=ON32 %s -; RUN: llc -march=mips64 -target-abi n64 -mattr=-long-calls %s -o - \ +; RUN: llc -mtriple=mips64 -target-abi n64 -mattr=-long-calls %s -o - \ ; RUN: | FileCheck -check-prefix=OFF %s -; RUN: llc -march=mips64 -target-abi n64 -mattr=+long-calls,+noabicalls %s -o - \ +; RUN: llc -mtriple=mips64 -target-abi n64 -mattr=+long-calls,+noabicalls %s -o - \ ; RUN: | FileCheck -check-prefix=ON64 %s declare void @callee() diff --git a/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll b/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll index 709cd477a778..3f6ac94801eb 100644 --- a/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll +++ b/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -mcpu=mips32r6 -force-mips-long-branch | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -force-mips-long-branch | FileCheck %s ; Check that when MIPS32R6 with the static relocation model with the usage of ; long branches, that there is a nop between any compact branch and the static diff --git a/llvm/test/CodeGen/Mips/machineverifier.ll b/llvm/test/CodeGen/Mips/machineverifier.ll index 39d2a7e4a936..73cb2c62ee05 100644 --- a/llvm/test/CodeGen/Mips/machineverifier.ll +++ b/llvm/test/CodeGen/Mips/machineverifier.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel -verify-machineinstrs +; RUN: llc < %s -mtriple=mipsel -verify-machineinstrs ; Make sure machine verifier understands the last instruction of a basic block ; is not the terminator instruction after delay slot filler pass is run. diff --git a/llvm/test/CodeGen/Mips/madd-msub.ll b/llvm/test/CodeGen/Mips/madd-msub.ll index 9f7145685ed3..6bb1ea48184f 100644 --- a/llvm/test/CodeGen/Mips/madd-msub.ll +++ b/llvm/test/CodeGen/Mips/madd-msub.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=32 -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=32 -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=32R6 -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP -; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=64 -; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=64 -; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=64R6 -; RUN: llc -march=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=16 +; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=32 +; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=32 +; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=32R6 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP +; RUN: llc -mtriple=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=64 +; RUN: llc -mtriple=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=64 +; RUN: llc -mtriple=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=64R6 +; RUN: llc -mtriple=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=16 define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone { ; 32-LABEL: madd1: diff --git a/llvm/test/CodeGen/Mips/mbrsize4a.ll b/llvm/test/CodeGen/Mips/mbrsize4a.ll index 7a08d169527d..b8d2e2db8098 100644 --- a/llvm/test/CodeGen/Mips/mbrsize4a.ll +++ b/llvm/test/CodeGen/Mips/mbrsize4a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=jal16 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=jal16 @j = global i32 10, align 4 @.str = private unnamed_addr constant [11 x i8] c"at bottom\0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/mcount.ll b/llvm/test/CodeGen/Mips/mcount.ll index 8a129536d976..41100e6cbeb6 100644 --- a/llvm/test/CodeGen/Mips/mcount.ll +++ b/llvm/test/CodeGen/Mips/mcount.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -verify-machineinstrs \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32 -; RUN: llc -march=mips -verify-machineinstrs -relocation-model=pic \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-PIC -; RUN: llc -march=mips64 -verify-machineinstrs \ +; RUN: llc -mtriple=mips64-elf -verify-machineinstrs \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS64 -; RUN: llc -march=mips64 -verify-machineinstrs -relocation-model=pic \ +; RUN: llc -mtriple=mips64-elf -verify-machineinstrs -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS64-PIC -; RUN: llc -march=mips -verify-machineinstrs -mattr=+micromips \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -mattr=+micromips \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM -; RUN: llc -march=mips -verify-machineinstrs -relocation-model=pic -mattr=+micromips \ +; RUN: llc -mtriple=mips-elf -verify-machineinstrs -relocation-model=pic -mattr=+micromips \ ; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM-PIC ; Test that checks ABI for _mcount calls. diff --git a/llvm/test/CodeGen/Mips/memcpy.ll b/llvm/test/CodeGen/Mips/memcpy.ll index 554452457166..009a2f99f5ce 100644 --- a/llvm/test/CodeGen/Mips/memcpy.ll +++ b/llvm/test/CodeGen/Mips/memcpy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s %struct.S1 = type { i32, [41 x i8] } diff --git a/llvm/test/CodeGen/Mips/micromips-addiu.ll b/llvm/test/CodeGen/Mips/micromips-addiu.ll index 5165994126a2..4129e6f6e0b4 100644 --- a/llvm/test/CodeGen/Mips/micromips-addiu.ll +++ b/llvm/test/CodeGen/Mips/micromips-addiu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @x = global i32 65504, align 4 diff --git a/llvm/test/CodeGen/Mips/micromips-addu16.ll b/llvm/test/CodeGen/Mips/micromips-addu16.ll index 04243fc899f8..75a0f2dd4147 100644 --- a/llvm/test/CodeGen/Mips/micromips-addu16.ll +++ b/llvm/test/CodeGen/Mips/micromips-addu16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s define i32 @main() { diff --git a/llvm/test/CodeGen/Mips/micromips-and16.ll b/llvm/test/CodeGen/Mips/micromips-and16.ll index 66cfb0807f9d..8a4da6824428 100644 --- a/llvm/test/CodeGen/Mips/micromips-and16.ll +++ b/llvm/test/CodeGen/Mips/micromips-and16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s define i32 @main() { diff --git a/llvm/test/CodeGen/Mips/micromips-andi.ll b/llvm/test/CodeGen/Mips/micromips-andi.ll index c84a99fbef41..8841e402f2b9 100644 --- a/llvm/test/CodeGen/Mips/micromips-andi.ll +++ b/llvm/test/CodeGen/Mips/micromips-andi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @x = global i32 65504, align 4 diff --git a/llvm/test/CodeGen/Mips/micromips-attr.ll b/llvm/test/CodeGen/Mips/micromips-attr.ll index 1ea9b136e1d4..8e70cc616e0b 100644 --- a/llvm/test/CodeGen/Mips/micromips-attr.ll +++ b/llvm/test/CodeGen/Mips/micromips-attr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=mips32 --mattr=-micromips < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32 --mattr=-micromips < %s | FileCheck %s define void @foo() #0 { entry: diff --git a/llvm/test/CodeGen/Mips/micromips-compact-branches.ll b/llvm/test/CodeGen/Mips/micromips-compact-branches.ll index 3b05e9e174f3..fb04f8f5ec6b 100644 --- a/llvm/test/CodeGen/Mips/micromips-compact-branches.ll +++ b/llvm/test/CodeGen/Mips/micromips-compact-branches.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm -O3 \ +; RUN: llc %s -mtriple=mipsel -mattr=micromips -filetype=asm -O3 \ ; RUN: -disable-mips-delay-filler -relocation-model=pic -o - | FileCheck %s define void @main() nounwind uwtable { diff --git a/llvm/test/CodeGen/Mips/micromips-compact-jump.ll b/llvm/test/CodeGen/Mips/micromips-compact-jump.ll index 70cff84e967f..a4c5e5fc492c 100644 --- a/llvm/test/CodeGen/Mips/micromips-compact-jump.ll +++ b/llvm/test/CodeGen/Mips/micromips-compact-jump.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -disable-mips-delay-filler -O3 < %s | FileCheck %s define i32 @foo(i32 signext %a) #0 { diff --git a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll index 95f557770a10..ae1a93e88488 100644 --- a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll +++ b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @g = external global i32 diff --git a/llvm/test/CodeGen/Mips/micromips-li.ll b/llvm/test/CodeGen/Mips/micromips-li.ll index bfac23c25ea5..ebe7e3c90ac3 100644 --- a/llvm/test/CodeGen/Mips/micromips-li.ll +++ b/llvm/test/CodeGen/Mips/micromips-li.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @x = external global i32 diff --git a/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll b/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll index 5215c3a51998..b41a4080e64e 100644 --- a/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll +++ b/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \ +; RUN: llc %s -mtriple=mipsel -mattr=micromips -filetype=asm \ ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s define i32 @sum(ptr %x, ptr %y) nounwind uwtable { diff --git a/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll b/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll index 29d46bed4226..4884d0a22a24 100644 --- a/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll +++ b/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \ +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \ ; RUN: -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MM32 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \ +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \ ; RUN: -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MM32 diff --git a/llvm/test/CodeGen/Mips/micromips-not16.ll b/llvm/test/CodeGen/Mips/micromips-not16.ll index 2def472fce40..ef1ff01f9b2c 100644 --- a/llvm/test/CodeGen/Mips/micromips-not16.ll +++ b/llvm/test/CodeGen/Mips/micromips-not16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s define i32 @main() { diff --git a/llvm/test/CodeGen/Mips/micromips-or16.ll b/llvm/test/CodeGen/Mips/micromips-or16.ll index ae2c53884ef7..d82d3f68fc38 100644 --- a/llvm/test/CodeGen/Mips/micromips-or16.ll +++ b/llvm/test/CodeGen/Mips/micromips-or16.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s -; RUN: llc -O0 -march=mips -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -O0 -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -asm-show-inst < %s | FileCheck %s ; Branch instruction added to enable FastISel::selectOperator diff --git a/llvm/test/CodeGen/Mips/micromips-shift.ll b/llvm/test/CodeGen/Mips/micromips-shift.ll index 11472b8ac99f..9d2a5ec075ed 100644 --- a/llvm/test/CodeGen/Mips/micromips-shift.ll +++ b/llvm/test/CodeGen/Mips/micromips-shift.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @a = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir index 216fec6a7f6e..cadb440cfdab 100644 --- a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir +++ b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips %s -o - \ +# RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips %s -o - \ # RUN: -start-after=block-placement | FileCheck %s # Test that the micromips jal instruction is correctly handled by the delay slot diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll index 8949b19f4ada..cedd76ebea00 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s define i32 @f1() { entry: diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll index 4cada64548f4..663fb078ecb8 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s define void @f1(ptr %p) { ; CHECK-LABEL: f1: diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll index 46a963e2373f..5d594e27c2fc 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s ; Function Attrs: nounwind define i32 @function1(ptr %f) { diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll index e953df62bf2a..3120b1a5b6d6 100644 --- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll +++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s ; Function Attrs: nounwind readnone define i1 @fun(i32 %a, i32 %b) { diff --git a/llvm/test/CodeGen/Mips/micromips-subu16.ll b/llvm/test/CodeGen/Mips/micromips-subu16.ll index 874f6dfbcbfa..972cca99ba1b 100644 --- a/llvm/test/CodeGen/Mips/micromips-subu16.ll +++ b/llvm/test/CodeGen/Mips/micromips-subu16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s define i32 @main() { diff --git a/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll b/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll index c11c817b4165..890e6d002db5 100644 --- a/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll +++ b/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \ +; RUN: llc %s -mtriple=mipsel -mattr=micromips -filetype=asm \ ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s ; Function Attrs: noinline nounwind diff --git a/llvm/test/CodeGen/Mips/micromips-xor16.ll b/llvm/test/CodeGen/Mips/micromips-xor16.ll index a09531bc706c..3bf6b8bfbb4c 100644 --- a/llvm/test/CodeGen/Mips/micromips-xor16.ll +++ b/llvm/test/CodeGen/Mips/micromips-xor16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s define i32 @main() { diff --git a/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll b/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll index 46cba348ceb7..80294b5cd958 100644 --- a/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll +++ b/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll @@ -1,6 +1,6 @@ ; Check that stubs generation for mips16 hard-float mode does not depend ; on the function 'use-soft-float' attribute's value. -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel \ +; RUN: llc -mtriple=mipsel-linux-gnu \ ; RUN: -mattr=mips16 -relocation-model=pic < %s | FileCheck %s define void @bar_sf() #1 { diff --git a/llvm/test/CodeGen/Mips/mips16-hf-attr.ll b/llvm/test/CodeGen/Mips/mips16-hf-attr.ll index dabe61842d5d..c8af7127b00e 100644 --- a/llvm/test/CodeGen/Mips/mips16-hf-attr.ll +++ b/llvm/test/CodeGen/Mips/mips16-hf-attr.ll @@ -1,6 +1,6 @@ ; Check that stubs generation for mips16 hard-float mode does not depend ; on the function 'use-soft-float' attribute's value. -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel \ +; RUN: llc -mtriple=mipsel-linux-gnu \ ; RUN: -mattr=mips16 -relocation-model=pic < %s | FileCheck %s define void @bar_hf() #0 { diff --git a/llvm/test/CodeGen/Mips/mips16_32_1.ll b/llvm/test/CodeGen/Mips/mips16_32_1.ll index bf95c06a4932..0d020221c5ef 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_1.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_1.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s +; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s define void @foo() #0 { entry: diff --git a/llvm/test/CodeGen/Mips/mips16_fpret.ll b/llvm/test/CodeGen/Mips/mips16_fpret.ll index 2f68a8b96039..19f90fdff134 100644 --- a/llvm/test/CodeGen/Mips/mips16_fpret.ll +++ b/llvm/test/CodeGen/Mips/mips16_fpret.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=2 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=3 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=4 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=1 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=2 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=3 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=4 @x = global float 0x41F487E980000000, align 4 diff --git a/llvm/test/CodeGen/Mips/mips16fpe.ll b/llvm/test/CodeGen/Mips/mips16fpe.ll index 310213b43b00..7c6fdd532414 100644 --- a/llvm/test/CodeGen/Mips/mips16fpe.ll +++ b/llvm/test/CodeGen/Mips/mips16fpe.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 \ +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=16hf @x = global float 5.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/mips3-spill-slot.ll b/llvm/test/CodeGen/Mips/mips3-spill-slot.ll index 4eabbeb867e3..d1cfce09e67e 100644 --- a/llvm/test/CodeGen/Mips/mips3-spill-slot.ll +++ b/llvm/test/CodeGen/Mips/mips3-spill-slot.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64 -mcpu=mips3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=mips64 -mcpu=mips3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK ; This testcase is from PR35859. ; Check that spill slot has the correct size for mips3 and n64 ABI. ; Previously, this test case would fail during register diff --git a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll index 8eac8d4683d1..4e8b58834553 100644 --- a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll +++ b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -; RUN: not llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r6 < %s | FileCheck %s +; RUN: not llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS32r6 is not compatible with the DSP ASE diff --git a/llvm/test/CodeGen/Mips/mips64-f128-call.ll b/llvm/test/CodeGen/Mips/mips64-f128-call.ll index 879dc902eeb3..58ea4c424fe2 100644 --- a/llvm/test/CodeGen/Mips/mips64-f128-call.ll +++ b/llvm/test/CodeGen/Mips/mips64-f128-call.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck %s @gld0 = external global fp128 @gld1 = external global fp128 diff --git a/llvm/test/CodeGen/Mips/mips64-libcall.ll b/llvm/test/CodeGen/Mips/mips64-libcall.ll index 7c0e5b2bbfdc..9de35a893f4c 100644 --- a/llvm/test/CodeGen/Mips/mips64-libcall.ll +++ b/llvm/test/CodeGen/Mips/mips64-libcall.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mips64el -mcpu=mips64r2 -O3 < %s |\ +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -O3 < %s |\ ; RUN: FileCheck %s -check-prefix=HARD -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+soft-float < %s |\ +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+soft-float < %s |\ ; RUN: FileCheck %s -check-prefix=SOFT ; Check that %add is not passed in an integer register. diff --git a/llvm/test/CodeGen/Mips/mips64-sret.ll b/llvm/test/CodeGen/Mips/mips64-sret.ll index 9f4bc9ddfcc5..4c05ec097b06 100644 --- a/llvm/test/CodeGen/Mips/mips64-sret.ll +++ b/llvm/test/CodeGen/Mips/mips64-sret.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s define void @foo(ptr noalias sret(i32) %agg.result) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/mips64directive.ll b/llvm/test/CodeGen/Mips/mips64directive.ll index 6d6674496f7d..1434be0b6bf6 100644 --- a/llvm/test/CodeGen/Mips/mips64directive.ll +++ b/llvm/test/CodeGen/Mips/mips64directive.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips4 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el-elf -mcpu=mips64 -target-abi=n64 | FileCheck %s @gl = global i64 1250999896321, align 8 diff --git a/llvm/test/CodeGen/Mips/mips64ext.ll b/llvm/test/CodeGen/Mips/mips64ext.ll index 9c1243b8f18c..0e863001973c 100644 --- a/llvm/test/CodeGen/Mips/mips64ext.ll +++ b/llvm/test/CodeGen/Mips/mips64ext.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s define i64 @zext64_32(i32 %a) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/mips64extins.ll b/llvm/test/CodeGen/Mips/mips64extins.ll index f160603c2507..862193809218 100644 --- a/llvm/test/CodeGen/Mips/mips64extins.ll +++ b/llvm/test/CodeGen/Mips/mips64extins.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s define i64 @dext(i64 %i) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/mips64fpimm0.ll b/llvm/test/CodeGen/Mips/mips64fpimm0.ll index 0296cb523f98..a8d7f432eba4 100644 --- a/llvm/test/CodeGen/Mips/mips64fpimm0.ll +++ b/llvm/test/CodeGen/Mips/mips64fpimm0.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s define double @foo1() nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/mips64fpldst.ll b/llvm/test/CodeGen/Mips/mips64fpldst.ll index 7811ed85f3ad..ad09f78b3184 100644 --- a/llvm/test/CodeGen/Mips/mips64fpldst.ll +++ b/llvm/test/CodeGen/Mips/mips64fpldst.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 @f0 = common global float 0.000000e+00, align 4 @d0 = common global double 0.000000e+00, align 8 diff --git a/llvm/test/CodeGen/Mips/mips64imm.ll b/llvm/test/CodeGen/Mips/mips64imm.ll index 993c7c77e35c..a78e1dce518a 100644 --- a/llvm/test/CodeGen/Mips/mips64imm.ll +++ b/llvm/test/CodeGen/Mips/mips64imm.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s define i32 @foo1() nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/mips64instrs.ll b/llvm/test/CodeGen/Mips/mips64instrs.ll index e8b630b004cb..2dc88dfffa25 100644 --- a/llvm/test/CodeGen/Mips/mips64instrs.ll +++ b/llvm/test/CodeGen/Mips/mips64instrs.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MIPS4,ACCMULDIV %s -; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s -; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,GPRMULDIV %s +; RUN: llc -mtriple=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MIPS4,ACCMULDIV %s +; RUN: llc -mtriple=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,GPRMULDIV %s @gll0 = common global i64 0, align 8 @gll1 = common global i64 0, align 8 diff --git a/llvm/test/CodeGen/Mips/mips64intldst.ll b/llvm/test/CodeGen/Mips/mips64intldst.ll index 89e13247da01..7df92dd8028e 100644 --- a/llvm/test/CodeGen/Mips/mips64intldst.ll +++ b/llvm/test/CodeGen/Mips/mips64intldst.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 @c = common global i8 0, align 4 @s = common global i16 0, align 4 diff --git a/llvm/test/CodeGen/Mips/mips64lea.ll b/llvm/test/CodeGen/Mips/mips64lea.ll index 69c079603516..83f423993053 100644 --- a/llvm/test/CodeGen/Mips/mips64lea.ll +++ b/llvm/test/CodeGen/Mips/mips64lea.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s define void @foo3() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/mips64muldiv.ll b/llvm/test/CodeGen/Mips/mips64muldiv.ll index d1292be504e6..89dd52426949 100644 --- a/llvm/test/CodeGen/Mips/mips64muldiv.ll +++ b/llvm/test/CodeGen/Mips/mips64muldiv.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,ACC -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,ACC -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC -; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,ACC +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,ACC +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR ; FileCheck prefixes: ; ALL - All targets diff --git a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll index 174f4ce1771a..6484173e7c33 100644 --- a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll +++ b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -; RUN: not llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s +; RUN: llc -mtriple=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s +; RUN: not llc -mtriple=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS64r6 is not compatible with the DSP ASE diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll index ca09d2f5b290..d5b85ea65ce3 100644 --- a/llvm/test/CodeGen/Mips/mips64shift.ll +++ b/llvm/test/CodeGen/Mips/mips64shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck %s define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/mips64signextendsesf.ll b/llvm/test/CodeGen/Mips/mips64signextendsesf.ll index 831469ab0624..6160cd1dcffe 100644 --- a/llvm/test/CodeGen/Mips/mips64signextendsesf.ll +++ b/llvm/test/CodeGen/Mips/mips64signextendsesf.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+soft-float -O2 < %s | FileCheck %s +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+soft-float -O2 < %s | FileCheck %s define void @foosf() #0 { entry: diff --git a/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll b/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll index 12c353d72c56..10cc70e34065 100644 --- a/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll +++ b/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+soft-float -O0 < %s | FileCheck %s +; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+soft-float -O0 < %s | FileCheck %s define double @foo() #0 { diff --git a/llvm/test/CodeGen/Mips/mipslopat.ll b/llvm/test/CodeGen/Mips/mipslopat.ll index c6143844a8d4..109bf5ebb265 100644 --- a/llvm/test/CodeGen/Mips/mipslopat.ll +++ b/llvm/test/CodeGen/Mips/mipslopat.ll @@ -1,5 +1,5 @@ ; This test does not check the machine code output. -; RUN: llc -march=mips < %s +; RUN: llc -mtriple=mips < %s @stat_vol_ptr_int = internal global ptr null, align 4 @stat_ptr_vol_int = internal global ptr null, align 4 diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir index 6002705965ca..453a0b1b5e27 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \ +# RUN: llc -mtriple=mips64 -target-abi n64 -start-before=finalize-isel \ # RUN: -stop-after=finalize-isel -relocation-model=pic -mattr=+xgot \ # RUN: -o /dev/null %s diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir index d9703c74fc5c..8a20b5354f7c 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips -start-before=finalize-isel \ +# RUN: llc -mtriple=mips -start-before=finalize-isel \ # RUN: -stop-after=finalize-isel -relocation-model=pic \ # RUN: -o /dev/null %s diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir index 803a2d701fae..5151cb1c8902 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \ +# RUN: llc -mtriple=mips64 -target-abi n64 -start-before=finalize-isel \ # RUN: -stop-after=finalize-isel -relocation-model=pic \ # RUN: -o /dev/null %s diff --git a/llvm/test/CodeGen/Mips/misha.ll b/llvm/test/CodeGen/Mips/misha.ll index b8e45c633aaa..40a738fc8a5a 100644 --- a/llvm/test/CodeGen/Mips/misha.ll +++ b/llvm/test/CodeGen/Mips/misha.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 define i32 @sumc(ptr nocapture %to, ptr nocapture %from, i32) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/2r.ll b/llvm/test/CodeGen/Mips/msa/2r.ll index b7ea3fc11c6e..f5cde12f4efc 100644 --- a/llvm/test/CodeGen/Mips/msa/2r.ll +++ b/llvm/test/CodeGen/Mips/msa/2r.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll index f369a9ebca38..23857db4b06b 100644 --- a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format and ; convert scalars to vectors. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf.ll b/llvm/test/CodeGen/Mips/msa/2rf.ll index 6cdf5b7b8b42..61593f4690d9 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_flog2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll index f8bdf866c5f8..7c8376746df4 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll @@ -1,8 +1,8 @@ ; Test the MSA floating point conversion intrinsics (e.g. float->double) that ; are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16 @llvm_mips_fexupl_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll index da83b7eb180b..2c7eb0f9ca10 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA integer to floating point conversion intrinsics that are encoded ; with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 @llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll index 2d773bfda17c..3f4a76657540 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point to floating point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll index eeac8d449571..ee06361f370f 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,8 +2,8 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll index 110da0677781..dfb1458842e2 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point to fixed-point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index 31646350b680..8f97d6b12e91 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -1,11 +1,11 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. -; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ +; RUN: not llc -mtriple=mips-elf -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck -check-prefix=FP32ERROR %s ; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). diff --git a/llvm/test/CodeGen/Mips/msa/3r-b.ll b/llvm/test/CodeGen/Mips/msa/3r-b.ll index f824a6527d72..fc1f0c1071e2 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-b.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-c.ll b/llvm/test/CodeGen/Mips/msa/3r-c.ll index 8af06b3f20bd..000ebf45c472 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-c.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-d.ll b/llvm/test/CodeGen/Mips/msa/3r-d.ll index b40d2661ee6a..e46cfb0bedfd 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-d.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-d.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'd' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-i.ll b/llvm/test/CodeGen/Mips/msa/3r-i.ll index c06d79a975bf..e9af30d8e73b 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-i.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-i.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'i' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-m.ll b/llvm/test/CodeGen/Mips/msa/3r-m.ll index 855ceb3dd889..7a318ceed832 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-m.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-p.ll b/llvm/test/CodeGen/Mips/msa/3r-p.ll index 063da01c29db..4b3862c8f12a 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-p.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-p.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'p' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll index 6c673c543bf2..b86a560a29ff 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-s.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 's' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-v.ll b/llvm/test/CodeGen/Mips/msa/3r-v.ll index 80828a07907c..dacbf036f93c 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-v.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-v.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'v' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_vshf_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r.ll b/llvm/test/CodeGen/Mips/msa/3r_4r.ll index abeaee682fb4..7e9de2152e0d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format and ; use the result as a third operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll index 4b286a0e93cb..a6e753ec0cf1 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll @@ -2,8 +2,8 @@ ; use the result as a third operand and results in wider elements than the ; operands had. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16 @llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_splat.ll b/llvm/test/CodeGen/Mips/msa/3r_splat.ll index e8d9d23fa9b4..6b353e6cdcd0 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_splat.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,9 +1,9 @@ ; Test the MSA splat intrinsics that are encoded with the 3R instruction ; format. -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s @llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf.ll b/llvm/test/CodeGen/Mips/msa/3rf.ll index 9bae9ba53045..eed5bd229256 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll index 6142ada9fef9..a53e3d58fa72 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll index f397644df391..41011024e09f 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand and perform fixed-point operations. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll index 70da349d0f13..58a890634eb4 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point conversion intrinsics that are encoded with the ; 3RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll index 4c1328b49be5..d628d5ab1bbb 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; take an integer as an operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll index 7e186beb3205..137230aa6a6f 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; produce an integer as a result. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_q.ll index 5e3358ccd063..cc1588ce7de5 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction ; format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic.ll b/llvm/test/CodeGen/Mips/msa/arithmetic.ll index 62fd35a69aba..a262ce183d74 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL define void @add_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; ALL-LABEL: add_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll index b2ce43171aeb..b97e0539fcf6 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @add_v4f32(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: add_v4f32: diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations.ll b/llvm/test/CodeGen/Mips/msa/basic_operations.ll index 1f6c430a932e..820259d7c7bc 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations.ll @@ -1,20 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=O32,O32-BE %s -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=O32,O32-LE %s -; RUN: llc -march=mips64 -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ ; RUN: -relocation-model=pic -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N32,N32-BE %s -; RUN: llc -march=mips64el -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: llc -mtriple=mips64el -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ ; RUN: -relocation-model=pic -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N32,N32-LE %s -; RUN: llc -march=mips64 -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N64,N64-BE %s -; RUN: llc -march=mips64el -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mips64el -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N64,N64-LE %s diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll index 83ac551c8dc9..a1b5215d3ea2 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,O32 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N64 %s @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0> diff --git a/llvm/test/CodeGen/Mips/msa/bit.ll b/llvm/test/CodeGen/Mips/msa/bit.ll index 1b2012cec5f5..ea3277422651 100644 --- a/llvm/test/CodeGen/Mips/msa/bit.ll +++ b/llvm/test/CodeGen/Mips/msa/bit.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the BIT instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/bitcast.ll b/llvm/test/CodeGen/Mips/msa/bitcast.ll index 11c5a5fb42c7..c34e89b196e8 100644 --- a/llvm/test/CodeGen/Mips/msa/bitcast.ll +++ b/llvm/test/CodeGen/Mips/msa/bitcast.ll @@ -1,7 +1,7 @@ ; Test the bitcast operation for big-endian and little-endian. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s define void @v16i8_to_v16i8(ptr %src, ptr %dst) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/bitwise.ll b/llvm/test/CodeGen/Mips/msa/bitwise.ll index c7790b71b963..def77c8c4726 100644 --- a/llvm/test/CodeGen/Mips/msa/bitwise.ll +++ b/llvm/test/CodeGen/Mips/msa/bitwise.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPS -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPSEL +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPS +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPSEL define void @and_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK-LABEL: and_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll b/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll index ab2c36eae67d..5bc8b27bf336 100644 --- a/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll +++ b/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 16 @llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/compare.ll b/llvm/test/CodeGen/Mips/msa/compare.ll index a3910bde8cd1..351f0f1f79a3 100644 --- a/llvm/test/CodeGen/Mips/msa/compare.ll +++ b/llvm/test/CodeGen/Mips/msa/compare.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ceq_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: ceq_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/compare_float.ll b/llvm/test/CodeGen/Mips/msa/compare_float.ll index cd4924eca44c..2656cb839768 100644 --- a/llvm/test/CodeGen/Mips/msa/compare_float.ll +++ b/llvm/test/CodeGen/Mips/msa/compare_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind diff --git a/llvm/test/CodeGen/Mips/msa/elm_copy.ll b/llvm/test/CodeGen/Mips/msa/elm_copy.ll index 6e0ee2da0920..27d2faa8e66f 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_copy.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_copy.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are element extraction operations. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll index 7d44620e2579..dd8afa61e3db 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll @@ -1,8 +1,8 @@ ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM ; instruction format). -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s define i32 @msa_ir_cfcmsa_test() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/elm_insv.ll b/llvm/test/CodeGen/Mips/msa/elm_insv.ll index 6c00483cf653..23acdc0b9bbf 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_insv.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_insv.ll @@ -1,13 +1,13 @@ ; Test the MSA element insertion intrinsics that are encoded with the ELM ; instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_move.ll b/llvm/test/CodeGen/Mips/msa/elm_move.ll index 4065fc753a55..ed368815838b 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_move.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_move.ll @@ -1,8 +1,8 @@ ; Test the MSA move intrinsics (which are encoded with the ELM instruction ; format). -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll index 548cdf394ac8..8195595c62d1 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are either shifts or slides. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sldi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir index 208946452866..dcc64f58c564 100644 --- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir +++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir @@ -1,4 +1,4 @@ -# RUN: llc %s -start-after=shrink-wrap -march=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null +# RUN: llc %s -start-after=shrink-wrap -mtriple=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null # Test that estimated size of the stack leads to the creation of an emergency # spill when MSA is in use. Previously, this test case would fail during diff --git a/llvm/test/CodeGen/Mips/msa/endian.ll b/llvm/test/CodeGen/Mips/msa/endian.ll index 63aa3f6e1872..c9e63403d6ee 100644 --- a/llvm/test/CodeGen/Mips/msa/endian.ll +++ b/llvm/test/CodeGen/Mips/msa/endian.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> diff --git a/llvm/test/CodeGen/Mips/msa/fexuprl.ll b/llvm/test/CodeGen/Mips/msa/fexuprl.ll index abd9d164d7c6..e25ae39e7e4e 100644 --- a/llvm/test/CodeGen/Mips/msa/fexuprl.ll +++ b/llvm/test/CodeGen/Mips/msa/fexuprl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -mattr=+fp64,+msa | FileCheck %s ; Test that fexup[rl].w don't crash LLVM during type legalization. diff --git a/llvm/test/CodeGen/Mips/msa/frameindex.ll b/llvm/test/CodeGen/Mips/msa/frameindex.ll index 1ee527bd88a4..f6d46b186683 100644 --- a/llvm/test/CodeGen/Mips/msa/frameindex.ll +++ b/llvm/test/CodeGen/Mips/msa/frameindex.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s define void @loadstore_v16i8_near() nounwind { ; CHECK: loadstore_v16i8_near: diff --git a/llvm/test/CodeGen/Mips/msa/i10.ll b/llvm/test/CodeGen/Mips/msa/i10.ll index e130d6df4b90..2698c91308f7 100644 --- a/llvm/test/CodeGen/Mips/msa/i10.ll +++ b/llvm/test/CodeGen/Mips/msa/i10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I10 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-a.ll b/llvm/test/CodeGen/Mips/msa/i5-a.ll index 7fd14da4b5f0..2e551a6a04c3 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-a.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-a.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-b.ll b/llvm/test/CodeGen/Mips/msa/i5-b.ll index 4a36bfe540d1..1aff85d3327b 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-b.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-b.ll @@ -2,8 +2,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-c.ll b/llvm/test/CodeGen/Mips/msa/i5-c.ll index 96f5e6286276..976dfcf9c270 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-c.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ceqi_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-m.ll b/llvm/test/CodeGen/Mips/msa/i5-m.ll index 74599185963a..c1729a7ba0de 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-m.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_maxi_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-s.ll b/llvm/test/CodeGen/Mips/msa/i5-s.ll index 0ba71fa9acd3..754c4c57d755 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-s.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-s.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 's' diff --git a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll index e55799cf1766..b54247ea0707 100644 --- a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll +++ b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format and ; are loads or stores. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i8.ll b/llvm/test/CodeGen/Mips/msa/i8.ll index 89f5725c1735..b286574079da 100644 --- a/llvm/test/CodeGen/Mips/msa/i8.ll +++ b/llvm/test/CodeGen/Mips/msa/i8.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I8 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll index bbb76f3b8b6b..f8bb5b36c44c 100644 --- a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll +++ b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 +; RUN: not --crash llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 ; RUN: FileCheck %s < %t1 ; Test that the immediate intrinsics with out of range values trigger an error. diff --git a/llvm/test/CodeGen/Mips/msa/immediates.ll b/llvm/test/CodeGen/Mips/msa/immediates.ll index 5808643aded1..ba1ae74f227b 100644 --- a/llvm/test/CodeGen/Mips/msa/immediates.ll +++ b/llvm/test/CodeGen/Mips/msa/immediates.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck %s -check-prefixes=MSA,MSA32 -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \ +; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \ ; RUN: | FileCheck %s -check-prefix=MSA64N32 -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \ +; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \ ; RUN: | FileCheck %s -check-prefixes=MSA,MSA64N64 ; Test that the immediate intrinsics don't crash LLVM. diff --git a/llvm/test/CodeGen/Mips/msa/inline-asm.ll b/llvm/test/CodeGen/Mips/msa/inline-asm.ll index f84b11e05387..a41f96047ba7 100644 --- a/llvm/test/CodeGen/Mips/msa/inline-asm.ll +++ b/llvm/test/CodeGen/Mips/msa/inline-asm.ll @@ -1,6 +1,6 @@ ; A basic inline assembly test -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @v4i32_r = global <4 x i32> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/ldr_str.ll b/llvm/test/CodeGen/Mips/msa/ldr_str.ll index 74f84aa9bbd7..ff766491834e 100644 --- a/llvm/test/CodeGen/Mips/msa/ldr_str.ll +++ b/llvm/test/CodeGen/Mips/msa/ldr_str.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL -; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB +; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB +; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 ; Test intrinsics for 4-byte and 8-byte MSA load and stores. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll index db2b52028a89..d658dbdce639 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; "Unexpected illegal type!" assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll index a220b9887f90..77fa9f471521 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; `Opc && "Cannot copy registers"' assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll index e27ca939d42d..d4b80c63aea8 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a "Cannot select ..." error. ; This was because undef's are ignored when checking if a vector constant is a diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll index 91f2ca3d8d50..cd20c98e2fe4 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a "Cannot select ..." error. ; This happened because the legalizer treated undef's in the <4 x float> diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll index d1d2f0db69dc..596dc2594c9b 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA after dereferencing a null this pointer. ; It should at least successfully build. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll index c3158801bee5..137e7cf4efa6 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; "Don't know how to expand this condition!" unreachable. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll index ace3f54b33a3..c8123e9a8c8e 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; "Type for zero vector elements is not legal" assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll index d88dfb6bd29a..cea8ac8f9fff 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed to select instructions for extract_vector_elt for ; v4f32 on MSA. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll index de3f5a27eb46..81d6830a19f1 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test is based on an llvm-stress generated test case with seed=449609655 diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll index 0185c8d3eb33..aad184962c44 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; `Num < NumOperands && "Invalid child # of SDNode!"' assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll index ae02778783e3..d3b65b5177e3 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed to select instructions for extract_vector_elt for ; v2f64 on MSA. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll index 16900fbf4838..8fc5de240650 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed to select code for a truncstore of a ; build_vector. diff --git a/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll b/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll index 3071a358d6dc..8deff611f66b 100644 --- a/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll +++ b/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s ; Test that the register allocator honours +nooddspreg and does not pick an odd ; single precision subregister of an MSA register. diff --git a/llvm/test/CodeGen/Mips/msa/nori.b.ll b/llvm/test/CodeGen/Mips/msa/nori.b.ll index ea0d2a958a29..3332dd34d2de 100644 --- a/llvm/test/CodeGen/Mips/msa/nori.b.ll +++ b/llvm/test/CodeGen/Mips/msa/nori.b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s ; Test that simply checks if it will finish when value 255 (-1) appears as ; immediate in 'nori.b' instruction. diff --git a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll index 64f976c97a35..313b51ee31f4 100644 --- a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll +++ b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -march=mipsel -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=mipsel-elf -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s ; Test that checks if spill for ldi can be avoided and instruction will be ; rematerialized. diff --git a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll index 1f8572751c1a..dbbd0fdfaf89 100644 --- a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll +++ b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ashr_v4i32(ptr %c) nounwind { ; CHECK-LABEL: ashr_v4i32: diff --git a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll index 9312a05f5696..79fb1b04da5f 100644 --- a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll +++ b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll @@ -1,13 +1,13 @@ ; Test whether the following functions, with vectors featuring negative or values larger than the element ; bit size have their results of operations generated correctly when placed into constant pools -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s @llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/shift_no_and.ll b/llvm/test/CodeGen/Mips/msa/shift_no_and.ll index d975f43e0c06..58d20458afc7 100644 --- a/llvm/test/CodeGen/Mips/msa/shift_no_and.ll +++ b/llvm/test/CodeGen/Mips/msa/shift_no_and.ll @@ -1,7 +1,7 @@ ; Test the absence of the andi.b / and.v instructions -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/shuffle.ll b/llvm/test/CodeGen/Mips/msa/shuffle.ll index 61b42f5df441..e93bb7cdd112 100644 --- a/llvm/test/CodeGen/Mips/msa/shuffle.ll +++ b/llvm/test/CodeGen/Mips/msa/shuffle.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @vshf_v16i8_0(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK-LABEL: vshf_v16i8_0: diff --git a/llvm/test/CodeGen/Mips/msa/special.ll b/llvm/test/CodeGen/Mips/msa/special.ll index 3e392110cccf..f70d9db34841 100644 --- a/llvm/test/CodeGen/Mips/msa/special.ll +++ b/llvm/test/CodeGen/Mips/msa/special.ll @@ -1,12 +1,12 @@ ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind { diff --git a/llvm/test/CodeGen/Mips/msa/spill.ll b/llvm/test/CodeGen/Mips/msa/spill.ll index 29f02920b10c..5b00f3cad12c 100644 --- a/llvm/test/CodeGen/Mips/msa/spill.ll +++ b/llvm/test/CodeGen/Mips/msa/spill.ll @@ -1,8 +1,8 @@ ; Test that the correct instruction is chosen for spill and reload by trying ; to have 33 live MSA registers simultaneously -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define i32 @test_i8(ptr %p0, ptr %q1) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/vec.ll b/llvm/test/CodeGen/Mips/msa/vec.ll index cc4eba6c95bf..21c550bc7542 100644 --- a/llvm/test/CodeGen/Mips/msa/vec.ll +++ b/llvm/test/CodeGen/Mips/msa/vec.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the VEC instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s @llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/vecs10.ll b/llvm/test/CodeGen/Mips/msa/vecs10.ll index ce61efc33f3a..9d720f5f318c 100644 --- a/llvm/test/CodeGen/Mips/msa/vecs10.ll +++ b/llvm/test/CodeGen/Mips/msa/vecs10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the VECS10 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/mul.ll b/llvm/test/CodeGen/Mips/mul.ll index 41ea550dbce7..f5efed6415dc 100644 --- a/llvm/test/CodeGen/Mips/mul.ll +++ b/llvm/test/CodeGen/Mips/mul.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 5, align 4 @jjjj = global i32 -6, align 4 diff --git a/llvm/test/CodeGen/Mips/mulll.ll b/llvm/test/CodeGen/Mips/mulll.ll index 08813809bd5f..c65c1bbd980c 100644 --- a/llvm/test/CodeGen/Mips/mulll.ll +++ b/llvm/test/CodeGen/Mips/mulll.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i64 5, align 8 @jjjj = global i64 -6, align 8 diff --git a/llvm/test/CodeGen/Mips/mulull.ll b/llvm/test/CodeGen/Mips/mulull.ll index 749adfa05572..129054776a03 100644 --- a/llvm/test/CodeGen/Mips/mulull.ll +++ b/llvm/test/CodeGen/Mips/mulull.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i64 5, align 8 @jjjj = global i64 6, align 8 diff --git a/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll b/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll index b3768b088747..b03418dff6cc 100644 --- a/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll +++ b/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -O3 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -O3 < %s | FileCheck %s ; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \ ; RUN: | FileCheck %s -check-prefix=CHECK-NACL diff --git a/llvm/test/CodeGen/Mips/neg1.ll b/llvm/test/CodeGen/Mips/neg1.ll index 7f35a9884a10..00d76be167bc 100644 --- a/llvm/test/CodeGen/Mips/neg1.ll +++ b/llvm/test/CodeGen/Mips/neg1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/nmadd.ll b/llvm/test/CodeGen/Mips/nmadd.ll index 0fb534fbe3c7..57774b184d8c 100644 --- a/llvm/test/CodeGen/Mips/nmadd.ll +++ b/llvm/test/CodeGen/Mips/nmadd.ll @@ -1,15 +1,15 @@ ; Check whether nmadd/nmsub instructions are properly generated -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -enable-no-nans-fp-math -asm-show-inst | FileCheck %s -check-prefixes=ALL,CHECK-NM,CHECK-MM -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 -; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM -; RUN: llc < %s -march=mips64el -mcpu=mips3 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM-64 -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM -; RUN: llc < %s -march=mipsel -mcpu=mips32r3 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=micromips -enable-no-nans-fp-math -asm-show-inst | FileCheck %s -check-prefixes=ALL,CHECK-NM,CHECK-MM +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 +; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64 +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM +; RUN: llc < %s -mtriple=mips64el -mcpu=mips3 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM-64 +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r3 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM define float @add1(float %f, float %g, float %h) local_unnamed_addr #0 { entry: diff --git a/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll b/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll index a71a645a4017..7c9f375cbb9a 100644 --- a/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll +++ b/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,-nooddspreg \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,-nooddspreg \ ; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,ODDSPREG -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg \ ; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,NOODDSPREG diff --git a/llvm/test/CodeGen/Mips/nomips16.ll b/llvm/test/CodeGen/Mips/nomips16.ll index d05f37e39bf4..62564f9f890d 100644 --- a/llvm/test/CodeGen/Mips/nomips16.ll +++ b/llvm/test/CodeGen/Mips/nomips16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s @x = global float 0.000000e+00, align 4 @.str = private unnamed_addr constant [20 x i8] c"in main: mips16 %f\0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/not1.ll b/llvm/test/CodeGen/Mips/not1.ll index 30b6f45a3b21..7893cb08f719 100644 --- a/llvm/test/CodeGen/Mips/not1.ll +++ b/llvm/test/CodeGen/Mips/not1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/llvm/test/CodeGen/Mips/null.ll b/llvm/test/CodeGen/Mips/null.ll index 67e346d959f9..9f7c6eace93a 100644 --- a/llvm/test/CodeGen/Mips/null.ll +++ b/llvm/test/CodeGen/Mips/null.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 < %s | FileCheck %s -check-prefix=16 define i32 @main() nounwind { diff --git a/llvm/test/CodeGen/Mips/o32_cc.ll b/llvm/test/CodeGen/Mips/o32_cc.ll index cef1290a75bd..fb6529ebe147 100644 --- a/llvm/test/CodeGen/Mips/o32_cc.ll +++ b/llvm/test/CodeGen/Mips/o32_cc.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=ALL %s -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,NO-MFHC1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s +; RUN: llc -mtriple=mipsel < %s | FileCheck -check-prefix=ALL %s +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,NO-MFHC1 %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s ; $f12, $f14 ; ALL-LABEL: testlowercall0: diff --git a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll index 750457eac5e9..f509f49a341a 100644 --- a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll +++ b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -pre-RA-sched=source < %s | FileCheck %s ; All test functions do the same thing - they return the first variable ; argument. diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll index 11e93736f5cf..e6c375a0d9c3 100644 --- a/llvm/test/CodeGen/Mips/octeon.ll +++ b/llvm/test/CodeGen/Mips/octeon.ll @@ -1,6 +1,6 @@ -; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON -; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 -; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 +; RUN: llc -O1 < %s -mtriple=mips64-elf -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC define i64 @addi64(i64 %a, i64 %b) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/octeon_popcnt.ll b/llvm/test/CodeGen/Mips/octeon_popcnt.ll index 13488ed59504..84fb0bdc5afc 100644 --- a/llvm/test/CodeGen/Mips/octeon_popcnt.ll +++ b/llvm/test/CodeGen/Mips/octeon_popcnt.ll @@ -1,5 +1,5 @@ -; RUN: llc -O1 -march=mips64 -mcpu=octeon < %s | FileCheck %s -check-prefix=OCTEON -; RUN: llc -O1 -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64 +; RUN: llc -O1 -mtriple=mips64 -mcpu=octeon < %s | FileCheck %s -check-prefix=OCTEON +; RUN: llc -O1 -mtriple=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64 define i8 @cnt8(i8 %x) nounwind readnone { %cnt = tail call i8 @llvm.ctpop.i8(i8 %x) diff --git a/llvm/test/CodeGen/Mips/optimize-fp-math.ll b/llvm/test/CodeGen/Mips/optimize-fp-math.ll index 7886f29f5cef..7124013714bb 100644 --- a/llvm/test/CodeGen/Mips/optimize-fp-math.ll +++ b/llvm/test/CodeGen/Mips/optimize-fp-math.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 ; 32-LABEL: test_sqrtf_float_: ; 32: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}} diff --git a/llvm/test/CodeGen/Mips/or1.ll b/llvm/test/CodeGen/Mips/or1.ll index 94e314491a7c..2657270bee94 100644 --- a/llvm/test/CodeGen/Mips/or1.ll +++ b/llvm/test/CodeGen/Mips/or1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll b/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll index 730e01d8f114..63a730c18616 100644 --- a/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll +++ b/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -regalloc=pbqp <%s > %t +; RUN: llc -mtriple=mips -regalloc=pbqp <%s > %t ; ModuleID = 'bugpoint-reduced-simplified.bc' ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Mips/powif64_16.ll b/llvm/test/CodeGen/Mips/powif64_16.ll index 465f71f3d6af..3443b6225a38 100644 --- a/llvm/test/CodeGen/Mips/powif64_16.ll +++ b/llvm/test/CodeGen/Mips/powif64_16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s declare float @llvm.powi.f32.i32(float %Val, i32 %power) declare double @llvm.powi.f64.i32(double %Val, i32 %power) diff --git a/llvm/test/CodeGen/Mips/pr33682.ll b/llvm/test/CodeGen/Mips/pr33682.ll index 93ef4f900db0..545b25c18fae 100644 --- a/llvm/test/CodeGen/Mips/pr33682.ll +++ b/llvm/test/CodeGen/Mips/pr33682.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,BE -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,LE +; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,BE +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,LE ; Verify visitTRUNCATE respects endianness when transforming trunc to insert_vector_elt. diff --git a/llvm/test/CodeGen/Mips/pr33978.ll b/llvm/test/CodeGen/Mips/pr33978.ll index 921fa543cfda..136de5edfd33 100644 --- a/llvm/test/CodeGen/Mips/pr33978.ll +++ b/llvm/test/CodeGen/Mips/pr33978.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=mips32r2 < %s -o /dev/null +; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s -o /dev/null ; Test that SelectionDAG does not crash during DAGCombine when two pointers ; to the stack match with differing bases and offsets when expanding memcpy. diff --git a/llvm/test/CodeGen/Mips/prevent-hoisting.ll b/llvm/test/CodeGen/Mips/prevent-hoisting.ll index e44b895689b4..3d659746ddb9 100644 --- a/llvm/test/CodeGen/Mips/prevent-hoisting.ll +++ b/llvm/test/CodeGen/Mips/prevent-hoisting.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -O3 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -O3 -relocation-model=pic < %s | FileCheck %s ; MIPS direct branches implicitly define register $at. This test makes sure that diff --git a/llvm/test/CodeGen/Mips/private.ll b/llvm/test/CodeGen/Mips/private.ll index e93c2d7fc5d9..be936ddde007 100644 --- a/llvm/test/CodeGen/Mips/private.ll +++ b/llvm/test/CodeGen/Mips/private.ll @@ -1,6 +1,6 @@ ; Test to make sure that the 'private' is used correctly. ; -; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips -relocation-model=pic < %s | FileCheck %s define private void @foo() { ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/Mips/ra-allocatable.ll b/llvm/test/CodeGen/Mips/ra-allocatable.ll index dcbf90393576..52ec4cf77ce4 100644 --- a/llvm/test/CodeGen/Mips/ra-allocatable.ll +++ b/llvm/test/CodeGen/Mips/ra-allocatable.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s +; RUN: llc < %s -mtriple=mipsel | FileCheck %s @a0 = external global i32 @b0 = external global ptr diff --git a/llvm/test/CodeGen/Mips/rem.ll b/llvm/test/CodeGen/Mips/rem.ll index 525ab633ca01..c7b4da98d63e 100644 --- a/llvm/test/CodeGen/Mips/rem.ll +++ b/llvm/test/CodeGen/Mips/rem.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 -4, align 4 diff --git a/llvm/test/CodeGen/Mips/remat-immed-load.ll b/llvm/test/CodeGen/Mips/remat-immed-load.ll index 3d37b43bbc63..ec32acb2b78f 100644 --- a/llvm/test/CodeGen/Mips/remat-immed-load.ll +++ b/llvm/test/CodeGen/Mips/remat-immed-load.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=64 define void @f0() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/remu.ll b/llvm/test/CodeGen/Mips/remu.ll index 3d5f5d7629d9..6008d2d06a64 100644 --- a/llvm/test/CodeGen/Mips/remu.ll +++ b/llvm/test/CodeGen/Mips/remu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 4, align 4 diff --git a/llvm/test/CodeGen/Mips/return-vector.ll b/llvm/test/CodeGen/Mips/return-vector.ll index c59695d18734..c4fe4467bdcc 100644 --- a/llvm/test/CodeGen/Mips/return-vector.ll +++ b/llvm/test/CodeGen/Mips/return-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s ; Check that function accesses vector return value from stack in cases when diff --git a/llvm/test/CodeGen/Mips/return_address.ll b/llvm/test/CodeGen/Mips/return_address.ll index 65b4ff5733f4..0d02c1b3a920 100644 --- a/llvm/test/CodeGen/Mips/return_address.ll +++ b/llvm/test/CodeGen/Mips/return_address.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -verify-machineinstrs < %s | FileCheck %s define ptr @f1() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/return_address_err.ll b/llvm/test/CodeGen/Mips/return_address_err.ll index bf2ab3c16488..9a8fe1d0545f 100644 --- a/llvm/test/CodeGen/Mips/return_address_err.ll +++ b/llvm/test/CodeGen/Mips/return_address_err.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=mips < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=mips < %s 2>&1 | FileCheck %s declare ptr @llvm.returnaddress(i32) nounwind readnone diff --git a/llvm/test/CodeGen/Mips/rotate.ll b/llvm/test/CodeGen/Mips/rotate.ll index 77936b7bef9b..6fe6639285ca 100644 --- a/llvm/test/CodeGen/Mips/rotate.ll +++ b/llvm/test/CodeGen/Mips/rotate.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16 -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \ +; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16 +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \ ; RUN: -check-prefix=MM32 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \ +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \ ; RUN: -check-prefix=MM32 ; CHECK: rotrv $2, $4 diff --git a/llvm/test/CodeGen/Mips/s2rem.ll b/llvm/test/CodeGen/Mips/s2rem.ll index 92bb5ce51f31..fdf06cedc774 100644 --- a/llvm/test/CodeGen/Mips/s2rem.ll +++ b/llvm/test/CodeGen/Mips/s2rem.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC @xi = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/sb1.ll b/llvm/test/CodeGen/Mips/sb1.ll index 8b79f39d2c70..daecafc8418e 100644 --- a/llvm/test/CodeGen/Mips/sb1.ll +++ b/llvm/test/CodeGen/Mips/sb1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 97, align 4 @c = common global i8 0, align 1 diff --git a/llvm/test/CodeGen/Mips/sel1c.ll b/llvm/test/CodeGen/Mips/sel1c.ll index b4cba37b78ec..071f988abac3 100644 --- a/llvm/test/CodeGen/Mips/sel1c.ll +++ b/llvm/test/CodeGen/Mips/sel1c.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/sel2c.ll b/llvm/test/CodeGen/Mips/sel2c.ll index 9cf8b20eecdd..0c3b9578e69f 100644 --- a/llvm/test/CodeGen/Mips/sel2c.ll +++ b/llvm/test/CodeGen/Mips/sel2c.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll index a81393b0b080..939d192ba28e 100644 --- a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll +++ b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll index e703e317a0fb..7524bf240867 100644 --- a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll +++ b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll index 132d5ed77020..792168e567db 100644 --- a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll +++ b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/llvm/test/CodeGen/Mips/selectcc.ll b/llvm/test/CodeGen/Mips/selectcc.ll index 1bec29e8bcd5..532fc006ccd4 100644 --- a/llvm/test/CodeGen/Mips/selectcc.ll +++ b/llvm/test/CodeGen/Mips/selectcc.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s -; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED -; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED +; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic < %s +; RUN: llc -mtriple=mipsel -mcpu=mips32 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic < %s +; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED @gf0 = external global float @gf1 = external global float diff --git a/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll b/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll index 9632eac84419..048a362ab132 100644 --- a/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll +++ b/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0 -; RUN: llc -march=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2 +; RUN: llc -mtriple=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0 +; RUN: llc -mtriple=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2 ; At -O0, DAGCombine won't try to merge these consecutive loads but it will at ; -O2. diff --git a/llvm/test/CodeGen/Mips/seleq.ll b/llvm/test/CodeGen/Mips/seleq.ll index ecbeb2b51e3d..579c9c140a6b 100644 --- a/llvm/test/CodeGen/Mips/seleq.ll +++ b/llvm/test/CodeGen/Mips/seleq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/seleqk.ll b/llvm/test/CodeGen/Mips/seleqk.ll index 911c6f1996b6..73a5967ae4aa 100644 --- a/llvm/test/CodeGen/Mips/seleqk.ll +++ b/llvm/test/CodeGen/Mips/seleqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selgek.ll b/llvm/test/CodeGen/Mips/selgek.ll index a909bb543538..a9de8b20dfe3 100644 --- a/llvm/test/CodeGen/Mips/selgek.ll +++ b/llvm/test/CodeGen/Mips/selgek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selgt.ll b/llvm/test/CodeGen/Mips/selgt.ll index 30d7f8ff3a69..47648490a5e3 100644 --- a/llvm/test/CodeGen/Mips/selgt.ll +++ b/llvm/test/CodeGen/Mips/selgt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selle.ll b/llvm/test/CodeGen/Mips/selle.ll index bccc3de56705..c7a321d4aa04 100644 --- a/llvm/test/CodeGen/Mips/selle.ll +++ b/llvm/test/CodeGen/Mips/selle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selltk.ll b/llvm/test/CodeGen/Mips/selltk.ll index b070c301b019..dccee12a5102 100644 --- a/llvm/test/CodeGen/Mips/selltk.ll +++ b/llvm/test/CodeGen/Mips/selltk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selne.ll b/llvm/test/CodeGen/Mips/selne.ll index 6fe9e4827987..ff4cd116441c 100644 --- a/llvm/test/CodeGen/Mips/selne.ll +++ b/llvm/test/CodeGen/Mips/selne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selnek.ll b/llvm/test/CodeGen/Mips/selnek.ll index f38ab246e60f..f21693aeff0c 100644 --- a/llvm/test/CodeGen/Mips/selnek.ll +++ b/llvm/test/CodeGen/Mips/selnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/selpat.ll b/llvm/test/CodeGen/Mips/selpat.ll index d765acbab33a..dafe40e76363 100644 --- a/llvm/test/CodeGen/Mips/selpat.ll +++ b/llvm/test/CodeGen/Mips/selpat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-elf -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll index 0e74db3c6786..26fd2845f081 100644 --- a/llvm/test/CodeGen/Mips/setcc-se.ll +++ b/llvm/test/CodeGen/Mips/setcc-se.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6 @g1 = external global i32 diff --git a/llvm/test/CodeGen/Mips/seteq.ll b/llvm/test/CodeGen/Mips/seteq.ll index 37fd1634f796..8bbde5de812c 100644 --- a/llvm/test/CodeGen/Mips/seteq.ll +++ b/llvm/test/CodeGen/Mips/seteq.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/seteqz.ll b/llvm/test/CodeGen/Mips/seteqz.ll index c71ed1d91f72..006752d6e28d 100644 --- a/llvm/test/CodeGen/Mips/seteqz.ll +++ b/llvm/test/CodeGen/Mips/seteqz.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 0, align 4 @j = global i32 99, align 4 diff --git a/llvm/test/CodeGen/Mips/setge.ll b/llvm/test/CodeGen/Mips/setge.ll index 6fb549e24b3f..e6021150ab7d 100644 --- a/llvm/test/CodeGen/Mips/setge.ll +++ b/llvm/test/CodeGen/Mips/setge.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setgek.ll b/llvm/test/CodeGen/Mips/setgek.ll index 661a3f160e32..066b65b8be32 100644 --- a/llvm/test/CodeGen/Mips/setgek.ll +++ b/llvm/test/CodeGen/Mips/setgek.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @k = global i32 10, align 4 @r1 = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/setle.ll b/llvm/test/CodeGen/Mips/setle.ll index 35453b8f5f6a..ecd779cc04b0 100644 --- a/llvm/test/CodeGen/Mips/setle.ll +++ b/llvm/test/CodeGen/Mips/setle.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setlt.ll b/llvm/test/CodeGen/Mips/setlt.ll index fcf9a25be72c..234d1bc2b3c2 100644 --- a/llvm/test/CodeGen/Mips/setlt.ll +++ b/llvm/test/CodeGen/Mips/setlt.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setltk.ll b/llvm/test/CodeGen/Mips/setltk.ll index 95aa9ea07d24..4be83bb49541 100644 --- a/llvm/test/CodeGen/Mips/setltk.ll +++ b/llvm/test/CodeGen/Mips/setltk.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setne.ll b/llvm/test/CodeGen/Mips/setne.ll index d9396b1bf775..5a37c88ea59b 100644 --- a/llvm/test/CodeGen/Mips/setne.ll +++ b/llvm/test/CodeGen/Mips/setne.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @i = global i32 1, align 4 @j = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setuge.ll b/llvm/test/CodeGen/Mips/setuge.ll index afdd4ef73375..121daf327246 100644 --- a/llvm/test/CodeGen/Mips/setuge.ll +++ b/llvm/test/CodeGen/Mips/setuge.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setugt.ll b/llvm/test/CodeGen/Mips/setugt.ll index afe4e4b09c78..2a08d80e0f42 100644 --- a/llvm/test/CodeGen/Mips/setugt.ll +++ b/llvm/test/CodeGen/Mips/setugt.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setule.ll b/llvm/test/CodeGen/Mips/setule.ll index 024e7701fad4..63ee5257ec9a 100644 --- a/llvm/test/CodeGen/Mips/setule.ll +++ b/llvm/test/CodeGen/Mips/setule.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setult.ll b/llvm/test/CodeGen/Mips/setult.ll index ef354ec0971e..0272dd300b15 100644 --- a/llvm/test/CodeGen/Mips/setult.ll +++ b/llvm/test/CodeGen/Mips/setult.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/setultk.ll b/llvm/test/CodeGen/Mips/setultk.ll index 9801d388d223..8f06fb324b5a 100644 --- a/llvm/test/CodeGen/Mips/setultk.ll +++ b/llvm/test/CodeGen/Mips/setultk.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/llvm/test/CodeGen/Mips/sh1.ll b/llvm/test/CodeGen/Mips/sh1.ll index 6bfa9f56231f..d3bdc15eedc3 100644 --- a/llvm/test/CodeGen/Mips/sh1.ll +++ b/llvm/test/CodeGen/Mips/sh1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 97, align 4 @s = common global i16 0, align 2 diff --git a/llvm/test/CodeGen/Mips/shift-parts.ll b/llvm/test/CodeGen/Mips/shift-parts.ll index 38cbf28108ca..c77ec0249ae1 100644 --- a/llvm/test/CodeGen/Mips/shift-parts.ll +++ b/llvm/test/CodeGen/Mips/shift-parts.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s define i64 @shl0(i64 %a, i32 %b) nounwind readnone { entry: diff --git a/llvm/test/CodeGen/Mips/simplebr.ll b/llvm/test/CodeGen/Mips/simplebr.ll index ba97bdd89c17..cfe547fe7ca2 100644 --- a/llvm/test/CodeGen/Mips/simplebr.ll +++ b/llvm/test/CodeGen/Mips/simplebr.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mips16-hard-float -mattr=+soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mips16-hard-float -mattr=+soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 ; ModuleID = 'simplebr.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll b/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll index 4d15f428e44b..b79d25dfe5ed 100644 --- a/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll +++ b/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64 @gint_ = external global i32 @gLL_ = external global i64 diff --git a/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll b/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll index 3e2de21b63ca..0f406f069547 100644 --- a/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll +++ b/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s @foo12.d4 = internal unnamed_addr global double 0.000000e+00, align 8 diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir index 45807b2e48b0..b87ee412038c 100644 --- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir +++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s +# RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s # Test that the 'sll $zero, $zero, 0' is correctly recognized as a real # instruction rather than some unimplemented opcode for the purposes of diff --git a/llvm/test/CodeGen/Mips/sll1.ll b/llvm/test/CodeGen/Mips/sll1.ll index bf36682100d9..79b8d4bf70b3 100644 --- a/llvm/test/CodeGen/Mips/sll1.ll +++ b/llvm/test/CodeGen/Mips/sll1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @j = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/sll2.ll b/llvm/test/CodeGen/Mips/sll2.ll index 5de0b561cc98..c3d763f0551f 100644 --- a/llvm/test/CodeGen/Mips/sll2.ll +++ b/llvm/test/CodeGen/Mips/sll2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @j = global i32 4, align 4 diff --git a/llvm/test/CodeGen/Mips/slt.ll b/llvm/test/CodeGen/Mips/slt.ll index a17f5ab0e57d..01dc1299f4f1 100644 --- a/llvm/test/CodeGen/Mips/slt.ll +++ b/llvm/test/CodeGen/Mips/slt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s define i32 @slt(i32 signext %a) nounwind readnone { %1 = icmp slt i32 %a, 7 diff --git a/llvm/test/CodeGen/Mips/small-section-reserve-gp.ll b/llvm/test/CodeGen/Mips/small-section-reserve-gp.ll index cbe1218c3421..4c1a76a79ae9 100644 --- a/llvm/test/CodeGen/Mips/small-section-reserve-gp.ll +++ b/llvm/test/CodeGen/Mips/small-section-reserve-gp.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-sde-elf -march=mipsel -relocation-model=static -mattr=+noabicalls -mgpopt < %s \ +; RUN: llc -mtriple=mipsel-sde-elf -relocation-model=static -mattr=+noabicalls -mgpopt < %s \ ; RUN: | FileCheck %s @i = internal unnamed_addr global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/spill-copy-acreg.ll b/llvm/test/CodeGen/Mips/spill-copy-acreg.ll index ea24bebe3e5f..71aab3832d0b 100644 --- a/llvm/test/CodeGen/Mips/spill-copy-acreg.ll +++ b/llvm/test/CodeGen/Mips/spill-copy-acreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=+dsp < %s +; RUN: llc -mtriple=mipsel -mattr=+dsp < %s @g1 = common global i64 0, align 8 @g2 = common global i64 0, align 8 diff --git a/llvm/test/CodeGen/Mips/sr1.ll b/llvm/test/CodeGen/Mips/sr1.ll index 47948c488aab..c6fa9fcc4fb0 100644 --- a/llvm/test/CodeGen/Mips/sr1.ll +++ b/llvm/test/CodeGen/Mips/sr1.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=NEG +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=NEG @f = common global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/sra1.ll b/llvm/test/CodeGen/Mips/sra1.ll index 08286760d5cd..ad8382f23871 100644 --- a/llvm/test/CodeGen/Mips/sra1.ll +++ b/llvm/test/CodeGen/Mips/sra1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 -354, align 4 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/sra2.ll b/llvm/test/CodeGen/Mips/sra2.ll index 2dd966b0ff84..50b00c935b9b 100644 --- a/llvm/test/CodeGen/Mips/sra2.ll +++ b/llvm/test/CodeGen/Mips/sra2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 -354, align 4 @j = global i32 3, align 4 diff --git a/llvm/test/CodeGen/Mips/srl1.ll b/llvm/test/CodeGen/Mips/srl1.ll index 21cdeda4af44..e9fb916758a7 100644 --- a/llvm/test/CodeGen/Mips/srl1.ll +++ b/llvm/test/CodeGen/Mips/srl1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10654, align 4 @j = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/srl2.ll b/llvm/test/CodeGen/Mips/srl2.ll index b433893822dc..17895ff85d08 100644 --- a/llvm/test/CodeGen/Mips/srl2.ll +++ b/llvm/test/CodeGen/Mips/srl2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10654, align 4 @j = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Mips/stack-alignment.ll b/llvm/test/CodeGen/Mips/stack-alignment.ll index 2ae917f50be1..22275a53f38e 100644 --- a/llvm/test/CodeGen/Mips/stack-alignment.ll +++ b/llvm/test/CodeGen/Mips/stack-alignment.ll @@ -1,12 +1,12 @@ ; RUN: split-file %s %t ; RUN: cat %t/main.ll %t/_32.ll > %t/32.ll -; RUN: llc -march=mipsel < %t/main.ll | FileCheck %s -check-prefix=32 -; RUN: llc -march=mipsel < %t/32.ll | FileCheck %s -check-prefix=A32-32 -; RUN: llc -march=mipsel -mattr=+fp64,+mips32r2 < %t/main.ll | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips3 < %t/main.ll | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips4 < %t/main.ll | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 < %t/main.ll | FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 < %t/32.ll | FileCheck %s -check-prefix=A32-64 +; RUN: llc -mtriple=mipsel < %t/main.ll | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mipsel < %t/32.ll | FileCheck %s -check-prefix=A32-32 +; RUN: llc -mtriple=mipsel -mattr=+fp64,+mips32r2 < %t/main.ll | FileCheck %s -check-prefix=32 +; RUN: llc -mtriple=mips64el -mcpu=mips3 < %t/main.ll | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mips64el -mcpu=mips4 < %t/main.ll | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %t/main.ll | FileCheck %s -check-prefix=64 +; RUN: llc -mtriple=mips64el -mcpu=mips64 < %t/32.ll | FileCheck %s -check-prefix=A32-64 ;--- main.ll ; 32: addiu $sp, $sp, -8 diff --git a/llvm/test/CodeGen/Mips/stackcoloring.ll b/llvm/test/CodeGen/Mips/stackcoloring.ll index aeedbc8abccd..12ccabd52e47 100644 --- a/llvm/test/CodeGen/Mips/stackcoloring.ll +++ b/llvm/test/CodeGen/Mips/stackcoloring.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s @g1 = external global ptr diff --git a/llvm/test/CodeGen/Mips/stchar.ll b/llvm/test/CodeGen/Mips/stchar.ll index 0a2dfbe1183a..f9bb1b0c2fb1 100644 --- a/llvm/test/CodeGen/Mips/stchar.ll +++ b/llvm/test/CodeGen/Mips/stchar.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_h -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_b +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_h +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_b @.str = private unnamed_addr constant [9 x i8] c"%hd %c \0A\00", align 1 @sp = common global ptr null, align 4 diff --git a/llvm/test/CodeGen/Mips/stldst.ll b/llvm/test/CodeGen/Mips/stldst.ll index 0208d62b4f8a..6f1ed4c78f3b 100644 --- a/llvm/test/CodeGen/Mips/stldst.ll +++ b/llvm/test/CodeGen/Mips/stldst.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @kkkk = global i32 67, align 4 @llll = global i32 33, align 4 diff --git a/llvm/test/CodeGen/Mips/sub1.ll b/llvm/test/CodeGen/Mips/sub1.ll index 8e30a1732ce4..8f1e941b99d5 100644 --- a/llvm/test/CodeGen/Mips/sub1.ll +++ b/llvm/test/CodeGen/Mips/sub1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 diff --git a/llvm/test/CodeGen/Mips/sub2.ll b/llvm/test/CodeGen/Mips/sub2.ll index 5d6296d279e4..c2a404dbc5c3 100644 --- a/llvm/test/CodeGen/Mips/sub2.ll +++ b/llvm/test/CodeGen/Mips/sub2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @j = global i32 20, align 4 diff --git a/llvm/test/CodeGen/Mips/swzero.ll b/llvm/test/CodeGen/Mips/swzero.ll index cc17a1559db9..6059839e2de1 100644 --- a/llvm/test/CodeGen/Mips/swzero.ll +++ b/llvm/test/CodeGen/Mips/swzero.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s %struct.unaligned = type <{ i32 }> diff --git a/llvm/test/CodeGen/Mips/tail16.ll b/llvm/test/CodeGen/Mips/tail16.ll index 831de34f8d89..779ef6b4a11f 100644 --- a/llvm/test/CodeGen/Mips/tail16.ll +++ b/llvm/test/CodeGen/Mips/tail16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s ; Function Attrs: nounwind optsize define float @h() { diff --git a/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll b/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll index dda24a2ca163..c7ad22cf427b 100644 --- a/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll +++ b/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32 -O0 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \ +; RUN: llc -mtriple=mips -mcpu=mips32 -O0 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \ ; RUN: %s -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -mtriple=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64 -; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n32 \ +; RUN: llc -mtriple=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n32 \ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64 diff --git a/llvm/test/CodeGen/Mips/thread-pointer.ll b/llvm/test/CodeGen/Mips/thread-pointer.ll index b460d6dd0a18..30d3c9385b98 100644 --- a/llvm/test/CodeGen/Mips/thread-pointer.ll +++ b/llvm/test/CodeGen/Mips/thread-pointer.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s | FileCheck %s -; RUN: llc -march=mips64 < %s | FileCheck %s -; RUN: llc -march=mipsel < %s | FileCheck %s -; RUN: llc -march=mips64el < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips64 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel < %s | FileCheck %s +; RUN: llc -mtriple=mips64el < %s | FileCheck %s declare ptr @llvm.thread.pointer() nounwind readnone diff --git a/llvm/test/CodeGen/Mips/tls-alias.ll b/llvm/test/CodeGen/Mips/tls-alias.ll index 184283088077..a2ba2250995f 100644 --- a/llvm/test/CodeGen/Mips/tls-alias.ll +++ b/llvm/test/CodeGen/Mips/tls-alias.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -disable-mips-delay-filler < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -relocation-model=pic -disable-mips-delay-filler < %s | FileCheck %s @foo = thread_local global i32 42 @bar = hidden thread_local alias i32, ptr @foo diff --git a/llvm/test/CodeGen/Mips/tnaked.ll b/llvm/test/CodeGen/Mips/tnaked.ll index 803fef965bb1..ac54f2faae3f 100644 --- a/llvm/test/CodeGen/Mips/tnaked.ll +++ b/llvm/test/CodeGen/Mips/tnaked.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=mipsel < %s -verify-machineinstrs | FileCheck %s define void @tnaked() #0 { diff --git a/llvm/test/CodeGen/Mips/trap.ll b/llvm/test/CodeGen/Mips/trap.ll index beb4b894632b..e824d01d5f7c 100644 --- a/llvm/test/CodeGen/Mips/trap.ll +++ b/llvm/test/CodeGen/Mips/trap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s declare void @llvm.trap() diff --git a/llvm/test/CodeGen/Mips/trap1.ll b/llvm/test/CodeGen/Mips/trap1.ll index 575574a0a3b1..c0c614631509 100644 --- a/llvm/test/CodeGen/Mips/trap1.ll +++ b/llvm/test/CodeGen/Mips/trap1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic declare void @llvm.trap() diff --git a/llvm/test/CodeGen/Mips/uitofp.ll b/llvm/test/CodeGen/Mips/uitofp.ll index 08cd692deb3c..1682a627155a 100644 --- a/llvm/test/CodeGen/Mips/uitofp.ll +++ b/llvm/test/CodeGen/Mips/uitofp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+single-float < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+single-float < %s | FileCheck %s define void @f0() nounwind { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Mips/ul1.ll b/llvm/test/CodeGen/Mips/ul1.ll index 5e3fc20dd39f..f21050aec11f 100644 --- a/llvm/test/CodeGen/Mips/ul1.ll +++ b/llvm/test/CodeGen/Mips/ul1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 %struct.ua = type <{ i16, i32 }> @foo = common global %struct.ua zeroinitializer, align 1 diff --git a/llvm/test/CodeGen/Mips/unaligned-memops.ll b/llvm/test/CodeGen/Mips/unaligned-memops.ll index 58475a216d6c..caaa212a40cd 100644 --- a/llvm/test/CodeGen/Mips/unaligned-memops.ll +++ b/llvm/test/CodeGen/Mips/unaligned-memops.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS +; RUN: llc -mtriple=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS ; Test that the correct ISA version of the unaligned memory operations is ; selected up front. diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll index da57b92e8f6d..912998ab9d03 100644 --- a/llvm/test/CodeGen/Mips/unalignedload.ll +++ b/llvm/test/CodeGen/Mips/unalignedload.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL -; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB +; RUN: llc < %s -mtriple=mipsel-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL +; RUN: llc < %s -mtriple=mips-elf -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB %struct.S2 = type { %struct.S1, %struct.S1 } %struct.S1 = type { i8, i8 } diff --git a/llvm/test/CodeGen/Mips/vector-load-store.ll b/llvm/test/CodeGen/Mips/vector-load-store.ll index 142f383b72c7..daa402291216 100644 --- a/llvm/test/CodeGen/Mips/vector-load-store.ll +++ b/llvm/test/CodeGen/Mips/vector-load-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+dsp < %s | FileCheck %s @g1 = common global <2 x i16> zeroinitializer, align 4 @g0 = common global <2 x i16> zeroinitializer, align 4 diff --git a/llvm/test/CodeGen/Mips/vector-setcc.ll b/llvm/test/CodeGen/Mips/vector-setcc.ll index f8e6d5e67520..57787c937a04 100644 --- a/llvm/test/CodeGen/Mips/vector-setcc.ll +++ b/llvm/test/CodeGen/Mips/vector-setcc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s +; RUN: llc -mtriple=mipsel < %s @a = common global <4 x i32> zeroinitializer, align 16 @b = common global <4 x i32> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll b/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll index c3f15fb6afa6..e86097633b7f 100644 --- a/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll +++ b/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s ; Function Attrs: nounwind define dso_local void @fun_s(float %a) local_unnamed_addr #0 { diff --git a/llvm/test/CodeGen/Mips/vr4300-mulmul.ll b/llvm/test/CodeGen/Mips/vr4300-mulmul.ll index 33d909c7b436..823b7d0a2abf 100644 --- a/llvm/test/CodeGen/Mips/vr4300-mulmul.ll +++ b/llvm/test/CodeGen/Mips/vr4300-mulmul.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s ; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn define dso_local float @fun_s(float %x) local_unnamed_addr !dbg !7 { diff --git a/llvm/test/CodeGen/Mips/weak.ll b/llvm/test/CodeGen/Mips/weak.ll index fdc0a1d88541..021cc6b9d726 100644 --- a/llvm/test/CodeGen/Mips/weak.ll +++ b/llvm/test/CodeGen/Mips/weak.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -mtriple=mips < %s | FileCheck %s @t = common global ptr null, align 4 diff --git a/llvm/test/CodeGen/Mips/whitespace.ll b/llvm/test/CodeGen/Mips/whitespace.ll index 6710b73acbf1..51dd13231fd0 100644 --- a/llvm/test/CodeGen/Mips/whitespace.ll +++ b/llvm/test/CodeGen/Mips/whitespace.ll @@ -1,6 +1,6 @@ ; Test that the instructions have the correct whitespace. -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck -strict-whitespace %s -check-prefix=16 -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -strict-whitespace -check-prefix=32R2 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck -strict-whitespace %s -check-prefix=16 +; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -strict-whitespace -check-prefix=32R2 @main.L = internal unnamed_addr constant [5 x ptr] [ptr blockaddress(@main, %L1), ptr blockaddress(@main, %L2), ptr blockaddress(@main, %L3), ptr blockaddress(@main, %L4), ptr null], align 4 @str = private unnamed_addr constant [2 x i8] c"A\00" diff --git a/llvm/test/CodeGen/Mips/xor1.ll b/llvm/test/CodeGen/Mips/xor1.ll index dcdfbf538ffd..3dca266bf93d 100644 --- a/llvm/test/CodeGen/Mips/xor1.ll +++ b/llvm/test/CodeGen/Mips/xor1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/llvm/test/CodeGen/Mips/zeroreg.ll b/llvm/test/CodeGen/Mips/zeroreg.ll index f2abdb61503c..91705489b731 100644 --- a/llvm/test/CodeGen/Mips/zeroreg.ll +++ b/llvm/test/CodeGen/Mips/zeroreg.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 -; RUN: llc < %s -march=mipsel -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64r2 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 +; RUN: llc < %s -mtriple=mipsel -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -mtriple=mipsel -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -mtriple=mipsel -mcpu=mips64r2 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -mtriple=mipsel -mcpu=mips64r6 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 @g1 = external global i32 |