diff options
Diffstat (limited to 'llvm/test/CodeGen/Mips/msa')
81 files changed, 201 insertions, 201 deletions
diff --git a/llvm/test/CodeGen/Mips/msa/2r.ll b/llvm/test/CodeGen/Mips/msa/2r.ll index b7ea3fc11c6e..f5cde12f4efc 100644 --- a/llvm/test/CodeGen/Mips/msa/2r.ll +++ b/llvm/test/CodeGen/Mips/msa/2r.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll index f369a9ebca38..23857db4b06b 100644 --- a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format and ; convert scalars to vectors. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf.ll b/llvm/test/CodeGen/Mips/msa/2rf.ll index 6cdf5b7b8b42..61593f4690d9 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_flog2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll index f8bdf866c5f8..7c8376746df4 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll @@ -1,8 +1,8 @@ ; Test the MSA floating point conversion intrinsics (e.g. float->double) that ; are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16 @llvm_mips_fexupl_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll index da83b7eb180b..2c7eb0f9ca10 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA integer to floating point conversion intrinsics that are encoded ; with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 @llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll index 2d773bfda17c..3f4a76657540 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point to floating point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll index eeac8d449571..ee06361f370f 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,8 +2,8 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll index 110da0677781..dfb1458842e2 100644 --- a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll +++ b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point to fixed-point conversion intrinsics that are ; encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index 31646350b680..8f97d6b12e91 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -1,11 +1,11 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. -; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ +; RUN: not llc -mtriple=mips-elf -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck -check-prefix=FP32ERROR %s ; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). diff --git a/llvm/test/CodeGen/Mips/msa/3r-b.ll b/llvm/test/CodeGen/Mips/msa/3r-b.ll index f824a6527d72..fc1f0c1071e2 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-b.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-c.ll b/llvm/test/CodeGen/Mips/msa/3r-c.ll index 8af06b3f20bd..000ebf45c472 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-c.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-d.ll b/llvm/test/CodeGen/Mips/msa/3r-d.ll index b40d2661ee6a..e46cfb0bedfd 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-d.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-d.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'd' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-i.ll b/llvm/test/CodeGen/Mips/msa/3r-i.ll index c06d79a975bf..e9af30d8e73b 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-i.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-i.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'i' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-m.ll b/llvm/test/CodeGen/Mips/msa/3r-m.ll index 855ceb3dd889..7a318ceed832 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-m.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-p.ll b/llvm/test/CodeGen/Mips/msa/3r-p.ll index 063da01c29db..4b3862c8f12a 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-p.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-p.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'p' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll index 6c673c543bf2..b86a560a29ff 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-s.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 's' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r-v.ll b/llvm/test/CodeGen/Mips/msa/3r-v.ll index 80828a07907c..dacbf036f93c 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-v.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-v.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'v' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_vshf_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r.ll b/llvm/test/CodeGen/Mips/msa/3r_4r.ll index abeaee682fb4..7e9de2152e0d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format and ; use the result as a third operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll index 4b286a0e93cb..a6e753ec0cf1 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll @@ -2,8 +2,8 @@ ; use the result as a third operand and results in wider elements than the ; operands had. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16 @llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3r_splat.ll b/llvm/test/CodeGen/Mips/msa/3r_splat.ll index e8d9d23fa9b4..6b353e6cdcd0 100644 --- a/llvm/test/CodeGen/Mips/msa/3r_splat.ll +++ b/llvm/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,9 +1,9 @@ ; Test the MSA splat intrinsics that are encoded with the 3R instruction ; format. -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s @llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf.ll b/llvm/test/CodeGen/Mips/msa/3rf.ll index 9bae9ba53045..eed5bd229256 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll index 6142ada9fef9..a53e3d58fa72 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll index f397644df391..41011024e09f 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; use the result as a third operand and perform fixed-point operations. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll index 70da349d0f13..58a890634eb4 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll @@ -1,8 +1,8 @@ ; Test the MSA floating-point conversion intrinsics that are encoded with the ; 3RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll index 4c1328b49be5..d628d5ab1bbb 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; take an integer as an operand. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll index 7e186beb3205..137230aa6a6f 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3RF instruction format and ; produce an integer as a result. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/3rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_q.ll index 5e3358ccd063..cc1588ce7de5 100644 --- a/llvm/test/CodeGen/Mips/msa/3rf_q.ll +++ b/llvm/test/CodeGen/Mips/msa/3rf_q.ll @@ -1,8 +1,8 @@ ; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction ; format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 @llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic.ll b/llvm/test/CodeGen/Mips/msa/arithmetic.ll index 62fd35a69aba..a262ce183d74 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL define void @add_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; ALL-LABEL: add_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll index b2ce43171aeb..b97e0539fcf6 100644 --- a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @add_v4f32(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: add_v4f32: diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations.ll b/llvm/test/CodeGen/Mips/msa/basic_operations.ll index 1f6c430a932e..820259d7c7bc 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations.ll @@ -1,20 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=O32,O32-BE %s -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=O32,O32-LE %s -; RUN: llc -march=mips64 -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ ; RUN: -relocation-model=pic -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N32,N32-BE %s -; RUN: llc -march=mips64el -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: llc -mtriple=mips64el -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \ ; RUN: -relocation-model=pic -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N32,N32-LE %s -; RUN: llc -march=mips64 -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N64,N64-BE %s -; RUN: llc -march=mips64el -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: llc -mtriple=mips64el -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \ ; RUN: -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=N64,N64-LE %s diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll index 83ac551c8dc9..a1b5215d3ea2 100644 --- a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,O32 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N64 %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,N64 %s @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0> diff --git a/llvm/test/CodeGen/Mips/msa/bit.ll b/llvm/test/CodeGen/Mips/msa/bit.ll index 1b2012cec5f5..ea3277422651 100644 --- a/llvm/test/CodeGen/Mips/msa/bit.ll +++ b/llvm/test/CodeGen/Mips/msa/bit.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the BIT instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/bitcast.ll b/llvm/test/CodeGen/Mips/msa/bitcast.ll index 11c5a5fb42c7..c34e89b196e8 100644 --- a/llvm/test/CodeGen/Mips/msa/bitcast.ll +++ b/llvm/test/CodeGen/Mips/msa/bitcast.ll @@ -1,7 +1,7 @@ ; Test the bitcast operation for big-endian and little-endian. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s define void @v16i8_to_v16i8(ptr %src, ptr %dst) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/bitwise.ll b/llvm/test/CodeGen/Mips/msa/bitwise.ll index c7790b71b963..def77c8c4726 100644 --- a/llvm/test/CodeGen/Mips/msa/bitwise.ll +++ b/llvm/test/CodeGen/Mips/msa/bitwise.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPS -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPSEL +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPS +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPSEL define void @and_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK-LABEL: and_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll b/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll index ab2c36eae67d..5bc8b27bf336 100644 --- a/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll +++ b/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 16 @llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/compare.ll b/llvm/test/CodeGen/Mips/msa/compare.ll index a3910bde8cd1..351f0f1f79a3 100644 --- a/llvm/test/CodeGen/Mips/msa/compare.ll +++ b/llvm/test/CodeGen/Mips/msa/compare.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ceq_v16i8(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK: ceq_v16i8: diff --git a/llvm/test/CodeGen/Mips/msa/compare_float.ll b/llvm/test/CodeGen/Mips/msa/compare_float.ll index cd4924eca44c..2656cb839768 100644 --- a/llvm/test/CodeGen/Mips/msa/compare_float.ll +++ b/llvm/test/CodeGen/Mips/msa/compare_float.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind diff --git a/llvm/test/CodeGen/Mips/msa/elm_copy.ll b/llvm/test/CodeGen/Mips/msa/elm_copy.ll index 6e0ee2da0920..27d2faa8e66f 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_copy.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_copy.ll @@ -1,13 +1,13 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are element extraction operations. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll index 7d44620e2579..dd8afa61e3db 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll @@ -1,8 +1,8 @@ ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM ; instruction format). -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s define i32 @msa_ir_cfcmsa_test() nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/elm_insv.ll b/llvm/test/CodeGen/Mips/msa/elm_insv.ll index 6c00483cf653..23acdc0b9bbf 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_insv.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_insv.ll @@ -1,13 +1,13 @@ ; Test the MSA element insertion intrinsics that are encoded with the ELM ; instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: llc -mtriple=mips64el-elf -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_move.ll b/llvm/test/CodeGen/Mips/msa/elm_move.ll index 4065fc753a55..ed368815838b 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_move.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_move.ll @@ -1,8 +1,8 @@ ; Test the MSA move intrinsics (which are encoded with the ELM instruction ; format). -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll index 548cdf394ac8..8195595c62d1 100644 --- a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll +++ b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are either shifts or slides. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sldi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir index 208946452866..dcc64f58c564 100644 --- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir +++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir @@ -1,4 +1,4 @@ -# RUN: llc %s -start-after=shrink-wrap -march=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null +# RUN: llc %s -start-after=shrink-wrap -mtriple=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null # Test that estimated size of the stack leads to the creation of an emergency # spill when MSA is in use. Previously, this test case would fail during diff --git a/llvm/test/CodeGen/Mips/msa/endian.ll b/llvm/test/CodeGen/Mips/msa/endian.ll index 63aa3f6e1872..c9e63403d6ee 100644 --- a/llvm/test/CodeGen/Mips/msa/endian.ll +++ b/llvm/test/CodeGen/Mips/msa/endian.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> diff --git a/llvm/test/CodeGen/Mips/msa/fexuprl.ll b/llvm/test/CodeGen/Mips/msa/fexuprl.ll index abd9d164d7c6..e25ae39e7e4e 100644 --- a/llvm/test/CodeGen/Mips/msa/fexuprl.ll +++ b/llvm/test/CodeGen/Mips/msa/fexuprl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa | FileCheck %s +; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -mattr=+fp64,+msa | FileCheck %s ; Test that fexup[rl].w don't crash LLVM during type legalization. diff --git a/llvm/test/CodeGen/Mips/msa/frameindex.ll b/llvm/test/CodeGen/Mips/msa/frameindex.ll index 1ee527bd88a4..f6d46b186683 100644 --- a/llvm/test/CodeGen/Mips/msa/frameindex.ll +++ b/llvm/test/CodeGen/Mips/msa/frameindex.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s define void @loadstore_v16i8_near() nounwind { ; CHECK: loadstore_v16i8_near: diff --git a/llvm/test/CodeGen/Mips/msa/i10.ll b/llvm/test/CodeGen/Mips/msa/i10.ll index e130d6df4b90..2698c91308f7 100644 --- a/llvm/test/CodeGen/Mips/msa/i10.ll +++ b/llvm/test/CodeGen/Mips/msa/i10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I10 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-a.ll b/llvm/test/CodeGen/Mips/msa/i5-a.ll index 7fd14da4b5f0..2e551a6a04c3 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-a.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-a.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-b.ll b/llvm/test/CodeGen/Mips/msa/i5-b.ll index 4a36bfe540d1..1aff85d3327b 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-b.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-b.ll @@ -2,8 +2,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-c.ll b/llvm/test/CodeGen/Mips/msa/i5-c.ll index 96f5e6286276..976dfcf9c270 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-c.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-c.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'c' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ceqi_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-m.ll b/llvm/test/CodeGen/Mips/msa/i5-m.ll index 74599185963a..c1729a7ba0de 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-m.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-m.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'm' -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_maxi_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i5-s.ll b/llvm/test/CodeGen/Mips/msa/i5-s.ll index 0ba71fa9acd3..754c4c57d755 100644 --- a/llvm/test/CodeGen/Mips/msa/i5-s.ll +++ b/llvm/test/CodeGen/Mips/msa/i5-s.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 's' diff --git a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll index e55799cf1766..b54247ea0707 100644 --- a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll +++ b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format and ; are loads or stores. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/i8.ll b/llvm/test/CodeGen/Mips/msa/i8.ll index 89f5725c1735..b286574079da 100644 --- a/llvm/test/CodeGen/Mips/msa/i8.ll +++ b/llvm/test/CodeGen/Mips/msa/i8.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I8 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll index bbb76f3b8b6b..f8bb5b36c44c 100644 --- a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll +++ b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 +; RUN: not --crash llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 ; RUN: FileCheck %s < %t1 ; Test that the immediate intrinsics with out of range values trigger an error. diff --git a/llvm/test/CodeGen/Mips/msa/immediates.ll b/llvm/test/CodeGen/Mips/msa/immediates.ll index 5808643aded1..ba1ae74f227b 100644 --- a/llvm/test/CodeGen/Mips/msa/immediates.ll +++ b/llvm/test/CodeGen/Mips/msa/immediates.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck %s -check-prefixes=MSA,MSA32 -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \ +; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \ ; RUN: | FileCheck %s -check-prefix=MSA64N32 -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \ +; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \ ; RUN: | FileCheck %s -check-prefixes=MSA,MSA64N64 ; Test that the immediate intrinsics don't crash LLVM. diff --git a/llvm/test/CodeGen/Mips/msa/inline-asm.ll b/llvm/test/CodeGen/Mips/msa/inline-asm.ll index f84b11e05387..a41f96047ba7 100644 --- a/llvm/test/CodeGen/Mips/msa/inline-asm.ll +++ b/llvm/test/CodeGen/Mips/msa/inline-asm.ll @@ -1,6 +1,6 @@ ; A basic inline assembly test -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @v4i32_r = global <4 x i32> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/ldr_str.ll b/llvm/test/CodeGen/Mips/msa/ldr_str.ll index 74f84aa9bbd7..ff766491834e 100644 --- a/llvm/test/CodeGen/Mips/msa/ldr_str.ll +++ b/llvm/test/CodeGen/Mips/msa/ldr_str.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB -; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL -; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB +; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB +; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL +; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6 ; Test intrinsics for 4-byte and 8-byte MSA load and stores. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll index db2b52028a89..d658dbdce639 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; "Unexpected illegal type!" assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll index a220b9887f90..77fa9f471521 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; `Opc && "Cannot copy registers"' assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll index e27ca939d42d..d4b80c63aea8 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a "Cannot select ..." error. ; This was because undef's are ignored when checking if a vector constant is a diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll index 91f2ca3d8d50..cd20c98e2fe4 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a "Cannot select ..." error. ; This happened because the legalizer treated undef's in the <4 x float> diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll index d1d2f0db69dc..596dc2594c9b 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA after dereferencing a null this pointer. ; It should at least successfully build. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll index c3158801bee5..137e7cf4efa6 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; "Don't know how to expand this condition!" unreachable. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll index ace3f54b33a3..c8123e9a8c8e 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; "Type for zero vector elements is not legal" assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll index d88dfb6bd29a..cea8ac8f9fff 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed to select instructions for extract_vector_elt for ; v4f32 on MSA. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll index de3f5a27eb46..81d6830a19f1 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test is based on an llvm-stress generated test case with seed=449609655 diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll index 0185c8d3eb33..aad184962c44 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed for MSA with a ; `Num < NumOperands && "Invalid child # of SDNode!"' assertion. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll index ae02778783e3..d3b65b5177e3 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed to select instructions for extract_vector_elt for ; v2f64 on MSA. diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll index 16900fbf4838..8fc5de240650 100644 --- a/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll +++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips < %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s -; RUN: llc -march=mipsel < %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mips < %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s +; RUN: llc -mtriple=mipsel < %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s ; This test originally failed to select code for a truncstore of a ; build_vector. diff --git a/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll b/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll index 3071a358d6dc..8deff611f66b 100644 --- a/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll +++ b/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s +; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s ; Test that the register allocator honours +nooddspreg and does not pick an odd ; single precision subregister of an MSA register. diff --git a/llvm/test/CodeGen/Mips/msa/nori.b.ll b/llvm/test/CodeGen/Mips/msa/nori.b.ll index ea0d2a958a29..3332dd34d2de 100644 --- a/llvm/test/CodeGen/Mips/msa/nori.b.ll +++ b/llvm/test/CodeGen/Mips/msa/nori.b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s ; Test that simply checks if it will finish when value 255 (-1) appears as ; immediate in 'nori.b' instruction. diff --git a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll index 64f976c97a35..313b51ee31f4 100644 --- a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll +++ b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O3 -march=mipsel -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=mipsel-elf -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s ; Test that checks if spill for ldi can be avoided and instruction will be ; rematerialized. diff --git a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll index 1f8572751c1a..dbbd0fdfaf89 100644 --- a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll +++ b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @ashr_v4i32(ptr %c) nounwind { ; CHECK-LABEL: ashr_v4i32: diff --git a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll index 9312a05f5696..79fb1b04da5f 100644 --- a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll +++ b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll @@ -1,13 +1,13 @@ ; Test whether the following functions, with vectors featuring negative or values larger than the element ; bit size have their results of operations generated correctly when placed into constant pools -; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips64el-elf -mattr=+msa,+fp64 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s @llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/shift_no_and.ll b/llvm/test/CodeGen/Mips/msa/shift_no_and.ll index d975f43e0c06..58d20458afc7 100644 --- a/llvm/test/CodeGen/Mips/msa/shift_no_and.ll +++ b/llvm/test/CodeGen/Mips/msa/shift_no_and.ll @@ -1,7 +1,7 @@ ; Test the absence of the andi.b / and.v instructions -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/shuffle.ll b/llvm/test/CodeGen/Mips/msa/shuffle.ll index 61b42f5df441..e93bb7cdd112 100644 --- a/llvm/test/CodeGen/Mips/msa/shuffle.ll +++ b/llvm/test/CodeGen/Mips/msa/shuffle.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define void @vshf_v16i8_0(ptr %c, ptr %a, ptr %b) nounwind { ; CHECK-LABEL: vshf_v16i8_0: diff --git a/llvm/test/CodeGen/Mips/msa/special.ll b/llvm/test/CodeGen/Mips/msa/special.ll index 3e392110cccf..f70d9db34841 100644 --- a/llvm/test/CodeGen/Mips/msa/special.ll +++ b/llvm/test/CodeGen/Mips/msa/special.ll @@ -1,12 +1,12 @@ ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips-elf -mcpu=mips32r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \ +; RUN: llc -mtriple=mips64-elf -mcpu=mips64r6 -mattr=+msa < %s | \ ; RUN: FileCheck %s --check-prefix=MIPS64 define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind { diff --git a/llvm/test/CodeGen/Mips/msa/spill.ll b/llvm/test/CodeGen/Mips/msa/spill.ll index 29f02920b10c..5b00f3cad12c 100644 --- a/llvm/test/CodeGen/Mips/msa/spill.ll +++ b/llvm/test/CodeGen/Mips/msa/spill.ll @@ -1,8 +1,8 @@ ; Test that the correct instruction is chosen for spill and reload by trying ; to have 33 live MSA registers simultaneously -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s define i32 @test_i8(ptr %p0, ptr %q1) nounwind { entry: diff --git a/llvm/test/CodeGen/Mips/msa/vec.ll b/llvm/test/CodeGen/Mips/msa/vec.ll index cc4eba6c95bf..21c550bc7542 100644 --- a/llvm/test/CodeGen/Mips/msa/vec.ll +++ b/llvm/test/CodeGen/Mips/msa/vec.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the VEC instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \ ; RUN: | FileCheck -check-prefix=ANYENDIAN %s @llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/llvm/test/CodeGen/Mips/msa/vecs10.ll b/llvm/test/CodeGen/Mips/msa/vecs10.ll index ce61efc33f3a..9d720f5f318c 100644 --- a/llvm/test/CodeGen/Mips/msa/vecs10.ll +++ b/llvm/test/CodeGen/Mips/msa/vecs10.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the VECS10 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mips-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-elf -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s @llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 |