diff options
Diffstat (limited to 'llvm/test/CodeGen/LoongArch/lsx')
259 files changed, 1958 insertions, 697 deletions
diff --git a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll index c46747ef3050..349684ff22be 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll @@ -1,16 +1,27 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s - -; TODO: Load a element and splat it to a vector could be lowerd to vldrepl +; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 ; A load has more than one user shouldn't be lowered to vldrepl define <2 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst){ -; CHECK-LABEL: should_not_be_optimized: -; CHECK: # %bb.0: -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: vreplgr2vr.d $vr0, $a0 -; CHECK-NEXT: st.d $a0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: should_not_be_optimized: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: st.w $a2, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3 +; LA32-NEXT: st.w $a0, $a1, 4 +; LA32-NEXT: ret +; +; LA64-LABEL: should_not_be_optimized: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vreplgr2vr.d $vr0, $a0 +; LA64-NEXT: st.d $a0, $a1, 0 +; LA64-NEXT: ret %tmp = load i64, ptr %ptr store i64 %tmp, ptr %dst %tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0 @@ -18,12 +29,48 @@ define <2 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst){ ret <2 x i64> %tmp2 } -define <2 x i64> @vldrepl_d_unaligned_offset(ptr %ptr) { -; CHECK-LABEL: vldrepl_d_unaligned_offset: +define <8 x i16> @should_not_be_optimized_sext_load(ptr %ptr) { +; CHECK-LABEL: should_not_be_optimized_sext_load: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $a0, $a0, 4 -; CHECK-NEXT: vldrepl.d $vr0, $a0, 0 +; CHECK-NEXT: ld.b $a0, $a0, 0 +; CHECK-NEXT: vreplgr2vr.h $vr0, $a0 +; CHECK-NEXT: ret + %tmp = load i8, ptr %ptr + %tmp1 = sext i8 %tmp to i16 + %tmp2 = insertelement <8 x i16> zeroinitializer, i16 %tmp1, i32 0 + %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> poison, <8 x i32> zeroinitializer + ret <8 x i16> %tmp3 +} + +define <8 x i16> @should_not_be_optimized_zext_load(ptr %ptr) { +; CHECK-LABEL: should_not_be_optimized_zext_load: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.bu $a0, $a0, 0 +; CHECK-NEXT: vreplgr2vr.h $vr0, $a0 ; CHECK-NEXT: ret + %tmp = load i8, ptr %ptr + %tmp1 = zext i8 %tmp to i16 + %tmp2 = insertelement <8 x i16> zeroinitializer, i16 %tmp1, i32 0 + %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> poison, <8 x i32> zeroinitializer + ret <8 x i16> %tmp3 +} + +define <2 x i64> @vldrepl_d_unaligned_offset(ptr %ptr) { +; LA32-LABEL: vldrepl_d_unaligned_offset: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a0, $a0, 8 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3 +; LA32-NEXT: ret +; +; LA64-LABEL: vldrepl_d_unaligned_offset: +; LA64: # %bb.0: +; LA64-NEXT: addi.d $a0, $a0, 4 +; LA64-NEXT: vldrepl.d $vr0, $a0, 0 +; LA64-NEXT: ret %p = getelementptr i32, ptr %ptr, i32 1 %tmp = load i64, ptr %p %tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0 @@ -102,10 +149,20 @@ define <4 x i32> @vldrepl_w_offset(ptr %ptr) { } define <2 x i64> @vldrepl_d(ptr %ptr) { -; CHECK-LABEL: vldrepl_d: -; CHECK: # %bb.0: -; CHECK-NEXT: vldrepl.d $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: vldrepl_d: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a1, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3 +; LA32-NEXT: ret +; +; LA64-LABEL: vldrepl_d: +; LA64: # %bb.0: +; LA64-NEXT: vldrepl.d $vr0, $a0, 0 +; LA64-NEXT: ret %tmp = load i64, ptr %ptr %tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0 %tmp2 = shufflevector <2 x i64> %tmp1, <2 x i64> poison, <2 x i32> zeroinitializer @@ -113,10 +170,20 @@ define <2 x i64> @vldrepl_d(ptr %ptr) { } define <2 x i64> @vldrepl_d_offset(ptr %ptr) { -; CHECK-LABEL: vldrepl_d_offset: -; CHECK: # %bb.0: -; CHECK-NEXT: vldrepl.d $vr0, $a0, 264 -; CHECK-NEXT: ret +; LA32-LABEL: vldrepl_d_offset: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a1, $a0, 264 +; LA32-NEXT: ld.w $a0, $a0, 268 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3 +; LA32-NEXT: ret +; +; LA64-LABEL: vldrepl_d_offset: +; LA64: # %bb.0: +; LA64-NEXT: vldrepl.d $vr0, $a0, 264 +; LA64-NEXT: ret %p = getelementptr i64, ptr %ptr, i64 33 %tmp = load i64, ptr %p %tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0 diff --git a/llvm/test/CodeGen/LoongArch/lsx/bswap.ll b/llvm/test/CodeGen/LoongArch/lsx/bswap.ll index 8172e21eae34..ecfb82627fe9 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/bswap.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/bswap.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s define void @bswap_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: bswap_v8i16: diff --git a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll index 9517558a92ed..24df71c2ad71 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind { ; CHECK-LABEL: buildvector_v16i8_splat: @@ -41,11 +42,20 @@ entry: } define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind { -; CHECK-LABEL: buildvector_v2i64_splat: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vreplgr2vr.d $vr0, $a1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v2i64_splat: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v2i64_splat: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vreplgr2vr.d $vr0, $a1 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %insert = insertelement <2 x i64> undef, i64 %a0, i8 0 %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer @@ -138,12 +148,19 @@ entry: } define void @buildvector_v2f64_const_splat(ptr %dst) nounwind { -; CHECK-LABEL: buildvector_v2f64_const_splat: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lu52i.d $a1, $zero, 1023 -; CHECK-NEXT: vreplgr2vr.d $vr0, $a1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v2f64_const_splat: +; LA32: # %bb.0: # %entry +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0) +; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0) +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v2f64_const_splat: +; LA64: # %bb.0: # %entry +; LA64-NEXT: lu52i.d $a1, $zero, 1023 +; LA64-NEXT: vreplgr2vr.d $vr0, $a1 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: store <2 x double> <double 1.0, double 1.0>, ptr %dst ret void @@ -222,35 +239,65 @@ entry: } define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind { -; CHECK-LABEL: buildvector_v16i8: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ld.b $t0, $sp, 64 -; CHECK-NEXT: ld.b $t1, $sp, 56 -; CHECK-NEXT: ld.b $t2, $sp, 48 -; CHECK-NEXT: ld.b $t3, $sp, 40 -; CHECK-NEXT: ld.b $t4, $sp, 32 -; CHECK-NEXT: ld.b $t5, $sp, 24 -; CHECK-NEXT: ld.b $t6, $sp, 16 -; CHECK-NEXT: ld.b $t7, $sp, 8 -; CHECK-NEXT: ld.b $t8, $sp, 0 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 4 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 5 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 6 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t8, 7 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t7, 8 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t6, 9 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t5, 10 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t4, 11 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t3, 12 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t2, 13 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t1, 14 -; CHECK-NEXT: vinsgr2vr.b $vr0, $t0, 15 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v16i8: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.b $t0, $sp, 32 +; LA32-NEXT: ld.b $t1, $sp, 28 +; LA32-NEXT: ld.b $t2, $sp, 24 +; LA32-NEXT: ld.b $t3, $sp, 20 +; LA32-NEXT: ld.b $t4, $sp, 16 +; LA32-NEXT: ld.b $t5, $sp, 12 +; LA32-NEXT: ld.b $t6, $sp, 8 +; LA32-NEXT: ld.b $t7, $sp, 4 +; LA32-NEXT: ld.b $t8, $sp, 0 +; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA32-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; LA32-NEXT: vinsgr2vr.b $vr0, $a3, 2 +; LA32-NEXT: vinsgr2vr.b $vr0, $a4, 3 +; LA32-NEXT: vinsgr2vr.b $vr0, $a5, 4 +; LA32-NEXT: vinsgr2vr.b $vr0, $a6, 5 +; LA32-NEXT: vinsgr2vr.b $vr0, $a7, 6 +; LA32-NEXT: vinsgr2vr.b $vr0, $t8, 7 +; LA32-NEXT: vinsgr2vr.b $vr0, $t7, 8 +; LA32-NEXT: vinsgr2vr.b $vr0, $t6, 9 +; LA32-NEXT: vinsgr2vr.b $vr0, $t5, 10 +; LA32-NEXT: vinsgr2vr.b $vr0, $t4, 11 +; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 12 +; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 13 +; LA32-NEXT: vinsgr2vr.b $vr0, $t1, 14 +; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 15 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v16i8: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.b $t0, $sp, 64 +; LA64-NEXT: ld.b $t1, $sp, 56 +; LA64-NEXT: ld.b $t2, $sp, 48 +; LA64-NEXT: ld.b $t3, $sp, 40 +; LA64-NEXT: ld.b $t4, $sp, 32 +; LA64-NEXT: ld.b $t5, $sp, 24 +; LA64-NEXT: ld.b $t6, $sp, 16 +; LA64-NEXT: ld.b $t7, $sp, 8 +; LA64-NEXT: ld.b $t8, $sp, 0 +; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA64-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; LA64-NEXT: vinsgr2vr.b $vr0, $a3, 2 +; LA64-NEXT: vinsgr2vr.b $vr0, $a4, 3 +; LA64-NEXT: vinsgr2vr.b $vr0, $a5, 4 +; LA64-NEXT: vinsgr2vr.b $vr0, $a6, 5 +; LA64-NEXT: vinsgr2vr.b $vr0, $a7, 6 +; LA64-NEXT: vinsgr2vr.b $vr0, $t8, 7 +; LA64-NEXT: vinsgr2vr.b $vr0, $t7, 8 +; LA64-NEXT: vinsgr2vr.b $vr0, $t6, 9 +; LA64-NEXT: vinsgr2vr.b $vr0, $t5, 10 +; LA64-NEXT: vinsgr2vr.b $vr0, $t4, 11 +; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 12 +; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 13 +; LA64-NEXT: vinsgr2vr.b $vr0, $t1, 14 +; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 15 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 @@ -338,6 +385,133 @@ entry: ret void } +define void @buildvector_v16i8_subseq_2(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7) nounwind { +; CHECK-LABEL: buildvector_v16i8_subseq_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ld.b $t0, $sp, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 4 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 5 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 6 +; CHECK-NEXT: vinsgr2vr.b $vr0, $t0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 8 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 9 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 10 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 11 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 12 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 13 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 14 +; CHECK-NEXT: vinsgr2vr.b $vr0, $t0, 15 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 + %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 + %ins4 = insertelement <16 x i8> %ins3, i8 %a4, i32 4 + %ins5 = insertelement <16 x i8> %ins4, i8 %a5, i32 5 + %ins6 = insertelement <16 x i8> %ins5, i8 %a6, i32 6 + %ins7 = insertelement <16 x i8> %ins6, i8 %a7, i32 7 + %ins8 = insertelement <16 x i8> %ins7, i8 %a0, i32 8 + %ins9 = insertelement <16 x i8> %ins8, i8 %a1, i32 9 + %ins10 = insertelement <16 x i8> %ins9, i8 %a2, i32 10 + %ins11 = insertelement <16 x i8> %ins10, i8 %a3, i32 11 + %ins12 = insertelement <16 x i8> %ins11, i8 %a4, i32 12 + %ins13 = insertelement <16 x i8> %ins12, i8 %a5, i32 13 + %ins14 = insertelement <16 x i8> %ins13, i8 %a6, i32 14 + %ins15 = insertelement <16 x i8> %ins14, i8 %a7, i32 15 + store <16 x i8> %ins15, ptr %dst + ret void +} + +define void @buildvector_v16i8_subseq_4(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3) nounwind { +; CHECK-LABEL: buildvector_v16i8_subseq_4: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 4 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 5 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 6 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 7 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 8 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 9 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 10 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 11 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 12 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 13 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 14 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 15 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2 + %ins3 = insertelement <16 x i8> %ins2, i8 %a3, i32 3 + %ins4 = insertelement <16 x i8> %ins3, i8 %a0, i32 4 + %ins5 = insertelement <16 x i8> %ins4, i8 %a1, i32 5 + %ins6 = insertelement <16 x i8> %ins5, i8 %a2, i32 6 + %ins7 = insertelement <16 x i8> %ins6, i8 %a3, i32 7 + %ins8 = insertelement <16 x i8> %ins7, i8 %a0, i32 8 + %ins9 = insertelement <16 x i8> %ins8, i8 %a1, i32 9 + %ins10 = insertelement <16 x i8> %ins9, i8 %a2, i32 10 + %ins11 = insertelement <16 x i8> %ins10, i8 %a3, i32 11 + %ins12 = insertelement <16 x i8> %ins11, i8 %a0, i32 12 + %ins13 = insertelement <16 x i8> %ins12, i8 %a1, i32 13 + %ins14 = insertelement <16 x i8> %ins13, i8 %a2, i32 14 + %ins15 = insertelement <16 x i8> %ins14, i8 %a3, i32 15 + store <16 x i8> %ins15, ptr %dst + ret void +} + +define void @buildvector_v16i8_subseq_8(ptr %dst, i8 %a0, i8 %a1) nounwind { +; CHECK-LABEL: buildvector_v16i8_subseq_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 3 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 4 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 5 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 6 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 7 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 8 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 9 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 10 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 11 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 12 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 13 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 14 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 15 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <16 x i8> %ins1, i8 %a0, i32 2 + %ins3 = insertelement <16 x i8> %ins2, i8 %a1, i32 3 + %ins4 = insertelement <16 x i8> %ins3, i8 %a0, i32 4 + %ins5 = insertelement <16 x i8> %ins4, i8 %a1, i32 5 + %ins6 = insertelement <16 x i8> %ins5, i8 %a0, i32 6 + %ins7 = insertelement <16 x i8> %ins6, i8 %a1, i32 7 + %ins8 = insertelement <16 x i8> %ins7, i8 %a0, i32 8 + %ins9 = insertelement <16 x i8> %ins8, i8 %a1, i32 9 + %ins10 = insertelement <16 x i8> %ins9, i8 %a0, i32 10 + %ins11 = insertelement <16 x i8> %ins10, i8 %a1, i32 11 + %ins12 = insertelement <16 x i8> %ins11, i8 %a0, i32 12 + %ins13 = insertelement <16 x i8> %ins12, i8 %a1, i32 13 + %ins14 = insertelement <16 x i8> %ins13, i8 %a0, i32 14 + %ins15 = insertelement <16 x i8> %ins14, i8 %a1, i32 15 + store <16 x i8> %ins15, ptr %dst + ret void +} + define void @buildvector_v8i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { ; CHECK-LABEL: buildvector_v8i16: ; CHECK: # %bb.0: # %entry @@ -410,6 +584,58 @@ entry: ret void } +define void @buildvector_v8i16_subseq_2(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3) nounwind { +; CHECK-LABEL: buildvector_v8i16_subseq_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 2 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 3 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 4 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 5 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 6 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 7 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 + %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 + %ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2 + %ins3 = insertelement <8 x i16> %ins2, i16 %a3, i32 3 + %ins4 = insertelement <8 x i16> %ins3, i16 %a0, i32 4 + %ins5 = insertelement <8 x i16> %ins4, i16 %a1, i32 5 + %ins6 = insertelement <8 x i16> %ins5, i16 %a2, i32 6 + %ins7 = insertelement <8 x i16> %ins6, i16 %a3, i32 7 + store <8 x i16> %ins7, ptr %dst + ret void +} + +define void @buildvector_v8i16_subseq_4(ptr %dst, i16 %a0, i16 %a1) nounwind { +; CHECK-LABEL: buildvector_v8i16_subseq_4: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 2 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 3 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 4 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 5 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 6 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 7 +; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0 + %ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1 + %ins2 = insertelement <8 x i16> %ins1, i16 %a0, i32 2 + %ins3 = insertelement <8 x i16> %ins2, i16 %a1, i32 3 + %ins4 = insertelement <8 x i16> %ins3, i16 %a0, i32 4 + %ins5 = insertelement <8 x i16> %ins4, i16 %a1, i32 5 + %ins6 = insertelement <8 x i16> %ins5, i16 %a0, i32 6 + %ins7 = insertelement <8 x i16> %ins6, i16 %a1, i32 7 + store <8 x i16> %ins7, ptr %dst + ret void +} + define void @buildvector_v4i32(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind { ; CHECK-LABEL: buildvector_v4i32: ; CHECK: # %bb.0: # %entry @@ -462,14 +688,41 @@ entry: ret void } -define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind { -; CHECK-LABEL: buildvector_v2i64: +define void @buildvector_v4i32_subseq_2(ptr %dst, i32 %a0, i32 %a1) nounwind { +; CHECK-LABEL: buildvector_v4i32_subseq_2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 1 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a1, 2 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 3 ; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: + %ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0 + %ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1 + %ins2 = insertelement <4 x i32> %ins1, i32 %a0, i32 2 + %ins3 = insertelement <4 x i32> %ins2, i32 %a1, i32 3 + store <4 x i32> %ins3, ptr %dst + ret void +} + +define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind { +; LA32-LABEL: buildvector_v2i64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1 +; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 3 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v2i64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 1 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret +entry: %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0 %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1 store <2 x i64> %ins1, ptr %dst @@ -477,11 +730,18 @@ entry: } define void @buildvector_v2i64_partial(ptr %dst, i64 %a0) nounwind { -; CHECK-LABEL: buildvector_v2i64_partial: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v2i64_partial: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v2i64_partial: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0 %ins1 = insertelement <2 x i64> %ins0, i64 undef, i32 1 @@ -490,12 +750,20 @@ entry: } define void @buildvector_v2i64_with_constant(ptr %dst, i64 %a1) nounwind { -; CHECK-LABEL: buildvector_v2i64_with_constant: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vrepli.b $vr0, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v2i64_with_constant: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vrepli.b $vr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v2i64_with_constant: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vrepli.b $vr0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 1 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %ins0 = insertelement <2 x i64> undef, i64 0, i32 0 %ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1 @@ -562,6 +830,26 @@ entry: ret void } +define void @buildvector_v4f32_subseq_2(ptr %dst, float %a0, float %a1) nounwind { +; CHECK-LABEL: buildvector_v4f32_subseq_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f1 killed $f1 def $vr1 +; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0 +; CHECK-NEXT: vori.b $vr2, $vr0, 0 +; CHECK-NEXT: vextrins.w $vr2, $vr1, 16 +; CHECK-NEXT: vextrins.w $vr2, $vr0, 32 +; CHECK-NEXT: vextrins.w $vr2, $vr1, 48 +; CHECK-NEXT: vst $vr2, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <4 x float> undef, float %a0, i32 0 + %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1 + %ins2 = insertelement <4 x float> %ins1, float %a0, i32 2 + %ins3 = insertelement <4 x float> %ins2, float %a1, i32 3 + store <4 x float> %ins3, ptr %dst + ret void +} + define void @buildvector_v2f64(ptr %dst, double %a0, double %a1) nounwind { ; CHECK-LABEL: buildvector_v2f64: ; CHECK: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll b/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll index 5df553fba7ef..a9a38e8f75f9 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s define void @ctpop_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: ctpop_v16i8: diff --git a/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll index 21dbbf310ad8..58e16d37ae27 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefix=FAULT -; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA32 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA64 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind { ; FAULT-LABEL: fdiv_v4f32: @@ -13,13 +15,13 @@ define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind { ; ; CHECK-LABEL: fdiv_v4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a2, 0 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: vfrecipe.s $vr2, $vr0 -; CHECK-NEXT: vfmul.s $vr3, $vr1, $vr2 -; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr3, $vr1 -; CHECK-NEXT: vfmadd.s $vr0, $vr2, $vr0, $vr3 -; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: vld $vr0, $a2, 0 +; CHECK-NEXT: vld $vr1, $a1, 0 +; CHECK-NEXT: vfrecipe.s $vr2, $vr0 +; CHECK-NEXT: vfmul.s $vr3, $vr1, $vr2 +; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr3, $vr1 +; CHECK-NEXT: vfmadd.s $vr0, $vr2, $vr0, $vr3 +; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: %v0 = load <4 x float>, ptr %a0 @@ -38,20 +40,35 @@ define void @fdiv_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind { ; FAULT-NEXT: vst $vr0, $a0, 0 ; FAULT-NEXT: ret ; -; CHECK-LABEL: fdiv_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a2, 0 -; CHECK-NEXT: vld $vr1, $a1, 0 -; CHECK-NEXT: lu52i.d $a1, $zero, -1025 -; CHECK-NEXT: vreplgr2vr.d $vr2, $a1 -; CHECK-NEXT: vfrecipe.d $vr3, $vr0 -; CHECK-NEXT: vfmadd.d $vr2, $vr0, $vr3, $vr2 -; CHECK-NEXT: vfnmsub.d $vr2, $vr2, $vr3, $vr3 -; CHECK-NEXT: vfmul.d $vr3, $vr1, $vr2 -; CHECK-NEXT: vfnmsub.d $vr0, $vr0, $vr3, $vr1 -; CHECK-NEXT: vfmadd.d $vr0, $vr2, $vr0, $vr3 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: fdiv_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI1_0) +; LA32-NEXT: vld $vr0, $a2, 0 +; LA32-NEXT: vld $vr1, $a3, %pc_lo12(.LCPI1_0) +; LA32-NEXT: vld $vr2, $a1, 0 +; LA32-NEXT: vfrecipe.d $vr3, $vr0 +; LA32-NEXT: vfmadd.d $vr1, $vr0, $vr3, $vr1 +; LA32-NEXT: vfnmsub.d $vr1, $vr1, $vr3, $vr3 +; LA32-NEXT: vfmul.d $vr3, $vr2, $vr1 +; LA32-NEXT: vfnmsub.d $vr0, $vr0, $vr3, $vr2 +; LA32-NEXT: vfmadd.d $vr0, $vr1, $vr0, $vr3 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: fdiv_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vld $vr0, $a2, 0 +; LA64-NEXT: vld $vr1, $a1, 0 +; LA64-NEXT: lu52i.d $a1, $zero, -1025 +; LA64-NEXT: vreplgr2vr.d $vr2, $a1 +; LA64-NEXT: vfrecipe.d $vr3, $vr0 +; LA64-NEXT: vfmadd.d $vr2, $vr0, $vr3, $vr2 +; LA64-NEXT: vfnmsub.d $vr2, $vr2, $vr3, $vr3 +; LA64-NEXT: vfmul.d $vr3, $vr1, $vr2 +; LA64-NEXT: vfnmsub.d $vr0, $vr0, $vr3, $vr1 +; LA64-NEXT: vfmadd.d $vr0, $vr2, $vr0, $vr3 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <2 x double>, ptr %a0 %v1 = load <2 x double>, ptr %a1 @@ -71,13 +88,13 @@ define void @one_fdiv_v4f32(ptr %res, ptr %a0) nounwind { ; ; CHECK-LABEL: one_fdiv_v4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vfrecipe.s $vr1, $vr0 -; CHECK-NEXT: lu12i.w $a1, -264192 -; CHECK-NEXT: vreplgr2vr.w $vr2, $a1 -; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2 -; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr1, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vfrecipe.s $vr1, $vr0 +; CHECK-NEXT: lu12i.w $a1, -264192 +; CHECK-NEXT: vreplgr2vr.w $vr2, $a1 +; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2 +; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr1, $vr1 +; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: %v0 = load <4 x float>, ptr %a0 @@ -87,25 +104,47 @@ entry: } define void @one_fdiv_v2f64(ptr %res, ptr %a0) nounwind { -; FAULT-LABEL: one_fdiv_v2f64: -; FAULT: # %bb.0: # %entry -; FAULT-NEXT: vld $vr0, $a1, 0 -; FAULT-NEXT: vfrecip.d $vr0, $vr0 -; FAULT-NEXT: vst $vr0, $a0, 0 -; FAULT-NEXT: ret +; FAULT-LA32-LABEL: one_fdiv_v2f64: +; FAULT-LA32: # %bb.0: # %entry +; FAULT-LA32-NEXT: vld $vr0, $a1, 0 +; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; FAULT-LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0) +; FAULT-LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0 +; FAULT-LA32-NEXT: vst $vr0, $a0, 0 +; FAULT-LA32-NEXT: ret ; -; CHECK-LABEL: one_fdiv_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vfrecipe.d $vr1, $vr0 -; CHECK-NEXT: lu52i.d $a1, $zero, 1023 -; CHECK-NEXT: vreplgr2vr.d $vr2, $a1 -; CHECK-NEXT: vfnmsub.d $vr3, $vr0, $vr1, $vr2 -; CHECK-NEXT: vfmadd.d $vr1, $vr1, $vr3, $vr1 -; CHECK-NEXT: vfnmsub.d $vr0, $vr0, $vr1, $vr2 -; CHECK-NEXT: vfmadd.d $vr0, $vr1, $vr0, $vr1 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_fdiv_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vld $vr0, $a1, 0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: vfrecipe.d $vr2, $vr0 +; LA32-NEXT: vfnmsub.d $vr3, $vr0, $vr2, $vr1 +; LA32-NEXT: vfmadd.d $vr2, $vr2, $vr3, $vr2 +; LA32-NEXT: vfnmsub.d $vr0, $vr0, $vr2, $vr1 +; LA32-NEXT: vfmadd.d $vr0, $vr2, $vr0, $vr2 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; FAULT-LA64-LABEL: one_fdiv_v2f64: +; FAULT-LA64: # %bb.0: # %entry +; FAULT-LA64-NEXT: vld $vr0, $a1, 0 +; FAULT-LA64-NEXT: vfrecip.d $vr0, $vr0 +; FAULT-LA64-NEXT: vst $vr0, $a0, 0 +; FAULT-LA64-NEXT: ret +; +; LA64-LABEL: one_fdiv_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vld $vr0, $a1, 0 +; LA64-NEXT: vfrecipe.d $vr1, $vr0 +; LA64-NEXT: lu52i.d $a1, $zero, 1023 +; LA64-NEXT: vreplgr2vr.d $vr2, $a1 +; LA64-NEXT: vfnmsub.d $vr3, $vr0, $vr1, $vr2 +; LA64-NEXT: vfmadd.d $vr1, $vr1, $vr3, $vr1 +; LA64-NEXT: vfnmsub.d $vr0, $vr0, $vr1, $vr2 +; LA64-NEXT: vfmadd.d $vr0, $vr1, $vr0, $vr1 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <2 x double>, ptr %a0 %div = fdiv fast <2 x double> <double 1.0, double 1.0>, %v0 diff --git a/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll b/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll index c83c563952d4..89442908b31b 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll @@ -1,8 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=fast < %s \ +; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST ; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=fast < %s \ ; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=on < %s \ +; RUN: | FileCheck %s --check-prefix=CONTRACT-ON ; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=on < %s \ ; RUN: | FileCheck %s --check-prefix=CONTRACT-ON +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=off < %s \ +; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF ; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=off < %s \ ; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF diff --git a/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll b/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll index 1f316d5b1c8a..0e5cd3cdcd35 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll @@ -1,8 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=fast < %s \ +; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST ; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=fast < %s \ ; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=on < %s \ +; RUN: | FileCheck %s --check-prefix=CONTRACT-ON ; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=on < %s \ ; RUN: | FileCheck %s --check-prefix=CONTRACT-ON +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=off < %s \ +; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF ; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=off < %s \ ; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF diff --git a/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll b/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll index 735dad453660..8005318f4f62 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll @@ -1,57 +1,102 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefix=LA64 declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32) define <4 x float> @powi_v4f32(<4 x float> %va, i32 %b) nounwind { -; CHECK-LABEL: powi_v4f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi.d $sp, $sp, -48 -; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill -; CHECK-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill -; CHECK-NEXT: addi.w $fp, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr0, $vr0, 1 -; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 -; CHECK-NEXT: move $a0, $fp -; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2) -; CHECK-NEXT: jirl $ra, $ra, 0 -; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0 -; CHECK-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill -; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload -; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0 -; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 -; CHECK-NEXT: move $a0, $fp -; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2) -; CHECK-NEXT: jirl $ra, $ra, 0 -; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0 -; CHECK-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload -; CHECK-NEXT: vextrins.w $vr0, $vr1, 16 -; CHECK-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill -; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload -; CHECK-NEXT: vreplvei.w $vr0, $vr0, 2 -; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 -; CHECK-NEXT: move $a0, $fp -; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2) -; CHECK-NEXT: jirl $ra, $ra, 0 -; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0 -; CHECK-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload -; CHECK-NEXT: vextrins.w $vr1, $vr0, 32 -; CHECK-NEXT: vst $vr1, $sp, 0 # 16-byte Folded Spill -; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload -; CHECK-NEXT: vreplvei.w $vr0, $vr0, 3 -; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 -; CHECK-NEXT: move $a0, $fp -; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2) -; CHECK-NEXT: jirl $ra, $ra, 0 -; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0 -; CHECK-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload -; CHECK-NEXT: vextrins.w $vr1, $vr0, 48 -; CHECK-NEXT: vori.b $vr0, $vr1, 0 -; CHECK-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 48 -; CHECK-NEXT: ret +; LA32-LABEL: powi_v4f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -48 +; LA32-NEXT: st.w $ra, $sp, 44 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 40 # 4-byte Folded Spill +; LA32-NEXT: move $fp, $a0 +; LA32-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill +; LA32-NEXT: vreplvei.w $vr0, $vr0, 1 +; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA32-NEXT: bl __powisf2 +; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA32-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill +; LA32-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload +; LA32-NEXT: vreplvei.w $vr0, $vr0, 0 +; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA32-NEXT: move $a0, $fp +; LA32-NEXT: bl __powisf2 +; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA32-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload +; LA32-NEXT: vextrins.w $vr0, $vr1, 16 +; LA32-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill +; LA32-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload +; LA32-NEXT: vreplvei.w $vr0, $vr0, 2 +; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA32-NEXT: move $a0, $fp +; LA32-NEXT: bl __powisf2 +; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA32-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload +; LA32-NEXT: vextrins.w $vr1, $vr0, 32 +; LA32-NEXT: vst $vr1, $sp, 0 # 16-byte Folded Spill +; LA32-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload +; LA32-NEXT: vreplvei.w $vr0, $vr0, 3 +; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA32-NEXT: move $a0, $fp +; LA32-NEXT: bl __powisf2 +; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA32-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload +; LA32-NEXT: vextrins.w $vr1, $vr0, 48 +; LA32-NEXT: vori.b $vr0, $vr1, 0 +; LA32-NEXT: ld.w $fp, $sp, 40 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 44 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 48 +; LA32-NEXT: ret +; +; LA64-LABEL: powi_v4f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: addi.d $sp, $sp, -48 +; LA64-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill +; LA64-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill +; LA64-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill +; LA64-NEXT: addi.w $fp, $a0, 0 +; LA64-NEXT: vreplvei.w $vr0, $vr0, 1 +; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA64-NEXT: move $a0, $fp +; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2) +; LA64-NEXT: jirl $ra, $ra, 0 +; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA64-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill +; LA64-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload +; LA64-NEXT: vreplvei.w $vr0, $vr0, 0 +; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA64-NEXT: move $a0, $fp +; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2) +; LA64-NEXT: jirl $ra, $ra, 0 +; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA64-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload +; LA64-NEXT: vextrins.w $vr0, $vr1, 16 +; LA64-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill +; LA64-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload +; LA64-NEXT: vreplvei.w $vr0, $vr0, 2 +; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA64-NEXT: move $a0, $fp +; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2) +; LA64-NEXT: jirl $ra, $ra, 0 +; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA64-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload +; LA64-NEXT: vextrins.w $vr1, $vr0, 32 +; LA64-NEXT: vst $vr1, $sp, 0 # 16-byte Folded Spill +; LA64-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload +; LA64-NEXT: vreplvei.w $vr0, $vr0, 3 +; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; LA64-NEXT: move $a0, $fp +; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2) +; LA64-NEXT: jirl $ra, $ra, 0 +; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0 +; LA64-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload +; LA64-NEXT: vextrins.w $vr1, $vr0, 48 +; LA64-NEXT: vori.b $vr0, $vr1, 0 +; LA64-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload +; LA64-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload +; LA64-NEXT: addi.d $sp, $sp, 48 +; LA64-NEXT: ret entry: %res = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %va, i32 %b) ret <4 x float> %res @@ -60,33 +105,58 @@ entry: declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32) define <2 x double> @powi_v2f64(<2 x double> %va, i32 %b) nounwind { -; CHECK-LABEL: powi_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi.d $sp, $sp, -48 -; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill -; CHECK-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill -; CHECK-NEXT: addi.w $fp, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr0, $vr0, 1 -; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 -; CHECK-NEXT: move $a0, $fp -; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2) -; CHECK-NEXT: jirl $ra, $ra, 0 -; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 -; CHECK-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill -; CHECK-NEXT: vld $vr0, $sp, 0 # 16-byte Folded Reload -; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0 -; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 -; CHECK-NEXT: move $a0, $fp -; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2) -; CHECK-NEXT: jirl $ra, $ra, 0 -; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 -; CHECK-NEXT: vld $vr1, $sp, 16 # 16-byte Folded Reload -; CHECK-NEXT: vextrins.d $vr0, $vr1, 16 -; CHECK-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 48 -; CHECK-NEXT: ret +; LA32-LABEL: powi_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -48 +; LA32-NEXT: st.w $ra, $sp, 44 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 40 # 4-byte Folded Spill +; LA32-NEXT: move $fp, $a0 +; LA32-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill +; LA32-NEXT: vreplvei.d $vr0, $vr0, 1 +; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 +; LA32-NEXT: bl __powidf2 +; LA32-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 +; LA32-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill +; LA32-NEXT: vld $vr0, $sp, 0 # 16-byte Folded Reload +; LA32-NEXT: vreplvei.d $vr0, $vr0, 0 +; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 +; LA32-NEXT: move $a0, $fp +; LA32-NEXT: bl __powidf2 +; LA32-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 +; LA32-NEXT: vld $vr1, $sp, 16 # 16-byte Folded Reload +; LA32-NEXT: vextrins.d $vr0, $vr1, 16 +; LA32-NEXT: ld.w $fp, $sp, 40 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 44 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 48 +; LA32-NEXT: ret +; +; LA64-LABEL: powi_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: addi.d $sp, $sp, -48 +; LA64-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill +; LA64-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill +; LA64-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill +; LA64-NEXT: addi.w $fp, $a0, 0 +; LA64-NEXT: vreplvei.d $vr0, $vr0, 1 +; LA64-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 +; LA64-NEXT: move $a0, $fp +; LA64-NEXT: pcaddu18i $ra, %call36(__powidf2) +; LA64-NEXT: jirl $ra, $ra, 0 +; LA64-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 +; LA64-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill +; LA64-NEXT: vld $vr0, $sp, 0 # 16-byte Folded Reload +; LA64-NEXT: vreplvei.d $vr0, $vr0, 0 +; LA64-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 +; LA64-NEXT: move $a0, $fp +; LA64-NEXT: pcaddu18i $ra, %call36(__powidf2) +; LA64-NEXT: jirl $ra, $ra, 0 +; LA64-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0 +; LA64-NEXT: vld $vr1, $sp, 16 # 16-byte Folded Reload +; LA64-NEXT: vextrins.d $vr0, $vr1, 16 +; LA64-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload +; LA64-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload +; LA64-NEXT: addi.d $sp, $sp, 48 +; LA64-NEXT: ret entry: %res = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> %va, i32 %b) ret <2 x double> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll index 912d06242f7d..1f744830bd56 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefix=FAULT -; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA32 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA64 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA64 ;; 1.0 / (fsqrt vec) define void @one_div_sqrt_v4f32(ptr %res, ptr %a0) nounwind { @@ -11,20 +13,20 @@ define void @one_div_sqrt_v4f32(ptr %res, ptr %a0) nounwind { ; FAULT-NEXT: vst $vr0, $a0, 0 ; FAULT-NEXT: ret ; -; CHECK-LABEL one_div_sqrt_v4f32: +; CHECK-LABEL: one_div_sqrt_v4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vfrsqrte.s $vr1, $vr0 -; CHECK-NEXT: vfmul.s $vr1, $vr0, $vr1 -; CHECK-NEXT: vfmul.s $vr0, $vr0, $vr1 -; CHECK-NEXT: lu12i.w $a1, -261120 -; CHECK-NEXT: vreplgr2vr.w $vr2, $a1 -; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2 -; CHECK-NEXT: lu12i.w $a1, -266240 -; CHECK-NEXT: vreplgr2vr.w $vr2, $a1 -; CHECK-NEXT: vfmul.s $vr1, $vr1, $vr2 -; CHECK-NEXT: vfmul.s $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a0, 0 +; CHECK-NEXT: vld $vr0, $a1, 0 +; CHECK-NEXT: vfrsqrte.s $vr1, $vr0 +; CHECK-NEXT: vfmul.s $vr1, $vr0, $vr1 +; CHECK-NEXT: vfmul.s $vr0, $vr0, $vr1 +; CHECK-NEXT: lu12i.w $a1, -261120 +; CHECK-NEXT: vreplgr2vr.w $vr2, $a1 +; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2 +; CHECK-NEXT: lu12i.w $a1, -266240 +; CHECK-NEXT: vreplgr2vr.w $vr2, $a1 +; CHECK-NEXT: vfmul.s $vr1, $vr1, $vr2 +; CHECK-NEXT: vfmul.s $vr0, $vr1, $vr0 +; CHECK-NEXT: vst $vr0, $a0, 0 ; CHECK-NEXT: ret entry: %v0 = load <4 x float>, ptr %a0, align 16 @@ -35,34 +37,64 @@ entry: } define void @one_div_sqrt_v2f64(ptr %res, ptr %a0) nounwind { -; FAULT-LABEL: one_div_sqrt_v2f64: -; FAULT: # %bb.0: # %entry -; FAULT-NEXT: vld $vr0, $a1, 0 -; FAULT-NEXT: vfrsqrt.d $vr0, $vr0 -; FAULT-NEXT: vst $vr0, $a0, 0 -; FAULT-NEXT: ret +; FAULT-LA32-LABEL: one_div_sqrt_v2f64: +; FAULT-LA32: # %bb.0: # %entry +; FAULT-LA32-NEXT: vld $vr0, $a1, 0 +; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0) +; FAULT-LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI1_0) +; FAULT-LA32-NEXT: vfsqrt.d $vr0, $vr0 +; FAULT-LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0 +; FAULT-LA32-NEXT: vst $vr0, $a0, 0 +; FAULT-LA32-NEXT: ret ; -; CHECK-LABEL one_div_sqrt_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vfrsqrte.d $vr1, $vr0 -; CHECK-NEXT: vfmul.d $vr1, $vr0, $vr1 -; CHECK-NEXT: vfmul.d $vr2, $vr0, $vr1 -; CHECK-NEXT: ori $a1, $zero, 0 -; CHECK-NEXT: lu32i.d $a1, -524288 -; CHECK-NEXT: lu52i.d $a1, $a1, -1024 -; CHECK-NEXT: vreplgr2vr.d $vr3, $a1 -; CHECK-NEXT: vfmadd.d $vr2, $vr2, $vr1, $vr3 -; CHECK-NEXT: lu52i.d $a1, $zero, -1026 -; CHECK-NEXT: vreplgr2vr.d $vr4, $a1 -; CHECK-NEXT: vfmul.d $vr1, $vr1, $vr4 -; CHECK-NEXT: vfmul.d $vr1, $vr1, $vr2 -; CHECK-NEXT: vfmul.d $vr0, $vr0, $vr1 -; CHECK-NEXT: vfmadd.d $vr0, $vr0, $vr1, $vr3 -; CHECK-NEXT: vfmul.d $vr1, $vr1, $vr4 -; CHECK-NEXT: vfmul.d $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_div_sqrt_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vld $vr0, $a1, 0 +; LA32-NEXT: vfrsqrte.d $vr1, $vr0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0) +; LA32-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI1_0) +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_1) +; LA32-NEXT: vld $vr3, $a1, %pc_lo12(.LCPI1_1) +; LA32-NEXT: vfmul.d $vr1, $vr0, $vr1 +; LA32-NEXT: vfmul.d $vr4, $vr0, $vr1 +; LA32-NEXT: vfmadd.d $vr4, $vr4, $vr1, $vr2 +; LA32-NEXT: vfmul.d $vr1, $vr1, $vr3 +; LA32-NEXT: vfmul.d $vr1, $vr1, $vr4 +; LA32-NEXT: vfmul.d $vr0, $vr0, $vr1 +; LA32-NEXT: vfmadd.d $vr0, $vr0, $vr1, $vr2 +; LA32-NEXT: vfmul.d $vr1, $vr1, $vr3 +; LA32-NEXT: vfmul.d $vr0, $vr1, $vr0 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; FAULT-LA64-LABEL: one_div_sqrt_v2f64: +; FAULT-LA64: # %bb.0: # %entry +; FAULT-LA64-NEXT: vld $vr0, $a1, 0 +; FAULT-LA64-NEXT: vfrsqrt.d $vr0, $vr0 +; FAULT-LA64-NEXT: vst $vr0, $a0, 0 +; FAULT-LA64-NEXT: ret +; +; LA64-LABEL: one_div_sqrt_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vld $vr0, $a1, 0 +; LA64-NEXT: vfrsqrte.d $vr1, $vr0 +; LA64-NEXT: vfmul.d $vr1, $vr0, $vr1 +; LA64-NEXT: vfmul.d $vr2, $vr0, $vr1 +; LA64-NEXT: ori $a1, $zero, 0 +; LA64-NEXT: lu32i.d $a1, -524288 +; LA64-NEXT: lu52i.d $a1, $a1, -1024 +; LA64-NEXT: vreplgr2vr.d $vr3, $a1 +; LA64-NEXT: vfmadd.d $vr2, $vr2, $vr1, $vr3 +; LA64-NEXT: lu52i.d $a1, $zero, -1026 +; LA64-NEXT: vreplgr2vr.d $vr4, $a1 +; LA64-NEXT: vfmul.d $vr1, $vr1, $vr4 +; LA64-NEXT: vfmul.d $vr1, $vr1, $vr2 +; LA64-NEXT: vfmul.d $vr0, $vr0, $vr1 +; LA64-NEXT: vfmadd.d $vr0, $vr0, $vr1, $vr3 +; LA64-NEXT: vfmul.d $vr1, $vr1, $vr4 +; LA64-NEXT: vfmul.d $vr0, $vr1, $vr0 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <2 x double>, ptr %a0, align 16 %sqrt = call fast <2 x double> @llvm.sqrt.v2f64 (<2 x double> %v0) diff --git a/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll b/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll index a57bc1ca0e94..d88e0d1ea7c2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 ;; fsqrt define void @sqrt_v4f32(ptr %res, ptr %a0) nounwind { @@ -47,12 +48,22 @@ entry: } define void @one_div_sqrt_v2f64(ptr %res, ptr %a0) nounwind { -; CHECK-LABEL: one_div_sqrt_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vfrsqrt.d $vr0, $vr0 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_div_sqrt_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vld $vr0, $a1, 0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: vfsqrt.d $vr0, $vr0 +; LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: one_div_sqrt_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vld $vr0, $a1, 0 +; LA64-NEXT: vfrsqrt.d $vr0, $vr0 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <2 x double>, ptr %a0, align 16 %sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %v0) diff --git a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll index c46e624ddaa8..951ccbe4d08c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s define void @test_w() nounwind { ; CHECK-LABEL: test_w: diff --git a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll index ceea3621be2f..eacfca88fc74 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @register_vr1() nounwind { ; CHECK-LABEL: register_vr1: @@ -42,16 +43,27 @@ entry: ;; register which is preserved across calls. That's why the ;; fst.d and fld.d instructions are emitted. define void @register_vr31() nounwind { -; CHECK-LABEL: register_vr31: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi.d $sp, $sp, -16 -; CHECK-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill -; CHECK-NEXT: #APP -; CHECK-NEXT: vldi $vr31, 1 -; CHECK-NEXT: #NO_APP -; CHECK-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 16 -; CHECK-NEXT: ret +; LA32-LABEL: register_vr31: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill +; LA32-NEXT: #APP +; LA32-NEXT: vldi $vr31, 1 +; LA32-NEXT: #NO_APP +; LA32-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: register_vr31: +; LA64: # %bb.0: # %entry +; LA64-NEXT: addi.d $sp, $sp, -16 +; LA64-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill +; LA64-NEXT: #APP +; LA64-NEXT: vldi $vr31, 1 +; LA64-NEXT: #NO_APP +; LA64-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload +; LA64-NEXT: addi.d $sp, $sp, 16 +; LA64-NEXT: ret entry: %0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr31}"() ret void diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll index 811d9d712de4..0b3c559ef97d 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vabsd.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll index fac16c8308da..daaed8388bca 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll index 79be0a184bfb..c2d5264d5441 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vadda.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll index 6875872b6f83..a1fa4f3449b2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll index 87d32b3ce02a..19100bc1426c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll index b9134e0724fe..68ce36ccd801 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll index 086e3bec12d2..3951e121bdc6 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vaddwev.h.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll index 77496239c3a9..6fe22ea83b7d 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vand.v(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll index 82a117b2aba5..f36b2f39bc1e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vandi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll index c0c35c775266..43f60d9e56e4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vandi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll index 9a1c38a641d0..f6966213e32f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vandi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll index b08c759ecc32..2484051943c4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vandn.v(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll index fb0861f4cd5e..189e95ccb0c0 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vavg.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll index 8bf7d0ed8817..0675361263e2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vavgr.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll index b020806cd86c..3b968483dee8 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitclri.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll index df6cdb99cdbc..335dd66ba740 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitclri.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll index f5fba6dbb141..ac0eca2fc33e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <16 x i8> @llvm.loongarch.lsx.vbitclr.b(<16 x i8>, <16 x i8>) @@ -40,10 +41,21 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vbitclr.d(<2 x i64>, <2 x i64>) define <2 x i64> @lsx_vbitclr_d(<2 x i64> %va, <2 x i64> %vb) nounwind { -; CHECK-LABEL: lsx_vbitclr_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vbitclr.d $vr0, $vr0, $vr1 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vbitclr_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vrepli.d $vr2, 63 +; LA32-NEXT: vand.v $vr1, $vr1, $vr2 +; LA32-NEXT: vrepli.d $vr2, 1 +; LA32-NEXT: vsll.d $vr1, $vr2, $vr1 +; LA32-NEXT: vrepli.b $vr2, -1 +; LA32-NEXT: vxor.v $vr1, $vr1, $vr2 +; LA32-NEXT: vand.v $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vbitclr_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vbitclr.d $vr0, $vr0, $vr1 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vbitclr.d(<2 x i64> %va, <2 x i64> %vb) ret <2 x i64> %res @@ -88,10 +100,17 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vbitclri.d(<2 x i64>, i32) define <2 x i64> @lsx_vbitclri_d(<2 x i64> %va) nounwind { -; CHECK-LABEL: lsx_vbitclri_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vbitclri.d $vr0, $vr0, 63 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vbitclri_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0) +; LA32-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0) +; LA32-NEXT: vand.v $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vbitclri_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vbitclri.d $vr0, $vr0, 63 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vbitclri.d(<2 x i64> %va, i32 63) ret <2 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll index 24b6ec3284cb..a664bdebf642 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitrevi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll index 3ffb494c9907..379ba45863a9 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitrevi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll index ad56e88fdb88..ece12db99ce2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <16 x i8> @llvm.loongarch.lsx.vbitrev.b(<16 x i8>, <16 x i8>) @@ -40,10 +41,19 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vbitrev.d(<2 x i64>, <2 x i64>) define <2 x i64> @lsx_vbitrev_d(<2 x i64> %va, <2 x i64> %vb) nounwind { -; CHECK-LABEL: lsx_vbitrev_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vbitrev.d $vr0, $vr0, $vr1 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vbitrev_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vrepli.d $vr2, 63 +; LA32-NEXT: vand.v $vr1, $vr1, $vr2 +; LA32-NEXT: vrepli.d $vr2, 1 +; LA32-NEXT: vsll.d $vr1, $vr2, $vr1 +; LA32-NEXT: vxor.v $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vbitrev_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vbitrev.d $vr0, $vr0, $vr1 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vbitrev.d(<2 x i64> %va, <2 x i64> %vb) ret <2 x i64> %res @@ -88,10 +98,17 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vbitrevi.d(<2 x i64>, i32) define <2 x i64> @lsx_vbitrevi_d(<2 x i64> %va) nounwind { -; CHECK-LABEL: lsx_vbitrevi_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vbitrevi.d $vr0, $vr0, 63 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vbitrevi_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0) +; LA32-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0) +; LA32-NEXT: vxor.v $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vbitrevi_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vbitrevi.d $vr0, $vr0, 63 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vbitrevi.d(<2 x i64> %va, i32 63) ret <2 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll index 4b4b5ff1fc8c..23caf9c12836 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitsel.v(<16 x i8>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll index bc63b40e9fca..5fa9db3bd0ea 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitseli.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll index 52c1eb7d2024..05724df0a3dd 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitseli.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll index 28d342b5c378..93111bc86c2b 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitseli.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll index e57e14d8cb07..089c192b567a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitseti.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll index 9b2bde015ed9..182c46078505 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbitseti.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll index 75d98e6f8bce..b01e533a1c8b 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <16 x i8> @llvm.loongarch.lsx.vbitset.b(<16 x i8>, <16 x i8>) @@ -40,10 +41,19 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vbitset.d(<2 x i64>, <2 x i64>) define <2 x i64> @lsx_vbitset_d(<2 x i64> %va, <2 x i64> %vb) nounwind { -; CHECK-LABEL: lsx_vbitset_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vbitset.d $vr0, $vr0, $vr1 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vbitset_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vrepli.d $vr2, 63 +; LA32-NEXT: vand.v $vr1, $vr1, $vr2 +; LA32-NEXT: vrepli.d $vr2, 1 +; LA32-NEXT: vsll.d $vr1, $vr2, $vr1 +; LA32-NEXT: vor.v $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vbitset_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vbitset.d $vr0, $vr0, $vr1 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vbitset.d(<2 x i64> %va, <2 x i64> %vb) ret <2 x i64> %res @@ -88,10 +98,17 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vbitseti.d(<2 x i64>, i32) define <2 x i64> @lsx_vbitseti_d(<2 x i64> %va) nounwind { -; CHECK-LABEL: lsx_vbitseti_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vbitseti.d $vr0, $vr0, 63 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vbitseti_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0) +; LA32-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0) +; LA32-NEXT: vor.v $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vbitseti_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vbitseti.d $vr0, $vr0, 63 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vbitseti.d(<2 x i64> %va, i32 63) ret <2 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll index eb49af49c9be..84771bf4ea95 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbsll.v(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll index 5b10c9e91a4f..8a4fb0c9364c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbsll.v(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll index e7eb1cfcb407..5613b4dd0c7f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbsll.v(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll index bf56822e2ef5..8ff1a23c58d0 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbsrl.v(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll index 0bc038c869ce..89fb0c6b922a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbsrl.v(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll index fe0565297641..04b4894b6cff 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vbsrl.v(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll index c581109f3fd0..7f7f25c69013 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vclo.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll index 25c37b64349b..d205c171c091 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vclz.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll index 53166e84d269..04434d9fb014 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vdiv.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll index 2f3e891a9eef..93b08b2cfe00 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vexth.h.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll index cbf19e2a3919..c4c86f928e93 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <2 x i64> @llvm.loongarch.lsx.vextl.q.d(<2 x i64>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll index 7f94234ed603..9ef68997b4af 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll index e834002bb60b..aa0fa319c82e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll index 8f03a2b81291..895cffc07208 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll index 569002314c92..9d6c1cc22e8a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfadd.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll index 0c6682187101..aa35970017cb 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x i32> @llvm.loongarch.lsx.vfclass.s(<4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll index a6a151a96d84..4da977ca398d 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vfcvt.h.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll index a9e4328bd011..81897ecf5dea 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfcvth.s.h(<8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll index 9a69964bb227..0abbbe3dba13 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfcvtl.s.h(<8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll index 1ca8e5e2c0e9..4f39b2d5cee9 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfdiv.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll index 62fbcfa339cd..c3286a529898 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vffint.s.w(<4 x i32>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll index d8382acc70ed..d382b862b506 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vflogb.s(<4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll index adbaf6c76b1b..6f921a490ac3 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfmadd.s(<4 x float>, <4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll index 89f757c4e456..850170db39f2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfmax.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll index 5662acc0b9a1..3365841b804a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfmaxa.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll index 0f844240277f..da7e4d203c14 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfmin.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll index 27f70b5fba32..4fb1c5bfeb84 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfmina.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll index 856ca9cadbd9..090c1dd0d09c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfmsub.s(<4 x float>, <4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll index 1e6c4c77d536..50b335f17563 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfmul.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll index e1a9ea78ef9d..bdb7667e1962 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfnmadd.s(<4 x float>, <4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll index 46db0f4a5061..ac035b3bc7f1 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfnmsub.s(<4 x float>, <4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll index 669fde5912d4..db63deb618e6 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfrecip.s(<4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll index 8d872fc72962..ba40b6d8ceae 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfrintrne.s(<4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll index 326d87308b0b..9ddd45b5dd53 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfrsqrt.s(<4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll index 0184c855c9c1..8758478f4735 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vfrstpi.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll index 9583f672a305..164c0676b76c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vfrstpi.b(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll index 5c072b194d4f..dfe75b2181a0 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vfrstp.b(<16 x i8>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll index 55bffba9e99e..f8d0713dad08 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfsqrt.s(<4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll index 2beba4a70dc9..cc0f88d9d32c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x float> @llvm.loongarch.lsx.vfsub.s(<4 x float>, <4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll index 2a494cd7fa87..1024ee34715a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x i32> @llvm.loongarch.lsx.vftintrne.w.s(<4 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll index 05725582334a..349c2ddccf3b 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vhaddw.h.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll index dd5815b2ea85..039f5994bfba 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vhsubw.h.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll index 77b0b3484df8..0c731f45f7ea 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vilvl.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll index 3d4f84fb6e03..4ba83bc5cb66 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll index 2a4c2218de8c..3633ba0a2d91 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll index 61d2cbd28066..8ededfd38d1f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32) @@ -43,11 +44,18 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64>, i64, i32) define <2 x i64> @lsx_vinsgr2vr_d(<2 x i64> %va) nounwind { -; CHECK-LABEL: lsx_vinsgr2vr_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ori $a0, $zero, 1 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vinsgr2vr_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ori $a0, $zero, 1 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2 +; LA32-NEXT: vinsgr2vr.w $vr0, $zero, 3 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vinsgr2vr_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ori $a0, $zero, 1 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 1 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64> %va, i64 1, i32 1) ret <2 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll index 9375f9f01a92..de2189a8e892 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vld(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll index f8b4c42326df..be7365d0ee5a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vld(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll index 57f6f8e81d91..106b8e6e6dfd 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <2 x i64> @llvm.loongarch.lsx.vldi(i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll index a8f8278f8097..2f4a577f36c3 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <2 x i64> @llvm.loongarch.lsx.vldi(i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll index ace910b54d9a..582b49a74cb4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <2 x i64> @llvm.loongarch.lsx.vldi(i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll index 34bf945c9df4..f0dd80063189 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vldrepl.b(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll index 9613c1a62540..8f8f0aeade05 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vldrepl.b(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll index 9ebe0c2fccd5..74f20745a3d0 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vldrepl.b(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll index 89503724fd73..14634fe8daec 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmadd.b(<16 x i8>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll index 1e3ab25a5fcf..58ee70aacae9 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.b(<8 x i16>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll index 34bbe3495670..6c7a0657940e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmaxi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll index 4dd289cf6ed7..caea2e0d6818 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmax.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll index 5d9b98cec4d0..444220f87039 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmini.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll index aa12a5ead6a3..fa26a5bc430d 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmin.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll index 6b3dc6865584..46630562c84f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmod.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll index 3ecd777aee67..8bc4c572e728 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmskgez.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll index be00c76137c7..9e36cc77080a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmskltz.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll index 02f1752f7190..a47f0303db27 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmsknz.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll index 98684e10c78e..1b7ae48b44ad 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmsub.b(<16 x i8>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll index a4deb8f8f823..ce584fe9ed0c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmuh.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll index aca60d1663b7..46f6f0919571 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vmul.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll index eb55c1f809e3..74358585a444 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vmulwev.h.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll index 43c6e9757614..2e6dbdbc99b1 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vneg.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll index 16619225f2d1..2bf21fb2dc31 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vnor.v(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll index 8c59d8fb9fa5..e82f9c78f2ab 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vnori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll index 322a39c106a6..0dd3accc8e5e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vnori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll index c2388a1e0da3..0777fab45d09 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vnori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll index ab557003d150..40b4549d1b58 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vor.v(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll index 4a7fc7e109d9..612fecfd239e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll index 5644b8581dce..d8b78e71fcb4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll index 85c0f432c54a..71bd9f03feea 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll index 4528628e02c3..8974703ba6e1 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vorn.v(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll index 70a3620d1757..42d614250684 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vpackev.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll index 431b270ab0a1..177d732604af 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vpcnt.b(<16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll index e439bbae6130..f719c5cf30e7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <4 x i32> @llvm.loongarch.lsx.vpermi.w(<4 x i32>, <4 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll index bdfc08ed680a..e41d74ef2dae 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <4 x i32> @llvm.loongarch.lsx.vpermi.w(<4 x i32>, <4 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll index b8367d98caf6..ccad1b7a8250 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <4 x i32> @llvm.loongarch.lsx.vpermi.w(<4 x i32>, <4 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll index 4ebf29e1409c..d75889965f39 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vpickev.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll index 6dd3c1f27a81..707334640771 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare i32 @llvm.loongarch.lsx.vpickve2gr.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll index 3ba184dad052..35fd8d644700 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vreplve.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll index d625441122a6..7fdc8fe8c690 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll index 3d271bb2b307..e7f8a0708ad1 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll index 9b8af1878cb8..216c2ae52844 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll index 3c53b36672ad..6e0b6e6e4f3e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vrotri.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll index fd8ba3a1c633..b7cc04338576 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vrotri.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll index df8650677147..5ee7b2642999 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vrotr.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll index a54f955766df..82149a263bd7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsadd.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll index 45fa4e43be19..9b15c0538200 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsat.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll index afdbe0c1ce0b..ce99366ee5f8 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsat.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll index 4286842a63b9..3412b878eed4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsat.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll index 220398ff28cd..304894dbf410 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vseqi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll index 5fa1dd30475c..82db51ada1c2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vseqi.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll index 3cb4acd82439..ac946cacc63a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vseq.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll index f5d516521e45..5deca45044cc 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vshuf.b(<16 x i8>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll index 4d6fadf08c26..9d7f2729c0f2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vshuf4i.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll index a7d138bcc00b..b5518763975e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vshuf4i.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll index 1ad5f2af5591..3cb712fd07fa 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vshuf4i.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll index 3997b0cc995c..46f18670e0df 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsigncov.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll index 4c945e296711..39787b3d0f5b 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vslei.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll index 0fc137bf0549..0feb967068cb 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vslei.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll index 5a9d5f06e63f..8a225a31f9da 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsle.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll index 75406f94887c..6a5b11196cae 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vslli.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll index 7474b5e29734..ce005d097fa7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vslli.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll index 7bc20af41f17..d1316e04efbb 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <16 x i8> @llvm.loongarch.lsx.vsll.b(<16 x i8>, <16 x i8>) @@ -40,10 +41,17 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vsll.d(<2 x i64>, <2 x i64>) define <2 x i64> @lsx_vsll_d(<2 x i64> %va, <2 x i64> %vb) nounwind { -; CHECK-LABEL: lsx_vsll_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsll.d $vr0, $vr0, $vr1 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vsll_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vrepli.d $vr2, 63 +; LA32-NEXT: vand.v $vr1, $vr1, $vr2 +; LA32-NEXT: vsll.d $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vsll_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vsll.d $vr0, $vr0, $vr1 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vsll.d(<2 x i64> %va, <2 x i64> %vb) ret <2 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll index bda3523a0b5c..74e65742cfa8 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll index a03656d5ca07..51921e7e6b43 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll index 29ab70da1ced..65f1f6b49c81 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll index f6d014b19d6c..e585f370b7f0 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vslti.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll index 9a8b757dab4e..e42215291f25 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vslti.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll index 18683e9dc46f..a0eb870ba9ad 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vslt.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll index 2a033a21b565..cacb7d7c6448 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrai.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll index c3b328145864..f3bfe73911b4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrai.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll index e85c8464c18e..14c3801a8040 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <16 x i8> @llvm.loongarch.lsx.vsra.b(<16 x i8>, <16 x i8>) @@ -40,10 +41,17 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vsra.d(<2 x i64>, <2 x i64>) define <2 x i64> @lsx_vsra_d(<2 x i64> %va, <2 x i64> %vb) nounwind { -; CHECK-LABEL: lsx_vsra_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsra.d $vr0, $vr0, $vr1 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vsra_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vrepli.d $vr2, 63 +; LA32-NEXT: vand.v $vr1, $vr1, $vr2 +; LA32-NEXT: vsra.d $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vsra_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vsra.d $vr0, $vr0, $vr1 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vsra.d(<2 x i64> %va, <2 x i64> %vb) ret <2 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll index 4ffe5a704c2c..4cb38b4612f7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsran.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll index d68064e9b902..bd0cdb79d918 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll index 38cfde214dc1..8a501434b1d2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll index 717c641616c8..7e2a9e107f4a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll index b6c2d70cebbc..a8f59a58a0c4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrari.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll index 2ad8adcd823b..f2122054ae4d 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrari.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll index 8b52b7ac9631..40aa39e89bf1 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrar.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll index d4cdfb5359ea..c952fae87719 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrarn.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll index d24cf92a0392..5e4d9f94b385 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrarni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll index 19de7445cba1..15ac105abd76 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrarni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll index 2253e88372fc..af3ce7722e46 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrarni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll index 3beff790afab..0d1b8906e655 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrli.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll index 98652aca0d62..9c32772c0aba 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrli.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll index 1cddd9622233..9499a0ab445e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <16 x i8> @llvm.loongarch.lsx.vsrl.b(<16 x i8>, <16 x i8>) @@ -40,10 +41,17 @@ entry: declare <2 x i64> @llvm.loongarch.lsx.vsrl.d(<2 x i64>, <2 x i64>) define <2 x i64> @lsx_vsrl_d(<2 x i64> %va, <2 x i64> %vb) nounwind { -; CHECK-LABEL: lsx_vsrl_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsrl.d $vr0, $vr0, $vr1 -; CHECK-NEXT: ret +; LA32-LABEL: lsx_vsrl_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vrepli.d $vr2, 63 +; LA32-NEXT: vand.v $vr1, $vr1, $vr2 +; LA32-NEXT: vsrl.d $vr0, $vr0, $vr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lsx_vsrl_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vsrl.d $vr0, $vr0, $vr1 +; LA64-NEXT: ret entry: %res = call <2 x i64> @llvm.loongarch.lsx.vsrl.d(<2 x i64> %va, <2 x i64> %vb) ret <2 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll index 1c9b23243ffb..7a86688e43f4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrln.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll index 054c4f393548..366effc2e7c6 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll index 76341df197fd..d3f5cc07966e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll index 6e523efa1824..e8d06e7e8bc6 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll index bcbd38e26e5f..6b557dfbada3 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlri.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll index 4862b1546ccf..c0ba458cb2f5 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlri.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll index 51638fa1a47f..0d479951a57a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlr.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll index 893e51396241..9563b9459788 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlrn.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll index 8988ae88f9eb..e4085b52bbf8 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlrni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll index e5530db56fed..51488926f92c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlrni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll index d1ea450d2237..3db7e3f3e571 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsrlrni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll index cecccbb730c9..96493d555da6 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssran.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll index f7817921ebeb..bf185ae5d974 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrani.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll index a80ede9c5243..a4f0a4ed9319 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrani.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll index 57b8eb169866..75577dbafb1c 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrani.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll index c6b7d9ec8e1d..5ad63f2bd0ab 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrarn.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll index 4edda8c0a24a..f54bb71881c4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrarni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll index a77e6e764c9d..00cfc60b4314 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrarni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll index 1a2e91962ac3..af32b58b53f8 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrarni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll index 697ccc3962a8..6fb1a3b15860 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrln.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll index 6218af1fa773..4fb4b307a706 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrlni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll index 688be826f467..2c8356ed0a60 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrlni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll index 8dd41e7abe87..deb1575bedcc 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrlni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll index a8e76cbaa7fd..a17ab94d02ca 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrlrn.b.h(<8 x i16>, <8 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll index 98a0c5b3cd28..61e85be08c0a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrlrni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll index c389b4fd6023..f4450f25274e 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrlrni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll index 869e81b2b09d..840fafc038fc 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssrlrni.b.h(<16 x i8>, <16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll index c594b426d650..ac0ef538cdcb 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vssub.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll index a72126cd15a6..079fba79b350 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lsx.vst(<16 x i8>, ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll index ba9f44c59c37..aae751c17497 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lsx.vst(<16 x i8>, ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll index 82dba30ed1e7..7f3c343dd5bf 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lsx.vstelm.b(<16 x i8>, ptr, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll index a8a74819c204..feb8fbaf2952 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lsx.vstelm.b(<16 x i8>, ptr, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll index 4f8412be9579..9b6af6fc1a96 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare void @llvm.loongarch.lsx.vstelm.b(<16 x i8>, ptr, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll index 5c04a3d8de0d..8f1b441e92fe 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsub.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll index 96cc1241fbf3..fc1c9e110876 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll index 162f9ad131c7..68b59ca9c02f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll index 304a4e4a78cc..46642171aaa1 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll index 48100db74334..f41a3a1b99fd 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <8 x i16> @llvm.loongarch.lsx.vsubwev.h.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll index 72a1fe93c2c0..5a49605f5fa5 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vxor.v(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll index 5f5613189ac8..a3e3fa9dfa03 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vxori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll index 4238d89120f1..d0a6df6bc78a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vxori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll index 09669cd5ac14..7241bfbfcedd 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s declare <16 x i8> @llvm.loongarch.lsx.vxori.b(<16 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll index f77a31b60076..6546719647f3 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc -mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s ;; 1. trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b) or abdu(a,b) diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll index 485bd1df8d66..41164b635983 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @add_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll index d3e4efb1b1c2..2d6f0bea0712 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @and_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll index 2a3107447098..3a099cb18d37 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @ashr_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll index 9a40feb45671..514a5527e829 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll @@ -1,11 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefix=LA64 define i32 @bitcast_extract_v4f32(<4 x float> %a) nounwind { -; CHECK-LABEL: bitcast_extract_v4f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3 -; CHECK-NEXT: ret +; LA32-LABEL: bitcast_extract_v4f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vreplvei.w $vr0, $vr0, 3 +; LA32-NEXT: movfr2gr.s $a0, $fa0 +; LA32-NEXT: ret +; +; LA64-LABEL: bitcast_extract_v4f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vpickve2gr.w $a0, $vr0, 3 +; LA64-NEXT: ret entry: %b = extractelement <4 x float> %a, i32 3 %c = bitcast float %b to i32 @@ -13,10 +20,17 @@ entry: } define i64 @bitcast_extract_v2f64(<2 x double> %a) nounwind { -; CHECK-LABEL: bitcast_extract_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vpickve2gr.d $a0, $vr0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: bitcast_extract_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vreplvei.d $vr0, $vr0, 1 +; LA32-NEXT: movfr2gr.s $a0, $fa0 +; LA32-NEXT: movfrh2gr.s $a1, $fa0 +; LA32-NEXT: ret +; +; LA64-LABEL: bitcast_extract_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vpickve2gr.d $a0, $vr0, 1 +; LA64-NEXT: ret entry: %b = extractelement <2 x double> %a, i32 1 %c = bitcast double %b to i64 diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll index 989ad10a44ff..c0f010a93662 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @fadd_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll index 95e46a4e71da..9a1498f55582 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s ;; TREU diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll index 3b9642e31b02..603bd21ab9af 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: fdiv_v4f32: @@ -49,12 +50,21 @@ entry: } define void @one_fdiv_v2f64(ptr %res, ptr %a0) nounwind { -; CHECK-LABEL: one_fdiv_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vfrecip.d $vr0, $vr0 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_fdiv_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vld $vr0, $a1, 0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: one_fdiv_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vld $vr0, $a1, 0 +; LA64-NEXT: vfrecip.d $vr0, $vr0 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <2 x double>, ptr %a0 %div = fdiv <2 x double> <double 1.0, double 1.0>, %v0 diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll index f604a8962958..faf461c67781 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @fmul_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll index 795c1ac8b368..007634d28d17 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @fneg_v4f32(ptr %res, ptr %a0) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll index c3008fe96e47..7ea6d7431670 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @fptosi_v4f32_v4i32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll index f0aeb0bd14e7..ec3a86713ed2 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @fptoui_v4f32_v4i32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll index 02350c0763ba..f7fe458f353f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @fsub_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll index 04b4831f1188..7166469bf5ce 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s ;; SETEQ diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll index c42e3013c113..e7e0a89a8958 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll @@ -1,11 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefix=LA64 define <4 x float> @insert_bitcast_v4f32(<4 x float> %a, i32 %b) nounwind { -; CHECK-LABEL: insert_bitcast_v4f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: insert_bitcast_v4f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: movgr2fr.w $fa1, $a0 +; LA32-NEXT: vextrins.w $vr0, $vr1, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: insert_bitcast_v4f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA64-NEXT: ret entry: %c = bitcast i32 %b to float %d = insertelement <4 x float> %a, float %c, i32 1 @@ -13,10 +20,17 @@ entry: } define <2 x double> @insert_bitcast_v2f64(<2 x double> %a, i64 %b) nounwind { -; CHECK-LABEL: insert_bitcast_v2f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: insert_bitcast_v2f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: movgr2fr.w $fa1, $a0 +; LA32-NEXT: movgr2frh.w $fa1, $a1 +; LA32-NEXT: vextrins.d $vr0, $vr1, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: insert_bitcast_v2f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 1 +; LA64-NEXT: ret entry: %c = bitcast i64 %b to double %d = insertelement <2 x double> %a, double %c, i32 1 diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll index e9a0c8a11045..65aff8071897 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define <16 x i8> @insert_extract_v16i8(<16 x i8> %a) nounwind { ; CHECK-LABEL: insert_extract_v16i8: @@ -46,10 +47,18 @@ entry: } define <2 x i64> @insert_extract_v2i64(<2 x i64> %a) nounwind { -; CHECK-LABEL: insert_extract_v2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextrins.d $vr0, $vr0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: insert_extract_v2i64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vori.b $vr1, $vr0, 0 +; LA32-NEXT: vextrins.w $vr1, $vr0, 2 +; LA32-NEXT: vextrins.w $vr1, $vr0, 19 +; LA32-NEXT: vori.b $vr0, $vr1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: insert_extract_v2i64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vextrins.d $vr0, $vr0, 1 +; LA64-NEXT: ret entry: %b = extractelement <2 x i64> %a, i32 1 %c = insertelement <2 x i64> %a, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll index 2693310b4f50..584b202691c7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @lshr_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll index f66cae6a1802..efe85fb13e69 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @mul_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll index 89702e60c01f..94a129438457 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @or_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll index cdff58defdae..c5dfe231b686 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @sdiv_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll index 4b34c04f3374..1d8ed9ec7e90 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @shl_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll index 31398c6081c0..076395e56e81 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s ;; vilvl.b diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll index 171e68306cd1..4034773a8a1f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s ;; vpackev.b diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll index ca636d942b58..c6d6019517be 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s ;; vpickev.b diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll index 1e820a37a240..37eb9e7e8dc4 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @sitofp_v4i32_v4f32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll index 2813d9c97e68..ab135faa6ee3 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @sub_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll index 32dac67d36a8..65a4075cf359 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @udiv_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll index 3d4913f12e57..3ae1119435ef 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @uitofp_v4i32_v4f32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll index 482cecb1d752..fd63b2122a8b 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @xor_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/mulh.ll b/llvm/test/CodeGen/LoongArch/lsx/mulh.ll index b0ca556eeff3..687b3040f5e7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/mulh.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/mulh.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define void @mulhs_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll index ba8ffc349318..f359b44cec4a 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define <4 x i32> @xor_shl_splat_vec_one(i32 %x, <4 x i32> %y) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll index 87b68ac59172..d2a506dd9854 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 ;; Test scalar_to_vector expansion. @@ -31,10 +32,16 @@ define <4 x i32> @scalar_to_4xi32(i32 %val) { } define <2 x i64> @scalar_to_2xi64(i64 %val) { -; CHECK-LABEL: scalar_to_2xi64: -; CHECK: # %bb.0: -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: scalar_to_2xi64: +; LA32: # %bb.0: +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1 +; LA32-NEXT: ret +; +; LA64-LABEL: scalar_to_2xi64: +; LA64: # %bb.0: +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: ret %ret = insertelement <2 x i64> poison, i64 %val, i32 0 ret <2 x i64> %ret } diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll index a71bdea917cb..57fd09ed2e09 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll @@ -5,15 +5,12 @@ define void @vec_reduce_add_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vadd.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 +; CHECK-NEXT: vhaddw.h.b $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.w.h $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.d.w $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.q.d $vr0, $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.d $a0, $vr0, 0 +; CHECK-NEXT: st.b $a0, $a1, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %v) @@ -21,17 +18,62 @@ define void @vec_reduce_add_v16i8(ptr %src, ptr %dst) nounwind { ret void } +define void @vec_reduce_add_v8i8(ptr %src, ptr %dst) nounwind { +; CHECK-LABEL: vec_reduce_add_v8i8: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.d $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; CHECK-NEXT: vhaddw.h.b $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.w.h $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.d.w $vr0, $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0 +; CHECK-NEXT: st.b $a0, $a1, 0 +; CHECK-NEXT: ret + %v = load <8 x i8>, ptr %src + %res = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %v) + store i8 %res, ptr %dst + ret void +} + +define void @vec_reduce_add_v4i8(ptr %src, ptr %dst) nounwind { +; CHECK-LABEL: vec_reduce_add_v4i8: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 +; CHECK-NEXT: vhaddw.h.b $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.w.h $vr0, $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0 +; CHECK-NEXT: st.b $a0, $a1, 0 +; CHECK-NEXT: ret + %v = load <4 x i8>, ptr %src + %res = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %v) + store i8 %res, ptr %dst + ret void +} + +define void @vec_reduce_add_v2i8(ptr %src, ptr %dst) nounwind { +; CHECK-LABEL: vec_reduce_add_v2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.h $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 +; CHECK-NEXT: vhaddw.h.b $vr0, $vr0, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 +; CHECK-NEXT: ret + %v = load <2 x i8>, ptr %src + %res = call i8 @llvm.vector.reduce.add.v2i8(<2 x i8> %v) + store i8 %res, ptr %dst + ret void +} + define void @vec_reduce_add_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vadd.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 +; CHECK-NEXT: vhaddw.w.h $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.d.w $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.q.d $vr0, $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.d $a0, $vr0, 0 +; CHECK-NEXT: st.h $a0, $a1, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %v) @@ -39,15 +81,44 @@ define void @vec_reduce_add_v8i16(ptr %src, ptr %dst) nounwind { ret void } +define void @vec_reduce_add_v4i16(ptr %src, ptr %dst) nounwind { +; CHECK-LABEL: vec_reduce_add_v4i16: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.d $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; CHECK-NEXT: vhaddw.w.h $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.d.w $vr0, $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0 +; CHECK-NEXT: st.h $a0, $a1, 0 +; CHECK-NEXT: ret + %v = load <4 x i16>, ptr %src + %res = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %v) + store i16 %res, ptr %dst + ret void +} + +define void @vec_reduce_add_v2i16(ptr %src, ptr %dst) nounwind { +; CHECK-LABEL: vec_reduce_add_v2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 +; CHECK-NEXT: vhaddw.w.h $vr0, $vr0, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 +; CHECK-NEXT: ret + %v = load <2 x i16>, ptr %src + %res = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> %v) + store i16 %res, ptr %dst + ret void +} + define void @vec_reduce_add_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vadd.w $vr0, $vr0, $vr1 -; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 +; CHECK-NEXT: vhaddw.d.w $vr0, $vr0, $vr0 +; CHECK-NEXT: vhaddw.q.d $vr0, $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.d $a0, $vr0, 0 +; CHECK-NEXT: st.w $a0, $a1, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v) @@ -55,12 +126,25 @@ define void @vec_reduce_add_v4i32(ptr %src, ptr %dst) nounwind { ret void } +define void @vec_reduce_add_v2i32(ptr %src, ptr %dst) nounwind { +; CHECK-LABEL: vec_reduce_add_v2i32: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.d $a0, $a0, 0 +; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; CHECK-NEXT: vhaddw.d.w $vr0, $vr0, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 +; CHECK-NEXT: ret + %v = load <2 x i32>, ptr %src + %res = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %v) + store i32 %res, ptr %dst + ret void +} + define void @vec_reduce_add_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vadd.d $vr0, $vr0, $vr1 +; CHECK-NEXT: vhaddw.q.d $vr0, $vr0, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll index c16de1023964..cca4ce30758f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll @@ -6,13 +6,13 @@ define void @vec_reduce_and_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src @@ -26,12 +26,12 @@ define void @vec_reduce_and_v8i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i8>, ptr %src @@ -45,10 +45,10 @@ define void @vec_reduce_and_v4i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i8>, ptr %src @@ -62,8 +62,8 @@ define void @vec_reduce_and_v2i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.h $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i8>, ptr %src @@ -77,11 +77,11 @@ define void @vec_reduce_and_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src @@ -95,10 +95,10 @@ define void @vec_reduce_and_v4i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i16>, ptr %src @@ -112,8 +112,8 @@ define void @vec_reduce_and_v2i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i16>, ptr %src @@ -126,10 +126,10 @@ define void @vec_reduce_and_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_and_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src @@ -143,8 +143,8 @@ define void @vec_reduce_and_v2i32(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i32>, ptr %src @@ -157,8 +157,8 @@ define void @vec_reduce_and_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_and_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll index 52f18cce611d..ce431f0cf6a7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll @@ -6,13 +6,13 @@ define void @vec_reduce_or_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src @@ -26,12 +26,12 @@ define void @vec_reduce_or_v8i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i8>, ptr %src @@ -45,10 +45,10 @@ define void @vec_reduce_or_v4i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i8>, ptr %src @@ -62,8 +62,8 @@ define void @vec_reduce_or_v2i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.h $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i8>, ptr %src @@ -77,11 +77,11 @@ define void @vec_reduce_or_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src @@ -95,10 +95,10 @@ define void @vec_reduce_or_v4i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i16>, ptr %src @@ -112,8 +112,8 @@ define void @vec_reduce_or_v2i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i16>, ptr %src @@ -126,10 +126,10 @@ define void @vec_reduce_or_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_or_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src @@ -143,8 +143,8 @@ define void @vec_reduce_or_v2i32(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i32>, ptr %src @@ -157,8 +157,8 @@ define void @vec_reduce_or_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_or_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll index 5d8c3e36549d..bdf153ad7794 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll @@ -6,13 +6,13 @@ define void @vec_reduce_smax_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src @@ -26,12 +26,12 @@ define void @vec_reduce_smax_v8i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i8>, ptr %src @@ -45,10 +45,10 @@ define void @vec_reduce_smax_v4i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i8>, ptr %src @@ -62,8 +62,8 @@ define void @vec_reduce_smax_v2i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.h $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i8>, ptr %src @@ -77,11 +77,11 @@ define void @vec_reduce_smax_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src @@ -95,10 +95,10 @@ define void @vec_reduce_smax_v4i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i16>, ptr %src @@ -112,8 +112,8 @@ define void @vec_reduce_smax_v2i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i16>, ptr %src @@ -126,10 +126,10 @@ define void @vec_reduce_smax_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smax_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.w $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src @@ -143,8 +143,8 @@ define void @vec_reduce_smax_v2i32(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.w $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i32>, ptr %src @@ -157,8 +157,8 @@ define void @vec_reduce_smax_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smax_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vmax.d $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.d $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll index 2d53095db89d..e3b3c5e6f241 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll @@ -6,13 +6,13 @@ define void @vec_reduce_smin_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src @@ -26,12 +26,12 @@ define void @vec_reduce_smin_v8i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i8>, ptr %src @@ -45,10 +45,10 @@ define void @vec_reduce_smin_v4i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i8>, ptr %src @@ -62,8 +62,8 @@ define void @vec_reduce_smin_v2i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.h $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i8>, ptr %src @@ -77,11 +77,11 @@ define void @vec_reduce_smin_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src @@ -95,10 +95,10 @@ define void @vec_reduce_smin_v4i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i16>, ptr %src @@ -112,8 +112,8 @@ define void @vec_reduce_smin_v2i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i16>, ptr %src @@ -126,10 +126,10 @@ define void @vec_reduce_smin_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smin_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.w $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src @@ -143,8 +143,8 @@ define void @vec_reduce_smin_v2i32(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.w $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i32>, ptr %src @@ -157,8 +157,8 @@ define void @vec_reduce_smin_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smin_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vmin.d $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.d $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll index abe9ba7dfb24..fff2304befd6 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll @@ -6,13 +6,13 @@ define void @vec_reduce_umax_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src @@ -26,12 +26,12 @@ define void @vec_reduce_umax_v8i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i8>, ptr %src @@ -45,10 +45,10 @@ define void @vec_reduce_umax_v4i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i8>, ptr %src @@ -62,8 +62,8 @@ define void @vec_reduce_umax_v2i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.h $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i8>, ptr %src @@ -77,11 +77,11 @@ define void @vec_reduce_umax_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src @@ -95,10 +95,10 @@ define void @vec_reduce_umax_v4i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i16>, ptr %src @@ -112,8 +112,8 @@ define void @vec_reduce_umax_v2i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i16>, ptr %src @@ -126,10 +126,10 @@ define void @vec_reduce_umax_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umax_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.wu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.wu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src @@ -143,8 +143,8 @@ define void @vec_reduce_umax_v2i32(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.wu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i32>, ptr %src @@ -157,8 +157,8 @@ define void @vec_reduce_umax_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umax_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vmax.du $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.du $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll index 3d396f3692e7..e14a294cbcfb 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll @@ -6,13 +6,13 @@ define void @vec_reduce_umin_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src @@ -26,12 +26,12 @@ define void @vec_reduce_umin_v8i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i8>, ptr %src @@ -45,10 +45,10 @@ define void @vec_reduce_umin_v4i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i8>, ptr %src @@ -62,8 +62,8 @@ define void @vec_reduce_umin_v2i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.h $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i8>, ptr %src @@ -77,11 +77,11 @@ define void @vec_reduce_umin_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src @@ -95,10 +95,10 @@ define void @vec_reduce_umin_v4i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i16>, ptr %src @@ -112,8 +112,8 @@ define void @vec_reduce_umin_v2i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i16>, ptr %src @@ -126,10 +126,10 @@ define void @vec_reduce_umin_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umin_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.wu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.wu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src @@ -143,8 +143,8 @@ define void @vec_reduce_umin_v2i32(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.wu $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i32>, ptr %src @@ -157,8 +157,8 @@ define void @vec_reduce_umin_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umin_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vmin.du $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.du $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll index 1894532d6121..ae2bb8f91de0 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll @@ -6,13 +6,13 @@ define void @vec_reduce_xor_v16i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i8>, ptr %src @@ -26,12 +26,12 @@ define void @vec_reduce_xor_v8i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vsrli.d $vr1, $vr0, 32 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i8>, ptr %src @@ -45,10 +45,10 @@ define void @vec_reduce_xor_v4i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.b $vr1, $vr0, 14 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i8>, ptr %src @@ -62,8 +62,8 @@ define void @vec_reduce_xor_v2i8(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.h $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.b $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i8>, ptr %src @@ -77,11 +77,11 @@ define void @vec_reduce_xor_v8i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i16>, ptr %src @@ -95,10 +95,10 @@ define void @vec_reduce_xor_v4i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.h $vr1, $vr0, 14 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i16>, ptr %src @@ -112,8 +112,8 @@ define void @vec_reduce_xor_v2i16(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.w $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.h $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i16>, ptr %src @@ -126,10 +126,10 @@ define void @vec_reduce_xor_v4i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_xor_v4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vshuf4i.w $vr1, $vr0, 14 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i32>, ptr %src @@ -143,8 +143,8 @@ define void @vec_reduce_xor_v2i32(ptr %src, ptr %dst) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: ld.d $a0, $a0, 0 ; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.w $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i32>, ptr %src @@ -157,8 +157,8 @@ define void @vec_reduce_xor_v2i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_xor_v2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vld $vr0, $a0, 0 -; CHECK-NEXT: vreplvei.d $vr1, $vr0, 1 -; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 ; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <2 x i64>, ptr %src diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll index 48f18a35a38c..efb6b8632f95 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s define <16 x i8> @shuffle_to_vslli_h_8(<16 x i8> %a) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll index 7e9f5b653d01..5e0ff9a07585 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @shuffle_sign_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind { ; CHECK-LABEL: shuffle_sign_ext_2i8_to_2i64: @@ -37,14 +38,24 @@ define void @shuffle_sign_ext_2i16_to_2i64(ptr %ptr, ptr %dst) nounwind { } define void @shuffle_sign_ext_2i32_to_2i64(ptr %ptr, ptr %dst) nounwind { -; CHECK-LABEL: shuffle_sign_ext_2i32_to_2i64: -; CHECK: # %bb.0: -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vrepli.b $vr1, 0 -; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: shuffle_sign_ext_2i32_to_2i64: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vrepli.b $vr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2 +; LA32-NEXT: vst $vr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: shuffle_sign_ext_2i32_to_2i64: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 0 +; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0 +; LA64-NEXT: vst $vr0, $a1, 0 +; LA64-NEXT: ret %x = load <2 x i32>, ptr %ptr %y = shufflevector <2 x i32> %x, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 3, i32 1, i32 2> %r = bitcast <4 x i32> %y to <2 x i64> @@ -70,14 +81,25 @@ define void @shuffle_sign_ext_4i8_to_4i32(ptr %ptr, ptr %dst) nounwind { } define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind { -; CHECK-LABEL: shuffle_sign_ext_4i16_to_4i32: -; CHECK: # %bb.0: -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vrepli.b $vr1, 0 -; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: shuffle_sign_ext_4i16_to_4i32: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.b $vr1, 0 +; LA32-NEXT: vilvl.h $vr0, $vr1, $vr0 +; LA32-NEXT: vst $vr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: shuffle_sign_ext_4i16_to_4i32: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 0 +; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0 +; LA64-NEXT: vst $vr0, $a1, 0 +; LA64-NEXT: ret %x = load <4 x i16>, ptr %ptr %y = shufflevector <4 x i16> %x, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 7, i32 1, i32 6, i32 2, i32 5, i32 3, i32 4> %r = bitcast <8 x i16> %y to <4 x i32> @@ -86,14 +108,25 @@ define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind { } define void @shuffle_sign_ext_8i8_to_8i16(ptr %ptr, ptr %dst) nounwind { -; CHECK-LABEL: shuffle_sign_ext_8i8_to_8i16: -; CHECK: # %bb.0: -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vrepli.b $vr1, 0 -; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: shuffle_sign_ext_8i8_to_8i16: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.b $vr1, 0 +; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0 +; LA32-NEXT: vst $vr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: shuffle_sign_ext_8i8_to_8i16: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 0 +; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0 +; LA64-NEXT: vst $vr0, $a1, 0 +; LA64-NEXT: ret %x = load <8 x i8>, ptr %ptr %y = shufflevector <8 x i8> %x, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 15, i32 1, i32 14, i32 2, i32 13, i32 3, i32 12, i32 4, i32 11, i32 5, i32 10, i32 6, i32 9, i32 7, i32 8> %r = bitcast <16 x i8> %y to <8 x i16> diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll index bbcfbe1b0726..602c0f1a5a91 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64 define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) { @@ -38,14 +39,25 @@ entry: } define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) { -; CHECK-LABEL: load_zext_8i8_to_8i16: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vrepli.b $vr1, 0 -; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: load_zext_8i8_to_8i16: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.b $vr1, 0 +; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0 +; LA32-NEXT: vst $vr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: load_zext_8i8_to_8i16: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 0 +; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0 +; LA64-NEXT: vst $vr0, $a1, 0 +; LA64-NEXT: ret entry: %A = load <8 x i8>, ptr %ptr %B = zext <8 x i8> %A to <8 x i16> @@ -71,14 +83,25 @@ entry: } define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) { -; CHECK-LABEL: load_zext_4i16_to_4i32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vrepli.b $vr1, 0 -; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: load_zext_4i16_to_4i32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1 +; LA32-NEXT: vrepli.b $vr1, 0 +; LA32-NEXT: vilvl.h $vr0, $vr1, $vr0 +; LA32-NEXT: vst $vr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: load_zext_4i16_to_4i32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 0 +; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0 +; LA64-NEXT: vst $vr0, $a1, 0 +; LA64-NEXT: ret entry: %A = load <4 x i16>, ptr %ptr %B = zext <4 x i16> %A to <4 x i32> @@ -87,14 +110,24 @@ entry: } define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) { -; CHECK-LABEL: load_zext_2i32_to_2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0 -; CHECK-NEXT: vrepli.b $vr1, 0 -; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0 -; CHECK-NEXT: vst $vr0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: load_zext_2i32_to_2i64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: vrepli.b $vr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0 +; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2 +; LA32-NEXT: vst $vr0, $a1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: load_zext_2i32_to_2i64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr1, 0 +; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0 +; LA64-NEXT: vst $vr0, $a1, 0 +; LA64-NEXT: ret entry: %A = load <2 x i32>, ptr %ptr %B = zext <2 x i32> %A to <2 x i64> diff --git a/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll b/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll index ad57bbf9ee5c..7fa591db5d1f 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll @@ -603,3 +603,207 @@ define i4 @vmsk_eq_allzeros_v4i8(<4 x i8> %a) { %2 = bitcast <4 x i1> %1 to i4 ret i4 %2 } + +define i32 @vmsk2_eq_allzeros_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_eq_allzeros_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vseqi.b $vr0, $vr0, 0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vseqi.b $vr0, $vr1, 0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp eq <32 x i8> %a, splat (i8 0) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_sgt_allzeros_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_sgt_allzeros_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.b $vr2, 0 +; CHECK-NEXT: vslt.b $vr0, $vr2, $vr0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vslt.b $vr0, $vr2, $vr1 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp sgt <32 x i8> %a, splat (i8 0) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_sgt_allones_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_sgt_allones_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.b $vr2, -1 +; CHECK-NEXT: vslt.b $vr0, $vr2, $vr0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vslt.b $vr0, $vr2, $vr1 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp sgt <32 x i8> %a, splat (i8 -1) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_sge_allzeros_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_sge_allzeros_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.b $vr2, 0 +; CHECK-NEXT: vsle.b $vr0, $vr2, $vr0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vsle.b $vr0, $vr2, $vr1 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp sge <32 x i8> %a, splat (i8 0) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_slt_allzeros_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_slt_allzeros_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vmskltz.b $vr0, $vr1 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp slt <32 x i8> %a, splat (i8 0) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_sle_allzeros_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_sle_allzeros_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vslei.b $vr0, $vr0, 0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vslei.b $vr0, $vr1, 0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp sle <32 x i8> %a, splat (i8 0) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_sle_allones_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_sle_allones_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vslei.b $vr0, $vr0, -1 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vslei.b $vr0, $vr1, -1 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp sle <32 x i8> %a, splat (i8 -1) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_ne_allzeros_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_ne_allzeros_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vseqi.b $vr0, $vr0, 0 +; CHECK-NEXT: vxori.b $vr0, $vr0, 255 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vseqi.b $vr0, $vr1, 0 +; CHECK-NEXT: vxori.b $vr0, $vr0, 255 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret +entry: + %1 = icmp ne <32 x i8> %a, splat (i8 0) + %2 = bitcast <32 x i1> %1 to i32 + ret i32 %2 +} + +define i32 @vmsk2_sgt_v32i8(<32 x i8> %a, <32 x i8> %b) { +; CHECK-LABEL: vmsk2_sgt_v32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vslt.b $vr0, $vr2, $vr0 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vslt.b $vr0, $vr3, $vr1 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret + %x = icmp sgt <32 x i8> %a, %b + %res = bitcast <32 x i1> %x to i32 + ret i32 %res +} + +define i32 @vmsk2_sgt_and_sgt_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i8> %d) { +; CHECK-LABEL: vmsk2_sgt_and_sgt_v32i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vslt.b $vr0, $vr2, $vr0 +; CHECK-NEXT: vslt.b $vr1, $vr3, $vr1 +; CHECK-NEXT: vslt.b $vr2, $vr6, $vr4 +; CHECK-NEXT: vslt.b $vr3, $vr7, $vr5 +; CHECK-NEXT: vand.v $vr1, $vr1, $vr3 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr2 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vmskltz.b $vr0, $vr1 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret + %x0 = icmp sgt <32 x i8> %a, %b + %x1 = icmp sgt <32 x i8> %c, %d + %y = and <32 x i1> %x0, %x1 + %res = bitcast <32 x i1> %y to i32 + ret i32 %res +} + +define i32 @vmsk2_trunc_i8(<32 x i8> %a) { +; CHECK-LABEL: vmsk2_trunc_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vslli.b $vr0, $vr0, 7 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a0, $vr0, 0 +; CHECK-NEXT: vslli.b $vr0, $vr1, 7 +; CHECK-NEXT: vmskltz.b $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.hu $a1, $vr0, 0 +; CHECK-NEXT: slli.d $a1, $a1, 16 +; CHECK-NEXT: or $a0, $a0, $a1 +; CHECK-NEXT: ret + %y = trunc <32 x i8> %a to <32 x i1> + %res = bitcast <32 x i1> %y to i32 + ret i32 %res +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/vselect.ll b/llvm/test/CodeGen/LoongArch/lsx/vselect.ll index 4d2ddeb2889b..5dbff4a402b3 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/vselect.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/vselect.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @select_v16i8_imm(ptr %res, ptr %a0) nounwind { ; CHECK-LABEL: select_v16i8_imm: @@ -49,16 +50,26 @@ define void @select_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind { } define void @select_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind { -; CHECK-LABEL: select_v4i32: -; CHECK: # %bb.0: -; CHECK-NEXT: vld $vr0, $a1, 0 -; CHECK-NEXT: vld $vr1, $a2, 0 -; CHECK-NEXT: ori $a1, $zero, 0 -; CHECK-NEXT: lu32i.d $a1, -1 -; CHECK-NEXT: vreplgr2vr.d $vr2, $a1 -; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 -; CHECK-NEXT: vst $vr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: select_v4i32: +; LA32: # %bb.0: +; LA32-NEXT: vld $vr0, $a1, 0 +; LA32-NEXT: vld $vr1, $a2, 0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 +; LA32-NEXT: vst $vr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: select_v4i32: +; LA64: # %bb.0: +; LA64-NEXT: vld $vr0, $a1, 0 +; LA64-NEXT: vld $vr1, $a2, 0 +; LA64-NEXT: ori $a1, $zero, 0 +; LA64-NEXT: lu32i.d $a1, -1 +; LA64-NEXT: vreplgr2vr.d $vr2, $a1 +; LA64-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2 +; LA64-NEXT: vst $vr0, $a0, 0 +; LA64-NEXT: ret %v0 = load <4 x i32>, ptr %a0 %v1 = load <4 x i32>, ptr %a1 %sel = select <4 x i1> <i1 false, i1 true, i1 false, i1 true>, <4 x i32> %v0, <4 x i32> %v1 |