diff options
Diffstat (limited to 'llvm/test/CodeGen/LoongArch/lasx')
271 files changed, 5396 insertions, 2196 deletions
diff --git a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll index 976924bdca68..4aa2bd76ab80 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll @@ -1,16 +1,31 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 -; TODO: Load a element and splat it to a vector could be lowerd to xvldrepl -; A load has more than one user shouldn't be lowered to xvldrepl define <4 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst) { -; CHECK-LABEL: should_not_be_optimized: -; CHECK: # %bb.0: -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: xvreplgr2vr.d $xr0, $a0 -; CHECK-NEXT: st.d $a0, $a1, 0 -; CHECK-NEXT: ret +; LA32-LABEL: should_not_be_optimized: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a2, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: st.w $a2, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 6 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7 +; LA32-NEXT: st.w $a0, $a1, 4 +; LA32-NEXT: ret +; +; LA64-LABEL: should_not_be_optimized: +; LA64: # %bb.0: +; LA64-NEXT: ld.d $a0, $a0, 0 +; LA64-NEXT: xvreplgr2vr.d $xr0, $a0 +; LA64-NEXT: st.d $a0, $a1, 0 +; LA64-NEXT: ret %tmp = load i64, ptr %ptr store i64 %tmp, ptr %dst %tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0 @@ -18,12 +33,52 @@ define <4 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst) { ret <4 x i64> %tmp2 } -define <4 x i64> @xvldrepl_d_unaligned_offset(ptr %ptr) { -; CHECK-LABEL: xvldrepl_d_unaligned_offset: +define <16 x i16> @should_not_be_optimized_sext_load(ptr %ptr) { +; CHECK-LABEL: should_not_be_optimized_sext_load: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $a0, $a0, 4 -; CHECK-NEXT: xvldrepl.d $xr0, $a0, 0 +; CHECK-NEXT: ld.b $a0, $a0, 0 +; CHECK-NEXT: xvreplgr2vr.h $xr0, $a0 +; CHECK-NEXT: ret + %tmp = load i8, ptr %ptr + %tmp1 = sext i8 %tmp to i16 + %tmp2 = insertelement <16 x i16> zeroinitializer, i16 %tmp1, i32 0 + %tmp3 = shufflevector <16 x i16> %tmp2, <16 x i16> poison, <16 x i32> zeroinitializer + ret <16 x i16> %tmp3 +} + +define <16 x i16> @should_not_be_optimized_zext_load(ptr %ptr) { +; CHECK-LABEL: should_not_be_optimized_zext_load: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.bu $a0, $a0, 0 +; CHECK-NEXT: xvreplgr2vr.h $xr0, $a0 ; CHECK-NEXT: ret + %tmp = load i8, ptr %ptr + %tmp1 = zext i8 %tmp to i16 + %tmp2 = insertelement <16 x i16> zeroinitializer, i16 %tmp1, i32 0 + %tmp3 = shufflevector <16 x i16> %tmp2, <16 x i16> poison, <16 x i32> zeroinitializer + ret <16 x i16> %tmp3 +} + +define <4 x i64> @xvldrepl_d_unaligned_offset(ptr %ptr) { +; LA32-LABEL: xvldrepl_d_unaligned_offset: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a0, $a0, 8 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7 +; LA32-NEXT: ret +; +; LA64-LABEL: xvldrepl_d_unaligned_offset: +; LA64: # %bb.0: +; LA64-NEXT: addi.d $a0, $a0, 4 +; LA64-NEXT: xvldrepl.d $xr0, $a0, 0 +; LA64-NEXT: ret %p = getelementptr i32, ptr %ptr, i32 1 %tmp = load i64, ptr %p %tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0 @@ -103,10 +158,24 @@ define <8 x i32> @xvldrepl_w_offset(ptr %ptr) { define <4 x i64> @xvldrepl_d(ptr %ptr) { -; CHECK-LABEL: xvldrepl_d: -; CHECK: # %bb.0: -; CHECK-NEXT: xvldrepl.d $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: xvldrepl_d: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a1, $a0, 0 +; LA32-NEXT: ld.w $a0, $a0, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7 +; LA32-NEXT: ret +; +; LA64-LABEL: xvldrepl_d: +; LA64: # %bb.0: +; LA64-NEXT: xvldrepl.d $xr0, $a0, 0 +; LA64-NEXT: ret %tmp = load i64, ptr %ptr %tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0 %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> poison, <4 x i32> zeroinitializer @@ -114,10 +183,24 @@ define <4 x i64> @xvldrepl_d(ptr %ptr) { } define <4 x i64> @xvldrepl_d_offset(ptr %ptr) { -; CHECK-LABEL: xvldrepl_d_offset: -; CHECK: # %bb.0: -; CHECK-NEXT: xvldrepl.d $xr0, $a0, 264 -; CHECK-NEXT: ret +; LA32-LABEL: xvldrepl_d_offset: +; LA32: # %bb.0: +; LA32-NEXT: ld.w $a1, $a0, 264 +; LA32-NEXT: ld.w $a0, $a0, 268 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7 +; LA32-NEXT: ret +; +; LA64-LABEL: xvldrepl_d_offset: +; LA64: # %bb.0: +; LA64-NEXT: xvldrepl.d $xr0, $a0, 264 +; LA64-NEXT: ret %p = getelementptr i64, ptr %ptr, i64 33 %tmp = load i64, ptr %p %tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0 diff --git a/llvm/test/CodeGen/LoongArch/lasx/bswap.ll b/llvm/test/CodeGen/LoongArch/lasx/bswap.ll index 1b0132d25ed5..a4c9abac7dcc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/bswap.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/bswap.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @bswap_v16i16(ptr %src, ptr %dst) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll index cc9ad633b427..23245726c896 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @buildvector_v32i8_splat(ptr %dst, i8 %a0) nounwind { ; CHECK-LABEL: buildvector_v32i8_splat: @@ -41,11 +42,24 @@ entry: } define void @buildvector_v4i64_splat(ptr %dst, i64 %a0) nounwind { -; CHECK-LABEL: buildvector_v4i64_splat: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvreplgr2vr.d $xr0, $a1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v4i64_splat: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 5 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 7 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v4i64_splat: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvreplgr2vr.d $xr0, $a1 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %insert = insertelement <4 x i64> undef, i64 %a0, i8 0 %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer @@ -138,12 +152,19 @@ entry: } define void @buildvector_v4f64_const_splat(ptr %dst) nounwind { -; CHECK-LABEL: buildvector_v4f64_const_splat: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: lu52i.d $a1, $zero, 1023 -; CHECK-NEXT: xvreplgr2vr.d $xr0, $a1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v4f64_const_splat: +; LA32: # %bb.0: # %entry +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0) +; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI11_0) +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v4f64_const_splat: +; LA64: # %bb.0: # %entry +; LA64-NEXT: lu52i.d $a1, $zero, 1023 +; LA64-NEXT: xvreplgr2vr.d $xr0, $a1 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: store <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, ptr %dst ret void @@ -222,147 +243,289 @@ entry: } define void @buildvector_v32i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31) nounwind { -; CHECK-LABEL: buildvector_v32i8: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi.d $sp, $sp, -80 -; CHECK-NEXT: fst.d $fs0, $sp, 72 # 8-byte Folded Spill -; CHECK-NEXT: fst.d $fs1, $sp, 64 # 8-byte Folded Spill -; CHECK-NEXT: fst.d $fs2, $sp, 56 # 8-byte Folded Spill -; CHECK-NEXT: fst.d $fs3, $sp, 48 # 8-byte Folded Spill -; CHECK-NEXT: fst.d $fs4, $sp, 40 # 8-byte Folded Spill -; CHECK-NEXT: fst.d $fs5, $sp, 32 # 8-byte Folded Spill -; CHECK-NEXT: fst.d $fs6, $sp, 24 # 8-byte Folded Spill -; CHECK-NEXT: fst.d $fs7, $sp, 16 # 8-byte Folded Spill -; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2 -; CHECK-NEXT: xvreplgr2vr.b $xr2, $a3 -; CHECK-NEXT: xvreplgr2vr.b $xr3, $a4 -; CHECK-NEXT: ld.b $a1, $sp, 264 -; CHECK-NEXT: xvreplgr2vr.b $xr4, $a5 -; CHECK-NEXT: ld.b $a2, $sp, 80 -; CHECK-NEXT: xvreplgr2vr.b $xr5, $a6 -; CHECK-NEXT: ld.b $a3, $sp, 88 -; CHECK-NEXT: xvreplgr2vr.b $xr6, $a7 -; CHECK-NEXT: ld.b $a4, $sp, 96 -; CHECK-NEXT: xvreplgr2vr.b $xr7, $a2 -; CHECK-NEXT: ld.b $a2, $sp, 104 -; CHECK-NEXT: xvreplgr2vr.b $xr8, $a3 -; CHECK-NEXT: ld.b $a3, $sp, 112 -; CHECK-NEXT: xvreplgr2vr.b $xr9, $a4 -; CHECK-NEXT: ld.b $a4, $sp, 120 -; CHECK-NEXT: xvreplgr2vr.b $xr10, $a2 -; CHECK-NEXT: ld.b $a2, $sp, 128 -; CHECK-NEXT: xvreplgr2vr.b $xr11, $a3 -; CHECK-NEXT: ld.b $a3, $sp, 136 -; CHECK-NEXT: xvreplgr2vr.b $xr12, $a4 -; CHECK-NEXT: ld.b $a4, $sp, 144 -; CHECK-NEXT: xvreplgr2vr.b $xr13, $a2 -; CHECK-NEXT: ld.b $a2, $sp, 152 -; CHECK-NEXT: xvreplgr2vr.b $xr14, $a3 -; CHECK-NEXT: ld.b $a3, $sp, 160 -; CHECK-NEXT: xvreplgr2vr.b $xr15, $a4 -; CHECK-NEXT: ld.b $a4, $sp, 168 -; CHECK-NEXT: xvreplgr2vr.b $xr16, $a2 -; CHECK-NEXT: ld.b $a2, $sp, 176 -; CHECK-NEXT: xvreplgr2vr.b $xr17, $a3 -; CHECK-NEXT: ld.b $a3, $sp, 184 -; CHECK-NEXT: xvreplgr2vr.b $xr18, $a4 -; CHECK-NEXT: ld.b $a4, $sp, 192 -; CHECK-NEXT: xvreplgr2vr.b $xr19, $a2 -; CHECK-NEXT: ld.b $a2, $sp, 200 -; CHECK-NEXT: xvreplgr2vr.b $xr20, $a3 -; CHECK-NEXT: ld.b $a3, $sp, 208 -; CHECK-NEXT: xvreplgr2vr.b $xr21, $a4 -; CHECK-NEXT: ld.b $a4, $sp, 216 -; CHECK-NEXT: xvreplgr2vr.b $xr22, $a2 -; CHECK-NEXT: ld.b $a2, $sp, 224 -; CHECK-NEXT: xvreplgr2vr.b $xr23, $a3 -; CHECK-NEXT: ld.b $a3, $sp, 232 -; CHECK-NEXT: xvreplgr2vr.b $xr24, $a4 -; CHECK-NEXT: ld.b $a4, $sp, 240 -; CHECK-NEXT: xvreplgr2vr.b $xr25, $a2 -; CHECK-NEXT: ld.b $a2, $sp, 248 -; CHECK-NEXT: xvreplgr2vr.b $xr26, $a3 -; CHECK-NEXT: ld.b $a3, $sp, 256 -; CHECK-NEXT: xvreplgr2vr.b $xr27, $a4 -; CHECK-NEXT: ld.b $a4, $sp, 272 -; CHECK-NEXT: xvreplgr2vr.b $xr28, $a2 -; CHECK-NEXT: xvreplgr2vr.b $xr29, $a3 -; CHECK-NEXT: xvreplgr2vr.b $xr30, $a1 -; CHECK-NEXT: xvreplgr2vr.b $xr31, $a4 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17 -; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr2, 34 -; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr3, 51 -; CHECK-NEXT: xvpermi.q $xr4, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr4, 68 -; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr5, 85 -; CHECK-NEXT: xvpermi.q $xr6, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr6, 102 -; CHECK-NEXT: xvpermi.q $xr7, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr7, 119 -; CHECK-NEXT: xvpermi.q $xr8, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr8, 136 -; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr9, 153 -; CHECK-NEXT: xvpermi.q $xr10, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr10, 170 -; CHECK-NEXT: xvpermi.q $xr11, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr11, 187 -; CHECK-NEXT: xvpermi.q $xr12, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr12, 204 -; CHECK-NEXT: xvpermi.q $xr13, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr13, 221 -; CHECK-NEXT: xvpermi.q $xr14, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr14, 238 -; CHECK-NEXT: xvpermi.q $xr15, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr15, 255 -; CHECK-NEXT: xvpermi.q $xr16, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr16, 0 -; CHECK-NEXT: xvpermi.q $xr17, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr17, 17 -; CHECK-NEXT: xvpermi.q $xr18, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr18, 34 -; CHECK-NEXT: xvpermi.q $xr19, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr19, 51 -; CHECK-NEXT: xvpermi.q $xr20, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr20, 68 -; CHECK-NEXT: xvpermi.q $xr21, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr21, 85 -; CHECK-NEXT: xvpermi.q $xr22, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr22, 102 -; CHECK-NEXT: xvpermi.q $xr23, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr23, 119 -; CHECK-NEXT: xvpermi.q $xr24, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr24, 136 -; CHECK-NEXT: xvpermi.q $xr25, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr25, 153 -; CHECK-NEXT: xvpermi.q $xr26, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr26, 170 -; CHECK-NEXT: xvpermi.q $xr27, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr27, 187 -; CHECK-NEXT: xvpermi.q $xr28, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr28, 204 -; CHECK-NEXT: xvpermi.q $xr29, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr29, 221 -; CHECK-NEXT: xvpermi.q $xr30, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr30, 238 -; CHECK-NEXT: xvpermi.q $xr31, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr31, 255 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: fld.d $fs7, $sp, 16 # 8-byte Folded Reload -; CHECK-NEXT: fld.d $fs6, $sp, 24 # 8-byte Folded Reload -; CHECK-NEXT: fld.d $fs5, $sp, 32 # 8-byte Folded Reload -; CHECK-NEXT: fld.d $fs4, $sp, 40 # 8-byte Folded Reload -; CHECK-NEXT: fld.d $fs3, $sp, 48 # 8-byte Folded Reload -; CHECK-NEXT: fld.d $fs2, $sp, 56 # 8-byte Folded Reload -; CHECK-NEXT: fld.d $fs1, $sp, 64 # 8-byte Folded Reload -; CHECK-NEXT: fld.d $fs0, $sp, 72 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 80 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v32i8: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -80 +; LA32-NEXT: fst.d $fs0, $sp, 72 # 8-byte Folded Spill +; LA32-NEXT: fst.d $fs1, $sp, 64 # 8-byte Folded Spill +; LA32-NEXT: fst.d $fs2, $sp, 56 # 8-byte Folded Spill +; LA32-NEXT: fst.d $fs3, $sp, 48 # 8-byte Folded Spill +; LA32-NEXT: fst.d $fs4, $sp, 40 # 8-byte Folded Spill +; LA32-NEXT: fst.d $fs5, $sp, 32 # 8-byte Folded Spill +; LA32-NEXT: fst.d $fs6, $sp, 24 # 8-byte Folded Spill +; LA32-NEXT: fst.d $fs7, $sp, 16 # 8-byte Folded Spill +; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA32-NEXT: xvreplgr2vr.b $xr2, $a3 +; LA32-NEXT: xvreplgr2vr.b $xr3, $a4 +; LA32-NEXT: ld.b $a1, $sp, 172 +; LA32-NEXT: xvreplgr2vr.b $xr4, $a5 +; LA32-NEXT: ld.b $a2, $sp, 80 +; LA32-NEXT: xvreplgr2vr.b $xr5, $a6 +; LA32-NEXT: ld.b $a3, $sp, 84 +; LA32-NEXT: xvreplgr2vr.b $xr6, $a7 +; LA32-NEXT: ld.b $a4, $sp, 88 +; LA32-NEXT: xvreplgr2vr.b $xr7, $a2 +; LA32-NEXT: ld.b $a2, $sp, 92 +; LA32-NEXT: xvreplgr2vr.b $xr8, $a3 +; LA32-NEXT: ld.b $a3, $sp, 96 +; LA32-NEXT: xvreplgr2vr.b $xr9, $a4 +; LA32-NEXT: ld.b $a4, $sp, 100 +; LA32-NEXT: xvreplgr2vr.b $xr10, $a2 +; LA32-NEXT: ld.b $a2, $sp, 104 +; LA32-NEXT: xvreplgr2vr.b $xr11, $a3 +; LA32-NEXT: ld.b $a3, $sp, 108 +; LA32-NEXT: xvreplgr2vr.b $xr12, $a4 +; LA32-NEXT: ld.b $a4, $sp, 112 +; LA32-NEXT: xvreplgr2vr.b $xr13, $a2 +; LA32-NEXT: ld.b $a2, $sp, 116 +; LA32-NEXT: xvreplgr2vr.b $xr14, $a3 +; LA32-NEXT: ld.b $a3, $sp, 120 +; LA32-NEXT: xvreplgr2vr.b $xr15, $a4 +; LA32-NEXT: ld.b $a4, $sp, 124 +; LA32-NEXT: xvreplgr2vr.b $xr16, $a2 +; LA32-NEXT: ld.b $a2, $sp, 128 +; LA32-NEXT: xvreplgr2vr.b $xr17, $a3 +; LA32-NEXT: ld.b $a3, $sp, 132 +; LA32-NEXT: xvreplgr2vr.b $xr18, $a4 +; LA32-NEXT: ld.b $a4, $sp, 136 +; LA32-NEXT: xvreplgr2vr.b $xr19, $a2 +; LA32-NEXT: ld.b $a2, $sp, 140 +; LA32-NEXT: xvreplgr2vr.b $xr20, $a3 +; LA32-NEXT: ld.b $a3, $sp, 144 +; LA32-NEXT: xvreplgr2vr.b $xr21, $a4 +; LA32-NEXT: ld.b $a4, $sp, 148 +; LA32-NEXT: xvreplgr2vr.b $xr22, $a2 +; LA32-NEXT: ld.b $a2, $sp, 152 +; LA32-NEXT: xvreplgr2vr.b $xr23, $a3 +; LA32-NEXT: ld.b $a3, $sp, 156 +; LA32-NEXT: xvreplgr2vr.b $xr24, $a4 +; LA32-NEXT: ld.b $a4, $sp, 160 +; LA32-NEXT: xvreplgr2vr.b $xr25, $a2 +; LA32-NEXT: ld.b $a2, $sp, 164 +; LA32-NEXT: xvreplgr2vr.b $xr26, $a3 +; LA32-NEXT: ld.b $a3, $sp, 168 +; LA32-NEXT: xvreplgr2vr.b $xr27, $a4 +; LA32-NEXT: ld.b $a4, $sp, 176 +; LA32-NEXT: xvreplgr2vr.b $xr28, $a2 +; LA32-NEXT: xvreplgr2vr.b $xr29, $a3 +; LA32-NEXT: xvreplgr2vr.b $xr30, $a1 +; LA32-NEXT: xvreplgr2vr.b $xr31, $a4 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA32-NEXT: xvpermi.q $xr2, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr2, 34 +; LA32-NEXT: xvpermi.q $xr3, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr3, 51 +; LA32-NEXT: xvpermi.q $xr4, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr4, 68 +; LA32-NEXT: xvpermi.q $xr5, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr5, 85 +; LA32-NEXT: xvpermi.q $xr6, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr6, 102 +; LA32-NEXT: xvpermi.q $xr7, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr7, 119 +; LA32-NEXT: xvpermi.q $xr8, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr8, 136 +; LA32-NEXT: xvpermi.q $xr9, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr9, 153 +; LA32-NEXT: xvpermi.q $xr10, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr10, 170 +; LA32-NEXT: xvpermi.q $xr11, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr11, 187 +; LA32-NEXT: xvpermi.q $xr12, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr12, 204 +; LA32-NEXT: xvpermi.q $xr13, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr13, 221 +; LA32-NEXT: xvpermi.q $xr14, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr14, 238 +; LA32-NEXT: xvpermi.q $xr15, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr15, 255 +; LA32-NEXT: xvpermi.q $xr16, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr16, 0 +; LA32-NEXT: xvpermi.q $xr17, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr17, 17 +; LA32-NEXT: xvpermi.q $xr18, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr18, 34 +; LA32-NEXT: xvpermi.q $xr19, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr19, 51 +; LA32-NEXT: xvpermi.q $xr20, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr20, 68 +; LA32-NEXT: xvpermi.q $xr21, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr21, 85 +; LA32-NEXT: xvpermi.q $xr22, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr22, 102 +; LA32-NEXT: xvpermi.q $xr23, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr23, 119 +; LA32-NEXT: xvpermi.q $xr24, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr24, 136 +; LA32-NEXT: xvpermi.q $xr25, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr25, 153 +; LA32-NEXT: xvpermi.q $xr26, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr26, 170 +; LA32-NEXT: xvpermi.q $xr27, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr27, 187 +; LA32-NEXT: xvpermi.q $xr28, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr28, 204 +; LA32-NEXT: xvpermi.q $xr29, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr29, 221 +; LA32-NEXT: xvpermi.q $xr30, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr30, 238 +; LA32-NEXT: xvpermi.q $xr31, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr31, 255 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: fld.d $fs7, $sp, 16 # 8-byte Folded Reload +; LA32-NEXT: fld.d $fs6, $sp, 24 # 8-byte Folded Reload +; LA32-NEXT: fld.d $fs5, $sp, 32 # 8-byte Folded Reload +; LA32-NEXT: fld.d $fs4, $sp, 40 # 8-byte Folded Reload +; LA32-NEXT: fld.d $fs3, $sp, 48 # 8-byte Folded Reload +; LA32-NEXT: fld.d $fs2, $sp, 56 # 8-byte Folded Reload +; LA32-NEXT: fld.d $fs1, $sp, 64 # 8-byte Folded Reload +; LA32-NEXT: fld.d $fs0, $sp, 72 # 8-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 80 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v32i8: +; LA64: # %bb.0: # %entry +; LA64-NEXT: addi.d $sp, $sp, -80 +; LA64-NEXT: fst.d $fs0, $sp, 72 # 8-byte Folded Spill +; LA64-NEXT: fst.d $fs1, $sp, 64 # 8-byte Folded Spill +; LA64-NEXT: fst.d $fs2, $sp, 56 # 8-byte Folded Spill +; LA64-NEXT: fst.d $fs3, $sp, 48 # 8-byte Folded Spill +; LA64-NEXT: fst.d $fs4, $sp, 40 # 8-byte Folded Spill +; LA64-NEXT: fst.d $fs5, $sp, 32 # 8-byte Folded Spill +; LA64-NEXT: fst.d $fs6, $sp, 24 # 8-byte Folded Spill +; LA64-NEXT: fst.d $fs7, $sp, 16 # 8-byte Folded Spill +; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA64-NEXT: xvreplgr2vr.b $xr2, $a3 +; LA64-NEXT: xvreplgr2vr.b $xr3, $a4 +; LA64-NEXT: ld.b $a1, $sp, 264 +; LA64-NEXT: xvreplgr2vr.b $xr4, $a5 +; LA64-NEXT: ld.b $a2, $sp, 80 +; LA64-NEXT: xvreplgr2vr.b $xr5, $a6 +; LA64-NEXT: ld.b $a3, $sp, 88 +; LA64-NEXT: xvreplgr2vr.b $xr6, $a7 +; LA64-NEXT: ld.b $a4, $sp, 96 +; LA64-NEXT: xvreplgr2vr.b $xr7, $a2 +; LA64-NEXT: ld.b $a2, $sp, 104 +; LA64-NEXT: xvreplgr2vr.b $xr8, $a3 +; LA64-NEXT: ld.b $a3, $sp, 112 +; LA64-NEXT: xvreplgr2vr.b $xr9, $a4 +; LA64-NEXT: ld.b $a4, $sp, 120 +; LA64-NEXT: xvreplgr2vr.b $xr10, $a2 +; LA64-NEXT: ld.b $a2, $sp, 128 +; LA64-NEXT: xvreplgr2vr.b $xr11, $a3 +; LA64-NEXT: ld.b $a3, $sp, 136 +; LA64-NEXT: xvreplgr2vr.b $xr12, $a4 +; LA64-NEXT: ld.b $a4, $sp, 144 +; LA64-NEXT: xvreplgr2vr.b $xr13, $a2 +; LA64-NEXT: ld.b $a2, $sp, 152 +; LA64-NEXT: xvreplgr2vr.b $xr14, $a3 +; LA64-NEXT: ld.b $a3, $sp, 160 +; LA64-NEXT: xvreplgr2vr.b $xr15, $a4 +; LA64-NEXT: ld.b $a4, $sp, 168 +; LA64-NEXT: xvreplgr2vr.b $xr16, $a2 +; LA64-NEXT: ld.b $a2, $sp, 176 +; LA64-NEXT: xvreplgr2vr.b $xr17, $a3 +; LA64-NEXT: ld.b $a3, $sp, 184 +; LA64-NEXT: xvreplgr2vr.b $xr18, $a4 +; LA64-NEXT: ld.b $a4, $sp, 192 +; LA64-NEXT: xvreplgr2vr.b $xr19, $a2 +; LA64-NEXT: ld.b $a2, $sp, 200 +; LA64-NEXT: xvreplgr2vr.b $xr20, $a3 +; LA64-NEXT: ld.b $a3, $sp, 208 +; LA64-NEXT: xvreplgr2vr.b $xr21, $a4 +; LA64-NEXT: ld.b $a4, $sp, 216 +; LA64-NEXT: xvreplgr2vr.b $xr22, $a2 +; LA64-NEXT: ld.b $a2, $sp, 224 +; LA64-NEXT: xvreplgr2vr.b $xr23, $a3 +; LA64-NEXT: ld.b $a3, $sp, 232 +; LA64-NEXT: xvreplgr2vr.b $xr24, $a4 +; LA64-NEXT: ld.b $a4, $sp, 240 +; LA64-NEXT: xvreplgr2vr.b $xr25, $a2 +; LA64-NEXT: ld.b $a2, $sp, 248 +; LA64-NEXT: xvreplgr2vr.b $xr26, $a3 +; LA64-NEXT: ld.b $a3, $sp, 256 +; LA64-NEXT: xvreplgr2vr.b $xr27, $a4 +; LA64-NEXT: ld.b $a4, $sp, 272 +; LA64-NEXT: xvreplgr2vr.b $xr28, $a2 +; LA64-NEXT: xvreplgr2vr.b $xr29, $a3 +; LA64-NEXT: xvreplgr2vr.b $xr30, $a1 +; LA64-NEXT: xvreplgr2vr.b $xr31, $a4 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA64-NEXT: xvpermi.q $xr2, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr2, 34 +; LA64-NEXT: xvpermi.q $xr3, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr3, 51 +; LA64-NEXT: xvpermi.q $xr4, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr4, 68 +; LA64-NEXT: xvpermi.q $xr5, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr5, 85 +; LA64-NEXT: xvpermi.q $xr6, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr6, 102 +; LA64-NEXT: xvpermi.q $xr7, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr7, 119 +; LA64-NEXT: xvpermi.q $xr8, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr8, 136 +; LA64-NEXT: xvpermi.q $xr9, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr9, 153 +; LA64-NEXT: xvpermi.q $xr10, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr10, 170 +; LA64-NEXT: xvpermi.q $xr11, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr11, 187 +; LA64-NEXT: xvpermi.q $xr12, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr12, 204 +; LA64-NEXT: xvpermi.q $xr13, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr13, 221 +; LA64-NEXT: xvpermi.q $xr14, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr14, 238 +; LA64-NEXT: xvpermi.q $xr15, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr15, 255 +; LA64-NEXT: xvpermi.q $xr16, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr16, 0 +; LA64-NEXT: xvpermi.q $xr17, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr17, 17 +; LA64-NEXT: xvpermi.q $xr18, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr18, 34 +; LA64-NEXT: xvpermi.q $xr19, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr19, 51 +; LA64-NEXT: xvpermi.q $xr20, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr20, 68 +; LA64-NEXT: xvpermi.q $xr21, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr21, 85 +; LA64-NEXT: xvpermi.q $xr22, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr22, 102 +; LA64-NEXT: xvpermi.q $xr23, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr23, 119 +; LA64-NEXT: xvpermi.q $xr24, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr24, 136 +; LA64-NEXT: xvpermi.q $xr25, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr25, 153 +; LA64-NEXT: xvpermi.q $xr26, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr26, 170 +; LA64-NEXT: xvpermi.q $xr27, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr27, 187 +; LA64-NEXT: xvpermi.q $xr28, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr28, 204 +; LA64-NEXT: xvpermi.q $xr29, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr29, 221 +; LA64-NEXT: xvpermi.q $xr30, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr30, 238 +; LA64-NEXT: xvpermi.q $xr31, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr31, 255 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: fld.d $fs7, $sp, 16 # 8-byte Folded Reload +; LA64-NEXT: fld.d $fs6, $sp, 24 # 8-byte Folded Reload +; LA64-NEXT: fld.d $fs5, $sp, 32 # 8-byte Folded Reload +; LA64-NEXT: fld.d $fs4, $sp, 40 # 8-byte Folded Reload +; LA64-NEXT: fld.d $fs3, $sp, 48 # 8-byte Folded Reload +; LA64-NEXT: fld.d $fs2, $sp, 56 # 8-byte Folded Reload +; LA64-NEXT: fld.d $fs1, $sp, 64 # 8-byte Folded Reload +; LA64-NEXT: fld.d $fs0, $sp, 72 # 8-byte Folded Reload +; LA64-NEXT: addi.d $sp, $sp, 80 +; LA64-NEXT: ret entry: %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 @@ -401,61 +564,117 @@ entry: } define void @buildvector_v32i8_partial(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a5, i8 %a7, i8 %a8, i8 %a15, i8 %a17, i8 %a18, i8 %a20, i8 %a22, i8 %a23, i8 %a27, i8 %a28, i8 %a31) nounwind { -; CHECK-LABEL: buildvector_v32i8_partial: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ld.b $t0, $sp, 56 -; CHECK-NEXT: ld.b $t1, $sp, 48 -; CHECK-NEXT: ld.b $t2, $sp, 40 -; CHECK-NEXT: ld.b $t3, $sp, 32 -; CHECK-NEXT: ld.b $t4, $sp, 24 -; CHECK-NEXT: ld.b $t5, $sp, 16 -; CHECK-NEXT: ld.b $t6, $sp, 8 -; CHECK-NEXT: ld.b $t7, $sp, 0 -; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a3 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a4 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 85 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a5 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 119 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a6 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 136 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a7 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t7 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t6 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t5 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 68 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t4 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 102 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t3 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 119 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t2 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 187 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t1 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 204 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t0 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v32i8_partial: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.b $t0, $sp, 28 +; LA32-NEXT: ld.b $t1, $sp, 24 +; LA32-NEXT: ld.b $t2, $sp, 20 +; LA32-NEXT: ld.b $t3, $sp, 16 +; LA32-NEXT: ld.b $t4, $sp, 12 +; LA32-NEXT: ld.b $t5, $sp, 8 +; LA32-NEXT: ld.b $t6, $sp, 4 +; LA32-NEXT: ld.b $t7, $sp, 0 +; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a3 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a4 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 85 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a5 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 119 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a6 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 136 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a7 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t7 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t6 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t5 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 68 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t4 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 102 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t3 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 119 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t2 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 187 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t1 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 204 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t0 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v32i8_partial: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.b $t0, $sp, 56 +; LA64-NEXT: ld.b $t1, $sp, 48 +; LA64-NEXT: ld.b $t2, $sp, 40 +; LA64-NEXT: ld.b $t3, $sp, 32 +; LA64-NEXT: ld.b $t4, $sp, 24 +; LA64-NEXT: ld.b $t5, $sp, 16 +; LA64-NEXT: ld.b $t6, $sp, 8 +; LA64-NEXT: ld.b $t7, $sp, 0 +; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a3 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a4 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 85 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a5 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 119 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a6 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 136 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a7 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t7 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t6 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t5 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 68 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t4 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 102 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t3 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 119 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t2 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 187 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t1 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 204 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t0 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 @@ -494,64 +713,123 @@ entry: } define void @buildvector_v32i8_with_constant(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a5, i8 %a8, i8 %a9, i8 %a15, i8 %a17, i8 %a18, i8 %a20, i8 %a22, i8 %a23, i8 %a27, i8 %a28, i8 %a31) nounwind { -; CHECK-LABEL: buildvector_v32i8_with_constant: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ld.b $t0, $sp, 56 -; CHECK-NEXT: ld.b $t1, $sp, 48 -; CHECK-NEXT: ld.b $t2, $sp, 40 -; CHECK-NEXT: ld.b $t3, $sp, 32 -; CHECK-NEXT: ld.b $t4, $sp, 24 -; CHECK-NEXT: ld.b $t5, $sp, 16 -; CHECK-NEXT: ld.b $t6, $sp, 8 -; CHECK-NEXT: ld.b $t7, $sp, 0 -; CHECK-NEXT: xvrepli.b $xr0, 0 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a1 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 0 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a3 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a4 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 85 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a5 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 136 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a6 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 153 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $a7 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t7 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t6 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t5 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 68 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t4 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 102 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t3 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 119 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t2 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 187 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t1 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 204 -; CHECK-NEXT: xvreplgr2vr.b $xr1, $t0 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v32i8_with_constant: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.b $t0, $sp, 28 +; LA32-NEXT: ld.b $t1, $sp, 24 +; LA32-NEXT: ld.b $t2, $sp, 20 +; LA32-NEXT: ld.b $t3, $sp, 16 +; LA32-NEXT: ld.b $t4, $sp, 12 +; LA32-NEXT: ld.b $t5, $sp, 8 +; LA32-NEXT: ld.b $t6, $sp, 4 +; LA32-NEXT: ld.b $t7, $sp, 0 +; LA32-NEXT: xvrepli.b $xr0, 0 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a1 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 0 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a3 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a4 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 85 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a5 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 136 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a6 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 153 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a7 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t7 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t6 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t5 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 68 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t4 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 102 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t3 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 119 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t2 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 187 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t1 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 204 +; LA32-NEXT: xvreplgr2vr.b $xr1, $t0 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v32i8_with_constant: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.b $t0, $sp, 56 +; LA64-NEXT: ld.b $t1, $sp, 48 +; LA64-NEXT: ld.b $t2, $sp, 40 +; LA64-NEXT: ld.b $t3, $sp, 32 +; LA64-NEXT: ld.b $t4, $sp, 24 +; LA64-NEXT: ld.b $t5, $sp, 16 +; LA64-NEXT: ld.b $t6, $sp, 8 +; LA64-NEXT: ld.b $t7, $sp, 0 +; LA64-NEXT: xvrepli.b $xr0, 0 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a1 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 0 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a3 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a4 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 85 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a5 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 136 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a6 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 153 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a7 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t7 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t6 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 34 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t5 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 68 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t4 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 102 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t3 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 119 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t2 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 187 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t1 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 204 +; LA64-NEXT: xvreplgr2vr.b $xr1, $t0 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 255 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 @@ -589,67 +867,789 @@ entry: ret void } -define void @buildvector_v16i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind { -; CHECK-LABEL: buildvector_v16i16: +define void @buildvector_v32i8_subseq_2(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind { +; LA32-LABEL: buildvector_v32i8_subseq_2: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.b $t0, $sp, 32 +; LA32-NEXT: ld.b $t1, $sp, 28 +; LA32-NEXT: ld.b $t2, $sp, 24 +; LA32-NEXT: ld.b $t3, $sp, 20 +; LA32-NEXT: ld.b $t4, $sp, 16 +; LA32-NEXT: ld.b $t5, $sp, 12 +; LA32-NEXT: ld.b $t6, $sp, 8 +; LA32-NEXT: ld.b $t7, $sp, 4 +; LA32-NEXT: ld.b $t8, $sp, 0 +; LA32-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA32-NEXT: xvori.b $xr3, $xr1, 0 +; LA32-NEXT: xvpermi.q $xr3, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr2, $a3 +; LA32-NEXT: xvextrins.b $xr0, $xr3, 17 +; LA32-NEXT: xvori.b $xr4, $xr2, 0 +; LA32-NEXT: xvpermi.q $xr4, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr3, $a4 +; LA32-NEXT: xvextrins.b $xr0, $xr4, 34 +; LA32-NEXT: xvori.b $xr5, $xr3, 0 +; LA32-NEXT: xvpermi.q $xr5, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr4, $a5 +; LA32-NEXT: xvextrins.b $xr0, $xr5, 51 +; LA32-NEXT: xvori.b $xr6, $xr4, 0 +; LA32-NEXT: xvpermi.q $xr6, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr5, $a6 +; LA32-NEXT: xvextrins.b $xr0, $xr6, 68 +; LA32-NEXT: xvori.b $xr7, $xr5, 0 +; LA32-NEXT: xvpermi.q $xr7, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr6, $a7 +; LA32-NEXT: xvextrins.b $xr0, $xr7, 85 +; LA32-NEXT: xvori.b $xr8, $xr6, 0 +; LA32-NEXT: xvpermi.q $xr8, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr7, $t8 +; LA32-NEXT: xvextrins.b $xr0, $xr8, 102 +; LA32-NEXT: xvori.b $xr9, $xr7, 0 +; LA32-NEXT: xvpermi.q $xr9, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr8, $t7 +; LA32-NEXT: xvextrins.b $xr0, $xr9, 119 +; LA32-NEXT: xvori.b $xr10, $xr8, 0 +; LA32-NEXT: xvpermi.q $xr10, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr9, $t6 +; LA32-NEXT: xvextrins.b $xr0, $xr10, 136 +; LA32-NEXT: xvori.b $xr11, $xr9, 0 +; LA32-NEXT: xvpermi.q $xr11, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr10, $t5 +; LA32-NEXT: xvextrins.b $xr0, $xr11, 153 +; LA32-NEXT: xvori.b $xr12, $xr10, 0 +; LA32-NEXT: xvpermi.q $xr12, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr11, $t4 +; LA32-NEXT: xvextrins.b $xr0, $xr12, 170 +; LA32-NEXT: xvori.b $xr13, $xr11, 0 +; LA32-NEXT: xvpermi.q $xr13, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr12, $t3 +; LA32-NEXT: xvextrins.b $xr0, $xr13, 187 +; LA32-NEXT: xvori.b $xr14, $xr12, 0 +; LA32-NEXT: xvpermi.q $xr14, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr13, $t2 +; LA32-NEXT: xvextrins.b $xr0, $xr14, 204 +; LA32-NEXT: xvori.b $xr15, $xr13, 0 +; LA32-NEXT: xvpermi.q $xr15, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr14, $t1 +; LA32-NEXT: xvextrins.b $xr0, $xr15, 221 +; LA32-NEXT: xvori.b $xr16, $xr14, 0 +; LA32-NEXT: xvpermi.q $xr16, $xr0, 18 +; LA32-NEXT: xvreplgr2vr.b $xr15, $t0 +; LA32-NEXT: xvextrins.b $xr0, $xr16, 238 +; LA32-NEXT: xvori.b $xr16, $xr15, 0 +; LA32-NEXT: xvpermi.q $xr16, $xr0, 18 +; LA32-NEXT: xvextrins.b $xr0, $xr16, 255 +; LA32-NEXT: xvreplgr2vr.b $xr16, $a1 +; LA32-NEXT: xvpermi.q $xr16, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr16, 0 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA32-NEXT: xvpermi.q $xr2, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr2, 34 +; LA32-NEXT: xvpermi.q $xr3, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr3, 51 +; LA32-NEXT: xvpermi.q $xr4, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr4, 68 +; LA32-NEXT: xvpermi.q $xr5, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr5, 85 +; LA32-NEXT: xvpermi.q $xr6, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr6, 102 +; LA32-NEXT: xvpermi.q $xr7, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr7, 119 +; LA32-NEXT: xvpermi.q $xr8, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr8, 136 +; LA32-NEXT: xvpermi.q $xr9, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr9, 153 +; LA32-NEXT: xvpermi.q $xr10, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr10, 170 +; LA32-NEXT: xvpermi.q $xr11, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr11, 187 +; LA32-NEXT: xvpermi.q $xr12, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr12, 204 +; LA32-NEXT: xvpermi.q $xr13, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr13, 221 +; LA32-NEXT: xvpermi.q $xr14, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr14, 238 +; LA32-NEXT: xvpermi.q $xr15, $xr0, 48 +; LA32-NEXT: xvextrins.b $xr0, $xr15, 255 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v32i8_subseq_2: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.b $t0, $sp, 64 +; LA64-NEXT: ld.b $t1, $sp, 56 +; LA64-NEXT: ld.b $t2, $sp, 48 +; LA64-NEXT: ld.b $t3, $sp, 40 +; LA64-NEXT: ld.b $t4, $sp, 32 +; LA64-NEXT: ld.b $t5, $sp, 24 +; LA64-NEXT: ld.b $t6, $sp, 16 +; LA64-NEXT: ld.b $t7, $sp, 8 +; LA64-NEXT: ld.b $t8, $sp, 0 +; LA64-NEXT: xvreplgr2vr.b $xr1, $a2 +; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; LA64-NEXT: xvori.b $xr3, $xr1, 0 +; LA64-NEXT: xvpermi.q $xr3, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr2, $a3 +; LA64-NEXT: xvextrins.b $xr0, $xr3, 17 +; LA64-NEXT: xvori.b $xr4, $xr2, 0 +; LA64-NEXT: xvpermi.q $xr4, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr3, $a4 +; LA64-NEXT: xvextrins.b $xr0, $xr4, 34 +; LA64-NEXT: xvori.b $xr5, $xr3, 0 +; LA64-NEXT: xvpermi.q $xr5, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr4, $a5 +; LA64-NEXT: xvextrins.b $xr0, $xr5, 51 +; LA64-NEXT: xvori.b $xr6, $xr4, 0 +; LA64-NEXT: xvpermi.q $xr6, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr5, $a6 +; LA64-NEXT: xvextrins.b $xr0, $xr6, 68 +; LA64-NEXT: xvori.b $xr7, $xr5, 0 +; LA64-NEXT: xvpermi.q $xr7, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr6, $a7 +; LA64-NEXT: xvextrins.b $xr0, $xr7, 85 +; LA64-NEXT: xvori.b $xr8, $xr6, 0 +; LA64-NEXT: xvpermi.q $xr8, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr7, $t8 +; LA64-NEXT: xvextrins.b $xr0, $xr8, 102 +; LA64-NEXT: xvori.b $xr9, $xr7, 0 +; LA64-NEXT: xvpermi.q $xr9, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr8, $t7 +; LA64-NEXT: xvextrins.b $xr0, $xr9, 119 +; LA64-NEXT: xvori.b $xr10, $xr8, 0 +; LA64-NEXT: xvpermi.q $xr10, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr9, $t6 +; LA64-NEXT: xvextrins.b $xr0, $xr10, 136 +; LA64-NEXT: xvori.b $xr11, $xr9, 0 +; LA64-NEXT: xvpermi.q $xr11, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr10, $t5 +; LA64-NEXT: xvextrins.b $xr0, $xr11, 153 +; LA64-NEXT: xvori.b $xr12, $xr10, 0 +; LA64-NEXT: xvpermi.q $xr12, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr11, $t4 +; LA64-NEXT: xvextrins.b $xr0, $xr12, 170 +; LA64-NEXT: xvori.b $xr13, $xr11, 0 +; LA64-NEXT: xvpermi.q $xr13, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr12, $t3 +; LA64-NEXT: xvextrins.b $xr0, $xr13, 187 +; LA64-NEXT: xvori.b $xr14, $xr12, 0 +; LA64-NEXT: xvpermi.q $xr14, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr13, $t2 +; LA64-NEXT: xvextrins.b $xr0, $xr14, 204 +; LA64-NEXT: xvori.b $xr15, $xr13, 0 +; LA64-NEXT: xvpermi.q $xr15, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr14, $t1 +; LA64-NEXT: xvextrins.b $xr0, $xr15, 221 +; LA64-NEXT: xvori.b $xr16, $xr14, 0 +; LA64-NEXT: xvpermi.q $xr16, $xr0, 18 +; LA64-NEXT: xvreplgr2vr.b $xr15, $t0 +; LA64-NEXT: xvextrins.b $xr0, $xr16, 238 +; LA64-NEXT: xvori.b $xr16, $xr15, 0 +; LA64-NEXT: xvpermi.q $xr16, $xr0, 18 +; LA64-NEXT: xvextrins.b $xr0, $xr16, 255 +; LA64-NEXT: xvreplgr2vr.b $xr16, $a1 +; LA64-NEXT: xvpermi.q $xr16, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr16, 0 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr1, 17 +; LA64-NEXT: xvpermi.q $xr2, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr2, 34 +; LA64-NEXT: xvpermi.q $xr3, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr3, 51 +; LA64-NEXT: xvpermi.q $xr4, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr4, 68 +; LA64-NEXT: xvpermi.q $xr5, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr5, 85 +; LA64-NEXT: xvpermi.q $xr6, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr6, 102 +; LA64-NEXT: xvpermi.q $xr7, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr7, 119 +; LA64-NEXT: xvpermi.q $xr8, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr8, 136 +; LA64-NEXT: xvpermi.q $xr9, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr9, 153 +; LA64-NEXT: xvpermi.q $xr10, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr10, 170 +; LA64-NEXT: xvpermi.q $xr11, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr11, 187 +; LA64-NEXT: xvpermi.q $xr12, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr12, 204 +; LA64-NEXT: xvpermi.q $xr13, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr13, 221 +; LA64-NEXT: xvpermi.q $xr14, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr14, 238 +; LA64-NEXT: xvpermi.q $xr15, $xr0, 48 +; LA64-NEXT: xvextrins.b $xr0, $xr15, 255 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret +entry: + %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <32 x i8> %ins1, i8 %a2, i32 2 + %ins3 = insertelement <32 x i8> %ins2, i8 %a3, i32 3 + %ins4 = insertelement <32 x i8> %ins3, i8 %a4, i32 4 + %ins5 = insertelement <32 x i8> %ins4, i8 %a5, i32 5 + %ins6 = insertelement <32 x i8> %ins5, i8 %a6, i32 6 + %ins7 = insertelement <32 x i8> %ins6, i8 %a7, i32 7 + %ins8 = insertelement <32 x i8> %ins7, i8 %a8, i32 8 + %ins9 = insertelement <32 x i8> %ins8, i8 %a9, i32 9 + %ins10 = insertelement <32 x i8> %ins9, i8 %a10, i32 10 + %ins11 = insertelement <32 x i8> %ins10, i8 %a11, i32 11 + %ins12 = insertelement <32 x i8> %ins11, i8 %a12, i32 12 + %ins13 = insertelement <32 x i8> %ins12, i8 %a13, i32 13 + %ins14 = insertelement <32 x i8> %ins13, i8 %a14, i32 14 + %ins15 = insertelement <32 x i8> %ins14, i8 %a15, i32 15 + %ins16 = insertelement <32 x i8> %ins15, i8 %a0, i32 16 + %ins17 = insertelement <32 x i8> %ins16, i8 %a1, i32 17 + %ins18 = insertelement <32 x i8> %ins17, i8 %a2, i32 18 + %ins19 = insertelement <32 x i8> %ins18, i8 %a3, i32 19 + %ins20 = insertelement <32 x i8> %ins19, i8 %a4, i32 20 + %ins21 = insertelement <32 x i8> %ins20, i8 %a5, i32 21 + %ins22 = insertelement <32 x i8> %ins21, i8 %a6, i32 22 + %ins23 = insertelement <32 x i8> %ins22, i8 %a7, i32 23 + %ins24 = insertelement <32 x i8> %ins23, i8 %a8, i32 24 + %ins25 = insertelement <32 x i8> %ins24, i8 %a9, i32 25 + %ins26 = insertelement <32 x i8> %ins25, i8 %a10, i32 26 + %ins27 = insertelement <32 x i8> %ins26, i8 %a11, i32 27 + %ins28 = insertelement <32 x i8> %ins27, i8 %a12, i32 28 + %ins29 = insertelement <32 x i8> %ins28, i8 %a13, i32 29 + %ins30 = insertelement <32 x i8> %ins29, i8 %a14, i32 30 + %ins31 = insertelement <32 x i8> %ins30, i8 %a15, i32 31 + store <32 x i8> %ins31, ptr %dst + ret void +} + +define void @buildvector_v32i8_subseq_4(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7) nounwind { +; CHECK-LABEL: buildvector_v32i8_subseq_4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ld.h $t0, $sp, 64 -; CHECK-NEXT: ld.h $t1, $sp, 56 -; CHECK-NEXT: ld.h $t2, $sp, 48 -; CHECK-NEXT: ld.h $t3, $sp, 40 -; CHECK-NEXT: ld.h $t4, $sp, 32 -; CHECK-NEXT: ld.h $t5, $sp, 24 -; CHECK-NEXT: ld.h $t6, $sp, 16 -; CHECK-NEXT: ld.h $t7, $sp, 8 -; CHECK-NEXT: ld.h $t8, $sp, 0 -; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $a2 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 17 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $a3 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 34 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $a4 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 51 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $a5 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 68 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $a6 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 85 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $a7 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 102 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t8 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 119 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t7 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 0 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t6 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 17 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t5 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 34 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t4 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 51 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t3 -; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 68 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t2 +; CHECK-NEXT: ld.b $t0, $sp, 0 +; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr2, $a3 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 17 +; CHECK-NEXT: xvori.b $xr4, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr4, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr3, $a4 +; CHECK-NEXT: xvextrins.b $xr0, $xr4, 34 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr4, $a5 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 51 +; CHECK-NEXT: xvori.b $xr6, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr6, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr5, $a6 +; CHECK-NEXT: xvextrins.b $xr0, $xr6, 68 +; CHECK-NEXT: xvori.b $xr7, $xr5, 0 +; CHECK-NEXT: xvpermi.q $xr7, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr6, $a7 +; CHECK-NEXT: xvextrins.b $xr0, $xr7, 85 +; CHECK-NEXT: xvori.b $xr8, $xr6, 0 +; CHECK-NEXT: xvpermi.q $xr8, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr7, $t0 +; CHECK-NEXT: xvextrins.b $xr0, $xr8, 102 +; CHECK-NEXT: xvori.b $xr9, $xr7, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr8, $a1 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 119 +; CHECK-NEXT: xvori.b $xr9, $xr8, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 136 +; CHECK-NEXT: xvori.b $xr9, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 153 +; CHECK-NEXT: xvori.b $xr9, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 170 +; CHECK-NEXT: xvori.b $xr9, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 187 +; CHECK-NEXT: xvori.b $xr9, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 204 +; CHECK-NEXT: xvori.b $xr9, $xr5, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 221 +; CHECK-NEXT: xvori.b $xr9, $xr6, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 238 +; CHECK-NEXT: xvori.b $xr9, $xr7, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 255 +; CHECK-NEXT: xvori.b $xr9, $xr8, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 0 +; CHECK-NEXT: xvori.b $xr9, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 17 +; CHECK-NEXT: xvori.b $xr9, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 34 +; CHECK-NEXT: xvori.b $xr9, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 51 +; CHECK-NEXT: xvori.b $xr9, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 68 +; CHECK-NEXT: xvori.b $xr9, $xr5, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 85 +; CHECK-NEXT: xvori.b $xr9, $xr6, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 102 +; CHECK-NEXT: xvori.b $xr9, $xr7, 0 +; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr9, 119 +; CHECK-NEXT: xvpermi.q $xr8, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr8, 136 ; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 85 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t1 +; CHECK-NEXT: xvextrins.b $xr0, $xr1, 153 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr2, 170 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 187 +; CHECK-NEXT: xvpermi.q $xr4, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr4, 204 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 221 +; CHECK-NEXT: xvpermi.q $xr6, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr6, 238 +; CHECK-NEXT: xvpermi.q $xr7, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr7, 255 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <32 x i8> %ins1, i8 %a2, i32 2 + %ins3 = insertelement <32 x i8> %ins2, i8 %a3, i32 3 + %ins4 = insertelement <32 x i8> %ins3, i8 %a4, i32 4 + %ins5 = insertelement <32 x i8> %ins4, i8 %a5, i32 5 + %ins6 = insertelement <32 x i8> %ins5, i8 %a6, i32 6 + %ins7 = insertelement <32 x i8> %ins6, i8 %a7, i32 7 + %ins8 = insertelement <32 x i8> %ins7, i8 %a0, i32 8 + %ins9 = insertelement <32 x i8> %ins8, i8 %a1, i32 9 + %ins10 = insertelement <32 x i8> %ins9, i8 %a2, i32 10 + %ins11 = insertelement <32 x i8> %ins10, i8 %a3, i32 11 + %ins12 = insertelement <32 x i8> %ins11, i8 %a4, i32 12 + %ins13 = insertelement <32 x i8> %ins12, i8 %a5, i32 13 + %ins14 = insertelement <32 x i8> %ins13, i8 %a6, i32 14 + %ins15 = insertelement <32 x i8> %ins14, i8 %a7, i32 15 + %ins16 = insertelement <32 x i8> %ins15, i8 %a0, i32 16 + %ins17 = insertelement <32 x i8> %ins16, i8 %a1, i32 17 + %ins18 = insertelement <32 x i8> %ins17, i8 %a2, i32 18 + %ins19 = insertelement <32 x i8> %ins18, i8 %a3, i32 19 + %ins20 = insertelement <32 x i8> %ins19, i8 %a4, i32 20 + %ins21 = insertelement <32 x i8> %ins20, i8 %a5, i32 21 + %ins22 = insertelement <32 x i8> %ins21, i8 %a6, i32 22 + %ins23 = insertelement <32 x i8> %ins22, i8 %a7, i32 23 + %ins24 = insertelement <32 x i8> %ins23, i8 %a0, i32 24 + %ins25 = insertelement <32 x i8> %ins24, i8 %a1, i32 25 + %ins26 = insertelement <32 x i8> %ins25, i8 %a2, i32 26 + %ins27 = insertelement <32 x i8> %ins26, i8 %a3, i32 27 + %ins28 = insertelement <32 x i8> %ins27, i8 %a4, i32 28 + %ins29 = insertelement <32 x i8> %ins28, i8 %a5, i32 29 + %ins30 = insertelement <32 x i8> %ins29, i8 %a6, i32 30 + %ins31 = insertelement <32 x i8> %ins30, i8 %a7, i32 31 + store <32 x i8> %ins31, ptr %dst + ret void +} + +define void @buildvector_v32i8_subseq_8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3) nounwind { +; CHECK-LABEL: buildvector_v32i8_subseq_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr2, $a3 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 17 +; CHECK-NEXT: xvori.b $xr4, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr4, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr3, $a4 +; CHECK-NEXT: xvextrins.b $xr0, $xr4, 34 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr4, $a1 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 51 +; CHECK-NEXT: xvori.b $xr5, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 68 +; CHECK-NEXT: xvori.b $xr5, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 85 +; CHECK-NEXT: xvori.b $xr5, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 102 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 119 +; CHECK-NEXT: xvori.b $xr5, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 136 +; CHECK-NEXT: xvori.b $xr5, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 153 +; CHECK-NEXT: xvori.b $xr5, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 170 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 187 +; CHECK-NEXT: xvori.b $xr5, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 204 +; CHECK-NEXT: xvori.b $xr5, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 221 +; CHECK-NEXT: xvori.b $xr5, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 238 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 255 +; CHECK-NEXT: xvori.b $xr5, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 0 +; CHECK-NEXT: xvori.b $xr5, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 17 +; CHECK-NEXT: xvori.b $xr5, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 34 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 51 +; CHECK-NEXT: xvori.b $xr5, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 68 +; CHECK-NEXT: xvori.b $xr5, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 85 +; CHECK-NEXT: xvori.b $xr5, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 102 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 119 +; CHECK-NEXT: xvori.b $xr5, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 136 +; CHECK-NEXT: xvori.b $xr5, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 153 +; CHECK-NEXT: xvori.b $xr5, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 170 +; CHECK-NEXT: xvori.b $xr5, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr5, 187 +; CHECK-NEXT: xvpermi.q $xr4, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr4, 204 ; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 102 -; CHECK-NEXT: xvreplgr2vr.h $xr1, $t0 +; CHECK-NEXT: xvextrins.b $xr0, $xr1, 221 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr2, 238 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 255 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <32 x i8> %ins1, i8 %a2, i32 2 + %ins3 = insertelement <32 x i8> %ins2, i8 %a3, i32 3 + %ins4 = insertelement <32 x i8> %ins3, i8 %a0, i32 4 + %ins5 = insertelement <32 x i8> %ins4, i8 %a1, i32 5 + %ins6 = insertelement <32 x i8> %ins5, i8 %a2, i32 6 + %ins7 = insertelement <32 x i8> %ins6, i8 %a3, i32 7 + %ins8 = insertelement <32 x i8> %ins7, i8 %a0, i32 8 + %ins9 = insertelement <32 x i8> %ins8, i8 %a1, i32 9 + %ins10 = insertelement <32 x i8> %ins9, i8 %a2, i32 10 + %ins11 = insertelement <32 x i8> %ins10, i8 %a3, i32 11 + %ins12 = insertelement <32 x i8> %ins11, i8 %a0, i32 12 + %ins13 = insertelement <32 x i8> %ins12, i8 %a1, i32 13 + %ins14 = insertelement <32 x i8> %ins13, i8 %a2, i32 14 + %ins15 = insertelement <32 x i8> %ins14, i8 %a3, i32 15 + %ins16 = insertelement <32 x i8> %ins15, i8 %a0, i32 16 + %ins17 = insertelement <32 x i8> %ins16, i8 %a1, i32 17 + %ins18 = insertelement <32 x i8> %ins17, i8 %a2, i32 18 + %ins19 = insertelement <32 x i8> %ins18, i8 %a3, i32 19 + %ins20 = insertelement <32 x i8> %ins19, i8 %a0, i32 20 + %ins21 = insertelement <32 x i8> %ins20, i8 %a1, i32 21 + %ins22 = insertelement <32 x i8> %ins21, i8 %a2, i32 22 + %ins23 = insertelement <32 x i8> %ins22, i8 %a3, i32 23 + %ins24 = insertelement <32 x i8> %ins23, i8 %a0, i32 24 + %ins25 = insertelement <32 x i8> %ins24, i8 %a1, i32 25 + %ins26 = insertelement <32 x i8> %ins25, i8 %a2, i32 26 + %ins27 = insertelement <32 x i8> %ins26, i8 %a3, i32 27 + %ins28 = insertelement <32 x i8> %ins27, i8 %a0, i32 28 + %ins29 = insertelement <32 x i8> %ins28, i8 %a1, i32 29 + %ins30 = insertelement <32 x i8> %ins29, i8 %a2, i32 30 + %ins31 = insertelement <32 x i8> %ins30, i8 %a3, i32 31 + store <32 x i8> %ins31, ptr %dst + ret void +} + +define void @buildvector_v32i8_subseq_16(ptr %dst, i8 %a0, i8 %a1) nounwind { +; CHECK-LABEL: buildvector_v32i8_subseq_16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2 +; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.b $xr2, $a1 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 17 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 34 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 51 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 68 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 85 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 102 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 119 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 136 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 153 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 170 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 187 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 204 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 221 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 238 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 255 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 0 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 17 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 34 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 51 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 68 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 85 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 102 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 119 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 136 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 153 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 170 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 187 +; CHECK-NEXT: xvori.b $xr3, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 204 +; CHECK-NEXT: xvori.b $xr3, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr3, 221 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.b $xr0, $xr2, 238 ; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 -; CHECK-NEXT: xvextrins.h $xr0, $xr1, 119 +; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: + %ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0 + %ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1 + %ins2 = insertelement <32 x i8> %ins1, i8 %a0, i32 2 + %ins3 = insertelement <32 x i8> %ins2, i8 %a1, i32 3 + %ins4 = insertelement <32 x i8> %ins3, i8 %a0, i32 4 + %ins5 = insertelement <32 x i8> %ins4, i8 %a1, i32 5 + %ins6 = insertelement <32 x i8> %ins5, i8 %a0, i32 6 + %ins7 = insertelement <32 x i8> %ins6, i8 %a1, i32 7 + %ins8 = insertelement <32 x i8> %ins7, i8 %a0, i32 8 + %ins9 = insertelement <32 x i8> %ins8, i8 %a1, i32 9 + %ins10 = insertelement <32 x i8> %ins9, i8 %a0, i32 10 + %ins11 = insertelement <32 x i8> %ins10, i8 %a1, i32 11 + %ins12 = insertelement <32 x i8> %ins11, i8 %a0, i32 12 + %ins13 = insertelement <32 x i8> %ins12, i8 %a1, i32 13 + %ins14 = insertelement <32 x i8> %ins13, i8 %a0, i32 14 + %ins15 = insertelement <32 x i8> %ins14, i8 %a1, i32 15 + %ins16 = insertelement <32 x i8> %ins15, i8 %a0, i32 16 + %ins17 = insertelement <32 x i8> %ins16, i8 %a1, i32 17 + %ins18 = insertelement <32 x i8> %ins17, i8 %a0, i32 18 + %ins19 = insertelement <32 x i8> %ins18, i8 %a1, i32 19 + %ins20 = insertelement <32 x i8> %ins19, i8 %a0, i32 20 + %ins21 = insertelement <32 x i8> %ins20, i8 %a1, i32 21 + %ins22 = insertelement <32 x i8> %ins21, i8 %a0, i32 22 + %ins23 = insertelement <32 x i8> %ins22, i8 %a1, i32 23 + %ins24 = insertelement <32 x i8> %ins23, i8 %a0, i32 24 + %ins25 = insertelement <32 x i8> %ins24, i8 %a1, i32 25 + %ins26 = insertelement <32 x i8> %ins25, i8 %a0, i32 26 + %ins27 = insertelement <32 x i8> %ins26, i8 %a1, i32 27 + %ins28 = insertelement <32 x i8> %ins27, i8 %a0, i32 28 + %ins29 = insertelement <32 x i8> %ins28, i8 %a1, i32 29 + %ins30 = insertelement <32 x i8> %ins29, i8 %a0, i32 30 + %ins31 = insertelement <32 x i8> %ins30, i8 %a1, i32 31 + store <32 x i8> %ins31, ptr %dst + ret void +} + +define void @buildvector_v16i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind { +; LA32-LABEL: buildvector_v16i16: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.h $t0, $sp, 32 +; LA32-NEXT: ld.h $t1, $sp, 28 +; LA32-NEXT: ld.h $t2, $sp, 24 +; LA32-NEXT: ld.h $t3, $sp, 20 +; LA32-NEXT: ld.h $t4, $sp, 16 +; LA32-NEXT: ld.h $t5, $sp, 12 +; LA32-NEXT: ld.h $t6, $sp, 8 +; LA32-NEXT: ld.h $t7, $sp, 4 +; LA32-NEXT: ld.h $t8, $sp, 0 +; LA32-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; LA32-NEXT: xvreplgr2vr.h $xr1, $a2 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 17 +; LA32-NEXT: xvreplgr2vr.h $xr1, $a3 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 34 +; LA32-NEXT: xvreplgr2vr.h $xr1, $a4 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 51 +; LA32-NEXT: xvreplgr2vr.h $xr1, $a5 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 68 +; LA32-NEXT: xvreplgr2vr.h $xr1, $a6 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 85 +; LA32-NEXT: xvreplgr2vr.h $xr1, $a7 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 102 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t8 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 119 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t7 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 0 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t6 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 17 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t5 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 34 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t4 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 51 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t3 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 68 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t2 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 85 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t1 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 102 +; LA32-NEXT: xvreplgr2vr.h $xr1, $t0 +; LA32-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA32-NEXT: xvextrins.h $xr0, $xr1, 119 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v16i16: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ld.h $t0, $sp, 64 +; LA64-NEXT: ld.h $t1, $sp, 56 +; LA64-NEXT: ld.h $t2, $sp, 48 +; LA64-NEXT: ld.h $t3, $sp, 40 +; LA64-NEXT: ld.h $t4, $sp, 32 +; LA64-NEXT: ld.h $t5, $sp, 24 +; LA64-NEXT: ld.h $t6, $sp, 16 +; LA64-NEXT: ld.h $t7, $sp, 8 +; LA64-NEXT: ld.h $t8, $sp, 0 +; LA64-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; LA64-NEXT: xvreplgr2vr.h $xr1, $a2 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 17 +; LA64-NEXT: xvreplgr2vr.h $xr1, $a3 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 34 +; LA64-NEXT: xvreplgr2vr.h $xr1, $a4 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 51 +; LA64-NEXT: xvreplgr2vr.h $xr1, $a5 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 68 +; LA64-NEXT: xvreplgr2vr.h $xr1, $a6 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 85 +; LA64-NEXT: xvreplgr2vr.h $xr1, $a7 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 102 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t8 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 18 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 119 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t7 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 0 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t6 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 17 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t5 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 34 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t4 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 51 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t3 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 68 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t2 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 85 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t1 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 102 +; LA64-NEXT: xvreplgr2vr.h $xr1, $t0 +; LA64-NEXT: xvpermi.q $xr1, $xr0, 48 +; LA64-NEXT: xvextrins.h $xr0, $xr1, 119 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret +entry: %ins0 = insertelement <16 x i16> undef, i16 %a0, i32 0 %ins1 = insertelement <16 x i16> %ins0, i16 %a1, i32 1 %ins2 = insertelement <16 x i16> %ins1, i16 %a2, i32 2 @@ -763,6 +1763,223 @@ entry: ret void } +define void @buildvector_v16i16_subseq_2(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind { +; CHECK-LABEL: buildvector_v16i16_subseq_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: ld.h $t0, $sp, 0 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a2 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; CHECK-NEXT: xvori.b $xr2, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr3, $a3 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 17 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr4, $a4 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 34 +; CHECK-NEXT: xvori.b $xr2, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr5, $a5 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 51 +; CHECK-NEXT: xvori.b $xr2, $xr5, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr6, $a6 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 68 +; CHECK-NEXT: xvori.b $xr2, $xr6, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr7, $a7 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 85 +; CHECK-NEXT: xvori.b $xr2, $xr7, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr8, $t0 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 102 +; CHECK-NEXT: xvori.b $xr2, $xr8, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 119 +; CHECK-NEXT: xvreplgr2vr.h $xr2, $a1 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 17 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr3, 34 +; CHECK-NEXT: xvpermi.q $xr4, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr4, 51 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr5, 68 +; CHECK-NEXT: xvpermi.q $xr6, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr6, 85 +; CHECK-NEXT: xvpermi.q $xr7, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr7, 102 +; CHECK-NEXT: xvpermi.q $xr8, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr8, 119 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i16> undef, i16 %a0, i32 0 + %ins1 = insertelement <16 x i16> %ins0, i16 %a1, i32 1 + %ins2 = insertelement <16 x i16> %ins1, i16 %a2, i32 2 + %ins3 = insertelement <16 x i16> %ins2, i16 %a3, i32 3 + %ins4 = insertelement <16 x i16> %ins3, i16 %a4, i32 4 + %ins5 = insertelement <16 x i16> %ins4, i16 %a5, i32 5 + %ins6 = insertelement <16 x i16> %ins5, i16 %a6, i32 6 + %ins7 = insertelement <16 x i16> %ins6, i16 %a7, i32 7 + %ins8 = insertelement <16 x i16> %ins7, i16 %a0, i32 8 + %ins9 = insertelement <16 x i16> %ins8, i16 %a1, i32 9 + %ins10 = insertelement <16 x i16> %ins9, i16 %a2, i32 10 + %ins11 = insertelement <16 x i16> %ins10, i16 %a3, i32 11 + %ins12 = insertelement <16 x i16> %ins11, i16 %a4, i32 12 + %ins13 = insertelement <16 x i16> %ins12, i16 %a5, i32 13 + %ins14 = insertelement <16 x i16> %ins13, i16 %a6, i32 14 + %ins15 = insertelement <16 x i16> %ins14, i16 %a7, i32 15 + store <16 x i16> %ins15, ptr %dst + ret void +} + +define void @buildvector_v16i16_subseq_4(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3) nounwind { +; CHECK-LABEL: buildvector_v16i16_subseq_4: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a2 +; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0 +; CHECK-NEXT: xvori.b $xr2, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr3, $a3 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 17 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr4, $a4 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 34 +; CHECK-NEXT: xvori.b $xr2, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr5, $a1 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 51 +; CHECK-NEXT: xvori.b $xr2, $xr5, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 68 +; CHECK-NEXT: xvori.b $xr2, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 85 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 102 +; CHECK-NEXT: xvori.b $xr2, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 119 +; CHECK-NEXT: xvori.b $xr2, $xr5, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 0 +; CHECK-NEXT: xvori.b $xr2, $xr1, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 17 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 34 +; CHECK-NEXT: xvori.b $xr2, $xr4, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr2, 51 +; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr5, 68 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 85 +; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr3, 102 +; CHECK-NEXT: xvpermi.q $xr4, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr4, 119 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i16> undef, i16 %a0, i32 0 + %ins1 = insertelement <16 x i16> %ins0, i16 %a1, i32 1 + %ins2 = insertelement <16 x i16> %ins1, i16 %a2, i32 2 + %ins3 = insertelement <16 x i16> %ins2, i16 %a3, i32 3 + %ins4 = insertelement <16 x i16> %ins3, i16 %a0, i32 4 + %ins5 = insertelement <16 x i16> %ins4, i16 %a1, i32 5 + %ins6 = insertelement <16 x i16> %ins5, i16 %a2, i32 6 + %ins7 = insertelement <16 x i16> %ins6, i16 %a3, i32 7 + %ins8 = insertelement <16 x i16> %ins7, i16 %a0, i32 8 + %ins9 = insertelement <16 x i16> %ins8, i16 %a1, i32 9 + %ins10 = insertelement <16 x i16> %ins9, i16 %a2, i32 10 + %ins11 = insertelement <16 x i16> %ins10, i16 %a3, i32 11 + %ins12 = insertelement <16 x i16> %ins11, i16 %a0, i32 12 + %ins13 = insertelement <16 x i16> %ins12, i16 %a1, i32 13 + %ins14 = insertelement <16 x i16> %ins13, i16 %a2, i32 14 + %ins15 = insertelement <16 x i16> %ins14, i16 %a3, i32 15 + store <16 x i16> %ins15, ptr %dst + ret void +} + +define void @buildvector_v16i16_subseq_8(ptr %dst, i16 %a0, i16 %a1) nounwind { +; CHECK-LABEL: buildvector_v16i16_subseq_8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvreplgr2vr.h $xr0, $a2 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 18 +; CHECK-NEXT: xvreplgr2vr.h $xr3, $a1 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 17 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 18 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 34 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 18 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 51 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 18 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 68 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 18 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 85 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 18 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 102 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 18 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 119 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 0 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 17 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 34 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 51 +; CHECK-NEXT: xvori.b $xr2, $xr3, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 68 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr2, 85 +; CHECK-NEXT: xvpermi.q $xr3, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr3, 102 +; CHECK-NEXT: xvpermi.q $xr0, $xr1, 48 +; CHECK-NEXT: xvextrins.h $xr1, $xr0, 119 +; CHECK-NEXT: xvst $xr1, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <16 x i16> undef, i16 %a0, i32 0 + %ins1 = insertelement <16 x i16> %ins0, i16 %a1, i32 1 + %ins2 = insertelement <16 x i16> %ins1, i16 %a0, i32 2 + %ins3 = insertelement <16 x i16> %ins2, i16 %a1, i32 3 + %ins4 = insertelement <16 x i16> %ins3, i16 %a0, i32 4 + %ins5 = insertelement <16 x i16> %ins4, i16 %a1, i32 5 + %ins6 = insertelement <16 x i16> %ins5, i16 %a0, i32 6 + %ins7 = insertelement <16 x i16> %ins6, i16 %a1, i32 7 + %ins8 = insertelement <16 x i16> %ins7, i16 %a0, i32 8 + %ins9 = insertelement <16 x i16> %ins8, i16 %a1, i32 9 + %ins10 = insertelement <16 x i16> %ins9, i16 %a0, i32 10 + %ins11 = insertelement <16 x i16> %ins10, i16 %a1, i32 11 + %ins12 = insertelement <16 x i16> %ins11, i16 %a0, i32 12 + %ins13 = insertelement <16 x i16> %ins12, i16 %a1, i32 13 + %ins14 = insertelement <16 x i16> %ins13, i16 %a0, i32 14 + %ins15 = insertelement <16 x i16> %ins14, i16 %a1, i32 15 + store <16 x i16> %ins15, ptr %dst + ret void +} + define void @buildvector_v8i32(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) nounwind { ; CHECK-LABEL: buildvector_v8i32: ; CHECK: # %bb.0: # %entry @@ -835,16 +2052,82 @@ entry: ret void } -define void @buildvector_v4i64(ptr %dst, i64 %a0, i64 %a1, i64 %a2, i64 %a3) nounwind { -; CHECK-LABEL: buildvector_v4i64: +define void @buildvector_v8i32_subseq_2(ptr %dst, i32 %a0, i32 %a1, i32 %a2, i32 %a3) nounwind { +; CHECK-LABEL: buildvector_v8i32_subseq_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a3, 2 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a4, 3 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 5 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a3, 6 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a4, 7 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x i32> undef, i32 %a0, i32 0 + %ins1 = insertelement <8 x i32> %ins0, i32 %a1, i32 1 + %ins2 = insertelement <8 x i32> %ins1, i32 %a2, i32 2 + %ins3 = insertelement <8 x i32> %ins2, i32 %a3, i32 3 + %ins4 = insertelement <8 x i32> %ins3, i32 %a0, i32 4 + %ins5 = insertelement <8 x i32> %ins4, i32 %a1, i32 5 + %ins6 = insertelement <8 x i32> %ins5, i32 %a2, i32 6 + %ins7 = insertelement <8 x i32> %ins6, i32 %a3, i32 7 + store <8 x i32> %ins7, ptr %dst + ret void +} + +define void @buildvector_v8i32_subseq_4(ptr %dst, i32 %a0, i32 %a1) nounwind { +; CHECK-LABEL: buildvector_v8i32_subseq_4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 0 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 1 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a3, 2 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a4, 3 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 2 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 3 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 5 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a1, 6 +; CHECK-NEXT: xvinsgr2vr.w $xr0, $a2, 7 ; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: + %ins0 = insertelement <8 x i32> undef, i32 %a0, i32 0 + %ins1 = insertelement <8 x i32> %ins0, i32 %a1, i32 1 + %ins2 = insertelement <8 x i32> %ins1, i32 %a0, i32 2 + %ins3 = insertelement <8 x i32> %ins2, i32 %a1, i32 3 + %ins4 = insertelement <8 x i32> %ins3, i32 %a0, i32 4 + %ins5 = insertelement <8 x i32> %ins4, i32 %a1, i32 5 + %ins6 = insertelement <8 x i32> %ins5, i32 %a0, i32 6 + %ins7 = insertelement <8 x i32> %ins6, i32 %a1, i32 7 + store <8 x i32> %ins7, ptr %dst + ret void +} + +define void @buildvector_v4i64(ptr %dst, i64 %a0, i64 %a1, i64 %a2, i64 %a3) nounwind { +; LA32-LABEL: buildvector_v4i64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ld.w $t0, $sp, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a5, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a6, 5 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a7, 6 +; LA32-NEXT: xvinsgr2vr.w $xr0, $t0, 7 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v4i64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 0 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 1 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a3, 2 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a4, 3 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret +entry: %ins0 = insertelement <4 x i64> undef, i64 %a0, i32 0 %ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 1 %ins2 = insertelement <4 x i64> %ins1, i64 %a2, i32 2 @@ -854,12 +2137,21 @@ entry: } define void @buildvector_v4i64_partial(ptr %dst, i64 %a1, i64 %a2) nounwind { -; CHECK-LABEL: buildvector_v4i64_partial: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 1 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 2 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v4i64_partial: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 5 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v4i64_partial: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 1 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 2 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %ins0 = insertelement <4 x i64> undef, i64 undef, i32 0 %ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 1 @@ -870,13 +2162,23 @@ entry: } define void @buildvector_v4i64_with_constant(ptr %dst, i64 %a0, i64 %a2) nounwind { -; CHECK-LABEL: buildvector_v4i64_with_constant: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvrepli.b $xr0, 0 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 0 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 2 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: buildvector_v4i64_with_constant: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvrepli.b $xr0, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 5 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v4i64_with_constant: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvrepli.b $xr0, 0 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 0 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 2 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %ins0 = insertelement <4 x i64> undef, i64 %a0, i32 0 %ins1 = insertelement <4 x i64> %ins0, i64 0, i32 1 @@ -886,6 +2188,37 @@ entry: ret void } +define void @buildvector_v4i64_subseq_2(ptr %dst, i64 %a0, i64 %a1) nounwind { +; LA32-LABEL: buildvector_v4i64_subseq_2: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 3 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 5 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 6 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 7 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: buildvector_v4i64_subseq_2: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 0 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 1 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 2 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 3 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret +entry: + %ins0 = insertelement <4 x i64> undef, i64 %a0, i32 0 + %ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 1 + %ins2 = insertelement <4 x i64> %ins1, i64 %a0, i32 2 + %ins3 = insertelement <4 x i64> %ins2, i64 %a1, i32 3 + store <4 x i64> %ins3, ptr %dst + ret void +} + define void @buildvector_v8f32(ptr %dst, float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) nounwind { ; CHECK-LABEL: buildvector_v8f32: ; CHECK: # %bb.0: # %entry @@ -973,6 +2306,64 @@ entry: ret void } +define void @buildvector_v8f32_subseq_2(ptr %dst, float %a0, float %a1, float %a2, float %a3) nounwind { +; CHECK-LABEL: buildvector_v8f32_subseq_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f3 killed $f3 def $xr3 +; CHECK-NEXT: # kill: def $f2 killed $f2 def $xr2 +; CHECK-NEXT: # kill: def $f1 killed $f1 def $xr1 +; CHECK-NEXT: # kill: def $f0 killed $f0 def $xr0 +; CHECK-NEXT: xvori.b $xr4, $xr0, 0 +; CHECK-NEXT: xvinsve0.w $xr4, $xr1, 1 +; CHECK-NEXT: xvinsve0.w $xr4, $xr2, 2 +; CHECK-NEXT: xvinsve0.w $xr4, $xr3, 3 +; CHECK-NEXT: xvinsve0.w $xr4, $xr0, 4 +; CHECK-NEXT: xvinsve0.w $xr4, $xr1, 5 +; CHECK-NEXT: xvinsve0.w $xr4, $xr2, 6 +; CHECK-NEXT: xvinsve0.w $xr4, $xr3, 7 +; CHECK-NEXT: xvst $xr4, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x float> undef, float %a0, i32 0 + %ins1 = insertelement <8 x float> %ins0, float %a1, i32 1 + %ins2 = insertelement <8 x float> %ins1, float %a2, i32 2 + %ins3 = insertelement <8 x float> %ins2, float %a3, i32 3 + %ins4 = insertelement <8 x float> %ins3, float %a0, i32 4 + %ins5 = insertelement <8 x float> %ins4, float %a1, i32 5 + %ins6 = insertelement <8 x float> %ins5, float %a2, i32 6 + %ins7 = insertelement <8 x float> %ins6, float %a3, i32 7 + store <8 x float> %ins7, ptr %dst + ret void +} + +define void @buildvector_v8f32_subseq_4(ptr %dst, float %a0, float %a1) nounwind { +; CHECK-LABEL: buildvector_v8f32_subseq_4: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f1 killed $f1 def $xr1 +; CHECK-NEXT: # kill: def $f0 killed $f0 def $xr0 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvinsve0.w $xr2, $xr1, 1 +; CHECK-NEXT: xvinsve0.w $xr2, $xr0, 2 +; CHECK-NEXT: xvinsve0.w $xr2, $xr1, 3 +; CHECK-NEXT: xvinsve0.w $xr2, $xr0, 4 +; CHECK-NEXT: xvinsve0.w $xr2, $xr1, 5 +; CHECK-NEXT: xvinsve0.w $xr2, $xr0, 6 +; CHECK-NEXT: xvinsve0.w $xr2, $xr1, 7 +; CHECK-NEXT: xvst $xr2, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <8 x float> undef, float %a0, i32 0 + %ins1 = insertelement <8 x float> %ins0, float %a1, i32 1 + %ins2 = insertelement <8 x float> %ins1, float %a0, i32 2 + %ins3 = insertelement <8 x float> %ins2, float %a1, i32 3 + %ins4 = insertelement <8 x float> %ins3, float %a0, i32 4 + %ins5 = insertelement <8 x float> %ins4, float %a1, i32 5 + %ins6 = insertelement <8 x float> %ins5, float %a0, i32 6 + %ins7 = insertelement <8 x float> %ins6, float %a1, i32 7 + store <8 x float> %ins7, ptr %dst + ret void +} + define void @buildvector_v4f64(ptr %dst, double %a0, double %a1, double %a2, double %a3) nounwind { ; CHECK-LABEL: buildvector_v4f64: ; CHECK: # %bb.0: # %entry @@ -1029,3 +2420,23 @@ entry: store <4 x double> %ins3, ptr %dst ret void } + +define void @buildvector_v4f64_subseq_2(ptr %dst, double %a0, double %a1) nounwind { +; CHECK-LABEL: buildvector_v4f64_subseq_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 def $xr1 +; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $xr0 +; CHECK-NEXT: xvori.b $xr2, $xr0, 0 +; CHECK-NEXT: xvinsve0.d $xr2, $xr1, 1 +; CHECK-NEXT: xvinsve0.d $xr2, $xr0, 2 +; CHECK-NEXT: xvinsve0.d $xr2, $xr1, 3 +; CHECK-NEXT: xvst $xr2, $a0, 0 +; CHECK-NEXT: ret +entry: + %ins0 = insertelement <4 x double> undef, double %a0, i32 0 + %ins1 = insertelement <4 x double> %ins0, double %a1, i32 1 + %ins2 = insertelement <4 x double> %ins1, double %a0, i32 2 + %ins3 = insertelement <4 x double> %ins2, double %a1, i32 3 + store <4 x double> %ins3, ptr %dst + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll b/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll index 231e82a6d53a..d1868a949a07 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define <32 x i8> @concat_poison_v32i8_1(<16 x i8> %a) { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll b/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll index 7786e399c95f..ba2118fb94f6 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @ctpop_v32i8(ptr %src, ptr %dst) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll index 769d9ef81faf..7514dafa8000 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll @@ -1,25 +1,27 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT -; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA32 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA64 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @fdiv_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { ; FAULT-LABEL: fdiv_v8f32: -; FAULT: # %bb.0: -; FAULT-NEXT: xvld $xr0, $a1, 0 -; FAULT-NEXT: xvld $xr1, $a2, 0 -; FAULT-NEXT: xvfdiv.s $xr0, $xr0, $xr1 -; FAULT-NEXT: xvst $xr0, $a0, 0 +; FAULT: # %bb.0: # %entry +; FAULT-NEXT: xvld $xr0, $a1, 0 +; FAULT-NEXT: xvld $xr1, $a2, 0 +; FAULT-NEXT: xvfdiv.s $xr0, $xr0, $xr1 +; FAULT-NEXT: xvst $xr0, $a0, 0 ; FAULT-NEXT: ret ; ; CHECK-LABEL: fdiv_v8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a2, 0 -; CHECK-NEXT: xvld $xr1, $a1, 0 -; CHECK-NEXT: xvfrecipe.s $xr2, $xr0 -; CHECK-NEXT: xvfmul.s $xr3, $xr1, $xr2 -; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr3, $xr1 -; CHECK-NEXT: xvfmadd.s $xr0, $xr2, $xr0, $xr3 -; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: xvld $xr0, $a2, 0 +; CHECK-NEXT: xvld $xr1, $a1, 0 +; CHECK-NEXT: xvfrecipe.s $xr2, $xr0 +; CHECK-NEXT: xvfmul.s $xr3, $xr1, $xr2 +; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr3, $xr1 +; CHECK-NEXT: xvfmadd.s $xr0, $xr2, $xr0, $xr3 +; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 @@ -31,27 +33,42 @@ entry: define void @fdiv_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind { ; FAULT-LABEL: fdiv_v4f64: -; FAULT: # %bb.0: -; FAULT-NEXT: xvld $xr0, $a1, 0 -; FAULT-NEXT: xvld $xr1, $a2, 0 -; FAULT-NEXT: xvfdiv.d $xr0, $xr0, $xr1 -; FAULT-NEXT: xvst $xr0, $a0, 0 +; FAULT: # %bb.0: # %entry +; FAULT-NEXT: xvld $xr0, $a1, 0 +; FAULT-NEXT: xvld $xr1, $a2, 0 +; FAULT-NEXT: xvfdiv.d $xr0, $xr0, $xr1 +; FAULT-NEXT: xvst $xr0, $a0, 0 ; FAULT-NEXT: ret ; -; CHECK-LABEL: fdiv_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a2, 0 -; CHECK-NEXT: xvld $xr1, $a1, 0 -; CHECK-NEXT: lu52i.d $a1, $zero, -1025 -; CHECK-NEXT: xvreplgr2vr.d $xr2, $a1 -; CHECK-NEXT: xvfrecipe.d $xr3, $xr0 -; CHECK-NEXT: xvfmadd.d $xr2, $xr0, $xr3, $xr2 -; CHECK-NEXT: xvfnmsub.d $xr2, $xr2, $xr3, $xr3 -; CHECK-NEXT: xvfmul.d $xr3, $xr1, $xr2 -; CHECK-NEXT: xvfnmsub.d $xr0, $xr0, $xr3, $xr1 -; CHECK-NEXT: xvfmadd.d $xr0, $xr2, $xr0, $xr3 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: fdiv_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI1_0) +; LA32-NEXT: xvld $xr0, $a2, 0 +; LA32-NEXT: xvld $xr1, $a3, %pc_lo12(.LCPI1_0) +; LA32-NEXT: xvld $xr2, $a1, 0 +; LA32-NEXT: xvfrecipe.d $xr3, $xr0 +; LA32-NEXT: xvfmadd.d $xr1, $xr0, $xr3, $xr1 +; LA32-NEXT: xvfnmsub.d $xr1, $xr1, $xr3, $xr3 +; LA32-NEXT: xvfmul.d $xr3, $xr2, $xr1 +; LA32-NEXT: xvfnmsub.d $xr0, $xr0, $xr3, $xr2 +; LA32-NEXT: xvfmadd.d $xr0, $xr1, $xr0, $xr3 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: fdiv_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a2, 0 +; LA64-NEXT: xvld $xr1, $a1, 0 +; LA64-NEXT: lu52i.d $a1, $zero, -1025 +; LA64-NEXT: xvreplgr2vr.d $xr2, $a1 +; LA64-NEXT: xvfrecipe.d $xr3, $xr0 +; LA64-NEXT: xvfmadd.d $xr2, $xr0, $xr3, $xr2 +; LA64-NEXT: xvfnmsub.d $xr2, $xr2, $xr3, $xr3 +; LA64-NEXT: xvfmul.d $xr3, $xr1, $xr2 +; LA64-NEXT: xvfnmsub.d $xr0, $xr0, $xr3, $xr1 +; LA64-NEXT: xvfmadd.d $xr0, $xr2, $xr0, $xr3 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -63,21 +80,21 @@ entry: ;; 1.0 / vec define void @one_fdiv_v8f32(ptr %res, ptr %a0) nounwind { ; FAULT-LABEL: one_fdiv_v8f32: -; FAULT: # %bb.0: -; FAULT-NEXT: xvld $xr0, $a1, 0 -; FAULT-NEXT: xvfrecip.s $xr0, $xr0 -; FAULT-NEXT: xvst $xr0, $a0, 0 +; FAULT: # %bb.0: # %entry +; FAULT-NEXT: xvld $xr0, $a1, 0 +; FAULT-NEXT: xvfrecip.s $xr0, $xr0 +; FAULT-NEXT: xvst $xr0, $a0, 0 ; FAULT-NEXT: ret ; ; CHECK-LABEL: one_fdiv_v8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfrecipe.s $xr1, $xr0 -; CHECK-NEXT: lu12i.w $a1, -264192 -; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1 -; CHECK-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvfrecipe.s $xr1, $xr0 +; CHECK-NEXT: lu12i.w $a1, -264192 +; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1 +; CHECK-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 ; CHECK-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 @@ -87,25 +104,47 @@ entry: } define void @one_fdiv_v4f64(ptr %res, ptr %a0) nounwind { -; FAULT-LABEL: one_fdiv_v4f64: -; FAULT: # %bb.0: -; FAULT-NEXT: xvld $xr0, $a1, 0 -; FAULT-NEXT: xvfrecip.d $xr0, $xr0 -; FAULT-NEXT: xvst $xr0, $a0, 0 -; FAULT-NEXT: ret +; FAULT-LA32-LABEL: one_fdiv_v4f64: +; FAULT-LA32: # %bb.0: # %entry +; FAULT-LA32-NEXT: xvld $xr0, $a1, 0 +; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; FAULT-LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0) +; FAULT-LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0 +; FAULT-LA32-NEXT: xvst $xr0, $a0, 0 +; FAULT-LA32-NEXT: ret ; -; CHECK-LABEL: one_fdiv_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfrecipe.d $xr1, $xr0 -; CHECK-NEXT: lu52i.d $a1, $zero, 1023 -; CHECK-NEXT: xvreplgr2vr.d $xr2, $a1 -; CHECK-NEXT: xvfnmsub.d $xr3, $xr0, $xr1, $xr2 -; CHECK-NEXT: xvfmadd.d $xr1, $xr1, $xr3, $xr1 -; CHECK-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CHECK-NEXT: xvfmadd.d $xr0, $xr1, $xr0, $xr1 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_fdiv_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: xvfrecipe.d $xr2, $xr0 +; LA32-NEXT: xvfnmsub.d $xr3, $xr0, $xr2, $xr1 +; LA32-NEXT: xvfmadd.d $xr2, $xr2, $xr3, $xr2 +; LA32-NEXT: xvfnmsub.d $xr0, $xr0, $xr2, $xr1 +; LA32-NEXT: xvfmadd.d $xr0, $xr2, $xr0, $xr2 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; FAULT-LA64-LABEL: one_fdiv_v4f64: +; FAULT-LA64: # %bb.0: # %entry +; FAULT-LA64-NEXT: xvld $xr0, $a1, 0 +; FAULT-LA64-NEXT: xvfrecip.d $xr0, $xr0 +; FAULT-LA64-NEXT: xvst $xr0, $a0, 0 +; FAULT-LA64-NEXT: ret +; +; LA64-LABEL: one_fdiv_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfrecipe.d $xr1, $xr0 +; LA64-NEXT: lu52i.d $a1, $zero, 1023 +; LA64-NEXT: xvreplgr2vr.d $xr2, $a1 +; LA64-NEXT: xvfnmsub.d $xr3, $xr0, $xr1, $xr2 +; LA64-NEXT: xvfmadd.d $xr1, $xr1, $xr3, $xr1 +; LA64-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-NEXT: xvfmadd.d $xr0, $xr1, $xr0, $xr1 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %div = fdiv fast <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, %v0 diff --git a/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll b/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll index 0f3df3d573b6..8e1ba7ea1601 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll @@ -1,40 +1,75 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=fast < %s \ +; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-FAST +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=on < %s \ +; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-ON +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=off < %s \ +; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-OFF ; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=fast < %s \ -; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST +; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-FAST ; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=on < %s \ -; RUN: | FileCheck %s --check-prefix=CONTRACT-ON +; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-ON ; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=off < %s \ -; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF +; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-OFF define void @xvfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmadd_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmadd_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmadd_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmadd_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmadd_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmadd_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmadd_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmadd_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmadd_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -46,34 +81,63 @@ entry: } define void @xvfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmsub_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmsub_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmsub_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmsub_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmsub_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmsub_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmsub_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmsub_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmsub_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -85,36 +149,67 @@ entry: } define void @xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmadd_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmadd_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmadd_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmadd_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmadd_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmadd_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmadd_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmadd_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmadd_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -127,36 +222,67 @@ entry: } define void @xvfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmadd_d_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmadd_d_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmadd_d_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmadd_d_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmadd_d_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmadd_d_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmadd_d_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmadd_d_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmadd_d_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -171,37 +297,69 @@ entry: ;; Check that xvfnmadd.d is not emitted. define void @not_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_xvfnmadd_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_xvfnmadd_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_xvfnmadd_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_xvfnmadd_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_xvfnmadd_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_xvfnmadd_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_xvfnmadd_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_xvfnmadd_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_xvfnmadd_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -215,36 +373,67 @@ entry: } define void @xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmsub_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmsub_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmsub_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmsub_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmsub_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmsub_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmsub_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmsub_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmsub_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -258,34 +447,63 @@ entry: } define void @xvfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmsub_d_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmsub_d_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmsub_d_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmsub_d_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmsub_d_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmsub_d_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmsub_d_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmsub_d_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmsub_d_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -299,35 +517,65 @@ entry: ;; Check that xvfnmsub.d is not emitted. define void @not_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_xvfnmsub_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_xvfnmsub_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_xvfnmsub_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_xvfnmsub_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_xvfnmsub_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_xvfnmsub_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_xvfnmsub_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_xvfnmsub_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_xvfnmsub_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -340,32 +588,59 @@ entry: } define void @contract_xvfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfmadd_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfmadd_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfmadd_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfmadd_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfmadd_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfmadd_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfmadd_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfmadd_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfmadd_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -377,32 +652,59 @@ entry: } define void @contract_xvfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfmsub_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfmsub_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfmsub_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfmsub_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfmsub_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfmsub_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfmsub_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfmsub_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfmsub_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -414,32 +716,59 @@ entry: } define void @contract_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmadd_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmadd_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmadd_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -452,32 +781,59 @@ entry: } define void @contract_xvfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmadd_d_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmadd_d_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmadd_d_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_d_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_d_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_d_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_d_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_d_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_d_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -492,35 +848,65 @@ entry: ;; Check that xvfnmadd.d is not emitted. define void @not_contract_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_contract_xvfnmadd_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_contract_xvfnmadd_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_contract_xvfnmadd_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmadd_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmadd_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -534,32 +920,59 @@ entry: } define void @contract_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmsub_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmsub_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmsub_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -573,32 +986,59 @@ entry: } define void @contract_xvfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmsub_d_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmsub_d_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmsub_d_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_d_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_d_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_d_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_d_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_d_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_d_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -612,35 +1052,65 @@ entry: ;; Check that xvfnmsub.d is not emitted. define void @not_contract_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_contract_xvfnmsub_d: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_contract_xvfnmsub_d: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_contract_xvfnmsub_d: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 -; CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_d: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmsub_d: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_d: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA32-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_d: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmsub_d: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_d: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63 +; LA64-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -653,32 +1123,59 @@ entry: } define void @xvfmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmadd_d_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmadd_d_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmadd_d_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmadd_d_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmadd_d_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmadd_d_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmadd_d_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmadd_d_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmadd_d_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -690,32 +1187,59 @@ entry: } define void @xvfmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmsub_d_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmsub_d_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmsub_d_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmsub_d_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmsub_d_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmsub_d_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmsub_d_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmsub_d_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmsub_d_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -727,32 +1251,59 @@ entry: } define void @xvfnmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmadd_d_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmadd_d_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmadd_d_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmadd_d_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmadd_d_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmadd_d_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmadd_d_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmadd_d_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmadd_d_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 @@ -765,32 +1316,59 @@ entry: } define void @xvfnmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmsub_d_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmsub_d_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmsub_d_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmsub_d_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmsub_d_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmsub_d_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmsub_d_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmsub_d_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmsub_d_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %v1 = load <4 x double>, ptr %a1 diff --git a/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll b/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll index 6fd14d93a751..57b283801675 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll @@ -1,40 +1,75 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=fast < %s \ +; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-FAST +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=on < %s \ +; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-ON +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=off < %s \ +; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-OFF ; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=fast < %s \ -; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST +; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-FAST ; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=on < %s \ -; RUN: | FileCheck %s --check-prefix=CONTRACT-ON +; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-ON ; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=off < %s \ -; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF +; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-OFF define void @xvfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmadd_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmadd_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmadd_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmadd_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmadd_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmadd_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmadd_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmadd_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmadd_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -46,34 +81,63 @@ entry: } define void @xvfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmsub_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmsub_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmsub_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmsub_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmsub_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmsub_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmsub_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmsub_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmsub_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -85,36 +149,67 @@ entry: } define void @xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmadd_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmadd_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmadd_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmadd_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmadd_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmadd_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmadd_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmadd_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmadd_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -127,36 +222,67 @@ entry: } define void @xvfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmadd_s_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmadd_s_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmadd_s_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmadd_s_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmadd_s_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmadd_s_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmadd_s_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmadd_s_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmadd_s_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -171,37 +297,69 @@ entry: ;; Check that fnmadd.s is not emitted. define void @not_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_xvfnmadd_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_xvfnmadd_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_xvfnmadd_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_xvfnmadd_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_xvfnmadd_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_xvfnmadd_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_xvfnmadd_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_xvfnmadd_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_xvfnmadd_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -215,36 +373,67 @@ entry: } define void @xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmsub_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmsub_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmsub_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 -; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmsub_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmsub_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmsub_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmsub_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmsub_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmsub_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -258,34 +447,63 @@ entry: } define void @xvfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmsub_s_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmsub_s_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmsub_s_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmsub_s_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmsub_s_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmsub_s_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmsub_s_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmsub_s_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmsub_s_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -299,35 +517,65 @@ entry: ;; Check that fnmsub.s is not emitted. define void @not_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_xvfnmsub_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_xvfnmsub_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_xvfnmsub_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_xvfnmsub_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_xvfnmsub_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_xvfnmsub_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_xvfnmsub_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_xvfnmsub_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_xvfnmsub_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -340,32 +588,59 @@ entry: } define void @contract_xvfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfmadd_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfmadd_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfmadd_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfmadd_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfmadd_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfmadd_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfmadd_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfmadd_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfmadd_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -377,32 +652,59 @@ entry: } define void @contract_xvfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfmsub_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfmsub_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfmsub_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfmsub_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfmsub_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfmsub_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfmsub_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfmsub_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfmsub_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -414,32 +716,59 @@ entry: } define void @contract_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmadd_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmadd_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmadd_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -452,32 +781,59 @@ entry: } define void @contract_xvfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmadd_s_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmadd_s_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmadd_s_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_s_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_s_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_s_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_s_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_s_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_s_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -492,35 +848,65 @@ entry: ;; Check that fnmadd.s is not emitted. define void @not_contract_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_contract_xvfnmadd_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_contract_xvfnmadd_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_contract_xvfnmadd_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmadd_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmadd_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -534,32 +920,59 @@ entry: } define void @contract_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmsub_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmsub_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmsub_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -573,32 +986,59 @@ entry: } define void @contract_xvfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: contract_xvfnmsub_s_nsz: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: contract_xvfnmsub_s_nsz: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: contract_xvfnmsub_s_nsz: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_s_nsz: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_s_nsz: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_s_nsz: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_s_nsz: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_s_nsz: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_s_nsz: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -612,35 +1052,65 @@ entry: ;; Check that fnmsub.s is not emitted. define void @not_contract_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: not_contract_xvfnmsub_s: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: not_contract_xvfnmsub_s: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: not_contract_xvfnmsub_s: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 -; CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_s: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmsub_s: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_s: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA32-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_s: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmsub_s: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_s: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31 +; LA64-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -653,32 +1123,59 @@ entry: } define void @xvfmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmadd_s_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmadd_s_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmadd_s_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmadd_s_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmadd_s_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmadd_s_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmadd_s_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmadd_s_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmadd_s_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -690,32 +1187,59 @@ entry: } define void @xvfmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfmsub_s_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfmsub_s_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfmsub_s_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfmsub_s_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfmsub_s_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfmsub_s_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfmsub_s_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfmsub_s_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfmsub_s_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -727,32 +1251,59 @@ entry: } define void @xvfnmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmadd_s_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmadd_s_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmadd_s_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmadd_s_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmadd_s_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmadd_s_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmadd_s_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmadd_s_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmadd_s_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 @@ -765,32 +1316,59 @@ entry: } define void @xvfnmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind { -; CONTRACT-FAST-LABEL: xvfnmsub_s_contract: -; CONTRACT-FAST: # %bb.0: # %entry -; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-FAST-NEXT: ret -; -; CONTRACT-ON-LABEL: xvfnmsub_s_contract: -; CONTRACT-ON: # %bb.0: # %entry -; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-ON-NEXT: ret -; -; CONTRACT-OFF-LABEL: xvfnmsub_s_contract: -; CONTRACT-OFF: # %bb.0: # %entry -; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 -; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 -; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 -; CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 -; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 -; CONTRACT-OFF-NEXT: ret +; LA32-CONTRACT-FAST-LABEL: xvfnmsub_s_contract: +; LA32-CONTRACT-FAST: # %bb.0: # %entry +; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-FAST-NEXT: ret +; +; LA32-CONTRACT-ON-LABEL: xvfnmsub_s_contract: +; LA32-CONTRACT-ON: # %bb.0: # %entry +; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-ON-NEXT: ret +; +; LA32-CONTRACT-OFF-LABEL: xvfnmsub_s_contract: +; LA32-CONTRACT-OFF: # %bb.0: # %entry +; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA32-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA32-CONTRACT-OFF-NEXT: ret +; +; LA64-CONTRACT-FAST-LABEL: xvfnmsub_s_contract: +; LA64-CONTRACT-FAST: # %bb.0: # %entry +; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-FAST-NEXT: ret +; +; LA64-CONTRACT-ON-LABEL: xvfnmsub_s_contract: +; LA64-CONTRACT-ON: # %bb.0: # %entry +; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-ON-NEXT: ret +; +; LA64-CONTRACT-OFF-LABEL: xvfnmsub_s_contract: +; LA64-CONTRACT-OFF: # %bb.0: # %entry +; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0 +; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0 +; LA64-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2 +; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0 +; LA64-CONTRACT-OFF-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0 %v1 = load <8 x float>, ptr %a1 diff --git a/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll index 48fd12697417..4e475daa8ced 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll @@ -1,31 +1,114 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT -; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT-LA32 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,+frecipe < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT-LA64 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s --check-prefix=LA64 ;; 1.0 / (fsqrt vec) define void @one_div_sqrt_v8f32(ptr %res, ptr %a0) nounwind { -; FAULT-LABEL: one_div_sqrt_v8f32: -; FAULT: # %bb.0: # %entry -; FAULT-NEXT: xvld $xr0, $a1, 0 -; FAULT-NEXT: xvfrsqrt.s $xr0, $xr0 -; FAULT-NEXT: xvst $xr0, $a0, 0 -; FAULT-NEXT: ret +; FAULT-LA32-LABEL: one_div_sqrt_v8f32: +; FAULT-LA32: # %bb.0: # %entry +; FAULT-LA32-NEXT: addi.w $sp, $sp, -128 +; FAULT-LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; FAULT-LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; FAULT-LA32-NEXT: addi.w $fp, $sp, 128 +; FAULT-LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; FAULT-LA32-NEXT: vld $vr0, $a1, 16 +; FAULT-LA32-NEXT: vst $vr0, $sp, 48 +; FAULT-LA32-NEXT: ld.w $a2, $a1, 12 +; FAULT-LA32-NEXT: st.w $a2, $sp, 44 +; FAULT-LA32-NEXT: ld.w $a2, $a1, 8 +; FAULT-LA32-NEXT: st.w $a2, $sp, 40 +; FAULT-LA32-NEXT: ld.w $a2, $a1, 4 +; FAULT-LA32-NEXT: st.w $a2, $sp, 36 +; FAULT-LA32-NEXT: ld.w $a1, $a1, 0 +; FAULT-LA32-NEXT: st.w $a1, $sp, 32 +; FAULT-LA32-NEXT: xvld $xr0, $sp, 32 +; FAULT-LA32-NEXT: xvfrsqrt.s $xr0, $xr0 +; FAULT-LA32-NEXT: xvst $xr0, $sp, 64 +; FAULT-LA32-NEXT: vld $vr0, $sp, 80 +; FAULT-LA32-NEXT: vst $vr0, $a0, 16 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 76 +; FAULT-LA32-NEXT: st.w $a1, $a0, 12 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 72 +; FAULT-LA32-NEXT: st.w $a1, $a0, 8 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 68 +; FAULT-LA32-NEXT: st.w $a1, $a0, 4 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 64 +; FAULT-LA32-NEXT: st.w $a1, $a0, 0 +; FAULT-LA32-NEXT: addi.w $sp, $fp, -128 +; FAULT-LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; FAULT-LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; FAULT-LA32-NEXT: addi.w $sp, $sp, 128 +; FAULT-LA32-NEXT: ret ; -; CHECK-LABEL: one_div_sqrt_v8f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfrsqrte.s $xr1, $xr0 -; CHECK-NEXT: xvfmul.s $xr1, $xr0, $xr1 -; CHECK-NEXT: xvfmul.s $xr0, $xr0, $xr1 -; CHECK-NEXT: lu12i.w $a1, -261120 -; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1 -; CHECK-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 -; CHECK-NEXT: lu12i.w $a1, -266240 -; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1 -; CHECK-NEXT: xvfmul.s $xr1, $xr1, $xr2 -; CHECK-NEXT: xvfmul.s $xr0, $xr1, $xr0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_div_sqrt_v8f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -128 +; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; LA32-NEXT: addi.w $fp, $sp, 128 +; LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; LA32-NEXT: vld $vr0, $a1, 16 +; LA32-NEXT: vst $vr0, $sp, 48 +; LA32-NEXT: ld.w $a2, $a1, 12 +; LA32-NEXT: st.w $a2, $sp, 44 +; LA32-NEXT: ld.w $a2, $a1, 8 +; LA32-NEXT: st.w $a2, $sp, 40 +; LA32-NEXT: ld.w $a2, $a1, 4 +; LA32-NEXT: st.w $a2, $sp, 36 +; LA32-NEXT: ld.w $a1, $a1, 0 +; LA32-NEXT: st.w $a1, $sp, 32 +; LA32-NEXT: xvld $xr0, $sp, 32 +; LA32-NEXT: xvfrsqrte.s $xr1, $xr0 +; LA32-NEXT: xvfmul.s $xr1, $xr0, $xr1 +; LA32-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA32-NEXT: lu12i.w $a1, -261120 +; LA32-NEXT: xvreplgr2vr.w $xr2, $a1 +; LA32-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA32-NEXT: lu12i.w $a1, -266240 +; LA32-NEXT: xvreplgr2vr.w $xr2, $a1 +; LA32-NEXT: xvfmul.s $xr1, $xr1, $xr2 +; LA32-NEXT: xvfmul.s $xr0, $xr1, $xr0 +; LA32-NEXT: xvst $xr0, $sp, 64 +; LA32-NEXT: vld $vr0, $sp, 80 +; LA32-NEXT: vst $vr0, $a0, 16 +; LA32-NEXT: ld.w $a1, $sp, 76 +; LA32-NEXT: st.w $a1, $a0, 12 +; LA32-NEXT: ld.w $a1, $sp, 72 +; LA32-NEXT: st.w $a1, $a0, 8 +; LA32-NEXT: ld.w $a1, $sp, 68 +; LA32-NEXT: st.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a1, $sp, 64 +; LA32-NEXT: st.w $a1, $a0, 0 +; LA32-NEXT: addi.w $sp, $fp, -128 +; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 128 +; LA32-NEXT: ret +; +; FAULT-LA64-LABEL: one_div_sqrt_v8f32: +; FAULT-LA64: # %bb.0: # %entry +; FAULT-LA64-NEXT: xvld $xr0, $a1, 0 +; FAULT-LA64-NEXT: xvfrsqrt.s $xr0, $xr0 +; FAULT-LA64-NEXT: xvst $xr0, $a0, 0 +; FAULT-LA64-NEXT: ret +; +; LA64-LABEL: one_div_sqrt_v8f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfrsqrte.s $xr1, $xr0 +; LA64-NEXT: xvfmul.s $xr1, $xr0, $xr1 +; LA64-NEXT: xvfmul.s $xr0, $xr0, $xr1 +; LA64-NEXT: lu12i.w $a1, -261120 +; LA64-NEXT: xvreplgr2vr.w $xr2, $a1 +; LA64-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2 +; LA64-NEXT: lu12i.w $a1, -266240 +; LA64-NEXT: xvreplgr2vr.w $xr2, $a1 +; LA64-NEXT: xvfmul.s $xr1, $xr1, $xr2 +; LA64-NEXT: xvfmul.s $xr0, $xr1, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0, align 16 %sqrt = call fast <8 x float> @llvm.sqrt.v8f32 (<8 x float> %v0) @@ -35,34 +118,122 @@ entry: } define void @one_div_sqrt_v4f64(ptr %res, ptr %a0) nounwind { -; FAULT-LABEL: one_div_sqrt_v4f64: -; FAULT: # %bb.0: # %entry -; FAULT-NEXT: xvld $xr0, $a1, 0 -; FAULT-NEXT: xvfrsqrt.d $xr0, $xr0 -; FAULT-NEXT: xvst $xr0, $a0, 0 -; FAULT-NEXT: ret +; FAULT-LA32-LABEL: one_div_sqrt_v4f64: +; FAULT-LA32: # %bb.0: # %entry +; FAULT-LA32-NEXT: addi.w $sp, $sp, -128 +; FAULT-LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; FAULT-LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; FAULT-LA32-NEXT: addi.w $fp, $sp, 128 +; FAULT-LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; FAULT-LA32-NEXT: vld $vr0, $a1, 16 +; FAULT-LA32-NEXT: vst $vr0, $sp, 48 +; FAULT-LA32-NEXT: ld.w $a2, $a1, 12 +; FAULT-LA32-NEXT: st.w $a2, $sp, 44 +; FAULT-LA32-NEXT: ld.w $a2, $a1, 8 +; FAULT-LA32-NEXT: st.w $a2, $sp, 40 +; FAULT-LA32-NEXT: ld.w $a2, $a1, 4 +; FAULT-LA32-NEXT: st.w $a2, $sp, 36 +; FAULT-LA32-NEXT: ld.w $a1, $a1, 0 +; FAULT-LA32-NEXT: st.w $a1, $sp, 32 +; FAULT-LA32-NEXT: xvld $xr0, $sp, 32 +; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0) +; FAULT-LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI1_0) +; FAULT-LA32-NEXT: xvfsqrt.d $xr0, $xr0 +; FAULT-LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0 +; FAULT-LA32-NEXT: xvst $xr0, $sp, 64 +; FAULT-LA32-NEXT: vld $vr0, $sp, 80 +; FAULT-LA32-NEXT: vst $vr0, $a0, 16 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 76 +; FAULT-LA32-NEXT: st.w $a1, $a0, 12 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 72 +; FAULT-LA32-NEXT: st.w $a1, $a0, 8 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 68 +; FAULT-LA32-NEXT: st.w $a1, $a0, 4 +; FAULT-LA32-NEXT: ld.w $a1, $sp, 64 +; FAULT-LA32-NEXT: st.w $a1, $a0, 0 +; FAULT-LA32-NEXT: addi.w $sp, $fp, -128 +; FAULT-LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; FAULT-LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; FAULT-LA32-NEXT: addi.w $sp, $sp, 128 +; FAULT-LA32-NEXT: ret +; +; LA32-LABEL: one_div_sqrt_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -128 +; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; LA32-NEXT: addi.w $fp, $sp, 128 +; LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; LA32-NEXT: vld $vr0, $a1, 16 +; LA32-NEXT: vst $vr0, $sp, 48 +; LA32-NEXT: ld.w $a2, $a1, 12 +; LA32-NEXT: st.w $a2, $sp, 44 +; LA32-NEXT: ld.w $a2, $a1, 8 +; LA32-NEXT: st.w $a2, $sp, 40 +; LA32-NEXT: ld.w $a2, $a1, 4 +; LA32-NEXT: st.w $a2, $sp, 36 +; LA32-NEXT: ld.w $a1, $a1, 0 +; LA32-NEXT: st.w $a1, $sp, 32 +; LA32-NEXT: xvld $xr0, $sp, 32 +; LA32-NEXT: xvfrsqrte.d $xr1, $xr0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0) +; LA32-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI1_0) +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_1) +; LA32-NEXT: xvld $xr3, $a1, %pc_lo12(.LCPI1_1) +; LA32-NEXT: xvfmul.d $xr1, $xr0, $xr1 +; LA32-NEXT: xvfmul.d $xr4, $xr0, $xr1 +; LA32-NEXT: xvfmadd.d $xr4, $xr4, $xr1, $xr2 +; LA32-NEXT: xvfmul.d $xr1, $xr1, $xr3 +; LA32-NEXT: xvfmul.d $xr1, $xr1, $xr4 +; LA32-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA32-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2 +; LA32-NEXT: xvfmul.d $xr1, $xr1, $xr3 +; LA32-NEXT: xvfmul.d $xr0, $xr1, $xr0 +; LA32-NEXT: xvst $xr0, $sp, 64 +; LA32-NEXT: vld $vr0, $sp, 80 +; LA32-NEXT: vst $vr0, $a0, 16 +; LA32-NEXT: ld.w $a1, $sp, 76 +; LA32-NEXT: st.w $a1, $a0, 12 +; LA32-NEXT: ld.w $a1, $sp, 72 +; LA32-NEXT: st.w $a1, $a0, 8 +; LA32-NEXT: ld.w $a1, $sp, 68 +; LA32-NEXT: st.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a1, $sp, 64 +; LA32-NEXT: st.w $a1, $a0, 0 +; LA32-NEXT: addi.w $sp, $fp, -128 +; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 128 +; LA32-NEXT: ret +; +; FAULT-LA64-LABEL: one_div_sqrt_v4f64: +; FAULT-LA64: # %bb.0: # %entry +; FAULT-LA64-NEXT: xvld $xr0, $a1, 0 +; FAULT-LA64-NEXT: xvfrsqrt.d $xr0, $xr0 +; FAULT-LA64-NEXT: xvst $xr0, $a0, 0 +; FAULT-LA64-NEXT: ret ; -; CHECK-LABEL: one_div_sqrt_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfrsqrte.d $xr1, $xr0 -; CHECK-NEXT: xvfmul.d $xr1, $xr0, $xr1 -; CHECK-NEXT: xvfmul.d $xr2, $xr0, $xr1 -; CHECK-NEXT: ori $a1, $zero, 0 -; CHECK-NEXT: lu32i.d $a1, -524288 -; CHECK-NEXT: lu52i.d $a1, $a1, -1024 -; CHECK-NEXT: xvreplgr2vr.d $xr3, $a1 -; CHECK-NEXT: xvfmadd.d $xr2, $xr2, $xr1, $xr3 -; CHECK-NEXT: lu52i.d $a1, $zero, -1026 -; CHECK-NEXT: xvreplgr2vr.d $xr4, $a1 -; CHECK-NEXT: xvfmul.d $xr1, $xr1, $xr4 -; CHECK-NEXT: xvfmul.d $xr1, $xr1, $xr2 -; CHECK-NEXT: xvfmul.d $xr0, $xr0, $xr1 -; CHECK-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr3 -; CHECK-NEXT: xvfmul.d $xr1, $xr1, $xr4 -; CHECK-NEXT: xvfmul.d $xr0, $xr1, $xr0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA64-LABEL: one_div_sqrt_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfrsqrte.d $xr1, $xr0 +; LA64-NEXT: xvfmul.d $xr1, $xr0, $xr1 +; LA64-NEXT: xvfmul.d $xr2, $xr0, $xr1 +; LA64-NEXT: ori $a1, $zero, 0 +; LA64-NEXT: lu32i.d $a1, -524288 +; LA64-NEXT: lu52i.d $a1, $a1, -1024 +; LA64-NEXT: xvreplgr2vr.d $xr3, $a1 +; LA64-NEXT: xvfmadd.d $xr2, $xr2, $xr1, $xr3 +; LA64-NEXT: lu52i.d $a1, $zero, -1026 +; LA64-NEXT: xvreplgr2vr.d $xr4, $a1 +; LA64-NEXT: xvfmul.d $xr1, $xr1, $xr4 +; LA64-NEXT: xvfmul.d $xr1, $xr1, $xr2 +; LA64-NEXT: xvfmul.d $xr0, $xr0, $xr1 +; LA64-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr3 +; LA64-NEXT: xvfmul.d $xr1, $xr1, $xr4 +; LA64-NEXT: xvfmul.d $xr0, $xr1, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0, align 16 %sqrt = call fast <4 x double> @llvm.sqrt.v4f64 (<4 x double> %v0) diff --git a/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll b/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll index c4a881bdeae9..f8a3284f04dc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll @@ -1,14 +1,51 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64 ;; fsqrt define void @sqrt_v8f32(ptr %res, ptr %a0) nounwind { -; CHECK-LABEL: sqrt_v8f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfsqrt.s $xr0, $xr0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: sqrt_v8f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -128 +; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; LA32-NEXT: addi.w $fp, $sp, 128 +; LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; LA32-NEXT: vld $vr0, $a1, 16 +; LA32-NEXT: vst $vr0, $sp, 48 +; LA32-NEXT: ld.w $a2, $a1, 12 +; LA32-NEXT: st.w $a2, $sp, 44 +; LA32-NEXT: ld.w $a2, $a1, 8 +; LA32-NEXT: st.w $a2, $sp, 40 +; LA32-NEXT: ld.w $a2, $a1, 4 +; LA32-NEXT: st.w $a2, $sp, 36 +; LA32-NEXT: ld.w $a1, $a1, 0 +; LA32-NEXT: st.w $a1, $sp, 32 +; LA32-NEXT: xvld $xr0, $sp, 32 +; LA32-NEXT: xvfsqrt.s $xr0, $xr0 +; LA32-NEXT: xvst $xr0, $sp, 64 +; LA32-NEXT: vld $vr0, $sp, 80 +; LA32-NEXT: vst $vr0, $a0, 16 +; LA32-NEXT: ld.w $a1, $sp, 76 +; LA32-NEXT: st.w $a1, $a0, 12 +; LA32-NEXT: ld.w $a1, $sp, 72 +; LA32-NEXT: st.w $a1, $a0, 8 +; LA32-NEXT: ld.w $a1, $sp, 68 +; LA32-NEXT: st.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a1, $sp, 64 +; LA32-NEXT: st.w $a1, $a0, 0 +; LA32-NEXT: addi.w $sp, $fp, -128 +; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 128 +; LA32-NEXT: ret +; +; LA64-LABEL: sqrt_v8f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfsqrt.s $xr0, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0, align 16 %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %v0) @@ -17,12 +54,48 @@ entry: } define void @sqrt_v4f64(ptr %res, ptr %a0) nounwind { -; CHECK-LABEL: sqrt_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfsqrt.d $xr0, $xr0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: sqrt_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -128 +; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; LA32-NEXT: addi.w $fp, $sp, 128 +; LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; LA32-NEXT: vld $vr0, $a1, 16 +; LA32-NEXT: vst $vr0, $sp, 48 +; LA32-NEXT: ld.w $a2, $a1, 12 +; LA32-NEXT: st.w $a2, $sp, 44 +; LA32-NEXT: ld.w $a2, $a1, 8 +; LA32-NEXT: st.w $a2, $sp, 40 +; LA32-NEXT: ld.w $a2, $a1, 4 +; LA32-NEXT: st.w $a2, $sp, 36 +; LA32-NEXT: ld.w $a1, $a1, 0 +; LA32-NEXT: st.w $a1, $sp, 32 +; LA32-NEXT: xvld $xr0, $sp, 32 +; LA32-NEXT: xvfsqrt.d $xr0, $xr0 +; LA32-NEXT: xvst $xr0, $sp, 64 +; LA32-NEXT: vld $vr0, $sp, 80 +; LA32-NEXT: vst $vr0, $a0, 16 +; LA32-NEXT: ld.w $a1, $sp, 76 +; LA32-NEXT: st.w $a1, $a0, 12 +; LA32-NEXT: ld.w $a1, $sp, 72 +; LA32-NEXT: st.w $a1, $a0, 8 +; LA32-NEXT: ld.w $a1, $sp, 68 +; LA32-NEXT: st.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a1, $sp, 64 +; LA32-NEXT: st.w $a1, $a0, 0 +; LA32-NEXT: addi.w $sp, $fp, -128 +; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 128 +; LA32-NEXT: ret +; +; LA64-LABEL: sqrt_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfsqrt.d $xr0, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0, align 16 %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %v0) @@ -32,12 +105,48 @@ entry: ;; 1.0 / (fsqrt vec) define void @one_div_sqrt_v8f32(ptr %res, ptr %a0) nounwind { -; CHECK-LABEL: one_div_sqrt_v8f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfrsqrt.s $xr0, $xr0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_div_sqrt_v8f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -128 +; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; LA32-NEXT: addi.w $fp, $sp, 128 +; LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; LA32-NEXT: vld $vr0, $a1, 16 +; LA32-NEXT: vst $vr0, $sp, 48 +; LA32-NEXT: ld.w $a2, $a1, 12 +; LA32-NEXT: st.w $a2, $sp, 44 +; LA32-NEXT: ld.w $a2, $a1, 8 +; LA32-NEXT: st.w $a2, $sp, 40 +; LA32-NEXT: ld.w $a2, $a1, 4 +; LA32-NEXT: st.w $a2, $sp, 36 +; LA32-NEXT: ld.w $a1, $a1, 0 +; LA32-NEXT: st.w $a1, $sp, 32 +; LA32-NEXT: xvld $xr0, $sp, 32 +; LA32-NEXT: xvfrsqrt.s $xr0, $xr0 +; LA32-NEXT: xvst $xr0, $sp, 64 +; LA32-NEXT: vld $vr0, $sp, 80 +; LA32-NEXT: vst $vr0, $a0, 16 +; LA32-NEXT: ld.w $a1, $sp, 76 +; LA32-NEXT: st.w $a1, $a0, 12 +; LA32-NEXT: ld.w $a1, $sp, 72 +; LA32-NEXT: st.w $a1, $a0, 8 +; LA32-NEXT: ld.w $a1, $sp, 68 +; LA32-NEXT: st.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a1, $sp, 64 +; LA32-NEXT: st.w $a1, $a0, 0 +; LA32-NEXT: addi.w $sp, $fp, -128 +; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 128 +; LA32-NEXT: ret +; +; LA64-LABEL: one_div_sqrt_v8f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfrsqrt.s $xr0, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <8 x float>, ptr %a0, align 16 %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %v0) @@ -47,12 +156,51 @@ entry: } define void @one_div_sqrt_v4f64(ptr %res, ptr %a0) nounwind { -; CHECK-LABEL: one_div_sqrt_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfrsqrt.d $xr0, $xr0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_div_sqrt_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -128 +; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill +; LA32-NEXT: addi.w $fp, $sp, 128 +; LA32-NEXT: bstrins.w $sp, $zero, 4, 0 +; LA32-NEXT: vld $vr0, $a1, 16 +; LA32-NEXT: vst $vr0, $sp, 48 +; LA32-NEXT: ld.w $a2, $a1, 12 +; LA32-NEXT: st.w $a2, $sp, 44 +; LA32-NEXT: ld.w $a2, $a1, 8 +; LA32-NEXT: st.w $a2, $sp, 40 +; LA32-NEXT: ld.w $a2, $a1, 4 +; LA32-NEXT: st.w $a2, $sp, 36 +; LA32-NEXT: ld.w $a1, $a1, 0 +; LA32-NEXT: st.w $a1, $sp, 32 +; LA32-NEXT: xvld $xr0, $sp, 32 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: xvfsqrt.d $xr0, $xr0 +; LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0 +; LA32-NEXT: xvst $xr0, $sp, 64 +; LA32-NEXT: vld $vr0, $sp, 80 +; LA32-NEXT: vst $vr0, $a0, 16 +; LA32-NEXT: ld.w $a1, $sp, 76 +; LA32-NEXT: st.w $a1, $a0, 12 +; LA32-NEXT: ld.w $a1, $sp, 72 +; LA32-NEXT: st.w $a1, $a0, 8 +; LA32-NEXT: ld.w $a1, $sp, 68 +; LA32-NEXT: st.w $a1, $a0, 4 +; LA32-NEXT: ld.w $a1, $sp, 64 +; LA32-NEXT: st.w $a1, $a0, 0 +; LA32-NEXT: addi.w $sp, $fp, -128 +; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 128 +; LA32-NEXT: ret +; +; LA64-LABEL: one_div_sqrt_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfrsqrt.d $xr0, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0, align 16 %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %v0) diff --git a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll index 8b25a6525381..1e60b389bb23 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @test_u() nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll index dd400ecfcf91..1289892b2c03 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @register_xr1() nounwind { ; CHECK-LABEL: register_xr1: @@ -42,16 +43,27 @@ entry: ;; is a callee-saved register which is preserved across calls. ;; That's why the fst.d and fld.d instructions are emitted. define void @register_xr31() nounwind { -; CHECK-LABEL: register_xr31: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi.d $sp, $sp, -16 -; CHECK-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill -; CHECK-NEXT: #APP -; CHECK-NEXT: xvldi $xr31, 1 -; CHECK-NEXT: #NO_APP -; CHECK-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 16 -; CHECK-NEXT: ret +; LA32-LABEL: register_xr31: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill +; LA32-NEXT: #APP +; LA32-NEXT: xvldi $xr31, 1 +; LA32-NEXT: #NO_APP +; LA32-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: register_xr31: +; LA64: # %bb.0: # %entry +; LA64-NEXT: addi.d $sp, $sp, -16 +; LA64-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill +; LA64-NEXT: #APP +; LA64-NEXT: xvldi $xr31, 1 +; LA64-NEXT: #NO_APP +; LA64-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload +; LA64-NEXT: addi.d $sp, $sp, 16 +; LA64-NEXT: ret entry: %0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr31}"() ret void diff --git a/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll b/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll index 7a90afca376d..48d6e0130105 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32>, <4 x i32>, i64) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll index bf54f44357b0..09c4161728bd 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvabsd.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll index 0c2f2ace29fc..2eac147a860c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvadd.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll index c1258d53e913..0f5bdad6c777 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvadda.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll index 4998847f0910..8855a8a6cc1b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvaddi.bu(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll index f25f0e61a28e..cb7ae06a5f56 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvaddi.bu(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll index 09b5d07a0151..fb39220b27c7 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvaddi.bu(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll index ef7a1b5a50ef..7f6fc9c4dbc1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvaddwev.h.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll index 15f3a8094770..e726657bd629 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvand.v(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll index 60f0b765f954..cd85cdacdbb1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvandi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll index 1273dc6b450b..ca12d53ddf29 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvandi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll index 88cf142d6968..924b69745ea2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvandi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll index f385ef3661cb..4eabdc021ec0 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvandn.v(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll index 488d3b96b003..b89511cbeeb5 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvavg.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll index b5ab5a5366aa..0aa573e64c49 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvavgr.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll index ecc287e89bbc..462ea24510be 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitclri.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll index 09da85411082..0ecd45ca296d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitclri.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll index cec71bab2fe8..9f148e5a447a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <32 x i8> @llvm.loongarch.lasx.xvbitclr.b(<32 x i8>, <32 x i8>) @@ -40,10 +41,21 @@ entry: declare <4 x i64> @llvm.loongarch.lasx.xvbitclr.d(<4 x i64>, <4 x i64>) define <4 x i64> @lasx_xvbitclr_d(<4 x i64> %va, <4 x i64> %vb) nounwind { -; CHECK-LABEL: lasx_xvbitclr_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvbitclr.d $xr0, $xr0, $xr1 -; CHECK-NEXT: ret +; LA32-LABEL: lasx_xvbitclr_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvrepli.d $xr2, 63 +; LA32-NEXT: xvand.v $xr1, $xr1, $xr2 +; LA32-NEXT: xvrepli.d $xr2, 1 +; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1 +; LA32-NEXT: xvrepli.b $xr2, -1 +; LA32-NEXT: xvxor.v $xr1, $xr1, $xr2 +; LA32-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lasx_xvbitclr_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvbitclr.d $xr0, $xr0, $xr1 +; LA64-NEXT: ret entry: %res = call <4 x i64> @llvm.loongarch.lasx.xvbitclr.d(<4 x i64> %va, <4 x i64> %vb) ret <4 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll index dff0884fdd5a..9532684ab420 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitrevi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll index e1aef1a82f0c..800ce010e317 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitrevi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll index fb4f9fbc2e4b..01c56eebf6c5 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <32 x i8> @llvm.loongarch.lasx.xvbitrev.b(<32 x i8>, <32 x i8>) @@ -40,10 +41,19 @@ entry: declare <4 x i64> @llvm.loongarch.lasx.xvbitrev.d(<4 x i64>, <4 x i64>) define <4 x i64> @lasx_xvbitrev_d(<4 x i64> %va, <4 x i64> %vb) nounwind { -; CHECK-LABEL: lasx_xvbitrev_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvbitrev.d $xr0, $xr0, $xr1 -; CHECK-NEXT: ret +; LA32-LABEL: lasx_xvbitrev_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvrepli.d $xr2, 63 +; LA32-NEXT: xvand.v $xr1, $xr1, $xr2 +; LA32-NEXT: xvrepli.d $xr2, 1 +; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1 +; LA32-NEXT: xvxor.v $xr0, $xr0, $xr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lasx_xvbitrev_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvbitrev.d $xr0, $xr0, $xr1 +; LA64-NEXT: ret entry: %res = call <4 x i64> @llvm.loongarch.lasx.xvbitrev.d(<4 x i64> %va, <4 x i64> %vb) ret <4 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll index 2e91407590ac..f112b58b28c8 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitsel.v(<32 x i8>, <32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll index 3f6fd44f842c..7b0b60ebbf45 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitseli.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll index 40533ab96d86..6f582fd4a9a1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitseli.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll index 79dd55cbfef9..1a3d5799194a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitseli.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll index 17a77ece7775..f05b5c7681a2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitseti.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll index 613285804e0e..a684c1bfec44 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbitseti.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll index 83d1f0ef60c6..0baad661ad59 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <32 x i8> @llvm.loongarch.lasx.xvbitset.b(<32 x i8>, <32 x i8>) @@ -40,10 +41,19 @@ entry: declare <4 x i64> @llvm.loongarch.lasx.xvbitset.d(<4 x i64>, <4 x i64>) define <4 x i64> @lasx_xvbitset_d(<4 x i64> %va, <4 x i64> %vb) nounwind { -; CHECK-LABEL: lasx_xvbitset_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvbitset.d $xr0, $xr0, $xr1 -; CHECK-NEXT: ret +; LA32-LABEL: lasx_xvbitset_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvrepli.d $xr2, 63 +; LA32-NEXT: xvand.v $xr1, $xr1, $xr2 +; LA32-NEXT: xvrepli.d $xr2, 1 +; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1 +; LA32-NEXT: xvor.v $xr0, $xr0, $xr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lasx_xvbitset_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvbitset.d $xr0, $xr0, $xr1 +; LA64-NEXT: ret entry: %res = call <4 x i64> @llvm.loongarch.lasx.xvbitset.d(<4 x i64> %va, <4 x i64> %vb) ret <4 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll index 1da08a633bd2..fbe6b69b679a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbsll.v(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll index e19a3232c179..694de9ec5a03 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbsll.v(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll index cbb63ced5cc0..f6e3542ed7cc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbsll.v(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll index 5d2b63391e67..72a75f491a91 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbsrl.v(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll index 8dfd0ca579b8..b74676a73ad9 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbsrl.v(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll index b0c26cbe3e35..3e865eaa95d6 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvbsrl.v(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll index 29b2be03d54e..4e8110f74fc8 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvclo.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll index 5247ceedbd14..526bc8ee176d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvclz.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll index 813204092e94..9e23ee1bf240 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvdiv.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll index 48721b52af00..faf2a58f90a2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll index 543589e61b12..1580a09ca975 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll index 7040c8c784cd..b437c1f87687 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <4 x i64> @llvm.loongarch.lasx.xvextl.q.d(<4 x i64>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll index 1301b8a146eb..337f46a45fc3 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll index bca8f8b3c778..9164f8f623fa 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll index c8774a7b29c0..af1b3e2959a7 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll index 563a0ce9e384..6b309d89b62e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfadd.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll index 901ca5bb0260..1a22e3a7eca7 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvfclass.s(<8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll index b01f908e71af..581d1a68bdda 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvfcmp.caf.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll index 82bf1d3df72c..62206d7b8496 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvfcvt.h.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll index e1a6a2923e67..c562e2923135 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfcvth.s.h(<16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll index 0b3e693c7f51..4e270284568b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfcvtl.s.h(<16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll index 49923ddd4e8d..45a4d4c4d5ca 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfdiv.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll index 24da0bd33838..fb96482795c5 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvffint.s.w(<8 x i32>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll index bccef4504d70..7e8273956331 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvflogb.s(<8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll index 0fc06f971660..1caf43fb4299 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfmadd.s(<8 x float>, <8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll index 2422fa0c00d8..eb2fa913311c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfmax.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll index cd9ccc656aef..adc4649d3933 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfmaxa.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll index effb3f9e1d75..61205890a440 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfmin.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll index 753a6f31ba06..214ab30ee7b3 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfmina.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll index 57909d0dd168..132aae31c4ed 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfmsub.s(<8 x float>, <8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll index 9cad6f383066..aca107fd4c18 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfmul.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll index c30993590f98..007b9739fe6a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfnmadd.s(<8 x float>, <8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll index 2e7ca695be62..3e711803828c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfnmsub.s(<8 x float>, <8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll index da3a26df2824..aa3581018bef 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfrecip.s(<8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll index ddead27cd14b..b410d76c395a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfrintrne.s(<8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll index 6efa8122baf1..692cfc19218d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfrsqrt.s(<8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll index 64b4632669d2..e9d1bf38eb5a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvfrstpi.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll index ca92cff9b2d1..767d69ccc09c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvfrstpi.b(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll index e83e55a52a11..853778f292a1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvfrstp.b(<32 x i8>, <32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll index a13333d8d81c..4669f2c92ed1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfsqrt.s(<8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll index b52774a03618..3dde655fd568 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x float> @llvm.loongarch.lasx.xvfsub.s(<8 x float>, <8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll index 74cd507f16d2..b716c32d43e2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvftintrne.w.s(<8 x float>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll index 2c64ab23806b..a75325228213 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvhaddw.h.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll index a5223c1d89a0..a40e80b730d0 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvhsubw.h.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll index c9d0ca6b0324..7e83feb2ed9a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvilvl.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll index 4982f2c7d43a..1dd4ffad8fb3 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll index 3accabf6dbd9..ef3c09cc1c42 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll index ea98c96464ae..1d1b33b4f9e6 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32) @@ -17,11 +18,18 @@ entry: declare <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64>, i64, i32) define <4 x i64> @lasx_xvinsgr2vr_d(<4 x i64> %va) nounwind { -; CHECK-LABEL: lasx_xvinsgr2vr_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: ori $a0, $zero, 1 -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: lasx_xvinsgr2vr_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: ori $a0, $zero, 1 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 2 +; LA32-NEXT: xvinsgr2vr.w $xr0, $zero, 3 +; LA32-NEXT: ret +; +; LA64-LABEL: lasx_xvinsgr2vr_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: ori $a0, $zero, 1 +; LA64-NEXT: xvinsgr2vr.d $xr0, $a0, 1 +; LA64-NEXT: ret entry: %res = call <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64> %va, i64 1, i32 1) ret <4 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll index a54fa8515fba..98d1532b26d1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32>, <8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll index 53e59db11aa6..04f64e7a9c29 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32>, <8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll index 27ae819c4144..561ba17e8ff1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32>, <8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll index 27c690c91aec..4dd6fc037aa2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvld(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll index 1d8d5c764ce8..c0e3239dfb89 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvld(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll index f3dd3650cf8a..c574833ec8f3 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <4 x i64> @llvm.loongarch.lasx.xvldi(i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll index 6466818bf674..eb41e993b9d1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <4 x i64> @llvm.loongarch.lasx.xvldi(i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll index 59f79dd32af3..e65ecf5fda19 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <4 x i64> @llvm.loongarch.lasx.xvldi(i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll index 6fe6de82e1c0..14cf0593c2de 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvldrepl.b(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll index 74c22298db50..05a44e9d2806 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvldrepl.b(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll index ccd969a9f299..bb5bb6539d2a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvldrepl.b(ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll index d3b09396727e..8dd45221d421 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmadd.b(<32 x i8>, <32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll index 146624a764a2..eb7189cf0ae7 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.b(<16 x i16>, <32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll index b85798b53c92..33035ffb1413 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmaxi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll index 9cf09df4439a..4739ed6be91d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmax.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll index b81931977aad..f853ca45fce1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmini.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll index c94b1e4ea44c..dde42a0239ad 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmin.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll index a177246bb235..9b13612c8d04 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmod.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll index da87c20ad6ee..afb8472d18a7 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmskgez.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll index b2218487535c..4a6640ead171 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmskltz.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll index becd2c883a7e..f6d4998f47d4 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmsknz.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll index c89f9578b77d..5a7f5bffe228 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmsub.b(<32 x i8>, <32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll index 97461512ce16..4d7b14cc5fe0 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmuh.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll index d5d852e58a9f..305604ed6c08 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvmul.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll index f69e64aa7698..d7a8aaade203 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll index ecbedf334657..e4b7ef728490 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvneg.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll index 674746b7624e..fa6f5a22cdbc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvnor.v(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll index 1130e094bf1f..e3f061e6a1c9 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvnori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll index 8f2333064d64..92feeeb00aa1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvnori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll index 55eebf87ee92..fc3c6398d6f1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvnori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll index 16462cfafc54..b1b5e4b7e009 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvor.v(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll index 90dec8e55f2d..de37309a623f 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll index ae6571d98f4a..49296350000b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll index 8e53d88bac37..96eaf0140a41 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll index 3a335cdd3716..ea2c69bbb1c8 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvorn.v(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll index 512b30234917..89ca5d4883c2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvpackev.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll index d77f1d2082c8..80c8f0a19c8e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvpcnt.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll index 4ec434edd4ec..086b250324b1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvperm.w(<8 x i32>, <8 x i32>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll index 41f4856bd8f7..78f876cf4661 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32>, <8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll index afb335c5d6ca..50723bb1960e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32>, <8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll index 0d9f9daabc44..73797899431b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32>, <8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll index bbd6d693ca0b..cc3c4bb3ed38 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvpickev.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll index cfc6ec42874e..f113ee2c3e9a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvpickve.w(<8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll index be1f19a89737..eae84ac93d7e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvpickve.w(<8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll index 546777bc72ab..a4f0bad28d41 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <8 x i32> @llvm.loongarch.lasx.xvpickve.w(<8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll index 0fa8c94adc60..f3d6e3149187 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare i32 @llvm.loongarch.lasx.xvpickve2gr.w(<8 x i32>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll index a0cb309c54e1..4a20a21baf4c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll index c537ffa66ba7..fd99f3b52f65 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll index 25fab44f461f..500ab529b725 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll index 21d36ff7bb5e..b95c5323d973 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvreplve.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll index 7996bb36ef03..c70fb4e01e91 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvreplve0.b(<32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll index 40abdf497605..1f7434c77594 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvrotri.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll index dd38301d0534..69ed350f3480 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvrotri.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll index 64d2773864e9..c65f8d073757 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvrotr.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll index 54a5e2e9c833..bec705422d19 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsadd.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll index 839fbc9990d3..e9d9e9f5d18a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsat.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll index b73b32ebd3b0..9d9027465340 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsat.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll index 293b9dc9eb4d..77fc912e78f9 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsat.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll index bb6ef0cc6574..39ef86cc36b4 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvseqi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll index fb2c6206da7b..24cf5c0b940a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvseqi.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll index 83bc93c88c73..d4e48e8575a6 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvseq.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll index 9b9140f6ad62..35fab17aa611 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvshuf.b(<32 x i8>, <32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll index 9217d1f6a05d..65660dbbe780 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvshuf4i.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll index 8d6d1c694193..0f2652472a64 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvshuf4i.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll index 31205086759c..7e0e6a8a2aa9 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvshuf4i.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll index e6c6d8ccd0d3..2ee27d612888 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsigncov.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll index 5b10aca9801d..791f7b284580 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvslei.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll index 903bc10d88b7..6a3c6efe1e60 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvslei.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll index 8895efc84b84..fa3e3389ed8e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsle.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll index bf8205376a6c..2514788b1dff 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvslli.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll index b5368a86b5c3..0cc5f7962199 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvslli.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll index 14110b613dbe..228facde7b96 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <32 x i8> @llvm.loongarch.lasx.xvsll.b(<32 x i8>, <32 x i8>) @@ -40,10 +41,17 @@ entry: declare <4 x i64> @llvm.loongarch.lasx.xvsll.d(<4 x i64>, <4 x i64>) define <4 x i64> @lasx_xvsll_d(<4 x i64> %va, <4 x i64> %vb) nounwind { -; CHECK-LABEL: lasx_xvsll_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvsll.d $xr0, $xr0, $xr1 -; CHECK-NEXT: ret +; LA32-LABEL: lasx_xvsll_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvrepli.d $xr2, 63 +; LA32-NEXT: xvand.v $xr1, $xr1, $xr2 +; LA32-NEXT: xvsll.d $xr0, $xr0, $xr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lasx_xvsll_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvsll.d $xr0, $xr0, $xr1 +; LA64-NEXT: ret entry: %res = call <4 x i64> @llvm.loongarch.lasx.xvsll.d(<4 x i64> %va, <4 x i64> %vb) ret <4 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll index 18803767d6c0..28df3fcc37ec 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll index 3f5d4d631671..49e1a1d4108c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll index a72b8a6cbb4f..9cd6312d07ef 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll index dc0567da4e47..c92c006672aa 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvslti.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll index a2cedc8d3ef3..b129cb00caf6 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvslti.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll index 3ea87adff110..94e587288c13 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvslt.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll index 15b522d5e7e3..004f0ffb277c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrai.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll index fefee7246ae6..1438becbea98 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrai.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll index a7498682559b..12bc60695304 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <32 x i8> @llvm.loongarch.lasx.xvsra.b(<32 x i8>, <32 x i8>) @@ -40,10 +41,17 @@ entry: declare <4 x i64> @llvm.loongarch.lasx.xvsra.d(<4 x i64>, <4 x i64>) define <4 x i64> @lasx_xvsra_d(<4 x i64> %va, <4 x i64> %vb) nounwind { -; CHECK-LABEL: lasx_xvsra_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvsra.d $xr0, $xr0, $xr1 -; CHECK-NEXT: ret +; LA32-LABEL: lasx_xvsra_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvrepli.d $xr2, 63 +; LA32-NEXT: xvand.v $xr1, $xr1, $xr2 +; LA32-NEXT: xvsra.d $xr0, $xr0, $xr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lasx_xvsra_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvsra.d $xr0, $xr0, $xr1 +; LA64-NEXT: ret entry: %res = call <4 x i64> @llvm.loongarch.lasx.xvsra.d(<4 x i64> %va, <4 x i64> %vb) ret <4 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll index f59ae4c19662..9690b9b960d3 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsran.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll index bedbfc4889d2..c4592d628e57 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrani.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll index 3c17f2b6090a..2ac5cd9d6399 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrani.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll index 91fb90da9c52..dc017da9edda 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrani.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll index e417e3cc5bbf..49f8505746eb 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrari.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll index 15fed7966f1c..430187b11b74 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrari.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll index e2c160557c4d..fcba1aa005e2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrar.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll index 02dd989773ca..bfb725d13547 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrarn.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll index 83e977827e2d..35786248752c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrarni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll index eb577a29fb33..fb7bcc380aab 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrarni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll index a7d2c3739793..9c3848b39611 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrarni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll index 3ab02dcb97ed..2824c3944b88 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrli.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll index bc085aeaa232..52a84c8b5bcc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrli.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll index 7b2992f2ca3b..315ca74ad6dc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 declare <32 x i8> @llvm.loongarch.lasx.xvsrl.b(<32 x i8>, <32 x i8>) @@ -40,10 +41,17 @@ entry: declare <4 x i64> @llvm.loongarch.lasx.xvsrl.d(<4 x i64>, <4 x i64>) define <4 x i64> @lasx_xvsrl_d(<4 x i64> %va, <4 x i64> %vb) nounwind { -; CHECK-LABEL: lasx_xvsrl_d: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvsrl.d $xr0, $xr0, $xr1 -; CHECK-NEXT: ret +; LA32-LABEL: lasx_xvsrl_d: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvrepli.d $xr2, 63 +; LA32-NEXT: xvand.v $xr1, $xr1, $xr2 +; LA32-NEXT: xvsrl.d $xr0, $xr0, $xr1 +; LA32-NEXT: ret +; +; LA64-LABEL: lasx_xvsrl_d: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvsrl.d $xr0, $xr0, $xr1 +; LA64-NEXT: ret entry: %res = call <4 x i64> @llvm.loongarch.lasx.xvsrl.d(<4 x i64> %va, <4 x i64> %vb) ret <4 x i64> %res diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll index dc5c0e016ea0..f72672ffba5a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrln.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll index 9e7c94305630..67f9fb70fcaf 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll index 66d800470003..58b2182e929b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll index 0301ebb195e2..f87b41304f03 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll index 52621ddc6f49..de78e88c3e48 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlri.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll index 5663e3475b12..e088643d97b3 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlri.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll index e04504158e27..0a57b07b38f6 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlr.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll index 1e7df379c6e1..546da1030698 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlrn.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll index 2d65a75b175a..eafdbf5b2bde 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlrni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll index 82da0d21d013..8a401ef8a992 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlrni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll index 56dbafe8b1ac..2851d4715473 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsrlrni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll index da1857dad145..29640da6f7c6 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssran.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll index e10d5d7bd488..cd3b3baa9a58 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrani.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll index a928cc2de8c8..3d912502e0cc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrani.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll index 9efa659b4a1e..7461f4c71c01 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrani.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll index b5d59ff06f4d..9502b29b5d67 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrarn.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll index 42cd6ac99754..5d0153fd4c8d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrarni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll index f050e7d79b0f..d7ba76e878df 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrarni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll index da411dad645b..90abf2fab74d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrarni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll index c60b5bdf81a0..1352baecd12a 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrln.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll index 26be21a83aa4..fc41df8c6fbf 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrlni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll index 72da2a746dd5..99b0d4561792 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrlni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll index e57dd426bde8..1a49761dedae 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrlni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll index 774cf1bd5e84..d89511ba180e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrlrn.b.h(<16 x i16>, <16 x i16>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll index cd778e2c0627..36d19b5ce9f4 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrlrni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll index a10c54329149..69f5baa8536b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrlrni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll index 9a80516d8d78..b3119d6b27bb 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssrlrni.b.h(<32 x i8>, <32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll index cd3ccd9f5262..e600eac3f002 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvssub.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll index 6108ae1883da..d659f1d95865 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lasx.xvst(<32 x i8>, ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll index 969fb5765dd8..0882834b23a3 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lasx.xvst(<32 x i8>, ptr, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll index 4593de13fbff..a1de4f49b580 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lasx.xvstelm.b(<32 x i8>, ptr, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll index faa7d501eb74..d970689e63d4 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare void @llvm.loongarch.lasx.xvstelm.b(<32 x i8>, ptr, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll index 34d1866e9d5e..87c5946270ef 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare void @llvm.loongarch.lasx.xvstelm.b(<32 x i8>, ptr, i32, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll index 4d69dd83dcde..f8778adb458e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsub.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll index 810008c17f7e..8e24ec98d0c5 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsubi.bu(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll index 924b89ce9d6c..73ff9268230d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsubi.bu(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll index cc3235ff4657..1992628aefbc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvsubi.bu(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll index 6f203e894990..afdd7b2e7935 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <16 x i16> @llvm.loongarch.lasx.xvsubwev.h.b(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll index 6395b3d6f2e7..98d180f3560f 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvxor.v(<32 x i8>, <32 x i8>) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll index 0170d204cf42..d12082b3eafc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvxori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll index 1478f691a1cc..e1c9574aeafa 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll @@ -1,3 +1,4 @@ +; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s ; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvxori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll index c71d7e731165..8cc53991fb6e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s declare <32 x i8> @llvm.loongarch.lasx.xvxori.b(<32 x i8>, i32) diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll index c5df9f842083..20934480dce9 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc -mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s ;; 1. trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b) or abdu(a,b) diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll index 136f34bafb32..030f75b775ad 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @add_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll index b06d1bea4ef6..a2df7aa1ae6d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @and_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll index 4dd2cee7a2ed..edcbe1583945 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @ashr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll index 09ce1a04d6c9..073fc54f5654 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll @@ -1,11 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64 define i32 @bitcast_extract_v8f32(<8 x float> %a) nounwind { -; CHECK-LABEL: bitcast_extract_v8f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7 -; CHECK-NEXT: ret +; LA32-LABEL: bitcast_extract_v8f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvpickve.w $xr0, $xr0, 7 +; LA32-NEXT: movfr2gr.s $a0, $fa0 +; LA32-NEXT: ret +; +; LA64-LABEL: bitcast_extract_v8f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvpickve2gr.w $a0, $xr0, 7 +; LA64-NEXT: ret entry: %b = extractelement <8 x float> %a, i32 7 %c = bitcast float %b to i32 @@ -13,10 +20,17 @@ entry: } define i64 @bitcast_extract_v4f64(<4 x double> %a) nounwind { -; CHECK-LABEL: bitcast_extract_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 3 -; CHECK-NEXT: ret +; LA32-LABEL: bitcast_extract_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvpickve.d $xr0, $xr0, 3 +; LA32-NEXT: movfr2gr.s $a0, $fa0 +; LA32-NEXT: movfrh2gr.s $a1, $fa0 +; LA32-NEXT: ret +; +; LA64-LABEL: bitcast_extract_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvpickve2gr.d $a0, $xr0, 3 +; LA64-NEXT: ret entry: %b = extractelement <4 x double> %a, i32 3 %c = bitcast double %b to i64 diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll index 2e1618748688..dddee35fb9e7 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll @@ -76,21 +76,11 @@ define void @extract_4xdouble(ptr %src, ptr %dst) nounwind { define void @extract_32xi8_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; CHECK-LABEL: extract_32xi8_idx: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $sp, $sp, -96 -; CHECK-NEXT: st.d $ra, $sp, 88 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 80 # 8-byte Folded Spill -; CHECK-NEXT: addi.d $fp, $sp, 96 -; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvst $xr0, $sp, 32 -; CHECK-NEXT: addi.d $a0, $sp, 32 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 0 -; CHECK-NEXT: ld.b $a0, $a0, 0 -; CHECK-NEXT: st.b $a0, $a1, 0 -; CHECK-NEXT: addi.d $sp, $fp, -96 -; CHECK-NEXT: ld.d $fp, $sp, 80 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 96 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: movgr2fr.w $fa2, $a2 +; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2 +; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load volatile <32 x i8>, ptr %src %e = extractelement <32 x i8> %v, i32 %idx @@ -101,21 +91,11 @@ define void @extract_32xi8_idx(ptr %src, ptr %dst, i32 %idx) nounwind { define void @extract_16xi16_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; CHECK-LABEL: extract_16xi16_idx: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $sp, $sp, -96 -; CHECK-NEXT: st.d $ra, $sp, 88 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 80 # 8-byte Folded Spill -; CHECK-NEXT: addi.d $fp, $sp, 96 -; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvst $xr0, $sp, 32 -; CHECK-NEXT: addi.d $a0, $sp, 32 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 1 -; CHECK-NEXT: ld.h $a0, $a0, 0 -; CHECK-NEXT: st.h $a0, $a1, 0 -; CHECK-NEXT: addi.d $sp, $fp, -96 -; CHECK-NEXT: ld.d $fp, $sp, 80 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 96 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: movgr2fr.w $fa2, $a2 +; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0 +; CHECK-NEXT: xvstelm.h $xr2, $a1, 0, 0 ; CHECK-NEXT: ret %v = load volatile <16 x i16>, ptr %src %e = extractelement <16 x i16> %v, i32 %idx @@ -126,21 +106,10 @@ define void @extract_16xi16_idx(ptr %src, ptr %dst, i32 %idx) nounwind { define void @extract_8xi32_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; CHECK-LABEL: extract_8xi32_idx: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $sp, $sp, -96 -; CHECK-NEXT: st.d $ra, $sp, 88 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 80 # 8-byte Folded Spill -; CHECK-NEXT: addi.d $fp, $sp, 96 -; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvst $xr0, $sp, 32 -; CHECK-NEXT: addi.d $a0, $sp, 32 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 2 -; CHECK-NEXT: ld.w $a0, $a0, 0 -; CHECK-NEXT: st.w $a0, $a1, 0 -; CHECK-NEXT: addi.d $sp, $fp, -96 -; CHECK-NEXT: ld.d $fp, $sp, 80 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 96 +; CHECK-NEXT: xvreplgr2vr.w $xr1, $a2 +; CHECK-NEXT: xvperm.w $xr0, $xr0, $xr1 +; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load volatile <8 x i32>, ptr %src %e = extractelement <8 x i32> %v, i32 %idx @@ -151,21 +120,11 @@ define void @extract_8xi32_idx(ptr %src, ptr %dst, i32 %idx) nounwind { define void @extract_4xi64_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; CHECK-LABEL: extract_4xi64_idx: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $sp, $sp, -96 -; CHECK-NEXT: st.d $ra, $sp, 88 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 80 # 8-byte Folded Spill -; CHECK-NEXT: addi.d $fp, $sp, 96 -; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvst $xr0, $sp, 32 -; CHECK-NEXT: addi.d $a0, $sp, 32 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 3 -; CHECK-NEXT: ld.d $a0, $a0, 0 -; CHECK-NEXT: st.d $a0, $a1, 0 -; CHECK-NEXT: addi.d $sp, $fp, -96 -; CHECK-NEXT: ld.d $fp, $sp, 80 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 96 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: movgr2fr.w $fa2, $a2 +; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0 +; CHECK-NEXT: xvstelm.d $xr2, $a1, 0, 0 ; CHECK-NEXT: ret %v = load volatile <4 x i64>, ptr %src %e = extractelement <4 x i64> %v, i32 %idx @@ -176,21 +135,10 @@ define void @extract_4xi64_idx(ptr %src, ptr %dst, i32 %idx) nounwind { define void @extract_8xfloat_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; CHECK-LABEL: extract_8xfloat_idx: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $sp, $sp, -96 -; CHECK-NEXT: st.d $ra, $sp, 88 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 80 # 8-byte Folded Spill -; CHECK-NEXT: addi.d $fp, $sp, 96 -; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvst $xr0, $sp, 32 -; CHECK-NEXT: addi.d $a0, $sp, 32 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 2 -; CHECK-NEXT: fld.s $fa0, $a0, 0 -; CHECK-NEXT: fst.s $fa0, $a1, 0 -; CHECK-NEXT: addi.d $sp, $fp, -96 -; CHECK-NEXT: ld.d $fp, $sp, 80 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 96 +; CHECK-NEXT: xvreplgr2vr.w $xr1, $a2 +; CHECK-NEXT: xvperm.w $xr0, $xr0, $xr1 +; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load volatile <8 x float>, ptr %src %e = extractelement <8 x float> %v, i32 %idx @@ -201,21 +149,11 @@ define void @extract_8xfloat_idx(ptr %src, ptr %dst, i32 %idx) nounwind { define void @extract_4xdouble_idx(ptr %src, ptr %dst, i32 %idx) nounwind { ; CHECK-LABEL: extract_4xdouble_idx: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $sp, $sp, -96 -; CHECK-NEXT: st.d $ra, $sp, 88 # 8-byte Folded Spill -; CHECK-NEXT: st.d $fp, $sp, 80 # 8-byte Folded Spill -; CHECK-NEXT: addi.d $fp, $sp, 96 -; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvst $xr0, $sp, 32 -; CHECK-NEXT: addi.d $a0, $sp, 32 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 3 -; CHECK-NEXT: fld.d $fa0, $a0, 0 -; CHECK-NEXT: fst.d $fa0, $a1, 0 -; CHECK-NEXT: addi.d $sp, $fp, -96 -; CHECK-NEXT: ld.d $fp, $sp, 80 # 8-byte Folded Reload -; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload -; CHECK-NEXT: addi.d $sp, $sp, 96 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: movgr2fr.w $fa2, $a2 +; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0 +; CHECK-NEXT: xvstelm.d $xr2, $a1, 0, 0 ; CHECK-NEXT: ret %v = load volatile <4 x double>, ptr %src %e = extractelement <4 x double> %v, i32 %idx diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll index b3eb328e8d44..b4d5dc10c20c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @fadd_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll index 4f56dd29c1b2..be60b7518e39 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s ;; TREU diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll index 63d8c222ae54..ae6f091ddb49 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @fdiv_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { ; CHECK-LABEL: fdiv_v8f32: @@ -49,12 +50,21 @@ entry: } define void @one_fdiv_v4f64(ptr %res, ptr %a0) nounwind { -; CHECK-LABEL: one_fdiv_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvfrecip.d $xr0, $xr0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: one_fdiv_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: one_fdiv_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvfrecip.d $xr0, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret entry: %v0 = load <4 x double>, ptr %a0 %div = fdiv <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, %v0 diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll index 8ee567c2a92f..ffb793dd1301 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s ;; Fix https://github.com/llvm/llvm-project/issues/137000. diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll index f777151cdb0a..430ab98a5c69 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @fmul_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll index 5eb468fc55a0..515403f8362c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @fneg_v8f32(ptr %res, ptr %a0) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll index ed333c303879..5b63ef3e53a4 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @fptosi_v8f32_v8i32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll index 9c499ba71d64..4c699a0721bf 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @fptoui_v8f32_v8i32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll index 201ba5f5df66..99074e08c0de 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @fsub_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll index d15c4133855f..47229fc9a0fc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s ;; SETEQ diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll index b37b525981fd..4a9d2579766b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll @@ -1,11 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64 define <8 x float> @insert_bitcast_v8f32(<8 x float> %a, i32 %b) nounwind { -; CHECK-LABEL: insert_bitcast_v8f32: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: insert_bitcast_v8f32: +; LA32: # %bb.0: # %entry +; LA32-NEXT: movgr2fr.w $fa1, $a0 +; LA32-NEXT: xvinsve0.w $xr0, $xr1, 1 +; LA32-NEXT: ret +; +; LA64-LABEL: insert_bitcast_v8f32: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvinsgr2vr.w $xr0, $a0, 1 +; LA64-NEXT: ret entry: %c = bitcast i32 %b to float %d = insertelement <8 x float> %a, float %c, i32 1 @@ -13,10 +20,17 @@ entry: } define <4 x double> @insert_bitcast_v4f64(<4 x double> %a, i64 %b) nounwind { -; CHECK-LABEL: insert_bitcast_v4f64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: insert_bitcast_v4f64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: movgr2fr.w $fa1, $a0 +; LA32-NEXT: movgr2frh.w $fa1, $a1 +; LA32-NEXT: xvinsve0.d $xr0, $xr1, 1 +; LA32-NEXT: ret +; +; LA64-LABEL: insert_bitcast_v4f64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: xvinsgr2vr.d $xr0, $a0, 1 +; LA64-NEXT: ret entry: %c = bitcast i64 %b to double %d = insertelement <4 x double> %a, double %c, i32 1 diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll index 5b992b5e38de..4baa6e2bf1a2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @lshr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll index 4745e7003cb1..620d2233c904 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @mul_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll index f32b8897bebc..07ccb88f2bba 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @or_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll index 879caa5a6700..2c783e3a5e22 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @sdiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll index 56c69171c9d4..3e496eac475c 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @shl_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll index 22ab19b9fa44..382c0f551692 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s ;; xvilvl.b diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll index 2ff9af4069b9..c36a87f77bb2 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s ;; xvpackev.b diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll index 294d292d1764..327f1d4f5481 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s ;; xvpickev.b diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll index 208a758ea4e9..3673f594094b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @sitofp_v8i32_v8f32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll index 5102abac83d8..bf9f29b578d7 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @sub_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll index 43f558f3cdf3..c3bd69a8a0bc 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @udiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll index 70cf71c4cec2..6e417032acff 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @uitofp_v8i32_v8f32(ptr %res, ptr %in){ diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll index e062e10b21d9..5365685d395e 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @xor_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll index 506b5c1232f2..249414f5b1bb 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64 ;; Without this patch(codegen for concat_vectors), the test will hang. @g_156 = external global [12 x i32] @@ -7,23 +8,51 @@ @g_813 = external global i32 define void @foo() { -; CHECK-LABEL: foo: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: pcalau12i $a0, %got_pc_hi20(g_156) -; CHECK-NEXT: ld.d $a0, $a0, %got_pc_lo12(g_156) -; CHECK-NEXT: pcalau12i $a1, %got_pc_hi20(g_490) -; CHECK-NEXT: ld.d $a1, $a1, %got_pc_lo12(g_490) -; CHECK-NEXT: ld.w $a2, $a0, 24 -; CHECK-NEXT: pcalau12i $a3, %got_pc_hi20(g_813) -; CHECK-NEXT: ld.d $a3, $a3, %got_pc_lo12(g_813) -; CHECK-NEXT: st.w $zero, $a1, 0 -; CHECK-NEXT: st.w $a2, $a3, 0 -; CHECK-NEXT: xvrepli.b $xr0, 0 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: vrepli.b $vr0, 0 -; CHECK-NEXT: vst $vr0, $a0, 32 -; CHECK-NEXT: st.w $zero, $a0, 20 -; CHECK-NEXT: ret +; LA32-LABEL: foo: +; LA32: # %bb.0: # %entry +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: .cfi_def_cfa_offset 16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: st.w $fp, $sp, 8 # 4-byte Folded Spill +; LA32-NEXT: .cfi_offset 1, -4 +; LA32-NEXT: .cfi_offset 22, -8 +; LA32-NEXT: pcalau12i $a0, %got_pc_hi20(g_156) +; LA32-NEXT: ld.w $fp, $a0, %got_pc_lo12(g_156) +; LA32-NEXT: pcalau12i $a0, %got_pc_hi20(g_490) +; LA32-NEXT: ld.w $a0, $a0, %got_pc_lo12(g_490) +; LA32-NEXT: ld.w $a1, $fp, 24 +; LA32-NEXT: pcalau12i $a2, %got_pc_hi20(g_813) +; LA32-NEXT: ld.w $a2, $a2, %got_pc_lo12(g_813) +; LA32-NEXT: st.w $zero, $fp, 20 +; LA32-NEXT: st.w $zero, $a0, 0 +; LA32-NEXT: st.w $a1, $a2, 0 +; LA32-NEXT: ori $a2, $zero, 48 +; LA32-NEXT: move $a0, $fp +; LA32-NEXT: move $a1, $zero +; LA32-NEXT: bl memset +; LA32-NEXT: st.w $zero, $fp, 20 +; LA32-NEXT: ld.w $fp, $sp, 8 # 4-byte Folded Reload +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: foo: +; LA64: # %bb.0: # %entry +; LA64-NEXT: pcalau12i $a0, %got_pc_hi20(g_156) +; LA64-NEXT: ld.d $a0, $a0, %got_pc_lo12(g_156) +; LA64-NEXT: pcalau12i $a1, %got_pc_hi20(g_490) +; LA64-NEXT: ld.d $a1, $a1, %got_pc_lo12(g_490) +; LA64-NEXT: ld.w $a2, $a0, 24 +; LA64-NEXT: pcalau12i $a3, %got_pc_hi20(g_813) +; LA64-NEXT: ld.d $a3, $a3, %got_pc_lo12(g_813) +; LA64-NEXT: st.w $zero, $a1, 0 +; LA64-NEXT: st.w $a2, $a3, 0 +; LA64-NEXT: xvrepli.b $xr0, 0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: vrepli.b $vr0, 0 +; LA64-NEXT: vst $vr0, $a0, 32 +; LA64-NEXT: st.w $zero, $a0, 20 +; LA64-NEXT: ret entry: store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4 store i32 0, ptr @g_490, align 4 diff --git a/llvm/test/CodeGen/LoongArch/lasx/mulh.ll b/llvm/test/CodeGen/LoongArch/lasx/mulh.ll index db3cc7f38774..f99cc0a6cc33 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/mulh.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/mulh.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define void @mulhs_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll index 05fbb746bd9d..5593890bb768 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 ;; Test scalar_to_vector expansion. @@ -31,10 +32,16 @@ define <8 x i32> @scalar_to_8xi32(i32 %val) { } define <4 x i64> @scalar_to_4xi64(i64 %val) { -; CHECK-LABEL: scalar_to_4xi64: -; CHECK: # %bb.0: -; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: scalar_to_4xi64: +; LA32: # %bb.0: +; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 0 +; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 1 +; LA32-NEXT: ret +; +; LA64-LABEL: scalar_to_4xi64: +; LA64: # %bb.0: +; LA64-NEXT: xvinsgr2vr.d $xr0, $a0, 0 +; LA64-NEXT: ret %ret = insertelement <4 x i64> poison, i64 %val, i32 0 ret <4 x i64> %ret } diff --git a/llvm/test/CodeGen/LoongArch/lasx/shuffle-as-permute-and-shuffle.ll b/llvm/test/CodeGen/LoongArch/lasx/shuffle-as-permute-and-shuffle.ll index fed085843485..5f76d9951df9 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/shuffle-as-permute-and-shuffle.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/shuffle-as-permute-and-shuffle.ll @@ -61,13 +61,8 @@ define <8 x i32> @shuffle_v8i32(<8 x i32> %a) { ; CHECK-LABEL: shuffle_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0) -; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI4_0) -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_1) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI4_1) -; CHECK-NEXT: xvpermi.d $xr3, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr2, $xr0, $xr3 -; CHECK-NEXT: xvshuf.d $xr1, $xr2, $xr0 -; CHECK-NEXT: xvori.b $xr0, $xr1, 0 +; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI4_0) +; CHECK-NEXT: xvperm.w $xr0, $xr0, $xr1 ; CHECK-NEXT: ret %shuffle = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 4, i32 5, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7> ret <8 x i32> %shuffle @@ -117,13 +112,8 @@ define <8 x float> @shuffle_v8f32(<8 x float> %a) { ; CHECK-LABEL: shuffle_v8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_0) -; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI8_0) -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI8_1) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI8_1) -; CHECK-NEXT: xvpermi.d $xr3, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr2, $xr0, $xr3 -; CHECK-NEXT: xvshuf.d $xr1, $xr2, $xr0 -; CHECK-NEXT: xvori.b $xr0, $xr1, 0 +; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI8_0) +; CHECK-NEXT: xvperm.w $xr0, $xr0, $xr1 ; CHECK-NEXT: ret %shuffle = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> <i32 4, i32 5, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7> ret <8 x float> %shuffle diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-add.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-add.ll index bf5effd7b391..7268eb24ee51 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-add.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-add.ll @@ -1,27 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 - ; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s define void @vec_reduce_add_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvadd.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvhaddw.h.b $xr0, $xr0, $xr0 +; CHECK-NEXT: xvhaddw.w.h $xr0, $xr0, $xr0 +; CHECK-NEXT: xvhaddw.d.w $xr0, $xr0, $xr0 +; CHECK-NEXT: xvhaddw.q.d $xr0, $xr0, $xr0 +; CHECK-NEXT: xvpermi.d $xr1, $xr0, 2 +; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 0 +; CHECK-NEXT: st.b $a0, $a1, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %v) @@ -33,19 +24,13 @@ define void @vec_reduce_add_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvadd.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvhaddw.w.h $xr0, $xr0, $xr0 +; CHECK-NEXT: xvhaddw.d.w $xr0, $xr0, $xr0 +; CHECK-NEXT: xvhaddw.q.d $xr0, $xr0, $xr0 +; CHECK-NEXT: xvpermi.d $xr1, $xr0, 2 +; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 0 +; CHECK-NEXT: st.h $a0, $a1, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %v) @@ -57,16 +42,12 @@ define void @vec_reduce_add_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvadd.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvhaddw.d.w $xr0, $xr0, $xr0 +; CHECK-NEXT: xvhaddw.q.d $xr0, $xr0, $xr0 +; CHECK-NEXT: xvpermi.d $xr1, $xr0, 2 +; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0 +; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 0 +; CHECK-NEXT: st.w $a0, $a1, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v) @@ -78,14 +59,9 @@ define void @vec_reduce_add_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_add_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvadd.d $xr0, $xr0, $xr1 +; CHECK-NEXT: xvhaddw.q.d $xr0, $xr0, $xr0 +; CHECK-NEXT: xvpermi.d $xr1, $xr0, 2 +; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0 ; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src @@ -93,4 +69,3 @@ define void @vec_reduce_add_v4i64(ptr %src, ptr %dst) nounwind { store i64 %res, ptr %dst ret void } - diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll index a3160f10c8ca..fd64beab57bf 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll @@ -5,22 +5,17 @@ define void @vec_reduce_and_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_and_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %v) @@ -32,19 +27,15 @@ define void @vec_reduce_and_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_and_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %v) @@ -56,16 +47,13 @@ define void @vec_reduce_and_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_and_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %v) @@ -77,15 +65,11 @@ define void @vec_reduce_and_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_and_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vand.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %v) diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll index bc910c23e4b1..cdb08d9de382 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll @@ -5,22 +5,17 @@ define void @vec_reduce_or_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_or_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %v) @@ -32,19 +27,15 @@ define void @vec_reduce_or_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_or_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %v) @@ -56,16 +47,13 @@ define void @vec_reduce_or_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_or_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %v) @@ -77,15 +65,11 @@ define void @vec_reduce_or_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_or_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src %res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %v) diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll index 378088c9f828..1d182731c93b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll @@ -5,22 +5,17 @@ define void @vec_reduce_smax_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smax_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %v) @@ -32,19 +27,15 @@ define void @vec_reduce_smax_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smax_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %v) @@ -56,16 +47,13 @@ define void @vec_reduce_smax_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smax_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.w $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %v) @@ -77,15 +65,11 @@ define void @vec_reduce_smax_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smax_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.d $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.d $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.d $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src %res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %v) diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll index 1c7f2054cd4e..369afdd1fc7b 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll @@ -5,22 +5,17 @@ define void @vec_reduce_smin_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smin_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.b $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.b $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %v) @@ -32,19 +27,15 @@ define void @vec_reduce_smin_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smin_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.h $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.h $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %v) @@ -56,16 +47,13 @@ define void @vec_reduce_smin_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smin_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.w $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.w $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.w $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %v) @@ -77,15 +65,11 @@ define void @vec_reduce_smin_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_smin_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvmin.d $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.d $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.d $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.d $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src %res = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %v) diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll index 152f093cbd02..5256a72ad7d9 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll @@ -5,22 +5,17 @@ define void @vec_reduce_umax_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umax_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %v) @@ -32,19 +27,15 @@ define void @vec_reduce_umax_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umax_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %v) @@ -56,16 +47,13 @@ define void @vec_reduce_umax_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umax_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvmax.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvmax.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.wu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.wu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmax.wu $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %v) @@ -77,15 +65,11 @@ define void @vec_reduce_umax_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umax_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvmax.du $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvmax.du $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmax.du $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmax.du $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src %res = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %v) diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll index 64ed377535ab..a82c886d8eed 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll @@ -5,22 +5,17 @@ define void @vec_reduce_umin_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umin_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.bu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.bu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %v) @@ -32,19 +27,15 @@ define void @vec_reduce_umin_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umin_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.hu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.hu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %v) @@ -56,16 +47,13 @@ define void @vec_reduce_umin_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umin_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvmin.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvmin.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.wu $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.wu $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.wu $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vmin.wu $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %v) @@ -77,15 +65,11 @@ define void @vec_reduce_umin_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_umin_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvmin.du $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvmin.du $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vmin.du $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vmin.du $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src %res = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %v) diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll index 5dbf37e73263..429fadcdd156 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll @@ -5,22 +5,17 @@ define void @vec_reduce_xor_v32i8(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_xor_v32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 228 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvsrli.d $xr1, $xr1, 32 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.b $xr1, $xr1, 14 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.b $xr1, $xr1, 1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.b $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <32 x i8>, ptr %src %res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %v) @@ -32,19 +27,15 @@ define void @vec_reduce_xor_v16i16(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_xor_v16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 228 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvbsrl.v $xr1, $xr1, 8 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.h $xr1, $xr1, 14 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.h $xr1, $xr1, 1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.h $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <16 x i16>, ptr %src %res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %v) @@ -56,16 +47,13 @@ define void @vec_reduce_xor_v8i32(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_xor_v8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 78 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 228 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvshuf4i.w $xr1, $xr1, 14 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.w $xr1, $xr1, 1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.w $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 4 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.w $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <8 x i32>, ptr %src %res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %v) @@ -77,15 +65,11 @@ define void @vec_reduce_xor_v4i64(ptr %src, ptr %dst) nounwind { ; CHECK-LABEL: vec_reduce_xor_v4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: xvld $xr0, $a0, 0 -; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0) -; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI3_0) -; CHECK-NEXT: xvpermi.d $xr2, $xr0, 78 -; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr2 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvpermi.d $xr1, $xr0, 68 -; CHECK-NEXT: xvrepl128vei.d $xr1, $xr1, 1 -; CHECK-NEXT: xvxor.v $xr0, $xr0, $xr1 -; CHECK-NEXT: xvstelm.d $xr0, $a1, 0, 0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1 +; CHECK-NEXT: vxor.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vbsrl.v $vr1, $vr0, 8 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vstelm.d $vr0, $a1, 0, 0 ; CHECK-NEXT: ret %v = load <4 x i64>, ptr %src %res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %v) diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll index 72e06f680e43..48a534f43a0d 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define <32 x i8> @shuffle_to_xvslli_h_8(<32 x i8> %a) nounwind { diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll index 15bfce902f9d..cea604e96bc1 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define <32 x i8> @shuffle_32i8_byte_left_shift_1(<32 x i8> %a) { diff --git a/llvm/test/CodeGen/LoongArch/lasx/vselect.ll b/llvm/test/CodeGen/LoongArch/lasx/vselect.ll index 17ba28afc81f..44e4f71c8d08 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/vselect.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/vselect.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define void @select_v32i8_imm(ptr %res, ptr %a0) nounwind { ; CHECK-LABEL: select_v32i8_imm: @@ -49,16 +50,26 @@ define void @select_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind { } define void @select_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind { -; CHECK-LABEL: select_v8i32: -; CHECK: # %bb.0: -; CHECK-NEXT: xvld $xr0, $a1, 0 -; CHECK-NEXT: xvld $xr1, $a2, 0 -; CHECK-NEXT: ori $a1, $zero, 0 -; CHECK-NEXT: lu32i.d $a1, -1 -; CHECK-NEXT: xvreplgr2vr.d $xr2, $a1 -; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2 -; CHECK-NEXT: xvst $xr0, $a0, 0 -; CHECK-NEXT: ret +; LA32-LABEL: select_v8i32: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0) +; LA32-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI3_0) +; LA32-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: select_v8i32: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: ori $a1, $zero, 0 +; LA64-NEXT: lu32i.d $a1, -1 +; LA64-NEXT: xvreplgr2vr.d $xr2, $a1 +; LA64-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret %v0 = load <8 x i32>, ptr %a0 %v1 = load <8 x i32>, ptr %a1 %sel = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i32> %v0, <8 x i32> %v1 diff --git a/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll b/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll index df639cb78cd1..2efe96fe18d4 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll @@ -1,4 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s define <32 x i8> @widen_shuffle_mask_v32i8_to_v16i16(<32 x i8> %a, <32 x i8> %b) { |