diff options
Diffstat (limited to 'llvm/test/CodeGen/Hexagon')
1266 files changed, 1473 insertions, 1388 deletions
diff --git a/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll b/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll index 81bc2f95ae88..c61e5a7fed68 100644 --- a/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll +++ b/llvm/test/CodeGen/Hexagon/64bit_tstbit.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test checks that S2_tstbit_i instruction is generated ; and it does not assert. diff --git a/llvm/test/CodeGen/Hexagon/Atomics.ll b/llvm/test/CodeGen/Hexagon/Atomics.ll index 886ddd08bd27..6e6be6354425 100644 --- a/llvm/test/CodeGen/Hexagon/Atomics.ll +++ b/llvm/test/CodeGen/Hexagon/Atomics.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=hexagon +; RUN: llc < %s -mtriple=hexagon @si = common global i32 0, align 4 @sll = common global i64 0, align 8 diff --git a/llvm/test/CodeGen/Hexagon/BranchPredict.ll b/llvm/test/CodeGen/Hexagon/BranchPredict.ll index ba60a4e2c455..197524a4d1ec 100644 --- a/llvm/test/CodeGen/Hexagon/BranchPredict.ll +++ b/llvm/test/CodeGen/Hexagon/BranchPredict.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -ifcvt-limit=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -ifcvt-limit=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; Check if the branch probabilities are reflected in the instructions: ; The basic block placement pass should place the more probable successor diff --git a/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll b/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll index 14aef485526b..1ef2e9fcc6e5 100644 --- a/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll +++ b/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll b/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll index 7ff3c357c79d..e6c0ba190fd2 100644 --- a/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll +++ b/llvm/test/CodeGen/Hexagon/Halide_vec_cast_trunc2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll b/llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll index ac4083ba3759..5da79ec75e52 100644 --- a/llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll +++ b/llvm/test/CodeGen/Hexagon/M4_mpyri_addi_global.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = add(##g0,mpyi(r{{[0-9]+}},#24)) %s.0 = type { i32, i32, i32, i32, i32, i8 } diff --git a/llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll b/llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll index 9247a6cbe836..239c1b5fead6 100644 --- a/llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll +++ b/llvm/test/CodeGen/Hexagon/M4_mpyrr_addi_global.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = add(##g0{{.*}},mpyi(r{{[0-9]+}},r{{[0-9]+}})) %s.0 = type { %s.1, ptr } diff --git a/llvm/test/CodeGen/Hexagon/NVJumpCmp.ll b/llvm/test/CodeGen/Hexagon/NVJumpCmp.ll index 2ef35172279f..1ff67c2feb7f 100644 --- a/llvm/test/CodeGen/Hexagon/NVJumpCmp.ll +++ b/llvm/test/CodeGen/Hexagon/NVJumpCmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s ; Look for an instruction, we really just do not want to see an abort. ; CHECK: trace_event diff --git a/llvm/test/CodeGen/Hexagon/P08214.ll b/llvm/test/CodeGen/Hexagon/P08214.ll index c06aa2c5a729..31b424504252 100644 --- a/llvm/test/CodeGen/Hexagon/P08214.ll +++ b/llvm/test/CodeGen/Hexagon/P08214.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/PR33749.ll b/llvm/test/CodeGen/Hexagon/PR33749.ll index 4441fe235103..ec5c25e2d552 100644 --- a/llvm/test/CodeGen/Hexagon/PR33749.ll +++ b/llvm/test/CodeGen/Hexagon/PR33749.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This testcase used to fail with "cannot select 'i1 = add x, y'". ; Check for some sane output: ; CHECK: xor(p{{[0-3]}},p{{[0-3]}}) diff --git a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll index 10db03550bbf..c6077327727e 100644 --- a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll +++ b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 -hexagon-initial-cfg-cleanup=0 --stats -o - 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -mcpu=hexagonv60 -hexagon-initial-cfg-cleanup=0 --stats -o - 2>&1 < %s | FileCheck %s ; This was aborting while processing SUnits. ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/V60-VDblNew.ll b/llvm/test/CodeGen/Hexagon/V60-VDblNew.ll index 76b05fcdde05..44bca98b9585 100644 --- a/llvm/test/CodeGen/Hexagon/V60-VDblNew.ll +++ b/llvm/test/CodeGen/Hexagon/V60-VDblNew.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-vecdbl-nv-stores=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -disable-vecdbl-nv-stores=0 < %s | FileCheck %s ; CHECK-NOT: v{{[0-9]*}}.new diff --git a/llvm/test/CodeGen/Hexagon/abi-padding-2.ll b/llvm/test/CodeGen/Hexagon/abi-padding-2.ll index 9e5ec81742ad..9576ac9716d9 100644 --- a/llvm/test/CodeGen/Hexagon/abi-padding-2.ll +++ b/llvm/test/CodeGen/Hexagon/abi-padding-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv65 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 < %s | FileCheck %s ; C file was: ; struct S { char b; long long a; }; diff --git a/llvm/test/CodeGen/Hexagon/abi-padding.ll b/llvm/test/CodeGen/Hexagon/abi-padding.ll index 32a44b5f4387..83c66d7dbf9c 100644 --- a/llvm/test/CodeGen/Hexagon/abi-padding.ll +++ b/llvm/test/CodeGen/Hexagon/abi-padding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv65 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 < %s | FileCheck %s ; C file was: ; struct S { int a[3];}; @@ -17,7 +17,7 @@ ; Check that the flag hexagon-disable-args-min-alignment works and the struct ; is aligned to 8 bytes. -; RUN: llc -march=hexagon -mcpu=hexagonv65 -hexagon-disable-args-min-alignment < %s | FileCheck -check-prefix=HEXAGON_LEGACY %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -hexagon-disable-args-min-alignment < %s | FileCheck -check-prefix=HEXAGON_LEGACY %s ; HEXAGON_LEGACY: memw(r{{[0-9]+}}+#16) = #9 diff --git a/llvm/test/CodeGen/Hexagon/abs.ll b/llvm/test/CodeGen/Hexagon/abs.ll index 79b0bd03ca96..3f2e19de9f30 100644 --- a/llvm/test/CodeGen/Hexagon/abs.ll +++ b/llvm/test/CodeGen/Hexagon/abs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: r0 = abs(r0) diff --git a/llvm/test/CodeGen/Hexagon/absaddr-store.ll b/llvm/test/CodeGen/Hexagon/absaddr-store.ll index 4574c4e5c794..23708b79bbce 100644 --- a/llvm/test/CodeGen/Hexagon/absaddr-store.ll +++ b/llvm/test/CodeGen/Hexagon/absaddr-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s ; Check that we generate load instructions with absolute addressing mode. @a0 = external global i32 diff --git a/llvm/test/CodeGen/Hexagon/absimm.ll b/llvm/test/CodeGen/Hexagon/absimm.ll index 767324b1ab60..3288d8a1564c 100644 --- a/llvm/test/CodeGen/Hexagon/absimm.ll +++ b/llvm/test/CodeGen/Hexagon/absimm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate absolute addressing mode instructions ; with immediate value. diff --git a/llvm/test/CodeGen/Hexagon/add-use.ll b/llvm/test/CodeGen/Hexagon/add-use.ll index c5e8d49ac6e9..b1372c338a4c 100644 --- a/llvm/test/CodeGen/Hexagon/add-use.ll +++ b/llvm/test/CodeGen/Hexagon/add-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Do not want to see register copies in the loop. ; CHECK-NOT: r{{[0-9]*}} = r{{[0-9]*}} diff --git a/llvm/test/CodeGen/Hexagon/add_int_double.ll b/llvm/test/CodeGen/Hexagon/add_int_double.ll index 75b1488923ac..5ad7bb8c6d9f 100644 --- a/llvm/test/CodeGen/Hexagon/add_int_double.ll +++ b/llvm/test/CodeGen/Hexagon/add_int_double.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}}:{{[0-9]+}} = add(r{{[0-9]+}}:{{[0-9+]}},r{{[0-9]+}}:{{[0-9]+}}):raw:{{..}} define i64 @f0(i32 %a0, i64 %a1) #0 { diff --git a/llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll b/llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll index 92643f8d135d..3c3c2b189cee 100644 --- a/llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll +++ b/llvm/test/CodeGen/Hexagon/add_mpi_RRR.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; CHECK: [[REG0:(r[0-9]+)]] = add(r{{[0-9]+}},mpyi([[REG0]],r{{[0-9]+}}) ; CHECK: [[REG0:(r[0-9]+)]] = add(r{{[0-9]+}},mpyi([[REG0]],r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/addaddi.ll b/llvm/test/CodeGen/Hexagon/addaddi.ll index a0b18f2f0580..cfeb2f0fe603 100644 --- a/llvm/test/CodeGen/Hexagon/addaddi.ll +++ b/llvm/test/CodeGen/Hexagon/addaddi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for S4_addaddi: ; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},add(r{{[0-9]+}},#2)) diff --git a/llvm/test/CodeGen/Hexagon/addasl-address.ll b/llvm/test/CodeGen/Hexagon/addasl-address.ll index 10e923c9e84f..5eabb721e333 100644 --- a/llvm/test/CodeGen/Hexagon/addasl-address.ll +++ b/llvm/test/CodeGen/Hexagon/addasl-address.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK: r{{[0-9]*}} = add(##g0,asl(r{{[0-9]*}},#2)) %s.0 = type { i16, i8 } diff --git a/llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll b/llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll index 821ed011fed7..cbee055ca284 100644 --- a/llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll +++ b/llvm/test/CodeGen/Hexagon/addh-sext-trunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{H|h}}) target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/addh-shifted.ll b/llvm/test/CodeGen/Hexagon/addh-shifted.ll index 697a5c5c69bf..62508af8b698 100644 --- a/llvm/test/CodeGen/Hexagon/addh-shifted.ll +++ b/llvm/test/CodeGen/Hexagon/addh-shifted.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}):<<16 define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/addh.ll b/llvm/test/CodeGen/Hexagon/addh.ll index b7719929a1c9..f05f3c32689a 100644 --- a/llvm/test/CodeGen/Hexagon/addh.ll +++ b/llvm/test/CodeGen/Hexagon/addh.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s -; RUN: llc -march=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}) define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll b/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll index 3a0019ebd4ea..bce448abc4fa 100644 --- a/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll +++ b/llvm/test/CodeGen/Hexagon/addr-calc-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Test whether we can produce minimal code for this complex address ; calculation. diff --git a/llvm/test/CodeGen/Hexagon/addr-mode-opt.ll b/llvm/test/CodeGen/Hexagon/addr-mode-opt.ll index e47bda84e4e5..4f1aa2719bbd 100644 --- a/llvm/test/CodeGen/Hexagon/addr-mode-opt.ll +++ b/llvm/test/CodeGen/Hexagon/addr-mode-opt.ll @@ -1,6 +1,6 @@ ; Broken by r326208 ; XFAIL: * -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK-NOT: add(r{{[0-9]+}},#2) ; CHECK-NOT: add(r{{[0-9]+}},#3) ; CHECK: memub(r{{[0-9]+}}+#2) diff --git a/llvm/test/CodeGen/Hexagon/addrmode-align.ll b/llvm/test/CodeGen/Hexagon/addrmode-align.ll index c6d0978d3190..b449d3be84c5 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-align.ll +++ b/llvm/test/CodeGen/Hexagon/addrmode-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: [[REG0:(r[0-9]+)]] = add(r29 ; CHECK: [[REG1:(r[0-9]+)]] = add([[REG0]],#8) diff --git a/llvm/test/CodeGen/Hexagon/addrmode-globoff.mir b/llvm/test/CodeGen/Hexagon/addrmode-globoff.mir index 7ac172f66d90..91308c33e116 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-globoff.mir +++ b/llvm/test/CodeGen/Hexagon/addrmode-globoff.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass amode-opt %s -o - | FileCheck %s --- | @g0 = external global [16 x i16], align 8 diff --git a/llvm/test/CodeGen/Hexagon/addrmode-immop.mir b/llvm/test/CodeGen/Hexagon/addrmode-immop.mir index 1412d31f35ac..23487a3bb741 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-immop.mir +++ b/llvm/test/CodeGen/Hexagon/addrmode-immop.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass amode-opt -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass amode-opt -verify-machineinstrs %s -o - | FileCheck %s # REQUIRES: asserts # Check that this doesn't crash. diff --git a/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll b/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll index dfe88a2ba3f9..117041c97d6c 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll +++ b/llvm/test/CodeGen/Hexagon/addrmode-indoff.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Bug 6840. Use absolute+index addressing. diff --git a/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll b/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll index 5a9dd03ac6ac..9db8962b53d9 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll +++ b/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that the addressing mode optimization does not propagate ; an add instruction where the base register would have a different diff --git a/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir b/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir index 919bf5f8ae88..742edddddfe4 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir +++ b/llvm/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass amode-opt %s -o - | FileCheck %s # Check that the addasl is not propagated into the addressing mode. # CHECK-NOT: L4_loadri_ur diff --git a/llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir b/llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir index ab035d9b9222..f1e9d89fd3e9 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir +++ b/llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: call f1 diff --git a/llvm/test/CodeGen/Hexagon/addrmode-offset.ll b/llvm/test/CodeGen/Hexagon/addrmode-offset.ll index 2afe8224ae8a..e560299d19cb 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-offset.ll +++ b/llvm/test/CodeGen/Hexagon/addrmode-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK-NOT: [[REG0:(r[0-9]+)]] = memw([[REG0:(r[0-9]+)]]<<#2+##state-4) diff --git a/llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir b/llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir index ce6e398aa28a..58083f696795 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir +++ b/llvm/test/CodeGen/Hexagon/addrmode-opt-assert.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -mcpu=hexagonv62 -run-pass amode-opt %s -o - +# RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -run-pass amode-opt %s -o - # REQUIRES: asserts # # This test merely checks if the pass that optimizes addressing modes in the diff --git a/llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir b/llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir index 282aefd73d89..fea1c69807e1 100644 --- a/llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir +++ b/llvm/test/CodeGen/Hexagon/addrmode-rr-to-io.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass amode-opt %s -o - | FileCheck %s # This testcase used to crash. # CHECK: S2_storerb_io killed $r0, @var_i8, killed $r2 diff --git a/llvm/test/CodeGen/Hexagon/addrspacecast-crash.ll b/llvm/test/CodeGen/Hexagon/addrspacecast-crash.ll new file mode 100644 index 000000000000..ce197bdeea1f --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/addrspacecast-crash.ll @@ -0,0 +1,12 @@ +; Tests if addrspacecast is handled in Hexagon backend + +; REQUIRES: asserts + +; RUN: llc -march=hexagon %s -o /dev/null + +define double @f(ptr %G, ptr %x) { +BB: + %Castaddrspacecast = addrspacecast ptr %x to ptr addrspace(1) + store ptr addrspace(1) %Castaddrspacecast, ptr %G, align 8 + ret double 0.000000e+00 +} diff --git a/llvm/test/CodeGen/Hexagon/addsubcarry.ll b/llvm/test/CodeGen/Hexagon/addsubcarry.ll index 85eb71bfc533..9b78118cf9d8 100644 --- a/llvm/test/CodeGen/Hexagon/addsubcarry.ll +++ b/llvm/test/CodeGen/Hexagon/addsubcarry.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @g = global i128 zeroinitializer, align 8 diff --git a/llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll b/llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll index 3bcbd012523a..56c04c27ba84 100644 --- a/llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll +++ b/llvm/test/CodeGen/Hexagon/adjust-latency-stackST.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that if there's only one store to the stack, it gets packetized ; with allocframe as there's a latency of 2 cycles between allocframe and diff --git a/llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll b/llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll index ac8e47d565ca..ad4fe5b6c61c 100644 --- a/llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll +++ b/llvm/test/CodeGen/Hexagon/aggr-antidep-tied.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s ; REQUIRES: asserts ; Test that the aggressive anti-dependence breaker does not attempt diff --git a/llvm/test/CodeGen/Hexagon/aggr-copy-order.ll b/llvm/test/CodeGen/Hexagon/aggr-copy-order.ll index c539a8adf250..80467b6c4492 100644 --- a/llvm/test/CodeGen/Hexagon/aggr-copy-order.ll +++ b/llvm/test/CodeGen/Hexagon/aggr-copy-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr=-packets -hexagon-check-bank-conflict=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=-packets -hexagon-check-bank-conflict=0 < %s | FileCheck %s ; Do not check stores. They undergo some optimizations in the DAG combiner ; resulting in getting out of order. There is likely little that can be ; done to keep the original order. diff --git a/llvm/test/CodeGen/Hexagon/aggr-licm.ll b/llvm/test/CodeGen/Hexagon/aggr-licm.ll index 84496d5cec33..88b65348168d 100644 --- a/llvm/test/CodeGen/Hexagon/aggr-licm.ll +++ b/llvm/test/CodeGen/Hexagon/aggr-licm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -enable-misched=false | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -enable-misched=false | FileCheck %s ; Test that LICM doesn't hoist an instruction incorrectly ; when register aliases are not processed. In this case, LICM hoists diff --git a/llvm/test/CodeGen/Hexagon/aggressive_licm.ll b/llvm/test/CodeGen/Hexagon/aggressive_licm.ll index 3936e232fec2..aa3a50dc70e1 100644 --- a/llvm/test/CodeGen/Hexagon/aggressive_licm.ll +++ b/llvm/test/CodeGen/Hexagon/aggressive_licm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-block-placement=0 -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-block-placement=0 -O2 < %s | FileCheck %s ; CHECK: [[Reg:r[0-9]+]] = {{lsr\(r[0-9]+,#16\)|extractu\(r[0-9]+,#16,#16\)}} ; CHECK-NOT: [[Reg]] = #0 ; CHECK: align diff --git a/llvm/test/CodeGen/Hexagon/align_Os.ll b/llvm/test/CodeGen/Hexagon/align_Os.ll index aa9368ce64a4..652cce3af2c9 100644 --- a/llvm/test/CodeGen/Hexagon/align_Os.ll +++ b/llvm/test/CodeGen/Hexagon/align_Os.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: {{.balign 4|.p2align 2}} ; CHECK: {{.balign 4|.p2align 2}} diff --git a/llvm/test/CodeGen/Hexagon/align_test.ll b/llvm/test/CodeGen/Hexagon/align_test.ll index 900066543513..079173cb8935 100644 --- a/llvm/test/CodeGen/Hexagon/align_test.ll +++ b/llvm/test/CodeGen/Hexagon/align_test.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: memw ; CHECK: memub diff --git a/llvm/test/CodeGen/Hexagon/alu64.ll b/llvm/test/CodeGen/Hexagon/alu64.ll index 49e06d2da0d8..67218fd9866e 100644 --- a/llvm/test/CodeGen/Hexagon/alu64.ll +++ b/llvm/test/CodeGen/Hexagon/alu64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK-LABEL: @test00 ; CHECK: = cmp.eq(r1:0,r3:2) diff --git a/llvm/test/CodeGen/Hexagon/always-ext.ll b/llvm/test/CodeGen/Hexagon/always-ext.ll index 159ec0cfcb79..7b64b2346db8 100644 --- a/llvm/test/CodeGen/Hexagon/always-ext.ll +++ b/llvm/test/CodeGen/Hexagon/always-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we don't generate an invalid packet with too many instructions ; due to a store that has a must-extend operand. diff --git a/llvm/test/CodeGen/Hexagon/anti-dep-partial.mir b/llvm/test/CodeGen/Hexagon/anti-dep-partial.mir index 00ffd968ef09..b7a3f8051f69 100644 --- a/llvm/test/CodeGen/Hexagon/anti-dep-partial.mir +++ b/llvm/test/CodeGen/Hexagon/anti-dep-partial.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s --- | declare void @check(i64, i32, i32, i64) diff --git a/llvm/test/CodeGen/Hexagon/args.ll b/llvm/test/CodeGen/Hexagon/args.ll index 998b0b0f56b8..ed318e67b68f 100644 --- a/llvm/test/CodeGen/Hexagon/args.ll +++ b/llvm/test/CodeGen/Hexagon/args.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-DAG: r5:4 = combine(#6,#5) ; CHECK-DAG: r3:2 = combine(#4,#3) ; CHECK-DAG: r1:0 = combine(#2,#1) diff --git a/llvm/test/CodeGen/Hexagon/ashift-left-right.ll b/llvm/test/CodeGen/Hexagon/ashift-left-right.ll index bc3e813220db..db377ff9ea22 100644 --- a/llvm/test/CodeGen/Hexagon/ashift-left-right.ll +++ b/llvm/test/CodeGen/Hexagon/ashift-left-right.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define i32 @foo(i32 %a, i32 %b) nounwind readnone { ; CHECK: lsl diff --git a/llvm/test/CodeGen/Hexagon/asr-rnd.ll b/llvm/test/CodeGen/Hexagon/asr-rnd.ll index cd088dd8f013..663cd3d4abc6 100644 --- a/llvm/test/CodeGen/Hexagon/asr-rnd.ll +++ b/llvm/test/CodeGen/Hexagon/asr-rnd.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check if we generate rounding-asr instruction. It is equivalent to ; Rd = ((Rs >> #u) +1) >> 1. diff --git a/llvm/test/CodeGen/Hexagon/asr-rnd64.ll b/llvm/test/CodeGen/Hexagon/asr-rnd64.ll index e32bdff7d764..a8f296ab0ed7 100644 --- a/llvm/test/CodeGen/Hexagon/asr-rnd64.ll +++ b/llvm/test/CodeGen/Hexagon/asr-rnd64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check if we generate rounding-asr instruction. It is equivalent to ; Rd = ((Rs >> #u) +1) >> 1. diff --git a/llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll b/llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll index b81237cdb212..674c3e1dbdaf 100644 --- a/llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll +++ b/llvm/test/CodeGen/Hexagon/assert-postinc-ptr-not-value.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: f1 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll b/llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll index 858bb20da7e3..4372cad3f87c 100644 --- a/llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll +++ b/llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s %s.0 = type { i8 } @g0 = internal global i8 0, align 1 diff --git a/llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll b/llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll index f1ffc5f4f68d..5ac915bf58fc 100644 --- a/llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll +++ b/llvm/test/CodeGen/Hexagon/atomic-rmw-add.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: .LBB0_1: ; CHECK: [[R1:r[0-9]+]] = memw_locked(r0) diff --git a/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll index 92a3da1793b9..ba09c3e2852d 100644 --- a/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll +++ b/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; CHECK-LABEL: atomicrmw_usub_cond_i8: diff --git a/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll index d51c9554a022..6b6946d0dbb0 100644 --- a/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; CHECK-LABEL: atomicrmw_uinc_wrap_i8: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/abs.ll b/llvm/test/CodeGen/Hexagon/autohvx/abs.ll index f22537d97d8e..db2f1f7ad03b 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/abs.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/abs.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <128 x i8> @abs80(<128 x i8> %a0) #0 { ; CHECK-LABEL: abs80: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll b/llvm/test/CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll index 00ee5842f93c..5bbe24b6fb94 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/addi-offset-opt-addr-mode.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=hexagon -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE1 +; RUN: llc -mtriple=hexagon -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE1 -; RUN: llc -march=hexagon -disable-hexagon-amodeopt=0 < %s | FileCheck %s --check-prefix=CHECK-AMODE +; RUN: llc -mtriple=hexagon -disable-hexagon-amodeopt=0 < %s | FileCheck %s --check-prefix=CHECK-AMODE ; CHECK-NO-AMODE1: r{{[0-9]+}} = add([[REG1:(r[0-9]+)]],#{{[0-9]+}}) ; CHECK-NO-AMODE1: r{{[0-9]+}} = add([[REG1]],#{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/addi-opt-predicated-def-bug.ll b/llvm/test/CodeGen/Hexagon/autohvx/addi-opt-predicated-def-bug.ll index 0464bea339fa..db08e06f77c1 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/addi-opt-predicated-def-bug.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/addi-opt-predicated-def-bug.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; We do not want the opt-addr-mode pass to modify the addi instructions whose ; base register has a predicated register definition diff --git a/llvm/test/CodeGen/Hexagon/autohvx/align-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/align-128b.ll index e360fc6ef429..64ccc9b0c768 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/align-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/align-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK-NOT: valign diff --git a/llvm/test/CodeGen/Hexagon/autohvx/align-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/align-64b.ll index bfc05b6860ee..14f9f77c65c3 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/align-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/align-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK-NOT: valign diff --git a/llvm/test/CodeGen/Hexagon/autohvx/align2-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/align2-128b.ll index 75eea82a280c..cf251572db60 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/align2-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/align2-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK-NOT: v0 = diff --git a/llvm/test/CodeGen/Hexagon/autohvx/align2-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/align2-64b.ll index 34bc04432870..f82400ce5675 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/align2-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/align2-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK-NOT: v0 = diff --git a/llvm/test/CodeGen/Hexagon/autohvx/arith-float.ll b/llvm/test/CodeGen/Hexagon/autohvx/arith-float.ll index 0ba7f2c04601..43f544b88944 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/arith-float.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/arith-float.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <64 x half> @f0(<64 x half> %a0, <64 x half> %a1) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/arith.ll b/llvm/test/CodeGen/Hexagon/autohvx/arith.ll index 348f3dd1df05..f45dce779111 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/arith.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/arith.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; --- and diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll index d4e17f9f49fe..378620d446c3 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0 ; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vzxt(v0.ub) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll index 586f0a3968bd..adbb41ee42e4 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0 ; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vzxt(v0.ub) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll index 08dd342d0632..ea14e5ab9f2a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: t00 ; CHECK: vand(v{{[0-9:]+}},v{{[0-9:]+}}) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll index 3895670a0443..2265faf5c192 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: t00 ; CHECK: vand(v{{[0-9:]+}},v{{[0-9:]+}}) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bswap.ll b/llvm/test/CodeGen/Hexagon/autohvx/bswap.ll index e5e507c0ae76..c6b569128d3c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/bswap.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/bswap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00 ; CHECK: [[R00:r[0-9]+]] = ##16843009 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll index e261e99f1a63..d56520da78ae 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-float-type.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this code does compile. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll index 102ebd26c825..ed85e57bb06e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that vector is produced with vxor ; CHECK: v{{[0-9]*}} = vxor diff --git a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll index 85a7872b8a61..512d0242235f 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that vector is produced with vxor ; CHECK: v{{[0-9]*}} = vxor diff --git a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll index 0e44358b34c1..2bf960f970b7 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: sfcmp diff --git a/llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll b/llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll index e4a423f0a149..d0210e30fdf6 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(<128 x i8> %a0, ptr %a1) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll index 660c7365d2ed..a033f2003151 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: concat_8: ; CHECK: v[[H00:[0-9]+]]:[[L00:[0-9]+]] = vcombine(v0,v1) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-64b.ll index 47011fb6308d..b01bb7eaa826 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/concat-vectors-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: concat_8: ; CHECK: v[[H00:[0-9]+]]:[[L00:[0-9]+]] = vcombine(v0,v1) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll index 67ccfb3c12da..62d81379922e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/contract-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK: v0.b = vshuffe(v1.b,v0.b) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll index 19a126027c10..07a975c6d545 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/contract-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK: v0.b = vshuffe(v1.b,v0.b) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll b/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll index f5096ea9128f..47b891d31be3 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-fp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <64 x half> @f0(<64 x float> %a0) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll b/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll index 889b4b3fbabf..76ac90661b46 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/conv-fp-int-ieee.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <64 x i16> @f0(<64 x half> %a0) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll b/llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll index cadccc3efca2..0be4e8bb31d0 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/ctpop-split.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check if popcounts of vector pairs are properly split. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll index 429ead4a47f7..30a3b2d7e93a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/deal-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check the individual vdeal shuffles for all 128 controls. ; Note: for shuffles with a single 2x2 transpose, vshuff is generated instead diff --git a/llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll index 92f05b58898f..525d942d518e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/deal-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check the individual vdeal shuffles for all 64 controls. ; Note: for shuffles with a single 2x2 transpose, vshuff is generated instead diff --git a/llvm/test/CodeGen/Hexagon/autohvx/delta-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/delta-128b.ll index fe221edeb41b..a8512f828532 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/delta-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/delta-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK: vdelta diff --git a/llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll index c4961f549e5d..b995eaf1bb5f 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/delta-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK: vdelta diff --git a/llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll index 59f56446e341..5ebe127109d0 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/delta2-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK-DAG: vdelta diff --git a/llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll b/llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll index 10d8822a4600..78cf4ae62aa5 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/extract-element.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that extract-element is handled. ; CHECK-LABEL: ext_00: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll b/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll index 089bc9967d08..614184ed9b53 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll @@ -1,4 +1,4 @@ -; RUN: opt -march=hexagon -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s +; RUN: opt -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s ; REQUIRES: asserts ; Check that the cost model makes vectorization non-profitable. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll b/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll index 66db73f5c69f..ac51662242de 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll index c69e76d2d4e6..a9bf133273b8 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/funnel-128b.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V60 %s -; RUN: llc -march=hexagon -mattr=+hvxv62,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V62 %s -; RUN: llc -march=hexagon -mattr=+hvxv66,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V66 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv60,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V60 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv62,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V62 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv66,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V66 %s define <128 x i8> @f0(<128 x i8> %a0, <128 x i8> %a1, i8 %a2) #0 { ; V60-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll b/llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll index 78092e813587..7d6705843d01 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate a proper vinsert instruction for f16 types. ; CHECK: vinsert diff --git a/llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll b/llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll index 13ff6154f15a..2ba3e2206169 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/hvx-idiom-empty-results.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: func_end diff --git a/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll b/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll index 5cfa09b0822b..c0e38b924303 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s -verify-machineinstrs | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll index a4b24a1a6110..0a3ee5e12a2c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll @@ -1,4 +1,4 @@ -; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s +; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s ; Check that the loop has been interleaved. ; CHECK: store <64 x i32> %interleaved.vec diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll index 39fb325db4a2..95e16f60a34a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This code causes any_extend_vector_inreg to appear in the selection DAG. ; Make sure that it is handled instead of crashing. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll index 05b67c0da136..3300880b17db 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-anyext-pair.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. ; CHECK: vunpack diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll index a98cffbfc8a4..08343fe5cd7c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This testcase exposed a problem with a previous handling of selecting ; constant vectors (for vdelta). Originally a bitcast of a vsplat was diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll index e957a4a8eb6d..3ff0469fa701 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. ; CHECK: vsplat diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll index d2dcacb94332..dad056f1d94b 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-bool-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this testcase doesn't crash. ; CHECK: sfcmp diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll index c5c76fef0518..e4898bd6d5a1 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; During lowering, a BUILD_VECTOR of undef values was created. This was ; not properly handled by buildHvxVectorReg, which tried to generate a diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll index e6b8445f5121..b5387ae98e35 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-build-vector.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <32 x i32> @fred(i32 %a0) #0 { ; CHECK-LABEL: fred: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll index 1a7c281f22a8..362918e0ca53 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-multiple.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This code generates a concat_vectors with more than 2 inputs. Make sure ; that this compiles successfully. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll index 73ac65f7e147..5baf2f076679 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; Check for successful compilation. ; CHECK: sfcmp diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll index 678fda150811..05df6f4e698e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for a non-crashing output. ; CHECK: vsplat diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll index 4e378b71f5a7..814c1a499a02 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; The generation of a constant vector in the selection step resulted in ; a VSPLAT, which, deeper in the expression tree had an unrelated BITCAST. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll index 3576f63d11ab..5cdd585314fd 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-imm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; Check that this doesn't crash. A "splat_vector" was causing trouble, ; initially, so check that a vsplat appears in the output. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll index 9386a815bdc3..208794eebbca 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r[[V:[0-9]+]] = ##16843009 ; CHECK: vsplat(r[[V]]) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll index fbd72b275c39..7f1822054e61 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that the elements of the constants have correct type. ; CHECK: .half 31 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll index 7b6b78bf961f..a27e50fb2931 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads-noindexed.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; Check for successful compilation. ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll index c2de46a17b9d..86e94460f739 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-expand-unaligned-loads.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-packetizer -hexagon-align-loads < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-packetizer -hexagon-align-loads < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll index 0d27a0a4d944..1d457b38612b 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure this doesn't crash. ; CHECK: = mem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll index c0d985d40a98..d3defd8bd382 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: memw diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll index 6bf2cdaf146e..d00b6826f630 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-hvx-pred-bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: danny: ; CHECK: vrmpy diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll index dba7421b39de..fb56fd2e05bf 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-insert-subvector-v4i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to crash. Make sure that it compiles successfully. ; CHECK: dealloc_return diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll index c3428f5728e3..d4558a32e19a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This will crash with "cannot select" error, if the intrinsic matching code ; (HexagonDepMapAsm2Intrin.td) uses predicate "HasV69" instead of "UseHVXV69". diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll index 2b11c0631a12..18481bdcd12f 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for a non-crashing output. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll index e288f5260c14..b6dc87009e86 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-q-legalization-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Check that this doesn't crash. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll index f22b99c852cd..3f6a0401cd91 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-q2v-pair.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that this doesn't crash. ; CHECK: vadd diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll index 03f9f81da3d1..791c6a6659df 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; Make sure we can select QFALSE. ; CHECK: vcmp.gt(v0.w,v0.w) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll index 1f39acdce5e3..e07eedc45760 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-select-const.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: vlut32 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll index f189775a8fbe..954a84ac50f8 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-select-q.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that selection (based on i1) between vector predicates works. define <128 x i8> @f0(<128 x i8> %a0, <128 x i8> %a1, <128 x i8> %a2, <128 x i8> %a3, i32 %a4) #0 { diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll index f094b139f181..627d049f1f6c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair-fp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll index fb3be22f8e26..ea4e8d9fd76e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; Check that a setcc of a vector pair is handled (without crashing). ; CHECK: vcmp diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll index b0fbb1ceaf0f..60e0b4c14087 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-setcc-v256i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. The select should be broken up into two ; vmux instructions. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll index 72da335ba798..ccd128424c17 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-sext-inreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that both functions compile successfully. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll index c9e5e2f3c2ea..4dfa7e49054c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-shift-byte.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. ; CHECK: vasl diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll index 9ef4543790ba..97dc25931dba 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuff-single.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Perfect shuffle with single input vector. Half of it first needs to be ; transposed into the other vector before the generated shuffles can take diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll index b0c47cd7ded1..1c624a8fced2 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-gather.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Several shufflevector instructions have masks that are shorter than the ; source vectors. They "gather" a subset of the input elements into a single diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll index 7fd38098d556..9e2d07999a1c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-isdisel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. ; CHECK: dealloc_return diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll index b606608f81f5..ac21f8e74590 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-no-perfect-completion.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't end up being an entirely perfect shuffle. ; CHECK: vshuff diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll index a16bb4bc7183..aeb41455e6ec 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-shuffle-pack.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to ICE in selecting shuffle. Make sure it compiles successfully. ; Valign is a likely instruction to be generated here, so check for that. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll index 15739aaeaadf..935f4c5a8537 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-split-masked.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll index cb35286fafca..45aa49cbf1fa 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-store-bitcast-v128i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Primarily check if this compiles without failing. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll index 014a90cf7f23..3b21bd2b424e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate-legal.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; Truncating a type-to-be-widenened to a legal type (v8i8). ; Check that this compiles successfully. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll index 6fa0585843f4..e0db93553e1c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll index 2afc9fc0e96a..380f983d10ec 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; Check that we don't generate lots of vinserts (of 0 that should be undef). ; CHECK: vinsert diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll index 5565f1ea140b..94d561c152b4 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-vec-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll index 3319a76907ff..716e0367efe6 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1, ptr %a2) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll index 3e6523b69af8..eca43a1e3e58 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-vsplat-pair.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. ; CHECK: vsplat diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll index 5a9141d1bd5c..e7f6524bd561 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-memop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for successful compilation. ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll index 500451e9c4ec..d4d0d32a4000 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=16 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=16 < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: q[[Q0:[0-3]]] = vsetq(r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll index d6ebb9f4855b..6c5dec1c284e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-illegal-elem.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this does not crash. ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll index 0aaf54ae475e..a4b91f5f9e33 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-op.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s -; RUN: llc -march=hexagon -hexagon-hvx-widen=16 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=16 < %s | FileCheck %s ; Check for successful compilation. ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll index a40cc0ba06d5..674a0f6218b3 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This has a v32i8 = truncate v16i32 (64b mode), which was legalized to ; 64i8 = vpackl v32i32, for which there were no selection patterns provided. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll index 5921a56a3a99..06c91f1d6896 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; Check for successful compilation. ; Expect that the truncate to v32i8 is lowered to vdeale. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll index 91f56d75fb12..f2e6bf366bb0 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/logical-128b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32) #0 declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32) #0 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll index e782b4da0852..f52bea157801 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/logical-64b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #0 declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #0 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll b/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll index 22ba0d2bc0b0..607532beb30e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-cgp-delete-phis < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-cgp-delete-phis < %s | FileCheck %s ; REQUIRES: asserts ; Check that this testcase compiles successfully. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll b/llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll index 2096977d011b..61240782c728 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: vmemu diff --git a/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll b/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll index e2a9f0937c84..4e882f2c6a04 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll @@ -1,4 +1,4 @@ -; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s +; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s ; Check that the loop is vectorized with VF=32. ; CHECK: wide.load{{.*}} = load <32 x i32> ; CHECK: wide.load{{.*}} = load <32 x i16> diff --git a/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll index e3f14966be33..a5aaeff08580 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; minb diff --git a/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll index 4ec758e61387..9cf5f1c7f22a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; minb diff --git a/llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll b/llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll index cb58004e6350..dd6a148591cc 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/minmax-float.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-qfloat < %s | FileCheck %s -; RUN: llc -march=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-ieee-fp < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-qfloat < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-ieee-fp < %s | FileCheck %s ; min diff --git a/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll b/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll index e6e9a06291ba..ef0173880f02 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V60 %s -; RUN: llc -march=hexagon -mattr=+hvxv65,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V65 %s -; RUN: llc -march=hexagon -mattr=+hvxv69,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V69 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv60,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V60 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv65,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V65 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V69 %s define <64 x i16> @mulhs16(<64 x i16> %a0, <64 x i16> %a1) #0 { ; V60-LABEL: mulhs16: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll b/llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll index e7b4387516ed..f8e0543ae3b6 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that <24 x i32> is treated as an HVX vector type. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll b/llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll index fb89711f33bd..83277984ab3c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/perfect-single.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: perfect_single_64: ; CHECK: vdeal diff --git a/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll index e22d79b1d81e..812966ca5ab4 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-128b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s declare <32 x i32> @llvm.hexagon.V6.vL32b.pred.ai.128B(i1, ptr, i32) declare <32 x i32> @llvm.hexagon.V6.vL32b.npred.ai.128B(i1, ptr, i32) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll index d1a8f75f46a0..f26849dbd035 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/pred-vmem-64b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s declare <16 x i32> @llvm.hexagon.V6.vL32b.pred.ai(i1, ptr, i32) declare <16 x i32> @llvm.hexagon.V6.vL32b.npred.ai(i1, ptr, i32) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll b/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll index 866db19355bc..c7da2765d8e0 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/qmul-add-over-32-bit.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure the add isn't dropped. ; CHECK: vadd{{.*}}:carry diff --git a/llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll b/llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll index 29f418f02297..dee3b0ee976f 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/qmul-chop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -verify-machineinstrs | FileCheck %s ; Check that the code is not scalarized: check that no scalar multiplication ; are generated. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll b/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll index 866bb283fbad..872c93fa7cb2 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1, ptr %a2) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll b/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll index 3aebed035c2c..2c741f8878a4 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/reg-sequence.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This testcase is to check that we use REG_SEQUENCE for reordering whole ; vectors. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll index d324ab270029..1fd09afc1009 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <128 x i8> @test0000(<128 x i8> %a0, i8 %a1) #0 { ; CHECK-LABEL: test0000: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll index 637a342636ab..81a87a549fb5 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <64 x i8> @test0000(<64 x i8> %a0, i8 %a1) #0 { ; CHECK-LABEL: test0000: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll index efaa530ff658..7b815496bcb5 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuff-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check the individual vshuff shuffles for all 128 controls. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll index cd0416e65636..b33b3be8052a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuff-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check the individual vshuff shuffles for all 64 controls. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll index fdaf7eb24308..869124335132 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Generator: vdeal(0x37), vdeal(0x53), vshuff(0x2f), vdeal(0x4b), vdeal(0x27), vdeal(0x43), vshuff(0x1f), vdeal(0x5b), vshuff(0x7e), vshuff(0x6c), vdeal(0x5a), vdeal(0x38), vshuff(0x16), vshuff(0x44), vdeal(0x72) ; CHECK-LABEL: test_0000: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll index 8114f3c47f74..c81b3534e2eb 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuff-combos-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Generator: vdeal(0x1f), vshuff(0x32), vshuff(0x24), vshuff(0x26), vshuff(0x08), vdeal(0x3a), vshuff(0x0c), vdeal(0x0e), vdeal(0x30), vdeal(0x22), vdeal(0x14), vdeal(0x36), vdeal(0x18), vdeal(0x0a), vdeal(0x3c) ; CHECK-LABEL: test_0000: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll index 94d338dab52c..9ce849e464d9 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuff-perfect-inverted-pair.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: r[[R0:[0-9]+]] = #60 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll index 677b170a5659..6f3e40902658 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuff-single.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_vdealb_64: ; CHECK: v0.b = vdeal(v0.b) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll index d03f16cb8694..6b37f486f65a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-128b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <256 x i8> @f0(<128 x i8> %a0) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll index fd97aa3a6e31..ba130f6f34ae 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-expanding-64b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <128 x i8> @f0(<64 x i8> %a0) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll index b10ca6825c62..a9542d5b4a30 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-128b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <128 x i8> @test_00(<128 x i8> %a0, <128 x i8> %a1) #0 { ; CHECK-LABEL: test_00: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll index 18a9c0256a90..61be86272eb9 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/shuffle-half-64b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <64 x i8> @test_00(<64 x i8> %a0, <64 x i8> %a1) #0 { ; CHECK-LABEL: test_00: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/splat.ll b/llvm/test/CodeGen/Hexagon/autohvx/splat.ll index eea089851e9c..45d2e5e395dd 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/splat.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/splat.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Splat immediate, 8-bit, v60 define <128 x i8> @f0() #0 { diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll b/llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll index 7bf17b952c75..3748bad6200f 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll index 917c18e46791..27365abe2e27 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-addr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; Test that the Hexagon Vector Combine pass computes the address ; correctly when the loading objects that contain extra padding diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll index 7aad382e6702..265cb1e2478a 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Test that the HexagonVectorCombine pass does not move an instruction diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll index cd075c9a9953..ecfb74d39c1c 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-bad-move3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll index 68368ce72843..db9963c61508 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-base-type-mismatch.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; The getelementptr's based on %a2, but with different base types caused ; a problem in vector alignment code. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll index 63c15deb799e..a0e094531b8e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Function Attrs: nounwind define <32 x i32> @f0(ptr %a0, i32 %a1) #0 { diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll index f65418333539..26c24daa2ec7 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-interleaved.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; In this testcase, when loads were moved close to users, they were actualy ; moved right before the consuming stores. This was after the store group diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll index 2f1c7035d048..45f849465dec 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-only-phi-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; One of the loads is only used in a PHI instruction. Make sure the PHI use ; still counts as a user of the load (and that the load is not removed). diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll index f8bf0e9957ab..1e0a42ec1310 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll index 5cf87cc5b8c4..536d5f779421 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-rescale-nonint.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll index 345d27d96fa6..7d475e37b9a2 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-scalar-mask.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll index 9726fe88eb5f..48aa1d5a61a7 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store-mask.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll index 876b02befe19..07748e3ca40e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hvc-va-full-stores < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hvc-va-full-stores < %s | FileCheck %s ; Make sure we generate 3 aligned stores. ; CHECK: vmem({{.*}}) = diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll index 7679346e3ea5..590b4fe9aa6f 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-terminator.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll index 1f6ac0d1ff3f..1fdb75f701fe 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-align-use-in-different-block.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to crash because of calling isSafeToMoveBeforeInBB with source ; and target in different blocks. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll index 2252d95979c4..a9483037e14b 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; --- Byte diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll index 55ac8981a1b2..7673f8b12264 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; --- Byte diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll index 3937b2ed97f2..f7e72b26b7eb 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-compare-float.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-qfloat < %s | FileCheck %s -; RUN: llc -march=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-ieee-fp < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-qfloat < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-ieee-fp < %s | FileCheck %s ; --- Half diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll index 0626bf46ac54..0f41472fba1e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-load-store-basic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll b/llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll index d7ce73a19dfc..45939973b4c8 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll index 1b464a404e14..1e098bd16ac5 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vext-128b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK: v1:0.h = vunpack(v0.b) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll index 7791fa4a81ee..de83ca9ccb23 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vext-64b.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK: v1:0.h = vunpack(v0.b) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll b/llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll index c18672ba0a83..ac024a09c474 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vmpy-parts.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V60 %s -; RUN: llc -march=hexagon -mattr=+hvxv62,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V62 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv60,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V60 %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv62,+hvx-length128b,-packets < %s | FileCheck --check-prefix=V62 %s define <32 x i32> @f0(<32 x i32> %a0, <32 x i32> %a1) #0 { ; V60-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll b/llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll index b08542da0e3f..2da306830d66 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/vmux-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for the correct order of vmux operands: the vcmp.eq sets predicate ; bits for 0s in the mask. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll b/llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll index dd39cc9e0fd5..ed9d72ed4528 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/widen-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; v32i8 -> v32i16 ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll b/llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll index 2a14ce468760..e4765bbcb4ef 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; Make sure that this doesn't crash. ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll b/llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll index 7f9a6078a26f..47d0ed4067fb 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/widen-trunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s ; If the "rx = #N, vsetq(rx)" get reordered with the rest, update the test. diff --git a/llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll b/llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll index 9a10e60d4457..fae506f5f893 100644 --- a/llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll +++ b/llvm/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll @@ -1,7 +1,7 @@ ; Check that a callee-saved register will be saved correctly if ; the predicate-to-GPR spilling code uses it. ; -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; ; We expect to spill p0 into a general-purpose register and keep it there, ; without adding an extra spill of that register. diff --git a/llvm/test/CodeGen/Hexagon/avoid-predspill.ll b/llvm/test/CodeGen/Hexagon/avoid-predspill.ll index 159c149c4422..97878c446ea9 100644 --- a/llvm/test/CodeGen/Hexagon/avoid-predspill.ll +++ b/llvm/test/CodeGen/Hexagon/avoid-predspill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; ; This checks that predicate registers are moved to GPRs instead of spilling ; where possible. diff --git a/llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll b/llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll index 3a63ea7f51b8..0b09ad6d4bf6 100644 --- a/llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll +++ b/llvm/test/CodeGen/Hexagon/avoidVectorLowering.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK-NOT: vmem target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/bank-conflict-load.mir b/llvm/test/CodeGen/Hexagon/bank-conflict-load.mir index 5d84e66f8349..01cc0ee8696f 100644 --- a/llvm/test/CodeGen/Hexagon/bank-conflict-load.mir +++ b/llvm/test/CodeGen/Hexagon/bank-conflict-load.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass post-RA-sched %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass post-RA-sched %s -o - | FileCheck %s # The two loads from %a ($r0) can cause a bank conflict. Check that they # are not scheduled next to each other. diff --git a/llvm/test/CodeGen/Hexagon/bank-conflict.mir b/llvm/test/CodeGen/Hexagon/bank-conflict.mir index f59fc5ce8f7d..12d7838b8372 100644 --- a/llvm/test/CodeGen/Hexagon/bank-conflict.mir +++ b/llvm/test/CodeGen/Hexagon/bank-conflict.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass post-RA-sched %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass post-RA-sched %s -o - | FileCheck %s # Test that the Post RA scheduler does not schedule back-to-back loads # when there is another instruction to schedule. The scheduler avoids diff --git a/llvm/test/CodeGen/Hexagon/barrier-flag.ll b/llvm/test/CodeGen/Hexagon/barrier-flag.ll index d4e48c8bb614..d10e31405fba 100644 --- a/llvm/test/CodeGen/Hexagon/barrier-flag.ll +++ b/llvm/test/CodeGen/Hexagon/barrier-flag.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; Check for successful compilation. It originally caused an abort due to ; the "isBarrier" flag set on instructions that were not meant to have it. diff --git a/llvm/test/CodeGen/Hexagon/base-offset-addr.ll b/llvm/test/CodeGen/Hexagon/base-offset-addr.ll index 3104448a675f..fbdb0d4f3ca5 100644 --- a/llvm/test/CodeGen/Hexagon/base-offset-addr.ll +++ b/llvm/test/CodeGen/Hexagon/base-offset-addr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-aa-sched-mi < %s +; RUN: llc -mtriple=hexagon -enable-aa-sched-mi < %s ; REQUIRES: asserts ; Make sure the base is a register and not an address. diff --git a/llvm/test/CodeGen/Hexagon/base-offset-post.ll b/llvm/test/CodeGen/Hexagon/base-offset-post.ll index 388d66728bcd..28568ed7d9ec 100644 --- a/llvm/test/CodeGen/Hexagon/base-offset-post.ll +++ b/llvm/test/CodeGen/Hexagon/base-offset-post.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the accessSize is set on a post-increment store. If not, an assert diff --git a/llvm/test/CodeGen/Hexagon/base-offset-stv4.ll b/llvm/test/CodeGen/Hexagon/base-offset-stv4.ll index 9b6305e7fe94..0a320e8e3ca9 100644 --- a/llvm/test/CodeGen/Hexagon/base-offset-stv4.ll +++ b/llvm/test/CodeGen/Hexagon/base-offset-stv4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/bit-addr-align.mir b/llvm/test/CodeGen/Hexagon/bit-addr-align.mir index 911f23e8084c..5f8c945b4d6a 100644 --- a/llvm/test/CodeGen/Hexagon/bit-addr-align.mir +++ b/llvm/test/CodeGen/Hexagon/bit-addr-align.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-bit-simplify %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-bit-simplify %s -o - | FileCheck %s # Hexagon bit tracker incorrectly calculated address alignment and removed # a necessary A2_andir instruction. Make sure it remains. diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll index 6d2375c2be46..dd90c0494388 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; This testcase used to crash due to putting the bitsplit instruction in a diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll index d4c7b741b2b6..9988cdae6174 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-regclass.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; Check for successful compilation. ; CHECK: r{{[0-9]+}} = insert(r{{[0-9]+}},#1,#31) diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll index 6fbcffd37281..a1b33fdca415 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; This used to crash. Check for some sane output. diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll index 0123d00ebc71..a2014800a0c3 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: bitsplit(r{{[0-9]+}},#5) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bit-cmp0.mir b/llvm/test/CodeGen/Hexagon/bit-cmp0.mir index e4a2514f0030..33b41281e906 100644 --- a/llvm/test/CodeGen/Hexagon/bit-cmp0.mir +++ b/llvm/test/CodeGen/Hexagon/bit-cmp0.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-bit-simplify -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-bit-simplify -o - %s | FileCheck %s --- | @g0 = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/bit-eval.ll b/llvm/test/CodeGen/Hexagon/bit-eval.ll index 361ebf40db86..368fe74a6ce1 100644 --- a/llvm/test/CodeGen/Hexagon/bit-eval.ll +++ b/llvm/test/CodeGen/Hexagon/bit-eval.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll index 713e3988457e..df07d8e5bdf4 100644 --- a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll +++ b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll index fb5d3a4db118..3396779737a4 100644 --- a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll +++ b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; CHECK: extractu(r1,#31,#0) ; In the IR this was an extract of 31 bits starting at position 32 in r1:0. diff --git a/llvm/test/CodeGen/Hexagon/bit-extract.ll b/llvm/test/CodeGen/Hexagon/bit-extract.ll index 33fa50c14f39..172c0ffd198c 100644 --- a/llvm/test/CodeGen/Hexagon/bit-extract.ll +++ b/llvm/test/CodeGen/Hexagon/bit-extract.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bit-extractu-half.ll b/llvm/test/CodeGen/Hexagon/bit-extractu-half.ll index fec4a02d9269..46d2164d3264 100644 --- a/llvm/test/CodeGen/Hexagon/bit-extractu-half.ll +++ b/llvm/test/CodeGen/Hexagon/bit-extractu-half.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Pick lsr (in bit-simplification) for extracting high halfword. ; CHECK: lsr{{.*}}#16 diff --git a/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll b/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll index 5d36cae76987..5fe9c9142a1a 100644 --- a/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll +++ b/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hsdr -enable-subreg-liveness < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hsdr -enable-subreg-liveness < %s | FileCheck %s ; Check that we don't generate any bitwise operations. ; CHECK-NOT: = or( diff --git a/llvm/test/CodeGen/Hexagon/bit-has.ll b/llvm/test/CodeGen/Hexagon/bit-has.ll index 41f234b326c9..4485af409d1e 100644 --- a/llvm/test/CodeGen/Hexagon/bit-has.ll +++ b/llvm/test/CodeGen/Hexagon/bit-has.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; REQUIRES: asserts ; This used to crash. Check for some sane output. diff --git a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll index 351091095651..c7ac603614e5 100644 --- a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll +++ b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" diff --git a/llvm/test/CodeGen/Hexagon/bit-loop.ll b/llvm/test/CodeGen/Hexagon/bit-loop.ll index 453790e427b5..595d1c8cb2eb 100644 --- a/llvm/test/CodeGen/Hexagon/bit-loop.ll +++ b/llvm/test/CodeGen/Hexagon/bit-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-DAG: memh(r{{[0-9]+}}+#0) = r{{[0-9]+}} ; CHECK-DAG: memh(r{{[0-9]+}}+#2) = r{{[0-9]+}}.h ; CHECK-DAG: memh(r{{[0-9]+}}+#4) = r{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/bit-phi.ll b/llvm/test/CodeGen/Hexagon/bit-phi.ll index 39e13a2e2d94..5e9bf923e614 100644 --- a/llvm/test/CodeGen/Hexagon/bit-phi.ll +++ b/llvm/test/CodeGen/Hexagon/bit-phi.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s -; RUN: llc -march=hexagon -disable-hcp < %s +; RUN: llc -mtriple=hexagon < %s +; RUN: llc -mtriple=hexagon -disable-hcp < %s ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/bit-rie.ll b/llvm/test/CodeGen/Hexagon/bit-rie.ll index 9b670b2e6207..6bb8e912d204 100644 --- a/llvm/test/CodeGen/Hexagon/bit-rie.ll +++ b/llvm/test/CodeGen/Hexagon/bit-rie.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: LBB0{{.*}}if.end ; CHECK: r[[REG:[0-9]+]] = zxth ; CHECK: lsr(r[[REG]], diff --git a/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll b/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll index 796d36ad7f41..5fc37596e1fe 100644 --- a/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll +++ b/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Either and or zxtb. ; CHECK: r0 = and(r1,#255) diff --git a/llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir b/llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir index ef84043cf502..3aa3bcda4ec4 100644 --- a/llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir +++ b/llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass=hexagon-bit-simplify -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass=hexagon-bit-simplify -o - %s | FileCheck %s # This test checks if the HexagonBitSimplify pass correctly replaces a # S2_storerh_io with a S2_storerf_io that stores the upper halfword diff --git a/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll b/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll index 42eed97786cd..5f3c2e2340aa 100644 --- a/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll +++ b/llvm/test/CodeGen/Hexagon/bit-validate-reg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexbit-extract=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexbit-extract=0 < %s | FileCheck %s ; Make sure we don't generate zxtb to transfer a predicate register into ; a general purpose register. diff --git a/llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll b/llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll index 62ffb1ed1b53..cdbbecc9bb80 100644 --- a/llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll +++ b/llvm/test/CodeGen/Hexagon/bit-visit-flowq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Check that we don't crash. diff --git a/llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll b/llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll index 323bac933fb6..5fbc35038b82 100644 --- a/llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll +++ b/llvm/test/CodeGen/Hexagon/bitcast-i128-to-v128i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr=+hvx-length128b < %s +; RUN: llc -mtriple=hexagon -mattr=+hvx-length128b < %s ; Function Attrs: nounwind readnone declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) diff --git a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll index dee7ae8c3896..5d44b3ba123c 100644 --- a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll +++ b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that ; is compiles without errors. diff --git a/llvm/test/CodeGen/Hexagon/bitmanip.ll b/llvm/test/CodeGen/Hexagon/bitmanip.ll index 2c21af62d6f3..a63a666626cb 100644 --- a/llvm/test/CodeGen/Hexagon/bitmanip.ll +++ b/llvm/test/CodeGen/Hexagon/bitmanip.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define i16 @popcount_i16(i16 %a0) #0 { ; CHECK-LABEL: popcount_i16: diff --git a/llvm/test/CodeGen/Hexagon/bkfir.ll b/llvm/test/CodeGen/Hexagon/bkfir.ll index fc8bcb5424b2..8ef82ce81c27 100644 --- a/llvm/test/CodeGen/Hexagon/bkfir.ll +++ b/llvm/test/CodeGen/Hexagon/bkfir.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/block-addr.ll b/llvm/test/CodeGen/Hexagon/block-addr.ll index 5d028bba9464..cc23d44dd7f5 100644 --- a/llvm/test/CodeGen/Hexagon/block-addr.ll +++ b/llvm/test/CodeGen/Hexagon/block-addr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; CHECK-DAG: r[[REG:[0-9]+]] = memw(r{{[0-9]+<<#[0-9]+}}+##.LJTI{{.*}}) ; CHECK-DAG: jumpr r[[REG]] diff --git a/llvm/test/CodeGen/Hexagon/block-address.ll b/llvm/test/CodeGen/Hexagon/block-address.ll index 62efaa3406c9..94e972a2b1c4 100644 --- a/llvm/test/CodeGen/Hexagon/block-address.ll +++ b/llvm/test/CodeGen/Hexagon/block-address.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s +; RUN: llc -mtriple=hexagon < %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s ; REQUIRES: asserts @g0 = external global ptr diff --git a/llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll b/llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll index d38a74f7e67c..0490696269a1 100644 --- a/llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll +++ b/llvm/test/CodeGen/Hexagon/block-ranges-nodef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll b/llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll index aeff33c9c824..1b517d85cd46 100644 --- a/llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll +++ b/llvm/test/CodeGen/Hexagon/blockaddr-fpic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -relocation-model=pic -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -relocation-model=pic -O2 < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = add(pc,##.Ltmp0@PCREL) ; CHECK-NOT: r{{[0-9]+}} = ##.Ltmp0 diff --git a/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir b/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir index ab4329fdd6db..2b10e4ba1b9b 100644 --- a/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir +++ b/llvm/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass branch-folder -run-pass if-converter -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass branch-folder -run-pass if-converter -verify-machineinstrs %s -o - | FileCheck %s # The hoisting of common instructions from successors could cause registers # to no longer be live-in in the successor blocks. The liveness was updated diff --git a/llvm/test/CodeGen/Hexagon/branch-non-mbb.ll b/llvm/test/CodeGen/Hexagon/branch-non-mbb.ll index a0782695a76a..1fba3ab31a54 100644 --- a/llvm/test/CodeGen/Hexagon/branch-non-mbb.ll +++ b/llvm/test/CodeGen/Hexagon/branch-non-mbb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; ; The tail calls to foo and bar are branches with functions as operands, diff --git a/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir b/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir index ef80515fc87f..97f57fcc97e9 100644 --- a/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir +++ b/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass branch-folder %s -o - -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass branch-folder %s -o - -verify-machineinstrs | FileCheck %s # Branch folding will perform tail merging of bb.1 and bb.2, and bb.2 will # become the common tail. The use of R0 in bb.2 is <undef> while the diff --git a/llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll b/llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll index 27959b1ec9b5..69046267d86c 100644 --- a/llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll +++ b/llvm/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; ; Check that the testcase compiles successfully. Expect that if-conversion ; took place. diff --git a/llvm/test/CodeGen/Hexagon/brcond-setne.ll b/llvm/test/CodeGen/Hexagon/brcond-setne.ll index 61393b706442..54900642e4e5 100644 --- a/llvm/test/CodeGen/Hexagon/brcond-setne.ll +++ b/llvm/test/CodeGen/Hexagon/brcond-setne.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; CHECK: cmpb.eq target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/brev_ld.ll b/llvm/test/CodeGen/Hexagon/brev_ld.ll index 8cc1d0bc858e..8ac2d8adbe27 100644 --- a/llvm/test/CodeGen/Hexagon/brev_ld.ll +++ b/llvm/test/CodeGen/Hexagon/brev_ld.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s -; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s ; Testing bitreverse load intrinsics: ; Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength); ; Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength); diff --git a/llvm/test/CodeGen/Hexagon/brev_st.ll b/llvm/test/CodeGen/Hexagon/brev_st.ll index db5d8314b593..566582f446f2 100644 --- a/llvm/test/CodeGen/Hexagon/brev_st.ll +++ b/llvm/test/CodeGen/Hexagon/brev_st.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s -; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s ; Test these 5 bitreverse store intrinsics: ; Q6_bitrev_store_update_D(inputLR, pDelay, nConvLength); ; Q6_bitrev_store_update_W(inputLR, pDelay, nConvLength); diff --git a/llvm/test/CodeGen/Hexagon/bss-local.ll b/llvm/test/CodeGen/Hexagon/bss-local.ll index 671e8aeb303b..39b36c2457bf 100644 --- a/llvm/test/CodeGen/Hexagon/bss-local.ll +++ b/llvm/test/CodeGen/Hexagon/bss-local.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll b/llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll index 3868dc979e25..b9a3b4b311f5 100644 --- a/llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll +++ b/llvm/test/CodeGen/Hexagon/bug-aa4463-ifconv-vecpred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts define inreg <16 x i32> @f0(i32 %a0, ptr nocapture %a1) #0 { diff --git a/llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll b/llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll index 20070345e6b9..9d49f01dee55 100644 --- a/llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll +++ b/llvm/test/CodeGen/Hexagon/bug-allocframe-size.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Make sure we allocate less than 100 bytes of stack ; CHECK: allocframe(#{{[1-9][0-9]}} diff --git a/llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll b/llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll index d2a006af89f9..804fb2081936 100644 --- a/llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll +++ b/llvm/test/CodeGen/Hexagon/bug-hcp-tied-kill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -verify-machineinstrs < %s | FileCheck %s ; CHECK: .globl diff --git a/llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll b/llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll index e0417e734002..b5a5c3f8a15a 100644 --- a/llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll +++ b/llvm/test/CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll b/llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll index 0efec7222cea..ea5126775704 100644 --- a/llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll +++ b/llvm/test/CodeGen/Hexagon/bug14859-split-const-block-addr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll b/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll index 5b3894a5b6af..2dc69dbb200e 100644 --- a/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll +++ b/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll @@ -1,4 +1,4 @@ -; RUN: opt -march=hexagon -O2 -S < %s +; RUN: opt -O2 -S < %s ; REQUIRES: asserts ; ; -fvectorize-loops infinite compile/memory diff --git a/llvm/test/CodeGen/Hexagon/bug17276.ll b/llvm/test/CodeGen/Hexagon/bug17276.ll index 699736482291..b5cdad850736 100644 --- a/llvm/test/CodeGen/Hexagon/bug17276.ll +++ b/llvm/test/CodeGen/Hexagon/bug17276.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -function-sections < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -function-sections < %s | FileCheck %s ; CHECK: if (!p0) ; CHECK-NOT: if (p0.new) ; CHECK: { diff --git a/llvm/test/CodeGen/Hexagon/bug17386.ll b/llvm/test/CodeGen/Hexagon/bug17386.ll index c36b825a93f7..6bc43983e1a3 100644 --- a/llvm/test/CodeGen/Hexagon/bug17386.ll +++ b/llvm/test/CodeGen/Hexagon/bug17386.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/bug18008.ll b/llvm/test/CodeGen/Hexagon/bug18008.ll index 6be045cdfdf9..cc095f728171 100644 --- a/llvm/test/CodeGen/Hexagon/bug18008.ll +++ b/llvm/test/CodeGen/Hexagon/bug18008.ll @@ -1,4 +1,4 @@ -;RUN: llc -march=hexagon -filetype=obj < %s -o - | llvm-objdump --no-print-imm-hex --mcpu=hexagonv60 --mattr=+hvx -d - | FileCheck %s +;RUN: llc -mtriple=hexagon -filetype=obj < %s -o - | llvm-objdump --no-print-imm-hex --mcpu=hexagonv60 --mattr=+hvx -d - | FileCheck %s ; Should not crash! and map to vxor diff --git a/llvm/test/CodeGen/Hexagon/bug18491-optsize.ll b/llvm/test/CodeGen/Hexagon/bug18491-optsize.ll index ecbf81fa5d06..4f82ef88c5b6 100644 --- a/llvm/test/CodeGen/Hexagon/bug18491-optsize.ll +++ b/llvm/test/CodeGen/Hexagon/bug18491-optsize.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: {{.balign 4|.p2align 2}} ; CHECK: {{.balign 4|.p2align 2}} ; CHECK: {{.balign 4|.p2align 2}} diff --git a/llvm/test/CodeGen/Hexagon/bug19076.ll b/llvm/test/CodeGen/Hexagon/bug19076.ll index 2e9103e493f4..995d2b93700e 100644 --- a/llvm/test/CodeGen/Hexagon/bug19076.ll +++ b/llvm/test/CodeGen/Hexagon/bug19076.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -march=hexagon -stats -o /dev/null < %s +; RUN: llc -mtriple=hexagon -stats -o /dev/null < %s %s.0 = type { ptr, ptr, ptr, i32, i32, i32, i32, ptr, ptr, ptr } %s.1 = type opaque diff --git a/llvm/test/CodeGen/Hexagon/bug19119.ll b/llvm/test/CodeGen/Hexagon/bug19119.ll index ebd17da225d5..048690c1d3ac 100644 --- a/llvm/test/CodeGen/Hexagon/bug19119.ll +++ b/llvm/test/CodeGen/Hexagon/bug19119.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: .sdata.4.g0,"aM" target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll b/llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll index 3aab75725062..03add68c124f 100644 --- a/llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll +++ b/llvm/test/CodeGen/Hexagon/bug19254-ifconv-vec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; we really just want to be sure this compilation does not abort. ; CHECK: vadd diff --git a/llvm/test/CodeGen/Hexagon/bug27085.ll b/llvm/test/CodeGen/Hexagon/bug27085.ll index 7289e969c6a3..3a893ec8db64 100644 --- a/llvm/test/CodeGen/Hexagon/bug27085.ll +++ b/llvm/test/CodeGen/Hexagon/bug27085.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -relocation-model=pic -mattr=+long-calls < %s | FileCheck --check-prefix=CHECK-LONG %s -; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -relocation-model=pic -mattr=+long-calls < %s | FileCheck --check-prefix=CHECK-LONG %s +; RUN: llc -mtriple=hexagon -relocation-model=pic < %s | FileCheck %s ; CHECK-LONG: call ##g0@GDPLT ; CHECK-LONG-NOT: call g0@GDPLT diff --git a/llvm/test/CodeGen/Hexagon/bug31839.ll b/llvm/test/CodeGen/Hexagon/bug31839.ll index 117cccb55021..91052b8a7b16 100644 --- a/llvm/test/CodeGen/Hexagon/bug31839.ll +++ b/llvm/test/CodeGen/Hexagon/bug31839.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll b/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll index ae743e50fddc..bf35f86d9e28 100644 --- a/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll +++ b/llvm/test/CodeGen/Hexagon/bug6757-endloop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that we can handle loops with multiple ENDLOOP instructions. ; This situation can arise due to tail duplication. diff --git a/llvm/test/CodeGen/Hexagon/bug9049.ll b/llvm/test/CodeGen/Hexagon/bug9049.ll index e6c92d9cda61..605bfe63d6b1 100644 --- a/llvm/test/CodeGen/Hexagon/bug9049.ll +++ b/llvm/test/CodeGen/Hexagon/bug9049.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/bug9963.ll b/llvm/test/CodeGen/Hexagon/bug9963.ll index 04ba813f8157..1515ebb730d3 100644 --- a/llvm/test/CodeGen/Hexagon/bug9963.ll +++ b/llvm/test/CodeGen/Hexagon/bug9963.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-NOT: memd ; CHECK: call f1 ; CHECK: r{{[0-9]}}:{{[0-9]}} = combine(#0,#10) diff --git a/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll b/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll index d9f48fd19835..2b9fd396ec87 100644 --- a/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll +++ b/llvm/test/CodeGen/Hexagon/bugAsmHWloop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: { ; CHECK: loop0(.LBB diff --git a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll index 223c161f2d8c..75b45034591a 100644 --- a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll +++ b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we don't crash. ; CHECK: vshuff diff --git a/llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll b/llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll index 73bf0169feda..6353d1c9a9b9 100644 --- a/llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll +++ b/llvm/test/CodeGen/Hexagon/build-vector-v4i8-zext.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate zero-extends, instead of just shifting and oring ; registers (which can contain sign-extended negative values). diff --git a/llvm/test/CodeGen/Hexagon/builtin-expect.ll b/llvm/test/CodeGen/Hexagon/builtin-expect.ll index 4783a2588e08..6302cde14956 100644 --- a/llvm/test/CodeGen/Hexagon/builtin-expect.ll +++ b/llvm/test/CodeGen/Hexagon/builtin-expect.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-block-placement < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-block-placement < %s | FileCheck %s ; Check that the branch to the block b10 is marked as taken (i.e. ":t"). ; CHECK-LABEL: foo diff --git a/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll b/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll index bbab0f0ffe9e..82d582774555 100644 --- a/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll +++ b/llvm/test/CodeGen/Hexagon/builtin-prefetch-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for the immediate offset. It must be a multiple of 8. ; CHECK: dcfetch({{.*}}+#8) ; In 6.2 (which supports v4+ only), we generate indexed dcfetch in all cases diff --git a/llvm/test/CodeGen/Hexagon/builtin-prefetch.ll b/llvm/test/CodeGen/Hexagon/builtin-prefetch.ll index e23e3488e68b..7fcbdcebcadb 100644 --- a/llvm/test/CodeGen/Hexagon/builtin-prefetch.ll +++ b/llvm/test/CodeGen/Hexagon/builtin-prefetch.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: dcfetch ; CHECK: dcfetch{{.*}}#8 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/call-long1.ll b/llvm/test/CodeGen/Hexagon/call-long1.ll index 4b2589575327..86028719a8c6 100644 --- a/llvm/test/CodeGen/Hexagon/call-long1.ll +++ b/llvm/test/CodeGen/Hexagon/call-long1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -spill-func-threshold-Os=0 -spill-func-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -spill-func-threshold-Os=0 -spill-func-threshold=0 < %s | FileCheck %s ; Check that the long-calls feature handles save and restore. ; This is a test commit. diff --git a/llvm/test/CodeGen/Hexagon/call-ret-i1.ll b/llvm/test/CodeGen/Hexagon/call-ret-i1.ll index 5cf3dfbfef2b..9e74a38371ab 100644 --- a/llvm/test/CodeGen/Hexagon/call-ret-i1.ll +++ b/llvm/test/CodeGen/Hexagon/call-ret-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the compiler does not assert because the DAG is not correct. diff --git a/llvm/test/CodeGen/Hexagon/call-v4.ll b/llvm/test/CodeGen/Hexagon/call-v4.ll index 67548c81fd9b..551689178311 100644 --- a/llvm/test/CodeGen/Hexagon/call-v4.ll +++ b/llvm/test/CodeGen/Hexagon/call-v4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -print-after=finalize-isel -o /dev/null 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -print-after=finalize-isel -o /dev/null 2>&1 < %s | FileCheck %s ; REQUIRES: asserts ; CHECK: J2_call @f1 diff --git a/llvm/test/CodeGen/Hexagon/callR_noreturn.ll b/llvm/test/CodeGen/Hexagon/callR_noreturn.ll index ad198ef853b2..e29cf43771d4 100644 --- a/llvm/test/CodeGen/Hexagon/callR_noreturn.ll +++ b/llvm/test/CodeGen/Hexagon/callR_noreturn.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: callr {{r[0-9]+}} %s.0 = type { [1 x %s.1], [4 x ptr] } diff --git a/llvm/test/CodeGen/Hexagon/calling-conv-2.ll b/llvm/test/CodeGen/Hexagon/calling-conv-2.ll index 74913417d2f7..5a0180ef843f 100644 --- a/llvm/test/CodeGen/Hexagon/calling-conv-2.ll +++ b/llvm/test/CodeGen/Hexagon/calling-conv-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s %struct.test_struct = type { i32, i8, i64 } diff --git a/llvm/test/CodeGen/Hexagon/calling-conv.ll b/llvm/test/CodeGen/Hexagon/calling-conv.ll index 68cce1a8ed5c..1447c7fa1c74 100644 --- a/llvm/test/CodeGen/Hexagon/calling-conv.ll +++ b/llvm/test/CodeGen/Hexagon/calling-conv.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=hexagon -mno-pairing -mno-compound <%s | FileCheck %s --check-prefix=CHECK-ONE -; RUN: llc -march=hexagon -mno-pairing -mno-compound <%s | FileCheck %s --check-prefix=CHECK-TWO -; RUN: llc -march=hexagon -mno-pairing -mno-compound <%s | FileCheck %s --check-prefix=CHECK-THREE +; RUN: llc -mtriple=hexagon -mno-pairing -mno-compound <%s | FileCheck %s --check-prefix=CHECK-ONE +; RUN: llc -mtriple=hexagon -mno-pairing -mno-compound <%s | FileCheck %s --check-prefix=CHECK-TWO +; RUN: llc -mtriple=hexagon -mno-pairing -mno-compound <%s | FileCheck %s --check-prefix=CHECK-THREE %s.0 = type { i32, i8, i64 } %s.1 = type { i8, i64 } diff --git a/llvm/test/CodeGen/Hexagon/callr-dep-edge.ll b/llvm/test/CodeGen/Hexagon/callr-dep-edge.ll index 7049121336c5..5e2af3c6533e 100644 --- a/llvm/test/CodeGen/Hexagon/callr-dep-edge.ll +++ b/llvm/test/CodeGen/Hexagon/callr-dep-edge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that the callr and the load into r0 are not packetized together. target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/cext-check.ll b/llvm/test/CodeGen/Hexagon/cext-check.ll index 0369866b054c..7124b3758173 100644 --- a/llvm/test/CodeGen/Hexagon/cext-check.ll +++ b/llvm/test/CodeGen/Hexagon/cext-check.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-eif=0 -ifcvt-limit=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-eif=0 -ifcvt-limit=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; Check that we constant extended instructions only when necessary. define i32 @cext_test1(ptr %a) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/cext-ice.ll b/llvm/test/CodeGen/Hexagon/cext-ice.ll index a56157b15654..c7cf62d2da30 100644 --- a/llvm/test/CodeGen/Hexagon/cext-ice.ll +++ b/llvm/test/CodeGen/Hexagon/cext-ice.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-basic.mir b/llvm/test/CodeGen/Hexagon/cext-opt-basic.mir index b47f584096ee..bf0f702225d0 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-basic.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-basic.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt -hexagon-cext-threshold=3 %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt -hexagon-cext-threshold=3 %s -o - | FileCheck %s --- | define void @test0() { ret void } diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir b/llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir index 9f140132dcd6..859ff8b68257 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-block-addr.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s # Check that the HexagonConstantExtenders pass does not assert when block # addresses from different functions are used diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir b/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir index 5586748a7870..e0fc94b841c4 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s # Skip fixed stack indices in hexagon-cext. The reason is that they cannot # be stored as indices (stackSlot2Index) together with registers and diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-numops.mir b/llvm/test/CodeGen/Hexagon/cext-opt-numops.mir index e4e172d79167..95d48bb595f9 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-numops.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-numops.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s # An incorrect assertion was triggered on this code, while attempting to # perform a valid transformation. diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir b/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir index 0d5febdc478d..54a58afe94bb 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-range-assert.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s # REQUIRES: asserts # # This testcase used to trigger an incorrect assertion. Make sure it no diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir b/llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir index 9a012e830af8..917bd242e517 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-range-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s # Check that this testcase does not crash. # CHECK: L4_and_memopw_io diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir b/llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir index e3a607872858..abffedf45814 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-shifted-range.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt %s -o - | FileCheck %s # Check that "misaligned" extended offsets are handled correctly, that is # that the non-extended offsets are still aligned. diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir b/llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir index 150cc073983e..2d5e77357501 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-cext-opt -hexagon-cext-threshold=1 -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-cext-opt -hexagon-cext-threshold=1 -o - %s | FileCheck %s # Make sure that the stores to the stack slot are not converted into rr forms. # CHECK: %[[REG:[0-9]+]]:intregs = PS_fi %stack.0, 267 diff --git a/llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir b/llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir index 0673ba7c218f..4c5569ce2367 100644 --- a/llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir +++ b/llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass=hexagon-cext-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass=hexagon-cext-opt %s -o - | FileCheck %s # Check that this test doesn't crash. # CHECK: %0:intregs = A2_tfrsi @0 diff --git a/llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll b/llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll index b0aa3c16f862..3f62b0139725 100644 --- a/llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll +++ b/llvm/test/CodeGen/Hexagon/cext-valid-packet1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that the packetizer generates valid packets with constant ; extended instructions. diff --git a/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll b/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll index 2d51414fea22..c75d99055c3b 100644 --- a/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll +++ b/llvm/test/CodeGen/Hexagon/cext-valid-packet2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv55 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv55 < %s | FileCheck %s ; Check that the packetizer generates valid packets with constant ; extended add and base+offset store instructions. @@ -6,7 +6,7 @@ ; CHECK-NEXT: memw(r{{[0-9]+}}+##12000) = r{{[0-9]+}}.new ; CHECK-NEXT: } -; RUN: llc -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s -check-prefix=CHECK-NEW +; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 < %s | FileCheck %s -check-prefix=CHECK-NEW ; Check that the packetizer generates .new store for v60 which has BSB scheduling model. ; CHECK-NEW: [[REG0:r([0-9]+)]] = add(r{{[0-9]+}},##200000) diff --git a/llvm/test/CodeGen/Hexagon/cext.ll b/llvm/test/CodeGen/Hexagon/cext.ll index 7cd654fa221d..5f0ea0166473 100644 --- a/llvm/test/CodeGen/Hexagon/cext.ll +++ b/llvm/test/CodeGen/Hexagon/cext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: memub(r{{[0-9]+}}<<#1+##a) @a = external global [5 x [2 x i8]] diff --git a/llvm/test/CodeGen/Hexagon/cexti16.ll b/llvm/test/CodeGen/Hexagon/cexti16.ll index e93ffa3f3ba9..153002320cce 100644 --- a/llvm/test/CodeGen/Hexagon/cexti16.ll +++ b/llvm/test/CodeGen/Hexagon/cexti16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: memuh(r{{[0-9]+}}<<#2+##a) @a = external global [5 x [2 x i16]] diff --git a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll index 53c610d659ab..050af3e75d25 100644 --- a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll +++ b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; REQUIRES: asserts ; Check for some sane output. This test used to crash. diff --git a/llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll b/llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll index 5b5518cd7f31..700b608fca69 100644 --- a/llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll +++ b/llvm/test/CodeGen/Hexagon/cfi-late-and-regpressure-init.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-misched=true < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-misched=true < %s | FileCheck %s ; This test checks the delayed emission of CFI instructions ; This test also checks the proper initialization of RegisterPressureTracker. ; The RegisterPressureTracker must skip debug instructions upon entry of a BB diff --git a/llvm/test/CodeGen/Hexagon/cfi-late.ll b/llvm/test/CodeGen/Hexagon/cfi-late.ll index 67485421fe8a..a4ab1e7b44d4 100644 --- a/llvm/test/CodeGen/Hexagon/cfi-late.ll +++ b/llvm/test/CodeGen/Hexagon/cfi-late.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-misched=false < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-misched=false < %s | FileCheck %s ; This testcase causes the scheduler to crash for some reason. Disable ; it for now. diff --git a/llvm/test/CodeGen/Hexagon/cfi-offset.ll b/llvm/test/CodeGen/Hexagon/cfi-offset.ll index ce750da9a6ca..0b58c2f11eed 100644 --- a/llvm/test/CodeGen/Hexagon/cfi-offset.ll +++ b/llvm/test/CodeGen/Hexagon/cfi-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that all the offsets in the .cfi_offset instructions are negative. ; They are all based on R30+8 which points to the pair FP/LR stored by an ; allocframe. Since the stack grows towards negative addresses, anything diff --git a/llvm/test/CodeGen/Hexagon/cfi_offset.ll b/llvm/test/CodeGen/Hexagon/cfi_offset.ll index 5795d7f8ec60..a506b549f7a3 100644 --- a/llvm/test/CodeGen/Hexagon/cfi_offset.ll +++ b/llvm/test/CodeGen/Hexagon/cfi_offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; CHECK: .cfi_def_cfa r30 ; CHECK: .cfi_offset r31 ; CHECK: .cfi_offset r30 diff --git a/llvm/test/CodeGen/Hexagon/cfi_offset2.ll b/llvm/test/CodeGen/Hexagon/cfi_offset2.ll index b068110cc8a0..94fd26bcf51c 100644 --- a/llvm/test/CodeGen/Hexagon/cfi_offset2.ll +++ b/llvm/test/CodeGen/Hexagon/cfi_offset2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: .cfi_offset r31, -4 ; CHECK: .cfi_offset r30, -8 ; CHECK: .cfi_offset r17, -12 diff --git a/llvm/test/CodeGen/Hexagon/check-dot-new.ll b/llvm/test/CodeGen/Hexagon/check-dot-new.ll index d9240fe9b31d..2a4cd459099a 100644 --- a/llvm/test/CodeGen/Hexagon/check-dot-new.ll +++ b/llvm/test/CodeGen/Hexagon/check-dot-new.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 -disable-hexagon-misched < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 -disable-hexagon-misched < %s | FileCheck %s ; CHECK-LABEL: f0 ; CHECK-DAG: [[REG:r[0-9]+]] = add ; CHECK-DAG: memw(##g0) = [[REG]].new diff --git a/llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll b/llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll index 0cd24b883a1f..a07f6197b953 100644 --- a/llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll +++ b/llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv67t < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv67t < %s ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" diff --git a/llvm/test/CodeGen/Hexagon/checktabs.ll b/llvm/test/CodeGen/Hexagon/checktabs.ll index 740433bf824a..d9d157771086 100644 --- a/llvm/test/CodeGen/Hexagon/checktabs.ll +++ b/llvm/test/CodeGen/Hexagon/checktabs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck --strict-whitespace %s +; RUN: llc -mtriple=hexagon < %s | FileCheck --strict-whitespace %s ; Make sure we are emitting tabs as formatting. ; CHECK: { ; CHECK-NEXT: {{jump|r}} diff --git a/llvm/test/CodeGen/Hexagon/circ-load-isel.ll b/llvm/test/CodeGen/Hexagon/circ-load-isel.ll index 61d0beea14ae..a3200412b781 100644 --- a/llvm/test/CodeGen/Hexagon/circ-load-isel.ll +++ b/llvm/test/CodeGen/Hexagon/circ-load-isel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: = memw{{.*}}circ target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/circ_ld.ll b/llvm/test/CodeGen/Hexagon/circ_ld.ll index 0984e20347f9..a44de2d8f6f3 100644 --- a/llvm/test/CodeGen/Hexagon/circ_ld.ll +++ b/llvm/test/CodeGen/Hexagon/circ_ld.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Testing for these 6 variants of circular load: ; Q6_circ_load_update_B(inputLR, pDelay, -1, nConvLength, 4); ; Q6_circ_load_update_D(inputLR, pDelay, -1, nConvLength, 4); diff --git a/llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll b/llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll index 7b60e4c9d9ad..89120e7ca5cd 100644 --- a/llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll +++ b/llvm/test/CodeGen/Hexagon/circ_ldd_bug.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/circ_ldw.ll b/llvm/test/CodeGen/Hexagon/circ_ldw.ll index 1521bc1b8b66..efc5cff55680 100644 --- a/llvm/test/CodeGen/Hexagon/circ_ldw.ll +++ b/llvm/test/CodeGen/Hexagon/circ_ldw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; CHECK: r{{[0-9]*}} = memw(r{{[0-9]+}}++#-4:circ(m0)) diff --git a/llvm/test/CodeGen/Hexagon/circ_new.ll b/llvm/test/CodeGen/Hexagon/circ_new.ll index d278e06468f7..c90e2fc509a5 100644 --- a/llvm/test/CodeGen/Hexagon/circ_new.ll +++ b/llvm/test/CodeGen/Hexagon/circ_new.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test1 ; CHECK: m[[REG1:([0-1])]] = r0 diff --git a/llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll b/llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll index 26c1d445f941..4cb9376eb8c6 100644 --- a/llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll +++ b/llvm/test/CodeGen/Hexagon/circ_pcr_assert.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; The test case validates the fact that if the modifier register value "-268430336" ; is passed as target constant, then the compiler must not assert. diff --git a/llvm/test/CodeGen/Hexagon/circ_st.ll b/llvm/test/CodeGen/Hexagon/circ_st.ll index 22007331adfe..590d4eb7671d 100644 --- a/llvm/test/CodeGen/Hexagon/circ_st.ll +++ b/llvm/test/CodeGen/Hexagon/circ_st.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s ; Testing for these 5 variants of circular store: ; Q6_circ_store_update_B(inputLR, pDelay, -1, nConvLength, 4); ; Q6_circ_store_update_D(inputLR, pDelay, -1, nConvLength, 4); diff --git a/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll b/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll index a38b2529be10..99e90165bd07 100644 --- a/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll +++ b/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-bit=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-bit=0 < %s | FileCheck %s ; Optimized bitwise operations. define i32 @my_clrbit(i32 %x) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/cmp-extend.ll b/llvm/test/CodeGen/Hexagon/cmp-extend.ll index 3a728ed51658..a72bb218dec2 100644 --- a/llvm/test/CodeGen/Hexagon/cmp-extend.ll +++ b/llvm/test/CodeGen/Hexagon/cmp-extend.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s %struct.RESULTS_S.A = type { i16, i16, i16, [4 x ptr], i32, i32, i32, ptr, %struct.MAT_PARAMS_S.D, i16, i16, i16, i16, i16, %struct.CORE_PORTABLE_S.E } %struct.list_head_s.B = type { ptr, ptr } diff --git a/llvm/test/CodeGen/Hexagon/cmp-promote.ll b/llvm/test/CodeGen/Hexagon/cmp-promote.ll index e3f8992507b2..8b52c0058b5f 100644 --- a/llvm/test/CodeGen/Hexagon/cmp-promote.ll +++ b/llvm/test/CodeGen/Hexagon/cmp-promote.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Bug 6714. Use sign-extend to promote the arguments for compare ; equal/not-equal for 8- and 16-bit types with negative constants. diff --git a/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll b/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll index a3658fb0c830..c06ce93ff227 100644 --- a/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll +++ b/llvm/test/CodeGen/Hexagon/cmp-to-genreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate compare to general register. define i32 @compare1(i32 %a) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll b/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll index 9e6e465027f4..f38e65ad6776 100644 --- a/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll +++ b/llvm/test/CodeGen/Hexagon/cmp-to-predreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate compare to predicate register. define i32 @compare1(i32 %a, i32 %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/cmp_pred.ll b/llvm/test/CodeGen/Hexagon/cmp_pred.ll index 4835eaf791f0..978e7fbed0dc 100644 --- a/llvm/test/CodeGen/Hexagon/cmp_pred.ll +++ b/llvm/test/CodeGen/Hexagon/cmp_pred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s ; Generate various cmpb instruction followed by if (p0) .. if (!p0)... target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/cmp_pred2.ll b/llvm/test/CodeGen/Hexagon/cmp_pred2.ll index 93afbc9c2e54..dcb6bf1394db 100644 --- a/llvm/test/CodeGen/Hexagon/cmp_pred2.ll +++ b/llvm/test/CodeGen/Hexagon/cmp_pred2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that the assembler mapped compare instructions are correctly generated. @c = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll b/llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll index 4835eaf791f0..978e7fbed0dc 100644 --- a/llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll +++ b/llvm/test/CodeGen/Hexagon/cmp_pred_reg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s ; Generate various cmpb instruction followed by if (p0) .. if (!p0)... target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll b/llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll index 49eab94a0768..3d382a220d3c 100644 --- a/llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll +++ b/llvm/test/CodeGen/Hexagon/cmpb-dec-imm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s ; REQUIRES: asserts ; Check that we generate 'cmpb.gtu' instruction for a byte comparision diff --git a/llvm/test/CodeGen/Hexagon/cmpb-eq.ll b/llvm/test/CodeGen/Hexagon/cmpb-eq.ll index faf2057a9f55..d88e11d12ec4 100644 --- a/llvm/test/CodeGen/Hexagon/cmpb-eq.ll +++ b/llvm/test/CodeGen/Hexagon/cmpb-eq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: cmpb.eq(r{{[0-9]+}},#-1) target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/cmpb_gtu.ll b/llvm/test/CodeGen/Hexagon/cmpb_gtu.ll index 4dcc7162022e..c867b72cfa63 100644 --- a/llvm/test/CodeGen/Hexagon/cmpb_gtu.ll +++ b/llvm/test/CodeGen/Hexagon/cmpb_gtu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: cmpb.gtu target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/cmpb_pred.ll b/llvm/test/CodeGen/Hexagon/cmpb_pred.ll index 39defe335c64..0566c39d70fc 100644 --- a/llvm/test/CodeGen/Hexagon/cmpb_pred.ll +++ b/llvm/test/CodeGen/Hexagon/cmpb_pred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s ; Generate various cmpb instruction followed by if (p0) .. if (!p0)... target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/cmpbeq.ll b/llvm/test/CodeGen/Hexagon/cmpbeq.ll index 7cf51b3d0881..5536da73b3e1 100644 --- a/llvm/test/CodeGen/Hexagon/cmpbeq.ll +++ b/llvm/test/CodeGen/Hexagon/cmpbeq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate 'cmpb.eq' instruction for a byte comparision. @g0 = common global i8 0, align 1 diff --git a/llvm/test/CodeGen/Hexagon/cmph-gtu.ll b/llvm/test/CodeGen/Hexagon/cmph-gtu.ll index 419eee963f3f..23a330783396 100644 --- a/llvm/test/CodeGen/Hexagon/cmph-gtu.ll +++ b/llvm/test/CodeGen/Hexagon/cmph-gtu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate 'cmph.gtu' instruction. ; CHECK-LABEL: @cmphgtu diff --git a/llvm/test/CodeGen/Hexagon/cmpy-round.ll b/llvm/test/CodeGen/Hexagon/cmpy-round.ll index 5999cf19af71..b3c1b1d8847d 100644 --- a/llvm/test/CodeGen/Hexagon/cmpy-round.ll +++ b/llvm/test/CodeGen/Hexagon/cmpy-round.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; r2 = round(r1:0):sat ; r3 = cmpyiwh(r1:0, r2):<<1:rnd:sat ; r0 = cmpyiwh(r1:0, r2*):<<1:rnd:sat diff --git a/llvm/test/CodeGen/Hexagon/coalesce_tfri.ll b/llvm/test/CodeGen/Hexagon/coalesce_tfri.ll index f83668f9c4a3..89782e37edea 100644 --- a/llvm/test/CodeGen/Hexagon/coalesce_tfri.ll +++ b/llvm/test/CodeGen/Hexagon/coalesce_tfri.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll b/llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll index ae9eb48c9a78..d442938333d2 100644 --- a/llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll +++ b/llvm/test/CodeGen/Hexagon/coalescing-hvx-across-calls.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/combine-imm-ext.ll b/llvm/test/CodeGen/Hexagon/combine-imm-ext.ll index 1ee6d55287c5..a17233f23479 100644 --- a/llvm/test/CodeGen/Hexagon/combine-imm-ext.ll +++ b/llvm/test/CodeGen/Hexagon/combine-imm-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll b/llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll index 1fe89dc17510..a40989863fde 100644 --- a/llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll +++ b/llvm/test/CodeGen/Hexagon/combine-imm-ext2.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/combine.ll b/llvm/test/CodeGen/Hexagon/combine.ll index 1069771d08a5..c17a0fb40671 100644 --- a/llvm/test/CodeGen/Hexagon/combine.ll +++ b/llvm/test/CodeGen/Hexagon/combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s ; CHECK: combine(r{{[0-9]+}},r{{[0-9]+}}) @j = external global i32 diff --git a/llvm/test/CodeGen/Hexagon/combine_ir.ll b/llvm/test/CodeGen/Hexagon/combine_ir.ll index 73d1eaef3369..2f5f490b46c8 100644 --- a/llvm/test/CodeGen/Hexagon/combine_ir.ll +++ b/llvm/test/CodeGen/Hexagon/combine_ir.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hsdr < %s | FileCheck %s declare void @bar(i64) diff --git a/llvm/test/CodeGen/Hexagon/combine_lh.ll b/llvm/test/CodeGen/Hexagon/combine_lh.ll index 7820f1252e12..74d538b68951 100644 --- a/llvm/test/CodeGen/Hexagon/combine_lh.ll +++ b/llvm/test/CodeGen/Hexagon/combine_lh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: combine(r{{[0-9]+}}.l,r{{[0-9]+}}.h) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/combiner-lts.ll b/llvm/test/CodeGen/Hexagon/combiner-lts.ll index 2731149abcc4..88334999a382 100644 --- a/llvm/test/CodeGen/Hexagon/combiner-lts.ll +++ b/llvm/test/CodeGen/Hexagon/combiner-lts.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; In DAG combiner, eliminate a store in cases where the store is fed by a ; load from the same location. This is already done in cases where the store's diff --git a/llvm/test/CodeGen/Hexagon/common-gep-basic.ll b/llvm/test/CodeGen/Hexagon/common-gep-basic.ll index adf2d58ab996..d8915e73fc50 100644 --- a/llvm/test/CodeGen/Hexagon/common-gep-basic.ll +++ b/llvm/test/CodeGen/Hexagon/common-gep-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: mpyi ; CHECK-NOT: mpyi ; The mpyis from the two GEPs should be commoned out. diff --git a/llvm/test/CodeGen/Hexagon/common-gep-icm.ll b/llvm/test/CodeGen/Hexagon/common-gep-icm.ll index 871df7f149a6..a388aac0de91 100644 --- a/llvm/test/CodeGen/Hexagon/common-gep-icm.ll +++ b/llvm/test/CodeGen/Hexagon/common-gep-icm.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Rely on the comments generated by llc. Make sure there are no add/addasl ; instructions in while.body13 (before the loads). ; CHECK: while.body13 diff --git a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll index bb8587443995..90e68fb25c3d 100644 --- a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll +++ b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug-only=commgep 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -debug-only=commgep 2>&1 < %s | FileCheck %s ; REQUIRES: asserts ; We should generate new GEPs with "inbounds" flag. diff --git a/llvm/test/CodeGen/Hexagon/common-global-addr.ll b/llvm/test/CodeGen/Hexagon/common-global-addr.ll index ffd93a9afe6c..2c4bed5741ac 100644 --- a/llvm/test/CodeGen/Hexagon/common-global-addr.ll +++ b/llvm/test/CodeGen/Hexagon/common-global-addr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt -hexagon-cext-threshold=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt -hexagon-cext-threshold=1 < %s | FileCheck %s ; Check commoning of global addresses. @g0 = external global i32 diff --git a/llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll b/llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll index 6f73b47f9a48..514066486657 100644 --- a/llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll +++ b/llvm/test/CodeGen/Hexagon/concat-vectors-legalize.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: setbit(r{{[0-9]+}},#1) target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/const-combine.ll b/llvm/test/CodeGen/Hexagon/const-combine.ll index 2a0a8a28f486..f523f5fad2cc 100644 --- a/llvm/test/CodeGen/Hexagon/const-combine.ll +++ b/llvm/test/CodeGen/Hexagon/const-combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-const64=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-const64=1 < %s | FileCheck %s ; CHECK: combine(##4917,#88) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll index b7a4b0aa58e8..a889d4dae637 100644 --- a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll +++ b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll @@ -1,4 +1,4 @@ -; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic +; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -mcpu=hexagonv60 -relocation-model pic ; CHECK: jumpr diff --git a/llvm/test/CodeGen/Hexagon/constant_compound.ll b/llvm/test/CodeGen/Hexagon/constant_compound.ll index 87c55d5cf128..6f8a49197329 100644 --- a/llvm/test/CodeGen/Hexagon/constant_compound.ll +++ b/llvm/test/CodeGen/Hexagon/constant_compound.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=hexagon < %s 2>&1 | FileCheck %s ; Generating a compound instruction with a constant is not profitable. ; The constant needs to be kept in a register before it is fed to compound diff --git a/llvm/test/CodeGen/Hexagon/constext-call.ll b/llvm/test/CodeGen/Hexagon/constext-call.ll index 5de40208530f..b5b7fbe7f561 100644 --- a/llvm/test/CodeGen/Hexagon/constext-call.ll +++ b/llvm/test/CodeGen/Hexagon/constext-call.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that the first packet contains 4 instructions, which includes ; a call. The compiler marked the call as constant extended incorrectly, diff --git a/llvm/test/CodeGen/Hexagon/constext-immstore.ll b/llvm/test/CodeGen/Hexagon/constext-immstore.ll index 1a035ea406c1..6f7bc17beb9d 100644 --- a/llvm/test/CodeGen/Hexagon/constext-immstore.ll +++ b/llvm/test/CodeGen/Hexagon/constext-immstore.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts %s.0 = type { i8, i8, ptr, i8, i32, ptr, ptr } diff --git a/llvm/test/CodeGen/Hexagon/constext-replace.ll b/llvm/test/CodeGen/Hexagon/constext-replace.ll index 5a34af363848..31ceb45f2c07 100644 --- a/llvm/test/CodeGen/Hexagon/constext-replace.ll +++ b/llvm/test/CodeGen/Hexagon/constext-replace.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that 3 or more addressing modes using the same constant extender are ; transformed into using a register. diff --git a/llvm/test/CodeGen/Hexagon/constp-andir-global.mir b/llvm/test/CodeGen/Hexagon/constp-andir-global.mir index f50e038c5876..1382366fee1a 100644 --- a/llvm/test/CodeGen/Hexagon/constp-andir-global.mir +++ b/llvm/test/CodeGen/Hexagon/constp-andir-global.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-constp %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-constp %s -o - | FileCheck %s # Check that this doesn't crash. # CHECK: A2_andir killed %{{[0-9]+}}, @g diff --git a/llvm/test/CodeGen/Hexagon/constp-clb.ll b/llvm/test/CodeGen/Hexagon/constp-clb.ll index e2e3e4a59c7c..398e7aa1676f 100644 --- a/llvm/test/CodeGen/Hexagon/constp-clb.ll +++ b/llvm/test/CodeGen/Hexagon/constp-clb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/constp-combine-neg.ll b/llvm/test/CodeGen/Hexagon/constp-combine-neg.ll index 0d74e1db6097..eba4e7d05c2e 100644 --- a/llvm/test/CodeGen/Hexagon/constp-combine-neg.ll +++ b/llvm/test/CodeGen/Hexagon/constp-combine-neg.ll @@ -1,9 +1,9 @@ ; XFAIL: * ; Implement generic selection of a constant. -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST1 -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST2 -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST3 +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST1 +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST2 +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-TEST3 define i32 @main() #0 { entry: %l = alloca [7 x i32], align 8 diff --git a/llvm/test/CodeGen/Hexagon/constp-ctb.ll b/llvm/test/CodeGen/Hexagon/constp-ctb.ll index 193e9d658825..94dc72357a72 100644 --- a/llvm/test/CodeGen/Hexagon/constp-ctb.ll +++ b/llvm/test/CodeGen/Hexagon/constp-ctb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/constp-extract.ll b/llvm/test/CodeGen/Hexagon/constp-extract.ll index cffa4856d868..b371044be08a 100644 --- a/llvm/test/CodeGen/Hexagon/constp-extract.ll +++ b/llvm/test/CodeGen/Hexagon/constp-extract.ll @@ -1,5 +1,5 @@ ; Expect the constant propagation to evaluate signed and unsigned bit extract. -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll b/llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll index 30854ed6bfe9..b6ff9c01ede8 100644 --- a/llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll +++ b/llvm/test/CodeGen/Hexagon/constp-rewrite-branches.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s define i32 @foo(i32 %x) { %p = icmp eq i32 %x, 0 diff --git a/llvm/test/CodeGen/Hexagon/constp-rseq.ll b/llvm/test/CodeGen/Hexagon/constp-rseq.ll index c89407e4b8e4..b9965070f927 100644 --- a/llvm/test/CodeGen/Hexagon/constp-rseq.ll +++ b/llvm/test/CodeGen/Hexagon/constp-rseq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: cmp ; Make sure that the result is not a compile-time constant. diff --git a/llvm/test/CodeGen/Hexagon/constp-vsplat.ll b/llvm/test/CodeGen/Hexagon/constp-vsplat.ll index c30cac015467..96e4f695f7fc 100644 --- a/llvm/test/CodeGen/Hexagon/constp-vsplat.ll +++ b/llvm/test/CodeGen/Hexagon/constp-vsplat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll index 05b182178599..3f275f2c7fcd 100644 --- a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll +++ b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: .space {{[0-9][0-9][0-9][0-9]}} ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}}) diff --git a/llvm/test/CodeGen/Hexagon/convertdptoint.ll b/llvm/test/CodeGen/Hexagon/convertdptoint.ll index 670fd9f22814..1000c12c4c37 100644 --- a/llvm/test/CodeGen/Hexagon/convertdptoint.ll +++ b/llvm/test/CodeGen/Hexagon/convertdptoint.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate conversion from double precision floating point ; to 32-bit int value in IEEE complaint mode in V5. diff --git a/llvm/test/CodeGen/Hexagon/convertdptoll.ll b/llvm/test/CodeGen/Hexagon/convertdptoll.ll index e0c104d3b273..9e8ffecfb18a 100644 --- a/llvm/test/CodeGen/Hexagon/convertdptoll.ll +++ b/llvm/test/CodeGen/Hexagon/convertdptoll.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate conversion from double precision floating point ; to 64-bit integer value in IEEE complaint mode in V5. diff --git a/llvm/test/CodeGen/Hexagon/convertsptoint.ll b/llvm/test/CodeGen/Hexagon/convertsptoint.ll index e5dbcc299cd8..159f689afa6b 100644 --- a/llvm/test/CodeGen/Hexagon/convertsptoint.ll +++ b/llvm/test/CodeGen/Hexagon/convertsptoint.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate conversion from single precision floating point ; to 32-bit int value in IEEE complaint mode in V5. diff --git a/llvm/test/CodeGen/Hexagon/convertsptoll.ll b/llvm/test/CodeGen/Hexagon/convertsptoll.ll index dc5b71bfcda0..e71abff68ad2 100644 --- a/llvm/test/CodeGen/Hexagon/convertsptoll.ll +++ b/llvm/test/CodeGen/Hexagon/convertsptoll.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate conversion from single precision floating point ; to 64-bit int value in IEEE complaint mode in V5. diff --git a/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir b/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir index d20d7692e861..ec2a55bb5ff9 100644 --- a/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir +++ b/llvm/test/CodeGen/Hexagon/copy-to-combine-const64.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=hexagon -run-pass hexagon-copy-combine -o - %s -disable-const64=0 | FileCheck --check-prefix CHECK64 %s -# RUN: llc -march=hexagon -run-pass hexagon-copy-combine -o - %s -disable-const64=1 | FileCheck --check-prefix CHECKNO64 %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-copy-combine -o - %s -disable-const64=0 | FileCheck --check-prefix CHECK64 %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-copy-combine -o - %s -disable-const64=1 | FileCheck --check-prefix CHECKNO64 %s # CHECK64: CONST64 # CHECKNO64-NOT: CONST64 diff --git a/llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll b/llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll index 62aea4a3d712..db198fce1428 100644 --- a/llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll +++ b/llvm/test/CodeGen/Hexagon/copy-to-combine-dbg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for some sane output (original problem was a crash). ; CHECK: DEBUG_VALUE: fred:Count <- 0 diff --git a/llvm/test/CodeGen/Hexagon/count_0s.ll b/llvm/test/CodeGen/Hexagon/count_0s.ll index f611a7bd8a6a..1fea26a1baf4 100644 --- a/llvm/test/CodeGen/Hexagon/count_0s.ll +++ b/llvm/test/CodeGen/Hexagon/count_0s.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/countbits-basic.ll b/llvm/test/CodeGen/Hexagon/countbits-basic.ll index 8892dd30fb73..a4ea81e44948 100644 --- a/llvm/test/CodeGen/Hexagon/countbits-basic.ll +++ b/llvm/test/CodeGen/Hexagon/countbits-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: count_leading_0: ; CHECK: cl0(r0) diff --git a/llvm/test/CodeGen/Hexagon/csr-func-usedef.ll b/llvm/test/CodeGen/Hexagon/csr-func-usedef.ll index 042c9da52539..845df76aeee4 100644 --- a/llvm/test/CodeGen/Hexagon/csr-func-usedef.ll +++ b/llvm/test/CodeGen/Hexagon/csr-func-usedef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll b/llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll index 5bba7b37063c..95fab8820dfd 100644 --- a/llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll +++ b/llvm/test/CodeGen/Hexagon/csr_stub_calls_dwarf_frame_info.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/ctor.ll b/llvm/test/CodeGen/Hexagon/ctor.ll index 81e659dae418..0f7c3ec970f0 100644 --- a/llvm/test/CodeGen/Hexagon/ctor.ll +++ b/llvm/test/CodeGen/Hexagon/ctor.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck -check-prefix=INITARRAY %s -; RUN: llc -march=hexagon < %s -use-ctors | FileCheck -check-prefix=CTOR %s +; RUN: llc -mtriple=hexagon < %s | FileCheck -check-prefix=INITARRAY %s +; RUN: llc -mtriple=hexagon < %s -use-ctors | FileCheck -check-prefix=CTOR %s @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_P10066.ii, ptr null }] define internal void @_GLOBAL__sub_I_P10066.ii() { diff --git a/llvm/test/CodeGen/Hexagon/dadd.ll b/llvm/test/CodeGen/Hexagon/dadd.ll index d34de23ccde7..e755e33eae1c 100644 --- a/llvm/test/CodeGen/Hexagon/dadd.ll +++ b/llvm/test/CodeGen/Hexagon/dadd.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate double precision floating point add in V5. ; CHECK: call __hexagon_adddf3 diff --git a/llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll b/llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll index 172a07b19688..6bdcbcc50f68 100644 --- a/llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll +++ b/llvm/test/CodeGen/Hexagon/dag-combine-select-or0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Make sure no mux with 0 is generated. ; CHECK-NOT: mux{{.*}}#0 ; CHECK: endloop diff --git a/llvm/test/CodeGen/Hexagon/dag-indexed.ll b/llvm/test/CodeGen/Hexagon/dag-indexed.ll index 71d1b9f9f0a8..bff86cf30b43 100644 --- a/llvm/test/CodeGen/Hexagon/dag-indexed.ll +++ b/llvm/test/CodeGen/Hexagon/dag-indexed.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the DAG combiner doesn't assert because it attempts to replace diff --git a/llvm/test/CodeGen/Hexagon/dccleana.ll b/llvm/test/CodeGen/Hexagon/dccleana.ll index 85cb6d210614..346bd9693b6f 100644 --- a/llvm/test/CodeGen/Hexagon/dccleana.ll +++ b/llvm/test/CodeGen/Hexagon/dccleana.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; CHECK: dccleana diff --git a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll index 23c80b0e4aa5..754d45fbe505 100644 --- a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll +++ b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62 < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon -mcpu=hexagonv62 < %s | FileCheck %s ; CHECK: ParseFunc: ; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]]) ; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]] diff --git a/llvm/test/CodeGen/Hexagon/dealloc-store.ll b/llvm/test/CodeGen/Hexagon/dealloc-store.ll index 1ac1464839f8..9277ff1bbdc3 100644 --- a/llvm/test/CodeGen/Hexagon/dealloc-store.ll +++ b/llvm/test/CodeGen/Hexagon/dealloc-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -hexagon-shrink-frame=0 -hexagon-cext-threshold=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -hexagon-shrink-frame=0 -hexagon-cext-threshold=1 < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/dealloc_return.ll b/llvm/test/CodeGen/Hexagon/dealloc_return.ll index 2b5e64ca8b0e..13b55835985d 100644 --- a/llvm/test/CodeGen/Hexagon/dealloc_return.ll +++ b/llvm/test/CodeGen/Hexagon/dealloc_return.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @g0 = external global i32 @g1 = external global i32 diff --git a/llvm/test/CodeGen/Hexagon/debug-line_table_start.ll b/llvm/test/CodeGen/Hexagon/debug-line_table_start.ll index 0cc1515ae243..c4ebf96b2668 100644 --- a/llvm/test/CodeGen/Hexagon/debug-line_table_start.ll +++ b/llvm/test/CodeGen/Hexagon/debug-line_table_start.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test case is little iffy. It checks for line_table_start, ; which in future may be completely replaced with some other label name. diff --git a/llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll b/llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll index c70267c11618..fcc9ffd816d4 100644 --- a/llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll +++ b/llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Broken after r326208. ; XFAIL: * diff --git a/llvm/test/CodeGen/Hexagon/debug-prologue.ll b/llvm/test/CodeGen/Hexagon/debug-prologue.ll index 94bcf488ed10..d21a1eabe7ad 100644 --- a/llvm/test/CodeGen/Hexagon/debug-prologue.ll +++ b/llvm/test/CodeGen/Hexagon/debug-prologue.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Verify store/load for -g prologue ; CHECK: allocframe diff --git a/llvm/test/CodeGen/Hexagon/def-undef-deps.ll b/llvm/test/CodeGen/Hexagon/def-undef-deps.ll index 5d4b409e5f42..9c595da8f5e3 100644 --- a/llvm/test/CodeGen/Hexagon/def-undef-deps.ll +++ b/llvm/test/CodeGen/Hexagon/def-undef-deps.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; The register coalescer created (via rematerialization) a definition of diff --git a/llvm/test/CodeGen/Hexagon/default-align.ll b/llvm/test/CodeGen/Hexagon/default-align.ll index f320e5c591de..21cda6e4a2f8 100644 --- a/llvm/test/CodeGen/Hexagon/default-align.ll +++ b/llvm/test/CodeGen/Hexagon/default-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Make sure we don't use setbit to add offsets to stack objects. ; CHECK-NOT: setbit diff --git a/llvm/test/CodeGen/Hexagon/deflate.ll b/llvm/test/CodeGen/Hexagon/deflate.ll index 6a925bce52f9..644ae76d79cb 100644 --- a/llvm/test/CodeGen/Hexagon/deflate.ll +++ b/llvm/test/CodeGen/Hexagon/deflate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that the parsing succeeded. ; CHECK: f0 diff --git a/llvm/test/CodeGen/Hexagon/df-min-max.ll b/llvm/test/CodeGen/Hexagon/df-min-max.ll index d4977c731bf4..6dbc0b0635b3 100644 --- a/llvm/test/CodeGen/Hexagon/df-min-max.ll +++ b/llvm/test/CodeGen/Hexagon/df-min-max.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: df_min_olt: ; CHECK: dfmin diff --git a/llvm/test/CodeGen/Hexagon/dfp.ll b/llvm/test/CodeGen/Hexagon/dfp.ll index e4fe10bad0bd..a3e983c4e387 100644 --- a/llvm/test/CodeGen/Hexagon/dfp.ll +++ b/llvm/test/CodeGen/Hexagon/dfp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: df_add: ; CHECK: dfadd diff --git a/llvm/test/CodeGen/Hexagon/dhry.ll b/llvm/test/CodeGen/Hexagon/dhry.ll index 076ac1886581..03a7fbf2fb6b 100644 --- a/llvm/test/CodeGen/Hexagon/dhry.ll +++ b/llvm/test/CodeGen/Hexagon/dhry.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: combine(#11,#10) ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/dhry_proc8.ll b/llvm/test/CodeGen/Hexagon/dhry_proc8.ll index 2da10e8c811a..7be4337af0df 100644 --- a/llvm/test/CodeGen/Hexagon/dhry_proc8.ll +++ b/llvm/test/CodeGen/Hexagon/dhry_proc8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; Test that we generate no more than 7 packets in f0. diff --git a/llvm/test/CodeGen/Hexagon/dhry_stall.ll b/llvm/test/CodeGen/Hexagon/dhry_stall.ll index bfe99d51634c..45cbf01d7e9b 100644 --- a/llvm/test/CodeGen/Hexagon/dhry_stall.ll +++ b/llvm/test/CodeGen/Hexagon/dhry_stall.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK: } ; CHECK: [[REG0:r([0-9]+)]] = addasl diff --git a/llvm/test/CodeGen/Hexagon/disable-const64.ll b/llvm/test/CodeGen/Hexagon/disable-const64.ll index 6e34f062fd7d..829298c03f61 100644 --- a/llvm/test/CodeGen/Hexagon/disable-const64.ll +++ b/llvm/test/CodeGen/Hexagon/disable-const64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv67t < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv67t < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/dmul.ll b/llvm/test/CodeGen/Hexagon/dmul.ll index 0ad862e0dbdb..1ceb3a4787ce 100644 --- a/llvm/test/CodeGen/Hexagon/dmul.ll +++ b/llvm/test/CodeGen/Hexagon/dmul.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate double precision floating point multiply in V5. ; CHECK: call __hexagon_muldf3 diff --git a/llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll b/llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll index 0d494d3188ba..2bdbc2ff6fbe 100644 --- a/llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll +++ b/llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s define i32 @f0(i32 %a0, i32 %a1) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/double.ll b/llvm/test/CodeGen/Hexagon/double.ll index 458ab3d8611d..3d1698bb5c6f 100644 --- a/llvm/test/CodeGen/Hexagon/double.ll +++ b/llvm/test/CodeGen/Hexagon/double.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: __hexagon_adddf3 ; CHECK: __hexagon_subdf3 diff --git a/llvm/test/CodeGen/Hexagon/dsub.ll b/llvm/test/CodeGen/Hexagon/dsub.ll index b9a89201969b..2cd306581026 100644 --- a/llvm/test/CodeGen/Hexagon/dsub.ll +++ b/llvm/test/CodeGen/Hexagon/dsub.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate double precision floating point subtract in V5. ; CHECK: call __hexagon_subdf3 diff --git a/llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir b/llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir index 6cb425758746..c9c135333320 100644 --- a/llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir +++ b/llvm/test/CodeGen/Hexagon/duplex-addi-global-imm.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -start-after if-converter %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -start-after if-converter %s -o - | FileCheck %s # This used to crash. # CHECK: add(r0,##g) diff --git a/llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll b/llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll index 91a94ab88373..3594535d74b3 100644 --- a/llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll +++ b/llvm/test/CodeGen/Hexagon/dwarf-discriminator.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: {{ discriminator }} ; Function Attrs: nounwind readnone diff --git a/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir b/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir index 8fe30e3c50cf..4e65e0e90719 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-early-if %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-early-if %s -o - | FileCheck %s # Test that the LIFETIME_END instruction is not speculated and moved to a # different basic block. diff --git a/llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll b/llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll index 395b0ce3bcca..0558421e2c63 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-conversion-bug1.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; we do not want to see a segv. ; CHECK-NOT: segmentation ; CHECK: call diff --git a/llvm/test/CodeGen/Hexagon/early-if-debug.mir b/llvm/test/CodeGen/Hexagon/early-if-debug.mir index 0eb2ba71a49f..5baad7717683 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-debug.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-debug.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -eif-limit=4 -run-pass hexagon-early-if -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -eif-limit=4 -run-pass hexagon-early-if -o - %s | FileCheck %s # Check that even with the limit of 4 instructions, the block bb.1 is # if-converted. diff --git a/llvm/test/CodeGen/Hexagon/early-if-low8.mir b/llvm/test/CodeGen/Hexagon/early-if-low8.mir index 16c6ad26570e..13ba35ec39a4 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-low8.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-low8.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-early-if %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-early-if %s -o - | FileCheck %s # Make sure that early if-conversion handles the *low8 register classes: # CHECK: intregslow8 = C2_mux diff --git a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll index a9c9a814c4d6..04fe00f69f9f 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that the loop in the end has only one basic block. ; CHECK-LABEL: fred diff --git a/llvm/test/CodeGen/Hexagon/early-if-phi-i1.ll b/llvm/test/CodeGen/Hexagon/early-if-phi-i1.ll index d0a911802d9e..747d4d358946 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-phi-i1.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-phi-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Check that the early if-conversion does not predicate block1 (where the ; join block has a phi node of type i1). diff --git a/llvm/test/CodeGen/Hexagon/early-if-predicator.mir b/llvm/test/CodeGen/Hexagon/early-if-predicator.mir index 1cb2f1e93373..fa5206ca1589 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-predicator.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-predicator.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass early-if-predicator %s -o - -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass early-if-predicator %s -o - -verify-machineinstrs | FileCheck %s # Check that the store gets predicated # CHECK: S4_storeirit_io %2, %0, 0, 1 diff --git a/llvm/test/CodeGen/Hexagon/early-if-spare.ll b/llvm/test/CodeGen/Hexagon/early-if-spare.ll index 04980e6e90b6..07497e93dbe5 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-spare.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-spare.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Check if the three stores in the loop were predicated. ; CHECK: if{{.*}}memw ; CHECK: if{{.*}}memw diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll index 62914243edb8..8535c3e7b411 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll index 2694fe58029a..119553a55047 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Hexagon early if-conversion used to crash on this testcase due to not diff --git a/llvm/test/CodeGen/Hexagon/early-if.ll b/llvm/test/CodeGen/Hexagon/early-if.ll index 3fea4833817c..b88eba09bee9 100644 --- a/llvm/test/CodeGen/Hexagon/early-if.ll +++ b/llvm/test/CodeGen/Hexagon/early-if.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Rely on the comments generated by llc. Check that "if.then" was predicated. ; CHECK: while.body13 ; CHECK: if{{.*}}memd diff --git a/llvm/test/CodeGen/Hexagon/eh_return-r30.ll b/llvm/test/CodeGen/Hexagon/eh_return-r30.ll index 02e18d50fda8..7cba525b3e09 100644 --- a/llvm/test/CodeGen/Hexagon/eh_return-r30.ll +++ b/llvm/test/CodeGen/Hexagon/eh_return-r30.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/eh_return.ll b/llvm/test/CodeGen/Hexagon/eh_return.ll index 9aa1c8e57834..b9df106233c8 100644 --- a/llvm/test/CodeGen/Hexagon/eh_return.ll +++ b/llvm/test/CodeGen/Hexagon/eh_return.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; Make sure we generate an exception handling return. ; CHECK: deallocframe diff --git a/llvm/test/CodeGen/Hexagon/eh_save_restore.ll b/llvm/test/CodeGen/Hexagon/eh_save_restore.ll index 9da2b42c5c28..065dc9ed01f1 100644 --- a/llvm/test/CodeGen/Hexagon/eh_save_restore.ll +++ b/llvm/test/CodeGen/Hexagon/eh_save_restore.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon -hexagon-small-data-threshold=0 -disable-packetizer < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon -hexagon-small-data-threshold=0 -disable-packetizer < %s | FileCheck %s ; This test was orignally written to test that we don't save an entire double ; register if only one of the integer registers needs to be saved. The problem diff --git a/llvm/test/CodeGen/Hexagon/ehabi.ll b/llvm/test/CodeGen/Hexagon/ehabi.ll index d9ed4f6883d8..3232f4a25f4d 100644 --- a/llvm/test/CodeGen/Hexagon/ehabi.ll +++ b/llvm/test/CodeGen/Hexagon/ehabi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; CHECK: GCC_except_table0: ; CHECK: Call site Encoding = uleb128 diff --git a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll index 8a28d9f01559..7b22546e95a1 100644 --- a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll +++ b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-bit=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-bit=0 < %s | FileCheck %s ; This spill should be eliminated. ; CHECK-NOT: vmem(r29+#6) diff --git a/llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll b/llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll index 4ff34063d38e..8c7b1fb4462c 100644 --- a/llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll +++ b/llvm/test/CodeGen/Hexagon/entryBB-isLoopHdr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hwloop-preheader < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hwloop-preheader < %s | FileCheck %s ; check for lack of assertion failures. diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-basic.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-basic.ll index 16fe8af47b13..2b1413a8ea0b 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-basic.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: if{{.*}}add ; CHECK: if{{.*}}sub diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll index 2bb11e9e7de1..5b3d47e662b1 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-copy-lis.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the compiler doesn't assert because the live interval information diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll index af314d233e80..528286b34fc4 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; REQUIRES: asserts ; Check for some output other than crashing. diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll index d2e8b1c73390..b3962a406599 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; REQUIRES: asserts ; Check for some output (as opposed to a crash). diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll index ba9859aa95cf..4ccc054f2c6e 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts ; Test that the dead and kill flags are not added incorrectly during the diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir index 7ac04b2d5d9a..0aa26b940f75 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-def-undef.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs | FileCheck %s # CHECK-LABEL: name: fred diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll index 359c449d7547..804b00da978b 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-extend.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Check for a reasonable output. This testcase used to crash. diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir index 2536d64e01ea..d24a053cbd75 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass expand-condsets %s -o - | FileCheck %s # Check that we can expand a mux with a global as an immediate operand. # CHECK: C2_cmoveif undef %0:predregs, @G diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-impuse.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-impuse.mir index e4f99d771653..ee6eb40d305b 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-impuse.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-impuse.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs | FileCheck %s # CHECK-LABEL: name: fred diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir index ebb361ab433c..2a2864275c1d 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass=expand-condsets %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass=expand-condsets %s -o - | FileCheck %s # Check that there is a tied implicit use despite having an explicit (but # untied) use: diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir index d252ec5fee40..de05aef45e4c 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass expand-condsets %s -o - | FileCheck %s # REQUIRES: asserts # The physical register as an operand to C2_mux caused a crash. diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll index dc02f5222ea9..c110e17fe81f 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef2.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef2.ll index 5201f3e30ebc..000f5fabbcc8 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef2.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: if{{.*}}add ; CHECK: if{{.*}}sub diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir index 463aa9a8e7f9..ad760848463a 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets 2>&1 | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets 2>&1 | FileCheck %s # REQUIRES: asserts # Check that coalesced registers are removed from live intervals. diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll index bc8ae52eb654..0328b45a4755 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-rm-segment.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir b/llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir index 5b942fd3c3f1..3194c6786314 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-same-inputs.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass expand-condsets -expand-condsets-coa-limit=0 -o - %s -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass expand-condsets -expand-condsets-coa-limit=0 -o - %s -verify-machineinstrs | FileCheck %s # CHECK-LABEL: name: fred diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll index f29a21017dc3..a43d9b11473b 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-undef2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the HexagonExpandCondsets pass does not assert due to diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll index 45ba5131e668..62a695d8255a 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-undefvni.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that this compiles successfully. ; CHECK: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets.ll b/llvm/test/CodeGen/Hexagon/expand-condsets.ll index c38795ef6f0d..e0a71278ad7b 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; Check if all or's in the loop were predicated. ; CHECK: if{{.*}} = or ; CHECK: if{{.*}} = or diff --git a/llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir b/llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir index d454f1a38f19..ba98e8e010d9 100644 --- a/llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir +++ b/llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass postrapseudos -run-pass machineverifier -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass postrapseudos -run-pass machineverifier -o - %s | FileCheck %s # Check that v3 is marked as "undef". # CHECK: $w0 = V6_vcombine undef $v3, $v2 diff --git a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.mir b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.mir index 9d5acbd62363..1a9cd4f5c944 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.mir +++ b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass=postrapseudos -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass=postrapseudos -o - %s | FileCheck %s # CHECK: $v2 = V6_vcmov $p0, killed $v0 # CHECK: $v2 = V6_vncmov killed $p0, killed $v1, implicit $v2 diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll index 69ba26622726..8cce7925c3fc 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; After register allocation it is possible to have a spill of a register ; that is only partially defined. That in itself it fine, but creates a diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll index 5c14e5de4c7a..a70e90a21d13 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Dead defs may still appear live in LivePhysRegs, leading to an expansion diff --git a/llvm/test/CodeGen/Hexagon/expand-wselect.mir b/llvm/test/CodeGen/Hexagon/expand-wselect.mir index cb3dbc25aa5e..bd6a3b787932 100644 --- a/llvm/test/CodeGen/Hexagon/expand-wselect.mir +++ b/llvm/test/CodeGen/Hexagon/expand-wselect.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass postrapseudos %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass postrapseudos %s -o - | FileCheck %s # Check that this doesn't crash. # CHECK: $w2 = V6_vccombine $p0, $v1, $v0 diff --git a/llvm/test/CodeGen/Hexagon/extload-combine.ll b/llvm/test/CodeGen/Hexagon/extload-combine.ll index 3999b60ae0ed..8b18c7fb17af 100644 --- a/llvm/test/CodeGen/Hexagon/extload-combine.ll +++ b/llvm/test/CodeGen/Hexagon/extload-combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 -disable-hsdr < %s | FileCheck %s ; Check that the combine/stxw instructions are being generated. ; In case of combine one of the operand should be 0 and another should be ; the output of absolute addressing load instruction. diff --git a/llvm/test/CodeGen/Hexagon/extract-basic.ll b/llvm/test/CodeGen/Hexagon/extract-basic.ll index 9df5817e5e29..e1ecd49aeaf6 100644 --- a/llvm/test/CodeGen/Hexagon/extract-basic.ll +++ b/llvm/test/CodeGen/Hexagon/extract-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; CHECK-DAG: extractu(r{{[0-9]*}},#3,#4) ; CHECK-DAG: extractu(r{{[0-9]*}},#8,#7) diff --git a/llvm/test/CodeGen/Hexagon/extract_0bits.ll b/llvm/test/CodeGen/Hexagon/extract_0bits.ll index c75889e21506..1cb691c335b3 100644 --- a/llvm/test/CodeGen/Hexagon/extract_0bits.ll +++ b/llvm/test/CodeGen/Hexagon/extract_0bits.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9:]+}} = #0 ; Function Attrs: nounwind readnone diff --git a/llvm/test/CodeGen/Hexagon/extractu_0bits.ll b/llvm/test/CodeGen/Hexagon/extractu_0bits.ll index 3205bad487b0..c986484588cb 100644 --- a/llvm/test/CodeGen/Hexagon/extractu_0bits.ll +++ b/llvm/test/CodeGen/Hexagon/extractu_0bits.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9:]+}} = #0 ; Function Attrs: nounwind readnone diff --git a/llvm/test/CodeGen/Hexagon/fadd.ll b/llvm/test/CodeGen/Hexagon/fadd.ll index 1fdd3ca29609..4d6decc3ec45 100644 --- a/llvm/test/CodeGen/Hexagon/fadd.ll +++ b/llvm/test/CodeGen/Hexagon/fadd.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate sp floating point add in V5. ; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}},r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/fcmp.ll b/llvm/test/CodeGen/Hexagon/fcmp.ll index 5e52ccf05c28..42c8e3d7cd32 100644 --- a/llvm/test/CodeGen/Hexagon/fcmp.ll +++ b/llvm/test/CodeGen/Hexagon/fcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate floating point compare in V5 ; CHECK: p{{[0-2]+}} = sfcmp.{{.}} diff --git a/llvm/test/CodeGen/Hexagon/feature-compound.ll b/llvm/test/CodeGen/Hexagon/feature-compound.ll index a9850a80f677..46ce1448ec4f 100644 --- a/llvm/test/CodeGen/Hexagon/feature-compound.ll +++ b/llvm/test/CodeGen/Hexagon/feature-compound.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: t0 ; CHECK: r0 = add(r1,add(r0,#23)) diff --git a/llvm/test/CodeGen/Hexagon/feature-memops.ll b/llvm/test/CodeGen/Hexagon/feature-memops.ll index 7b638ec238bc..61148009c772 100644 --- a/llvm/test/CodeGen/Hexagon/feature-memops.ll +++ b/llvm/test/CodeGen/Hexagon/feature-memops.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: enabled: ; CHECK: memw({{.*}}) += #1 diff --git a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll index 04e9d3fa31c6..2b499fe0a281 100644 --- a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll +++ b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; This code causes multiple endloop instructions to be generated for the diff --git a/llvm/test/CodeGen/Hexagon/find-loop.ll b/llvm/test/CodeGen/Hexagon/find-loop.ll index 3d2ffa12ce55..ab892b79ec0e 100644 --- a/llvm/test/CodeGen/Hexagon/find-loop.ll +++ b/llvm/test/CodeGen/Hexagon/find-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts ; Test that the compiler doesn't assert when attempting to find a diff --git a/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll b/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll index 5ffbc06f1bd2..f99b448cc1a7 100644 --- a/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll +++ b/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; The early return is predicated, and the save-restore code is mixed together: ; { diff --git a/llvm/test/CodeGen/Hexagon/float-amode.ll b/llvm/test/CodeGen/Hexagon/float-amode.ll index 62ec0c6f13c8..0f7133e2d179 100644 --- a/llvm/test/CodeGen/Hexagon/float-amode.ll +++ b/llvm/test/CodeGen/Hexagon/float-amode.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -fp-contract=fast -disable-hexagon-peephole -disable-hexagon-amodeopt < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -fp-contract=fast -disable-hexagon-peephole -disable-hexagon-amodeopt < %s | FileCheck %s ; The test checks for various addressing modes for floating point loads/stores. diff --git a/llvm/test/CodeGen/Hexagon/float-bitcast.ll b/llvm/test/CodeGen/Hexagon/float-bitcast.ll index 485a43f47a7a..d63a4c5f59ed 100644 --- a/llvm/test/CodeGen/Hexagon/float-bitcast.ll +++ b/llvm/test/CodeGen/Hexagon/float-bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; All of these should be no-ops. Check this with -O0, to make sure ; that no register copies are generated at any time. diff --git a/llvm/test/CodeGen/Hexagon/float-const64-G0.ll b/llvm/test/CodeGen/Hexagon/float-const64-G0.ll index 1bf44df40123..7822c948f249 100644 --- a/llvm/test/CodeGen/Hexagon/float-const64-G0.ll +++ b/llvm/test/CodeGen/Hexagon/float-const64-G0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s ; ; Check that no CONST64's are emitted for a -G0, mv5 compile ; CHECK-NOT: CONST diff --git a/llvm/test/CodeGen/Hexagon/float-gen-cmpop.ll b/llvm/test/CodeGen/Hexagon/float-gen-cmpop.ll index 8d39ec676794..422ca6458989 100644 --- a/llvm/test/CodeGen/Hexagon/float-gen-cmpop.ll +++ b/llvm/test/CodeGen/Hexagon/float-gen-cmpop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/float.ll b/llvm/test/CodeGen/Hexagon/float.ll index 86e103522984..f34d745a36b2 100644 --- a/llvm/test/CodeGen/Hexagon/float.ll +++ b/llvm/test/CodeGen/Hexagon/float.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: sfadd ; CHECK: sfsub diff --git a/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll b/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll index 86e103522984..f34d745a36b2 100644 --- a/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll +++ b/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: sfadd ; CHECK: sfsub diff --git a/llvm/test/CodeGen/Hexagon/fltnvjump.ll b/llvm/test/CodeGen/Hexagon/fltnvjump.ll index 259ff57eb369..8921b3834823 100644 --- a/llvm/test/CodeGen/Hexagon/fltnvjump.ll +++ b/llvm/test/CodeGen/Hexagon/fltnvjump.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; We do not want to see a new value compare after the convert ; CHECK: r{{[0-9]+}} = convert_df2w ; CHECK-NOT: if (!cmp.eq(r{{[0-9]+}}.new,r{{[0-9]+}})jump diff --git a/llvm/test/CodeGen/Hexagon/fmadd.ll b/llvm/test/CodeGen/Hexagon/fmadd.ll index 06333bfc4c16..f1740ccbdd20 100644 --- a/llvm/test/CodeGen/Hexagon/fmadd.ll +++ b/llvm/test/CodeGen/Hexagon/fmadd.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -fp-contract=fast < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -fp-contract=fast < %s | FileCheck %s @g0 = global float 0.000000e+00, align 4 @g1 = global float 1.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Hexagon/fminmax.ll b/llvm/test/CodeGen/Hexagon/fminmax.ll index c90b2a25b38f..a581bd3b2186 100644 --- a/llvm/test/CodeGen/Hexagon/fminmax.ll +++ b/llvm/test/CodeGen/Hexagon/fminmax.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/fmul-v67.ll b/llvm/test/CodeGen/Hexagon/fmul-v67.ll index f17eb9525050..49098cd0cdfe 100644 --- a/llvm/test/CodeGen/Hexagon/fmul-v67.ll +++ b/llvm/test/CodeGen/Hexagon/fmul-v67.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: diff --git a/llvm/test/CodeGen/Hexagon/fmul.ll b/llvm/test/CodeGen/Hexagon/fmul.ll index 2de3836d5bd8..5c820fbdea44 100644 --- a/llvm/test/CodeGen/Hexagon/fmul.ll +++ b/llvm/test/CodeGen/Hexagon/fmul.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate single precision floating point multiply in V5. ; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}},r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/formal-args-i1.ll b/llvm/test/CodeGen/Hexagon/formal-args-i1.ll index 52f903dad0de..f80806894141 100644 --- a/llvm/test/CodeGen/Hexagon/formal-args-i1.ll +++ b/llvm/test/CodeGen/Hexagon/formal-args-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This tests validates the fact that the formal arguments of type scalar i1 ; (passed using 32-bit register) is converted back to use predicate registers ; CHECK: [[P0:p[0-3]]] = tstbit(r0,#0) diff --git a/llvm/test/CodeGen/Hexagon/fp16.ll b/llvm/test/CodeGen/Hexagon/fp16.ll index 5f256e22aaff..2f933c92e42b 100644 --- a/llvm/test/CodeGen/Hexagon/fp16.ll +++ b/llvm/test/CodeGen/Hexagon/fp16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test validates the following facts for half-precision floating point ; conversions. diff --git a/llvm/test/CodeGen/Hexagon/fp_latency.ll b/llvm/test/CodeGen/Hexagon/fp_latency.ll index 275127e01246..0da763c6c8ba 100644 --- a/llvm/test/CodeGen/Hexagon/fp_latency.ll +++ b/llvm/test/CodeGen/Hexagon/fp_latency.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon -fp-contract=fast -pipeliner-prune-loop-carried=false < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon -fp-contract=fast -pipeliner-prune-loop-carried=false < %s | FileCheck %s ; Test that there is 1 packet between the FP result and its use. diff --git a/llvm/test/CodeGen/Hexagon/fpelim-basic.ll b/llvm/test/CodeGen/Hexagon/fpelim-basic.ll index 52a68a9d22f7..e881c94777a2 100644 --- a/llvm/test/CodeGen/Hexagon/fpelim-basic.ll +++ b/llvm/test/CodeGen/Hexagon/fpelim-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll index 8b1030549750..042693862514 100644 --- a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll +++ b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -march=hexagon --stats -o - 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon --stats -o - 2>&1 < %s | FileCheck %s ; Check that the compilation succeeded and that some code was generated. ; CHECK: vadd diff --git a/llvm/test/CodeGen/Hexagon/fsel.ll b/llvm/test/CodeGen/Hexagon/fsel.ll index a2f0b4a47f10..13a54c68214c 100644 --- a/llvm/test/CodeGen/Hexagon/fsel.ll +++ b/llvm/test/CodeGen/Hexagon/fsel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK-LABEL: danny: ; CHECK: mux(p0,r1,##1065353216) diff --git a/llvm/test/CodeGen/Hexagon/fsub.ll b/llvm/test/CodeGen/Hexagon/fsub.ll index a9711f43710b..c635be77f659 100644 --- a/llvm/test/CodeGen/Hexagon/fsub.ll +++ b/llvm/test/CodeGen/Hexagon/fsub.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate sp floating point subtract in V5. ; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}},r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/funnel-shift.ll b/llvm/test/CodeGen/Hexagon/funnel-shift.ll index 6ad3b8a30519..5c318dfb6066 100644 --- a/llvm/test/CodeGen/Hexagon/funnel-shift.ll +++ b/llvm/test/CodeGen/Hexagon/funnel-shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: r[[R00:[0-9]+]]:[[R01:[0-9]+]] = combine(r0,r1) diff --git a/llvm/test/CodeGen/Hexagon/fusedandshift.ll b/llvm/test/CodeGen/Hexagon/fusedandshift.ll index e7c48249bf05..0aaf19b2fac8 100644 --- a/llvm/test/CodeGen/Hexagon/fusedandshift.ll +++ b/llvm/test/CodeGen/Hexagon/fusedandshift.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-extract=0 -hexbit-extract=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-extract=0 -hexbit-extract=0 < %s | FileCheck %s ; Check that we generate fused logical and with shift instruction. ; Disable "extract" generation, since it may eliminate the and/lsr. diff --git a/llvm/test/CodeGen/Hexagon/generate-const-buildvector32.ll b/llvm/test/CodeGen/Hexagon/generate-const-buildvector32.ll index 637e622cd284..4a2d2f2e1bad 100644 --- a/llvm/test/CodeGen/Hexagon/generate-const-buildvector32.ll +++ b/llvm/test/CodeGen/Hexagon/generate-const-buildvector32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = ##673059850 diff --git a/llvm/test/CodeGen/Hexagon/getBlockAddress.ll b/llvm/test/CodeGen/Hexagon/getBlockAddress.ll index 07d9b19ec490..78c539cf244f 100644 --- a/llvm/test/CodeGen/Hexagon/getBlockAddress.ll +++ b/llvm/test/CodeGen/Hexagon/getBlockAddress.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll b/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll index 9d4cbd9bc7c8..05ec0ae4c29c 100644 --- a/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll +++ b/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll @@ -1,4 +1,4 @@ -; RUN: opt -Os -march=hexagon -S < %s | FileCheck %s +; RUN: opt -Os -S < %s | FileCheck %s ; Don't reset the alignment on the struct to 1. ; CHECK: align 4 diff --git a/llvm/test/CodeGen/Hexagon/global-const-gep.ll b/llvm/test/CodeGen/Hexagon/global-const-gep.ll index 1c163326847a..e12270ef20f5 100644 --- a/llvm/test/CodeGen/Hexagon/global-const-gep.ll +++ b/llvm/test/CodeGen/Hexagon/global-const-gep.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that global constant GEPs are calculated correctly ; diff --git a/llvm/test/CodeGen/Hexagon/global-ctor-pcrel.ll b/llvm/test/CodeGen/Hexagon/global-ctor-pcrel.ll index 9e256bcee020..7fb813630c55 100644 --- a/llvm/test/CodeGen/Hexagon/global-ctor-pcrel.ll +++ b/llvm/test/CodeGen/Hexagon/global-ctor-pcrel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: pcrelR0 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/global64bitbug.ll b/llvm/test/CodeGen/Hexagon/global64bitbug.ll index 418940b1faad..caf472074ffa 100644 --- a/llvm/test/CodeGen/Hexagon/global64bitbug.ll +++ b/llvm/test/CodeGen/Hexagon/global64bitbug.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll b/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll index c9a30f74d536..1ae998188ad8 100644 --- a/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll +++ b/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate load instructions with global + offset diff --git a/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll b/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll index 8eb8abe0fa61..796a9056c062 100644 --- a/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll +++ b/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate store instructions with global + offset %s.0 = type { i8, i8, i16, i32 } diff --git a/llvm/test/CodeGen/Hexagon/gp-rel.ll b/llvm/test/CodeGen/Hexagon/gp-rel.ll index 0228df9d3f07..02ce3d1d63b5 100644 --- a/llvm/test/CodeGen/Hexagon/gp-rel.ll +++ b/llvm/test/CodeGen/Hexagon/gp-rel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that gp-relative instructions are being generated. ; CHECK: r{{[0-9]+}} = memw(gp+#g0) diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll index e16bd6fab4aa..6755ad0eb178 100644 --- a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll +++ b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that this testcase does not crash. ; CHECK: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll index 2f690d397508..e2c6efc159d9 100644 --- a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll +++ b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that this testcase does not crash. ; CHECK: call foo0 diff --git a/llvm/test/CodeGen/Hexagon/hello-world-v55.ll b/llvm/test/CodeGen/Hexagon/hello-world-v55.ll index 3224d8cd9f0c..7699f895cce5 100644 --- a/llvm/test/CodeGen/Hexagon/hello-world-v55.ll +++ b/llvm/test/CodeGen/Hexagon/hello-world-v55.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: call puts @g0 = private unnamed_addr constant [13 x i8] c"Hello World!\00" diff --git a/llvm/test/CodeGen/Hexagon/hello-world-v60.ll b/llvm/test/CodeGen/Hexagon/hello-world-v60.ll index c2c86c87e638..3d4096f0a0d3 100644 --- a/llvm/test/CodeGen/Hexagon/hello-world-v60.ll +++ b/llvm/test/CodeGen/Hexagon/hello-world-v60.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: call puts @g0 = private unnamed_addr constant [13 x i8] c"Hello World!\00" diff --git a/llvm/test/CodeGen/Hexagon/hexagon-cond-jumpr31.ll b/llvm/test/CodeGen/Hexagon/hexagon-cond-jumpr31.ll index becc6e32219f..603f739c1f20 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon-cond-jumpr31.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon-cond-jumpr31.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK: if (!p{{[0-3]}}.new) jumpr:nt r31 ; CHECK-NOT: .falign diff --git a/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir b/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir index 6f2d562cbe09..72d5aa655151 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir +++ b/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-move-phicopy -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-move-phicopy -o - %s | FileCheck %s # CHECK-COUNT-1: %4:intregs = COPY %1 diff --git a/llvm/test/CodeGen/Hexagon/hexagon-tfr-add.ll b/llvm/test/CodeGen/Hexagon/hexagon-tfr-add.ll index cb37fce4baeb..740834151f4c 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon-tfr-add.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon-tfr-add.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-ADDI +; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-ADDI ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hexagon-verify-implicit-use.ll b/llvm/test/CodeGen/Hexagon/hexagon-verify-implicit-use.ll index 541a359e7fa8..a5aff62140c3 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon-verify-implicit-use.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon-verify-implicit-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s +; RUN: llc -mtriple=hexagon -O3 -verify-machineinstrs < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hexagon_cfi_offset.ll b/llvm/test/CodeGen/Hexagon/hexagon_cfi_offset.ll index 23d76dc6f193..602bbf1549c0 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon_cfi_offset.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon_cfi_offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Check the values of cfi offsets emitted. ; CHECK: .cfi_def_cfa r30, 8 ; CHECK: .cfi_offset r31, -4 diff --git a/llvm/test/CodeGen/Hexagon/hidden-relocation.ll b/llvm/test/CodeGen/Hexagon/hidden-relocation.ll index ac15e7263b35..791fa098665f 100644 --- a/llvm/test/CodeGen/Hexagon/hidden-relocation.ll +++ b/llvm/test/CodeGen/Hexagon/hidden-relocation.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -relocation-model=pic < %s | FileCheck %s ; ; CHECK: r{{[0-9]+}} = add({{pc|PC}},##g2@PCREL) diff --git a/llvm/test/CodeGen/Hexagon/honor-optsize.ll b/llvm/test/CodeGen/Hexagon/honor-optsize.ll index 7bf6aad145a3..9a7811953f09 100644 --- a/llvm/test/CodeGen/Hexagon/honor-optsize.ll +++ b/llvm/test/CodeGen/Hexagon/honor-optsize.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hrc-stack-coloring.ll b/llvm/test/CodeGen/Hexagon/hrc-stack-coloring.ll index 9b77337cfc97..5ed7e2ebf256 100644 --- a/llvm/test/CodeGen/Hexagon/hrc-stack-coloring.ll +++ b/llvm/test/CodeGen/Hexagon/hrc-stack-coloring.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test is no longer connected to HRC. target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll b/llvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll index c4d2564a86a3..d2be036e6695 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-bitcast-v64i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s ; Test that LLVM does not assert and bitcast v64i1 to i64 is lowered ; without crashing. diff --git a/llvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll b/llvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll index d737510b2880..656b1306fb45 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-byte-store-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length128b < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv60,+hvx-length128b < %s | FileCheck %s ; Test that we generate code for the vector byte enable store intrinsics. diff --git a/llvm/test/CodeGen/Hexagon/hvx-byte-store.ll b/llvm/test/CodeGen/Hexagon/hvx-byte-store.ll index 170ec02dfa28..edf90ab7d377 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-byte-store.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-byte-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length64b < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv60,+hvx-length64b < %s | FileCheck %s ; Test that we generate code for the vector byte enabled store intrinsics. diff --git a/llvm/test/CodeGen/Hexagon/hvx-concat-lower.ll b/llvm/test/CodeGen/Hexagon/hvx-concat-lower.ll index 2037493972fc..90f91238d51b 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-concat-lower.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-concat-lower.ll @@ -1,7 +1,7 @@ ; During lowering of HVX instruction for 64B vector, the rotation ; direction for VROR (as part of concat of vectors lowering) is fixed. -; RUN: llc -march=hexagon -O2 %s -o - | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 %s -o - | FileCheck %s ; CHECK: vec.epilog.ph ; CHECK: r{{.*}} = {{.*}}#48 diff --git a/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll b/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll index 8cd4265eb64f..b2790ea0be07 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-dbl-dual-output.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we compile the HVX dual output intrinsics. diff --git a/llvm/test/CodeGen/Hexagon/hvx-double-vzero.ll b/llvm/test/CodeGen/Hexagon/hvx-double-vzero.ll index 110eb6cdb0a4..3151c13a0d26 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-double-vzero.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-double-vzero.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that V_vzero and W_vzero intrinsics work. The W_vzero intrinsic was added ; for v65/hvx. diff --git a/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll b/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll index cb4158d37fdb..6998ffac5afd 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-dual-output.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we compile the HVX dual output intrinsics. diff --git a/llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll b/llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll index 7ba2bb2948c1..66d7af42153c 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to crash with ; "llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && ; Expected a SimpleValueType!' failed." diff --git a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll index 5054197fdf09..bbfd05f3b880 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" ; Function Attrs: norecurse nounwind diff --git a/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll b/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll index 9ca1b1790a8c..16cc1f34a253 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-reuse-fi-base.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hvx-vzero.ll b/llvm/test/CodeGen/Hexagon/hvx-vzero.ll index 3550f0929ff4..4f82e4963a39 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-vzero.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-vzero.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that V_vzero and W_vzero intrinsics work. The W_vzero intrinsic was added ; for v65/hvx. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll b/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll index 29cd88f334ff..fd91ab9e5f46 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -no-phi-elim-live-out-early-exit < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -no-phi-elim-live-out-early-exit < %s | FileCheck %s ; Check that we remove the compare and induction variable instructions ; after generating hardware loops. ; Bug 6685. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-const.ll b/llvm/test/CodeGen/Hexagon/hwloop-const.ll index 58160dec4498..27696daa02df 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-const.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-const.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: endloop target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/hwloop-crit-edge.ll b/llvm/test/CodeGen/Hexagon/hwloop-crit-edge.ll index d004fbbcbdd1..4f85d8e17c50 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-crit-edge.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-crit-edge.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; XFAIL: * ; ; Generate hardware loop when loop 'latch' block is different diff --git a/llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir b/llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir index db3c7bf86ff2..69aab00ae8b7 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir +++ b/llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hwloops -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hwloops -o - %s | FileCheck %s # This used to crash with `Assertion `isReg() && "This is not a register operand!"` # CHECK: J2_loop0r diff --git a/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll b/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll index 1739b6188f4d..b83ada79161d 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=hexagon -disable-lsr | FileCheck %s +; RUN: llc < %s -mtriple=hexagon -disable-lsr | FileCheck %s ; CHECK: loop0( ; CHECK-NOT: add({{r[0-9]*}}, # diff --git a/llvm/test/CodeGen/Hexagon/hwloop-ice.ll b/llvm/test/CodeGen/Hexagon/hwloop-ice.ll index 57e2faaa3a2a..b079cebe90d7 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-ice.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-ice.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s +; RUN: llc -O2 -mtriple=hexagon < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/hwloop-le.ll b/llvm/test/CodeGen/Hexagon/hwloop-le.ll index 4d6e7bd9b110..4601d3962638 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-le.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-le.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: loop0 diff --git a/llvm/test/CodeGen/Hexagon/hwloop-long.ll b/llvm/test/CodeGen/Hexagon/hwloop-long.ll index eb9627b846f5..a5f7788c45ef 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-long.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-long.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we generate a hardware loop for long long counters. ; Tests signed/unsigned GT, EQ, and NEQ cases. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-loop1.ll b/llvm/test/CodeGen/Hexagon/hwloop-loop1.ll index 47aa32a60e5b..ae20529f5c0a 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-loop1.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-loop1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner=0 < %s | FileCheck %s ; ; Generate loop1 instruction for double loop sequence. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-lt.ll b/llvm/test/CodeGen/Hexagon/hwloop-lt.ll index dc9d25e8071c..c3cd99edd2b7 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-lt.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-lt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK-LABEL: @test_pos1_ir_slt ; CHECK: loop0 diff --git a/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll b/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll index 614d23c389cd..378c2e90d75e 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-lt1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate a hardware loop instruction. ; CHECK: endloop0 diff --git a/llvm/test/CodeGen/Hexagon/hwloop-missed.ll b/llvm/test/CodeGen/Hexagon/hwloop-missed.ll index e0e01884ad1d..a11a0381c8a8 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-missed.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-missed.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hwloop-preheader < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-hwloop-preheader < %s | FileCheck %s ; Generate hardware loops when we also need to add a new preheader. ; we should generate two hardware loops for this test case. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-ne.ll b/llvm/test/CodeGen/Hexagon/hwloop-ne.ll index a474f3a1681f..be0a31dd217c 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-ne.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-ne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: loop0 diff --git a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll index d76c13d73bdf..59348d5b21dd 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll b/llvm/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll index 6ca50171ff05..f5c20545b9e1 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s ; Test that there is no redundant register assignment in the hardware loop ; preheader. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-phi-subreg.ll b/llvm/test/CodeGen/Hexagon/hwloop-phi-subreg.ll index b42a0d44f7ba..0a575144e8f4 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-phi-subreg.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-phi-subreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-hwloop-preheader < %s +; RUN: llc -mtriple=hexagon -hexagon-hwloop-preheader < %s ; REQUIRES: asserts ; Checks that a subreg in a Phi is propagated correctly when a diff --git a/llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll b/llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll index 7c5ea031ffae..2c52a258215b 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll @@ -1,4 +1,4 @@ -;RUN: llc -march=hexagon < %s | FileCheck %s +;RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that a hardware loop is not generaetd due to a potential ; underflow. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll index 5b45d59fe67c..c1a97220fc61 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-machine-licm -hwloop-spec-preheader=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-machine-licm -hwloop-spec-preheader=1 < %s | FileCheck %s ; CHECK: loop0 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hwloop-preheader.ll b/llvm/test/CodeGen/Hexagon/hwloop-preheader.ll index 19a8ae1a8b82..46f88c74210d 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-preheader.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-preheader.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-hwloop-preheader < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -hexagon-hwloop-preheader < %s ; REQUIRES: asserts ; Test that the preheader is added to the parent loop, otherwise diff --git a/llvm/test/CodeGen/Hexagon/hwloop-range.ll b/llvm/test/CodeGen/Hexagon/hwloop-range.ll index 59f94b20cfc0..2b7ed396036d 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-range.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-range.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-loop-range=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-loop-range=0 < %s | FileCheck %s ; Test that the loop start address operand uses a constant extender ; if the offset is out of range. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-recursion.ll b/llvm/test/CodeGen/Hexagon/hwloop-recursion.ll index d9f2a94d0fff..0ab792234dbd 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-recursion.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-recursion.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon -mcpu=hexagonv5 < %s +; RUN: llc -O2 -mtriple=hexagon -mcpu=hexagonv5 < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir b/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir index 16af60cc0169..0f83f9364e45 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir +++ b/llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hwloops %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hwloops %s -o - | FileCheck %s # Normally, if the registers holding the induction variable's bounds # are redefined inside of the loop's body, the loop cannot be converted diff --git a/llvm/test/CodeGen/Hexagon/hwloop-subreg.ll b/llvm/test/CodeGen/Hexagon/hwloop-subreg.ll index ef0ef5651cb3..5e2ca206a109 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-subreg.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-subreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/hwloop-swap.ll b/llvm/test/CodeGen/Hexagon/hwloop-swap.ll index fdb154ab5bbe..fef099e9a583 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-swap.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-swap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that the hardware loop pass does not alter the comparison ; to use the result from the induction expression instead of diff --git a/llvm/test/CodeGen/Hexagon/hwloop-with-return-call.ll b/llvm/test/CodeGen/Hexagon/hwloop-with-return-call.ll index 6fcf4b64b784..12f32b6b82a8 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-with-return-call.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-with-return-call.ll @@ -1,6 +1,6 @@ ; This test was return to make sure a hardware loop is not generated if a ; returning call is present in the basic block. -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: loop ; CHECK-NOT: endloop diff --git a/llvm/test/CodeGen/Hexagon/hwloop-wrap.ll b/llvm/test/CodeGen/Hexagon/hwloop-wrap.ll index e0f6a87fd2e4..b179b0858ec8 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-wrap.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-wrap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; We shouldn't generate a hardware loop in this case because the initial ; value may be zero, which means the endloop instruction will not decrement diff --git a/llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll b/llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll index ae041eed688c..686c3ef1c893 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s ; Test that we do not generate a hardware loop due to a potential underflow. diff --git a/llvm/test/CodeGen/Hexagon/hwloop1.ll b/llvm/test/CodeGen/Hexagon/hwloop1.ll index cdc9835e21a6..c8aeebc0dbe5 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop1.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner=false < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner=false < %s | FileCheck %s ; Check that we generate hardware loop instructions. ; Case 1 : Loop with a constant number of iterations. diff --git a/llvm/test/CodeGen/Hexagon/hwloop2.ll b/llvm/test/CodeGen/Hexagon/hwloop2.ll index 98d418abcd66..647f181c9892 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop2.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop2.ll @@ -1,4 +1,4 @@ -; RUN: llc -disable-lsr -march=hexagon < %s | FileCheck %s +; RUN: llc -disable-lsr -mtriple=hexagon < %s | FileCheck %s ; Test for multiple phis with induction variables. diff --git a/llvm/test/CodeGen/Hexagon/hwloop3.ll b/llvm/test/CodeGen/Hexagon/hwloop3.ll index f70623e78794..8b5002347b1f 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop3.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Remove the unconditional jump to following instruction. diff --git a/llvm/test/CodeGen/Hexagon/hwloop4.ll b/llvm/test/CodeGen/Hexagon/hwloop4.ll index 5c860628697f..7f7375b31ee3 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop4.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; ; Remove the unnecessary 'add' instruction used for the hardware loop setup. diff --git a/llvm/test/CodeGen/Hexagon/hwloop5.ll b/llvm/test/CodeGen/Hexagon/hwloop5.ll index b8b7745e5e36..bcf419869693 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop5.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop5.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; ; Generate hardware loop when unknown trip count loop is vectorized. diff --git a/llvm/test/CodeGen/Hexagon/hx_V6_lo_hi.ll b/llvm/test/CodeGen/Hexagon/hx_V6_lo_hi.ll index 909acaa7b66d..1db7a59a10cb 100644 --- a/llvm/test/CodeGen/Hexagon/hx_V6_lo_hi.ll +++ b/llvm/test/CodeGen/Hexagon/hx_V6_lo_hi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that we do not generate v0 = vand(v1,v1) diff --git a/llvm/test/CodeGen/Hexagon/i128-bitop.ll b/llvm/test/CodeGen/Hexagon/i128-bitop.ll index fc7cc100fece..24e8ce9f068d 100644 --- a/llvm/test/CodeGen/Hexagon/i128-bitop.ll +++ b/llvm/test/CodeGen/Hexagon/i128-bitop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/i16_VarArg.ll b/llvm/test/CodeGen/Hexagon/i16_VarArg.ll index 6f0e0b602af0..a1e40fbfbe7a 100644 --- a/llvm/test/CodeGen/Hexagon/i16_VarArg.ll +++ b/llvm/test/CodeGen/Hexagon/i16_VarArg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: dfcmp @g0 = internal constant [12 x i8] c"a < b = %d\0A\00" diff --git a/llvm/test/CodeGen/Hexagon/i1_VarArg.ll b/llvm/test/CodeGen/Hexagon/i1_VarArg.ll index a1b1cebc3e2f..9f3672f58db3 100644 --- a/llvm/test/CodeGen/Hexagon/i1_VarArg.ll +++ b/llvm/test/CodeGen/Hexagon/i1_VarArg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: dfcmp @g0 = internal constant [12 x i8] c"a < b = %d\0A\00" diff --git a/llvm/test/CodeGen/Hexagon/i8_VarArg.ll b/llvm/test/CodeGen/Hexagon/i8_VarArg.ll index 05c70dbc2df6..616a540f222f 100644 --- a/llvm/test/CodeGen/Hexagon/i8_VarArg.ll +++ b/llvm/test/CodeGen/Hexagon/i8_VarArg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: dfcmp @g0 = internal constant [12 x i8] c"a < b = %d\0A\00" diff --git a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll index 11f0363f8c7f..318c4c0f912b 100644 --- a/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll +++ b/llvm/test/CodeGen/Hexagon/idxload-with-zero-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate load instruction with (base + register offset << x) ; load word diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-common-kill.mir b/llvm/test/CodeGen/Hexagon/ifcvt-common-kill.mir index ede16edbf637..2b1128d30e5d 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-common-kill.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-common-kill.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass if-converter -o - %s -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass if-converter -o - %s -verify-machineinstrs | FileCheck %s # CHECK: $r26 = A2_tfr $r1 # CHECK: S2_pstorerhf_io undef $p0, undef $r0, 0, killed $r1 diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll index 507e3b25bacc..0c705c0d3839 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll +++ b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -minimum-jump-tables=1 < %s +; RUN: llc -mtriple=hexagon -minimum-jump-tables=1 < %s ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll index 00e9cf25a704..df6613fd8fb3 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll +++ b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-eif=0 -disable-machine-sink < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-eif=0 -disable-machine-sink < %s | FileCheck %s target triple = "hexagon" %struct.0 = type { i16, i16 } diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir index 630b2860e1b0..673e8c7b11b5 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass if-converter %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass if-converter %s -o - | FileCheck %s # Make sure this gets if-converted and it doesn't crash. # CHECK-LABEL: bb.0 diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll b/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll index b32f4b89484e..81cb317d8d58 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll +++ b/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -stop-after=if-converter < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -stop-after=if-converter < %s | FileCheck %s ; Check that the edge weights are updated correctly after if-conversion. ; CHECK: bb.3.if{{[0-9a-zA-Z.]*}}: diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir b/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir index 6b7fe9c3905b..4ebb4d4d63c8 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass if-converter %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass if-converter %s -o - | FileCheck %s # Make sure that the necessary implicit uses are added to predicated # instructions. diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir b/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir index 0db49f367310..328883e106e4 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass if-converter -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass if-converter -o - %s | FileCheck %s # Check that an implicit use is generated for a predicated instruction # when a subregister of the redefined register is live. diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-simple-bprob.ll b/llvm/test/CodeGen/Hexagon/ifcvt-simple-bprob.ll index 2d48d30dd7d8..9fa8fb2aa572 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-simple-bprob.ll +++ b/llvm/test/CodeGen/Hexagon/ifcvt-simple-bprob.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Check that branch probabilities are set correctly after performing the ; simple variant of if-conversion. The converted block has a branch that diff --git a/llvm/test/CodeGen/Hexagon/ignore-terminal-mbb.ll b/llvm/test/CodeGen/Hexagon/ignore-terminal-mbb.ll index 690ccb9ba7a5..0284b578fd61 100644 --- a/llvm/test/CodeGen/Hexagon/ignore-terminal-mbb.ll +++ b/llvm/test/CodeGen/Hexagon/ignore-terminal-mbb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; CHECK-NOT: if{{.*}}jump{{.*}}-1 ; CHECK: memw diff --git a/llvm/test/CodeGen/Hexagon/imm-range-check.ll b/llvm/test/CodeGen/Hexagon/imm-range-check.ll index 290a5b69d333..5f299aec81eb 100644 --- a/llvm/test/CodeGen/Hexagon/imm-range-check.ll +++ b/llvm/test/CodeGen/Hexagon/imm-range-check.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -filetype=obj < %s | llvm-objdump -d - | FileCheck %s +; RUN: llc -mtriple=hexagon -filetype=obj < %s | llvm-objdump -d - | FileCheck %s ; The output assembly (textual) contains the instruction ; r29 = add(r29,#4294967136) diff --git a/llvm/test/CodeGen/Hexagon/indirect-br.ll b/llvm/test/CodeGen/Hexagon/indirect-br.ll index 781481954f4e..6627f73f158e 100644 --- a/llvm/test/CodeGen/Hexagon/indirect-br.ll +++ b/llvm/test/CodeGen/Hexagon/indirect-br.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; CHECK: jumpr r{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/initial-exec.ll b/llvm/test/CodeGen/Hexagon/initial-exec.ll index 1d9527d05324..200539759b64 100644 --- a/llvm/test/CodeGen/Hexagon/initial-exec.ll +++ b/llvm/test/CodeGen/Hexagon/initial-exec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-a.ll b/llvm/test/CodeGen/Hexagon/inline-asm-a.ll index 23e48fa0f444..c7582918a98d 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-a.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-a.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that constraint a is handled correctly. ; CHECK: [[M:m[01]]] = r1 diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll b/llvm/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll index da638047ddb9..3f6241a4986b 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-bad-constraint.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=hexagon < %s 2>&1 | FileCheck %s ; CHECK: error: couldn't allocate output register for constraint 'r' diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-clobber-lr.ll b/llvm/test/CodeGen/Hexagon/inline-asm-clobber-lr.ll index 06de6dad23d6..84aa4477fde7 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-clobber-lr.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-clobber-lr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: allocframe target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-error.ll b/llvm/test/CodeGen/Hexagon/inline-asm-error.ll index cf6bf51faea1..4b9f6d246cb4 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-error.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-error.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=hexagon < %s 2>&1 | FileCheck %s ; CHECK: error: Don't know how to handle indirect register inputs yet for constraint 'r' diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll b/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll index 48313f5038f1..a965202515f8 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-hexagon.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -no-integrated-as < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll index ee5a415b1055..34213730a5bb 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r[[REG0:[0-9]+]] = usr ; CHECK: [[REG0]] = insert(r{{[0-9]+}},#1,#16) diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll index 0577c6be7d81..fe562fdc3d67 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -no-integrated-as < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -no-integrated-as < %s | FileCheck %s ; Check that constraints q and v are handled correctly. ; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w) diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll index 0a6dabb95e8b..4f2d196634c5 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Make sure we can handle the 'q' constraint in the 128-byte mode. diff --git a/llvm/test/CodeGen/Hexagon/inline-division-space.ll b/llvm/test/CodeGen/Hexagon/inline-division-space.ll index 9cf3c5c8b2b8..c1937600d47b 100644 --- a/llvm/test/CodeGen/Hexagon/inline-division-space.ll +++ b/llvm/test/CodeGen/Hexagon/inline-division-space.ll @@ -1,5 +1,5 @@ ; Test for checking division is inlined or not in case of Os. -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Function Attrs: optsize define dso_local i32 @testInt(i32 %a, i32 %b) local_unnamed_addr #0 { diff --git a/llvm/test/CodeGen/Hexagon/inline-division.ll b/llvm/test/CodeGen/Hexagon/inline-division.ll index 7249a3f55e86..5eb97a002b0f 100644 --- a/llvm/test/CodeGen/Hexagon/inline-division.ll +++ b/llvm/test/CodeGen/Hexagon/inline-division.ll @@ -1,5 +1,5 @@ ; Test for checking division is inlined or not in case of Os. -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s define dso_local i32 @testInt(i32 %a, i32 %b) local_unnamed_addr { entry: diff --git a/llvm/test/CodeGen/Hexagon/insert-basic.ll b/llvm/test/CodeGen/Hexagon/insert-basic.ll index 3781c423fefc..bf8f526c2139 100644 --- a/llvm/test/CodeGen/Hexagon/insert-basic.ll +++ b/llvm/test/CodeGen/Hexagon/insert-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; CHECK-DAG: insert(r{{[0-9]*}},#17,#0) ; CHECK-DAG: insert(r{{[0-9]*}},#18,#0) ; CHECK-DAG: insert(r{{[0-9]*}},#22,#0) diff --git a/llvm/test/CodeGen/Hexagon/insert.ll b/llvm/test/CodeGen/Hexagon/insert.ll index cb6e8bbfb0aa..7d96438a3e98 100644 --- a/llvm/test/CodeGen/Hexagon/insert.ll +++ b/llvm/test/CodeGen/Hexagon/insert.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: r{{[0-9]+}}:{{[0-9]+}} = insert(r{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}}) @g0 = common global [512 x i16] zeroinitializer, align 8 diff --git a/llvm/test/CodeGen/Hexagon/insert4.ll b/llvm/test/CodeGen/Hexagon/insert4.ll index f88ae8dc5f7b..1e27a4450a4c 100644 --- a/llvm/test/CodeGen/Hexagon/insert4.ll +++ b/llvm/test/CodeGen/Hexagon/insert4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that we no longer generate 4 inserts. ; CHECK: combine(r{{[0-9]+}}.l,r{{[0-9]+}}.l) diff --git a/llvm/test/CodeGen/Hexagon/instrprof-custom.ll b/llvm/test/CodeGen/Hexagon/instrprof-custom.ll index c2d1e3b54b5c..620b2acc4952 100644 --- a/llvm/test/CodeGen/Hexagon/instrprof-custom.ll +++ b/llvm/test/CodeGen/Hexagon/instrprof-custom.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test1: ; CHECK: {{call my_instrprof_handler|r0 = #999}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-alu.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-alu.ll index ca026ded3f91..cb8a6d16a6cd 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-alu.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-alu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test1: ; CHECK: v{{[0-9]+}} = vand(v{{[0-9]+}},v{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-misc.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-misc.ll index 8f12dca50434..af6c39bafba4 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-misc.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-misc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @l = external global <32 x i32> @k = external global <16 x i32> diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-permute.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-permute.ll index 7a16d77d8dd4..0930cf63eb24 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-permute.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-permute.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @d = external global <16 x i32> @c = external global <32 x i32> diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-shift.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-shift.ll index 162ab73918d3..23972c437484 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-shift.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @d = external global <16 x i32> diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll index 43953d9dca76..0fdfa005aab3 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @d = external global <16 x i32>, align 64 diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc-128B.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc-128B.ll index b35561a23605..8d4518cd0aea 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc-128B.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc-128B.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @c = external global <64 x i32> @d = external global <32 x i32> diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc.ll index 383314947523..8b37cd6da069 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy-acc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @c = external global <32 x i32> @d = external global <16 x i32> diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy.ll index 1060a809ede6..5a6f6b655358 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v60-vmpy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @c = external global <32 x i32> @d = external global <16 x i32> diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v66.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v66.ll index 2732b9cb3961..767c33fb643a 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v66.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v66.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv66 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv66 < %s | FileCheck %s ; CHECK-LABEL: @test1 ; CHECK: r0 -= mpyi(r1,r2) diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-v67.ll b/llvm/test/CodeGen/Hexagon/intrinsics-v67.ll index bca9332a4d58..ce7d7d2978f3 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics-v67.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics-v67.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: @t1 ; CHECK: r{{[0-9]+}}:{{[0-9]+}} += dfmpylh(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll b/llvm/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll index abdd4cba7c5c..2b9be8d683ee 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll b/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll index 554dac4563d1..d44500d39e9f 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll b/llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll index a682159ad24f..30afb93732e4 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/atomic_load.ll @@ -1,7 +1,7 @@ -; RUN: sed -e "s/ORDER/unordered/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s -; RUN: sed -e "s/ORDER/monotonic/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s -; RUN: sed -e "s/ORDER/acquire/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -march=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s +; RUN: sed -e "s/ORDER/unordered/" %s | llc -mtriple=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" %s | llc -mtriple=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" %s | llc -mtriple=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -mtriple=hexagon -disable-hexagon-amodeopt=0 | FileCheck %s %struct.Obj = type { [100 x i32] } diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/atomic_store.ll b/llvm/test/CodeGen/Hexagon/intrinsics/atomic_store.ll index 78eb11a1fee1..124e480b894a 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/atomic_store.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/atomic_store.ll @@ -1,7 +1,7 @@ -; RUN: sed -e "s/ORDER/unordered/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/monotonic/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -march=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/unordered/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -mtriple=hexagon | FileCheck %s %struct.Obj = type { [100 x i32] } diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll index d47bc8baa2b7..b1c5b3b54d91 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_addsub_native.ll @@ -1,13 +1,13 @@ -; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/add/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/sub/" %s | llc -march=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/add/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/add/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/add/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/add/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/add/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/sub/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/sub/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/sub/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/sub/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/sub/" %s | llc -mtriple=hexagon | FileCheck %s %struct.Obj = type { [100 x i32] } diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll index c60a30eff605..745a3edfad55 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_bitwise_native.ll @@ -1,18 +1,18 @@ -; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/and/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/and/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/and/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/and/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/and/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/xor/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/xor/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/xor/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/xor/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/xor/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/or/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/or/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/or/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/or/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/or/" %s | llc -march=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/and/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/and/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/and/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/and/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/and/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/xor/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/xor/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/xor/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/xor/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/xor/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" -e "s/BINARY_OP/or/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" -e "s/BINARY_OP/or/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" -e "s/BINARY_OP/or/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acq_rel/" -e "s/BINARY_OP/or/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" -e "s/BINARY_OP/or/" %s | llc -mtriple=hexagon | FileCheck %s @g0 = global i32 0, align 4 @g1 = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll index 5d292c39bc01..d9d4a37e4a15 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/atomicrmw_nand.ll @@ -1,8 +1,8 @@ -; RUN: sed -e "s/ORDER/monotonic/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acquire/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acq_rel/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -march=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/monotonic/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acq_rel/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -mtriple=hexagon | FileCheck %s @g0 = global i32 0, align 4 @g1 = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll index 7c50977d1529..65057d54c97a 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvxv60,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length128b -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq_128B ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll index 805fbf071f97..ba2dbfb9796d 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvxv60,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length64b -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll b/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll index 4c0fcb3707c1..5e08e57a11a5 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/cr.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.2 CR ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/fence.ll b/llvm/test/CodeGen/Hexagon/intrinsics/fence.ll index 6a34f3e13646..a3ccd6750867 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/fence.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/fence.ll @@ -1,11 +1,11 @@ -; RUN: sed -e "s/ORDER/acquire/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/release/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/acq_rel/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e 's/ORDER/syncscope("singlethread") acquire/' %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e 's/ORDER/syncscope("singlethread") release/' %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e 's/ORDER/syncscope("singlethread") acq_rel/' %s | llc -march=hexagon | FileCheck %s -; RUN: sed -e 's/ORDER/syncscope("singlethread") seq_cst/' %s | llc -march=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acquire/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/release/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/acq_rel/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e "s/ORDER/seq_cst/" %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e 's/ORDER/syncscope("singlethread") acquire/' %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e 's/ORDER/syncscope("singlethread") release/' %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e 's/ORDER/syncscope("singlethread") acq_rel/' %s | llc -mtriple=hexagon | FileCheck %s +; RUN: sed -e 's/ORDER/syncscope("singlethread") seq_cst/' %s | llc -mtriple=hexagon | FileCheck %s define void @fence_func() #0 { entry: diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll b/llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll index fbeaede5599d..a5cb10d19123 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/llsc_bundling.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s target triple = "hexagon-unknown--elf" ; Function Attrs: norecurse nounwind diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll index 8c7228a2c27e..bc9e47ca0120 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll index 6d9800ee882f..4fdcc4156631 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vgathermw_128B ; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll index 475cb6c8a3f4..691bad9733e9 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll @@ -1,4 +1,4 @@ -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vgathermw ; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll index 18ae2bac611f..74700e4bae5b 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vscattermw_128B ; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll index f7d857600cdd..816e9c0bb6d3 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll @@ -1,6 +1,6 @@ -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 -disable-packetizer < %s | FileCheck %s -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -mtriple=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -mtriple=hexagon -O2 -disable-packetizer < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: vtmp.h = vgather(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h ; CHECK-NEXT: vmem(r{{[0-9]+}}+#0) = vtmp.new diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll index 1a61ee8b9c62..96b06ab60888 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll @@ -1,4 +1,4 @@ -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vscattermw ; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll index 8ee366b844b7..fd1b629c35f7 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll @@ -1,5 +1,5 @@ -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll index 4d630c62005b..a28c9ff6e56e 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \ +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O0 < %s | \ ; RUN: FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll index ec7613e3ef2a..89492c92fdf2 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.2 XTYPE/BIT ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll index 254b928aa982..ed98a7687817 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.3 XTYPE/COMPLEX ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll index 7984fee55580..5ded0232b0dd 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \ +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O0 < %s | \ ; RUN: FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.4 XTYPE/FP diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll index 4da4a8a6393f..0ac93c3ffcf1 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \ +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O0 < %s | \ ; RUN: FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.5 XTYPE/MPY diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll index 9260790e33a6..7e73d9d313e6 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.6 XTYPE/PERM ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll index 506dc88d3c1a..7cfa08a33971 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll index 8809baf3551b..fbb00469269d 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s ; Hexagon Programmer's Reference Manual 11.10.8 XTYPE/SHIFT ; CHECK-CALL-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir b/llvm/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir index 7fe7fcfae581..6d5f46c0366d 100644 --- a/llvm/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir +++ b/llvm/test/CodeGen/Hexagon/invalid-dotnew-attempt.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -start-after if-converter %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -start-after if-converter %s -o - | FileCheck %s # CHECK: p0 = r0 # CHECK-NEXT: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/invalid-memrefs.ll b/llvm/test/CodeGen/Hexagon/invalid-memrefs.ll index ba87c3163f5c..87e3a51c1fd2 100644 --- a/llvm/test/CodeGen/Hexagon/invalid-memrefs.ll +++ b/llvm/test/CodeGen/Hexagon/invalid-memrefs.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon -hexagon-expand-condsets=0 < %s +; RUN: llc -O2 -mtriple=hexagon -hexagon-expand-condsets=0 < %s ; REQUIRES: asserts ; Disable expand-condsets because it will assert on undefined registers. diff --git a/llvm/test/CodeGen/Hexagon/is-legal-void.ll b/llvm/test/CodeGen/Hexagon/is-legal-void.ll index cc6639ef6f5a..d736ad09e83e 100644 --- a/llvm/test/CodeGen/Hexagon/is-legal-void.ll +++ b/llvm/test/CodeGen/Hexagon/is-legal-void.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; The two loads based on %struct.0, loading two different data types diff --git a/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll b/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll index 84a8f913a1f5..8cd65ba51781 100644 --- a/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll +++ b/llvm/test/CodeGen/Hexagon/isel-bitcast-v1i8-i8.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This shouldn't crash. diff --git a/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i1-i8.ll b/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i1-i8.ll index 37b82433dd70..e935af28fde6 100644 --- a/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i1-i8.ll +++ b/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i1-i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Check that this doesn't crash. diff --git a/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i8-v4i16.ll b/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i8-v4i16.ll index f45b1a77c6d7..623fe89e4447 100644 --- a/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i8-v4i16.ll +++ b/llvm/test/CodeGen/Hexagon/isel-bitcast-v8i8-v4i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't fail to select instructions. ; CHECK: vsplath diff --git a/llvm/test/CodeGen/Hexagon/isel-buildvector-v2f16.ll b/llvm/test/CodeGen/Hexagon/isel-buildvector-v2f16.ll index f306b5229134..34d33d4ed6a5 100644 --- a/llvm/test/CodeGen/Hexagon/isel-buildvector-v2f16.ll +++ b/llvm/test/CodeGen/Hexagon/isel-buildvector-v2f16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: dealloc_return diff --git a/llvm/test/CodeGen/Hexagon/isel-combine-half.ll b/llvm/test/CodeGen/Hexagon/isel-combine-half.ll index c5cb5a9237a7..3806f9e1bfa1 100644 --- a/llvm/test/CodeGen/Hexagon/isel-combine-half.ll +++ b/llvm/test/CodeGen/Hexagon/isel-combine-half.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: A2_combine_ll: ; CHECK: combine(r1.l,r0.l) diff --git a/llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll b/llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll index d7168489c1a3..a7ce79e2228c 100644 --- a/llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll +++ b/llvm/test/CodeGen/Hexagon/isel-dcfetch-intrin-map.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that intrinsic int_hexagon_Y2_dcfetch is mapped to Y2_dcfetchbo ; (not Y2_dcfetch). diff --git a/llvm/test/CodeGen/Hexagon/isel-exti1.ll b/llvm/test/CodeGen/Hexagon/isel-exti1.ll index b49986628e4e..1ba697ecd29b 100644 --- a/llvm/test/CodeGen/Hexagon/isel-exti1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-exti1.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: sexti1 ; CHECK: r[[REG:[0-9]+]] = mux(p{{[0-3]}},#-1,#0) diff --git a/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll b/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll index a622d18ea4d5..99a0e0613b32 100644 --- a/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s -; RUN: llc -march=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/isel-extract-pred.ll b/llvm/test/CodeGen/Hexagon/isel-extract-pred.ll index d05686524023..94b1d372367f 100644 --- a/llvm/test/CodeGen/Hexagon/isel-extract-pred.ll +++ b/llvm/test/CodeGen/Hexagon/isel-extract-pred.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define i32 @f0(ptr %a0, i32 %a1) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll b/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll index af479fde7ce3..72a62151371f 100644 --- a/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll +++ b/llvm/test/CodeGen/Hexagon/isel-global-offset-alignment.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This should compile without errors, and the offsets with respect to the ; beginning of the global "array" don't need to be multiples of 8. diff --git a/llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll b/llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll index 1fdf8a5fb0ea..8346a1a69ec1 100644 --- a/llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll +++ b/llvm/test/CodeGen/Hexagon/isel-hvx-pred-bitcast-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that the resulting register pair has the registers in the right order. diff --git a/llvm/test/CodeGen/Hexagon/isel-i1arg-crash.ll b/llvm/test/CodeGen/Hexagon/isel-i1arg-crash.ll index 7e8bd9e93b27..310440a9ac6f 100644 --- a/llvm/test/CodeGen/Hexagon/isel-i1arg-crash.ll +++ b/llvm/test/CodeGen/Hexagon/isel-i1arg-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug-only=isel < %s +; RUN: llc -mtriple=hexagon -debug-only=isel < %s ; REQUIRES: asserts define void @g(i1 %cond) { diff --git a/llvm/test/CodeGen/Hexagon/isel-insert-pred.ll b/llvm/test/CodeGen/Hexagon/isel-insert-pred.ll index 2fa4a8b7bf9f..4b0d605a4131 100644 --- a/llvm/test/CodeGen/Hexagon/isel-insert-pred.ll +++ b/llvm/test/CodeGen/Hexagon/isel-insert-pred.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, i32 %a1, i32 %a2) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll b/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll index 2eecfa9f47f1..e1b848c0d247 100644 --- a/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define i64 @f0(ptr %a0, <8 x i8> %a1) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll b/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll index d175d8dd295c..206a1335efb2 100644 --- a/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll +++ b/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; min diff --git a/llvm/test/CodeGen/Hexagon/isel-op-zext-i1.ll b/llvm/test/CodeGen/Hexagon/isel-op-zext-i1.ll index d77d0929e21f..af888fcffb0c 100644 --- a/llvm/test/CodeGen/Hexagon/isel-op-zext-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-op-zext-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s ; In the IR, the i1 value is zero-extended first, then passed to add. ; Check that in the final code, the mux happens after the add. diff --git a/llvm/test/CodeGen/Hexagon/isel-prefer.ll b/llvm/test/CodeGen/Hexagon/isel-prefer.ll index 3d5c8fb54ade..fbba17084121 100644 --- a/llvm/test/CodeGen/Hexagon/isel-prefer.ll +++ b/llvm/test/CodeGen/Hexagon/isel-prefer.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @data1 = external global [2 x [31 x i8]], align 8 @data2 = external global [2 x [91 x i8]], align 8 diff --git a/llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll b/llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll index b1c6d7157e39..57ca10604c9a 100644 --- a/llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll +++ b/llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to fail: ; LLVM ERROR: Cannot select: t54: v4i8 = select t50, t53, t52 diff --git a/llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll b/llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll index 008d976de8ab..5055a4ec0396 100644 --- a/llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-setcc-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; Check that this compiles successfully. ; CHECK: if (p0) diff --git a/llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll b/llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll index 1798654975e5..d1266bdec0a9 100644 --- a/llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll +++ b/llvm/test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we scalarize the comparison. This testcase used to loop forever ; due to the repeated split-widen operations in legalizing SETCC. diff --git a/llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll b/llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll index c982b93162ea..765e85390a08 100644 --- a/llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll +++ b/llvm/test/CodeGen/Hexagon/isel-simplify-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s ; This used to crash in SimplifyDemandedBits due to a type mismatch ; caused by a missing bitcast in vectorizing mul. diff --git a/llvm/test/CodeGen/Hexagon/isel-splat-vector-crash.ll b/llvm/test/CodeGen/Hexagon/isel-splat-vector-crash.ll index d6469d365696..af5e36291ae9 100644 --- a/llvm/test/CodeGen/Hexagon/isel-splat-vector-crash.ll +++ b/llvm/test/CodeGen/Hexagon/isel-splat-vector-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: vmemu diff --git a/llvm/test/CodeGen/Hexagon/isel-splat-vector-dag-crash.ll b/llvm/test/CodeGen/Hexagon/isel-splat-vector-dag-crash.ll index ab659990644f..2f88e5a7d945 100644 --- a/llvm/test/CodeGen/Hexagon/isel-splat-vector-dag-crash.ll +++ b/llvm/test/CodeGen/Hexagon/isel-splat-vector-dag-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to crash because SelectionDAG::isSplatValue did not set UndefElts ; for ISD::SPLAT_VECTOR. diff --git a/llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll b/llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll index 9bd5bde81d94..a8692a97b5d6 100644 --- a/llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll +++ b/llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <4 x i8> @fred() #0 { ; CHECK-LABEL: fred: diff --git a/llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll b/llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll index c4a23ab45861..0cfcd2b629d6 100644 --- a/llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-store-rr-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/isel-uaddo-1-i64.ll b/llvm/test/CodeGen/Hexagon/isel-uaddo-1-i64.ll index 753fe9a255de..fea6461a06b0 100644 --- a/llvm/test/CodeGen/Hexagon/isel-uaddo-1-i64.ll +++ b/llvm/test/CodeGen/Hexagon/isel-uaddo-1-i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this doesn't crash. ; CHECK: add{{.*}}:carry diff --git a/llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll b/llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll index b9c5e3bac8d8..ae56160577b3 100644 --- a/llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that a hardware loop is generated. ; CHECK: loop0 diff --git a/llvm/test/CodeGen/Hexagon/isel-v3i16.ll b/llvm/test/CodeGen/Hexagon/isel-v3i16.ll index 8c3565a37cf7..c7ad6adca7a0 100644 --- a/llvm/test/CodeGen/Hexagon/isel-v3i16.ll +++ b/llvm/test/CodeGen/Hexagon/isel-v3i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for a successful compilation. ; CHECK: callr diff --git a/llvm/test/CodeGen/Hexagon/isel-vacopy.ll b/llvm/test/CodeGen/Hexagon/isel-vacopy.ll index 81458ac13ef9..ec94f938a801 100644 --- a/llvm/test/CodeGen/Hexagon/isel-vacopy.ll +++ b/llvm/test/CodeGen/Hexagon/isel-vacopy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for successful compilation ; CHECK: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll b/llvm/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll index bf176d042c12..1ebb6f718fab 100644 --- a/llvm/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll +++ b/llvm/test/CodeGen/Hexagon/isel-vlsr-v2i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to crash with "cannot select" error. ; CHECK: vlsrh(r1:0,#4) diff --git a/llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll b/llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll index d895f129efcd..e8e4e9a560f4 100644 --- a/llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll +++ b/llvm/test/CodeGen/Hexagon/isel-vselect-v4i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This used to crash with "cannot select (v4i8 vselect ...)" ; CHECK: vtrunehb diff --git a/llvm/test/CodeGen/Hexagon/isel-zext-vNi1.ll b/llvm/test/CodeGen/Hexagon/isel-zext-vNi1.ll index f86263534f8c..f247b3091655 100644 --- a/llvm/test/CodeGen/Hexagon/isel-zext-vNi1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-zext-vNi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hsdr < %s | FileCheck %s ; Check that zero-extends of short boolean vectors are done correctly. ; These are not the only possible instruction sequences, so if something diff --git a/llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll index 7d589d21ed94..3df334823bad 100644 --- a/llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1, ptr %a2) { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll index 1f3df1122c64..a3d8c3d9a6db 100644 --- a/llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1, ptr %a2) { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll index e5c0abff4ce4..6c236a68d477 100644 --- a/llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1, ptr %a2) { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll index 144bde4d5898..75a32085c2ce 100644 --- a/llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1, ptr %a2) { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll b/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll index cfaf6fb0b57e..f56ea8757b87 100644 --- a/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @array8 = global [128 x i8] zeroinitializer @array32 = global [128 x i32] zeroinitializer diff --git a/llvm/test/CodeGen/Hexagon/isel/logical.ll b/llvm/test/CodeGen/Hexagon/isel/logical.ll index 680a8212b007..7f9c178c4241 100644 --- a/llvm/test/CodeGen/Hexagon/isel/logical.ll +++ b/llvm/test/CodeGen/Hexagon/isel/logical.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s declare i32 @llvm.hexagon.S2.tstbit.i(i32, i32 immarg) #0 diff --git a/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll b/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll index 3364a3c6dbe2..463e34da7a5c 100644 --- a/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll +++ b/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <4 x i8> @f0(<4 x i8> %a0, <4 x i8> %a1) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel/select-i1.ll b/llvm/test/CodeGen/Hexagon/isel/select-i1.ll index d480b7a16836..193b354bc5a8 100644 --- a/llvm/test/CodeGen/Hexagon/isel/select-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/select-i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(ptr %a0, ptr %a1, ptr %a2, ptr %a3) { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel/select-vec.ll b/llvm/test/CodeGen/Hexagon/isel/select-vec.ll index 7073c1a2a609..128dd5271a22 100644 --- a/llvm/test/CodeGen/Hexagon/isel/select-vec.ll +++ b/llvm/test/CodeGen/Hexagon/isel/select-vec.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s define <4 x i8> @f0(<4 x i8> %a0, <4 x i8> %a1, i32 %a2) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll b/llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll index 1394d49587de..1090b64fcad5 100644 --- a/llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define void @f0(<2 x i32> %a0, ptr %a1) { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/jump-prob.ll b/llvm/test/CodeGen/Hexagon/jump-prob.ll index 9910c9a6a3bb..bab31cf663f9 100644 --- a/llvm/test/CodeGen/Hexagon/jump-prob.ll +++ b/llvm/test/CodeGen/Hexagon/jump-prob.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: { ; CHECK: jump .LBB0_ diff --git a/llvm/test/CodeGen/Hexagon/jump-table-g0.ll b/llvm/test/CodeGen/Hexagon/jump-table-g0.ll index 9996f5223595..178867655e8b 100644 --- a/llvm/test/CodeGen/Hexagon/jump-table-g0.ll +++ b/llvm/test/CodeGen/Hexagon/jump-table-g0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/jump-table-isel.ll b/llvm/test/CodeGen/Hexagon/jump-table-isel.ll index 53755f80f4f5..bc85bd44aee0 100644 --- a/llvm/test/CodeGen/Hexagon/jump-table-isel.ll +++ b/llvm/test/CodeGen/Hexagon/jump-table-isel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-emit-jump-tables=0 < %s +; RUN: llc -mtriple=hexagon -hexagon-emit-jump-tables=0 < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/large-number-of-preds.ll b/llvm/test/CodeGen/Hexagon/large-number-of-preds.ll index c380576cd63e..495ebb2885f2 100644 --- a/llvm/test/CodeGen/Hexagon/large-number-of-preds.ll +++ b/llvm/test/CodeGen/Hexagon/large-number-of-preds.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s +; RUN: llc -O3 -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/late-pred.ll b/llvm/test/CodeGen/Hexagon/late-pred.ll index 0aba97d8440b..824de221b337 100644 --- a/llvm/test/CodeGen/Hexagon/late-pred.ll +++ b/llvm/test/CodeGen/Hexagon/late-pred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This generates A4_addp_c, which cannot be used as a dot-new predicate ; producer (resulting in a crash). diff --git a/llvm/test/CodeGen/Hexagon/late_instr.ll b/llvm/test/CodeGen/Hexagon/late_instr.ll index eeeea4488634..93e5a7dba4b3 100644 --- a/llvm/test/CodeGen/Hexagon/late_instr.ll +++ b/llvm/test/CodeGen/Hexagon/late_instr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hsdr < %s | FileCheck %s ; Check if instruction vandqrt.acc and its predecessor are scheduled in consecutive packets. ; CHECK: or(q{{[0-3]+}},q{{[0-3]+}}) diff --git a/llvm/test/CodeGen/Hexagon/lcomm.ll b/llvm/test/CodeGen/Hexagon/lcomm.ll index 558aadde7e1a..c82891351da3 100644 --- a/llvm/test/CodeGen/Hexagon/lcomm.ll +++ b/llvm/test/CodeGen/Hexagon/lcomm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: .lcomm g0,4,4,4 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/ldst_vector_offset.ll b/llvm/test/CodeGen/Hexagon/ldst_vector_offset.ll index 15695e835016..2f32005b9736 100644 --- a/llvm/test/CodeGen/Hexagon/ldst_vector_offset.ll +++ b/llvm/test/CodeGen/Hexagon/ldst_vector_offset.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -O3 -march=hexagon < %s -o /dev/null +; RUN: llc -O3 -mtriple=hexagon < %s -o /dev/null ; Make sure that this doesn't crash. ; This test validates that the compiler would not assert when analyzing the ; offset of V6_vS32b_pred_ai instruction diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-add-pristines.mir b/llvm/test/CodeGen/Hexagon/livephysregs-add-pristines.mir index 86ed9fcb41b4..03c5b232801a 100644 --- a/llvm/test/CodeGen/Hexagon/livephysregs-add-pristines.mir +++ b/llvm/test/CodeGen/Hexagon/livephysregs-add-pristines.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass if-converter -o - %s -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass if-converter -o - %s -verify-machineinstrs | FileCheck %s # The register r23 is live on the path bb.0->bb.2->bb.3. Make sure we add # an implicit use of r23 to the predicated redefinition: diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir index cea9b72e7d58..f37af9ad000c 100644 --- a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir +++ b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass if-converter -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass if-converter -verify-machineinstrs -o - %s | FileCheck %s # CHECK-LABEL: name: foo # CHECK: $p0 = C2_cmpeqi $r16, 0 diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir index a1f988d0b05f..2db45d95a77f 100644 --- a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir +++ b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks2.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -verify-machineinstrs -run-pass branch-folder -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -verify-machineinstrs -run-pass branch-folder -o - %s | FileCheck %s # CHECK-LABEL: name: fred diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir b/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir index 52213070f535..4fa77a0b221b 100644 --- a/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir +++ b/llvm/test/CodeGen/Hexagon/livephysregs-regmask-clobber.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -verify-machineinstrs -run-pass prologepilog -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -verify-machineinstrs -run-pass prologepilog -o - %s | FileCheck %s # The PS_vstorerw_ai of W0 would normally expand into stores of V0 and V1, # but both are clobbered by the regmask. Only V0 is re-defined before the diff --git a/llvm/test/CodeGen/Hexagon/load-abs.ll b/llvm/test/CodeGen/Hexagon/load-abs.ll index 975f98220528..1909c04b54da 100644 --- a/llvm/test/CodeGen/Hexagon/load-abs.ll +++ b/llvm/test/CodeGen/Hexagon/load-abs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s ; Check that absolute loads are generated for 64-bit target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/load-const-extend-opt.ll b/llvm/test/CodeGen/Hexagon/load-const-extend-opt.ll index 6f9e83c23ab3..8ac522590635 100644 --- a/llvm/test/CodeGen/Hexagon/load-const-extend-opt.ll +++ b/llvm/test/CodeGen/Hexagon/load-const-extend-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s ; This test checks the case if there are more than 2 uses of a constan address, move the ; value in to a register and replace all instances of constant with the register. ; The GenMemAbsolute pass generates a absolute-set instruction if there are more diff --git a/llvm/test/CodeGen/Hexagon/load-widen.ll b/llvm/test/CodeGen/Hexagon/load-widen.ll index 6fe47a57b89f..8e84e05adbc1 100644 --- a/llvm/test/CodeGen/Hexagon/load-widen.ll +++ b/llvm/test/CodeGen/Hexagon/load-widen.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s -; RUN: llc -march=hexagon -disable-load-widen < %s | FileCheck %s --check-prefix=CHECK-DISABLE +; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-load-widen < %s | FileCheck %s --check-prefix=CHECK-DISABLE %struct.node32 = type { ptr, ptr } diff --git a/llvm/test/CodeGen/Hexagon/loadi1-G0.ll b/llvm/test/CodeGen/Hexagon/loadi1-G0.ll index c3c0983a1e58..e6869dd12fdc 100644 --- a/llvm/test/CodeGen/Hexagon/loadi1-G0.ll +++ b/llvm/test/CodeGen/Hexagon/loadi1-G0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -hexagon-small-data-threshold=0 < %s | FileCheck %s target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll b/llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll index 2dd62d67232f..abe1ad84d20c 100644 --- a/llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll +++ b/llvm/test/CodeGen/Hexagon/loadi1-v4-G0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/loadi1-v4.ll b/llvm/test/CodeGen/Hexagon/loadi1-v4.ll index f99b7e1625a3..403fa3ec6112 100644 --- a/llvm/test/CodeGen/Hexagon/loadi1-v4.ll +++ b/llvm/test/CodeGen/Hexagon/loadi1-v4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/loadi1.ll b/llvm/test/CodeGen/Hexagon/loadi1.ll index 9914a498b534..adc27a1a4d50 100644 --- a/llvm/test/CodeGen/Hexagon/loadi1.ll +++ b/llvm/test/CodeGen/Hexagon/loadi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/local-exec.ll b/llvm/test/CodeGen/Hexagon/local-exec.ll index b57fb6c5bf85..d5c6a9bc65a9 100644 --- a/llvm/test/CodeGen/Hexagon/local-exec.ll +++ b/llvm/test/CodeGen/Hexagon/local-exec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/loop-balign.ll b/llvm/test/CodeGen/Hexagon/loop-balign.ll index 9d1f42a4b14b..78285f6d1ae6 100644 --- a/llvm/test/CodeGen/Hexagon/loop-balign.ll +++ b/llvm/test/CodeGen/Hexagon/loop-balign.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s -check-prefix=BALIGN +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s -check-prefix=BALIGN ; BALIGN: .p2align{{.*}}5 ; The test for checking the alignment of 'for.body4.for.body4_crit_edge' basic block diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll index 74c02d63d54d..b5639449d113 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll @@ -1,5 +1,5 @@ -; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s -; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s +; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s +; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s ; CHECK-LABEL: define void @fred ; Check that this test does not crash. diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll index 94b0c96c3d51..07536c7f4a50 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll @@ -1,5 +1,5 @@ -; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s -; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s +; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s +; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s ; ; The number of nested selects caused the simplification loop to take ; more than the maximum number of iterations. This caused the compiler diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll index 08e5f3ab1f1f..836a0e110b9e 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll @@ -2,8 +2,8 @@ ; the Hexagon loop idiom recognition runs. This is to check that we still ; get this opportunity regardless of what happens before. -; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s -; RUN: opt -passes='default<O2>' -march=hexagon -S < %s | FileCheck %s +; RUN: opt -O2 -S < %s | FileCheck %s +; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s target triple = "hexagon" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll index a00b1d5876ba..a0fcba15c35d 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll @@ -1,5 +1,5 @@ -; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s -; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s +; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s +; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s ; REQUIRES: asserts ; ; Check for sane output, this used to crash. diff --git a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll index 76e82688e544..5bac744ebf3d 100644 --- a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll +++ b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-loop-prefetch < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-loop-prefetch < %s | FileCheck %s ; CHECK: dcfetch target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/loop-rotate-bug.ll b/llvm/test/CodeGen/Hexagon/loop-rotate-bug.ll index 6a2aa76bc2ba..986dc7aebcfa 100644 --- a/llvm/test/CodeGen/Hexagon/loop-rotate-bug.ll +++ b/llvm/test/CodeGen/Hexagon/loop-rotate-bug.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: cmp.eq ; CHECK: cmp.eq diff --git a/llvm/test/CodeGen/Hexagon/loop-rotate-liveins.ll b/llvm/test/CodeGen/Hexagon/loop-rotate-liveins.ll index cdca09711357..462172c11385 100644 --- a/llvm/test/CodeGen/Hexagon/loop-rotate-liveins.ll +++ b/llvm/test/CodeGen/Hexagon/loop-rotate-liveins.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s ; ; Make sure that this testcase passes the verifier. ; CHECK: call f1 diff --git a/llvm/test/CodeGen/Hexagon/loop_align_count.ll b/llvm/test/CodeGen/Hexagon/loop_align_count.ll index 1f89d8e39495..fb70179a8b09 100644 --- a/llvm/test/CodeGen/Hexagon/loop_align_count.ll +++ b/llvm/test/CodeGen/Hexagon/loop_align_count.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv73 -O2 -mattr=+hvxv73,hvx-length64b \ +; RUN: llc -mtriple=hexagon -mcpu=hexagonv73 -O2 -mattr=+hvxv73,hvx-length64b \ ; RUN: -debug-only=hexagon-loop-align 2>&1 < %s | FileCheck %s ; Validate that there are 4 bundles in the loop. ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/loop_align_count.mir b/llvm/test/CodeGen/Hexagon/loop_align_count.mir index 6955b525e1ad..83530c00b304 100644 --- a/llvm/test/CodeGen/Hexagon/loop_align_count.mir +++ b/llvm/test/CodeGen/Hexagon/loop_align_count.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -O3 -run-pass hexagon-loop-align -o - %s\ +# RUN: llc -mtriple=hexagon -O3 -run-pass hexagon-loop-align -o - %s\ # RUN: -debug-only=hexagon-loop-align -verify-machineinstrs 2>&1 | FileCheck %s # REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/loop_correctness.ll b/llvm/test/CodeGen/Hexagon/loop_correctness.ll index 35e7c90d1bb7..08e563942fd2 100644 --- a/llvm/test/CodeGen/Hexagon/loop_correctness.ll +++ b/llvm/test/CodeGen/Hexagon/loop_correctness.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -O3 -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-instsimplify=0 < %s | FileCheck %s define void @f0(ptr nocapture %a0, i32 %a1, i32 %a2) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll index 9d9435ad4efa..e9084756c815 100644 --- a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll +++ b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test checks if we custom lower extract_subvector. If we cannot ; custom lower extract_subvector this test makes the compiler crash. diff --git a/llvm/test/CodeGen/Hexagon/lower-i1.ll b/llvm/test/CodeGen/Hexagon/lower-i1.ll index 6c8fa8ce1532..088e518f46d2 100644 --- a/llvm/test/CodeGen/Hexagon/lower-i1.ll +++ b/llvm/test/CodeGen/Hexagon/lower-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug < %s +; RUN: llc -mtriple=hexagon -debug < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/lsr-post-inc-cross-use-offsets.ll b/llvm/test/CodeGen/Hexagon/lsr-post-inc-cross-use-offsets.ll index 472c96d2c85f..84b0ff01fd58 100644 --- a/llvm/test/CodeGen/Hexagon/lsr-post-inc-cross-use-offsets.ll +++ b/llvm/test/CodeGen/Hexagon/lsr-post-inc-cross-use-offsets.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; CHECK: loop0(.[[BLOCK:LBB0_[0-9]+]] ; CHECK: .[[BLOCK]]: diff --git a/llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll b/llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll index 0e6aadf092db..94f6c5907dab 100644 --- a/llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll +++ b/llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; Test to ensure LSR does not optimize out addrec of the outerloop. ; This will help to generate post-increment instructions, otherwise ; it end up an as extra reg+reg add inside the loop. diff --git a/llvm/test/CodeGen/Hexagon/machine-cp-clobbers.mir b/llvm/test/CodeGen/Hexagon/machine-cp-clobbers.mir index 736eccc217ec..c12303ae48bb 100644 --- a/llvm/test/CodeGen/Hexagon/machine-cp-clobbers.mir +++ b/llvm/test/CodeGen/Hexagon/machine-cp-clobbers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -o - %s -run-pass=machine-cp | FileCheck %s +# RUN: llc -mtriple=hexagon -o - %s -run-pass=machine-cp | FileCheck %s --- name: dont_propagate_past_lower_subreg_kill diff --git a/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir b/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir index 45621d98da3e..f994493def0c 100644 --- a/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir +++ b/llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass machine-sink -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass machine-sink -o - %s | FileCheck %s # Test that MachineSink does not sink F2_conv_w2sf. # CHECK: name:{{.*}} main diff --git a/llvm/test/CodeGen/Hexagon/machine-sink.ll b/llvm/test/CodeGen/Hexagon/machine-sink.ll index 674c2528e4b6..739ecc445664 100644 --- a/llvm/test/CodeGen/Hexagon/machine-sink.ll +++ b/llvm/test/CodeGen/Hexagon/machine-sink.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -machine-sink-split < %s +; RUN: llc -mtriple=hexagon -machine-sink-split < %s ; REQUIRES: asserts ; MachineSink should not sink an MI which is used in a non-phi instruction ; in an MBB with multiple predecessors. diff --git a/llvm/test/CodeGen/Hexagon/macint.ll b/llvm/test/CodeGen/Hexagon/macint.ll index 0a0508e74747..9b79c274c01c 100644 --- a/llvm/test/CodeGen/Hexagon/macint.ll +++ b/llvm/test/CodeGen/Hexagon/macint.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate integer multiply accumulate. ; CHECK: r{{[0-9]+}} {{\+|\-}}= mpyi(r{{[0-9]+}}, diff --git a/llvm/test/CodeGen/Hexagon/maddsubu.ll b/llvm/test/CodeGen/Hexagon/maddsubu.ll index 85f2a2449eed..8fbd1c9ab0bd 100644 --- a/llvm/test/CodeGen/Hexagon/maddsubu.ll +++ b/llvm/test/CodeGen/Hexagon/maddsubu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we generate 64-bit mutiply accumulate/subtract. diff --git a/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll b/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll index 03dd0b8bbf5a..338efb5e01a1 100644 --- a/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll +++ b/llvm/test/CodeGen/Hexagon/mapped_intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s ; REQUIRES: asserts ; This test validates that ISel picks the correct equivalent of below mentioned intrinsics diff --git a/llvm/test/CodeGen/Hexagon/mask-instr.ll b/llvm/test/CodeGen/Hexagon/mask-instr.ll index ab60a6fcade7..40e18043670e 100644 --- a/llvm/test/CodeGen/Hexagon/mask-instr.ll +++ b/llvm/test/CodeGen/Hexagon/mask-instr.ll @@ -1,5 +1,5 @@ ; Enable Utlilize mask instruction pass only on v66 and above. -; RUN: llc -mv60 -march=hexagon < %s -o /dev/null +; RUN: llc -mv60 -mtriple=hexagon < %s -o /dev/null target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/maxd.ll b/llvm/test/CodeGen/Hexagon/maxd.ll index 7f237fd54e7a..5984920dc693 100644 --- a/llvm/test/CodeGen/Hexagon/maxd.ll +++ b/llvm/test/CodeGen/Hexagon/maxd.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: max define i64 @f(i64 %src, i64 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/maxh.ll b/llvm/test/CodeGen/Hexagon/maxh.ll index 79b5e922c1bb..7e94be4bad9a 100644 --- a/llvm/test/CodeGen/Hexagon/maxh.ll +++ b/llvm/test/CodeGen/Hexagon/maxh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; The result of max(half-word, half-word) is also half-word. ; Check that we are not producing a sign extend after the max. ; CHECK-NOT: sxth diff --git a/llvm/test/CodeGen/Hexagon/maxud.ll b/llvm/test/CodeGen/Hexagon/maxud.ll index eca4faee602c..01d1ed2987c9 100644 --- a/llvm/test/CodeGen/Hexagon/maxud.ll +++ b/llvm/test/CodeGen/Hexagon/maxud.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: maxu define i64 @f(i64 %src, i64 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/maxuw.ll b/llvm/test/CodeGen/Hexagon/maxuw.ll index 0dba1f5acdef..6ab204c35d7e 100644 --- a/llvm/test/CodeGen/Hexagon/maxuw.ll +++ b/llvm/test/CodeGen/Hexagon/maxuw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: maxu define i32 @f(i32 %src, i32 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/maxw.ll b/llvm/test/CodeGen/Hexagon/maxw.ll index e66ca958806f..cafa9d4a7bc8 100644 --- a/llvm/test/CodeGen/Hexagon/maxw.ll +++ b/llvm/test/CodeGen/Hexagon/maxw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: max define i32 @f(i32 %src, i32 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/mem-load-circ.ll b/llvm/test/CodeGen/Hexagon/mem-load-circ.ll index d716b3b6e33f..18a7b917aae9 100644 --- a/llvm/test/CodeGen/Hexagon/mem-load-circ.ll +++ b/llvm/test/CodeGen/Hexagon/mem-load-circ.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: r{{[1-9]+:[0-9]+}} = memd(r{{[0-9]*}}++#{{[0-9]}}:circ(m{{[01]}})) diff --git a/llvm/test/CodeGen/Hexagon/mem-ops-sub.ll b/llvm/test/CodeGen/Hexagon/mem-ops-sub.ll index 2ef11624cc79..b55b7f4d98d1 100644 --- a/llvm/test/CodeGen/Hexagon/mem-ops-sub.ll +++ b/llvm/test/CodeGen/Hexagon/mem-ops-sub.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Test that we do not exceed #u5 in memops. ; CHECK-NOT: memb(r2+#0) -= #32 diff --git a/llvm/test/CodeGen/Hexagon/mem-ops-sub_01.ll b/llvm/test/CodeGen/Hexagon/mem-ops-sub_01.ll index 2c41c13128e2..0c8cb99dae4f 100644 --- a/llvm/test/CodeGen/Hexagon/mem-ops-sub_01.ll +++ b/llvm/test/CodeGen/Hexagon/mem-ops-sub_01.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Test that we do generate max #u5 in memops. ; CHECK: memb(r{{[0-9]+}}+#0) -= #31 diff --git a/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16.ll b/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16.ll index a5bc0668a4d6..35823b25bc90 100644 --- a/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16.ll +++ b/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Test that we do generate max #u5 in memops. ; CHECK: memh(r{{[0-9]+}}+#0) -= #31 diff --git a/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16_01.ll b/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16_01.ll index e156bcfc44f3..b35e4472d7f0 100644 --- a/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16_01.ll +++ b/llvm/test/CodeGen/Hexagon/mem-ops-sub_i16_01.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Test that we do not exceed #u5 in memops. ; CHECK-NOT: memh(r2+#0) -= #32 diff --git a/llvm/test/CodeGen/Hexagon/memcmp.ll b/llvm/test/CodeGen/Hexagon/memcmp.ll index 30cdeb649d6b..b743b2cdb254 100644 --- a/llvm/test/CodeGen/Hexagon/memcmp.ll +++ b/llvm/test/CodeGen/Hexagon/memcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: loop0 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll b/llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll index 136e41509b73..fe21f69d5290 100644 --- a/llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll +++ b/llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: __hexagon_memcpy_likely_aligned_min32bytes_mult8bytes target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" diff --git a/llvm/test/CodeGen/Hexagon/memcpy-memmove-inline.ll b/llvm/test/CodeGen/Hexagon/memcpy-memmove-inline.ll index e7d9498c3f48..420974444dae 100644 --- a/llvm/test/CodeGen/Hexagon/memcpy-memmove-inline.ll +++ b/llvm/test/CodeGen/Hexagon/memcpy-memmove-inline.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mno-pairing -mno-compound < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -mno-pairing -mno-compound < %s | FileCheck %s ; Test to see if we inline calls to memcpy/memmove when ; the array size is small. diff --git a/llvm/test/CodeGen/Hexagon/memop-bit18.ll b/llvm/test/CodeGen/Hexagon/memop-bit18.ll index ecc81d058caf..b2c1478931d8 100644 --- a/llvm/test/CodeGen/Hexagon/memop-bit18.ll +++ b/llvm/test/CodeGen/Hexagon/memop-bit18.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/memops-stack.ll b/llvm/test/CodeGen/Hexagon/memops-stack.ll index 6d9fbf73ee65..3ff23aeeab5e 100644 --- a/llvm/test/CodeGen/Hexagon/memops-stack.ll +++ b/llvm/test/CodeGen/Hexagon/memops-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/memops.ll b/llvm/test/CodeGen/Hexagon/memops.ll index 65ddf5167cbd..cd3e24489347 100644 --- a/llvm/test/CodeGen/Hexagon/memops.ll +++ b/llvm/test/CodeGen/Hexagon/memops.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Generate MemOps for V4 and above. define void @memop_unsigned_char_add5(ptr nocapture %p) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/memops1.ll b/llvm/test/CodeGen/Hexagon/memops1.ll index 822df680920d..409e14a00685 100644 --- a/llvm/test/CodeGen/Hexagon/memops1.ll +++ b/llvm/test/CodeGen/Hexagon/memops1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Generate MemOps for V4 and above. diff --git a/llvm/test/CodeGen/Hexagon/memops2.ll b/llvm/test/CodeGen/Hexagon/memops2.ll index 74a4ed546d3e..4cad3bb511e0 100644 --- a/llvm/test/CodeGen/Hexagon/memops2.ll +++ b/llvm/test/CodeGen/Hexagon/memops2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Generate MemOps for V4 and above. diff --git a/llvm/test/CodeGen/Hexagon/memops3.ll b/llvm/test/CodeGen/Hexagon/memops3.ll index 6861b9b8e969..6210d1dfd33c 100644 --- a/llvm/test/CodeGen/Hexagon/memops3.ll +++ b/llvm/test/CodeGen/Hexagon/memops3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Generate MemOps for V4 and above. diff --git a/llvm/test/CodeGen/Hexagon/memops_global.ll b/llvm/test/CodeGen/Hexagon/memops_global.ll index 66d0531a238f..af4282cf031b 100644 --- a/llvm/test/CodeGen/Hexagon/memops_global.ll +++ b/llvm/test/CodeGen/Hexagon/memops_global.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @g0 = common global i8 0, align 1 @g1 = common global i8 0, align 1 diff --git a/llvm/test/CodeGen/Hexagon/memset-inline.ll b/llvm/test/CodeGen/Hexagon/memset-inline.ll index 5118b0122619..61a6b21b4f26 100644 --- a/llvm/test/CodeGen/Hexagon/memset-inline.ll +++ b/llvm/test/CodeGen/Hexagon/memset-inline.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/mind.ll b/llvm/test/CodeGen/Hexagon/mind.ll index 610283d97e2b..5652baa1fac6 100644 --- a/llvm/test/CodeGen/Hexagon/mind.ll +++ b/llvm/test/CodeGen/Hexagon/mind.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: min define i64 @f(i64 %src, i64 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/minu-zext-16.ll b/llvm/test/CodeGen/Hexagon/minu-zext-16.ll index ea9329a657c5..f516d654203f 100644 --- a/llvm/test/CodeGen/Hexagon/minu-zext-16.ll +++ b/llvm/test/CodeGen/Hexagon/minu-zext-16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: minu define zeroext i16 @f(ptr noalias nocapture %src) nounwind readonly { diff --git a/llvm/test/CodeGen/Hexagon/minu-zext-8.ll b/llvm/test/CodeGen/Hexagon/minu-zext-8.ll index 7ebdbd8961cc..86c5456e7de3 100644 --- a/llvm/test/CodeGen/Hexagon/minu-zext-8.ll +++ b/llvm/test/CodeGen/Hexagon/minu-zext-8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: minu define zeroext i8 @f(ptr noalias nocapture %src) nounwind readonly { diff --git a/llvm/test/CodeGen/Hexagon/minud.ll b/llvm/test/CodeGen/Hexagon/minud.ll index 29e81005081a..09fbb6fb3234 100644 --- a/llvm/test/CodeGen/Hexagon/minud.ll +++ b/llvm/test/CodeGen/Hexagon/minud.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: minu define i64 @f(i64 %src, i64 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/minuw.ll b/llvm/test/CodeGen/Hexagon/minuw.ll index a88d1e116037..9621d41f3485 100644 --- a/llvm/test/CodeGen/Hexagon/minuw.ll +++ b/llvm/test/CodeGen/Hexagon/minuw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: minu define i32 @f(i32 %src, i32 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/minw.ll b/llvm/test/CodeGen/Hexagon/minw.ll index 5bfaae09c805..7b1e3bac0b7b 100644 --- a/llvm/test/CodeGen/Hexagon/minw.ll +++ b/llvm/test/CodeGen/Hexagon/minw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: min define i32 @f(i32 %src, i32 %maxval) nounwind readnone { diff --git a/llvm/test/CodeGen/Hexagon/mipi-double-small.ll b/llvm/test/CodeGen/Hexagon/mipi-double-small.ll index 8c67d46c47cd..667c043b40ff 100644 --- a/llvm/test/CodeGen/Hexagon/mipi-double-small.ll +++ b/llvm/test/CodeGen/Hexagon/mipi-double-small.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/misaligned-access.ll b/llvm/test/CodeGen/Hexagon/misaligned-access.ll index b2e6b2713600..f363d796a558 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned-access.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned-access.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Check that the mis-aligned load doesn't cause compiler to assert. @g0 = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll b/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll index 25a9f02e4f1d..ea772f61b1b2 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=hexagon < %s 2>&1 | FileCheck %s ; Check that the misaligned load is diagnosed. ; CHECK: remark: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-load.c:2:10. The instruction has been replaced with a trap. diff --git a/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll b/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll index 75d3a4ec6935..acf5b19e62cb 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=hexagon < %s 2>&1 | FileCheck %s ; Check that the misaligned store is diagnosed. ; CHECK: remark: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-store.c:2:10. The instruction has been replaced with a trap. diff --git a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll index a2dde20eb4ab..1a60b7ceaeca 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -debug-only=isel 2>&1 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -debug-only=isel 2>&1 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; REQUIRES: asserts ; DAGCombiner converts the two vector stores to a double vector store, diff --git a/llvm/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll b/llvm/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll index 379ee485296b..a28f6480a805 100644 --- a/llvm/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll +++ b/llvm/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Check that we no longer get this error: diff --git a/llvm/test/CodeGen/Hexagon/mnaci_v66.ll b/llvm/test/CodeGen/Hexagon/mnaci_v66.ll index 63f3788fe565..68bc13fa33db 100644 --- a/llvm/test/CodeGen/Hexagon/mnaci_v66.ll +++ b/llvm/test/CodeGen/Hexagon/mnaci_v66.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test validates the generation of v66 only instruction M2_mnaci ; CHECK: r{{[0-9]+}} -= mpyi(r{{[0-9]+}},r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/mpy.ll b/llvm/test/CodeGen/Hexagon/mpy.ll index 68d412fa1d0a..b52991328da0 100644 --- a/llvm/test/CodeGen/Hexagon/mpy.ll +++ b/llvm/test/CodeGen/Hexagon/mpy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: += mpyi define void @f0(i32 %a0, i32 %a1, i32 %a2) #0 { diff --git a/llvm/test/CodeGen/Hexagon/mpysin-imm.ll b/llvm/test/CodeGen/Hexagon/mpysin-imm.ll index acb7e3fbe427..b4f4cf6fa824 100644 --- a/llvm/test/CodeGen/Hexagon/mpysin-imm.ll +++ b/llvm/test/CodeGen/Hexagon/mpysin-imm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; M2_mpysin takes 8-bit unsigned immediates and is not extendable. ; CHECK-NOT: = -mpyi(r{{[0-9]*}},#1536) diff --git a/llvm/test/CodeGen/Hexagon/mul64-sext.ll b/llvm/test/CodeGen/Hexagon/mul64-sext.ll index b615c0a59629..128ae9f3021b 100644 --- a/llvm/test/CodeGen/Hexagon/mul64-sext.ll +++ b/llvm/test/CodeGen/Hexagon/mul64-sext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/mul64.ll b/llvm/test/CodeGen/Hexagon/mul64.ll index 1df6d3beac2a..0acc18b62f99 100644 --- a/llvm/test/CodeGen/Hexagon/mul64.ll +++ b/llvm/test/CodeGen/Hexagon/mul64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test checks for the generation of 64b mul instruction ; (dpmpyss_s0 and dpmpyuu_s0). diff --git a/llvm/test/CodeGen/Hexagon/mulh.ll b/llvm/test/CodeGen/Hexagon/mulh.ll index 013c69199cd0..5627c11c2940 100644 --- a/llvm/test/CodeGen/Hexagon/mulh.ll +++ b/llvm/test/CodeGen/Hexagon/mulh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/mulhs.ll b/llvm/test/CodeGen/Hexagon/mulhs.ll index 73ac4c788ad3..da0f0d5d785a 100644 --- a/llvm/test/CodeGen/Hexagon/mulhs.ll +++ b/llvm/test/CodeGen/Hexagon/mulhs.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s -; RUN: llc -march=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s ; CHECK: mpy ; CHECK-NOT: call diff --git a/llvm/test/CodeGen/Hexagon/multi-cycle.ll b/llvm/test/CodeGen/Hexagon/multi-cycle.ll index a3fc6f0c575e..c26316ebad50 100644 --- a/llvm/test/CodeGen/Hexagon/multi-cycle.ll +++ b/llvm/test/CodeGen/Hexagon/multi-cycle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h) ; CHECK: } diff --git a/llvm/test/CodeGen/Hexagon/mux-kill1.mir b/llvm/test/CodeGen/Hexagon/mux-kill1.mir index e258d870a27a..73c6935a5913 100644 --- a/llvm/test/CodeGen/Hexagon/mux-kill1.mir +++ b/llvm/test/CodeGen/Hexagon/mux-kill1.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s # CHECK: $r2 = C2_mux killed $p0, killed $r0, $r1 --- name: fred diff --git a/llvm/test/CodeGen/Hexagon/mux-kill2.mir b/llvm/test/CodeGen/Hexagon/mux-kill2.mir index 426b4a7d08b8..ce81b74daa8a 100644 --- a/llvm/test/CodeGen/Hexagon/mux-kill2.mir +++ b/llvm/test/CodeGen/Hexagon/mux-kill2.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - -verify-machineinstrs %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-gen-mux -o - -verify-machineinstrs %s | FileCheck %s # CHECK: $r1 = C2_muxri $p0, 123, $r0 # CHECK: $r2 = C2_muxir killed $p0, killed $r0, 321 --- diff --git a/llvm/test/CodeGen/Hexagon/mux-kill3.mir b/llvm/test/CodeGen/Hexagon/mux-kill3.mir index 9e74fb2df1b9..a28632f40abc 100644 --- a/llvm/test/CodeGen/Hexagon/mux-kill3.mir +++ b/llvm/test/CodeGen/Hexagon/mux-kill3.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s # Make sure this verifies correctly. # CHECK: PS_jmpret killed $r31, implicit-def $pc --- diff --git a/llvm/test/CodeGen/Hexagon/mux-undef.ll b/llvm/test/CodeGen/Hexagon/mux-undef.ll index 6b3d93ea49de..ba12db9961e4 100644 --- a/llvm/test/CodeGen/Hexagon/mux-undef.ll +++ b/llvm/test/CodeGen/Hexagon/mux-undef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; ; Make sure this test compiles successfully. ; CHECK: call foo diff --git a/llvm/test/CodeGen/Hexagon/muxii-bug.ll b/llvm/test/CodeGen/Hexagon/muxii-bug.ll index 7267efe9e2f2..bcaac900b6a0 100644 --- a/llvm/test/CodeGen/Hexagon/muxii-bug.ll +++ b/llvm/test/CodeGen/Hexagon/muxii-bug.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure "generate mux" pass does not optimize out the value "1908". ; CHECK-LABEL: foo diff --git a/llvm/test/CodeGen/Hexagon/muxii-crash.ll b/llvm/test/CodeGen/Hexagon/muxii-crash.ll index 32c71dc7c89e..0a104f142293 100644 --- a/llvm/test/CodeGen/Hexagon/muxii-crash.ll +++ b/llvm/test/CodeGen/Hexagon/muxii-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Make sure this doesn't crash. diff --git a/llvm/test/CodeGen/Hexagon/namedreg.ll b/llvm/test/CodeGen/Hexagon/namedreg.ll index a905332b2dee..cb8608009e7d 100644 --- a/llvm/test/CodeGen/Hexagon/namedreg.ll +++ b/llvm/test/CodeGen/Hexagon/namedreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+reserved-r19 -march=hexagon < %s | FileCheck %s +; RUN: llc -mattr=+reserved-r19 -mtriple=hexagon < %s | FileCheck %s define dso_local i32 @r19f() #0 { entry: %0 = call i32 @llvm.read_register.i32(metadata !0) diff --git a/llvm/test/CodeGen/Hexagon/nbench1.ll b/llvm/test/CodeGen/Hexagon/nbench1.ll index 66c046a68614..25a83db5717e 100644 --- a/llvm/test/CodeGen/Hexagon/nbench1.ll +++ b/llvm/test/CodeGen/Hexagon/nbench1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; if instruction being considered for addition to packet has higher latency, ; end existing packet and start a new one. diff --git a/llvm/test/CodeGen/Hexagon/neg.ll b/llvm/test/CodeGen/Hexagon/neg.ll index f430c130049f..54528ace7ef9 100644 --- a/llvm/test/CodeGen/Hexagon/neg.ll +++ b/llvm/test/CodeGen/Hexagon/neg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: r0 = sub(#0,r0) diff --git a/llvm/test/CodeGen/Hexagon/newify-crash.ll b/llvm/test/CodeGen/Hexagon/newify-crash.ll index 2454a38b0388..8be29d681135 100644 --- a/llvm/test/CodeGen/Hexagon/newify-crash.ll +++ b/llvm/test/CodeGen/Hexagon/newify-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that this testcase doesn't crash. ; CHECK: jump f0 diff --git a/llvm/test/CodeGen/Hexagon/newvalueSameReg.ll b/llvm/test/CodeGen/Hexagon/newvalueSameReg.ll index c8537c578c47..284e98013604 100644 --- a/llvm/test/CodeGen/Hexagon/newvalueSameReg.ll +++ b/llvm/test/CodeGen/Hexagon/newvalueSameReg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; ; Expand-condsets eliminates the "mux" instruction, which is what this ; testcase is checking. diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump-c4.mir b/llvm/test/CodeGen/Hexagon/newvaluejump-c4.mir index f432f049e9f8..4dd89df94c26 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump-c4.mir +++ b/llvm/test/CodeGen/Hexagon/newvaluejump-c4.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-nvj %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-nvj %s -o - | FileCheck %s --- # CHECK-LABEL: name: test0 diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump-float.mir b/llvm/test/CodeGen/Hexagon/newvaluejump-float.mir index 9cef4cd0da01..06c1197fc5a2 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump-float.mir +++ b/llvm/test/CodeGen/Hexagon/newvaluejump-float.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass=hexagon-nvj %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass=hexagon-nvj %s -o - | FileCheck %s # Check that we don't generate a new-value jump for a floating-point # instruction. diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll b/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll index 14ebdfde16eb..e3f36988f938 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; ; Check that this testcase compiles successfully and that a new-value jump ; has been created. diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump-kill2.mir b/llvm/test/CodeGen/Hexagon/newvaluejump-kill2.mir index 9dde98ffe476..e1b1d7571c62 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump-kill2.mir +++ b/llvm/test/CodeGen/Hexagon/newvaluejump-kill2.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-nvj -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-nvj -verify-machineinstrs %s -o - | FileCheck %s # CHECK: J4_cmpgtu_t_jumpnv_t killed $r3, killed $r1, %bb.1, implicit-def $pc --- diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump-postinc.ll b/llvm/test/CodeGen/Hexagon/newvaluejump-postinc.ll index 5eefac8b84dc..559b5c529dc7 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump-postinc.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump-postinc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-NOT: if {{.*}} cmp{{.*}}jump %s.0 = type opaque diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump-solo.mir b/llvm/test/CodeGen/Hexagon/newvaluejump-solo.mir index d1fc4eb1d50a..1076168be301 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump-solo.mir +++ b/llvm/test/CodeGen/Hexagon/newvaluejump-solo.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-nvj %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-nvj %s -o - | FileCheck %s # Check that there is no new-value jump: # CHECK-LABEL: name: fred diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump.ll b/llvm/test/CodeGen/Hexagon/newvaluejump.ll index 8e96a4afdbab..b640f6f121a4 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate new value jump. ; CHECK: if (cmp.eq(r{{[0-9]+}}.new,#0)) jump{{.}} diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump2.ll b/llvm/test/CodeGen/Hexagon/newvaluejump2.ll index 9dceea6917d1..b7f504b1a0b5 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump2.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \ +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \ ; RUN: | FileCheck %s ; Check that we generate new value jump, both registers, with one ; of the registers as new. diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll index 59a9b2461f0c..2f9ab72b8ff0 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -filetype=obj -o /dev/null < %s +; RUN: llc -mtriple=hexagon -filetype=obj -o /dev/null < %s ; REQUIRES: asserts ; This crashed in the MC code emitter, because a new-value branch was created diff --git a/llvm/test/CodeGen/Hexagon/newvaluestore.ll b/llvm/test/CodeGen/Hexagon/newvaluestore.ll index b3be23362ba0..b210347d2666 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluestore.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluestore.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate new value store. @i = global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/newvaluestore2.ll b/llvm/test/CodeGen/Hexagon/newvaluestore2.ll index 8e6c0530a4b0..eadcf42fea29 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluestore2.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluestore2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate new value stores. ; CHECK: r[[REG:[0-9]+]] = sfadd(r{{[0-9]+}},r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/no-falign-function-for-size.ll b/llvm/test/CodeGen/Hexagon/no-falign-function-for-size.ll index 0b5e4ddfd0ff..af0f906ff319 100644 --- a/llvm/test/CodeGen/Hexagon/no-falign-function-for-size.ll +++ b/llvm/test/CodeGen/Hexagon/no-falign-function-for-size.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Don't output falign for function entries when optimizing for size. ; CHECK-NOT: falign diff --git a/llvm/test/CodeGen/Hexagon/no-packets-gather.ll b/llvm/test/CodeGen/Hexagon/no-packets-gather.ll index 5def4ed40d7b..b83db38b6e7b 100644 --- a/llvm/test/CodeGen/Hexagon/no-packets-gather.ll +++ b/llvm/test/CodeGen/Hexagon/no-packets-gather.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr=+hvxv60,hvx-length64b,-packets < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv60,hvx-length64b,-packets < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/no-packets.ll b/llvm/test/CodeGen/Hexagon/no-packets.ll index 07198e4c7e62..866881c17601 100644 --- a/llvm/test/CodeGen/Hexagon/no-packets.ll +++ b/llvm/test/CodeGen/Hexagon/no-packets.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that there are no packets with two or more instructions, except ; for the endloop packet. diff --git a/llvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll b/llvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll index 8a5f5d2df47f..c5b561d07345 100644 --- a/llvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll +++ b/llvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Check that we don't generate .falign directives after function calls at O2. ; We need more than one basic block for this test because MachineBlockPlacement diff --git a/llvm/test/CodeGen/Hexagon/no_struct_element.ll b/llvm/test/CodeGen/Hexagon/no_struct_element.ll index add80f925242..366968358857 100644 --- a/llvm/test/CodeGen/Hexagon/no_struct_element.ll +++ b/llvm/test/CodeGen/Hexagon/no_struct_element.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; CHECK-NOT: 4294967295 diff --git a/llvm/test/CodeGen/Hexagon/noreturn-noepilog.ll b/llvm/test/CodeGen/Hexagon/noreturn-noepilog.ll index 14d5ca628d83..b4aeb4884bbd 100644 --- a/llvm/test/CodeGen/Hexagon/noreturn-noepilog.ll +++ b/llvm/test/CodeGen/Hexagon/noreturn-noepilog.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; ; Check that no epilogue is inserted after a noreturn call. diff --git a/llvm/test/CodeGen/Hexagon/noreturn-notail.ll b/llvm/test/CodeGen/Hexagon/noreturn-notail.ll index 4a684ad28c7b..af036adaa1b9 100644 --- a/llvm/test/CodeGen/Hexagon/noreturn-notail.ll +++ b/llvm/test/CodeGen/Hexagon/noreturn-notail.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that we are emitting a regular call instead of a tail call for a ; noreturn call in a function with a non-empty frame (to save instructions). diff --git a/llvm/test/CodeGen/Hexagon/not-op.ll b/llvm/test/CodeGen/Hexagon/not-op.ll index cd1d438e7dad..78b67e8e27fc 100644 --- a/llvm/test/CodeGen/Hexagon/not-op.ll +++ b/llvm/test/CodeGen/Hexagon/not-op.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = sub(#-1,r{{[0-9]+}}) define i32 @f0(i32 %a0) #0 { diff --git a/llvm/test/CodeGen/Hexagon/notcheap.ll b/llvm/test/CodeGen/Hexagon/notcheap.ll index 8a9f1df57268..9586ece95923 100644 --- a/llvm/test/CodeGen/Hexagon/notcheap.ll +++ b/llvm/test/CodeGen/Hexagon/notcheap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check if only one transfer immediate instruction is generated for init.end block. ; Since the transfer immediate of address operand is declared as not cheap, it ; should generate only one transfer immediate, rather than two of them. diff --git a/llvm/test/CodeGen/Hexagon/ntstbit.ll b/llvm/test/CodeGen/Hexagon/ntstbit.ll index 00a2dcfcf2f4..0c5e537a2dbe 100644 --- a/llvm/test/CodeGen/Hexagon/ntstbit.ll +++ b/llvm/test/CodeGen/Hexagon/ntstbit.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Function Attrs: nounwind define i32 @f0(i32 %a0, i32 %a1, i32 %a2) #0 { diff --git a/llvm/test/CodeGen/Hexagon/nv_store_vec.ll b/llvm/test/CodeGen/Hexagon/nv_store_vec.ll index 53a8bc09dd69..f9ea82bf58b3 100644 --- a/llvm/test/CodeGen/Hexagon/nv_store_vec.ll +++ b/llvm/test/CodeGen/Hexagon/nv_store_vec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that we generate new value stores in V60. diff --git a/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll b/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll index c51bd911bfff..b862ef78df41 100644 --- a/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll +++ b/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/opt-addr-mode.ll b/llvm/test/CodeGen/Hexagon/opt-addr-mode.ll index 2a88d88fa8db..7c496041f929 100644 --- a/llvm/test/CodeGen/Hexagon/opt-addr-mode.ll +++ b/llvm/test/CodeGen/Hexagon/opt-addr-mode.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt=0 -hexagon-amode-growth-limit=4 < %s | FileCheck %s --check-prefix=CHECK-AMODE +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt=0 -hexagon-amode-growth-limit=4 < %s | FileCheck %s --check-prefix=CHECK-AMODE ; CHECK-NO-AMODE: [[REG0:(r[0-9]+)]] = ##global_2 ; CHECK-NO-AMODE: memw([[REG0]]+{{.*}}<<#2) = diff --git a/llvm/test/CodeGen/Hexagon/opt-fneg.ll b/llvm/test/CodeGen/Hexagon/opt-fneg.ll index d874e71f44bf..85845452d727 100644 --- a/llvm/test/CodeGen/Hexagon/opt-fneg.ll +++ b/llvm/test/CodeGen/Hexagon/opt-fneg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Optimize fneg to togglebit in V5. define float @foo(float %x) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/opt-glob-addrs-000.ll b/llvm/test/CodeGen/Hexagon/opt-glob-addrs-000.ll index b8baa651e88f..98ab3f7e26cc 100644 --- a/llvm/test/CodeGen/Hexagon/opt-glob-addrs-000.ll +++ b/llvm/test/CodeGen/Hexagon/opt-glob-addrs-000.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-hexagon-misched < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-misched < %s | FileCheck %s target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/opt-glob-addrs-001.ll b/llvm/test/CodeGen/Hexagon/opt-glob-addrs-001.ll index c7d6b44a94d7..f01acb653ea1 100644 --- a/llvm/test/CodeGen/Hexagon/opt-glob-addrs-001.ll +++ b/llvm/test/CodeGen/Hexagon/opt-glob-addrs-001.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Ensure that the second use of ##grcolor doesn't get replaced with ; r26 which is an induction variable diff --git a/llvm/test/CodeGen/Hexagon/opt-glob-addrs-003.ll b/llvm/test/CodeGen/Hexagon/opt-glob-addrs-003.ll index d322fe9cd47f..2fef06620e1b 100644 --- a/llvm/test/CodeGen/Hexagon/opt-glob-addrs-003.ll +++ b/llvm/test/CodeGen/Hexagon/opt-glob-addrs-003.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s +; RUN: llc -mtriple=hexagon -O3 -verify-machineinstrs < %s ; REQUIRES: asserts ; Expect clean compilation. diff --git a/llvm/test/CodeGen/Hexagon/opt-sext-intrinsics.ll b/llvm/test/CodeGen/Hexagon/opt-sext-intrinsics.ll index 3a348908d355..1f2ddbce3404 100644 --- a/llvm/test/CodeGen/Hexagon/opt-sext-intrinsics.ll +++ b/llvm/test/CodeGen/Hexagon/opt-sext-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-NOT: sxth target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/opt-spill-volatile.ll b/llvm/test/CodeGen/Hexagon/opt-spill-volatile.ll index 48ac3fd5dab5..3428c8b35b76 100644 --- a/llvm/test/CodeGen/Hexagon/opt-spill-volatile.ll +++ b/llvm/test/CodeGen/Hexagon/opt-spill-volatile.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that the load/store to the volatile stack object has not been ; optimized away. diff --git a/llvm/test/CodeGen/Hexagon/optimize-mux.ll b/llvm/test/CodeGen/Hexagon/optimize-mux.ll index 6a8b4bcc82fc..68b8088e15d3 100644 --- a/llvm/test/CodeGen/Hexagon/optimize-mux.ll +++ b/llvm/test/CodeGen/Hexagon/optimize-mux.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=0 < %s | FileCheck %s --check-prefix=CHECK0 -; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s --check-prefix=CHECK4 +; RUN: llc -mtriple=hexagon -hexagon-gen-mux-threshold=0 < %s | FileCheck %s --check-prefix=CHECK0 +; RUN: llc -mtriple=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s --check-prefix=CHECK4 ; Generate mux with threshold = 0: ; CHECK0: [[R0:r[0-9]+]] = add(r0,#-48) diff --git a/llvm/test/CodeGen/Hexagon/order-stack-object.ll b/llvm/test/CodeGen/Hexagon/order-stack-object.ll index bdc16e928eae..920f95755ec5 100644 --- a/llvm/test/CodeGen/Hexagon/order-stack-object.ll +++ b/llvm/test/CodeGen/Hexagon/order-stack-object.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr=+hvxv68,+hvx-length128b < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+hvxv68,+hvx-length128b < %s | FileCheck %s ; Check that ordering objects on the stack from the largest to the smallest has ; decreased the space allocated on the stack by 512 Bytes. diff --git a/llvm/test/CodeGen/Hexagon/packed-store.ll b/llvm/test/CodeGen/Hexagon/packed-store.ll index 59bb2975770e..773e5a2d3c37 100644 --- a/llvm/test/CodeGen/Hexagon/packed-store.ll +++ b/llvm/test/CodeGen/Hexagon/packed-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Honor the alignment of a halfword on byte boundaries. ; CHECK-NOT: memh diff --git a/llvm/test/CodeGen/Hexagon/packetize-allocframe.ll b/llvm/test/CodeGen/Hexagon/packetize-allocframe.ll index e0d860271256..5ae3683c7aa0 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-allocframe.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-allocframe.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; The purpose of this test is to make sure that the packetizer is ignoring ; CFI instructions while forming packet for allocframe. Refer to 7d7d99622 diff --git a/llvm/test/CodeGen/Hexagon/packetize-call-r29.ll b/llvm/test/CodeGen/Hexagon/packetize-call-r29.ll index dab2df75ab88..f12eed3ed1b1 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-call-r29.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-call-r29.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that the assignment to r29 does not occur in the same packet as the call. diff --git a/llvm/test/CodeGen/Hexagon/packetize-cfi-location.ll b/llvm/test/CodeGen/Hexagon/packetize-cfi-location.ll index 5188667bfa4b..09c66d1a7a70 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-cfi-location.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-cfi-location.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" %type.0 = type { i32, ptr, i32, i32, i32 } diff --git a/llvm/test/CodeGen/Hexagon/packetize-dccleana.mir b/llvm/test/CodeGen/Hexagon/packetize-dccleana.mir index 16f58440d607..d6ddc072cb92 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-dccleana.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-dccleana.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass=hexagon-packetizer -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass=hexagon-packetizer -o - %s | FileCheck %s # Make sure that the load is not packetized together with the dccleana. # CHECK-NOT: BUNDLE diff --git a/llvm/test/CodeGen/Hexagon/packetize-debug-loc.mir b/llvm/test/CodeGen/Hexagon/packetize-debug-loc.mir index f86fb05ac670..77236f56a897 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-debug-loc.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-debug-loc.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s ############################################################################## # This test case is not really hexagon specific, but we use hexagon to get diff --git a/llvm/test/CodeGen/Hexagon/packetize-frame-setup-destroy.mir b/llvm/test/CodeGen/Hexagon/packetize-frame-setup-destroy.mir index 249907a49e45..4f61c8f563db 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-frame-setup-destroy.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-frame-setup-destroy.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s ############################################################################## # This test case is not really hexagon specific, but we use hexagon to get diff --git a/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll b/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll index 6e84602fb7ea..d6b64a5c22e7 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-impdef-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s ; REQUIRES: asserts ; Test that the compiler doesn't assert because IMPLICIT_DEF instructions are diff --git a/llvm/test/CodeGen/Hexagon/packetize-impdef.ll b/llvm/test/CodeGen/Hexagon/packetize-impdef.ll index c9c1e555ab7f..a36821a73761 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-impdef.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-impdef.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; ; Check that IMPLICIT_DEFs are packetized correctly diff --git a/llvm/test/CodeGen/Hexagon/packetize-l2fetch.ll b/llvm/test/CodeGen/Hexagon/packetize-l2fetch.ll index 77d8351b2eed..51c03393b5fa 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-l2fetch.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-l2fetch.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this testcase compiles successfully. ; Because l2fetch has mayLoad/mayStore flags on it, the packetizer diff --git a/llvm/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir b/llvm/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir index 815627ab1d4c..e9a13683ba09 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-load-store-aliasing.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -mcpu=hexagonv60 -run-pass hexagon-packetizer %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -run-pass hexagon-packetizer %s -o - | FileCheck %s # Check that a store can be packetized with a load that happens later # if these instructions are not aliased (the load will actually execute diff --git a/llvm/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir b/llvm/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir index 9f0bbcb36fe4..9fc8a267f15e 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-nvj-no-prune.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s # Make sure that the new-value jump is packetized with the producer. In this # case, the loads cold be packetized together (with updating the offset in diff --git a/llvm/test/CodeGen/Hexagon/packetize-nvstore.mir b/llvm/test/CodeGen/Hexagon/packetize-nvstore.mir index e010226e7a49..9746a3364ecd 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-nvstore.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-nvstore.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -start-before=hexagon-packetizer -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -start-before=hexagon-packetizer -o - %s | FileCheck %s # This used to generate an invalid packet: # { # r1 = #0 diff --git a/llvm/test/CodeGen/Hexagon/packetize-return-arg.ll b/llvm/test/CodeGen/Hexagon/packetize-return-arg.ll index e702b184de60..77db577297b0 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-return-arg.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-return-arg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that "r0 = rN" is packetized together with dealloc_return. ; CHECK: r0 = r ; CHECK-NOT: { diff --git a/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll b/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll index db617dfd2f52..e95015098cd0 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-tailcall-arg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; There should only be one packet: ; { ; jump free diff --git a/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir b/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir index 166e93e23cbe..cbaf7629e827 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-update-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-packetizer %s -o - | FileCheck %s # Make sure that we don't try to packetize the two stores together. The # dependence on $r0 could be broken by updating the offset in the storeiri, diff --git a/llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir b/llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir index fd9df82e7959..50e8b87ce685 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir +++ b/llvm/test/CodeGen/Hexagon/packetize-vgather-slot01.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -mcpu=hexagonv65 -mattr=+hvxv65,+hvx-length64b -run-pass=hexagon-packetizer -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -mattr=+hvxv65,+hvx-length64b -run-pass=hexagon-packetizer -o - %s | FileCheck %s # Check that we don't generate a packet with 5 instructions. diff --git a/llvm/test/CodeGen/Hexagon/packetize-volatiles.ll b/llvm/test/CodeGen/Hexagon/packetize-volatiles.ll index df594258b840..93c6bf148e67 100644 --- a/llvm/test/CodeGen/Hexagon/packetize-volatiles.ll +++ b/llvm/test/CodeGen/Hexagon/packetize-volatiles.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: mem{{.*}} = {{.*}}.new target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll b/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll index 8dca8f281147..6fcfd49ff3c9 100644 --- a/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll +++ b/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -tail-dup-size=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -tail-dup-size=1 < %s | FileCheck %s target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/packetizer-resources.ll b/llvm/test/CodeGen/Hexagon/packetizer-resources.ll index 6b705396b5df..b2030118aeb7 100644 --- a/llvm/test/CodeGen/Hexagon/packetizer-resources.ll +++ b/llvm/test/CodeGen/Hexagon/packetizer-resources.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s -debug-only=packets 2>&1 | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s -debug-only=packets 2>&1 | FileCheck %s ; REQUIRES: asserts ; CHECK: Finalizing packet: diff --git a/llvm/test/CodeGen/Hexagon/partword-cmpxchg.ll b/llvm/test/CodeGen/Hexagon/partword-cmpxchg.ll index 1ef6b95930a9..6e5a54ec6edf 100644 --- a/llvm/test/CodeGen/Hexagon/partword-cmpxchg.ll +++ b/llvm/test/CodeGen/Hexagon/partword-cmpxchg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: danny ; CHECK: memw_locked diff --git a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll index 4bf49c404a36..ca79ed8868b6 100644 --- a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll +++ b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; CHECK: memw ; Check that the testcase compiles without errors. diff --git a/llvm/test/CodeGen/Hexagon/peephole-move-phi.ll b/llvm/test/CodeGen/Hexagon/peephole-move-phi.ll index 70cb6939d2f8..964a847a2f00 100644 --- a/llvm/test/CodeGen/Hexagon/peephole-move-phi.ll +++ b/llvm/test/CodeGen/Hexagon/peephole-move-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Splitting live ranges of vector predicate registers (in hexagon-peephole) diff --git a/llvm/test/CodeGen/Hexagon/peephole-op-swap.ll b/llvm/test/CodeGen/Hexagon/peephole-op-swap.ll index 32db7851fb8b..e2a075068a58 100644 --- a/llvm/test/CodeGen/Hexagon/peephole-op-swap.ll +++ b/llvm/test/CodeGen/Hexagon/peephole-op-swap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; The operand-swapping code in HexagonPeephole was not handling subregisters diff --git a/llvm/test/CodeGen/Hexagon/phi-elim.ll b/llvm/test/CodeGen/Hexagon/phi-elim.ll index bb80cf4a264e..b8351c100241 100644 --- a/llvm/test/CodeGen/Hexagon/phi-elim.ll +++ b/llvm/test/CodeGen/Hexagon/phi-elim.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Check that the verifier doesn't fail due to incorrect diff --git a/llvm/test/CodeGen/Hexagon/pic-jumptables.ll b/llvm/test/CodeGen/Hexagon/pic-jumptables.ll index c19b251fed03..6a68c62f256e 100644 --- a/llvm/test/CodeGen/Hexagon/pic-jumptables.ll +++ b/llvm/test/CodeGen/Hexagon/pic-jumptables.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -relocation-model=pic < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = add({{pc|PC}},## ; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2) diff --git a/llvm/test/CodeGen/Hexagon/pic-local.ll b/llvm/test/CodeGen/Hexagon/pic-local.ll index 163d3ea438d0..a908f70cd9a3 100644 --- a/llvm/test/CodeGen/Hexagon/pic-local.ll +++ b/llvm/test/CodeGen/Hexagon/pic-local.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s define private void @f1() { ret void diff --git a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir index 413d13d642db..fbbb95a61f00 100644 --- a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir +++ b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir @@ -1,4 +1,4 @@ -# RUN: llc < %s -x mir -march=hexagon -run-pass=modulo-schedule-test -pipeliner-experimental-cg=true | FileCheck %s +# RUN: llc < %s -x mir -mtriple=hexagon -run-pass=modulo-schedule-test -pipeliner-experimental-cg=true | FileCheck %s # Simple check for this basic correctness test; ensure all instructions are in stage 0 in # the prolog and stage 3 in the epilog. diff --git a/llvm/test/CodeGen/Hexagon/plt-rel.ll b/llvm/test/CodeGen/Hexagon/plt-rel.ll index ff0c45545919..63e13561341e 100644 --- a/llvm/test/CodeGen/Hexagon/plt-rel.ll +++ b/llvm/test/CodeGen/Hexagon/plt-rel.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -relocation-model=pic -mattr=+long-calls < %s | FileCheck --check-prefix=CHECK-LONG %s -; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -relocation-model=pic -mattr=+long-calls < %s | FileCheck --check-prefix=CHECK-LONG %s +; RUN: llc -mtriple=hexagon -relocation-model=pic < %s | FileCheck %s ; CHECK-LONG: call ##_ZL13g_usr1_called@GDPLT ; CHECK-LONG-NOT: call _ZL13g_usr1_called@GDPLT diff --git a/llvm/test/CodeGen/Hexagon/pmpyw_acc.ll b/llvm/test/CodeGen/Hexagon/pmpyw_acc.ll index 881d74464a36..291ec2368f89 100644 --- a/llvm/test/CodeGen/Hexagon/pmpyw_acc.ll +++ b/llvm/test/CodeGen/Hexagon/pmpyw_acc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}}:{{[0-9]+}} ^= pmpyw(r{{[0-9]+}},r{{[0-9]+}}) ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll index 7d04ef8ff2e4..ebc9969cc381 100644 --- a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll +++ b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s ; REQUIRES: asserts ; Check that the generated post-increment load has TBAA information. diff --git a/llvm/test/CodeGen/Hexagon/post-ra-kill-update.mir b/llvm/test/CodeGen/Hexagon/post-ra-kill-update.mir index 5b9ee9f11f95..9fb4f8a257de 100644 --- a/llvm/test/CodeGen/Hexagon/post-ra-kill-update.mir +++ b/llvm/test/CodeGen/Hexagon/post-ra-kill-update.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -mcpu=hexagonv60 -run-pass post-RA-sched -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -run-pass post-RA-sched -o - %s | FileCheck %s # The post-RA scheduler reorders S2_lsr_r_p and S2_lsr_r_p_or. Both of them # use r9, and the last of the two kills it. The kill flag fixup did not diff --git a/llvm/test/CodeGen/Hexagon/postinc-aggr-dag-cycle.ll b/llvm/test/CodeGen/Hexagon/postinc-aggr-dag-cycle.ll index dbda3bd0418d..1adb011cd9fe 100644 --- a/llvm/test/CodeGen/Hexagon/postinc-aggr-dag-cycle.ll +++ b/llvm/test/CodeGen/Hexagon/postinc-aggr-dag-cycle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir b/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir index 3bf9b3ef7c79..fa07febcbf5a 100644 --- a/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir +++ b/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -start-before hexagon-packetizer %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -start-before hexagon-packetizer %s -o - | FileCheck %s # Check that we don't packetize these two instructions together. It happened # earlier because "offset" in the post-increment instruction was taken to be 8. diff --git a/llvm/test/CodeGen/Hexagon/postinc-load.ll b/llvm/test/CodeGen/Hexagon/postinc-load.ll index 6d4ef7d2ca44..1c6870aefbc1 100644 --- a/llvm/test/CodeGen/Hexagon/postinc-load.ll +++ b/llvm/test/CodeGen/Hexagon/postinc-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that post-increment load instructions are being generated. ; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}++#4) diff --git a/llvm/test/CodeGen/Hexagon/postinc-offset.ll b/llvm/test/CodeGen/Hexagon/postinc-offset.ll index e4c05764db34..8c9390fea44a 100644 --- a/llvm/test/CodeGen/Hexagon/postinc-offset.ll +++ b/llvm/test/CodeGen/Hexagon/postinc-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -enable-aa-sched-mi -march=hexagon -mcpu=hexagonv5 -rdf-opt=0 -disable-cgp-delete-phis \ +; RUN: llc -enable-aa-sched-mi -mtriple=hexagon -mcpu=hexagonv5 -rdf-opt=0 -disable-cgp-delete-phis \ ; RUN: < %s | FileCheck %s ; CHECK: { diff --git a/llvm/test/CodeGen/Hexagon/postinc-order.ll b/llvm/test/CodeGen/Hexagon/postinc-order.ll index 405dd2a8cec7..56b38fe221c8 100644 --- a/llvm/test/CodeGen/Hexagon/postinc-order.ll +++ b/llvm/test/CodeGen/Hexagon/postinc-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that store is post-incremented. ; CHECK: memd(r{{[0-9]+}}++#8) = r diff --git a/llvm/test/CodeGen/Hexagon/postinc-store.ll b/llvm/test/CodeGen/Hexagon/postinc-store.ll index bd8226cf5d37..2f724d035b86 100644 --- a/llvm/test/CodeGen/Hexagon/postinc-store.ll +++ b/llvm/test/CodeGen/Hexagon/postinc-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that post-increment store instructions are being generated. ; CHECK: memw(r{{[0-9]+}}++#4) = r{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir b/llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir index 0ac133738989..c7d878c88b6a 100644 --- a/llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir +++ b/llvm/test/CodeGen/Hexagon/postra-sink-subregs.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass postra-machine-sink,postrapseudos,if-converter -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass postra-machine-sink,postrapseudos,if-converter -verify-machineinstrs -o - %s | FileCheck %s # 1. Post-RA machine sinking moves the copy (1) to block %bb.1. The # subregisters $r2 and $r3 of $d1 are not removed from the live-ins. diff --git a/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll b/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll index 38169d703791..3847bda0c1a6 100644 --- a/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll +++ b/llvm/test/CodeGen/Hexagon/pred-absolute-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we are able to predicate instructions with absolute ; addressing mode. ; CHECK: if ({{!?}}p{{[0-3]}}.new) memw(##gvar) = r{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/pred-gp.ll b/llvm/test/CodeGen/Hexagon/pred-gp.ll index a36bba79506e..31802b39a853 100644 --- a/llvm/test/CodeGen/Hexagon/pred-gp.ll +++ b/llvm/test/CodeGen/Hexagon/pred-gp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we are able to predicate instructions with gp-relative ; addressing mode. diff --git a/llvm/test/CodeGen/Hexagon/pred-instrs.ll b/llvm/test/CodeGen/Hexagon/pred-instrs.ll index 0e62e0d82033..fcdf52f136f0 100644 --- a/llvm/test/CodeGen/Hexagon/pred-instrs.ll +++ b/llvm/test/CodeGen/Hexagon/pred-instrs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we are able to predicate instructions. ; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}} diff --git a/llvm/test/CodeGen/Hexagon/pred-sched.ll b/llvm/test/CodeGen/Hexagon/pred-sched.ll index 8fa237c1a2bf..41d66594e937 100644 --- a/llvm/test/CodeGen/Hexagon/pred-sched.ll +++ b/llvm/test/CodeGen/Hexagon/pred-sched.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; We want to see a .new instruction in this sequence. ; CHECK: p[[PRED:[0-3]]] = tstbit diff --git a/llvm/test/CodeGen/Hexagon/pred-simp.ll b/llvm/test/CodeGen/Hexagon/pred-simp.ll index 5330a6bbe1ff..d3790d791a08 100644 --- a/llvm/test/CodeGen/Hexagon/pred-simp.ll +++ b/llvm/test/CodeGen/Hexagon/pred-simp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-NOT: not( target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/pred-taken-jump.ll b/llvm/test/CodeGen/Hexagon/pred-taken-jump.ll index 71c28204658d..8e55a656f10f 100644 --- a/llvm/test/CodeGen/Hexagon/pred-taken-jump.ll +++ b/llvm/test/CodeGen/Hexagon/pred-taken-jump.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Predicated (old) taken jumps weren't supported prior to V60. The purpose ; of this test is to make sure that these instructions are not diff --git a/llvm/test/CodeGen/Hexagon/predicate-copy.ll b/llvm/test/CodeGen/Hexagon/predicate-copy.ll index 8939a75d9ebb..cf6a2803d553 100644 --- a/llvm/test/CodeGen/Hexagon/predicate-copy.ll +++ b/llvm/test/CodeGen/Hexagon/predicate-copy.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define i1 @f0(i32 %a0) #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/predicate-logical.ll b/llvm/test/CodeGen/Hexagon/predicate-logical.ll index 89e84a4da2dd..f5217729fe8e 100644 --- a/llvm/test/CodeGen/Hexagon/predicate-logical.ll +++ b/llvm/test/CodeGen/Hexagon/predicate-logical.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; CHECK: p{{[0-9]}} = or(p{{[0-9]}},and(p{{[0-9]}},p{{[0-9]}})) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/predicate-rcmp.ll b/llvm/test/CodeGen/Hexagon/predicate-rcmp.ll index 775327b89de5..90eb4b305743 100644 --- a/llvm/test/CodeGen/Hexagon/predicate-rcmp.ll +++ b/llvm/test/CodeGen/Hexagon/predicate-rcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; CHECK: cmp.eq(r{{[0-9]+}},#0) ; Check that the result of the builtin is not stored directly, i.e. that ; there is an instruction that converts it to {0,1} from {0,-1}. Right now diff --git a/llvm/test/CodeGen/Hexagon/predtfrs.ll b/llvm/test/CodeGen/Hexagon/predtfrs.ll index 086d771471d4..2b9d3b28e5dc 100644 --- a/llvm/test/CodeGen/Hexagon/predtfrs.ll +++ b/llvm/test/CodeGen/Hexagon/predtfrs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s ; CHECK: cmp.gt ; CHECK-NOT: r1 = p0 diff --git a/llvm/test/CodeGen/Hexagon/prefetch-intr.ll b/llvm/test/CodeGen/Hexagon/prefetch-intr.ll index b41b2dc67cfe..4e0b3f3971b0 100644 --- a/llvm/test/CodeGen/Hexagon/prefetch-intr.ll +++ b/llvm/test/CodeGen/Hexagon/prefetch-intr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: dcfetch( target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/prefetch-shuffler-ice.ll b/llvm/test/CodeGen/Hexagon/prefetch-shuffler-ice.ll index 3140c95e3ae9..634f5d075b63 100644 --- a/llvm/test/CodeGen/Hexagon/prefetch-shuffler-ice.ll +++ b/llvm/test/CodeGen/Hexagon/prefetch-shuffler-ice.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts ; Expect successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/prob-types.ll b/llvm/test/CodeGen/Hexagon/prob-types.ll index 129baffa4a64..2269c7858e8d 100644 --- a/llvm/test/CodeGen/Hexagon/prob-types.ll +++ b/llvm/test/CodeGen/Hexagon/prob-types.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; REQUIRES: asserts ; This was aborting in Machine Loop Invariant Code Motion, diff --git a/llvm/test/CodeGen/Hexagon/prof-early-if.ll b/llvm/test/CodeGen/Hexagon/prof-early-if.ll index 5f0c9c8f10a5..8daec5a3b310 100644 --- a/llvm/test/CodeGen/Hexagon/prof-early-if.ll +++ b/llvm/test/CodeGen/Hexagon/prof-early-if.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Rely on the comments generated by llc. Check that "if.then" was not predicated. ; CHECK: b5 ; CHECK: b2 diff --git a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll index 37983f6ce6df..44b08c813a3f 100644 --- a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll +++ b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @v0 = global <16 x i32> zeroinitializer, align 64 @v1 = global <16 x i32> zeroinitializer, align 64 diff --git a/llvm/test/CodeGen/Hexagon/ps_call_nr.ll b/llvm/test/CodeGen/Hexagon/ps_call_nr.ll index 31163e8dea5a..544cb35adb5a 100644 --- a/llvm/test/CodeGen/Hexagon/ps_call_nr.ll +++ b/llvm/test/CodeGen/Hexagon/ps_call_nr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that the compiler does not generate an invalid packet with three ; instructions that each requires slot 2 or 3. The specification for diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir b/llvm/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir index ea8e5fb3cfcb..e1617289c3f4 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir +++ b/llvm/test/CodeGen/Hexagon/rdf-copy-renamable-reserved.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-rdf-opt -hexagon-rdf-track-reserved %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-rdf-opt -hexagon-rdf-track-reserved %s -o - | FileCheck %s # Check that r29 gets propagated into the A2_addi, and that the renamable # flag is cleared. diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy-undef.ll b/llvm/test/CodeGen/Hexagon/rdf-copy-undef.ll index 0a0f7348813d..705f54a68247 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-copy-undef.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-copy-undef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; After a copy R20 = R29, RDF copy propagation attempted to replace R20 with diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy-undef2.ll b/llvm/test/CodeGen/Hexagon/rdf-copy-undef2.ll index 0d2b398b720b..af767626614d 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-copy-undef2.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-copy-undef2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy.ll b/llvm/test/CodeGen/Hexagon/rdf-copy.ll index fa1efeac9243..36cc0d4facf7 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-copy.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-copy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-copyprop < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-copyprop < %s | FileCheck %s ; Disable MachineCopyPropagation to expose this opportunity to RDF copy. ; diff --git a/llvm/test/CodeGen/Hexagon/rdf-cover-use.ll b/llvm/test/CodeGen/Hexagon/rdf-cover-use.ll index 4f3de0868aa6..5ebd8b38630c 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-cover-use.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-cover-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; Check for sane output. ; CHECK: vmpyweh diff --git a/llvm/test/CodeGen/Hexagon/rdf-dce-double-cover.mir b/llvm/test/CodeGen/Hexagon/rdf-dce-double-cover.mir index 3f3362b194eb..303468489ae1 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-dce-double-cover.mir +++ b/llvm/test/CodeGen/Hexagon/rdf-dce-double-cover.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-rdf-opt -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-rdf-opt -verify-machineinstrs %s -o - | FileCheck %s # Check that the L2_loadrd_io load from stack to $d6 # register, in bb.0, is not considered as dead code by RDF diff --git a/llvm/test/CodeGen/Hexagon/rdf-dead-loop.ll b/llvm/test/CodeGen/Hexagon/rdf-dead-loop.ll index 1bb64434f6e2..3a3c543c123a 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-dead-loop.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-dead-loop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: ={{.*}}add ; CHECK-NOT: mem{{[bdhwu]}} diff --git a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll index cc57096a4580..db25b64bd74f 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s ; REQUIRES: asserts ; Check for sane output. This testcase used to crash. diff --git a/llvm/test/CodeGen/Hexagon/rdf-ehlabel-live.mir b/llvm/test/CodeGen/Hexagon/rdf-ehlabel-live.mir index a31c774d332d..82c5990c275d 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-ehlabel-live.mir +++ b/llvm/test/CodeGen/Hexagon/rdf-ehlabel-live.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-rdf-opt -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-rdf-opt -o - %s | FileCheck %s # Check that EH_LABELs are not removed as dead (since they are no longer # marked as having side-effects): diff --git a/llvm/test/CodeGen/Hexagon/rdf-extra-livein.ll b/llvm/test/CodeGen/Hexagon/rdf-extra-livein.ll index 3352f6f50593..4841f56226e8 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-extra-livein.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-extra-livein.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; Verify that the code compiles successfully. ; CHECK: call printf diff --git a/llvm/test/CodeGen/Hexagon/rdf-filter-defs.ll b/llvm/test/CodeGen/Hexagon/rdf-filter-defs.ll index 68ae19acb8d6..4974251e2443 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-filter-defs.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-filter-defs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; Check that this testcase compiles successfully. ; CHECK: dealloc_return diff --git a/llvm/test/CodeGen/Hexagon/rdf-ignore-undef.ll b/llvm/test/CodeGen/Hexagon/rdf-ignore-undef.ll index 65f67cc03a39..2872d04f6d49 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-ignore-undef.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-ignore-undef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; Check that we don't crash. ; CHECK: call foo diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll index 557523172a10..5c76c6cccd7a 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r0 = #24 ; CHECK: r1 = ; // R2 should be assigned a value from R3+. diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll index 5f2a88ca575a..88af26b5c597 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/rdf-kill-last-op.ll b/llvm/test/CodeGen/Hexagon/rdf-kill-last-op.ll index 56c02be9a033..f27f91a8a2c7 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-kill-last-op.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-kill-last-op.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/rdf-multiple-phis-up.ll b/llvm/test/CodeGen/Hexagon/rdf-multiple-phis-up.ll index e1a6eee4d844..27c10a9ad95c 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-multiple-phis-up.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-multiple-phis-up.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Check that we do not crash. diff --git a/llvm/test/CodeGen/Hexagon/rdf-phi-shadows.ll b/llvm/test/CodeGen/Hexagon/rdf-phi-shadows.ll index 462df4aff0f9..68724da4775c 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-phi-shadows.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-phi-shadows.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; Check that we don't crash. ; CHECK: call printf target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/rdf-phi-up.ll b/llvm/test/CodeGen/Hexagon/rdf-phi-up.ll index d8739e960e8d..ea2fead8a8f1 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-phi-up.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-phi-up.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s ; Check that this testcase compiles successfully. ; CHECK-LABEL: fred: ; CHECK: call foo diff --git a/llvm/test/CodeGen/Hexagon/rdf-reset-kills.ll b/llvm/test/CodeGen/Hexagon/rdf-reset-kills.ll index 37db8c5f64e6..7aeff0197418 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-reset-kills.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-reset-kills.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; This test used to crash in register scavenger due to incorrectly set diff --git a/llvm/test/CodeGen/Hexagon/readcyclecounter.ll b/llvm/test/CodeGen/Hexagon/readcyclecounter.ll index 0a60c94b019c..b1b4696641de 100644 --- a/llvm/test/CodeGen/Hexagon/readcyclecounter.ll +++ b/llvm/test/CodeGen/Hexagon/readcyclecounter.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_readcyclecounter ; CHECK: r1:0 = c15:14 diff --git a/llvm/test/CodeGen/Hexagon/readsteadycounter.ll b/llvm/test/CodeGen/Hexagon/readsteadycounter.ll index 5a78552117d9..377097a99132 100644 --- a/llvm/test/CodeGen/Hexagon/readsteadycounter.ll +++ b/llvm/test/CodeGen/Hexagon/readsteadycounter.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_readsteadycounter ; CHECK: r1:0 = c31:30 diff --git a/llvm/test/CodeGen/Hexagon/redundant-branching2.ll b/llvm/test/CodeGen/Hexagon/redundant-branching2.ll index 30f69f370a0c..c837ae5e3552 100644 --- a/llvm/test/CodeGen/Hexagon/redundant-branching2.ll +++ b/llvm/test/CodeGen/Hexagon/redundant-branching2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; This test checks if redundant conditional branches are removed. ; CHECK: memub diff --git a/llvm/test/CodeGen/Hexagon/reg-by-name.ll b/llvm/test/CodeGen/Hexagon/reg-by-name.ll index cc8807e4f4d6..cfcee0e9a06e 100644 --- a/llvm/test/CodeGen/Hexagon/reg-by-name.ll +++ b/llvm/test/CodeGen/Hexagon/reg-by-name.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-tfr-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-tfr-cleanup=0 < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/reg-eq-cmp.ll b/llvm/test/CodeGen/Hexagon/reg-eq-cmp.ll index 49a70f0843f2..730ef8f4ffa8 100644 --- a/llvm/test/CodeGen/Hexagon/reg-eq-cmp.ll +++ b/llvm/test/CodeGen/Hexagon/reg-eq-cmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Generate reg = cmp. @g0 = common global i8 0, align 1 diff --git a/llvm/test/CodeGen/Hexagon/reg-scav-imp-use-dbl-vec.ll b/llvm/test/CodeGen/Hexagon/reg-scav-imp-use-dbl-vec.ll index 920e7a487150..45b2ec941c18 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scav-imp-use-dbl-vec.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scav-imp-use-dbl-vec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; REQUIRES: asserts ; Check that the code compiles successfully. diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll index 4b481a222c86..e58bd8684629 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; CHECK: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll index 62b5cdb36a18..61a0d6dfa9de 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-4.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-4.ll index b0211888e703..b69380284a5d 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-4.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the register scavenger does not fail because it can't find diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-5.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-5.ll index 9ad00cd83ad8..438d6aa84738 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-5.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-5.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the register scavenger does not assert because a spill slot diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug.ll index 710e3b44028c..b6876547496a 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavengebug.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s ; CHECK: v{{[0-9]+}}.w = vadd target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll index 57b0c8d03a40..ee0d67c4b99a 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; This testcase tries to force spills of both vector and int registers diff --git a/llvm/test/CodeGen/Hexagon/reg_seq.ll b/llvm/test/CodeGen/Hexagon/reg_seq.ll index c447e426db13..47a98d0bb166 100644 --- a/llvm/test/CodeGen/Hexagon/reg_seq.ll +++ b/llvm/test/CodeGen/Hexagon/reg_seq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Generate REG_SEQUENCE instead of combine ; CHECK-NOT: combine(#0 diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir index d291af97d3af..019d593c3494 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir @@ -1,9 +1,9 @@ -# RUN: llc -march=hexagon -enable-subreg-liveness -start-after machine-scheduler -stop-after stack-slot-coloring -o - %s | FileCheck %s +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=hexagon -enable-subreg-liveness -start-after machine-scheduler -stop-after stack-slot-coloring -o - %s | FileCheck %s --- | target triple = "hexagon" - ; Function Attrs: nounwind optsize define void @main() #0 { entry: br label %for.body @@ -142,6 +142,64 @@ frameInfo: hasVAStart: false hasMustTailInVarArgFunc: false body: | + ; CHECK-LABEL: name: main + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r20 = A2_tfrsi 524288 + ; CHECK-NEXT: renamable $r17 = A2_tfrsi 0 + ; CHECK-NEXT: renamable $d2 = S2_extractup undef renamable $d0, 6, 25 + ; CHECK-NEXT: renamable $d0 = A2_tfrpi 2 + ; CHECK-NEXT: renamable $d13 = A2_tfrpi -1 + ; CHECK-NEXT: renamable $d13 = S2_asl_r_p_acc killed renamable $d13, killed renamable $d0, renamable $r4 + ; CHECK-NEXT: S2_storerd_io %stack.0, 0, renamable $d2 :: (store (s64) into %stack.0) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.for.body: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK-NEXT: liveins: $d8:0x0000000000000001, $d13, $r20 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29 + ; CHECK-NEXT: J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3, implicit-def $r0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29 + ; CHECK-NEXT: renamable $r18 = COPY $r0 + ; CHECK-NEXT: renamable $r19 = S2_asr_i_r renamable $r18, 31 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29 + ; CHECK-NEXT: J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3, implicit-def $r0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29 + ; CHECK-NEXT: renamable $r16 = COPY $r0 + ; CHECK-NEXT: renamable $d12 = S2_extractup renamable $d8, 22, 9 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29 + ; CHECK-NEXT: J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3, implicit-def $r0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29 + ; CHECK-NEXT: renamable $r1 = COPY renamable $r17 + ; CHECK-NEXT: renamable $d0 = S2_extractup killed renamable $d0, 6, 25 + ; CHECK-NEXT: renamable $d11 = A2_tfrpi -1 + ; CHECK-NEXT: renamable $d1 = A2_tfrpi 2 + ; CHECK-NEXT: renamable $d11 = S2_asl_r_p_acc killed renamable $d11, killed renamable $d1, killed renamable $r0 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29 + ; CHECK-NEXT: J2_call @lrand48, implicit-def dead $d0, implicit-def dead $d1, implicit-def dead $d2, implicit-def dead $d3, implicit-def dead $d4, implicit-def dead $d5, implicit-def dead $d6, implicit-def dead $d7, implicit-def dead $r28, implicit-def dead $r31, implicit-def dead $p0, implicit-def dead $p1, implicit-def dead $p2, implicit-def dead $p3, implicit-def dead $m0, implicit-def dead $m1, implicit-def dead $lc0, implicit-def dead $lc1, implicit-def dead $sa0, implicit-def dead $sa1, implicit-def dead $usr, implicit-def $usr_ovf, implicit-def dead $cs0, implicit-def dead $cs1, implicit-def dead $w0, implicit-def dead $w1, implicit-def dead $w2, implicit-def dead $w3, implicit-def dead $w4, implicit-def dead $w5, implicit-def dead $w6, implicit-def dead $w7, implicit-def dead $w8, implicit-def dead $w9, implicit-def dead $w10, implicit-def dead $w11, implicit-def dead $w12, implicit-def dead $w13, implicit-def dead $w14, implicit-def dead $w15, implicit-def dead $q0, implicit-def dead $q1, implicit-def dead $q2, implicit-def dead $q3 + ; CHECK-NEXT: renamable $d2 = L2_loadrd_io %stack.0, 0 :: (load (s64) from %stack.0) + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29 + ; CHECK-NEXT: renamable $d0 = S2_asl_r_p killed renamable $d11, killed renamable $r4 + ; CHECK-NEXT: renamable $d1 = COPY renamable $d13 + ; CHECK-NEXT: renamable $d1 = S2_lsr_i_p_and killed renamable $d1, killed renamable $d9, 9 + ; CHECK-NEXT: renamable $d0 = S2_asl_i_p_and killed renamable $d0, killed renamable $d12, 42 + ; CHECK-NEXT: S2_storerd_io undef renamable $r0, 0, killed renamable $d0 :: (store (s64) into `ptr undef`) + ; CHECK-NEXT: renamable $d0 = A2_tfrpi 0 + ; CHECK-NEXT: renamable $p0 = C2_cmpeqp killed renamable $d1, killed renamable $d0 + ; CHECK-NEXT: J2_jumpt killed renamable $p0, %bb.3, implicit-def dead $pc + ; CHECK-NEXT: J2_jump %bb.2, implicit-def dead $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.end82: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $d8:0x0000000000000001, $d13, $r20 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r20 = A2_addi killed renamable $r20, -1 + ; CHECK-NEXT: renamable $p0 = C2_cmpeqi renamable $r20, 0 + ; CHECK-NEXT: J2_jumpf killed renamable $p0, %bb.1, implicit-def dead $pc + ; CHECK-NEXT: J2_jump %bb.3, implicit-def dead $pc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.end: bb.0.entry: successors: %bb.1.for.body @@ -153,11 +211,6 @@ body: | %13 = S2_asl_r_p_acc %13, %47, %8.isub_lo %51 = A2_tfrpi 0 - ; CHECK: $d2 = S2_extractup undef renamable $d0, 6, 25 - ; CHECK: $d0 = A2_tfrpi 2 - ; CHECK: $d13 = A2_tfrpi -1 - ; CHECK-NOT: undef $r4 - bb.1.for.body: successors: %bb.3.for.end, %bb.2.if.end82 diff --git a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll index 8632ddf44b6f..a421ea02c246 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll +++ b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for a sane output. This testcase used to cause a crash. ; CHECK: vlut16 diff --git a/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir b/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir index 16a22633e145..b2da1844bfc8 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass register-coalescer -verify-coalescing %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass register-coalescer -verify-coalescing %s -o - | FileCheck %s # # Check that this doesn't crash. # CHECK: ENDLOOP diff --git a/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir index fac59950b1bc..466d04be57c6 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-coal-fullreg-undef.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass=register-coalescer -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass=register-coalescer -o - %s | FileCheck %s # Make sure that the coalescer does not create a full definition with # an undef flag on the destination. This used to happen when rematerializing diff --git a/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir index 8cb88ae5949c..88ce8784e614 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass liveintervals -run-pass machineverifier -run-pass register-coalescer %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass liveintervals -run-pass machineverifier -run-pass register-coalescer %s -o - | FileCheck %s # # If there is no consumer of the live intervals, the live intervals pass # will be freed immediately after it runs, before the verifier. Add a diff --git a/llvm/test/CodeGen/Hexagon/registerscav-missing-spill-slot.ll b/llvm/test/CodeGen/Hexagon/registerscav-missing-spill-slot.ll index 1a8e06259abb..05a526d8a3e6 100644 --- a/llvm/test/CodeGen/Hexagon/registerscav-missing-spill-slot.ll +++ b/llvm/test/CodeGen/Hexagon/registerscav-missing-spill-slot.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -machine-sink-split=0 < %s +; RUN: llc -mtriple=hexagon -machine-sink-split=0 < %s ; REQUIRES: asserts ; Used to fail with: Assertion `ScavengingFrameIndex >= 0 && "Cannot scavenge register without an emergency spill slot!"' failed. diff --git a/llvm/test/CodeGen/Hexagon/registerscavenger-fail1.ll b/llvm/test/CodeGen/Hexagon/registerscavenger-fail1.ll index baafd3e9c624..b0bd3fb26a1d 100644 --- a/llvm/test/CodeGen/Hexagon/registerscavenger-fail1.ll +++ b/llvm/test/CodeGen/Hexagon/registerscavenger-fail1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -machine-sink-split=0 < %s +; RUN: llc -mtriple=hexagon -machine-sink-split=0 < %s ; REQUIRES: asserts target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/regp-underflow.ll b/llvm/test/CodeGen/Hexagon/regp-underflow.ll index bc4fb0357b37..ee643178c10f 100644 --- a/llvm/test/CodeGen/Hexagon/regp-underflow.ll +++ b/llvm/test/CodeGen/Hexagon/regp-underflow.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/regscav-wrong-super-sub-regs.ll b/llvm/test/CodeGen/Hexagon/regscav-wrong-super-sub-regs.ll index e01af104b4f6..e3c5c525ead7 100644 --- a/llvm/test/CodeGen/Hexagon/regscav-wrong-super-sub-regs.ll +++ b/llvm/test/CodeGen/Hexagon/regscav-wrong-super-sub-regs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that register scvenging does not assert because of wrong diff --git a/llvm/test/CodeGen/Hexagon/regscavenger_fail_hwloop.ll b/llvm/test/CodeGen/Hexagon/regscavenger_fail_hwloop.ll index 23d9931a019e..3cd3f6fefd17 100644 --- a/llvm/test/CodeGen/Hexagon/regscavenger_fail_hwloop.ll +++ b/llvm/test/CodeGen/Hexagon/regscavenger_fail_hwloop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; This test used to fail with; diff --git a/llvm/test/CodeGen/Hexagon/regscavengerbug.ll b/llvm/test/CodeGen/Hexagon/regscavengerbug.ll index 35d77c7c7ecb..60c8d9531235 100644 --- a/llvm/test/CodeGen/Hexagon/regscavengerbug.ll +++ b/llvm/test/CodeGen/Hexagon/regscavengerbug.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts ; This used to assert in the register scavenger. diff --git a/llvm/test/CodeGen/Hexagon/remove-endloop.ll b/llvm/test/CodeGen/Hexagon/remove-endloop.ll index c091fbbcad5f..6a57eb94ff51 100644 --- a/llvm/test/CodeGen/Hexagon/remove-endloop.ll +++ b/llvm/test/CodeGen/Hexagon/remove-endloop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s define void @foo(i32 %n, ptr nocapture %A, ptr nocapture %B) nounwind optsize { entry: diff --git a/llvm/test/CodeGen/Hexagon/remove_lsr.ll b/llvm/test/CodeGen/Hexagon/remove_lsr.ll index 9249174e5006..b21ca12f6985 100644 --- a/llvm/test/CodeGen/Hexagon/remove_lsr.ll +++ b/llvm/test/CodeGen/Hexagon/remove_lsr.ll @@ -1,5 +1,5 @@ ; Test fix for PR-13709. -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: f0 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32) ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32) diff --git a/llvm/test/CodeGen/Hexagon/restore-single-reg.ll b/llvm/test/CodeGen/Hexagon/restore-single-reg.ll index 8abd4a855463..67f4ec4b0759 100644 --- a/llvm/test/CodeGen/Hexagon/restore-single-reg.ll +++ b/llvm/test/CodeGen/Hexagon/restore-single-reg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/ret-struct-by-val.ll b/llvm/test/CodeGen/Hexagon/ret-struct-by-val.ll index 60a97bcccfc5..01ec848e7084 100644 --- a/llvm/test/CodeGen/Hexagon/ret-struct-by-val.ll +++ b/llvm/test/CodeGen/Hexagon/ret-struct-by-val.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r0 = add(r0,r1) ; Allow simple structures to be returned by value. diff --git a/llvm/test/CodeGen/Hexagon/retval-redundant-copy.ll b/llvm/test/CodeGen/Hexagon/retval-redundant-copy.ll index fbcc7d913180..5e57161251d5 100644 --- a/llvm/test/CodeGen/Hexagon/retval-redundant-copy.ll +++ b/llvm/test/CodeGen/Hexagon/retval-redundant-copy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; ; Check whether there are no redundant register copies of return values ; diff --git a/llvm/test/CodeGen/Hexagon/rotate-multi.ll b/llvm/test/CodeGen/Hexagon/rotate-multi.ll index 74e31872db80..efe921ad9327 100644 --- a/llvm/test/CodeGen/Hexagon/rotate-multi.ll +++ b/llvm/test/CodeGen/Hexagon/rotate-multi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; OR of two rotates of %a0(r0). ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/rotate.ll b/llvm/test/CodeGen/Hexagon/rotate.ll index 101d68b81bbc..19af539ed966 100644 --- a/llvm/test/CodeGen/Hexagon/rotate.ll +++ b/llvm/test/CodeGen/Hexagon/rotate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/rotl-i64.ll b/llvm/test/CodeGen/Hexagon/rotl-i64.ll index a37814cd9c5b..510364113e52 100644 --- a/llvm/test/CodeGen/Hexagon/rotl-i64.ll +++ b/llvm/test/CodeGen/Hexagon/rotl-i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: rol ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/save-kill-csr.ll b/llvm/test/CodeGen/Hexagon/save-kill-csr.ll index 994de78bdb0d..ebc7bfbe8242 100644 --- a/llvm/test/CodeGen/Hexagon/save-kill-csr.ll +++ b/llvm/test/CodeGen/Hexagon/save-kill-csr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/save-regs-thresh.ll b/llvm/test/CodeGen/Hexagon/save-regs-thresh.ll index 655aa77deabd..e0bce2d4c20c 100644 --- a/llvm/test/CodeGen/Hexagon/save-regs-thresh.ll +++ b/llvm/test/CodeGen/Hexagon/save-regs-thresh.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O2 -spill-func-threshold=4 < %s | FileCheck %s --check-prefix=NOSAVE -; RUN: llc -march=hexagon -O2 -spill-func-threshold=2 < %s | FileCheck %s --check-prefix=SAVE +; RUN: llc -mtriple=hexagon -O2 -spill-func-threshold=4 < %s | FileCheck %s --check-prefix=NOSAVE +; RUN: llc -mtriple=hexagon -O2 -spill-func-threshold=2 < %s | FileCheck %s --check-prefix=SAVE ; NOSAVE-NOT: call __save_r16_ ; SAVE: call __save_r16_ diff --git a/llvm/test/CodeGen/Hexagon/sdata-array.ll b/llvm/test/CodeGen/Hexagon/sdata-array.ll index 84cb32195745..93241761d237 100644 --- a/llvm/test/CodeGen/Hexagon/sdata-array.ll +++ b/llvm/test/CodeGen/Hexagon/sdata-array.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; No arrays in sdata. ; CHECK: memb(##foo) diff --git a/llvm/test/CodeGen/Hexagon/sdata-basic.ll b/llvm/test/CodeGen/Hexagon/sdata-basic.ll index e15a8c9a9a9d..3234c225e7a4 100644 --- a/llvm/test/CodeGen/Hexagon/sdata-basic.ll +++ b/llvm/test/CodeGen/Hexagon/sdata-basic.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-NOT: ##var target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/sdata-expand-const.ll b/llvm/test/CodeGen/Hexagon/sdata-expand-const.ll index 31c2c3f2c6d3..47b28d074f42 100644 --- a/llvm/test/CodeGen/Hexagon/sdata-expand-const.ll +++ b/llvm/test/CodeGen/Hexagon/sdata-expand-const.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s ; CHECK-NOT: CONST target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/sdata-explicit-section.ll b/llvm/test/CodeGen/Hexagon/sdata-explicit-section.ll index 807474f43826..6ae0c3dfaf35 100644 --- a/llvm/test/CodeGen/Hexagon/sdata-explicit-section.ll +++ b/llvm/test/CodeGen/Hexagon/sdata-explicit-section.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s -; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -relocation-model=pic < %s | FileCheck %s ; CHECK: .section .sdata.4,"aws",@progbits @g0 = global i32 zeroinitializer, section ".sdata" diff --git a/llvm/test/CodeGen/Hexagon/sdata-load-size.ll b/llvm/test/CodeGen/Hexagon/sdata-load-size.ll index fb63ffd35ade..815dcea037f5 100644 --- a/llvm/test/CodeGen/Hexagon/sdata-load-size.ll +++ b/llvm/test/CodeGen/Hexagon/sdata-load-size.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=8 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=8 < %s | FileCheck %s ; CHECK: = memd(gp+#g0) ; If an object will be placed in .sdata, do not shrink any references to it. ; In this case, g0 must be loaded via memd. diff --git a/llvm/test/CodeGen/Hexagon/sdata-opaque-type.ll b/llvm/test/CodeGen/Hexagon/sdata-opaque-type.ll index 64afefe467dc..20a350fdc520 100644 --- a/llvm/test/CodeGen/Hexagon/sdata-opaque-type.ll +++ b/llvm/test/CodeGen/Hexagon/sdata-opaque-type.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts ; This should compile cleanly. diff --git a/llvm/test/CodeGen/Hexagon/sdata-stack-guard.ll b/llvm/test/CodeGen/Hexagon/sdata-stack-guard.ll index 6b335930d477..b79800cfacce 100644 --- a/llvm/test/CodeGen/Hexagon/sdata-stack-guard.ll +++ b/llvm/test/CodeGen/Hexagon/sdata-stack-guard.ll @@ -1,9 +1,9 @@ ; Check that the __stack_chk_guard was placed in small data. -; RUN: llc -march=hexagon -mtriple=hexagon-unknown-linux-gnu -O2 -hexagon-small-data-threshold=4 < %s | FileCheck -check-prefix=GPREL %s +; RUN: llc -mtriple=hexagon -mtriple=hexagon-unknown-linux-gnu -O2 -hexagon-small-data-threshold=4 < %s | FileCheck -check-prefix=GPREL %s ; GPREL: memw(gp+#__stack_chk_guard) ; For threshold less than 4 (size of address), the variable is not placed in small-data -; RUN: llc -march=hexagon -mtriple=hexagon-unknown-linux-gnu -O2 -hexagon-small-data-threshold=0 < %s | FileCheck -check-prefix=ABS %s +; RUN: llc -mtriple=hexagon -mtriple=hexagon-unknown-linux-gnu -O2 -hexagon-small-data-threshold=0 < %s | FileCheck -check-prefix=ABS %s ; ABS: memw(##__stack_chk_guard) @g0 = private unnamed_addr constant [37 x i8] c"This string is longer than 16 bytes\0A\00", align 1 diff --git a/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll b/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll index 06b4dc1cedab..1f85644fcc16 100644 --- a/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll +++ b/llvm/test/CodeGen/Hexagon/sdiv-minsigned.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; This checks for a bug in the DAG combiner where a SETCC was created with diff --git a/llvm/test/CodeGen/Hexagon/sdr-global.mir b/llvm/test/CodeGen/Hexagon/sdr-global.mir index f5c5f46061a7..6885b9c70293 100644 --- a/llvm/test/CodeGen/Hexagon/sdr-global.mir +++ b/llvm/test/CodeGen/Hexagon/sdr-global.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-split-double %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-split-double %s -o - | FileCheck %s # This used to crash because the constant operand was not an immediate. # Make sure we can handle such a case. diff --git a/llvm/test/CodeGen/Hexagon/sdr-nosplit1.ll b/llvm/test/CodeGen/Hexagon/sdr-nosplit1.ll index bb20f77df5d9..5b12eeeeca04 100644 --- a/llvm/test/CodeGen/Hexagon/sdr-nosplit1.ll +++ b/llvm/test/CodeGen/Hexagon/sdr-nosplit1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Make sure that the A2_andp is not split. ; diff --git a/llvm/test/CodeGen/Hexagon/sdr-reg-profit.ll b/llvm/test/CodeGen/Hexagon/sdr-reg-profit.ll index 951a05a53df2..5819d4e8e772 100644 --- a/llvm/test/CodeGen/Hexagon/sdr-reg-profit.ll +++ b/llvm/test/CodeGen/Hexagon/sdr-reg-profit.ll @@ -1,6 +1,6 @@ ; REQUIRES: to-be-fixed ; This requires further patches. -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Split all andp/orp instructions (by boosting the profitability of their ; operands, which happen to be word masks). diff --git a/llvm/test/CodeGen/Hexagon/sdr-shr32.ll b/llvm/test/CodeGen/Hexagon/sdr-shr32.ll index 2e548fc5b0a0..d0e96c7c2a64 100644 --- a/llvm/test/CodeGen/Hexagon/sdr-shr32.ll +++ b/llvm/test/CodeGen/Hexagon/sdr-shr32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: lsr{{.*}}#31 target datalayout = "e-m:e-p:32:32-i64:64-a:0-v32:32-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/section_7275.ll b/llvm/test/CodeGen/Hexagon/section_7275.ll index 733cee86a60b..ea427c3a61f9 100644 --- a/llvm/test/CodeGen/Hexagon/section_7275.ll +++ b/llvm/test/CodeGen/Hexagon/section_7275.ll @@ -5,7 +5,7 @@ ; and that section is not sdata*/sbss* then the variable ; cannot use GPREL addressing, i.e. memw(#variablename). -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: foo ; CHECK-DAG: memw(##b) ; CHECK-DAG: memw(gp+#d) diff --git a/llvm/test/CodeGen/Hexagon/select-instr-align.ll b/llvm/test/CodeGen/Hexagon/select-instr-align.ll index 8a66ecb8fca4..354deaff3a6c 100644 --- a/llvm/test/CodeGen/Hexagon/select-instr-align.ll +++ b/llvm/test/CodeGen/Hexagon/select-instr-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-align-loads=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-align-loads=0 < %s | FileCheck %s ; CHECK-LABEL: aligned_load: ; CHECK: = vmem({{.*}}) diff --git a/llvm/test/CodeGen/Hexagon/select-vector-pred.ll b/llvm/test/CodeGen/Hexagon/select-vector-pred.ll index e4e7c957e7ad..46f45cf98a4c 100644 --- a/llvm/test/CodeGen/Hexagon/select-vector-pred.ll +++ b/llvm/test/CodeGen/Hexagon/select-vector-pred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b < %s | FileCheck %s ; Do not generate selectI1,Q,Q. ; CHECK: q[[Q:[0-9]+]] = vsetq(r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/setmemrefs.ll b/llvm/test/CodeGen/Hexagon/setmemrefs.ll index 7037505cb8ab..85f46af7e56a 100644 --- a/llvm/test/CodeGen/Hexagon/setmemrefs.ll +++ b/llvm/test/CodeGen/Hexagon/setmemrefs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This test checks to see if, after lowering the two loads below, we set up the ; memrefs of the resulting load MIs correctly, so that they are packetized diff --git a/llvm/test/CodeGen/Hexagon/sf-min-max.ll b/llvm/test/CodeGen/Hexagon/sf-min-max.ll index e795cb42d6a2..e4c6579275e6 100644 --- a/llvm/test/CodeGen/Hexagon/sf-min-max.ll +++ b/llvm/test/CodeGen/Hexagon/sf-min-max.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: sf_min_olt: ; CHECK: sfmin diff --git a/llvm/test/CodeGen/Hexagon/sffms.ll b/llvm/test/CodeGen/Hexagon/sffms.ll index e3fd11f495b3..577cad8aa9d3 100644 --- a/llvm/test/CodeGen/Hexagon/sffms.ll +++ b/llvm/test/CodeGen/Hexagon/sffms.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -fp-contract=fast < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -fp-contract=fast < %s | FileCheck %s ; Check that "Rx-=sfmpy(Rs,Rt)" is being generated for "fsub(fmul(..))" diff --git a/llvm/test/CodeGen/Hexagon/sfmin_dce.ll b/llvm/test/CodeGen/Hexagon/sfmin_dce.ll index fb81560ac9c3..a0d319e992d6 100644 --- a/llvm/test/CodeGen/Hexagon/sfmin_dce.ll +++ b/llvm/test/CodeGen/Hexagon/sfmin_dce.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: f0 ; CHECK-NOT: sfmin diff --git a/llvm/test/CodeGen/Hexagon/sfmpyacc_scale.ll b/llvm/test/CodeGen/Hexagon/sfmpyacc_scale.ll index ebfc4db2a532..a969b3ee8d8a 100644 --- a/llvm/test/CodeGen/Hexagon/sfmpyacc_scale.ll +++ b/llvm/test/CodeGen/Hexagon/sfmpyacc_scale.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]*}} += sfmpy(r{{[0-9]*}},r{{[0-9]*}},p{{[0-3]}}):scale target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/signed_immediates.ll b/llvm/test/CodeGen/Hexagon/signed_immediates.ll index 72e6d24cf794..2e968b032ff5 100644 --- a/llvm/test/CodeGen/Hexagon/signed_immediates.ll +++ b/llvm/test/CodeGen/Hexagon/signed_immediates.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; s4_0Imm ; CHECK: memb(r0++#-1) = r1 diff --git a/llvm/test/CodeGen/Hexagon/signext-inreg.ll b/llvm/test/CodeGen/Hexagon/signext-inreg.ll index fe74fa0f9a0e..3330d6a569a4 100644 --- a/llvm/test/CodeGen/Hexagon/signext-inreg.ll +++ b/llvm/test/CodeGen/Hexagon/signext-inreg.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -march=hexagon | FileCheck %s -; RUN: llc < %s -march=hexagon -mattr=+hvx,hvx-length64b | FileCheck %s --check-prefix=CHECK-64B -; RUN: llc < %s -march=hexagon -mattr=+hvx,hvx-length128b | FileCheck %s --check-prefix=CHECK-128B +; RUN: llc < %s -mtriple=hexagon | FileCheck %s +; RUN: llc < %s -mtriple=hexagon -mattr=+hvx,hvx-length64b | FileCheck %s --check-prefix=CHECK-64B +; RUN: llc < %s -mtriple=hexagon -mattr=+hvx,hvx-length128b | FileCheck %s --check-prefix=CHECK-128B define <2 x i32> @test1(<2 x i32> %m) { ; CHECK-LABEL: test1: ; CHECK: .cfi_startproc diff --git a/llvm/test/CodeGen/Hexagon/simple-types-mem.ll b/llvm/test/CodeGen/Hexagon/simple-types-mem.ll new file mode 100644 index 000000000000..01baa65a5935 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/simple-types-mem.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +; Only simple types memory accesses are handled. + +target triple = "hexagon" + +%struct.hoge = type { i320 } + +define dso_local void @widget() { +bb: + %tmp = alloca %struct.hoge, align 1 + %tmp1 = bitcast %struct.hoge* %tmp to i320* + %tmp2 = load i320, i320* %tmp1, align 1 + %tmp3 = and i320 %tmp2, -18446744073709551616 + %tmp4 = or i320 %tmp3, 0 + store i320 %tmp4, i320* %tmp1, align 1 + call void @llvm.trap() + unreachable +} + +declare void @llvm.trap() diff --git a/llvm/test/CodeGen/Hexagon/simpletailcall.ll b/llvm/test/CodeGen/Hexagon/simpletailcall.ll index 7d1055c9ae54..6634efe7c5e7 100644 --- a/llvm/test/CodeGen/Hexagon/simpletailcall.ll +++ b/llvm/test/CodeGen/Hexagon/simpletailcall.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: f0 ; CHECK-NOT: allocframe ; CHECK-NOT: memd(r29 diff --git a/llvm/test/CodeGen/Hexagon/simplify64bitops_7223.ll b/llvm/test/CodeGen/Hexagon/simplify64bitops_7223.ll index 427a9948f63b..a7fa8370eb20 100644 --- a/llvm/test/CodeGen/Hexagon/simplify64bitops_7223.ll +++ b/llvm/test/CodeGen/Hexagon/simplify64bitops_7223.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -enable-pipeliner=false < %s | FileCheck %s -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner=false < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; CHECK-NOT: and( ; CHECK-NOT: or( diff --git a/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir b/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir index 3ad67ce7931d..0232bd4d82b6 100644 --- a/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir +++ b/llvm/test/CodeGen/Hexagon/spill-vector-alignment.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass prologepilog %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass prologepilog %s -o - | FileCheck %s # Check that the spill of $q0 no longer uses unaligned store instruction. # CHECK: V6_vS32b_ai $r16, -256, killed $v0 diff --git a/llvm/test/CodeGen/Hexagon/split-const32-const64.ll b/llvm/test/CodeGen/Hexagon/split-const32-const64.ll index 5766053ae5ea..c8379bc9e75a 100644 --- a/llvm/test/CodeGen/Hexagon/split-const32-const64.ll +++ b/llvm/test/CodeGen/Hexagon/split-const32-const64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s ; Check that CONST32/CONST64 instructions are 'not' generated when the ; small data threshold is set to 0. diff --git a/llvm/test/CodeGen/Hexagon/split-muxii.ll b/llvm/test/CodeGen/Hexagon/split-muxii.ll index 687221b8f8ad..d4dd8374e2f1 100644 --- a/llvm/test/CodeGen/Hexagon/split-muxii.ll +++ b/llvm/test/CodeGen/Hexagon/split-muxii.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -hexagon-expand-condsets=true -hexagon-gen-mux-threshold=4 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -hexagon-expand-condsets=true -hexagon-gen-mux-threshold=4 < %s | FileCheck %s ; CHECK-NOT: mux(p target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/split-vecpred.ll b/llvm/test/CodeGen/Hexagon/split-vecpred.ll index c68c491d09c9..b0f73a397ffa 100644 --- a/llvm/test/CodeGen/Hexagon/split-vecpred.ll +++ b/llvm/test/CodeGen/Hexagon/split-vecpred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the splitVecPredRegs pass in the Hexagon Peephole pass does not diff --git a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll index 10bd8d4701cf..161918ca3487 100644 --- a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll +++ b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; This used to crash. ; CHECK: call f1 diff --git a/llvm/test/CodeGen/Hexagon/stack-align1.ll b/llvm/test/CodeGen/Hexagon/stack-align1.ll index b4bd125c687f..cdff6f965b8e 100644 --- a/llvm/test/CodeGen/Hexagon/stack-align1.ll +++ b/llvm/test/CodeGen/Hexagon/stack-align1.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; CHECK: and(r29,#-32) ; CHECK-DAG: add(r29,#0) ; CHECK-DAG: add(r29,#28) diff --git a/llvm/test/CodeGen/Hexagon/stack-align2.ll b/llvm/test/CodeGen/Hexagon/stack-align2.ll index 5ebcbbfff527..aac6a38e39b6 100644 --- a/llvm/test/CodeGen/Hexagon/stack-align2.ll +++ b/llvm/test/CodeGen/Hexagon/stack-align2.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; CHECK: and(r29,#-128) ; CHECK-DAG: add(r29,#0) ; CHECK-DAG: add(r29,#64) diff --git a/llvm/test/CodeGen/Hexagon/stack-alloca1.ll b/llvm/test/CodeGen/Hexagon/stack-alloca1.ll index 3c2296b4038d..926ef7dc0e0b 100644 --- a/llvm/test/CodeGen/Hexagon/stack-alloca1.ll +++ b/llvm/test/CodeGen/Hexagon/stack-alloca1.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; CHECK: sub(r29,r[[REG:[0-9]+]]) ; CHECK: r29 = r[[REG]] diff --git a/llvm/test/CodeGen/Hexagon/stack-alloca2.ll b/llvm/test/CodeGen/Hexagon/stack-alloca2.ll index 40c6ba8f12fc..950372dc82c5 100644 --- a/llvm/test/CodeGen/Hexagon/stack-alloca2.ll +++ b/llvm/test/CodeGen/Hexagon/stack-alloca2.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; CHECK: r[[AP:[0-9]+]] = and(r30,#-32) ; CHECK: sub(r29,r[[SP:[0-9]+]]) ; CHECK: r29 = r[[SP]] diff --git a/llvm/test/CodeGen/Hexagon/stack-guard-acceptable-type.ll b/llvm/test/CodeGen/Hexagon/stack-guard-acceptable-type.ll index 432699065554..0fc8fc2b5edb 100644 --- a/llvm/test/CodeGen/Hexagon/stack-guard-acceptable-type.ll +++ b/llvm/test/CodeGen/Hexagon/stack-guard-acceptable-type.ll @@ -1,7 +1,7 @@ ; Check that we accept a user definition/declaration of __stack_chk_guard ; that is not the expected type (ptr) but one of the same size. ; -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: __stack_chk_fail target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/static.ll b/llvm/test/CodeGen/Hexagon/static.ll index ea88580ff892..eeca08a6cc5a 100644 --- a/llvm/test/CodeGen/Hexagon/static.ll +++ b/llvm/test/CodeGen/Hexagon/static.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s @num = external global i32 @acc = external global i32 diff --git a/llvm/test/CodeGen/Hexagon/store-AbsSet.ll b/llvm/test/CodeGen/Hexagon/store-AbsSet.ll index 6ee2c61f4488..1f4d64b1ecfa 100644 --- a/llvm/test/CodeGen/Hexagon/store-AbsSet.ll +++ b/llvm/test/CodeGen/Hexagon/store-AbsSet.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Validates correct operand order for absolute-set stores. diff --git a/llvm/test/CodeGen/Hexagon/store-abs.ll b/llvm/test/CodeGen/Hexagon/store-abs.ll index 5ef3b506ab39..6f1051e75136 100644 --- a/llvm/test/CodeGen/Hexagon/store-abs.ll +++ b/llvm/test/CodeGen/Hexagon/store-abs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s ; This lit test validates that storetrunc for a 64bit value picks a store ; absolute pattern instead of base + index store pattern. This will facilitate ; the constant extender optimization pass to move the immediate value to a register diff --git a/llvm/test/CodeGen/Hexagon/store-const-extend-opt.ll b/llvm/test/CodeGen/Hexagon/store-const-extend-opt.ll index dccf176f3bd0..9f9dba4a3956 100644 --- a/llvm/test/CodeGen/Hexagon/store-const-extend-opt.ll +++ b/llvm/test/CodeGen/Hexagon/store-const-extend-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s ; This test checks the case if there are more than 2 uses of a constan address, move the ; value in to a register and replace all instances of constant with the register. ; The GenMemAbsolute pass generates a absolute-set instruction if there are more diff --git a/llvm/test/CodeGen/Hexagon/store-constant.ll b/llvm/test/CodeGen/Hexagon/store-constant.ll index 4599f21ab37e..14d769aba479 100644 --- a/llvm/test/CodeGen/Hexagon/store-constant.ll +++ b/llvm/test/CodeGen/Hexagon/store-constant.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Generate stores with assignment of constant values. diff --git a/llvm/test/CodeGen/Hexagon/store-imm-amode.ll b/llvm/test/CodeGen/Hexagon/store-imm-amode.ll index 8dd26ae86fa2..f635d409f6b1 100644 --- a/llvm/test/CodeGen/Hexagon/store-imm-amode.ll +++ b/llvm/test/CodeGen/Hexagon/store-imm-amode.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that a store with a proper addressing mode is selected for various ; cases of storing an immediate value. diff --git a/llvm/test/CodeGen/Hexagon/store-imm-byte.ll b/llvm/test/CodeGen/Hexagon/store-imm-byte.ll index 801b8dc7d7c6..4432c17f56dd 100644 --- a/llvm/test/CodeGen/Hexagon/store-imm-byte.ll +++ b/llvm/test/CodeGen/Hexagon/store-imm-byte.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: memb{{.*}} = #-1 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/store-imm-halword.ll b/llvm/test/CodeGen/Hexagon/store-imm-halword.ll index 31701adf8914..b357c0548337 100644 --- a/llvm/test/CodeGen/Hexagon/store-imm-halword.ll +++ b/llvm/test/CodeGen/Hexagon/store-imm-halword.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: memh{{.*}} = #-1 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/store-imm-large-stack.ll b/llvm/test/CodeGen/Hexagon/store-imm-large-stack.ll index f1727e802f62..ac15dc007127 100644 --- a/llvm/test/CodeGen/Hexagon/store-imm-large-stack.ll +++ b/llvm/test/CodeGen/Hexagon/store-imm-large-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this testcase compiles successfully. ; CHECK: allocframe diff --git a/llvm/test/CodeGen/Hexagon/store-imm-stack-object.ll b/llvm/test/CodeGen/Hexagon/store-imm-stack-object.ll index bb9f7cf7e6bc..88a792ed4d9b 100644 --- a/llvm/test/CodeGen/Hexagon/store-imm-stack-object.ll +++ b/llvm/test/CodeGen/Hexagon/store-imm-stack-object.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/store-imm-word.ll b/llvm/test/CodeGen/Hexagon/store-imm-word.ll index 16006ae27848..025637f25470 100644 --- a/llvm/test/CodeGen/Hexagon/store-imm-word.ll +++ b/llvm/test/CodeGen/Hexagon/store-imm-word.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: memw{{.*}} = #-1 target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/store-shift.ll b/llvm/test/CodeGen/Hexagon/store-shift.ll index b979c6d470fc..44dad593fec9 100644 --- a/llvm/test/CodeGen/Hexagon/store-shift.ll +++ b/llvm/test/CodeGen/Hexagon/store-shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-DAG: r[[BASE:[0-9]+]] = add(r1,#1000) ; CHECK-DAG: r[[IDX0:[0-9]+]] = add(r2,#5) diff --git a/llvm/test/CodeGen/Hexagon/store-vector-pred.ll b/llvm/test/CodeGen/Hexagon/store-vector-pred.ll index 6146bf55b0ed..b4f440c0fe65 100644 --- a/llvm/test/CodeGen/Hexagon/store-vector-pred.ll +++ b/llvm/test/CodeGen/Hexagon/store-vector-pred.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-instsimplify=0 -hexagon-masked-vmem=0 < %s | FileCheck %s ; This test checks that store a vector predicate of type v128i1 is lowered ; without crashing. diff --git a/llvm/test/CodeGen/Hexagon/store-widen-aliased-load.ll b/llvm/test/CodeGen/Hexagon/store-widen-aliased-load.ll index d5d2da4d1056..b614096447eb 100644 --- a/llvm/test/CodeGen/Hexagon/store-widen-aliased-load.ll +++ b/llvm/test/CodeGen/Hexagon/store-widen-aliased-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon --combiner-store-merging=false -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon --combiner-store-merging=false -verify-machineinstrs < %s | FileCheck %s ; CHECK: memh ; Check that store widening merges the two adjacent stores. diff --git a/llvm/test/CodeGen/Hexagon/store-widen-negv.ll b/llvm/test/CodeGen/Hexagon/store-widen-negv.ll index 5cdf250aead0..7af1e4f4a218 100644 --- a/llvm/test/CodeGen/Hexagon/store-widen-negv.ll +++ b/llvm/test/CodeGen/Hexagon/store-widen-negv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; We shouldn't see a 32-bit expansion of -120, just the uint8 value. ; CHECK: #136 define i32 @foo(ptr %ptr) { diff --git a/llvm/test/CodeGen/Hexagon/store-widen-negv2.ll b/llvm/test/CodeGen/Hexagon/store-widen-negv2.ll index e6b0483c1f6f..c6e45d69ee8d 100644 --- a/llvm/test/CodeGen/Hexagon/store-widen-negv2.ll +++ b/llvm/test/CodeGen/Hexagon/store-widen-negv2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: foo: ; CHECK: memh(r0+#0){{.*}}={{.*}}#-2 ; Don't use memh(r0+#0)=##65534. diff --git a/llvm/test/CodeGen/Hexagon/store-widen-subreg.ll b/llvm/test/CodeGen/Hexagon/store-widen-subreg.ll index 86a7db484915..0d80f269798d 100644 --- a/llvm/test/CodeGen/Hexagon/store-widen-subreg.ll +++ b/llvm/test/CodeGen/Hexagon/store-widen-subreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that the store widening optimization correctly transforms to a wider ; instruction with a sub register. Recently, the store widening occurs in the diff --git a/llvm/test/CodeGen/Hexagon/store-widen.ll b/llvm/test/CodeGen/Hexagon/store-widen.ll index 9691ec316135..931adbea0063 100644 --- a/llvm/test/CodeGen/Hexagon/store-widen.ll +++ b/llvm/test/CodeGen/Hexagon/store-widen.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/store1.ll b/llvm/test/CodeGen/Hexagon/store1.ll index 7cc7a278fe86..1a34604c1619 100644 --- a/llvm/test/CodeGen/Hexagon/store1.ll +++ b/llvm/test/CodeGen/Hexagon/store1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that the immediate form for the store instructions are generated. ; diff --git a/llvm/test/CodeGen/Hexagon/store_abs.ll b/llvm/test/CodeGen/Hexagon/store_abs.ll index 8a5f7eaf86b5..22bc55cb91a7 100644 --- a/llvm/test/CodeGen/Hexagon/store_abs.ll +++ b/llvm/test/CodeGen/Hexagon/store_abs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts ; Test that the compiler doesn't assert when attempting to diff --git a/llvm/test/CodeGen/Hexagon/storerd-io-over-rr.ll b/llvm/test/CodeGen/Hexagon/storerd-io-over-rr.ll index 3b67117f0cd3..8a233e905bec 100644 --- a/llvm/test/CodeGen/Hexagon/storerd-io-over-rr.ll +++ b/llvm/test/CodeGen/Hexagon/storerd-io-over-rr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for memd(base + #offset), instead of memd(base + reg<<#c). ; CHECK: memd(r{{[0-9]+}}+# diff --git a/llvm/test/CodeGen/Hexagon/storerinewabs.ll b/llvm/test/CodeGen/Hexagon/storerinewabs.ll index 1d40459a6e6a..4ed191c78175 100644 --- a/llvm/test/CodeGen/Hexagon/storerinewabs.ll +++ b/llvm/test/CodeGen/Hexagon/storerinewabs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s @global = external global i32, align 4 diff --git a/llvm/test/CodeGen/Hexagon/struct-const.ll b/llvm/test/CodeGen/Hexagon/struct-const.ll index 273fc571bdd0..320a6d443095 100644 --- a/llvm/test/CodeGen/Hexagon/struct-const.ll +++ b/llvm/test/CodeGen/Hexagon/struct-const.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Look for only one declaration of the const struct. ; CHECK: g0: diff --git a/llvm/test/CodeGen/Hexagon/struct_args.ll b/llvm/test/CodeGen/Hexagon/struct_args.ll index ef53fbb6bb68..d27818c86032 100644 --- a/llvm/test/CodeGen/Hexagon/struct_args.ll +++ b/llvm/test/CodeGen/Hexagon/struct_args.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hsdr < %s | FileCheck %s ; CHECK-DAG: r0 = memw ; CHECK-DAG: r1 = memw diff --git a/llvm/test/CodeGen/Hexagon/struct_args_large.ll b/llvm/test/CodeGen/Hexagon/struct_args_large.ll index 567c0c3f6538..da96bf1447c1 100644 --- a/llvm/test/CodeGen/Hexagon/struct_args_large.ll +++ b/llvm/test/CodeGen/Hexagon/struct_args_large.ll @@ -1,5 +1,5 @@ ; XFAIL: * -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r[[T0:[0-9]+]] = CONST32(#s2) ; CHECK: memw(r29+#0) = r{{.}} ; CHECK: memw(r29+#8) = r{{.}} diff --git a/llvm/test/CodeGen/Hexagon/struct_copy.ll b/llvm/test/CodeGen/Hexagon/struct_copy.ll index eb2368b1bfca..7b6cd029d7ff 100644 --- a/llvm/test/CodeGen/Hexagon/struct_copy.ll +++ b/llvm/test/CodeGen/Hexagon/struct_copy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s ; Disable small-data, or otherwise g3 will end up in .sdata. While that is ; not a problem, this test was originally written with the g3 not being in ; there, so keep it that way. diff --git a/llvm/test/CodeGen/Hexagon/struct_copy_sched_r16.ll b/llvm/test/CodeGen/Hexagon/struct_copy_sched_r16.ll index 9f594207a186..7afe5e2ddd5f 100644 --- a/llvm/test/CodeGen/Hexagon/struct_copy_sched_r16.ll +++ b/llvm/test/CodeGen/Hexagon/struct_copy_sched_r16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s ; Disable small-data, or the test will need to be modified to account for g0 ; being placed there. diff --git a/llvm/test/CodeGen/Hexagon/sub-add.ll b/llvm/test/CodeGen/Hexagon/sub-add.ll index 83ade9cec0b2..7c75b0a99e24 100644 --- a/llvm/test/CodeGen/Hexagon/sub-add.ll +++ b/llvm/test/CodeGen/Hexagon/sub-add.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=hexagon -enable-timing-class-latency=true < %s | FileCheck -check-prefix=CHECK-ONE %s +; RUN: llc -mtriple=hexagon -enable-timing-class-latency=true < %s | FileCheck -check-prefix=CHECK-ONE %s ; REQUIRES: asserts ; Check there is no assert when enabling enable-timing-class-latency ; CHECK-ONE: f0: -; RUN: llc -march=hexagon < %s | FileCheck -check-prefix=CHECK %s +; RUN: llc -mtriple=hexagon < %s | FileCheck -check-prefix=CHECK %s ; CHECK: add(r{{[0-9]*}},sub(#1,r{{[0-9]*}}) ; CHECK: call f1 diff --git a/llvm/test/CodeGen/Hexagon/subh-shifted.ll b/llvm/test/CodeGen/Hexagon/subh-shifted.ll index c274cc4e6216..575ba4a78006 100644 --- a/llvm/test/CodeGen/Hexagon/subh-shifted.ll +++ b/llvm/test/CodeGen/Hexagon/subh-shifted.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = sub(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}):<<16 ; Function Attrs: nounwind readnone diff --git a/llvm/test/CodeGen/Hexagon/subh.ll b/llvm/test/CodeGen/Hexagon/subh.ll index 299687d7592d..b0265c448a00 100644 --- a/llvm/test/CodeGen/Hexagon/subh.ll +++ b/llvm/test/CodeGen/Hexagon/subh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: r{{[0-9]+}} = sub(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}) ; Function Attrs: nounwind readnone diff --git a/llvm/test/CodeGen/Hexagon/subi-asl.ll b/llvm/test/CodeGen/Hexagon/subi-asl.ll index eb564c399bbe..b1157d5a3c07 100644 --- a/llvm/test/CodeGen/Hexagon/subi-asl.ll +++ b/llvm/test/CodeGen/Hexagon/subi-asl.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check if S4_subi_asl_ri is being generated correctly. diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll index 66a2c1eb9d45..0a8e28af5de6 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll @@ -5,7 +5,6 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon-unknown--elf" -;FUNCTEXT: .text ;FUNCTEXT: .section{{.*}}tcm.hexagon, ;FUNCTEXT-NOT: .section{{.*}}.rodata ;FUNCTEXT-NOT: .text diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll index 0b2afa75cedf..42e2c3044595 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll @@ -4,7 +4,6 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon-unknown--elf" -;FUNCTEXT: .text ;FUNCTEXT: .section{{.*}}text.foo, ;FUNCTEXT-NOT: .section{{.*}}.rodata ;FUNCTEXT: .Lswitch.table: diff --git a/llvm/test/CodeGen/Hexagon/swp-art-deps-rec.ll b/llvm/test/CodeGen/Hexagon/swp-art-deps-rec.ll index dee2695cdae9..aebd2fa15508 100644 --- a/llvm/test/CodeGen/Hexagon/swp-art-deps-rec.ll +++ b/llvm/test/CodeGen/Hexagon/swp-art-deps-rec.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: llc -march=hexagon -mcpu=hexagonv65 -O3 -debug-only=pipeliner \ +; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -O3 -debug-only=pipeliner \ ; RUN: < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s ; As part of https://reviews.llvm.org/D106308 this test broke. diff --git a/llvm/test/CodeGen/Hexagon/swp-bad-sched.ll b/llvm/test/CodeGen/Hexagon/swp-bad-sched.ll index e4e4bcda4cee..6a2b361316d7 100644 --- a/llvm/test/CodeGen/Hexagon/swp-bad-sched.ll +++ b/llvm/test/CodeGen/Hexagon/swp-bad-sched.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -march=hexagon -enable-pipeliner -enable-aa-sched-mi < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -enable-aa-sched-mi < %s -pipeliner-experimental-cg=true | FileCheck %s ; CHECK: loop0( ; CHECK: loop0(.LBB0_[[LOOP:.]], diff --git a/llvm/test/CodeGen/Hexagon/swp-badorder.ll b/llvm/test/CodeGen/Hexagon/swp-badorder.ll index 07f394d9f85d..e7b3933d4149 100644 --- a/llvm/test/CodeGen/Hexagon/swp-badorder.ll +++ b/llvm/test/CodeGen/Hexagon/swp-badorder.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/swp-carried-1.ll b/llvm/test/CodeGen/Hexagon/swp-carried-1.ll index 33a6af0e0d43..6993bd672c01 100644 --- a/llvm/test/CodeGen/Hexagon/swp-carried-1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-carried-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -rdf-opt=0 -disable-hexagon-misched -hexagon-initial-cfg-cleanup=0 -lsr-setupcost-depth-limit=1 -disable-cgp-delete-phis < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -rdf-opt=0 -disable-hexagon-misched -hexagon-initial-cfg-cleanup=0 -lsr-setupcost-depth-limit=1 -disable-cgp-delete-phis < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we generate the correct code when a loop carried value ; is scheduled one stage earlier than it's use. The code in diff --git a/llvm/test/CodeGen/Hexagon/swp-chain-refs.ll b/llvm/test/CodeGen/Hexagon/swp-chain-refs.ll index 966ff2398ec2..a508e00a2354 100644 --- a/llvm/test/CodeGen/Hexagon/swp-chain-refs.ll +++ b/llvm/test/CodeGen/Hexagon/swp-chain-refs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner=true -stats -o /dev/null < %s \ +; RUN: llc -mtriple=hexagon -enable-pipeliner=true -stats -o /dev/null < %s \ ; RUN: 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/swp-change-dep-cycle.ll b/llvm/test/CodeGen/Hexagon/swp-change-dep-cycle.ll index 9a0551eac9a8..f9c3551927bf 100644 --- a/llvm/test/CodeGen/Hexagon/swp-change-dep-cycle.ll +++ b/llvm/test/CodeGen/Hexagon/swp-change-dep-cycle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts ; Don't change the dependences if it's going to cause a cycle. diff --git a/llvm/test/CodeGen/Hexagon/swp-change-dep.ll b/llvm/test/CodeGen/Hexagon/swp-change-dep.ll index d75b8459589a..83a716e1b7a0 100644 --- a/llvm/test/CodeGen/Hexagon/swp-change-dep.ll +++ b/llvm/test/CodeGen/Hexagon/swp-change-dep.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-aa-sched-mi -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-aa-sched-mi -enable-pipeliner < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/swp-change-dep1.ll b/llvm/test/CodeGen/Hexagon/swp-change-dep1.ll index 8c7fa707b35e..c5dc09df41af 100644 --- a/llvm/test/CodeGen/Hexagon/swp-change-dep1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-change-dep1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=1 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -pipeliner-max-stages=1 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we update the offset correctly for loads that are ; moved past stores. In these cases, we change the dependences diff --git a/llvm/test/CodeGen/Hexagon/swp-change-deps.ll b/llvm/test/CodeGen/Hexagon/swp-change-deps.ll index 704a5b2b8f3c..2fef6bd5ee9b 100644 --- a/llvm/test/CodeGen/Hexagon/swp-change-deps.ll +++ b/llvm/test/CodeGen/Hexagon/swp-change-deps.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we generate the correct offsets for loads in the prolog ; after removing dependences on a post-increment instructions of the diff --git a/llvm/test/CodeGen/Hexagon/swp-check-offset.ll b/llvm/test/CodeGen/Hexagon/swp-check-offset.ll index 5fe2f3672301..bf0dd4ee540e 100644 --- a/llvm/test/CodeGen/Hexagon/swp-check-offset.ll +++ b/llvm/test/CodeGen/Hexagon/swp-check-offset.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv62 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V62 %s -; RUN: llc -march=hexagon -mcpu=hexagonv65 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V65 %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V62 %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V65 %s ; ; Make sure we pipeline the loop and that we generate the correct diff --git a/llvm/test/CodeGen/Hexagon/swp-const-tc.ll b/llvm/test/CodeGen/Hexagon/swp-const-tc.ll index 44e0a8983366..9426f44d38ed 100644 --- a/llvm/test/CodeGen/Hexagon/swp-const-tc.ll +++ b/llvm/test/CodeGen/Hexagon/swp-const-tc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner -verify-machineinstrs < %s | FileCheck %s ; If the trip count is a compile-time constant, then decrement it instead ; of computing a new LC0 value. diff --git a/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll b/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll index 9b6c91f6326e..4b8d756e9331 100644 --- a/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-const-tc1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -enable-pipeliner-opt-size \ +; RUN: llc -mtriple=hexagon -enable-pipeliner -enable-pipeliner-opt-size \ ; RUN: -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 \ ; RUN: -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \ ; RUN: < %s -pipeliner-experimental-cg=true | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-const-tc2.ll b/llvm/test/CodeGen/Hexagon/swp-const-tc2.ll index 859cc7eb17b6..1799151924ad 100644 --- a/llvm/test/CodeGen/Hexagon/swp-const-tc2.ll +++ b/llvm/test/CodeGen/Hexagon/swp-const-tc2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true -hoist-const-loads=false | FileCheck %s +; RUN: llc -mtriple=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true -hoist-const-loads=false | FileCheck %s ; Test that we fixup a pipelined loop correctly when the number of ; stages is greater than the compile-time loop trip count. In this diff --git a/llvm/test/CodeGen/Hexagon/swp-const-tc3.ll b/llvm/test/CodeGen/Hexagon/swp-const-tc3.ll index c7fdf18d116d..9ffe9fe70146 100644 --- a/llvm/test/CodeGen/Hexagon/swp-const-tc3.ll +++ b/llvm/test/CodeGen/Hexagon/swp-const-tc3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the pipeliner correctly fixes up the pipelined CFG when the loop ; has a constant trip count, and the trip count is less than the number of diff --git a/llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll b/llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll index 1562f1872ceb..006a8b6bfc94 100644 --- a/llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll +++ b/llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; This version of the conv3x3 test has both loops. This test checks that the ; inner loop has 14 packets. diff --git a/llvm/test/CodeGen/Hexagon/swp-copytophi-dag.ll b/llvm/test/CodeGen/Hexagon/swp-copytophi-dag.ll index 4ee05a8e7c84..7c9ecd5c3fde 100644 --- a/llvm/test/CodeGen/Hexagon/swp-copytophi-dag.ll +++ b/llvm/test/CodeGen/Hexagon/swp-copytophi-dag.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts ; -; RUN: llc -march=hexagon -enable-pipeliner=true -debug-only=pipeliner < %s \ +; RUN: llc -mtriple=hexagon -enable-pipeliner=true -debug-only=pipeliner < %s \ ; RUN: 2>&1 -pipeliner-experimental-cg=true | FileCheck %s ; Test that the artificial dependence is created as a result of diff --git a/llvm/test/CodeGen/Hexagon/swp-crash-iter.ll b/llvm/test/CodeGen/Hexagon/swp-crash-iter.ll index b2a8e40bd72b..9c5af2678ad7 100644 --- a/llvm/test/CodeGen/Hexagon/swp-crash-iter.ll +++ b/llvm/test/CodeGen/Hexagon/swp-crash-iter.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -march=hexagon -enable-pipeliner -o /dev/null < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -o /dev/null < %s ; Test that we do not crash when running CopyToPhi DAG mutation due to ; iterator invalidation. diff --git a/llvm/test/CodeGen/Hexagon/swp-cse-phi.ll b/llvm/test/CodeGen/Hexagon/swp-cse-phi.ll index b6d9bb344ae6..57cc15baf812 100644 --- a/llvm/test/CodeGen/Hexagon/swp-cse-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-cse-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; This test checks that we don't assert when the Phi value from the diff --git a/llvm/test/CodeGen/Hexagon/swp-dag-phi.ll b/llvm/test/CodeGen/Hexagon/swp-dag-phi.ll index 40511ea097ef..4ba56779f6a9 100644 --- a/llvm/test/CodeGen/Hexagon/swp-dag-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-dag-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 < %s ; REQUIRES: asserts ; This tests check that a dependence is created between a Phi and it's uses. diff --git a/llvm/test/CodeGen/Hexagon/swp-dag-phi1.ll b/llvm/test/CodeGen/Hexagon/swp-dag-phi1.ll index 4a67ca62513e..82b1a234a2af 100644 --- a/llvm/test/CodeGen/Hexagon/swp-dag-phi1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-dag-phi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; This test check that a dependence is created between a Phi and it's uses. diff --git a/llvm/test/CodeGen/Hexagon/swp-dead-regseq.ll b/llvm/test/CodeGen/Hexagon/swp-dead-regseq.ll index 3e30bcd241d2..0db63883f28a 100644 --- a/llvm/test/CodeGen/Hexagon/swp-dead-regseq.ll +++ b/llvm/test/CodeGen/Hexagon/swp-dead-regseq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Check that a dead REG_SEQUENCE doesn't ICE. diff --git a/llvm/test/CodeGen/Hexagon/swp-dep-neg-offset.ll b/llvm/test/CodeGen/Hexagon/swp-dep-neg-offset.ll index 109f7c410da8..ee2db94e26c6 100644 --- a/llvm/test/CodeGen/Hexagon/swp-dep-neg-offset.ll +++ b/llvm/test/CodeGen/Hexagon/swp-dep-neg-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the code that changes the dependences does not allow ; a load with a negative offset to be overlapped with the post diff --git a/llvm/test/CodeGen/Hexagon/swp-disable-Os.ll b/llvm/test/CodeGen/Hexagon/swp-disable-Os.ll index 838202e71c50..7591d0d3d911 100644 --- a/llvm/test/CodeGen/Hexagon/swp-disable-Os.ll +++ b/llvm/test/CodeGen/Hexagon/swp-disable-Os.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; CHECK: loop0(.LBB0_{{[0-9]+}},#347) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-numphis.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-numphis.ll index 030ef52c823a..e04c0d9e52e5 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-numphis.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-numphis.ll @@ -1,6 +1,6 @@ ; XFAIL: * ; Needs some fixed in the pipeliner. -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; CHECK: endloop0 ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi10.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi10.ll index 92ef455ee00f..ddf31ec8d9a3 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi10.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi10.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -simplifycfg-require-and-preserve-domtree=1 < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -simplifycfg-require-and-preserve-domtree=1 < %s ; REQUIRES: asserts define void @test(ptr noalias nocapture readonly %src, i32 %srcStride) local_unnamed_addr #0 { diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll index 2ebbec5c613b..0a2d1f16bcbf 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi12.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true -disable-cgp-delete-phis < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true -disable-cgp-delete-phis < %s | FileCheck %s ; Test epilogue generation when reading loop-carried dependency from a previous ; stage. The first epilogue should read value from iteration N-1 of the kernel. diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll index 663293220209..82a1067beced 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi13.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s ; Test epilogue generation when reading loop-carried dependency in stage 1 from ; stage 0. Make sure the illegal phi the expender creates gets cleaned up diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll index e1777d0e0b26..41a39155b1a9 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=3 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -pipeliner-max-stages=3 < %s -pipeliner-experimental-cg=true | FileCheck %s %s.0 = type { i16, i8, i8, i16, i8, i8, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i16, i8, i8, %s.1, [2 x [16 x %s.2]], ptr, ptr, ptr, [120 x i8], i8, i8, ptr, [2 x [120 x [8 x i8]]], [56 x i8], [2 x [121 x %s.5]], [2 x %s.5], ptr, ptr, i32, i32, i16, i8, i8, %s.7, %s.9, %s.11, ptr, ptr } %s.1 = type { i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, [16 x i8], i8, [4 x i8], [32 x i16], [32 x i16], [2 x i8], [4 x i8], [2 x [4 x i8]], [2 x [4 x i8]], i32, i32, i16, i8 } diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi4.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi4.ll index ee253fa0885d..7b6c462d8037 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we generate the correct value for a Phi in the epilog ; that is for a value defined two stages earlier. An extra copy in the diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi5.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi5.ll index b193ce60a92e..b6add0e1c20d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi5.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi5.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we use the correct name in an epilog phi for a phi value ; that is defined for the last time in the kernel. Previously, we diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll index 0a209339d646..424c6e448e76 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi6.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -debug-only=pipeliner -hexagon-initial-cfg-cleanup=0 -disable-cgp-delete-phis < %s -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -debug-only=pipeliner -hexagon-initial-cfg-cleanup=0 -disable-cgp-delete-phis < %s -o - 2>&1 > /dev/null | FileCheck %s ; REQUIRES: asserts ; Test that the phi in the first epilog block is getter the correct diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll index 8d7958e4747d..96a38939dc50 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi7.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -enable-pipeliner -disable-block-placement=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -enable-pipeliner -disable-block-placement=0 < %s | FileCheck %s ; For the Phis generated in the epilog, test that we generate the correct ; names for the values coming from the prolog stages. The test belows diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll index 74bbdb99e1ba..76434e79ad99 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mno-pairing -mno-compound -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mno-pairing -mno-compound -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; XFAIL: * ; Test that we generate the correct phi names in the epilog when the pipeliner diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll index 6dd08df7787a..af1b848a8cf2 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-phi9.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -disable-cgp-delete-phis < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -disable-cgp-delete-phis < %s | FileCheck %s ; Test that we generate the correct Phi name in the last couple of epilog ; blocks, when there are 3 epilog blocks. The Phi was scheduled in stage diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll index d09ce2799a9b..06b01928bf56 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 < %s ; REQUIRES: asserts ; Test that the pipeliner reuses an existing Phi when generating the epilog diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll index 4f20153b5506..9ae6fa01148d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse.ll @@ -1,4 +1,4 @@ -; RUN: llc -fp-contract=fast -O3 -march=hexagon -mcpu=hexagonv5 < %s +; RUN: llc -fp-contract=fast -O3 -mtriple=hexagon -mcpu=hexagonv5 < %s ; REQUIRES: asserts ; Test that the pipeliner doesn't ICE due because the PHI generation diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll index 96663508b3c5..3a5afb7dcb72 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse2.ll @@ -1,4 +1,4 @@ -; RUN: llc -fp-contract=fast -O3 -march=hexagon < %s +; RUN: llc -fp-contract=fast -O3 -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the pipeliner doesn't ICE due because the PHI generation diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse3.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse3.ll index 461dce491b0e..960187d007b3 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse3.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Test that the pipeliner doesn't ICE due to incorrect PHI diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse4.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse4.ll index 404b7d87bd59..19f297725fba 100644 --- a/llvm/test/CodeGen/Hexagon/swp-epilog-reuse4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-epilog-reuse4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -hexagon-expand-condsets=0 < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -hexagon-expand-condsets=0 < %s ; REQUIRES: asserts ; Disable expand-condsets because it will assert on undefined registers. diff --git a/llvm/test/CodeGen/Hexagon/swp-exit-fixup.ll b/llvm/test/CodeGen/Hexagon/swp-exit-fixup.ll index 27327a9ca439..015579bd2c3e 100644 --- a/llvm/test/CodeGen/Hexagon/swp-exit-fixup.ll +++ b/llvm/test/CodeGen/Hexagon/swp-exit-fixup.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Make sure we fix up the Phis when we connect the last diff --git a/llvm/test/CodeGen/Hexagon/swp-fix-last-use.ll b/llvm/test/CodeGen/Hexagon/swp-fix-last-use.ll index 6ac3ac9ad950..235f07075396 100644 --- a/llvm/test/CodeGen/Hexagon/swp-fix-last-use.ll +++ b/llvm/test/CodeGen/Hexagon/swp-fix-last-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; We need to rename uses that occurs after the loop. diff --git a/llvm/test/CodeGen/Hexagon/swp-fix-last-use1.ll b/llvm/test/CodeGen/Hexagon/swp-fix-last-use1.ll index 721e581c1db0..fb09f6c004fe 100644 --- a/llvm/test/CodeGen/Hexagon/swp-fix-last-use1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-fix-last-use1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/swp-intreglow8.ll b/llvm/test/CodeGen/Hexagon/swp-intreglow8.ll index e34db9f90bd7..2970269e2cd7 100644 --- a/llvm/test/CodeGen/Hexagon/swp-intreglow8.ll +++ b/llvm/test/CodeGen/Hexagon/swp-intreglow8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -verify-machineinstrs < %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s ; REQUIRES: asserts ; Test that we constrain the new register operands for instructions diff --git a/llvm/test/CodeGen/Hexagon/swp-kernel-last-use.ll b/llvm/test/CodeGen/Hexagon/swp-kernel-last-use.ll index b7923ce3faca..62069416770a 100644 --- a/llvm/test/CodeGen/Hexagon/swp-kernel-last-use.ll +++ b/llvm/test/CodeGen/Hexagon/swp-kernel-last-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; This test caused an assert because there was a use of an instruction diff --git a/llvm/test/CodeGen/Hexagon/swp-kernel-phi1.ll b/llvm/test/CodeGen/Hexagon/swp-kernel-phi1.ll index e70fd61df167..6ca8e94200b7 100644 --- a/llvm/test/CodeGen/Hexagon/swp-kernel-phi1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-kernel-phi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner-opt-size -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner-opt-size -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we generate the correct names for the phis in the kernel for the ; incoming values. In this case, the loop contains a phi and has another phi diff --git a/llvm/test/CodeGen/Hexagon/swp-large-rec.ll b/llvm/test/CodeGen/Hexagon/swp-large-rec.ll index 5bdcad49aae5..9717e446d481 100644 --- a/llvm/test/CodeGen/Hexagon/swp-large-rec.ll +++ b/llvm/test/CodeGen/Hexagon/swp-large-rec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -stats \ +; RUN: llc -mtriple=hexagon -enable-pipeliner -stats \ ; RUN: -pipeliner-prune-loop-carried=false -fp-contract=fast \ ; RUN: -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/swp-listen-loop3.ll b/llvm/test/CodeGen/Hexagon/swp-listen-loop3.ll index d4867e205337..616c5a510ce7 100644 --- a/llvm/test/CodeGen/Hexagon/swp-listen-loop3.ll +++ b/llvm/test/CodeGen/Hexagon/swp-listen-loop3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -pipeliner-ignore-recmii -pipeliner-max-stages=2 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -pipeliner-ignore-recmii -pipeliner-max-stages=2 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s ; This is a loop we pipeline to three packets, though we could do bettter. diff --git a/llvm/test/CodeGen/Hexagon/swp-loop-carried-crash.ll b/llvm/test/CodeGen/Hexagon/swp-loop-carried-crash.ll index 3066c26667fa..9fef0b132be4 100644 --- a/llvm/test/CodeGen/Hexagon/swp-loop-carried-crash.ll +++ b/llvm/test/CodeGen/Hexagon/swp-loop-carried-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the pipeliner doesn't assert in the addLoopCarriedDependence diff --git a/llvm/test/CodeGen/Hexagon/swp-loop-carried-unknown.ll b/llvm/test/CodeGen/Hexagon/swp-loop-carried-unknown.ll index ecc81fca5501..4983af748250 100644 --- a/llvm/test/CodeGen/Hexagon/swp-loop-carried-unknown.ll +++ b/llvm/test/CodeGen/Hexagon/swp-loop-carried-unknown.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the pipeliner schedules a store before the load in which there is a ; loop carried dependence. Previously, the loop carried dependence wasn't added diff --git a/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll b/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll index 062ea3ba4926..64c34f246f32 100644 --- a/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll +++ b/llvm/test/CodeGen/Hexagon/swp-loop-carried.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -fp-contract=fast -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -fp-contract=fast -enable-pipeliner < %s ; REQUIRES: asserts ; A Phi that depends on another Phi is loop carried. diff --git a/llvm/test/CodeGen/Hexagon/swp-loopval.ll b/llvm/test/CodeGen/Hexagon/swp-loopval.ll index 6ede28af02c4..7757bed5f3a9 100644 --- a/llvm/test/CodeGen/Hexagon/swp-loopval.ll +++ b/llvm/test/CodeGen/Hexagon/swp-loopval.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Check that we correctly rename instructions that use a Phi's loop value, diff --git a/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll b/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll index b4e3d1a79ebb..f5f480d161a9 100644 --- a/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll +++ b/llvm/test/CodeGen/Hexagon/swp-lots-deps.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s --check-prefix=STATS +; RUN: llc -mtriple=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s --check-prefix=STATS ; REQUIRES: asserts ; STATS: 1 pipeliner - Number of loops software pipelined diff --git a/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll b/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll index 9f2e3533525a..42efe60b96d4 100644 --- a/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll +++ b/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s | FileCheck %s ; From coremark. Test that we pipeline the matrix multiplication bitextract ; function. The pipelined code should have two packets. diff --git a/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll b/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll index 3b3a7495d489..e027616b9976 100644 --- a/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll +++ b/llvm/test/CodeGen/Hexagon/swp-max-stage3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -fp-contract=fast -pipeliner-max-stages=3 < %s +; RUN: llc -mtriple=hexagon -O3 -fp-contract=fast -pipeliner-max-stages=3 < %s ; REQUIRES: asserts ; Check Phis are generated correctly in epilogs after setting -swp-max-stages=3 diff --git a/llvm/test/CodeGen/Hexagon/swp-max.ll b/llvm/test/CodeGen/Hexagon/swp-max.ll index 2376cc50e325..99c312101192 100644 --- a/llvm/test/CodeGen/Hexagon/swp-max.ll +++ b/llvm/test/CodeGen/Hexagon/swp-max.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner \ +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner \ ; RUN: -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s @A = global [8 x i32] [i32 4, i32 -3, i32 5, i32 -2, i32 -1, i32 2, i32 6, i32 -2], align 8 diff --git a/llvm/test/CodeGen/Hexagon/swp-maxstart.ll b/llvm/test/CodeGen/Hexagon/swp-maxstart.ll index 9364fc45f0ef..db9f55c27645 100644 --- a/llvm/test/CodeGen/Hexagon/swp-maxstart.ll +++ b/llvm/test/CodeGen/Hexagon/swp-maxstart.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the MinStart computation, which is based upon the length ; of the chain edges, is computed correctly. A bug in the code allowed diff --git a/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll b/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll index adbcfa5158c5..c9613156a4df 100644 --- a/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll +++ b/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -fp-contract=fast < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -fp-contract=fast < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the memoperands for instructions in the epilog are updated ; correctly. Previously, the pipeliner updated the offset for the memoperands diff --git a/llvm/test/CodeGen/Hexagon/swp-more-phi.ll b/llvm/test/CodeGen/Hexagon/swp-more-phi.ll index 5612e9f1b11d..3d616945f3c4 100644 --- a/llvm/test/CodeGen/Hexagon/swp-more-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-more-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon --enable-pipeliner -hexagon-expand-condsets=0 < %s +; RUN: llc -mtriple=hexagon --enable-pipeliner -hexagon-expand-condsets=0 < %s ; REQUIRES: asserts ; Disable expand-condsets because it will assert on undefined registers. diff --git a/llvm/test/CodeGen/Hexagon/swp-multi-loops.ll b/llvm/test/CodeGen/Hexagon/swp-multi-loops.ll index c356353a0264..e6c13013807f 100644 --- a/llvm/test/CodeGen/Hexagon/swp-multi-loops.ll +++ b/llvm/test/CodeGen/Hexagon/swp-multi-loops.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s ; Make sure we attempt to pipeline all inner most loops. diff --git a/llvm/test/CodeGen/Hexagon/swp-multi-phi-refs.ll b/llvm/test/CodeGen/Hexagon/swp-multi-phi-refs.ll index b4f08c2dd7d7..8eaa45f45046 100644 --- a/llvm/test/CodeGen/Hexagon/swp-multi-phi-refs.ll +++ b/llvm/test/CodeGen/Hexagon/swp-multi-phi-refs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts ; Test that we generate the correct names for Phis when there is diff --git a/llvm/test/CodeGen/Hexagon/swp-new-phi.ll b/llvm/test/CodeGen/Hexagon/swp-new-phi.ll index f877722cdf78..e168ee755d48 100644 --- a/llvm/test/CodeGen/Hexagon/swp-new-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-new-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the generatePhi code doesn't rename a a Phi instruction that's defined ; in the same block. The bug causes a Phi to incorrectly depend on another Phi. diff --git a/llvm/test/CodeGen/Hexagon/swp-node-order.ll b/llvm/test/CodeGen/Hexagon/swp-node-order.ll index a7719eddf12e..8d0a27f40610 100644 --- a/llvm/test/CodeGen/Hexagon/swp-node-order.ll +++ b/llvm/test/CodeGen/Hexagon/swp-node-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Test that we include all the nodes in the final node ordering diff --git a/llvm/test/CodeGen/Hexagon/swp-order-carried.ll b/llvm/test/CodeGen/Hexagon/swp-order-carried.ll index f496b9fc7873..86c061878cc0 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-carried.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-carried.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that we order instruction within a packet correctly. In this case, diff --git a/llvm/test/CodeGen/Hexagon/swp-order-copies.ll b/llvm/test/CodeGen/Hexagon/swp-order-copies.ll index c667bf50a19f..1c9cc4a1cf9d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-copies.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-copies.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the instruction ordering code in the pipeliner fixes up dependences ; between post-increment register definitions and uses so that the register diff --git a/llvm/test/CodeGen/Hexagon/swp-order-deps1.ll b/llvm/test/CodeGen/Hexagon/swp-order-deps1.ll index 7316deaa1584..a48d2fccc437 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-deps1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-deps1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Check that the dependences are order correctly, and the list can be diff --git a/llvm/test/CodeGen/Hexagon/swp-order-deps3.ll b/llvm/test/CodeGen/Hexagon/swp-order-deps3.ll index 5236606aeffb..d118b1b88917 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-deps3.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-deps3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s +; RUN: llc -mtriple=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s ; REQUIRES: asserts ; Function Attrs: noinline nounwind ssp diff --git a/llvm/test/CodeGen/Hexagon/swp-order-deps4.ll b/llvm/test/CodeGen/Hexagon/swp-order-deps4.ll index ce231f3a60a6..44dc240aea79 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-deps4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-deps4.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s +; RUN: llc -O2 -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the final instruction ordering code does not result in infinite diff --git a/llvm/test/CodeGen/Hexagon/swp-order-deps5.ll b/llvm/test/CodeGen/Hexagon/swp-order-deps5.ll index c90cf2f9418d..04b1db4307fe 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-deps5.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-deps5.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-bit=0 < %s +; RUN: llc -mtriple=hexagon -hexagon-bit=0 < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/swp-order-deps6.ll b/llvm/test/CodeGen/Hexagon/swp-order-deps6.ll index e23de951f044..006391946635 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-deps6.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-deps6.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts %s.0 = type { i64 } diff --git a/llvm/test/CodeGen/Hexagon/swp-order-deps7.ll b/llvm/test/CodeGen/Hexagon/swp-order-deps7.ll index efac1e71c94c..5f1780fce39d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-deps7.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-deps7.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the pipeliner cause an assert and correctly pipelines the ; loop. diff --git a/llvm/test/CodeGen/Hexagon/swp-order-prec.ll b/llvm/test/CodeGen/Hexagon/swp-order-prec.ll index 6662a868567b..00ada9159f9c 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order-prec.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order-prec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the pipeliner doesn't assert in orderDependence because diff --git a/llvm/test/CodeGen/Hexagon/swp-order.ll b/llvm/test/CodeGen/Hexagon/swp-order.ll index ce7888cb338c..1ae24278a46b 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that when we order instructions in a packet we check for ; order dependences so that the source of an order dependence diff --git a/llvm/test/CodeGen/Hexagon/swp-order1.ll b/llvm/test/CodeGen/Hexagon/swp-order1.ll index 96341c63ec24..bb6d73344e1d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-order1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-order1.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s +; RUN: llc -O2 -mtriple=hexagon < %s ; REQUIRES: asserts %0 = type { [2 x [8 x [16 x i8]]], [4 x [16 x ptr]] } diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-ch-offset.ll b/llvm/test/CodeGen/Hexagon/swp-phi-ch-offset.ll index 3c909f31bda9..960db64a281f 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-ch-offset.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-ch-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we generate the correct offsets after we removed unneeded ; chain dependences between Phis and generated a better pipeline. diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-chains.ll b/llvm/test/CodeGen/Hexagon/swp-phi-chains.ll index 34f79dcc8910..07b5853cede9 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-chains.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-chains.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug-only=pipeliner < %s -o - 2>&1 -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -debug-only=pipeliner < %s -o - 2>&1 -pipeliner-experimental-cg=true | FileCheck %s ; REQUIRES: asserts ; Test that there is a chain edge between two dependent Phis. diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-def-use.ll b/llvm/test/CodeGen/Hexagon/swp-phi-def-use.ll index 62069eab0793..a06aa1b5d3b7 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-def-use.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-def-use.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that the pipeliner doesn't assert when renaming a phi diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-dep.ll b/llvm/test/CodeGen/Hexagon/swp-phi-dep.ll index 0c4707819392..8589cc96e695 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-dep.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-dep.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -enable-pipeliner -pipeliner-max-stages=2 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Check that the pipelined code uses the proper address in the ; prolog and the kernel. The bug occurs when the address computation diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-dep1.ll b/llvm/test/CodeGen/Hexagon/swp-phi-dep1.ll index 3d1e33d49534..863573cab2a6 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-dep1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-dep1.ll @@ -1,4 +1,4 @@ -; RUN: llc -disable-lsr -march=hexagon -enable-aa-sched-mi -O2 < %s +; RUN: llc -disable-lsr -mtriple=hexagon -enable-aa-sched-mi -O2 < %s ; REQUIRES: asserts ; Test when there is a Phi operand that is defined by another Phi, but diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-order.ll b/llvm/test/CodeGen/Hexagon/swp-phi-order.ll index 5dc01ab5eb8e..19d0613b9c5d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-order.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-order.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts %s.0 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, [49 x i8], [49 x i8], [25 x i8], [6 x i8], [29 x i8], i8, [6 x i8], [6 x i8] } diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-ref.ll b/llvm/test/CodeGen/Hexagon/swp-phi-ref.ll index 1b942ed7aa5c..6d790a45f1d6 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-ref.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-ref.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -enable-bsb-sched=0 -join-liveintervals=false < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -enable-bsb-sched=0 -join-liveintervals=false < %s -pipeliner-experimental-cg=true | FileCheck %s ; XFAIL: * ; This test is failing after post-ra machine sinking. diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-ref1.ll b/llvm/test/CodeGen/Hexagon/swp-phi-ref1.ll index bdd7aa77547f..0fc5d59daff1 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-ref1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-ref1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mno-pairing -mno-compound < %s +; RUN: llc -mtriple=hexagon -mno-pairing -mno-compound < %s ; REQUIRES: asserts ; Test that the SWP doesn't assert when generating new phis. In this example, a diff --git a/llvm/test/CodeGen/Hexagon/swp-phi-start.ll b/llvm/test/CodeGen/Hexagon/swp-phi-start.ll index 8ab1424cea19..52c258656ec2 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi-start.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi-start.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 -disable-packetizer < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -pipeliner-max-stages=2 -disable-packetizer < %s | FileCheck %s ; Test that the early start and late start values are computed correctly ; when a Phi depends on another Phi. In this case, they should occur in diff --git a/llvm/test/CodeGen/Hexagon/swp-phi.ll b/llvm/test/CodeGen/Hexagon/swp-phi.ll index 9606a2407e47..9b0e1262c73f 100644 --- a/llvm/test/CodeGen/Hexagon/swp-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-unsafe-fp-math -enable-pipeliner \ +; RUN: llc -mtriple=hexagon -enable-unsafe-fp-math -enable-pipeliner \ ; RUN: -pipeliner-prune-deps=false -stats -o /dev/null < %s ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/swp-physreg.ll b/llvm/test/CodeGen/Hexagon/swp-physreg.ll index 407acff508ae..d15de3464f6a 100644 --- a/llvm/test/CodeGen/Hexagon/swp-physreg.ll +++ b/llvm/test/CodeGen/Hexagon/swp-physreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Make sure pipeliner handle physical registers (e.g., used in diff --git a/llvm/test/CodeGen/Hexagon/swp-pragma-disable-bug.ll b/llvm/test/CodeGen/Hexagon/swp-pragma-disable-bug.ll index 7fd94a9b26c9..e6d3ae6baf02 100644 --- a/llvm/test/CodeGen/Hexagon/swp-pragma-disable-bug.ll +++ b/llvm/test/CodeGen/Hexagon/swp-pragma-disable-bug.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon -enable-pipeliner \ +; RUN: llc -O2 -mtriple=hexagon -enable-pipeliner \ ; RUN: -debug-only=pipeliner < %s 2>&1 > /dev/null | FileCheck %s ; REQUIRES: asserts ; diff --git a/llvm/test/CodeGen/Hexagon/swp-pragma-disable.ii b/llvm/test/CodeGen/Hexagon/swp-pragma-disable.ii index b97065c129b0..5938c26923fa 100644 --- a/llvm/test/CodeGen/Hexagon/swp-pragma-disable.ii +++ b/llvm/test/CodeGen/Hexagon/swp-pragma-disable.ii @@ -1,4 +1,4 @@ -; RUN: llc -disable-lsr -march=hexagon -enable-pipeliner \ +; RUN: llc -disable-lsr -mtriple=hexagon -enable-pipeliner \ ; RUN: -debug-only=pipeliner < %s 2>&1 > /dev/null -pipeliner-experimental-cg=true | FileCheck %s ; REQUIRES: asserts ; diff --git a/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval-reset.ii b/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval-reset.ii index 03c2a13f77f2..875bf390ba4c 100644 --- a/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval-reset.ii +++ b/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval-reset.ii @@ -1,4 +1,4 @@ -; RUN: llc -disable-lsr -march=hexagon -enable-pipeliner \ +; RUN: llc -disable-lsr -mtriple=hexagon -enable-pipeliner \ ; RUN: -debug-only=pipeliner < %s 2>&1 > /dev/null -pipeliner-experimental-cg=true | FileCheck %s ; REQUIRES: asserts ; diff --git a/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval.ii b/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval.ii index 2c6b606a99f7..b03302067744 100644 --- a/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval.ii +++ b/llvm/test/CodeGen/Hexagon/swp-pragma-initiation-interval.ii @@ -1,4 +1,4 @@ -; RUN: llc -disable-lsr -march=hexagon -enable-pipeliner \ +; RUN: llc -disable-lsr -mtriple=hexagon -enable-pipeliner \ ; RUN: -debug-only=pipeliner < %s 2>&1 > /dev/null -pipeliner-experimental-cg=true | FileCheck %s ; REQUIRES: asserts ; diff --git a/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll b/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll index cea1b5a263f9..ecb3c869d363 100644 --- a/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-prolog-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s +; RUN: llc -mtriple=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s ; Test that we generate the correct name for a value in a prolog block. The ; pipeliner was using an incorrect value for an instruction in the 2nd prolog diff --git a/llvm/test/CodeGen/Hexagon/swp-prolog-phi4.ll b/llvm/test/CodeGen/Hexagon/swp-prolog-phi4.ll index 50fc9a9c8930..8bed0e7ced6b 100644 --- a/llvm/test/CodeGen/Hexagon/swp-prolog-phi4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-prolog-phi4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -verify-machineinstrs < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -verify-machineinstrs < %s ; Test that the name rewriter code doesn't chase the Phi operands for ; Phis that do not occur in the loop that is being pipelined. diff --git a/llvm/test/CodeGen/Hexagon/swp-regseq.ll b/llvm/test/CodeGen/Hexagon/swp-regseq.ll index a36796f150de..0bab6cb4a111 100644 --- a/llvm/test/CodeGen/Hexagon/swp-regseq.ll +++ b/llvm/test/CodeGen/Hexagon/swp-regseq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts %s.0 = type { i64 } diff --git a/llvm/test/CodeGen/Hexagon/swp-remove-dep-ice.ll b/llvm/test/CodeGen/Hexagon/swp-remove-dep-ice.ll index bcf9d2801310..80bd8cd2aea4 100644 --- a/llvm/test/CodeGen/Hexagon/swp-remove-dep-ice.ll +++ b/llvm/test/CodeGen/Hexagon/swp-remove-dep-ice.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Test that the pipeliner doesn't ICE in the ScheduleDAG code because diff --git a/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll b/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll index 30ac657a48d2..c1b31738a7b3 100644 --- a/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-rename-dead-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -fp-contract=fast -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -fp-contract=fast -enable-pipeliner < %s ; REQUIRES: asserts ; Pipelining can eliminate the need for a Phi if the loop carried use diff --git a/llvm/test/CodeGen/Hexagon/swp-rename.ll b/llvm/test/CodeGen/Hexagon/swp-rename.ll index 8c3947a047f0..36119329ea15 100644 --- a/llvm/test/CodeGen/Hexagon/swp-rename.ll +++ b/llvm/test/CodeGen/Hexagon/swp-rename.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s ; A test that the Phi rewrite logic is correct. diff --git a/llvm/test/CodeGen/Hexagon/swp-replace-uses1.ll b/llvm/test/CodeGen/Hexagon/swp-replace-uses1.ll index 45258234a766..5f2071ef6a8c 100644 --- a/llvm/test/CodeGen/Hexagon/swp-replace-uses1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-replace-uses1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/swp-resmii-1.ll b/llvm/test/CodeGen/Hexagon/swp-resmii-1.ll index 6f8f19878df7..c6bb4a6d570f 100644 --- a/llvm/test/CodeGen/Hexagon/swp-resmii-1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-resmii-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -debug-only=pipeliner < %s -o - 2>&1 > /dev/null -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -debug-only=pipeliner < %s -o - 2>&1 > /dev/null -pipeliner-experimental-cg=true | FileCheck %s ; REQUIRES: asserts ; Test that checks that we compute the correct ResMII for haar. diff --git a/llvm/test/CodeGen/Hexagon/swp-resmii.ll b/llvm/test/CodeGen/Hexagon/swp-resmii.ll index f65ae7bec3ad..d15a9fc46a0e 100644 --- a/llvm/test/CodeGen/Hexagon/swp-resmii.ll +++ b/llvm/test/CodeGen/Hexagon/swp-resmii.ll @@ -1,4 +1,4 @@ -; RUN: llc -disable-lsr -march=hexagon -enable-pipeliner \ +; RUN: llc -disable-lsr -mtriple=hexagon -enable-pipeliner \ ; RUN: -debug-only=pipeliner < %s 2>&1 > /dev/null -pipeliner-experimental-cg=true | FileCheck %s ; REQUIRES: asserts ; diff --git a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-1.ll b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-1.ll index e1466929b0fa..99edf597c136 100644 --- a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-1.ll +++ b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-2.ll b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-2.ll index 12df50301d60..712f17a67e09 100644 --- a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-2.ll +++ b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner < %s ; REQUIRES: asserts ; Test that causes an assert when the phi reuse code does not set diff --git a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-4.ll b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-4.ll index d0e70a4f4be7..7a22d1db6b09 100644 --- a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s +; RUN: llc -mtriple=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s ; REQUIRES: asserts ; Test that we generate the correct Phi names in the epilog when we need diff --git a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-5.ll b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-5.ll index 102548dd4a4c..35f2e9821e8d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-5.ll +++ b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-5.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-bit=false < %s +; RUN: llc -mtriple=hexagon -hexagon-bit=false < %s ; REQUIRES: asserts ; Fix for an undefined virtual register assert that was caused by an diff --git a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-6.ll b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-6.ll index e6aa9ccb5308..6c8b0638ae5d 100644 --- a/llvm/test/CodeGen/Hexagon/swp-reuse-phi-6.ll +++ b/llvm/test/CodeGen/Hexagon/swp-reuse-phi-6.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that the pipeliner generates correct code when attempting to reuse ; an existing phi. This test case contains a phi that references another diff --git a/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll b/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll index f62069a786f8..36d390a7b10a 100644 --- a/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll +++ b/llvm/test/CodeGen/Hexagon/swp-reuse-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -fp-contract=fast < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -fp-contract=fast < %s ; REQUIRES: asserts ; Test that the code which reuses existing Phis works when the Phis are used diff --git a/llvm/test/CodeGen/Hexagon/swp-sigma.ll b/llvm/test/CodeGen/Hexagon/swp-sigma.ll index ce0e2b435efb..d7b2b51755d6 100644 --- a/llvm/test/CodeGen/Hexagon/swp-sigma.ll +++ b/llvm/test/CodeGen/Hexagon/swp-sigma.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s -pipeliner-experimental-cg=true -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s -pipeliner-experimental-cg=true -verify-machineinstrs | FileCheck %s ; We do not pipeline sigma yet, but the non-pipelined version ; with good scheduling is pretty fast. The compiler generates diff --git a/llvm/test/CodeGen/Hexagon/swp-stages.ll b/llvm/test/CodeGen/Hexagon/swp-stages.ll index 5778e1b9e684..98e531a9843b 100644 --- a/llvm/test/CodeGen/Hexagon/swp-stages.ll +++ b/llvm/test/CodeGen/Hexagon/swp-stages.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-aa-sched-mi -enable-pipeliner \ +; RUN: llc -mtriple=hexagon -enable-aa-sched-mi -enable-pipeliner \ ; RUN: -hexagon-expand-condsets=0 -pipeliner-max-stages=2 < %s ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/swp-stages3.ll b/llvm/test/CodeGen/Hexagon/swp-stages3.ll index bf0c8af76c93..cc04bc044369 100644 --- a/llvm/test/CodeGen/Hexagon/swp-stages3.ll +++ b/llvm/test/CodeGen/Hexagon/swp-stages3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -pipeliner-max-stages=2 < %s ; REQUIRES: asserts ; Test that the compiler doesn't seg fault due to incorrect names in epilog. diff --git a/llvm/test/CodeGen/Hexagon/swp-stages4.ll b/llvm/test/CodeGen/Hexagon/swp-stages4.ll index 5377dc4d13ab..0d029dc7d2f2 100644 --- a/llvm/test/CodeGen/Hexagon/swp-stages4.ll +++ b/llvm/test/CodeGen/Hexagon/swp-stages4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -disable-block-placement=0 -hexagon-bit=0 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -disable-block-placement=0 -hexagon-bit=0 < %s -pipeliner-experimental-cg=true | FileCheck %s ; Test that we rename registers correctly for multiple stages when there is a ; Phi and depends upon another Phi. diff --git a/llvm/test/CodeGen/Hexagon/swp-stages5.ll b/llvm/test/CodeGen/Hexagon/swp-stages5.ll index 888e6e1d8a76..d6c478299fb3 100644 --- a/llvm/test/CodeGen/Hexagon/swp-stages5.ll +++ b/llvm/test/CodeGen/Hexagon/swp-stages5.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -hexagon-bit=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner -pipeliner-max-stages=2 -hexagon-bit=0 < %s | FileCheck %s ; Very similar to swp-stages4.ll, but the pipelined schedule is a little ; different. diff --git a/llvm/test/CodeGen/Hexagon/swp-subreg.ll b/llvm/test/CodeGen/Hexagon/swp-subreg.ll index b9754f4eb362..f6872a27b151 100644 --- a/llvm/test/CodeGen/Hexagon/swp-subreg.ll +++ b/llvm/test/CodeGen/Hexagon/swp-subreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS +; RUN: llc -mtriple=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS ; REQUIRES: asserts ; We're unable to pipeline a loop with a subreg as an operand of a Phi. diff --git a/llvm/test/CodeGen/Hexagon/swp-swap.ll b/llvm/test/CodeGen/Hexagon/swp-swap.ll index 7812d0cd1819..a1a1adcaaa23 100644 --- a/llvm/test/CodeGen/Hexagon/swp-swap.ll +++ b/llvm/test/CodeGen/Hexagon/swp-swap.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS +; RUN: llc -mtriple=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS ; REQUIRES: asserts ; Test that we don't pipeline, incorrectly, the swap operation. diff --git a/llvm/test/CodeGen/Hexagon/swp-tfri.ll b/llvm/test/CodeGen/Hexagon/swp-tfri.ll index 15d5f8230942..26009793f63c 100644 --- a/llvm/test/CodeGen/Hexagon/swp-tfri.ll +++ b/llvm/test/CodeGen/Hexagon/swp-tfri.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s --check-prefix=STATS +; RUN: llc -mtriple=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true -disable-cgp-delete-phis | FileCheck %s --check-prefix=STATS ; REQUIRES: asserts ; Check that we handle the case when a value is first defined in the loop. diff --git a/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll b/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll index 85ff24b494e7..1177ee91df72 100644 --- a/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll +++ b/llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 < %s -pipeliner-experimental-cg=true | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s -pipeliner-experimental-cg=true | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true -early-live-intervals -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O2 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O3 < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true -early-live-intervals -verify-machineinstrs | FileCheck %s ; ; Check that we pipeline a vectorized dot product in a single packet. ; diff --git a/llvm/test/CodeGen/Hexagon/swp-vmult.ll b/llvm/test/CodeGen/Hexagon/swp-vmult.ll index 532a7caaece4..137422d743e6 100644 --- a/llvm/test/CodeGen/Hexagon/swp-vmult.ll +++ b/llvm/test/CodeGen/Hexagon/swp-vmult.ll @@ -1,5 +1,5 @@ ; REQUIRES: to-be-fixed -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s ; Multiply and accumulate ; CHECK: mpyi([[REG0:r([0-9]+)]],[[REG1:r([0-9]+)]]) diff --git a/llvm/test/CodeGen/Hexagon/swp-vsum.ll b/llvm/test/CodeGen/Hexagon/swp-vsum.ll index 39d351732567..47f2c3ab9a65 100644 --- a/llvm/test/CodeGen/Hexagon/swp-vsum.ll +++ b/llvm/test/CodeGen/Hexagon/swp-vsum.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=CHECKV60 +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=CHECKV60 ; Simple vector total. ; CHECK: loop0(.LBB0_[[LOOP:.]], diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir b/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir index 9645ced56452..85cfd804c3bc 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir b/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir index a6285445d85d..8f1af7cfcc72 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir b/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir index 278663543ed4..c97fdbf0e09e 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir index 447918dec825..e86ef4376d0a 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir @@ -1,12 +1,12 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s \ # RUN: --check-prefix=CHECK-INITIALIZE -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -window-region-limit=1 -window-ii-limit=1 \ # RUN: -filetype=null 2>&1 | FileCheck %s --check-prefix=CHECK-ANALYSE-II -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -window-region-limit=1 -window-search-ratio=80 \ # RUN: -filetype=null 2>&1 | FileCheck %s --check-prefix=CHECK-SCHED-NOT-NEEDED diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir index 2b9e790776c2..5fecedd3c40b 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir index be75301b016e..9862860e1c8b 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir index b56c69d4e352..6a7b88be7f90 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals.mir b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals.mir index 7fa3cdf62d09..87cec2019910 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-live-intervals.mir @@ -1,6 +1,6 @@ # REQUIRES: asserts # -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -window-search-num=100 \ # RUN: -window-search-ratio=100 -window-diff-limit=0 -verify-machineinstrs \ # RUN: 2>&1 | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir b/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir index ca6a87119b1d..1fafde0a81f1 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir b/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir index a0d3e95190f0..cc5ac70ee2cb 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-pragma-initiation-interval-fail.mir b/llvm/test/CodeGen/Hexagon/swp-ws-pragma-initiation-interval-fail.mir index 6e69a76290fb..0396bb63ce3e 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-pragma-initiation-interval-fail.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-pragma-initiation-interval-fail.mir @@ -1,4 +1,4 @@ -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s # REQUIRES: asserts diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-resource-reserve.mir b/llvm/test/CodeGen/Hexagon/swp-ws-resource-reserve.mir index 4a9a09c4148c..83b3443373d3 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-resource-reserve.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-resource-reserve.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: -window-search-ratio=100 -window-search-num=100 -window-diff-limit=1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir b/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir index 555608831c4d..dad69c1c6f27 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-stall-cycle.mir b/llvm/test/CodeGen/Hexagon/swp-ws-stall-cycle.mir index ddba67d78eb5..3e5c8914feff 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-stall-cycle.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-stall-cycle.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs \ # RUN: -window-region-limit=1 -window-search-ratio=100 -window-diff-limit=0 \ # RUN: 2>&1 | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir b/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir index b1720be689c0..bc3f26351940 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-zero-cost.mir b/llvm/test/CodeGen/Hexagon/swp-ws-zero-cost.mir index ecf49a83c69e..c2c0f9374d12 100644 --- a/llvm/test/CodeGen/Hexagon/swp-ws-zero-cost.mir +++ b/llvm/test/CodeGen/Hexagon/swp-ws-zero-cost.mir @@ -1,5 +1,5 @@ # REQUIRES: asserts -# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ +# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \ # RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Hexagon/swp-xxh2.ll b/llvm/test/CodeGen/Hexagon/swp-xxh2.ll index 16ca2136ca0a..0f392c520ae8 100644 --- a/llvm/test/CodeGen/Hexagon/swp-xxh2.ll +++ b/llvm/test/CodeGen/Hexagon/swp-xxh2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -debug-only=pipeliner < %s -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -debug-only=pipeliner < %s -o - 2>&1 > /dev/null | FileCheck %s ; REQUIRES: asserts ; Fix bug when pipelining xxh benchmark at O3, mv55, and with vectorization. diff --git a/llvm/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll b/llvm/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll index d701a72b2fcc..b38a617df2b3 100644 --- a/llvm/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll +++ b/llvm/test/CodeGen/Hexagon/tail-call-mem-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: tail_memcpy: ; CHECK: jump memcpy diff --git a/llvm/test/CodeGen/Hexagon/tail-call-trunc.ll b/llvm/test/CodeGen/Hexagon/tail-call-trunc.ll index 98214c7b1e97..eb0965db0427 100644 --- a/llvm/test/CodeGen/Hexagon/tail-call-trunc.ll +++ b/llvm/test/CodeGen/Hexagon/tail-call-trunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s declare i32 @ret_i32() diff --git a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-abort.ll b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-abort.ll index 82dae2cc586a..e13689b1aecc 100644 --- a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-abort.ll +++ b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-abort.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-cgp < %s +; RUN: llc -mtriple=hexagon -O2 -disable-cgp < %s ; REQUIRES: asserts ; ; Tail duplication can ignore subregister information on PHI nodes, and as diff --git a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll index 073a953d89bb..98d0da9cfb9d 100644 --- a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll +++ b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; REQUIRES: asserts ; When tail-duplicating a block with PHI nodes that use subregisters, the diff --git a/llvm/test/CodeGen/Hexagon/tailcall_fastcc_ccc.ll b/llvm/test/CodeGen/Hexagon/tailcall_fastcc_ccc.ll index 479fc15a8e8a..843e707c1df5 100644 --- a/llvm/test/CodeGen/Hexagon/tailcall_fastcc_ccc.ll +++ b/llvm/test/CodeGen/Hexagon/tailcall_fastcc_ccc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/target-flag-ext.mir b/llvm/test/CodeGen/Hexagon/target-flag-ext.mir index e839f8b76d14..eb98a4187d68 100644 --- a/llvm/test/CodeGen/Hexagon/target-flag-ext.mir +++ b/llvm/test/CodeGen/Hexagon/target-flag-ext.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass hexagon-packetizer -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass hexagon-packetizer -o - %s | FileCheck %s --- name: fred tracksRegLiveness: true diff --git a/llvm/test/CodeGen/Hexagon/tc_duplex.ll b/llvm/test/CodeGen/Hexagon/tc_duplex.ll index 18344ecf02d4..5252f7fd970a 100644 --- a/llvm/test/CodeGen/Hexagon/tc_duplex.ll +++ b/llvm/test/CodeGen/Hexagon/tc_duplex.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr=+duplex -mcpu=hexagonv67t < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mattr=+duplex -mcpu=hexagonv67t < %s | FileCheck %s ; Check that we generate two memory operations in tiny core if duplexes ; are enabled. diff --git a/llvm/test/CodeGen/Hexagon/tc_sched.ll b/llvm/test/CodeGen/Hexagon/tc_sched.ll index 2ef2ce6ce694..08bad36d886a 100644 --- a/llvm/test/CodeGen/Hexagon/tc_sched.ll +++ b/llvm/test/CodeGen/Hexagon/tc_sched.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv67t < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv67t < %s | FileCheck %s ; A simple test case for the tiny core instruction latency information. diff --git a/llvm/test/CodeGen/Hexagon/tc_sched1.ll b/llvm/test/CodeGen/Hexagon/tc_sched1.ll index 261b6fdcce5b..345665e34d0a 100644 --- a/llvm/test/CodeGen/Hexagon/tc_sched1.ll +++ b/llvm/test/CodeGen/Hexagon/tc_sched1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv67t < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv67t < %s | FileCheck %s ; Another scheduling test for Tiny Core. diff --git a/llvm/test/CodeGen/Hexagon/tcm-zext.ll b/llvm/test/CodeGen/Hexagon/tcm-zext.ll index 738c9bec1bb2..7c8336af7c7a 100644 --- a/llvm/test/CodeGen/Hexagon/tcm-zext.ll +++ b/llvm/test/CodeGen/Hexagon/tcm-zext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: jump f2 ; ; Check that we perform tail call merging on return types with zero extend. diff --git a/llvm/test/CodeGen/Hexagon/testbits.ll b/llvm/test/CodeGen/Hexagon/testbits.ll index 225ce07ed06e..d487845b6021 100644 --- a/llvm/test/CodeGen/Hexagon/testbits.ll +++ b/llvm/test/CodeGen/Hexagon/testbits.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: f0: ; CHECK: p0 = bitsset(r0,r1) diff --git a/llvm/test/CodeGen/Hexagon/tfr-cleanup.ll b/llvm/test/CodeGen/Hexagon/tfr-cleanup.ll index a576812c67da..64286d2ea0bf 100644 --- a/llvm/test/CodeGen/Hexagon/tfr-cleanup.ll +++ b/llvm/test/CodeGen/Hexagon/tfr-cleanup.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -hexagon-eif=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 -hexagon-eif=0 < %s | FileCheck %s ; Without TFR cleanup, the last block contained ; { ; r3 = xor(r1, r2) diff --git a/llvm/test/CodeGen/Hexagon/tfr-mux-nvj.ll b/llvm/test/CodeGen/Hexagon/tfr-mux-nvj.ll index 1bffc8e63ea0..cf2aa8093a78 100644 --- a/llvm/test/CodeGen/Hexagon/tfr-mux-nvj.ll +++ b/llvm/test/CodeGen/Hexagon/tfr-mux-nvj.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; CHECK: mux ; CHECK: cmp{{.*\.new}} diff --git a/llvm/test/CodeGen/Hexagon/tfr-to-combine.ll b/llvm/test/CodeGen/Hexagon/tfr-to-combine.ll index 98895dad9df4..6284da13e772 100644 --- a/llvm/test/CodeGen/Hexagon/tfr-to-combine.ll +++ b/llvm/test/CodeGen/Hexagon/tfr-to-combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -O3 -disable-hsdr < %s | FileCheck %s ; Check that we combine TFRs and TFRIs into COMBINEs. diff --git a/llvm/test/CodeGen/Hexagon/tied_oper.ll b/llvm/test/CodeGen/Hexagon/tied_oper.ll index 5f98944818f9..6479ce4d10c6 100644 --- a/llvm/test/CodeGen/Hexagon/tied_oper.ll +++ b/llvm/test/CodeGen/Hexagon/tied_oper.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 -verify-machineinstrs -disable-hexagon-peephole < %s +; RUN: llc -mtriple=hexagon -O3 -verify-machineinstrs -disable-hexagon-peephole < %s ; REQUIRES: asserts ; This test checks if tied operands are consistent. diff --git a/llvm/test/CodeGen/Hexagon/tiny_bkfir_artdeps.ll b/llvm/test/CodeGen/Hexagon/tiny_bkfir_artdeps.ll index d4103d1da76b..a6805135b50d 100644 --- a/llvm/test/CodeGen/Hexagon/tiny_bkfir_artdeps.ll +++ b/llvm/test/CodeGen/Hexagon/tiny_bkfir_artdeps.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mv67t -debug-only=pipeliner < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=hexagon -mv67t -debug-only=pipeliner < %s 2>&1 | FileCheck %s ; REQUIRES: asserts ; Test that the artificial dependencies have been created. diff --git a/llvm/test/CodeGen/Hexagon/tiny_bkfir_loop_align.ll b/llvm/test/CodeGen/Hexagon/tiny_bkfir_loop_align.ll index b733c0aad67e..92816105ae1e 100644 --- a/llvm/test/CodeGen/Hexagon/tiny_bkfir_loop_align.ll +++ b/llvm/test/CodeGen/Hexagon/tiny_bkfir_loop_align.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -mv67t -march=hexagon < %s | FileCheck %s +; RUN: llc -O3 -mv67t -mtriple=hexagon < %s | FileCheck %s ; Test that the inner loop in the tiny core version of bkfir has the assembler ; directive "p2align 4". diff --git a/llvm/test/CodeGen/Hexagon/tinycore.ll b/llvm/test/CodeGen/Hexagon/tinycore.ll index 70f063c8a9be..c44038e76719 100644 --- a/llvm/test/CodeGen/Hexagon/tinycore.ll +++ b/llvm/test/CodeGen/Hexagon/tinycore.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv67t < %s | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv65 < %s | FileCheck --check-prefix=CHECK-BIG %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv67t < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 < %s | FileCheck --check-prefix=CHECK-BIG %s ; Test that the tiny core architecture generates 3 slot packets at most and ; a single load/store per packet at most. diff --git a/llvm/test/CodeGen/Hexagon/tls_gd.ll b/llvm/test/CodeGen/Hexagon/tls_gd.ll index a52469b92191..2196a563c128 100644 --- a/llvm/test/CodeGen/Hexagon/tls_gd.ll +++ b/llvm/test/CodeGen/Hexagon/tls_gd.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -relocation-model=pic < %s | FileCheck %s ; CHECK: add({{pc|PC}},##_GLOBAL_OFFSET_TABLE_@PCREL) ; CHECK: call g1@GDPLT ; CHECK: call g0@GDPLT diff --git a/llvm/test/CodeGen/Hexagon/tls_pic.ll b/llvm/test/CodeGen/Hexagon/tls_pic.ll index 2f9b189b4878..76821409cd1f 100644 --- a/llvm/test/CodeGen/Hexagon/tls_pic.ll +++ b/llvm/test/CodeGen/Hexagon/tls_pic.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon -relocation-model=pic < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon -relocation-model=pic < %s | FileCheck %s @dst_ie = thread_local(initialexec) global i32 0, align 4 @src_ie = thread_local(initialexec) global i32 0, align 4 diff --git a/llvm/test/CodeGen/Hexagon/trap-crash.ll b/llvm/test/CodeGen/Hexagon/trap-crash.ll index a0afe5fdd304..c19f90c297ab 100644 --- a/llvm/test/CodeGen/Hexagon/trap-crash.ll +++ b/llvm/test/CodeGen/Hexagon/trap-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon --verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon --verify-machineinstrs < %s | FileCheck %s ; Generate code that is guaranteed to crash. At the moment, it's a ; misaligned load. diff --git a/llvm/test/CodeGen/Hexagon/trap-unreachable.ll b/llvm/test/CodeGen/Hexagon/trap-unreachable.ll index b14f1e3c1a5d..7051dda1432c 100644 --- a/llvm/test/CodeGen/Hexagon/trap-unreachable.ll +++ b/llvm/test/CodeGen/Hexagon/trap-unreachable.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -trap-unreachable < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -trap-unreachable < %s | FileCheck %s ; Trap is implemented via a misaligned load. ; CHECK: memd(##3134984174) diff --git a/llvm/test/CodeGen/Hexagon/trivialmemaliascheck.ll b/llvm/test/CodeGen/Hexagon/trivialmemaliascheck.ll index 49b615197b62..3d79401b5248 100644 --- a/llvm/test/CodeGen/Hexagon/trivialmemaliascheck.ll +++ b/llvm/test/CodeGen/Hexagon/trivialmemaliascheck.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-aa-sched-mi < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-aa-sched-mi < %s | FileCheck %s ; The two memory addresses in the load and the memop below are trivially ; non-aliasing. However, there are some cases where the scheduler cannot diff --git a/llvm/test/CodeGen/Hexagon/trunc-mpy.ll b/llvm/test/CodeGen/Hexagon/trunc-mpy.ll index ea132495cde8..84d287e165af 100644 --- a/llvm/test/CodeGen/Hexagon/trunc-mpy.ll +++ b/llvm/test/CodeGen/Hexagon/trunc-mpy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hexagon-peephole < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hexagon-peephole < %s | FileCheck %s ; Test that we're generating a 32-bit multiply high instead of a 64-bit version, ; when using the high 32-bits only. diff --git a/llvm/test/CodeGen/Hexagon/two-crash.ll b/llvm/test/CodeGen/Hexagon/two-crash.ll index 7e79cb3be912..fc857a7acb93 100644 --- a/llvm/test/CodeGen/Hexagon/two-crash.ll +++ b/llvm/test/CodeGen/Hexagon/two-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This testcase crashed, because we propagated a reg:sub into a tied use. ; The two-address pass rewrote it in a way that generated incorrect code. ; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}},#16) diff --git a/llvm/test/CodeGen/Hexagon/twoaddressbug.ll b/llvm/test/CodeGen/Hexagon/twoaddressbug.ll index 8fab1f0a55d2..ad28d4c59101 100644 --- a/llvm/test/CodeGen/Hexagon/twoaddressbug.ll +++ b/llvm/test/CodeGen/Hexagon/twoaddressbug.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts ; This file used to fail with an "UNREACHABLE executed!" in Post-RA pseudo diff --git a/llvm/test/CodeGen/Hexagon/undef-ret.ll b/llvm/test/CodeGen/Hexagon/undef-ret.ll index e879d7d01a47..d15239261ce9 100644 --- a/llvm/test/CodeGen/Hexagon/undef-ret.ll +++ b/llvm/test/CodeGen/Hexagon/undef-ret.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; Check for direct use of r0 in addadd. ; CHECK: = add(r0,add(r1,#2)) diff --git a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll index 8cf2b86fca41..cdcc987007f4 100644 --- a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll +++ b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; DAG combiner folds sequences of shifts, which can sometimes obscure ; optimization opportunities. For example diff --git a/llvm/test/CodeGen/Hexagon/union-1.ll b/llvm/test/CodeGen/Hexagon/union-1.ll index 5d98f915945e..7baea9bde3bb 100644 --- a/llvm/test/CodeGen/Hexagon/union-1.ll +++ b/llvm/test/CodeGen/Hexagon/union-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: f0 ; CHECK-NOT: combine(#0 ; CHECK: jump f1 diff --git a/llvm/test/CodeGen/Hexagon/unordered-fcmp.ll b/llvm/test/CodeGen/Hexagon/unordered-fcmp.ll index c4f163405399..cbbb48f56ebc 100644 --- a/llvm/test/CodeGen/Hexagon/unordered-fcmp.ll +++ b/llvm/test/CodeGen/Hexagon/unordered-fcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we generate correct set of instructions for unordered ; floating-point compares. diff --git a/llvm/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir b/llvm/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir index 2f78a6d9542a..79f9d5dfffbf 100644 --- a/llvm/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir +++ b/llvm/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass unreachable-mbb-elimination %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass unreachable-mbb-elimination %s -o - | FileCheck %s --- name: fred diff --git a/llvm/test/CodeGen/Hexagon/upper-mpy.ll b/llvm/test/CodeGen/Hexagon/upper-mpy.ll index 35bdc0cd439c..88eb1e9789e1 100644 --- a/llvm/test/CodeGen/Hexagon/upper-mpy.ll +++ b/llvm/test/CodeGen/Hexagon/upper-mpy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we generate multiple using upper result. diff --git a/llvm/test/CodeGen/Hexagon/v5_insns.ll b/llvm/test/CodeGen/Hexagon/v5_insns.ll index 3e9d1e98cf36..9c0db6e4e252 100644 --- a/llvm/test/CodeGen/Hexagon/v5_insns.ll +++ b/llvm/test/CodeGen/Hexagon/v5_insns.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-haar-balign32.ll b/llvm/test/CodeGen/Hexagon/v6-haar-balign32.ll index 6b3c0a94a494..a31ccb408c60 100644 --- a/llvm/test/CodeGen/Hexagon/v6-haar-balign32.ll +++ b/llvm/test/CodeGen/Hexagon/v6-haar-balign32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv73 -O2 -mattr=+hvxv73,hvx-length64b < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv73 -O2 -mattr=+hvxv73,hvx-length64b < %s | FileCheck %s ; CHECK: .p2align{{.*}}5 ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll index 01b5cc878b9d..99357a6f78fe 100644 --- a/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll +++ b/llvm/test/CodeGen/Hexagon/v6-inlasm1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s ; CHECK: vmemu(r{{[0-9]+}}+#0) = v{{[0-9]*}} target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll index 9506e2352b91..295d58565a9b 100644 --- a/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll +++ b/llvm/test/CodeGen/Hexagon/v6-inlasm2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s ; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}} target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll index 0a9933daad0c..d78d32e77357 100644 --- a/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll +++ b/llvm/test/CodeGen/Hexagon/v6-inlasm3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s ; CHECK: vmemu(r{{[0-9]}}+#0) = v{{[0-9]*}} target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-inlasm4.ll b/llvm/test/CodeGen/Hexagon/v6-inlasm4.ll index 286d0384ca21..d76eeda49951 100644 --- a/llvm/test/CodeGen/Hexagon/v6-inlasm4.ll +++ b/llvm/test/CodeGen/Hexagon/v6-inlasm4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s ; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]+}}) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-shuffl.ll b/llvm/test/CodeGen/Hexagon/v6-shuffl.ll index ba49f79a2893..c8b1b0111a9f 100644 --- a/llvm/test/CodeGen/Hexagon/v6-shuffl.ll +++ b/llvm/test/CodeGen/Hexagon/v6-shuffl.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK: vsplat target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6-spill1.ll b/llvm/test/CodeGen/Hexagon/v6-spill1.ll index 57ac69683c7d..941e5bdbcbe7 100644 --- a/llvm/test/CodeGen/Hexagon/v6-spill1.ll +++ b/llvm/test/CodeGen/Hexagon/v6-spill1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -pipeliner-max-mii=10 < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -pipeliner-max-mii=10 < %s -verify-machineinstrs | FileCheck %s ; CHECK-NOT: vmemu ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll b/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll index 56977a1041bd..b6494f918b03 100644 --- a/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll +++ b/llvm/test/CodeGen/Hexagon/v6-unaligned-spill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-cgp-delete-phis < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-cgp-delete-phis < %s | FileCheck %s ; Test that we no longer generate an unaligned vector store for a spill when ; a function has an alloca. diff --git a/llvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll b/llvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll index cf8bc7b495d4..0253e6b989b6 100644 --- a/llvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll +++ b/llvm/test/CodeGen/Hexagon/v6-vecpred-copy.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}}) ; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.b += v{{[0-9]*}}.b diff --git a/llvm/test/CodeGen/Hexagon/v60-align.ll b/llvm/test/CodeGen/Hexagon/v60-align.ll index 56dbd715c5c0..9543c4df242d 100644 --- a/llvm/test/CodeGen/Hexagon/v60-align.ll +++ b/llvm/test/CodeGen/Hexagon/v60-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: allocframe(r29,#{{[1-9][0-9]*}}):raw ; CHECK: r29 = and(r29,#-64) diff --git a/llvm/test/CodeGen/Hexagon/v60-cur.ll b/llvm/test/CodeGen/Hexagon/v60-cur.ll index f6db1968c34a..a55274fed0fa 100644 --- a/llvm/test/CodeGen/Hexagon/v60-cur.ll +++ b/llvm/test/CodeGen/Hexagon/v60-cur.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we generate a .cur diff --git a/llvm/test/CodeGen/Hexagon/v60-haar-postinc.ll b/llvm/test/CodeGen/Hexagon/v60-haar-postinc.ll index 919817777218..4321c1b873f3 100644 --- a/llvm/test/CodeGen/Hexagon/v60-haar-postinc.ll +++ b/llvm/test/CodeGen/Hexagon/v60-haar-postinc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: vmem(r{{[0-9]+}}++#1) ; CHECK: vmem(r{{[0-9]+}}++#1) diff --git a/llvm/test/CodeGen/Hexagon/v60-halide-vcombinei8.ll b/llvm/test/CodeGen/Hexagon/v60-halide-vcombinei8.ll index 59a9c13fcc0b..dddd3fcca258 100644 --- a/llvm/test/CodeGen/Hexagon/v60-halide-vcombinei8.ll +++ b/llvm/test/CodeGen/Hexagon/v60-halide-vcombinei8.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; do not crash with Cannot select on vcombine on v128i8 ; CHECK: vadd diff --git a/llvm/test/CodeGen/Hexagon/v60-vec-128b-1.ll b/llvm/test/CodeGen/Hexagon/v60-vec-128b-1.ll index ce2e1b5459ae..f610a94c00af 100644 --- a/llvm/test/CodeGen/Hexagon/v60-vec-128b-1.ll +++ b/llvm/test/CodeGen/Hexagon/v60-vec-128b-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: v{{[0-9]+}} = vsplat(r{{[0-9]+}}) ; CHECK: .comm g0,256,256 ; CHECK: .comm g1,128,128 diff --git a/llvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll b/llvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll index a0dfba5509f9..a4d182c9ac5c 100644 --- a/llvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll +++ b/llvm/test/CodeGen/Hexagon/v60-vecpred-spill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s -verify-machineinstrs | FileCheck %s ; CHECK-NOT: vmem(r30+#-1){{ *} = v{{[0-9]+}} ; CHECK-NOT: v{{[0-9]+}} = vmem(r30+#-1) ; CHECK: v{{[0-9]+}} = vmux diff --git a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll index 6572964685e3..51516b7a917f 100644 --- a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll +++ b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: if (p{{[0-3]}}) v{{[0-9]+}} = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/v60-vsel2.ll b/llvm/test/CodeGen/Hexagon/v60-vsel2.ll index 1883c4bea114..3a273617283c 100644 --- a/llvm/test/CodeGen/Hexagon/v60-vsel2.ll +++ b/llvm/test/CodeGen/Hexagon/v60-vsel2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vcombine(v{{[0-9]+}},v{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/v60Intrins.ll b/llvm/test/CodeGen/Hexagon/v60Intrins.ll index edf105ccfba8..5c4533739526 100644 --- a/llvm/test/CodeGen/Hexagon/v60Intrins.ll +++ b/llvm/test/CodeGen/Hexagon/v60Intrins.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -disable-post-ra < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -O2 -disable-post-ra < %s | FileCheck %s ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}}) ; CHECK: q{{[0-3]}} |= vand(v{{[0-9]*}},r{{[0-9]*}}) diff --git a/llvm/test/CodeGen/Hexagon/v60Vasr.ll b/llvm/test/CodeGen/Hexagon/v60Vasr.ll index 8f53c3e59acc..15d67bee8bd5 100644 --- a/llvm/test/CodeGen/Hexagon/v60Vasr.ll +++ b/llvm/test/CodeGen/Hexagon/v60Vasr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-7]+}}):sat diff --git a/llvm/test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll b/llvm/test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll index b1495a3dc210..cac6d77e2e05 100644 --- a/llvm/test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll +++ b/llvm/test/CodeGen/Hexagon/v60_Q6_P_rol_PI.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: r{{[0-9]*}}:{{[0-9]*}} = rol(r{{[0-9]*}}:{{[0-9]*}},#4) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v60_sort16.ll b/llvm/test/CodeGen/Hexagon/v60_sort16.ll index 1463bc258384..e408113892de 100644 --- a/llvm/test/CodeGen/Hexagon/v60_sort16.ll +++ b/llvm/test/CodeGen/Hexagon/v60_sort16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Looking for 3rd register field to be restricted to r0-r7. ; v3:2=vdeal(v3,v2,r1) ; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vdeal(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]+}}) diff --git a/llvm/test/CodeGen/Hexagon/v60rol-instrs.ll b/llvm/test/CodeGen/Hexagon/v60rol-instrs.ll index e174e0b7bbde..184c5fcb9beb 100644 --- a/llvm/test/CodeGen/Hexagon/v60rol-instrs.ll +++ b/llvm/test/CodeGen/Hexagon/v60rol-instrs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: r{{[0-9]*}} += rol(r{{[0-9]*}},#31) ; CHECK: r{{[0-9]*}} &= rol(r{{[0-9]*}},#31) diff --git a/llvm/test/CodeGen/Hexagon/v60small.ll b/llvm/test/CodeGen/Hexagon/v60small.ll index 8c83b80854db..0986f8d683ea 100644 --- a/llvm/test/CodeGen/Hexagon/v60small.ll +++ b/llvm/test/CodeGen/Hexagon/v60small.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}}) target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/v62-CJAllSlots.ll b/llvm/test/CodeGen/Hexagon/v62-CJAllSlots.ll index 52376b3614b9..412bf8cc68e0 100644 --- a/llvm/test/CodeGen/Hexagon/v62-CJAllSlots.ll +++ b/llvm/test/CodeGen/Hexagon/v62-CJAllSlots.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -disable-block-placement < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -disable-block-placement < %s | FileCheck %s ; Disable block placement because it intereferes with the generated code. ; CHECK: if (p{{[0-9]*}}) jump:nt .LBB0_2 diff --git a/llvm/test/CodeGen/Hexagon/v62-inlasm4.ll b/llvm/test/CodeGen/Hexagon/v62-inlasm4.ll index 777f7711540d..e78beb0803fe 100644 --- a/llvm/test/CodeGen/Hexagon/v62-inlasm4.ll +++ b/llvm/test/CodeGen/Hexagon/v62-inlasm4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: q{{[0-3]}} = vsetq2(r{{[0-9]+}}) target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6vassignp.ll b/llvm/test/CodeGen/Hexagon/v6vassignp.ll index be2d103a2013..7e2754e8ed20 100644 --- a/llvm/test/CodeGen/Hexagon/v6vassignp.ll +++ b/llvm/test/CodeGen/Hexagon/v6vassignp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; generate vmems for W_equals_W (vassignp) ; CHECK: vmem ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir b/llvm/test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir index cdb70c4f3af2..a803afb9c569 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir +++ b/llvm/test/CodeGen/Hexagon/v6vec-vmemcur-prob.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -start-after if-converter %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -start-after if-converter %s -o - | FileCheck %s # Test that we do no generate a .cur, which refers to vector register generated # in a previous packet and used in the current packet. diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vmemu1.ll b/llvm/test/CodeGen/Hexagon/v6vec-vmemu1.ll index 83690f157872..33212886c3b3 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vmemu1.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec-vmemu1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hexagon-shuffle=1 -O2 -enable-pipeliner=false < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hexagon-shuffle=1 -O2 -enable-pipeliner=false < %s | FileCheck %s ; Generate vmemu (unaligned). ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vmemu2.ll b/llvm/test/CodeGen/Hexagon/v6vec-vmemu2.ll index b79bedc10133..0d0c66db6eea 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vmemu2.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec-vmemu2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hexagon-shuffle=0 -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hexagon-shuffle=0 -O2 < %s | FileCheck %s ; Generate vmemu (unaligned). ; CHECK: vmemu diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll index 45a101e4ad3e..899438e6c709 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll @@ -1,5 +1,5 @@ -; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -no-integrated-as -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s +; RUN: llc -no-integrated-as -mtriple=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -no-integrated-as -mtriple=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s ; generate .long XXXX which is a vector debug print instruction. ; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0 diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll b/llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll index 1dc9d6a98a28..ff36a3dfc8b9 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec-vshuff.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hexagon-shuffle=1 -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hexagon-shuffle=1 -O2 < %s | FileCheck %s ; Generate vshuff with 3rd param as an Rt8. ; v1:0=vshuff(v0,v1,r7) ; CHECK: vshuff(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]}}) diff --git a/llvm/test/CodeGen/Hexagon/v6vec_inc1.ll b/llvm/test/CodeGen/Hexagon/v6vec_inc1.ll index 323dbd4560fb..8b072931e85b 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec_inc1.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec_inc1.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O2 -enable-pipeliner=false < %s | FileCheck %s -; RUN: llc -march=hexagon -O2 -debug-only=pipeliner < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SWP +; RUN: llc -mtriple=hexagon -O2 -enable-pipeliner=false < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 -debug-only=pipeliner < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SWP ; REQUIRES: asserts ; CHECK: { diff --git a/llvm/test/CodeGen/Hexagon/v6vec_zero.ll b/llvm/test/CodeGen/Hexagon/v6vec_zero.ll index ee2da0a0bbd9..551bb579332f 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec_zero.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec_zero.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Test that we do not ICE with a cannot select message when diff --git a/llvm/test/CodeGen/Hexagon/v6vect-dbl-fail1.ll b/llvm/test/CodeGen/Hexagon/v6vect-dbl-fail1.ll index 512d16a4eb1f..7a1a132c21a7 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-dbl-fail1.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-dbl-fail1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: vmem ; CHECK: vmem ; CHECK-NOT: r{{[0-9]*}} = add(r30,#-256) diff --git a/llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll b/llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll index 259e0df23520..124e1ada28de 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-dbl-spill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts ; Test that we don't assert because the compiler generates the wrong register diff --git a/llvm/test/CodeGen/Hexagon/v6vect-dbl.ll b/llvm/test/CodeGen/Hexagon/v6vect-dbl.ll index 234fdd3386a9..d42056c2caac 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-dbl.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-dbl.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck --check-prefix=CHECKO0 %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck --check-prefix=CHECKO0 %s ; KP: Removed -O2 check. The code has become more aggressively optimized ; (some loads were found to be redundant and have been removed completely), ; and verifying correct code generation has become more difficult than diff --git a/llvm/test/CodeGen/Hexagon/v6vect-dh1.ll b/llvm/test/CodeGen/Hexagon/v6vect-dh1.ll index 2af218d8ecbc..688bb1a637ab 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-dh1.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-dh1.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s -; RUN: llc -march=hexagon -O1 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; ; CHECK-NOT: v{{[0-9]*}}.cur ; diff --git a/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll b/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll index 50ea80ceb380..7c8d938e60df 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Checking for alignment of stack to 64. ; CHECK: r{{[0-9]+}} = and(r{{[0-9]+}},#-64) diff --git a/llvm/test/CodeGen/Hexagon/v6vect-no-sideeffects.ll b/llvm/test/CodeGen/Hexagon/v6vect-no-sideeffects.ll index 1e50b5c7940b..0a1f72275f31 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-no-sideeffects.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-no-sideeffects.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner=false -hexagon-vector-combine=false < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -enable-pipeliner=false -hexagon-vector-combine=false < %s | FileCheck %s ; Test that the vsplat and vmemu are not all serialized due to chain edges ; caused by the hasSideEffects flag. The exact code generation may change diff --git a/llvm/test/CodeGen/Hexagon/v6vect-pred2.ll b/llvm/test/CodeGen/Hexagon/v6vect-pred2.ll index 7bf385be1d4f..9137430b5754 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-pred2.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-pred2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-DAG: v{{[0-9]+}} = vsplat(r{{[0-9]+}}) ; CHECK-DAG: v{{[0-9]+}} = vsplat(r{{[0-9]+}}) ; CHECK-DAG: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll b/llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll index d22296acc943..f2abc77c934c 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-spill-kill.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s +; RUN: llc -mtriple=hexagon -O3 < %s ; REQUIRES: asserts ; Test that we don't assert because of requiring too many scavenger spill diff --git a/llvm/test/CodeGen/Hexagon/v6vect-vmem1.ll b/llvm/test/CodeGen/Hexagon/v6vect-vmem1.ll index 9a7930b9134b..3f5bdfee1814 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-vmem1.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-vmem1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: vmem(r{{[0-9]*}}+#1) = target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/v6vect-vsplat.ll b/llvm/test/CodeGen/Hexagon/v6vect-vsplat.ll index 53b45a6a8737..ef377b4d4384 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-vsplat.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-vsplat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; CHECK-NOT: vsplat ; CHECK: call f2 ; CHECK: v{{[0-9]+}} = vsplat diff --git a/llvm/test/CodeGen/Hexagon/vacopy.ll b/llvm/test/CodeGen/Hexagon/vacopy.ll index 999f151a5bee..fea62af9b58b 100644 --- a/llvm/test/CodeGen/Hexagon/vacopy.ll +++ b/llvm/test/CodeGen/Hexagon/vacopy.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s ; CHECK-LABEL: PrintInts: ; CHECK-DAG: memw{{.*}} = r{{[0-9]+}} ; CHECK-DAG: memw{{.*}} = r{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/vadd1.ll b/llvm/test/CodeGen/Hexagon/vadd1.ll index edb335288076..f1d615aa765a 100644 --- a/llvm/test/CodeGen/Hexagon/vadd1.ll +++ b/llvm/test/CodeGen/Hexagon/vadd1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: v{{[0-9]*}}.w = vadd target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/vaddh.ll b/llvm/test/CodeGen/Hexagon/vaddh.ll index eb7e74a3486f..ba3fd6bcc7d4 100644 --- a/llvm/test/CodeGen/Hexagon/vaddh.ll +++ b/llvm/test/CodeGen/Hexagon/vaddh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vaddh(r{{[0-9]+}},r{{[0-9]+}}) @g0 = external global i32 diff --git a/llvm/test/CodeGen/Hexagon/validate-offset.ll b/llvm/test/CodeGen/Hexagon/validate-offset.ll index d6ca532770e5..b1c71c00e066 100644 --- a/llvm/test/CodeGen/Hexagon/validate-offset.ll +++ b/llvm/test/CodeGen/Hexagon/validate-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s +; RUN: llc -mtriple=hexagon -O0 < %s ; This is a regression test which makes sure that the offset check ; is available for STRiw_indexed instruction. This is required diff --git a/llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll b/llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll index fbdfb65c57d7..96ba7b641960 100644 --- a/llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll +++ b/llvm/test/CodeGen/Hexagon/vararg-deallocate-sp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s ; Test that the compiler deallocates the register saved area on Linux ; for functions that do not need a frame pointer. diff --git a/llvm/test/CodeGen/Hexagon/vararg-formal.ll b/llvm/test/CodeGen/Hexagon/vararg-formal.ll index 6bba65fcab16..07a53c79020b 100644 --- a/llvm/test/CodeGen/Hexagon/vararg-formal.ll +++ b/llvm/test/CodeGen/Hexagon/vararg-formal.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that the first formal argument is not loaded from memory. ; CHECK-NOT: memw diff --git a/llvm/test/CodeGen/Hexagon/vararg-linux-abi.ll b/llvm/test/CodeGen/Hexagon/vararg-linux-abi.ll index f270afb2859b..efac978b55d9 100644 --- a/llvm/test/CodeGen/Hexagon/vararg-linux-abi.ll +++ b/llvm/test/CodeGen/Hexagon/vararg-linux-abi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mtriple=hexagon-unknown-linux-musl < %s | FileCheck %s ; Check that we update the stack pointer before we do allocframe, so that ; the LR/FP are stored in the location required by the Linux ABI. diff --git a/llvm/test/CodeGen/Hexagon/vararg.ll b/llvm/test/CodeGen/Hexagon/vararg.ll index 49fef2e4b1db..449c76d636d8 100644 --- a/llvm/test/CodeGen/Hexagon/vararg.ll +++ b/llvm/test/CodeGen/Hexagon/vararg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/Hexagon/vararg_align_check.ll b/llvm/test/CodeGen/Hexagon/vararg_align_check.ll index 53782ac93af0..66a8875dcc46 100644 --- a/llvm/test/CodeGen/Hexagon/vararg_align_check.ll +++ b/llvm/test/CodeGen/Hexagon/vararg_align_check.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll b/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll index 73737b8077f8..5eb539084cac 100644 --- a/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll +++ b/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/Hexagon/vararg_named.ll b/llvm/test/CodeGen/Hexagon/vararg_named.ll index cccc37cc447e..df9ceae87fdd 100644 --- a/llvm/test/CodeGen/Hexagon/vararg_named.ll +++ b/llvm/test/CodeGen/Hexagon/vararg_named.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/Hexagon/varargs-memv.ll b/llvm/test/CodeGen/Hexagon/varargs-memv.ll index e62864a715f6..fcec1477429c 100644 --- a/llvm/test/CodeGen/Hexagon/varargs-memv.ll +++ b/llvm/test/CodeGen/Hexagon/varargs-memv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Check that llc does not crash. diff --git a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll index 5da6250f7e67..d9a9740773d4 100644 --- a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll +++ b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This testcase is known to generate an opportunity for creating vcombine ; in HexagonCopyToCombine. diff --git a/llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll b/llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll index e42ac93e58ac..38665b47dcd7 100644 --- a/llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll +++ b/llvm/test/CodeGen/Hexagon/vcombine128_to_req_seq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; Test that we convert 128B vcombine instructions to REG_SEQUENCE instructions. diff --git a/llvm/test/CodeGen/Hexagon/vcombine_subreg.ll b/llvm/test/CodeGen/Hexagon/vcombine_subreg.ll index d3a603027c23..d2acb60175b5 100644 --- a/llvm/test/CodeGen/Hexagon/vcombine_subreg.ll +++ b/llvm/test/CodeGen/Hexagon/vcombine_subreg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/vcombine_to_req_seq.ll b/llvm/test/CodeGen/Hexagon/vcombine_to_req_seq.ll index 9b969d193593..03a4d25e0ce1 100644 --- a/llvm/test/CodeGen/Hexagon/vcombine_to_req_seq.ll +++ b/llvm/test/CodeGen/Hexagon/vcombine_to_req_seq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK-NOT: vcombine define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, i32 %a2, ptr nocapture %a3, i32 %a4, i32 %a5) #0 { diff --git a/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll b/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll index 2e4243340c12..2fba0ce61f46 100644 --- a/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll +++ b/llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll @@ -1,4 +1,4 @@ -; RUN: opt -march=hexagon -hexagon-vc -S < %s | FileCheck %s +; RUN: opt -hexagon-vc -S < %s | FileCheck %s ; Test that the HexagonVectorCombine pass identifies instruction ; pairs whose difference in pointers is zero. This creates a vector diff --git a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll index ab06fb09f662..de0f20840c57 100644 --- a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll +++ b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Thie tests checks a compiler assert. So the test just needs to compile for it to pass diff --git a/llvm/test/CodeGen/Hexagon/vdotprod.ll b/llvm/test/CodeGen/Hexagon/vdotprod.ll index abdd4cbeffc6..dfe49ec9d9b6 100644 --- a/llvm/test/CodeGen/Hexagon/vdotprod.ll +++ b/llvm/test/CodeGen/Hexagon/vdotprod.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we generate a single packet for the vectorized dot product loop. diff --git a/llvm/test/CodeGen/Hexagon/vec-align.ll b/llvm/test/CodeGen/Hexagon/vec-align.ll index 3ee75c799171..022a18526b52 100644 --- a/llvm/test/CodeGen/Hexagon/vec-align.ll +++ b/llvm/test/CodeGen/Hexagon/vec-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon < %s | FileCheck %s +; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s ; Make sure we generate stack alignment. ; CHECK: [[REG1:r[0-9]*]] = and(r29,#-64) diff --git a/llvm/test/CodeGen/Hexagon/vec-call-full1.ll b/llvm/test/CodeGen/Hexagon/vec-call-full1.ll index 24cc97593ad6..6d56d0e365c0 100644 --- a/llvm/test/CodeGen/Hexagon/vec-call-full1.ll +++ b/llvm/test/CodeGen/Hexagon/vec-call-full1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0) ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0) diff --git a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll index c9cd6dda91d2..9cfd7ca4474d 100644 --- a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll +++ b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}} ; CHECK: call puts diff --git a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll index cceb54419034..3e3317666bba 100644 --- a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll +++ b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; ; Check that the stack is aligned according to the outgoing function arguments. ; CHECK: r29 = and(r29,#-64) diff --git a/llvm/test/CodeGen/Hexagon/vecPred2Vec.ll b/llvm/test/CodeGen/Hexagon/vecPred2Vec.ll index 241f96f49e91..b50208e12e16 100644 --- a/llvm/test/CodeGen/Hexagon/vecPred2Vec.ll +++ b/llvm/test/CodeGen/Hexagon/vecPred2Vec.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s ; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}}) ; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}}) ; CHECK: q{{[0-3]}} = and(q{{[0-3]}},q{{[0-3]}}) diff --git a/llvm/test/CodeGen/Hexagon/vect-any_extend.ll b/llvm/test/CodeGen/Hexagon/vect-any_extend.ll index b4b4feb5613e..665f675808e9 100644 --- a/llvm/test/CodeGen/Hexagon/vect-any_extend.ll +++ b/llvm/test/CodeGen/Hexagon/vect-any_extend.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Used to fail with "Cannot select: 0x17300f0: v2i32 = any_extend" diff --git a/llvm/test/CodeGen/Hexagon/vect-dbl-post-inc.ll b/llvm/test/CodeGen/Hexagon/vect-dbl-post-inc.ll index 788dd3fbff8a..79ef74cc79db 100644 --- a/llvm/test/CodeGen/Hexagon/vect-dbl-post-inc.ll +++ b/llvm/test/CodeGen/Hexagon/vect-dbl-post-inc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that we generate a post-increment when using double hvx (128B) ; post-increment operations. diff --git a/llvm/test/CodeGen/Hexagon/vect-downscale.ll b/llvm/test/CodeGen/Hexagon/vect-downscale.ll index 65cd1ef489c1..3f519912c846 100644 --- a/llvm/test/CodeGen/Hexagon/vect-downscale.ll +++ b/llvm/test/CodeGen/Hexagon/vect-downscale.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure we generate a hardware loop and pipeline the inner loop using ; 4 packets, which is equivalent to the hand-coded version. diff --git a/llvm/test/CodeGen/Hexagon/vect-set_cc_v2i32.ll b/llvm/test/CodeGen/Hexagon/vect-set_cc_v2i32.ll index cbb9241b2490..851c1100d165 100644 --- a/llvm/test/CodeGen/Hexagon/vect-set_cc_v2i32.ll +++ b/llvm/test/CodeGen/Hexagon/vect-set_cc_v2i32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vcmp{{.*}} target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/vect-vd0.ll b/llvm/test/CodeGen/Hexagon/vect-vd0.ll index 09174b0d6e9e..744558c59775 100644 --- a/llvm/test/CodeGen/Hexagon/vect-vd0.ll +++ b/llvm/test/CodeGen/Hexagon/vect-vd0.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Verify __builtin_HEXAGON_V6_vd0 maps to vxor ; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}}) diff --git a/llvm/test/CodeGen/Hexagon/vect-zero_extend.ll b/llvm/test/CodeGen/Hexagon/vect-zero_extend.ll index 295cb1e4933f..e4da05771238 100644 --- a/llvm/test/CodeGen/Hexagon/vect-zero_extend.ll +++ b/llvm/test/CodeGen/Hexagon/vect-zero_extend.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend" diff --git a/llvm/test/CodeGen/Hexagon/vect/bit4x8.ll b/llvm/test/CodeGen/Hexagon/vect/bit4x8.ll index 2cc45f37150f..01e59c183413 100644 --- a/llvm/test/CodeGen/Hexagon/vect/bit4x8.ll +++ b/llvm/test/CodeGen/Hexagon/vect/bit4x8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00 ; CHECK: r0 = and(r0,r1) diff --git a/llvm/test/CodeGen/Hexagon/vect/build-vect64.ll b/llvm/test/CodeGen/Hexagon/vect/build-vect64.ll index 8b19e16864ad..a4d7a1beabb5 100644 --- a/llvm/test/CodeGen/Hexagon/vect/build-vect64.ll +++ b/llvm/test/CodeGen/Hexagon/vect/build-vect64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that the value produced is 0x0706050403020100. ; CHECK: r1:0 = CONST64(#506097522914230528) diff --git a/llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll b/llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll index 36c628b3594c..fad707beb78a 100644 --- a/llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure that element no.1 extracted from <2 x i1> translates to extracting ; bit no.4 from the predicate register. diff --git a/llvm/test/CodeGen/Hexagon/vect/extract-v4i1.ll b/llvm/test/CodeGen/Hexagon/vect/extract-v4i1.ll index d050cf1b195a..93fec6dafdcf 100644 --- a/llvm/test/CodeGen/Hexagon/vect/extract-v4i1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/extract-v4i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Test that the compiler generates the correct code when sign-extending a ; predicate register when it is converted from one vector predicate type diff --git a/llvm/test/CodeGen/Hexagon/vect/setcc-not.ll b/llvm/test/CodeGen/Hexagon/vect/setcc-not.ll index 486a36ecf8c9..d8ceeb80c33f 100644 --- a/llvm/test/CodeGen/Hexagon/vect/setcc-not.ll +++ b/llvm/test/CodeGen/Hexagon/vect/setcc-not.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00 ; CHECK: [[P00:p[0-9]+]] = vcmpb.eq(r1:0,r3:2) diff --git a/llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll b/llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll index ac8309a74f9f..3f2f838e9cbd 100644 --- a/llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll +++ b/llvm/test/CodeGen/Hexagon/vect/setcc-v2i32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; Check that this testcase doesn't crash. diff --git a/llvm/test/CodeGen/Hexagon/vect/setcc-v32.ll b/llvm/test/CodeGen/Hexagon/vect/setcc-v32.ll index 9baf9241e3f2..c79cd53148ad 100644 --- a/llvm/test/CodeGen/Hexagon/vect/setcc-v32.ll +++ b/llvm/test/CodeGen/Hexagon/vect/setcc-v32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00 ; CHECK: [[L00:r[0-9:]+]] = vsxtbh(r0) diff --git a/llvm/test/CodeGen/Hexagon/vect/shuff-32.ll b/llvm/test/CodeGen/Hexagon/vect/shuff-32.ll index 8c59d7a2ba08..7ee335d274e6 100644 --- a/llvm/test/CodeGen/Hexagon/vect/shuff-32.ll +++ b/llvm/test/CodeGen/Hexagon/vect/shuff-32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK: r0 = swiz(r0) diff --git a/llvm/test/CodeGen/Hexagon/vect/shuff-64.ll b/llvm/test/CodeGen/Hexagon/vect/shuff-64.ll index b8bc99038b3e..198dc46228b6 100644 --- a/llvm/test/CodeGen/Hexagon/vect/shuff-64.ll +++ b/llvm/test/CodeGen/Hexagon/vect/shuff-64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_00: ; CHECK-DAG: r[[REG00:[0-9]+]] = swiz(r0) diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-anyextend.ll b/llvm/test/CodeGen/Hexagon/vect/vect-anyextend.ll index cb23e5595a90..2136f83eb430 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-anyextend.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-anyextend.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Used to fail with "Cannot select: 0x17300f0: v2i32 = any_extend" ; ModuleID = 'bugpoint-reduced-simplified.bc' diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll b/llvm/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll index 6df628421eb5..c6bbee04dccd 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Used to fail with "Invalid APInt Truncate request". ; Used to fail with "Cannot select: 0x596010: v2i32 = sign_extend_inreg". diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll b/llvm/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll index 34537f674e3a..3cefdf681d43 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll index 64465b2c4b8e..cfc0bd043ea6 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Used to fail with: Assertion `VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BITCAST between types of different sizes!"' failed. diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-bitcast.ll b/llvm/test/CodeGen/Hexagon/vect/vect-bitcast.ll index 4806ff351577..7ba7196fd67f 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-bitcast.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Used to fail with "Cannot BITCAST between types of different sizes!" diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll b/llvm/test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll index 719b040e1de7..f2cbf6e81c65 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-bool-basic-compile.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that we can compile these functions. Don't check anything else for now. ; CHECK-LABEL: test_0: diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll b/llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll index 630bada36372..6d5418f1367a 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-bool-isel-crash.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check for a successful compilation. ; CHECK: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll b/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll index 03b61f04d457..5fbc20752f7a 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; This one should generate a combine with two immediates. ; CHECK: combine(#7,#7) @B = common global [400 x i32] zeroinitializer, align 8 diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll b/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll index 391b5c0d8e61..ff41a32921ee 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Make sure we can build the constant vector <1, 2, 3, 4> ; CHECK-DAG: ##B ; CHECK-DAG: ##A diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-cst.ll b/llvm/test/CodeGen/Hexagon/vect/vect-cst.ll index 3deec435b89d..cb243273123a 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-cst.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-cst.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Make sure we can build the constant vector <7, 7, 7, 7> ; CHECK: vaddub @B = common global [400 x i8] zeroinitializer, align 8 diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll b/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll index af2a55ea47d5..a1c09bcf64b4 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1-debug.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -debug-only=isel < %s 2>/dev/null +; RUN: llc -mtriple=hexagon -debug-only=isel < %s 2>/dev/null ; REQUIRES: asserts ; Make sure that this doesn't crash. Debug option enabled a failing assertion diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1.ll index 8bcf1768b882..990367b6dce5 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-extract-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s define i1 @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { entry: diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-extract.ll b/llvm/test/CodeGen/Hexagon/vect/vect-extract.ll index 8deb68dfbcdf..1fb455660567 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-extract.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-extract.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we do not generate extract. ; CHECK-NOT: extractu diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-fma.ll b/llvm/test/CodeGen/Hexagon/vect/vect-fma.ll index d5018ff774be..2fe443dfbc04 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-fma.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-fma.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s ; REQUIRES: asserts ; Used to fail with "SplitVectorResult #0: 0x16cbe60: v4f64 = fma" diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll b/llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll index 8e1c9af57bcf..8bc7c93ed13f 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-illegal-type.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; REQUIRES: asserts ; Used to fail with "Unexpected illegal type!" ; Used to fail with "Cannot select: ch = store x,x,x,<ST4[undef](align=8), trunc to v4i8>" diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-infloop.ll b/llvm/test/CodeGen/Hexagon/vect/vect-infloop.ll index 5c3df3224bbd..ead5dc82f365 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-infloop.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-infloop.ll @@ -1,5 +1,5 @@ ; Extracted from test/CodeGen/Generic/vector-casts.ll: used to loop indefinitely. -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: convert_df2w define void @a(ptr %p, ptr %q) { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll b/llvm/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll index 003fb9f7d50d..d28fa800325e 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Used to fail with an infinite recursion in the insn selection. target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-load-1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-load-1.ll index 34532180f62b..3a87c040e39e 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-load-1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-load-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; ; Used to fail with "Cannot select: v2i32,ch = load 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](align=8), sext from v2i8>" diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll index 161d985622a7..5f34a5a12c82 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 -hexagon-align-loads=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 -hexagon-align-loads=0 < %s | FileCheck %s ; CHECK-LABEL: danny: ; CHECK: r1 = r0 diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-load.ll b/llvm/test/CodeGen/Hexagon/vect/vect-load.ll index cbbfb79166c4..2d44d666afe7 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-load.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Used to fail with "Cannot select: 0x16cf370: v2i16,ch = load" ; ModuleID = 'bugpoint-reduced-simplified.bc' diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll index f1a80115cb61..ef21f8969009 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vmpyh ; CHECK: vtrunewh diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll index 1d439dd37e14..f7bb3eff9379 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: mpyi ; CHECK: mpyi diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll index a50d7f8adc17..0cfd605cfeb0 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vmpyh ; CHECK: vmpyh ; CHECK: vtrunewh diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll index 5ebc33726bbb..1e6f063f20bb 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; CHECK: vmpybu ; CHECK: vtrunehb diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll index aee0437effd7..453664a7c0bf 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; CHECK: vmpybu ; CHECK: vmpybu diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll index 550b0f81d33a..5bcaa10e5f8c 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: r1:0 = r1:0 define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll b/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll index 9081f18b3c27..374e23bf22e5 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK-NOT: r1:0 = combine(r1, r0) define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-shift-imm.ll b/llvm/test/CodeGen/Hexagon/vect/vect-shift-imm.ll index a4d6afa40bce..4501302ce618 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-shift-imm.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-shift-imm.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW -; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW -; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW -; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH -; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH -; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH +; RUN: llc -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW +; RUN: llc -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW +; RUN: llc -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW +; RUN: llc -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH +; RUN: llc -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH +; RUN: llc -mtriple=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH ; ; Make sure that the instructions with immediate operands are generated. ; CHECK-ASLW: vaslw({{.*}},#9) diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll b/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll index 46f73c5e0e81..8b07d607e785 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-shifts.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s define <4 x i8> @f0(<4 x i8> %a0) unnamed_addr #0 { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll b/llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll index 2d194dc4047a..09746b30a4c1 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-shuffle.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr --stats -o - 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -disable-hsdr --stats -o - 2>&1 < %s | FileCheck %s ; Check that store is post-incremented. ; CHECK-NOT: extractu(r{{[0-9]+}},#32, diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-splat.ll b/llvm/test/CodeGen/Hexagon/vect/vect-splat.ll index 54533b5668b2..6b07a7a4e3e6 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-splat.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-splat.ll @@ -1,5 +1,5 @@ ; Extracted from test/CodeGen/Generic/vector.ll: used to loop indefinitely. -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; CHECK: splat_i4 %i4 = type <4 x i32> diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll index 7813466a55f7..b32578e62ba4 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Used to fail with: "Cannot select: 0x3bab680: ch = store <ST4[%lsr.iv522525], trunc to v2i16> ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll b/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll index 7466ee8171d4..4214f13d568f 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-truncate.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Used to fail with "Cannot select: 0x16cb7f0: v2i16 = truncate" ; ModuleID = 'bugpoint-reduced-simplified.bc' diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll index 99487c4f7751..eb54124d636e 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s ; Check that store is post-incremented. ; CHECK: memh(r{{[0-9]+}}++#2) diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll index e646f8efdd5e..1df052d20eba 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vaddub define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vaddb.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vaddb.ll index 459546991903..9f1e5e2dda64 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vaddb.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vaddb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vaddub define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll index 1b43d4fb6cc8..dfb8e31fe6bc 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vaddh define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vaddh.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vaddh.ll index 32bf3cadacdc..ec0f4656d893 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vaddh.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vaddh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vaddh define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vaddw.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vaddw.ll index a8401345ab26..644df7f7a8bc 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vaddw.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vaddw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vaddw define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vaslw.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vaslw.ll index dcd2888d7477..e9d0d641bd53 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vaslw.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vaslw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vaslh target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll index d3f51c5382e4..568d596266b0 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vshifts.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that store is post-incremented. ; CHECK: r{{[0-9]+:[0-9]+}} = vasrw(r{{[0-9]+:[0-9]+}},r{{[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vsplatb.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vsplatb.ll index c4f4149e4a51..51e9594d7bff 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vsplatb.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vsplatb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hcp < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -disable-hcp < %s | FileCheck %s ; Make sure we build the constant vector <7, 7, 7, 7> with a vsplatb. ; CHECK: vsplatb @B = common global [400 x i8] zeroinitializer, align 8 diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vsplath.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vsplath.ll index c3214d2d689b..26a5df1eb44d 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vsplath.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vsplath.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Actually, don't use vsplath. diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll index 8ac76a0bf13c..03113e395b2e 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vsubub define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vsubb.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vsubb.ll index 73cfc74074ad..8c9f0925d1d2 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vsubb.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vsubb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vsubub define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll index c1f87bf090d6..b12f763722c6 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vsubh define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vsubh.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vsubh.ll index cc7e595644d2..2182a9dc6af2 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vsubh.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vsubh.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vsubh define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-vsubw.ll b/llvm/test/CodeGen/Hexagon/vect/vect-vsubw.ll index ba326a33109b..fafd05aa43d4 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-vsubw.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-vsubw.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; CHECK: vsubw define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind { diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll b/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll index 87a7f0eb252f..0f8526a43624 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s ; Check that the parsing succeeded. ; CHECK: r{{[0-9]+:[0-9]+}} = xor(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-zeroextend.ll b/llvm/test/CodeGen/Hexagon/vect/vect-zeroextend.ll index 86f242b9d8e3..5a085f113d3b 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vect-zeroextend.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vect-zeroextend.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend" ; ModuleID = 'bugpoint-reduced-simplified.bc' diff --git a/llvm/test/CodeGen/Hexagon/vect/vsplat-v8i8.ll b/llvm/test/CodeGen/Hexagon/vect/vsplat-v8i8.ll index c5b93f49c2ee..1a15ff3ea612 100644 --- a/llvm/test/CodeGen/Hexagon/vect/vsplat-v8i8.ll +++ b/llvm/test/CodeGen/Hexagon/vect/vsplat-v8i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that this compiles successfully. Used to crash with "cannot select ; v8i8 = vsplat ..." diff --git a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll index dddc4bd953d7..559bb68741e1 100644 --- a/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll +++ b/llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s ; Check that this compiles successfully. diff --git a/llvm/test/CodeGen/Hexagon/vect_setcc.ll b/llvm/test/CodeGen/Hexagon/vect_setcc.ll index b42ddf1c24f1..4e255b9598f1 100644 --- a/llvm/test/CodeGen/Hexagon/vect_setcc.ll +++ b/llvm/test/CodeGen/Hexagon/vect_setcc.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; CHECK: f0: diff --git a/llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll b/llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll index 61171b22f342..28a16c33dd8f 100644 --- a/llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll +++ b/llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; REQUIRES: asserts ; CHECK: f0 diff --git a/llvm/test/CodeGen/Hexagon/vector-align.ll b/llvm/test/CodeGen/Hexagon/vector-align.ll index dbacbababd86..cdcfda1eb3ed 100644 --- a/llvm/test/CodeGen/Hexagon/vector-align.ll +++ b/llvm/test/CodeGen/Hexagon/vector-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that the store to Q6VecPredResult does not get expanded into multiple ; stores. There should be no memd's. This relies on the alignment specified diff --git a/llvm/test/CodeGen/Hexagon/vector-ext-load.ll b/llvm/test/CodeGen/Hexagon/vector-ext-load.ll index 6f2edd81a630..bbe6770e221d 100644 --- a/llvm/test/CodeGen/Hexagon/vector-ext-load.ll +++ b/llvm/test/CodeGen/Hexagon/vector-ext-load.ll @@ -1,6 +1,6 @@ ; A copy of 2012-06-08-APIntCrash.ll with arch explicitly set to hexagon. -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s define void @test1(ptr %ptr) { %1 = load <8 x i32>, ptr %ptr, align 32 diff --git a/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll b/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll index 576b0d3e2dbb..cd7630e33df9 100644 --- a/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll +++ b/llvm/test/CodeGen/Hexagon/vector-sint-to-fp.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -mtriple=hexagon < %s -verify-machineinstrs | FileCheck %s ; Test that code is generated for the vector sint_to_fp node. diff --git a/llvm/test/CodeGen/Hexagon/vector-zext-v4i8.ll b/llvm/test/CodeGen/Hexagon/vector-zext-v4i8.ll index 4d0e6db22c3b..c55d2aa8d988 100644 --- a/llvm/test/CodeGen/Hexagon/vector-zext-v4i8.ll +++ b/llvm/test/CodeGen/Hexagon/vector-zext-v4i8.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s ; Check that when we extract a byte from the result of a mask from predicate ; that the results of the mask all fit in the same word. diff --git a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir index 8205a6c025c1..82e7fcc83f73 100644 --- a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir +++ b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir @@ -1,8 +1,8 @@ # Using a trick to run register-coalescer twice, that way # liveintervals should be preserved while running the machine verifier. # -# RUN: not --crash llc -o - %s -march=hexagon -enable-subreg-liveness=false -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s -# RUN: not --crash llc -o - %s -march=hexagon -enable-subreg-liveness=true -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-SUB %s +# RUN: not --crash llc -o - %s -mtriple=hexagon -enable-subreg-liveness=false -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s +# RUN: not --crash llc -o - %s -mtriple=hexagon -enable-subreg-liveness=true -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-SUB %s --- name: test_pass diff --git a/llvm/test/CodeGen/Hexagon/verify-sink-code.ll b/llvm/test/CodeGen/Hexagon/verify-sink-code.ll index 4ec1ab487343..fa92a13e95f4 100644 --- a/llvm/test/CodeGen/Hexagon/verify-sink-code.ll +++ b/llvm/test/CodeGen/Hexagon/verify-sink-code.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -march=hexagon -verify-machineinstrs < %s +; RUN: llc -O3 -mtriple=hexagon -verify-machineinstrs < %s ; REQUIRES: asserts ; Check for successful compilation. diff --git a/llvm/test/CodeGen/Hexagon/verify-undef.ll b/llvm/test/CodeGen/Hexagon/verify-undef.ll index fb95214cdac1..13d712ec8880 100644 --- a/llvm/test/CodeGen/Hexagon/verify-undef.ll +++ b/llvm/test/CodeGen/Hexagon/verify-undef.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-pipeliner -verify-machineinstrs < %s +; RUN: llc -mtriple=hexagon -enable-pipeliner -verify-machineinstrs < %s ; REQUIRES: asserts ; This test fails in the machine verifier because the verifier thinks the diff --git a/llvm/test/CodeGen/Hexagon/vextract-basic.mir b/llvm/test/CodeGen/Hexagon/vextract-basic.mir index 15391c059b60..9b1fd9da7e71 100644 --- a/llvm/test/CodeGen/Hexagon/vextract-basic.mir +++ b/llvm/test/CodeGen/Hexagon/vextract-basic.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -mattr=+hvx,+hvx-length64b -run-pass hexagon-vextract %s -o - | FileCheck %s +# RUN: llc -mtriple=hexagon -mattr=+hvx,+hvx-length64b -run-pass hexagon-vextract %s -o - | FileCheck %s --- name: fred diff --git a/llvm/test/CodeGen/Hexagon/vgather-opt-addr.ll b/llvm/test/CodeGen/Hexagon/vgather-opt-addr.ll index ae3b7c9b9daf..431d6f78d556 100644 --- a/llvm/test/CodeGen/Hexagon/vgather-opt-addr.ll +++ b/llvm/test/CodeGen/Hexagon/vgather-opt-addr.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -O3 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s --check-prefix=CHECK-AMODE +; RUN: llc -mtriple=hexagon -O3 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s --check-prefix=CHECK-AMODE ; CHECK-NO-AMODE: [[REG1:(r[0-9]+)]] = add({{r[0-9]+}},#0) diff --git a/llvm/test/CodeGen/Hexagon/vgather-packetize.mir b/llvm/test/CodeGen/Hexagon/vgather-packetize.mir index 7e3eb21c446e..a6a76d81fe58 100644 --- a/llvm/test/CodeGen/Hexagon/vgather-packetize.mir +++ b/llvm/test/CodeGen/Hexagon/vgather-packetize.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -mcpu=hexagonv65 -start-before hexagon-packetizer -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -start-before hexagon-packetizer -o - %s | FileCheck %s # Check that the vgather pseudo was expanded and packetized with the # surrounding instructions. diff --git a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll index 5884e20b5d71..5ecf9037ab76 100644 --- a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll +++ b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s ; CHECK: = vmem(r{{[0-9]+}}++#1) target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/vmemu-128.ll b/llvm/test/CodeGen/Hexagon/vmemu-128.ll index 9810332db3fc..d8d13d3d058a 100644 --- a/llvm/test/CodeGen/Hexagon/vmemu-128.ll +++ b/llvm/test/CodeGen/Hexagon/vmemu-128.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O3 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s ; Test that unaligned load is enabled for 128B ; CHECK-NOT: r{{[0-9]+}} = memw diff --git a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll index a71200296d1c..e904e443d638 100644 --- a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll +++ b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -mtriple=hexagon < %s ; Thie tests checks a compiler assert. So the test just needs to compile ; for it to pass diff --git a/llvm/test/CodeGen/Hexagon/vpack_eo.ll b/llvm/test/CodeGen/Hexagon/vpack_eo.ll index a9759f3025e6..3169c547e9cc 100644 --- a/llvm/test/CodeGen/Hexagon/vpack_eo.ll +++ b/llvm/test/CodeGen/Hexagon/vpack_eo.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon < %s | FileCheck %s target triple = "hexagon-unknown--elf" ; CHECK-DAG: vpacke diff --git a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll index e301a9d218cb..86754f993fb6 100644 --- a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll +++ b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s +; RUN: llc -mtriple=hexagon -mattr="+hvxv60,+hvx-length64b" < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/vsplat-ext.ll b/llvm/test/CodeGen/Hexagon/vsplat-ext.ll index b2a2e8d5a539..e79fec70c3a3 100644 --- a/llvm/test/CodeGen/Hexagon/vsplat-ext.ll +++ b/llvm/test/CodeGen/Hexagon/vsplat-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s ; Hexagon's vsplatb/vsplath only consider the lower 8/16 bits of the source ; register. Any extension of the source is not necessary. diff --git a/llvm/test/CodeGen/Hexagon/vsplat-isel.ll b/llvm/test/CodeGen/Hexagon/vsplat-isel.ll index 9c5e3e17c4e8..99aff95c27e1 100644 --- a/llvm/test/CodeGen/Hexagon/vsplat-isel.ll +++ b/llvm/test/CodeGen/Hexagon/vsplat-isel.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s ; CHECK: vsplatb declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0 diff --git a/llvm/test/CodeGen/Hexagon/wcsrtomb.ll b/llvm/test/CodeGen/Hexagon/wcsrtomb.ll index 0fc0741d3cd2..ff9e0760735a 100644 --- a/llvm/test/CodeGen/Hexagon/wcsrtomb.ll +++ b/llvm/test/CodeGen/Hexagon/wcsrtomb.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 < %s +; RUN: llc -mtriple=hexagon -O2 < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/widen-alias.ll b/llvm/test/CodeGen/Hexagon/widen-alias.ll index 4f8492865462..4e766a607407 100644 --- a/llvm/test/CodeGen/Hexagon/widen-alias.ll +++ b/llvm/test/CodeGen/Hexagon/widen-alias.ll @@ -3,7 +3,7 @@ ; though the load/stores alias with instructions that occur later in the block. ; The order of memory operations remains unchanged. -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/widen-not-load.ll b/llvm/test/CodeGen/Hexagon/widen-not-load.ll index 5bf8b57054a9..630ddc57a4c5 100644 --- a/llvm/test/CodeGen/Hexagon/widen-not-load.ll +++ b/llvm/test/CodeGen/Hexagon/widen-not-load.ll @@ -2,7 +2,7 @@ ; REQUIRES: asserts ; REQUIRES: asserts -; RUN: llc -march=hexagon -O2 -debug-only=hexagon-load-store-widening \ +; RUN: llc -mtriple=hexagon -O2 -debug-only=hexagon-load-store-widening \ ; RUN: %s -o 2>&1 - | FileCheck %s ; Loads with positive invalid postinc is not widened diff --git a/llvm/test/CodeGen/Hexagon/widen-volatile.ll b/llvm/test/CodeGen/Hexagon/widen-volatile.ll index 540f517a6c96..f5ab1b1929c0 100644 --- a/llvm/test/CodeGen/Hexagon/widen-volatile.ll +++ b/llvm/test/CodeGen/Hexagon/widen-volatile.ll @@ -1,6 +1,6 @@ ; Check the volatile load/stores are not widened by HexagonLoadStoreWidening pass -; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -verify-machineinstrs < %s | FileCheck %s target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/zextloadi1.ll b/llvm/test/CodeGen/Hexagon/zextloadi1.ll index 2aab42778225..e6722fd9be3a 100644 --- a/llvm/test/CodeGen/Hexagon/zextloadi1.ll +++ b/llvm/test/CodeGen/Hexagon/zextloadi1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -hexagon-cext=0 < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -hexagon-cext=0 < %s | FileCheck %s @i65_l = external global i65 @i65_s = external global i65 |