diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/stack-realign.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/stack-realign.ll | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll index cf827945fb5f..52d9a30ffb8b 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll @@ -45,8 +45,6 @@ define void @needs_align16_stack_align4(i32 %idx) #2 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0x3c0 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffffc00 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v2 @@ -59,6 +57,8 @@ define void @needs_align16_stack_align4(i32 %idx) #2 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_or_b32_e32 v1, 8, v0 ; GCN-NEXT: v_mov_b32_e32 v2, 3 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0x2800 ; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) @@ -84,8 +84,6 @@ define void @needs_align32(i32 %idx) #0 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0x7c0 ; GCN-NEXT: s_and_b32 s33, s33, 0xfffff800 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v2 @@ -98,6 +96,8 @@ define void @needs_align32(i32 %idx) #0 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_or_b32_e32 v1, 8, v0 ; GCN-NEXT: v_mov_b32_e32 v2, 3 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0x3000 ; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GCN-NEXT: s_waitcnt vmcnt(0) @@ -122,10 +122,10 @@ define void @force_realign4(i32 %idx) #1 { ; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xc0 ; GCN-NEXT: s_and_b32 s33, s33, 0xffffff00 -; GCN-NEXT: s_mov_b32 s5, s34 -; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 +; GCN-NEXT: s_mov_b32 s5, s34 +; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_addk_i32 s32, 0xd00 ; GCN-NEXT: v_add_u32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_mov_b32_e32 v1, 3 @@ -174,7 +174,7 @@ define amdgpu_kernel void @kernel_call_align16_from_8() #0 { } ; The call sequence should keep the stack on call aligned to 4 -define amdgpu_kernel void @kernel_call_align16_from_5() { +define amdgpu_kernel void @kernel_call_align16_from_5() #6 { ; GCN-LABEL: kernel_call_align16_from_5: ; GCN: ; %bb.0: ; GCN-NEXT: s_add_i32 s12, s12, s17 @@ -207,7 +207,7 @@ define amdgpu_kernel void @kernel_call_align16_from_5() { ret void } -define amdgpu_kernel void @kernel_call_align4_from_5() { +define amdgpu_kernel void @kernel_call_align4_from_5() #6 { ; GCN-LABEL: kernel_call_align4_from_5: ; GCN: ; %bb.0: ; GCN-NEXT: s_add_i32 s12, s12, s17 @@ -291,9 +291,9 @@ define void @func_call_align1024_bp_gets_vgpr_spill(<32 x i32> %a, i32 %b) #0 { ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:1028 ; 4-byte Folded Spill ; GCN-NEXT: s_mov_b64 exec, s[18:19] ; GCN-NEXT: v_writelane_b32 v40, s16, 2 +; GCN-NEXT: v_mov_b32_e32 v32, 0 ; GCN-NEXT: v_writelane_b32 v40, s34, 3 ; GCN-NEXT: s_mov_b32 s34, s32 -; GCN-NEXT: v_mov_b32_e32 v32, 0 ; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:1024 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s34 @@ -342,8 +342,8 @@ define i32 @needs_align1024_stack_args_used_inside_loop(ptr addrspace(5) nocaptu ; GCN-NEXT: s_mov_b32 s11, s33 ; GCN-NEXT: s_add_i32 s33, s32, 0xffc0 ; GCN-NEXT: s_mov_b32 s14, s34 -; GCN-NEXT: s_and_b32 s33, s33, 0xffff0000 ; GCN-NEXT: s_mov_b32 s34, s32 +; GCN-NEXT: s_and_b32 s33, s33, 0xffff0000 ; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s34 ; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: s_mov_b32 s10, 0 @@ -412,12 +412,12 @@ define void @no_free_scratch_sgpr_for_bp_copy(<32 x i32> %a, i32 %b) #0 { ; GCN-LABEL: no_free_scratch_sgpr_for_bp_copy: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s40, s33 -; GCN-NEXT: s_add_i32 s33, s32, 0x1fc0 -; GCN-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GCN-NEXT: s_mov_b32 s41, s34 ; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s34 offset:4 +; GCN-NEXT: s_mov_b32 s40, s33 +; GCN-NEXT: s_add_i32 s33, s32, 0x1fc0 +; GCN-NEXT: s_and_b32 s33, s33, 0xffffe000 ; GCN-NEXT: s_addk_i32 s32, 0x6000 ; GCN-NEXT: s_mov_b32 s32, s34 ; GCN-NEXT: s_mov_b32 s34, s41 @@ -691,3 +691,4 @@ attributes #2 = { noinline nounwind alignstack=4 } attributes #3 = { noinline nounwind "no-realign-stack" } attributes #4 = { noinline nounwind "frame-pointer"="all"} attributes #5 = { noinline nounwind "amdgpu-waves-per-eu"="6,6" } +attributes #6 = { nounwind } |