diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll | 112 |
1 files changed, 0 insertions, 112 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll index dafd23af9d65..ca508eb40017 100644 --- a/llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll +++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sopc.ll @@ -11,8 +11,6 @@ define amdgpu_vs void @f32_olt(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_olt: @@ -24,8 +22,6 @@ define amdgpu_vs void @f32_olt(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp olt float %a, %b @@ -43,8 +39,6 @@ define amdgpu_vs void @f32_oeq(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_oeq: @@ -56,8 +50,6 @@ define amdgpu_vs void @f32_oeq(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp oeq float %a, %b @@ -75,8 +67,6 @@ define amdgpu_vs void @f32_ole(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_ole: @@ -88,8 +78,6 @@ define amdgpu_vs void @f32_ole(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ole float %a, %b @@ -107,8 +95,6 @@ define amdgpu_vs void @f32_ogt(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_ogt: @@ -120,8 +106,6 @@ define amdgpu_vs void @f32_ogt(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ogt float %a, %b @@ -139,8 +123,6 @@ define amdgpu_vs void @f32_one(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_one: @@ -152,8 +134,6 @@ define amdgpu_vs void @f32_one(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp one float %a, %b @@ -171,8 +151,6 @@ define amdgpu_vs void @f32_oge(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_oge: @@ -184,8 +162,6 @@ define amdgpu_vs void @f32_oge(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp oge float %a, %b @@ -203,8 +179,6 @@ define amdgpu_vs void @f32_ord(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_ord: @@ -216,8 +190,6 @@ define amdgpu_vs void @f32_ord(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ord float %a, %b @@ -235,8 +207,6 @@ define amdgpu_vs void @f32_uno(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_uno: @@ -248,8 +218,6 @@ define amdgpu_vs void @f32_uno(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp uno float %a, %b @@ -267,8 +235,6 @@ define amdgpu_vs void @f32_ult(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_ult: @@ -280,8 +246,6 @@ define amdgpu_vs void @f32_ult(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ult float %a, %b @@ -299,8 +263,6 @@ define amdgpu_vs void @f32_ueq(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_ueq: @@ -312,8 +274,6 @@ define amdgpu_vs void @f32_ueq(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ueq float %a, %b @@ -331,8 +291,6 @@ define amdgpu_vs void @f32_ule(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_ule: @@ -344,8 +302,6 @@ define amdgpu_vs void @f32_ule(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ule float %a, %b @@ -363,8 +319,6 @@ define amdgpu_vs void @f32_ugt(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_ugt: @@ -376,8 +330,6 @@ define amdgpu_vs void @f32_ugt(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ugt float %a, %b @@ -395,8 +347,6 @@ define amdgpu_vs void @f32_une(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_une: @@ -408,8 +358,6 @@ define amdgpu_vs void @f32_une(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp une float %a, %b @@ -427,8 +375,6 @@ define amdgpu_vs void @f32_uge(ptr addrspace(1) inreg %out, float inreg %a, floa ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f32_uge: @@ -440,8 +386,6 @@ define amdgpu_vs void @f32_uge(ptr addrspace(1) inreg %out, float inreg %a, floa ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp uge float %a, %b @@ -459,8 +403,6 @@ define amdgpu_vs void @f16_olt(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_olt: @@ -472,8 +414,6 @@ define amdgpu_vs void @f16_olt(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp olt half %a, %b @@ -491,8 +431,6 @@ define amdgpu_vs void @f16_oeq(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_oeq: @@ -504,8 +442,6 @@ define amdgpu_vs void @f16_oeq(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp oeq half %a, %b @@ -523,8 +459,6 @@ define amdgpu_vs void @f16_ole(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_ole: @@ -536,8 +470,6 @@ define amdgpu_vs void @f16_ole(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ole half %a, %b @@ -555,8 +487,6 @@ define amdgpu_vs void @f16_ogt(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_ogt: @@ -568,8 +498,6 @@ define amdgpu_vs void @f16_ogt(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ogt half %a, %b @@ -587,8 +515,6 @@ define amdgpu_vs void @f16_one(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_one: @@ -600,8 +526,6 @@ define amdgpu_vs void @f16_one(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp one half %a, %b @@ -619,8 +543,6 @@ define amdgpu_vs void @f16_oge(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_oge: @@ -632,8 +554,6 @@ define amdgpu_vs void @f16_oge(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp oge half %a, %b @@ -651,8 +571,6 @@ define amdgpu_vs void @f16_ord(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_ord: @@ -664,8 +582,6 @@ define amdgpu_vs void @f16_ord(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ord half %a, %b @@ -683,8 +599,6 @@ define amdgpu_vs void @f16_uno(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_uno: @@ -696,8 +610,6 @@ define amdgpu_vs void @f16_uno(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp uno half %a, %b @@ -715,8 +627,6 @@ define amdgpu_vs void @f16_ult(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_ult: @@ -728,8 +638,6 @@ define amdgpu_vs void @f16_ult(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ult half %a, %b @@ -747,8 +655,6 @@ define amdgpu_vs void @f16_ueq(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_ueq: @@ -760,8 +666,6 @@ define amdgpu_vs void @f16_ueq(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ueq half %a, %b @@ -779,8 +683,6 @@ define amdgpu_vs void @f16_ule(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_ule: @@ -792,8 +694,6 @@ define amdgpu_vs void @f16_ule(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ule half %a, %b @@ -811,8 +711,6 @@ define amdgpu_vs void @f16_ugt(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_ugt: @@ -824,8 +722,6 @@ define amdgpu_vs void @f16_ugt(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp ugt half %a, %b @@ -843,8 +739,6 @@ define amdgpu_vs void @f16_une(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_une: @@ -856,8 +750,6 @@ define amdgpu_vs void @f16_une(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp une half %a, %b @@ -875,8 +767,6 @@ define amdgpu_vs void @f16_uge(ptr addrspace(1) inreg %out, half inreg %a, half ; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2 ; SDAG-NEXT: global_store_b32 v0, v1, s[0:1] -; SDAG-NEXT: s_nop 0 -; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; SDAG-NEXT: s_endpgm ; ; GISEL-LABEL: f16_uge: @@ -888,8 +778,6 @@ define amdgpu_vs void @f16_uge(ptr addrspace(1) inreg %out, half inreg %a, half ; GISEL-NEXT: s_bfe_i32 s2, s2, 0x10000 ; GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GISEL-NEXT: global_store_b32 v1, v0, s[0:1] -; GISEL-NEXT: s_nop 0 -; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GISEL-NEXT: s_endpgm entry: %0 = fcmp uge half %a, %b |