diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll index db80f5479d36..bd655a88704f 100644 --- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll +++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll @@ -16,7 +16,7 @@ ; so eliminateFrameIndex would not adjust the access to use the ; correct FP offset. -define amdgpu_kernel void @local_stack_offset_uses_sp(ptr addrspace(1) %out) { +define amdgpu_kernel void @local_stack_offset_uses_sp(ptr addrspace(1) %out) #1 { ; MUBUF-LABEL: local_stack_offset_uses_sp: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_add_u32 s0, s0, s17 @@ -103,21 +103,21 @@ entry: ret void } -define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { +define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) #1 { ; MUBUF-LABEL: func_local_stack_offset_uses_sp: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MUBUF-NEXT: s_mov_b32 s5, s33 ; MUBUF-NEXT: s_add_i32 s33, s32, 0x7ffc0 -; MUBUF-NEXT: s_mov_b32 s6, s34 ; MUBUF-NEXT: s_and_b32 s33, s33, 0xfff80000 -; MUBUF-NEXT: s_mov_b32 s34, s32 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x3000, v3 +; MUBUF-NEXT: s_mov_b32 s6, s34 ; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3 ; MUBUF-NEXT: v_mov_b32_e32 v3, 0 ; MUBUF-NEXT: v_mov_b32_e32 v4, 0x2000 ; MUBUF-NEXT: s_mov_b32 s4, 0 +; MUBUF-NEXT: s_mov_b32 s34, s32 ; MUBUF-NEXT: s_add_i32 s32, s32, 0x200000 ; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], s33 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) @@ -145,11 +145,11 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_mov_b32 s32, s34 ; MUBUF-NEXT: s_mov_b32 s34, s6 +; MUBUF-NEXT: s_mov_b32 s33, s5 ; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v4, v6 ; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v7, vcc ; MUBUF-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: s_mov_b32 s33, s5 ; MUBUF-NEXT: s_setpc_b64 s[30:31] ; ; FLATSCR-LABEL: func_local_stack_offset_uses_sp: @@ -157,8 +157,8 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s2, s33 ; FLATSCR-NEXT: s_add_i32 s33, s32, 0x1fff -; FLATSCR-NEXT: s_mov_b32 s3, s34 ; FLATSCR-NEXT: s_and_b32 s33, s33, 0xffffe000 +; FLATSCR-NEXT: s_mov_b32 s3, s34 ; FLATSCR-NEXT: s_mov_b32 s34, s32 ; FLATSCR-NEXT: s_add_i32 s32, s32, 0x8000 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 @@ -186,11 +186,11 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s32, s34 ; FLATSCR-NEXT: s_mov_b32 s34, s3 +; FLATSCR-NEXT: s_mov_b32 s33, s2 ; FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc ; FLATSCR-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; FLATSCR-NEXT: s_waitcnt vmcnt(0) -; FLATSCR-NEXT: s_mov_b32 s33, s2 ; FLATSCR-NEXT: s_setpc_b64 s[30:31] entry: %pin.low = alloca i32, align 8192, addrspace(5) @@ -206,7 +206,7 @@ entry: ret void } -define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out) { +define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out) #1 { ; MUBUF-LABEL: local_stack_offset_uses_sp_flat: ; MUBUF: ; %bb.0: ; %entry ; MUBUF-NEXT: s_add_u32 s0, s0, s17 @@ -347,3 +347,4 @@ entry: declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg) #0 attributes #0 = { argmemonly nounwind willreturn writeonly } +attributes #1 = { nounwind } |