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Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll48
1 files changed, 24 insertions, 24 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
index 57967bc1650f..559b1b171031 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.sat.pk.ll
@@ -16,7 +16,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
@@ -27,7 +27,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s2
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_v:
@@ -38,7 +38,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_v:
@@ -49,7 +49,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -63,7 +63,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
@@ -72,7 +72,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, s8
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_s:
@@ -83,7 +83,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_s:
@@ -94,7 +94,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -108,7 +108,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
@@ -117,7 +117,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v1, 0x64
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_i4_i8_f32_i:
@@ -126,7 +126,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; GISEL-REAL16-NEXT: v_sat_pk4_i4_i8_e32 v0.l, 0x64
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_i4_i8_f32_i:
@@ -135,7 +135,7 @@ define amdgpu_kernel void @sat_pk4_i4_i8_f32_i(ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_sat_pk4_i4_i8_e32 v0, 0x64
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.i4.i8(i32 100) #0
store i16 %cvt, ptr %out, align 2
@@ -151,7 +151,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
@@ -162,7 +162,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s2
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_v:
@@ -173,7 +173,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_v:
@@ -184,7 +184,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_v(i32 %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -198,7 +198,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s8
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
@@ -207,7 +207,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, s8
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_s:
@@ -218,7 +218,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, s2
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_s:
@@ -229,7 +229,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_s(i32 inreg %src, ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, s2
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 %src) #0
store i16 %cvt, ptr %out, align 2
@@ -243,7 +243,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; SDAG-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
-; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; SDAG-REAL16-NEXT: s_endpgm
;
; SDAG-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
@@ -252,7 +252,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, 0
; SDAG-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v1, 0x64
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
-; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: flat_store_b16 v0, v1, s[0:1]
; SDAG-FAKE16-NEXT: s_endpgm
;
; GISEL-REAL16-LABEL: sat_pk4_u4_u8_f32_i:
@@ -261,7 +261,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; GISEL-REAL16-NEXT: v_sat_pk4_u4_u8_e32 v0.l, 0x64
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
-; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-REAL16-NEXT: s_endpgm
;
; GISEL-FAKE16-LABEL: sat_pk4_u4_u8_f32_i:
@@ -270,7 +270,7 @@ define amdgpu_kernel void @sat_pk4_u4_u8_f32_i(ptr %out) #1 {
; GISEL-FAKE16-NEXT: v_sat_pk4_u4_u8_e32 v0, 0x64
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: flat_store_b16 v1, v0, s[0:1]
; GISEL-FAKE16-NEXT: s_endpgm
%cvt = call i16 @llvm.amdgcn.sat.pk4.u4.u8(i32 100) #0
store i16 %cvt, ptr %out, align 2
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:55:12 +0000