diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/global-saddr-store.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/global-saddr-store.ll | 244 |
1 files changed, 0 insertions, 244 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll index 790056b320d8..0b061da575a2 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll @@ -19,8 +19,6 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr(ptr addrspace(1) inreg %s ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i8_zext_vgpr: @@ -28,8 +26,6 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr(ptr addrspace(1) inreg %s ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %voffset = load i32, ptr addrspace(1) %voffset.ptr %zext.offset = zext i32 %voffset to i64 @@ -52,8 +48,6 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_2047(ptr addrspace ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] offset:2047 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047: @@ -61,8 +55,6 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_2047(ptr addrspace ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] offset:2047 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %voffset = load i32, ptr addrspace(1) %voffset.ptr %zext.offset = zext i32 %voffset to i64 @@ -86,8 +78,6 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_neg2048(ptr addrsp ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] offset:-2048 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048: @@ -95,8 +85,6 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_neg2048(ptr addrsp ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] offset:-2048 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %voffset = load i32, ptr addrspace(1) %voffset.ptr %zext.offset = zext i32 %voffset to i64 @@ -143,8 +131,6 @@ define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 ; GFX11-NEXT: v_readfirstlane_b32 s0, v2 ; GFX11-NEXT: v_readfirstlane_b32 s1, v3 ; GFX11-NEXT: global_store_b8 v0, v1, s[0:1] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_uniform_ptr_in_vgprs: @@ -155,8 +141,6 @@ define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset, i8 ; GFX12-NEXT: v_readfirstlane_b32 s0, v2 ; GFX12-NEXT: v_readfirstlane_b32 s1, v3 ; GFX12-NEXT: global_store_b8 v0, v1, s[0:1] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds %zext.offset = zext i32 %voffset to i64 @@ -196,8 +180,6 @@ define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %vo ; GFX11-NEXT: v_readfirstlane_b32 s0, v2 ; GFX11-NEXT: v_readfirstlane_b32 s1, v3 ; GFX11-NEXT: global_store_b8 v0, v1, s[0:1] offset:-120 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_uniform_ptr_in_vgprs_immoffset: @@ -208,8 +190,6 @@ define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs_immoffset(i32 %vo ; GFX12-NEXT: v_readfirstlane_b32 s0, v2 ; GFX12-NEXT: v_readfirstlane_b32 s1, v3 ; GFX12-NEXT: global_store_b8 v0, v1, s[0:1] offset:-120 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %sbase = load ptr addrspace(1), ptr addrspace(3) @ptr.in.lds %zext.offset = zext i32 %voffset to i64 @@ -232,15 +212,11 @@ define amdgpu_ps void @global_store_saddr_i16_zext_vgpr(ptr addrspace(1) inreg % ; GFX11-LABEL: global_store_saddr_i16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -257,15 +233,11 @@ define amdgpu_ps void @global_store_saddr_i16_zext_vgpr_offset_neg128(ptr addrsp ; GFX11-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -283,15 +255,11 @@ define amdgpu_ps void @global_store_saddr_f16_zext_vgpr(ptr addrspace(1) inreg % ; GFX11-LABEL: global_store_saddr_f16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -308,15 +276,11 @@ define amdgpu_ps void @global_store_saddr_f16_zext_vgpr_offset_neg128(ptr addrsp ; GFX11-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -334,15 +298,11 @@ define amdgpu_ps void @global_store_saddr_i32_zext_vgpr(ptr addrspace(1) inreg % ; GFX11-LABEL: global_store_saddr_i32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -359,15 +319,11 @@ define amdgpu_ps void @global_store_saddr_i32_zext_vgpr_offset_neg128(ptr addrsp ; GFX11-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -385,15 +341,11 @@ define amdgpu_ps void @global_store_saddr_f32_zext_vgpr(ptr addrspace(1) inreg % ; GFX11-LABEL: global_store_saddr_f32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -410,15 +362,11 @@ define amdgpu_ps void @global_store_saddr_f32_zext_vgpr_offset_neg128(ptr addrsp ; GFX11-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -436,15 +384,11 @@ define amdgpu_ps void @global_store_saddr_p3_zext_vgpr(ptr addrspace(1) inreg %s ; GFX11-LABEL: global_store_saddr_p3_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p3_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -461,15 +405,11 @@ define amdgpu_ps void @global_store_saddr_p3_zext_vgpr_offset_neg128(ptr addrspa ; GFX11-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -487,15 +427,11 @@ define amdgpu_ps void @global_store_saddr_i64_zext_vgpr(ptr addrspace(1) inreg % ; GFX11-LABEL: global_store_saddr_i64_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i64_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -512,15 +448,11 @@ define amdgpu_ps void @global_store_saddr_i64_zext_vgpr_offset_neg128(ptr addrsp ; GFX11-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -538,15 +470,11 @@ define amdgpu_ps void @global_store_saddr_f64_zext_vgpr(ptr addrspace(1) inreg % ; GFX11-LABEL: global_store_saddr_f64_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f64_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -563,15 +491,11 @@ define amdgpu_ps void @global_store_saddr_f64_zext_vgpr_offset_neg128(ptr addrsp ; GFX11-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -589,15 +513,11 @@ define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v2i32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -614,15 +534,11 @@ define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -640,15 +556,11 @@ define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v2f32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -665,15 +577,11 @@ define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -691,15 +599,11 @@ define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v4i16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -716,15 +620,11 @@ define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -742,15 +642,11 @@ define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v4f16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -767,15 +663,11 @@ define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -793,15 +685,11 @@ define amdgpu_ps void @global_store_saddr_p1_zext_vgpr(ptr addrspace(1) inreg %s ; GFX11-LABEL: global_store_saddr_p1_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p1_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -818,15 +706,11 @@ define amdgpu_ps void @global_store_saddr_p1_zext_vgpr_offset_neg128(ptr addrspa ; GFX11-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -844,15 +728,11 @@ define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v3i32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3i32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -869,15 +749,11 @@ define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -895,15 +771,11 @@ define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v3f32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3f32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -920,15 +792,11 @@ define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -946,15 +814,11 @@ define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v6i16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6i16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -971,15 +835,11 @@ define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -997,15 +857,11 @@ define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v6f16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6f16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1022,15 +878,11 @@ define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1048,15 +900,11 @@ define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v4i32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1073,15 +921,11 @@ define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1099,15 +943,11 @@ define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v4f32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1124,15 +964,11 @@ define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1150,15 +986,11 @@ define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v2i64_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i64_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1175,15 +1007,11 @@ define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1201,15 +1029,11 @@ define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v2f64_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f64_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1226,15 +1050,11 @@ define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1252,15 +1072,11 @@ define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v8i16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8i16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1277,15 +1093,11 @@ define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1303,15 +1115,11 @@ define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v8f16_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8f16_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1328,15 +1136,11 @@ define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr addr ; GFX11-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1354,15 +1158,11 @@ define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v2p1_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2p1_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1379,15 +1179,11 @@ define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr addrs ; GFX11-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1405,15 +1201,11 @@ define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr(ptr addrspace(1) inreg ; GFX11-LABEL: global_store_saddr_v4p3_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4p3_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1430,15 +1222,11 @@ define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr addrs ; GFX11-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1460,16 +1248,12 @@ define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr(ptr addrspace(1) ; GFX11-LABEL: atomic_global_store_saddr_i32_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1486,16 +1270,12 @@ define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr_offset_neg128(ptr ; GFX11-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SYS -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1513,16 +1293,12 @@ define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr(ptr addrspace(1) ; GFX11-LABEL: atomic_global_store_saddr_i64_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i64_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] scope:SCOPE_SYS -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1539,16 +1315,12 @@ define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr_offset_neg128(ptr ; GFX11-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_SYS -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1570,15 +1342,11 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr(ptr addrspace(1) i ; GFX11-LABEL: global_store_saddr_i16_d16hi_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1596,15 +1364,11 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr ; GFX11-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1623,15 +1387,11 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr addrsp ; GFX11-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1650,15 +1410,11 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg ; GFX11-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:-128 -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:-128 -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset |