diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll index 8c3d20ffb02f..d588c22a8857 100644 --- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll +++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll @@ -20,7 +20,7 @@ define amdgpu_ps void @main(i32 %0, float %1) { ; ISA: ; %bb.0: ; %start ; ISA-NEXT: v_readfirstlane_b32 s0, v0 ; ISA-NEXT: s_mov_b32 m0, s0 -; ISA-NEXT: s_mov_b32 s10, 0 +; ISA-NEXT: s_mov_b32 s8, 0 ; ISA-NEXT: v_interp_p1_f32_e32 v0, v1, attr0.x ; ISA-NEXT: v_cmp_nlt_f32_e32 vcc, 0, v0 ; ISA-NEXT: s_mov_b64 s[0:1], 0 @@ -30,40 +30,42 @@ define amdgpu_ps void @main(i32 %0, float %1) { ; ISA-NEXT: .LBB0_1: ; %Flow1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; ISA-NEXT: s_or_b64 exec, exec, s[4:5] -; ISA-NEXT: s_mov_b64 s[8:9], 0 ; ISA-NEXT: s_mov_b64 s[4:5], s[6:7] +; ISA-NEXT: s_mov_b64 s[6:7], 0 ; ISA-NEXT: .LBB0_2: ; %Flow ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 -; ISA-NEXT: s_and_b64 s[6:7], exec, s[4:5] -; ISA-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1] +; ISA-NEXT: s_and_b64 s[10:11], exec, s[4:5] +; ISA-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] ; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec -; ISA-NEXT: s_and_b64 s[6:7], s[8:9], exec +; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec ; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1] -; ISA-NEXT: s_cbranch_execz .LBB0_6 +; ISA-NEXT: s_cbranch_execz .LBB0_7 ; ISA-NEXT: .LBB0_3: ; %loop ; ISA-NEXT: ; =>This Inner Loop Header: Depth=1 ; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec +; ISA-NEXT: s_cmp_lt_u32 s8, 32 ; ISA-NEXT: s_mov_b64 s[6:7], -1 -; ISA-NEXT: s_cmp_lt_u32 s10, 32 -; ISA-NEXT: s_mov_b64 s[8:9], -1 -; ISA-NEXT: s_cbranch_scc0 .LBB0_2 +; ISA-NEXT: s_cbranch_scc0 .LBB0_6 ; ISA-NEXT: ; %bb.4: ; %endif1 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 ; ISA-NEXT: s_and_saveexec_b64 s[4:5], vcc ; ISA-NEXT: s_cbranch_execz .LBB0_1 ; ISA-NEXT: ; %bb.5: ; %endif2 ; ISA-NEXT: ; in Loop: Header=BB0_3 Depth=1 -; ISA-NEXT: s_add_i32 s10, s10, 1 +; ISA-NEXT: s_add_i32 s8, s8, 1 ; ISA-NEXT: s_xor_b64 s[6:7], exec, -1 ; ISA-NEXT: s_branch .LBB0_1 -; ISA-NEXT: .LBB0_6: ; %Flow2 +; ISA-NEXT: .LBB0_6: ; in Loop: Header=BB0_3 Depth=1 +; ISA-NEXT: ; implicit-def: $sgpr8 +; ISA-NEXT: s_branch .LBB0_2 +; ISA-NEXT: .LBB0_7: ; %Flow2 ; ISA-NEXT: s_or_b64 exec, exec, s[0:1] ; ISA-NEXT: v_mov_b32_e32 v1, 0 ; ISA-NEXT: s_and_saveexec_b64 s[0:1], s[2:3] -; ISA-NEXT: ; %bb.7: ; %if1 +; ISA-NEXT: ; %bb.8: ; %if1 ; ISA-NEXT: v_sqrt_f32_e32 v1, v0 -; ISA-NEXT: ; %bb.8: ; %endloop +; ISA-NEXT: ; %bb.9: ; %endloop ; ISA-NEXT: s_or_b64 exec, exec, s[0:1] ; ISA-NEXT: exp mrt0 v1, v1, v1, v1 done vm ; ISA-NEXT: s_endpgm |